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706 lines
20 KiB
C
706 lines
20 KiB
C
/*
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This file is part of the FreeRTOS.org distribution.
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FreeRTOS.org is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License (version 2) as published
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by the Free Software Foundation and modified by the FreeRTOS exception.
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FreeRTOS.org is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along
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with FreeRTOS.org; if not, write to the Free Software Foundation, Inc., 59
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Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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A special exception to the GPL is included to allow you to distribute a
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combined work that includes FreeRTOS.org without being obliged to provide
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the source code for any proprietary components. See the licensing section
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of http://www.FreeRTOS.org for full details.
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***************************************************************************
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* *
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* Get the FreeRTOS eBook! See http://www.FreeRTOS.org/Documentation *
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* *
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* This is a concise, step by step, 'hands on' guide that describes both *
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* general multitasking concepts and FreeRTOS specifics. It presents and *
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* explains numerous examples that are written using the FreeRTOS API. *
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* Full source code for all the examples is provided in an accompanying *
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* .zip file. *
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* *
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***************************************************************************
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1 tab == 4 spaces!
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Please ensure to read the configuration and relevant port sections of the
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online documentation.
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***************************************************************************
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* *
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* Having a problem? Start by reading the FAQ "My application does *
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* not run, what could be wrong? *
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* *
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* http://www.FreeRTOS.org/FAQHelp.html *
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* *
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***************************************************************************
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http://www.FreeRTOS.org - Documentation, training, latest information,
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license and contact details.
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http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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including FreeRTOS+Trace - an indispensable productivity tool.
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Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
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the code with commercial support, indemnification, and middleware, under
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the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
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provide a safety engineered and independently SIL3 certified version under
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the SafeRTOS brand: http://www.SafeRTOS.com.
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*/
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/* Kernel includes. */
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#include "FreeRTOS.h"
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#include "semphr.h"
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#include "task.h"
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/* Demo includes. */
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#include "FEC.h"
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#include "fecbd.h"
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#include "mii.h"
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#include "eth_phy.h"
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#include "eth.h"
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/* uIP includes. */
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#include "uip.h"
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#include "uip_arp.h"
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/*-----------------------------------------------------------*/
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/* FEC hardware specifics. */
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#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<0x1)
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#define MCF_FEC_RDAR_R_DES_ACTIVE ( 0x1000000 )
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#define MCF_FEC_TDAR_X_DES_ACTIVE ( 0x1000000 )
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/* PHY hardware specifics. */
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#define PHY_STATUS ( 16 )
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#define PHY_DUPLEX_STATUS ( 4 )
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/* Delay between polling the PHY to see if a link has been established. */
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#define fecLINK_DELAY ( 500 / portTICK_RATE_MS )
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/* Very short delay to use when waiting for the Tx to finish with a buffer if
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we run out of Rx buffers. */
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#define fecMINIMAL_DELAY ( 3 / portTICK_RATE_MS )
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/* Don't block to wait for a buffer more than this many times. */
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#define uipBUFFER_WAIT_ATTEMPTS ( 30 )
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/* The Tx re-uses the Rx buffers and only has one descriptor. */
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#define fecNUM_TX_DESCRIPTORS ( 1 )
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/* The total number of buffers available, which should be greater than the
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number of Rx descriptors. */
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#define fecNUM_BUFFERS ( configNUM_FEC_RX_DESCRIPTORS + 2 )
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/*-----------------------------------------------------------*/
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/*
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* Return an unused buffer to the pool of free buffers.
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*/
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static void prvReturnBuffer( unsigned char *pucBuffer );
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/*
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* Find and return the next buffer that is not in use by anything else.
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*/
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static unsigned char *prvGetFreeBuffer( void );
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/*-----------------------------------------------------------*/
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/* The semaphore used to wake the uIP task when data arrives. */
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xSemaphoreHandle xFECSemaphore = NULL;
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/* The buffer used by the uIP stack. In this case the pointer is used to
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point to one of the Rx buffers to avoid having to copy the Rx buffer into
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the uIP buffer. */
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unsigned char *uip_buf;
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/* The DMA descriptors. These are char arrays to allow us to align them
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correctly. */
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static unsigned char xFECTxDescriptors_unaligned[ ( fecNUM_TX_DESCRIPTORS * sizeof( FECBD ) ) + 16 ];
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static unsigned char xFECRxDescriptors_unaligned[ ( configNUM_FEC_RX_DESCRIPTORS * sizeof( FECBD ) ) + 16 ];
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static FECBD *pxFECTxDescriptor;
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static FECBD *xFECRxDescriptors;
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/* The DMA buffer. This is a char arrays to allow it to be aligned correctly. */
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static unsigned char ucFECRxBuffers[ ( fecNUM_BUFFERS * configFEC_BUFFER_SIZE ) + 16 ];
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/* Index to the next descriptor to be inspected for received data. */
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static unsigned long ulNextRxDescriptor = 0;
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/* Contains the start address of each Rx buffer, after it has been correctly
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aligned. */
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static unsigned char *pucAlignedBufferStartAddresses[ fecNUM_BUFFERS ] = { 0 };
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/* Each ucBufferInUse index corresponds to a position in the same index in the
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pucAlignedBufferStartAddresses array. If the index contains a 1 then the
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buffer within pucAlignedBufferStartAddresses is in use, if it contains a 0 then
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the buffer is free. */
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static unsigned char ucBufferInUse[ fecNUM_BUFFERS ] = { 0 };
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/*-----------------------------------------------------------*/
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/********************************************************************/
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/*
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* Write a value to a PHY's MII register.
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*
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* Parameters:
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* ch FEC channel
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* phy_addr Address of the PHY.
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* reg_addr Address of the register in the PHY.
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* data Data to be written to the PHY register.
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*
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* Return Values:
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* 0 on failure
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* 1 on success.
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*
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* Please refer to your PHY manual for registers and their meanings.
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* mii_write() polls for the FEC's MII interrupt event and clears it.
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* If after a suitable amount of time the event isn't triggered, a
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* value of 0 is returned.
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*/
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static int fec_mii_write( int phy_addr, int reg_addr, int data )
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{
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int timeout;
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unsigned long eimr;
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/* Clear the MII interrupt bit */
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EIR = EIR_MII;
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/* Mask the MII interrupt */
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eimr = EIMR;
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EIMR &= ~EIMR_MII;
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/* Write to the MII Management Frame Register to kick-off the MII write */
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MMFR = ( unsigned long ) ( FEC_MMFR_ST_01 | FEC_MMFR_OP_WRITE | FEC_MMFR_PA(phy_addr) | FEC_MMFR_RA(reg_addr) | FEC_MMFR_TA_10 | FEC_MMFR_DATA( data ) );
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/* Poll for the MII interrupt (interrupt should be masked) */
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for (timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++)
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{
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if( EIR & EIR_MII)
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{
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break;
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}
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}
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if( timeout == FEC_MII_TIMEOUT )
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{
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return 0;
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}
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/* Clear the MII interrupt bit */
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EIR = EIR_MII;
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/* Restore the EIMR */
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EIMR = eimr;
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return 1;
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}
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/********************************************************************/
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/*
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* Read a value from a PHY's MII register.
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*
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* Parameters:
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* ch FEC channel
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* phy_addr Address of the PHY.
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* reg_addr Address of the register in the PHY.
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* data Pointer to storage for the Data to be read
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* from the PHY register (passed by reference)
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*
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* Return Values:
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* 0 on failure
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* 1 on success.
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*
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* Please refer to your PHY manual for registers and their meanings.
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* mii_read() polls for the FEC's MII interrupt event and clears it.
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* If after a suitable amount of time the event isn't triggered, a
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* value of 0 is returned.
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*/
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static int fec_mii_read( int phy_addr, int reg_addr, unsigned short* data )
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{
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int timeout;
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unsigned long eimr;
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/* Clear the MII interrupt bit */
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EIR = 0xffffffff;
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/* Mask the MII interrupt */
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eimr = EIMR;
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EIMR &= ~EIMR_MII;
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/* Write to the MII Management Frame Register to kick-off the MII read */
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MMFR = ( unsigned long ) ( FEC_MMFR_ST_01 | FEC_MMFR_OP_READ | FEC_MMFR_PA(phy_addr) | FEC_MMFR_RA(reg_addr) | FEC_MMFR_TA_10 );
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/* Poll for the MII interrupt (interrupt should be masked) */
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for (timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++)
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{
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if (EIR)
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{
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break;
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}
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}
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if(timeout == FEC_MII_TIMEOUT)
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{
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return 0;
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}
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/* Clear the MII interrupt bit */
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EIR = EIR_MII;
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/* Restore the EIMR */
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EIMR = eimr;
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*data = (unsigned short)(MMFR & 0x0000FFFF);
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return 1;
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}
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/********************************************************************/
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/*
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* Generate the hash table settings for the given address
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*
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* Parameters:
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* addr 48-bit (6 byte) Address to generate the hash for
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*
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* Return Value:
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* The 6 most significant bits of the 32-bit CRC result
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*/
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static unsigned char fec_hash_address( const unsigned char* addr )
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{
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unsigned long crc;
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unsigned char byte;
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int i, j;
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crc = 0xFFFFFFFF;
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for(i=0; i<6; ++i)
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{
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byte = addr[i];
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for(j=0; j<8; ++j)
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{
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if((byte & 0x01)^(crc & 0x01))
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{
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crc >>= 1;
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crc = crc ^ 0xEDB88320;
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}
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else
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{
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crc >>= 1;
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}
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byte >>= 1;
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}
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}
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return (unsigned char)(crc >> 26);
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}
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/********************************************************************/
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/*
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* Set the Physical (Hardware) Address and the Individual Address
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* Hash in the selected FEC
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*
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* Parameters:
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* ch FEC channel
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* pa Physical (Hardware) Address for the selected FEC
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*/
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static void fec_set_address( const unsigned char *pa )
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{
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unsigned char crc;
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/*
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* Set the Physical Address
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*/
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PALR = (unsigned long)((pa[0]<<24) | (pa[1]<<16) | (pa[2]<<8) | pa[3]);
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PAUR = (unsigned long)((pa[4]<<24) | (pa[5]<<16));
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/*
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* Calculate and set the hash for given Physical Address
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* in the Individual Address Hash registers
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*/
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crc = fec_hash_address(pa);
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if(crc >= 32)
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{
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IAUR |= (unsigned long)(1 << (crc - 32));
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}
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else
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{
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IALR |= (unsigned long)(1 << crc);
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}
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}
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/*-----------------------------------------------------------*/
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static void prvInitialiseFECBuffers( void )
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{
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unsigned portBASE_TYPE ux;
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unsigned char *pcBufPointer;
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/* Set the pointer to a correctly aligned address. */
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pcBufPointer = &( xFECTxDescriptors_unaligned[ 0 ] );
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while( ( ( unsigned long ) pcBufPointer & 0x0fUL ) != 0 )
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{
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pcBufPointer++;
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}
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pxFECTxDescriptor = ( FECBD * ) pcBufPointer;
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/* Likewise the pointer to the Rx descriptor. */
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pcBufPointer = &( xFECRxDescriptors_unaligned[ 0 ] );
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while( ( ( unsigned long ) pcBufPointer & 0x0fUL ) != 0 )
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{
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pcBufPointer++;
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}
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xFECRxDescriptors = ( FECBD * ) pcBufPointer;
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/* There is no Tx buffer as the Rx buffer is reused. */
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pxFECTxDescriptor->length = 0;
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pxFECTxDescriptor->status = 0;
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/* Align the Rx buffers. */
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pcBufPointer = &( ucFECRxBuffers[ 0 ] );
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while( ( ( unsigned long ) pcBufPointer & 0x0fUL ) != 0 )
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{
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pcBufPointer++;
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}
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/* Then fill in the Rx descriptors. */
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for( ux = 0; ux < configNUM_FEC_RX_DESCRIPTORS; ux++ )
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{
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xFECRxDescriptors[ ux ].status = RX_BD_E;
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xFECRxDescriptors[ ux ].length = configFEC_BUFFER_SIZE;
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xFECRxDescriptors[ ux ].data = pcBufPointer;
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/* Note the start address of the buffer now that it is correctly
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aligned. */
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pucAlignedBufferStartAddresses[ ux ] = pcBufPointer;
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/* The buffer is in use by the descriptor. */
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ucBufferInUse[ ux ] = pdTRUE;
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pcBufPointer += configFEC_BUFFER_SIZE;
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}
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/* Note the start address of the last buffer as one more buffer is
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allocated than there are Rx descriptors. */
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pucAlignedBufferStartAddresses[ ux ] = pcBufPointer;
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/* Set uip_buf to point to the last buffer. */
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uip_buf = pcBufPointer;
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ucBufferInUse[ ux ] = pdTRUE;
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/* Set the wrap bit in the last descriptors to form a ring. */
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xFECRxDescriptors[ configNUM_FEC_RX_DESCRIPTORS - 1 ].status |= RX_BD_W;
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/* We start with descriptor 0. */
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ulNextRxDescriptor = 0;
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}
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/*-----------------------------------------------------------*/
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void vInitFEC( void )
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{
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unsigned short usData;
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struct uip_eth_addr xAddr;
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const unsigned char ucMACAddress[6] =
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{
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configMAC_0, configMAC_1,configMAC_2,configMAC_3,configMAC_4,configMAC_5
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};
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prvInitialiseFECBuffers();
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/* Create the semaphore used to wake the uIP task when data arrives. */
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vSemaphoreCreateBinary( xFECSemaphore );
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/* Set the MAC address within the stack. */
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for( usData = 0; usData < 6; usData++ )
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{
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xAddr.addr[ usData ] = ucMACAddress[ usData ];
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}
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uip_setethaddr( xAddr );
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/* Set the Reset bit and clear the Enable bit */
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ECR_RESET = 1;
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/* Enable the clock. */
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SCGC4 |= SCGC4_FEC_MASK;
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/* Wait at least 8 clock cycles */
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for( usData = 0; usData < 10; usData++ )
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{
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asm( "NOP" );
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}
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/* Set MII speed to 2.5MHz. */
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MSCR = MCF_FEC_MSCR_MII_SPEED( ( ( configCPU_CLOCK_HZ / 1000000 ) / 5 ) + 1 );
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/*
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* Make sure the external interface signals are enabled
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*/
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PTCPF2_C0 = 1;
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PTCPF2_C1 = 1;
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PTCPF2_C2 = 1;
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PTAPF1 = 0x55;
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PTAPF2 = 0x55;
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PTBPF1 = 0x55;
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PTBPF2 = 0x55;
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/* Set all pins to full drive with no filter. */
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PTADS = 0x06;
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PTAIFE = 0x06;
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PTBDS = 0xf4;
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PTBIFE = 0xf4;
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PTCDS = 0;
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PTCIFE = 0;
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/* Can we talk to the PHY? */
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do
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{
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vTaskDelay( fecLINK_DELAY );
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usData = 0xffff;
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fec_mii_read( configPHY_ADDRESS, PHY_PHYIDR1, &usData );
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} while( usData == 0xffff );
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/* Start auto negotiate. */
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fec_mii_write( configPHY_ADDRESS, PHY_BMCR, ( PHY_BMCR_AN_RESTART | PHY_BMCR_AN_ENABLE ) );
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/* Wait for auto negotiate to complete. */
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do
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{
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vTaskDelay( fecLINK_DELAY );
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fec_mii_read( configPHY_ADDRESS, PHY_BMSR, &usData );
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} while( !( usData & PHY_BMSR_AN_COMPLETE ) );
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/* When we get here we have a link - find out what has been negotiated. */
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usData = 0;
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fec_mii_read( configPHY_ADDRESS, PHY_STATUS, &usData );
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/* Setup half or full duplex. */
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if( usData & PHY_DUPLEX_STATUS )
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{
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RCR &= (unsigned long)~RCR_DRT;
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TCR |= TCR_FDEN;
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}
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else
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{
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RCR |= RCR_DRT;
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TCR &= (unsigned long)~TCR_FDEN;
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}
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/* Clear the Individual and Group Address Hash registers */
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IALR = 0;
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IAUR = 0;
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GALR = 0;
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GAUR = 0;
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/* Set the Physical Address for the selected FEC */
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fec_set_address( ucMACAddress );
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/* Set Rx Buffer Size */
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EMRBR = (unsigned short) configFEC_BUFFER_SIZE;
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/* Point to the start of the circular Rx buffer descriptor queue */
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ERDSR = ( volatile unsigned long ) &( xFECRxDescriptors[ 0 ] );
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/* Point to the start of the circular Tx buffer descriptor queue */
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ETSDR = ( volatile unsigned long ) pxFECTxDescriptor;
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/* Clear all FEC interrupt events */
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EIR = ( unsigned long ) -1;
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/* Various mode/status setup. */
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RCR = 0;
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RCR_MAX_FL = configFEC_BUFFER_SIZE;
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RCR_MII_MODE = 1;
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|
|
#if( configUSE_PROMISCUOUS_MODE == 1 )
|
|
{
|
|
RCR |= RCR_PROM;
|
|
}
|
|
#endif
|
|
|
|
/* Enable interrupts. */
|
|
EIMR = EIR_TXF_MASK | EIMR_RXF_MASK | EIMR_RXB_MASK | EIMR_UN_MASK | EIMR_RL_MASK | EIMR_LC_MASK | EIMR_BABT_MASK | EIMR_BABR_MASK | EIMR_HBERR_MASK;
|
|
|
|
/* Enable the MAC itself. */
|
|
ECR = ECR_ETHER_EN_MASK;
|
|
|
|
/* Indicate that there have been empty receive buffers produced */
|
|
RDAR = MCF_FEC_RDAR_R_DES_ACTIVE;
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
unsigned long ulFECRx( void )
|
|
{
|
|
unsigned long ulLen = 0UL;
|
|
|
|
/* Is a buffer ready? */
|
|
if( ( xFECRxDescriptors[ ulNextRxDescriptor ].status & RX_BD_E ) == 0 )
|
|
{
|
|
/* uip_buf is about to be set to a new buffer, so return the buffer it
|
|
is already pointing to. */
|
|
prvReturnBuffer( uip_buf );
|
|
|
|
/* Obtain the size of the packet and put it into the "len" variable. */
|
|
ulLen = xFECRxDescriptors[ ulNextRxDescriptor ].length;
|
|
uip_buf = xFECRxDescriptors[ ulNextRxDescriptor ].data;
|
|
|
|
/* The buffer that this descriptor was using is now in use by the
|
|
TCP/IP stack, so allocate it a new buffer. */
|
|
xFECRxDescriptors[ ulNextRxDescriptor ].data = prvGetFreeBuffer();
|
|
|
|
/* Doing this here could cause corruption! */
|
|
xFECRxDescriptors[ ulNextRxDescriptor ].status |= RX_BD_E;
|
|
|
|
portENTER_CRITICAL();
|
|
{
|
|
ulNextRxDescriptor++;
|
|
if( ulNextRxDescriptor >= configNUM_FEC_RX_DESCRIPTORS )
|
|
{
|
|
ulNextRxDescriptor = 0;
|
|
}
|
|
}
|
|
portEXIT_CRITICAL();
|
|
|
|
/* Tell the DMA a new buffer is available. */
|
|
RDAR = MCF_FEC_RDAR_R_DES_ACTIVE;
|
|
}
|
|
|
|
return ulLen;
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vFECTx( void )
|
|
{
|
|
/* When we get here the Tx descriptor should show as having completed. */
|
|
while( pxFECTxDescriptor->status & TX_BD_R )
|
|
{
|
|
vTaskDelay( fecMINIMAL_DELAY );
|
|
}
|
|
|
|
portENTER_CRITICAL();
|
|
{
|
|
/* To maintain the zero copy implementation, point the Tx descriptor
|
|
to the data from the Rx buffer. */
|
|
pxFECTxDescriptor->data = uip_buf;
|
|
|
|
/* Setup the buffer descriptor for transmission */
|
|
pxFECTxDescriptor->length = uip_len;
|
|
|
|
/* NB this assumes only one Tx descriptor! */
|
|
pxFECTxDescriptor->status = ( TX_BD_R | TX_BD_L | TX_BD_TC | TX_BD_W );
|
|
}
|
|
portEXIT_CRITICAL();
|
|
|
|
/* Continue the Tx DMA task (in case it was waiting for a new TxBD) */
|
|
TDAR = MCF_FEC_TDAR_X_DES_ACTIVE;
|
|
|
|
/* uip_buf is being used by the Tx descriptor. Allocate a new buffer to
|
|
uip_buf. */
|
|
uip_buf = prvGetFreeBuffer();
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvReturnBuffer( unsigned char *pucBuffer )
|
|
{
|
|
unsigned long ul;
|
|
|
|
/* Mark a buffer as free for use. */
|
|
for( ul = 0; ul < fecNUM_BUFFERS; ul++ )
|
|
{
|
|
if( pucAlignedBufferStartAddresses[ ul ] == pucBuffer )
|
|
{
|
|
ucBufferInUse[ ul ] = pdFALSE;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static unsigned char *prvGetFreeBuffer( void )
|
|
{
|
|
portBASE_TYPE x;
|
|
unsigned char *pucReturn = NULL;
|
|
unsigned long ulAttempts = 0;
|
|
|
|
while( pucReturn == NULL )
|
|
{
|
|
/* Look through the buffers to find one that is not in use by
|
|
anything else. */
|
|
for( x = 0; x < fecNUM_BUFFERS; x++ )
|
|
{
|
|
if( ucBufferInUse[ x ] == pdFALSE )
|
|
{
|
|
ucBufferInUse[ x ] = pdTRUE;
|
|
pucReturn = pucAlignedBufferStartAddresses[ x ];
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Was a buffer found? */
|
|
if( pucReturn == NULL )
|
|
{
|
|
ulAttempts++;
|
|
|
|
if( ulAttempts >= uipBUFFER_WAIT_ATTEMPTS )
|
|
{
|
|
break;
|
|
}
|
|
|
|
/* Wait then look again. */
|
|
vTaskDelay( fecMINIMAL_DELAY );
|
|
}
|
|
}
|
|
|
|
return pucReturn;
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void interrupt 86 vFECISRHandler( void )
|
|
{
|
|
unsigned long ulEvent;
|
|
portBASE_TYPE xHighPriorityTaskWoken = pdFALSE;
|
|
|
|
/* Determine the cause of the interrupt. */
|
|
ulEvent = EIR & EIMR;
|
|
EIR = ulEvent;
|
|
|
|
if( ulEvent & EIR_RXF_MASK )
|
|
{
|
|
/* A packet has been received. Wake the handler task in case it is
|
|
blocked. */
|
|
xSemaphoreGiveFromISR( xFECSemaphore, &xHighPriorityTaskWoken );
|
|
}
|
|
|
|
if( ulEvent & EIR_TXF_MASK )
|
|
{
|
|
/* The Tx has completed. Mark the buffer it was using as free again. */
|
|
prvReturnBuffer( pxFECTxDescriptor->data );
|
|
pxFECTxDescriptor->data = NULL;
|
|
}
|
|
|
|
if (ulEvent & ( EIR_UN_MASK | EIR_RL_MASK | EIR_LC_MASK | EIR_EBERR_MASK | EIR_BABT_MASK | EIR_BABR_MASK | EIR_HBERR_MASK ) )
|
|
{
|
|
/* Sledge hammer error handling. */
|
|
prvInitialiseFECBuffers();
|
|
RDAR = MCF_FEC_RDAR_R_DES_ACTIVE;
|
|
}
|
|
|
|
portEND_SWITCHING_ISR( xHighPriorityTaskWoken );
|
|
}
|