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554 lines
13 KiB
C
554 lines
13 KiB
C
/***********************************************************************/
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/* */
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/* FILE :vecttbl.c */
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/* DATE :Sun, Dec 27, 2009 */
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/* DESCRIPTION :Initialize of Vector Table */
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/* CPU TYPE :Other */
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/* */
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/* This file is generated by Renesas Project Generator (Ver.4.16). */
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/* */
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/***********************************************************************/
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#include "vect.h"
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extern void vPortStartFirstTask( void );
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extern void vPortYieldHandler( void );
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extern void vPortPreemptiveTick( void );
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extern void vEMAC_ISR_Wrapper( void );
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extern void MTU_Match( void );
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#pragma section VECTTBL
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void *RESET_Vectors[] = {
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//;<<VECTOR DATA START (POWER ON RESET)>>
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//;0 Power On Reset PC
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(void*) PowerON_Reset_PC,
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//;<<VECTOR DATA END (POWER ON RESET)>>
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// 1 Power On Reset SP
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__secend("S"),
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//;<<VECTOR DATA START (MANUAL RESET)>>
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//;2 Manual Reset PC
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(void*) Manual_Reset_PC,
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//;<<VECTOR DATA END (MANUAL RESET)>>
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// 3 Manual Reset SP
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__secend("S")
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};
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#pragma section INTTBL
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void *INT_Vectors[] = {
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// 4 Illegal code
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(void*) INT_Illegal_code,
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// 5 Reserved
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(void*) Dummy,
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// 6 Illegal slot
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(void*) INT_Illegal_slot,
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// 7 Reserved
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(void*) Dummy,
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// 8 Reserved
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(void*) Dummy,
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// 9 CPU Address error
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(void*) INT_CPU_Address,
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// 10 DMAC Address error
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(void*) INT_DMAC_Address,
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// 11 NMI
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(void*) INT_NMI,
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// 12 User breakpoint trap
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(void*) INT_User_Break,
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// 13 Reserved
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(void*) Dummy,
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// 14 H-UDI
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(void*) INT_HUDI,
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// 15 Register bank over
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(void*) INT_Bank_Overflow,
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// 16 Register bank under
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(void*) INT_Bank_Underflow,
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// 17 ZERO_DIV
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(void*) INT_Divide_by_Zero,
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// 18 OVER_DIV
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(void*) INT_Divide_Overflow,
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// 19 Reserved
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(void*) Dummy,
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// 20 Reserved
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(void*) Dummy,
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// 21 Reserved
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(void*) Dummy,
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// 22 Reserved
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(void*) Dummy,
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// 23 Reserved
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(void*) Dummy,
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// 24 Reserved
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(void*) Dummy,
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// 25 Reserved
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(void*) Dummy,
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// 26 Reserved
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(void*) Dummy,
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// 27 Reserved
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(void*) Dummy,
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// 28 Reserved
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(void*) Dummy,
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// 29 Reserved
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(void*) Dummy,
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// 30 Reserved
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(void*) Dummy,
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// 31 Reserved
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(void*) Dummy,
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// 32 TRAPA (User Vecter)
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// (void*) INT_TRAPA32,
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(void*) vPortStartFirstTask,
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// 33 TRAPA (User Vecter)
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// (void*) INT_TRAPA33,
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(void*) vPortYieldHandler,
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// 34 TRAPA (User Vecter)
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(void*) INT_TRAPA34,
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// 35 TRAPA (User Vecter)
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(void*) INT_TRAPA35,
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// 36 TRAPA (User Vecter)
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(void*) INT_TRAPA36,
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// 37 TRAPA (User Vecter)
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(void*) INT_TRAPA37,
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// 38 TRAPA (User Vecter)
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(void*) INT_TRAPA38,
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// 39 TRAPA (User Vecter)
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(void*) INT_TRAPA39,
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// 40 TRAPA (User Vecter)
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(void*) INT_TRAPA40,
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// 41 TRAPA (User Vecter)
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(void*) INT_TRAPA41,
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// 42 TRAPA (User Vecter)
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(void*) INT_TRAPA42,
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// 43 TRAPA (User Vecter)
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(void*) INT_TRAPA43,
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// 44 TRAPA (User Vecter)
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(void*) INT_TRAPA44,
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// 45 TRAPA (User Vecter)
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(void*) INT_TRAPA45,
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// 46 TRAPA (User Vecter)
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(void*) INT_TRAPA46,
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// 47 TRAPA (User Vecter)
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(void*) INT_TRAPA47,
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// 48 TRAPA (User Vecter)
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(void*) INT_TRAPA48,
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// 49 TRAPA (User Vecter)
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(void*) INT_TRAPA49,
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// 50 TRAPA (User Vecter)
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(void*) INT_TRAPA50,
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// 51 TRAPA (User Vecter)
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(void*) INT_TRAPA51,
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// 52 TRAPA (User Vecter)
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(void*) INT_TRAPA52,
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// 53 TRAPA (User Vecter)
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(void*) INT_TRAPA53,
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// 54 TRAPA (User Vecter)
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(void*) INT_TRAPA54,
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// 55 TRAPA (User Vecter)
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(void*) INT_TRAPA55,
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// 56 TRAPA (User Vecter)
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(void*) INT_TRAPA56,
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// 57 TRAPA (User Vecter)
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(void*) INT_TRAPA57,
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// 58 TRAPA (User Vecter)
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(void*) INT_TRAPA58,
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// 59 TRAPA (User Vecter)
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(void*) INT_TRAPA59,
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// 60 TRAPA (User Vecter)
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(void*) INT_TRAPA60,
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// 61 TRAPA (User Vecter)
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(void*) INT_TRAPA61,
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// 62 TRAPA (User Vecter)
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(void*) INT_TRAPA62,
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// 63 TRAPA (User Vecter)
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(void*) INT_TRAPA63,
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// 64 Interrupt IRQ0
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(void*) INT_IRQ0,
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// 65 Interrupt IRQ1
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(void*) INT_IRQ1,
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// 66 Interrupt IRQ2
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(void*) INT_IRQ2,
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// 67 Interrupt IRQ3
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(void*) INT_IRQ3,
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// 68 Interrupt IRQ4
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(void*) INT_IRQ4,
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// 69 Interrupt IRQ5
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(void*) INT_IRQ5,
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// 70 Interrupt IRQ6
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(void*) INT_IRQ6,
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// 71 Interrupt IRQ7
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(void*) INT_IRQ7,
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// 72 Reserved
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(void*) Dummy,
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// 73 Reserved
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(void*) Dummy,
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// 74 Reserved
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(void*) Dummy,
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// 75 Reserved
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(void*) Dummy,
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// 76 Reserved
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(void*) Dummy,
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// 77 Reserved
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(void*) Dummy,
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// 78 Reserved
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(void*) Dummy,
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// 79 Reserved
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(void*) Dummy,
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// 80 Interrupt PINT0
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(void*) INT_PINT0,
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// 81 Interrupt PINT1
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(void*) INT_PINT1,
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// 82 Interrupt PINT2
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(void*) INT_PINT2,
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// 83 Interrupt PINT3
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(void*) INT_PINT3,
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// 84 Interrupt PINT4
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(void*) INT_PINT4,
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// 85 Interrupt PINT5
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(void*) INT_PINT5,
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// 86 Interrupt PINT6
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(void*) INT_PINT6,
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// 87 Interrupt PINT7
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(void*) INT_PINT7,
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// 88 Reserved
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(void*) Dummy,
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// 89 Reserved
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(void*) Dummy,
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// 90 Reserved
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(void*) Dummy,
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// 91 ROM FIFE
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(void*) INT_ROM_FIFE,
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// 92 A/D ADI0
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(void*) INT_AD_ADI0,
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// 93 Reserved
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(void*) Dummy,
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// 94 Reserved
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(void*) Dummy,
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// 95 Reserved
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(void*) Dummy,
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// 96 A/D ADI1
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(void*) INT_AD_ADI1,
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// 97 Reserved
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(void*) Dummy,
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// 98 Reserved
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(void*) Dummy,
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// 99 Reserved
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(void*) Dummy,
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// 100 Reserved
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(void*) Dummy,
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// 101 Reserved
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(void*) Dummy,
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// 102 Reserved
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(void*) Dummy,
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// 103 Reserved
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(void*) Dummy,
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// 104 RCANET0 ERS_0
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(void*) INT_RCANET0_ERS_0,
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// 105 RCANET0 OVR_0
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(void*) INT_RCANET0_OVR_0,
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// 106 RCANET0 RM01_0
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(void*) INT_RCANET0_RM01_0,
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// 107 RCANET0 SLE_0
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(void*) INT_RCANET0_SLE_0,
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// 108 DMAC0 DEI0
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(void*) INT_DMAC0_DEI0,
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// 109 DMAC0 HEI0
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(void*) INT_DMAC0_HEI0,
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// 110 Reserved
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(void*) Dummy,
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// 111 Reserved
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(void*) Dummy,
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// 112 DMAC1 DEI1
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(void*) INT_DMAC1_DEI1,
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// 113 DMAC1 HEI1
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(void*) INT_DMAC1_HEI1,
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// 114 Reserved
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(void*) Dummy,
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// 115 Reserved
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(void*) Dummy,
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// 116 DMAC2 DEI2
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(void*) INT_DMAC2_DEI2,
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// 117 DMAC2 HEI2
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(void*) INT_DMAC2_HEI2,
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// 118 Reserved
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(void*) Dummy,
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// 119 Reserved
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(void*) Dummy,
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// 120 DMAC3 DEI3
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(void*) INT_DMAC3_DEI3,
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// 121 DMAC3 HEI3
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(void*) INT_DMAC3_HEI3,
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// 122 Reserved
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(void*) Dummy,
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// 123 Reserved
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(void*) Dummy,
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// 124 DMAC4 DEI4
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(void*) INT_DMAC4_DEI4,
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// 125 DMAC4 HEI4
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(void*) INT_DMAC4_HEI4,
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// 126 Reserved
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(void*) Dummy,
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// 127 Reserved
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(void*) Dummy,
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// 128 DMAC5 DEI5
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(void*) INT_DMAC5_DEI5,
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// 129 DMAC5 HEI5
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(void*) INT_DMAC5_HEI5,
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// 130 Reserved
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(void*) Dummy,
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// 131 Reserved
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(void*) Dummy,
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// 132 DMAC6 DEI6
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(void*) INT_DMAC6_DEI6,
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// 133 DMAC6 HEI6
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(void*) INT_DMAC6_HEI6,
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// 134 Reserved
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(void*) Dummy,
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// 135 Reserved
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(void*) Dummy,
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// 136 DMAC7 DEI7
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(void*) INT_DMAC7_DEI7,
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// 137 DMAC7 HEI7
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(void*) INT_DMAC7_HEI7,
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// 138 Reserved
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(void*) Dummy,
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// 139 Reserved
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(void*) Dummy,
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// 140 CMT CMI0
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// (void*) INT_CMT_CMI0,
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(void*) vPortPreemptiveTick,
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// 141 Reserved
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(void*) Dummy,
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// 142 Reserved
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(void*) Dummy,
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// 143 Reserved
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(void*) Dummy,
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// 144 CMT CMI1
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(void*) INT_CMT_CMI1,
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// 145 Reserved
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(void*) Dummy,
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// 146 Reserved
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(void*) Dummy,
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// 147 Reserved
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(void*) Dummy,
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// 148 BSC CMTI
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(void*) INT_BSC_CMTI,
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// 149 Reserved
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(void*) Dummy,
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// 150 USB EP4FULL
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(void*) INT_USB_EP4FULL,
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// 151 USB EP5EMPTY
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(void*) INT_USB_EP5EMPTY,
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// 152 WDT ITI
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(void*) INT_WDT_ITI,
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// 153 E-DMAC EINT0
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(void*) vEMAC_ISR_Wrapper,
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// 154 USB EP1FULL
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(void*) INT_USB_EP1FULL,
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// 155 USB EP2EMPTY
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(void*) INT_USB_EP2EMPTY,
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// 156 MTU2 MTU0 TGI0A
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// (void*) INT_MTU2_MTU0_TGI0A,
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(void*) MTU_Match,
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// 157 MTU2 MTU0 TGI0B
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(void*) INT_MTU2_MTU0_TGI0B,
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// 158 MTU2 MTU0 TGI0C
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(void*) INT_MTU2_MTU0_TGI0C,
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// 159 MTU2 MTU0 TGI0D
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(void*) INT_MTU2_MTU0_TGI0D,
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// 160 MTU2 MTU0 TGI0V
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(void*) INT_MTU2_MTU0_TGI0V,
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// 161 MTU2 MTU0 TGI0E
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(void*) INT_MTU2_MTU0_TGI0E,
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// 162 MTU2 MTU0 TGI0F
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(void*) INT_MTU2_MTU0_TGI0F,
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// 163 Reserved
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(void*) Dummy,
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// 164 MTU2 MTU1 TGI1A
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(void*) INT_MTU2_MTU1_TGI1A,
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// 165 MTU2 MTU1 TGI1B
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(void*) INT_MTU2_MTU1_TGI1B,
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// 166 Reserved
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(void*) Dummy,
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// 167 Reserved
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(void*) Dummy,
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// 168 MTU2 MTU1 TGI1V
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(void*) INT_MTU2_MTU1_TGI1V,
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// 169 MTU2 MTU1 TGI1U
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(void*) INT_MTU2_MTU1_TGI1U,
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// 170 Reserved
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(void*) Dummy,
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// 171 Reserved
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(void*) Dummy,
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// 172 MTU2 MTU2 TGI2A
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(void*) INT_MTU2_MTU2_TGI2A,
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// 173 MTU2 MTU2 TGI2B
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(void*) INT_MTU2_MTU2_TGI2B,
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// 174 Reserved
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(void*) Dummy,
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// 175 Reserved
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(void*) Dummy,
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// 176 MTU2 MTU2 TGI2V
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(void*) INT_MTU2_MTU2_TGI2V,
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// 177 MTU2 MTU2 TGI2U
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(void*) INT_MTU2_MTU2_TGI2U,
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// 178 Reserved
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(void*) Dummy,
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// 179 Reserved
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(void*) Dummy,
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// 180 MTU2 MTU3 TGI3A
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(void*) INT_MTU2_MTU3_TGI3A,
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// 181 MTU2 MTU3 TGI3B
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(void*) INT_MTU2_MTU3_TGI3B,
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// 182 MTU2 MTU3 TGI3C
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(void*) INT_MTU2_MTU3_TGI3C,
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// 183 MTU2 MTU3 TGI3D
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(void*) INT_MTU2_MTU3_TGI3D,
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// 184 MTU2 MTU3 TGI3V
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(void*) INT_MTU2_MTU3_TGI3V,
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// 185 Reserved
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(void*) Dummy,
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// 186 Reserved
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(void*) Dummy,
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// 187 Reserved
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(void*) Dummy,
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// 188 MTU2 MTU4 TGI4A
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(void*) INT_MTU2_MTU4_TGI4A,
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// 189 MTU2 MTU4 TGI4B
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(void*) INT_MTU2_MTU4_TGI4B,
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// 190 MTU2 MTU4 TGI4C
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(void*) INT_MTU2_MTU4_TGI4C,
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// 191 MTU2 MTU4 TGI4D
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(void*) INT_MTU2_MTU4_TGI4D,
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// 192 MTU2 MTU4 TGI4V
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(void*) INT_MTU2_MTU4_TGI4V,
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// 193 Reserved
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(void*) Dummy,
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// 194 Reserved
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(void*) Dummy,
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// 195 Reserved
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(void*) Dummy,
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// 196 MTU2 MTU5 TGI5U
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(void*) INT_MTU2_MTU5_TGI5U,
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// 197 MTU2 MTU5 TGI5V
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(void*) INT_MTU2_MTU5_TGI5V,
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// 198 MTU2 MTU5 TGI5W
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(void*) INT_MTU2_MTU5_TGI5W,
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// 199 Reserved
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(void*) Dummy,
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// 200 POE2 OEI1
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(void*) INT_POE2_OEI1,
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// 201 POE2 OEI2
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(void*) INT_POE2_OEI2,
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// 202 Reserved
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(void*) Dummy,
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// 203 Reserved
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(void*) Dummy,
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// 204 MTU2S MTU3S TGI3A
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(void*) INT_MTU2S_MTU3S_TGI3A,
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// 205 MTU2S MTU3S TGI3B
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(void*) INT_MTU2S_MTU3S_TGI3B,
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// 206 MTU2S MTU3S TGI3C
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(void*) INT_MTU2S_MTU3S_TGI3C,
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// 207 MTU2S MTU3S TGI3D
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(void*) INT_MTU2S_MTU3S_TGI3D,
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// 208 MTU2S MTU3S TGI3V
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(void*) INT_MTU2S_MTU3S_TGI3V,
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// 209 Reserved
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(void*) Dummy,
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// 210 Reserved
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(void*) Dummy,
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// 211 Reserved
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(void*) Dummy,
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// 212 MTU2S MTU4S TGI4A
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(void*) INT_MTU2S_MTU4S_TGI4A,
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// 213 MTU2S MTU4S TGI4B
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(void*) INT_MTU2S_MTU4S_TGI4B,
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// 214 MTU2S MTU4S TGI4C
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(void*) INT_MTU2S_MTU4S_TGI4C,
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// 215 MTU2S MTU4S TGI4D
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(void*) INT_MTU2S_MTU4S_TGI4D,
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// 216 MTU2S MTU4S TGI4V
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(void*) INT_MTU2S_MTU4S_TGI4V,
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// 217 Reserved
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(void*) Dummy,
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// 218 Reserved
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(void*) Dummy,
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// 219 Reserved
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(void*) Dummy,
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// 220 MTU2S MTU5S TGI5U
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(void*) INT_MTU2S_MTU5S_TGI5U,
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// 221 MTU2S MTU5S TGI5V
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(void*) INT_MTU2S_MTU5S_TGI5V,
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// 222 MTU2S MTU5S TGI5W
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(void*) INT_MTU2S_MTU5S_TGI5W,
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// 223 Reserved
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(void*) Dummy,
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// 224 POE2 OEI3
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(void*) INT_POE2_OEI3,
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// 225 Reserved
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(void*) Dummy,
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// 226 USB USI0
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(void*) INT_USB_USI0,
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// 227 USB USI1
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(void*) INT_USB_USI1,
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// 228 IIC3 STPI
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(void*) INT_IIC3_STPI,
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// 229 IIC3 NAKI
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(void*) INT_IIC3_NAKI,
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// 230 IIC3 RXI
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(void*) INT_IIC3_RXI,
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// 231 IIC3 TXI
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(void*) INT_IIC3_TXI,
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// 232 IIC3 TEI
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(void*) INT_IIC3_TEI,
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// 233 RSPI SPERI
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(void*) INT_RSPI_SPERI,
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// 234 RSPI SPRXI
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(void*) INT_RSPI_SPRXI,
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// 235 RSPI SPTXI
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(void*) INT_RSPI_SPTXI,
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// 236 SCI SCI4 ERI4
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(void*) INT_SCI_SCI4_ERI4,
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// 237 SCI SCI4 RXI4
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(void*) INT_SCI_SCI4_RXI4,
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// 238 SCI SCI4 TXI4
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(void*) INT_SCI_SCI4_TXI4,
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// 239 SCI SCI4 TEI4
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(void*) INT_SCI_SCI4_TEI4,
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// 240 SCI SCI0 ERI0
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(void*) INT_SCI_SCI0_ERI0,
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// 241 SCI SCI0 RXI0
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(void*) INT_SCI_SCI0_RXI0,
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// 242 SCI SCI0 TXI0
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(void*) INT_SCI_SCI0_TXI0,
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// 243 SCI SCI0 TEI0
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(void*) INT_SCI_SCI0_TEI0,
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// 244 SCI SCI1 ERI1
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(void*) INT_SCI_SCI1_ERI1,
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// 245 SCI SCI1 RXI1
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(void*) INT_SCI_SCI1_RXI1,
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// 246 SCI SCI1 TXI1
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(void*) INT_SCI_SCI1_TXI1,
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// 247 SCI SCI1 TEI1
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(void*) INT_SCI_SCI1_TEI1,
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// 248 SCI SCI2 ERI2
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(void*) INT_SCI_SCI2_ERI2,
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// 249 SCI SCI2 RXI2
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(void*) INT_SCI_SCI2_RXI2,
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// 250 SCI SCI2 TXI2
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(void*) INT_SCI_SCI2_TXI2,
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// 251 SCI SCI2 TEI2
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(void*) INT_SCI_SCI2_TEI2,
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// 252 SCIF SCIF3 BRI3
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|
(void*) INT_SCIF_SCIF3_BRI3,
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// 253 SCIF SCIF3 ERI3
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|
(void*) INT_SCIF_SCIF3_ERI3,
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// 254 SCIF SCIF3 RXI3
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|
(void*) INT_SCIF_SCIF3_RXI3,
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// 255 SCIF SCIF3 TXI3
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(void*) INT_SCIF_SCIF3_TXI3,
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|
// xx Reserved
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|
(void*) Dummy
|
|
};
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/* End of File */
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