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244 lines
12 KiB
C
244 lines
12 KiB
C
//*****************************************************************************
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//
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// hw_uart.h - Macros and defines used when accessing the UART hardware
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//
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// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
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//
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// Software License Agreement
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//
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// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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// exclusively on LMI's microcontroller products.
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//
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// The software is owned by LMI and/or its suppliers, and is protected under
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// applicable copyright laws. All rights are reserved. Any use in violation
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// of the foregoing restrictions may subject the user to criminal sanctions
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// under applicable laws, as well as to civil liability for the breach of the
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// terms and conditions of this license.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 1582 of the Stellaris Peripheral Driver Library.
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//
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//*****************************************************************************
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#ifndef __HW_UART_H__
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#define __HW_UART_H__
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//*****************************************************************************
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//
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// UART Register Offsets.
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//
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//*****************************************************************************
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#define UART_O_DR 0x00000000 // Data Register
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#define UART_O_RSR 0x00000004 // Receive Status Register (read)
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#define UART_O_ECR 0x00000004 // Error Clear Register (write)
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#define UART_O_FR 0x00000018 // Flag Register (read only)
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#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg
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#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg
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#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte
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#define UART_O_CTL 0x00000030 // Control Register
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#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg
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#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg
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#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register
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#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register
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#define UART_O_ICR 0x00000044 // Interrupt Clear Register
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#define UART_O_PeriphID4 0x00000FD0 //
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#define UART_O_PeriphID5 0x00000FD4 //
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#define UART_O_PeriphID6 0x00000FD8 //
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#define UART_O_PeriphID7 0x00000FDC //
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#define UART_O_PeriphID0 0x00000FE0 //
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#define UART_O_PeriphID1 0x00000FE4 //
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#define UART_O_PeriphID2 0x00000FE8 //
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#define UART_O_PeriphID3 0x00000FEC //
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#define UART_O_PCellID0 0x00000FF0 //
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#define UART_O_PCellID1 0x00000FF4 //
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#define UART_O_PCellID2 0x00000FF8 //
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#define UART_O_PCellID3 0x00000FFC //
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//*****************************************************************************
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//
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// Data Register bits
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//
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//*****************************************************************************
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#define UART_DR_OE 0x00000800 // Overrun Error
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#define UART_DR_BE 0x00000400 // Break Error
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#define UART_DR_PE 0x00000200 // Parity Error
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#define UART_DR_FE 0x00000100 // Framing Error
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#define UART_DR_DATA_MASK 0x000000FF // UART data
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//*****************************************************************************
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//
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// Receive Status Register bits
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//
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//*****************************************************************************
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#define UART_RSR_OE 0x00000008 // Overrun Error
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#define UART_RSR_BE 0x00000004 // Break Error
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#define UART_RSR_PE 0x00000002 // Parity Error
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#define UART_RSR_FE 0x00000001 // Framing Error
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//*****************************************************************************
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//
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// Flag Register bits
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//
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//*****************************************************************************
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#define UART_FR_TXFE 0x00000080 // TX FIFO Empty
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#define UART_FR_RXFF 0x00000040 // RX FIFO Full
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#define UART_FR_TXFF 0x00000020 // TX FIFO Full
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#define UART_FR_RXFE 0x00000010 // RX FIFO Empty
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#define UART_FR_BUSY 0x00000008 // UART Busy
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//*****************************************************************************
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//
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// Integer baud-rate divisor
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//
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//*****************************************************************************
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#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor
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//*****************************************************************************
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//
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// Fractional baud-rate divisor
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//
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//*****************************************************************************
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#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor
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//*****************************************************************************
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//
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// Line Control Register High bits
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//
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//*****************************************************************************
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#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select
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#define UART_LCR_H_WLEN 0x00000060 // Word length
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#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data
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#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data
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#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data
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#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data
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#define UART_LCR_H_FEN 0x00000010 // Enable FIFO
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#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select
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#define UART_LCR_H_EPS 0x00000004 // Even Parity Select
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#define UART_LCR_H_PEN 0x00000002 // Parity Enable
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#define UART_LCR_H_BRK 0x00000001 // Send Break
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//*****************************************************************************
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//
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// Control Register bits
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//
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//*****************************************************************************
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#define UART_CTL_RXE 0x00000200 // Receive Enable
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#define UART_CTL_TXE 0x00000100 // Transmit Enable
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#define UART_CTL_LBE 0x00000080 // Loopback Enable
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#define UART_CTL_SIRLP 0x00000004 // SIR (IrDA) Low Power Enable
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#define UART_CTL_SIREN 0x00000002 // SIR (IrDA) Enable
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#define UART_CTL_UARTEN 0x00000001 // UART Enable
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//*****************************************************************************
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//
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// Interrupt FIFO Level Select Register bits
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//
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//*****************************************************************************
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#define UART_IFLS_RX_MASK 0x00000038 // RX FIFO level mask
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#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full
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#define UART_IFLS_RX2_8 0x00000008 // 1/4 Full
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#define UART_IFLS_RX4_8 0x00000010 // 1/2 Full
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#define UART_IFLS_RX6_8 0x00000018 // 3/4 Full
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#define UART_IFLS_RX7_8 0x00000020 // 7/8 Full
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#define UART_IFLS_TX_MASK 0x00000007 // TX FIFO level mask
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#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full
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#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full
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#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full
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#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full
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#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full
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//*****************************************************************************
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//
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// Interrupt Mask Set/Clear Register bits
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//
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//*****************************************************************************
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#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask
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#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask
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#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask
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#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask
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#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask
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#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask
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#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask
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//*****************************************************************************
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//
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// Raw Interrupt Status Register
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//
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//*****************************************************************************
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#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status
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#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status
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#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status
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#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status
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#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status
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#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status
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#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status
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//*****************************************************************************
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//
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// Masked Interrupt Status Register
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//
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//*****************************************************************************
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#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status
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#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status
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#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status
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#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status
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#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status
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#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status
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#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status
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//*****************************************************************************
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//
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// Interrupt Clear Register bits
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//
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//*****************************************************************************
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#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear
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#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear
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#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear
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#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear
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#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear
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#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear
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#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear
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#define UART_RSR_ANY (UART_RSR_OE | \
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UART_RSR_BE | \
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UART_RSR_PE | \
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UART_RSR_FE)
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//*****************************************************************************
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//
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// Reset Values for UART Registers.
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//
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//*****************************************************************************
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#define UART_RV_DR 0x00000000
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#define UART_RV_RSR 0x00000000
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#define UART_RV_ECR 0x00000000
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#define UART_RV_FR 0x00000090
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#define UART_RV_IBRD 0x00000000
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#define UART_RV_FBRD 0x00000000
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#define UART_RV_LCR_H 0x00000000
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#define UART_RV_CTL 0x00000300
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#define UART_RV_IFLS 0x00000012
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#define UART_RV_IM 0x00000000
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#define UART_RV_RIS 0x00000000
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#define UART_RV_MIS 0x00000000
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#define UART_RV_ICR 0x00000000
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#define UART_RV_PeriphID4 0x00000000
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#define UART_RV_PeriphID5 0x00000000
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#define UART_RV_PeriphID6 0x00000000
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#define UART_RV_PeriphID7 0x00000000
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#define UART_RV_PeriphID0 0x00000011
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#define UART_RV_PeriphID1 0x00000000
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#define UART_RV_PeriphID2 0x00000018
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#define UART_RV_PeriphID3 0x00000001
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#define UART_RV_PCellID0 0x0000000D
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#define UART_RV_PCellID1 0x000000F0
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#define UART_RV_PCellID2 0x00000005
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#define UART_RV_PCellID3 0x000000B1
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#endif // __HW_UART_H__
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