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415 lines
19 KiB
C
415 lines
19 KiB
C
/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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#ifndef PORTMACRO_H
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#define PORTMACRO_H
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/* *INDENT-OFF* */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* *INDENT-ON* */
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/*-----------------------------------------------------------
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* Port specific definitions.
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*
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* The settings in this file configure FreeRTOS correctly for the
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* given hardware and compiler.
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*
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* These settings should not be altered.
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*-----------------------------------------------------------
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*/
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/* Type definitions. */
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#define portCHAR char
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#define portFLOAT float
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#define portDOUBLE double
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#define portLONG long
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#define portSHORT short
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#define portSTACK_TYPE uint32_t
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#define portBASE_TYPE long
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typedef portSTACK_TYPE StackType_t;
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typedef long BaseType_t;
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typedef unsigned long UBaseType_t;
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#if ( configUSE_16_BIT_TICKS == 1 )
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typedef uint16_t TickType_t;
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#define portMAX_DELAY ( TickType_t ) 0xffff
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#else
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typedef uint32_t TickType_t;
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#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
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/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
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* not need to be guarded with a critical section. */
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#define portTICK_TYPE_IS_ATOMIC 1
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#endif
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/*-----------------------------------------------------------*/
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/* MPU specific constants. */
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#define portUSING_MPU_WRAPPERS 1
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#define portPRIVILEGE_BIT ( 0x80000000UL )
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#define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL )
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#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL )
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#define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL )
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#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL )
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#define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY ( 0x02UL << 24UL )
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#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
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#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
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/* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size
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* Register (RASR). */
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#define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL )
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#define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL )
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/* MPU settings that can be overriden in FreeRTOSConfig.h. */
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#ifndef configTOTAL_MPU_REGIONS
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/* Define to 8 for backward compatibility. */
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#define configTOTAL_MPU_REGIONS ( 8UL )
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#endif
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/*
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* The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the
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* memory type, and where necessary the cacheable and shareable properties
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* of the memory region.
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*
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* The TEX, C, and B bits together indicate the memory type of the region,
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* and:
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* - For Normal memory, the cacheable properties of the region.
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* - For Device memory, whether the region is shareable.
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*
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* For Normal memory regions, the S bit indicates whether the region is
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* shareable. For Strongly-ordered and Device memory, the S bit is ignored.
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*
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* See the following two tables for setting TEX, S, C and B bits for
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* unprivileged flash, privileged flash and privileged RAM regions.
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*
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| TEX | C | B | Memory type | Description or Normal region cacheability | Shareable? |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 000 | 0 | 0 | Strongly-ordered | Strongly ordered | Shareable |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 000 | 0 | 1 | Device | Shared device | Shareable |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 000 | 1 | 0 | Normal | Outer and inner write-through; no write allocate | S bit |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 000 | 1 | 1 | Normal | Outer and inner write-back; no write allocate | S bit |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 001 | 0 | 0 | Normal | Outer and inner Non-cacheable | S bit |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 001 | 0 | 1 | Reserved | Reserved | Reserved |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 001 | 1 | 0 | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED | IMPLEMENTATION DEFINED |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 001 | 1 | 1 | Normal | Outer and inner write-back; write and read allocate | S bit |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 010 | 0 | 0 | Device | Non-shared device | Not shareable |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 010 | 0 | 1 | Reserved | Reserved | Reserved |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 010 | 1 | X | Reserved | Reserved | Reserved |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 011 | X | X | Reserved | Reserved | Reserved |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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| 1BB | A | A | Normal | Cached memory, with AA and BB indicating the inner and | Reserved |
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| | | | | outer cacheability rules that must be exported on the | |
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| | | | | bus. See the table below for the cacheability policy | |
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| | | | | encoding. memory, BB=Outer policy, AA=Inner policy. | |
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+-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
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+-----------------------------------------+----------------------------------------+
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| AA or BB subfield of {TEX,C,B} encoding | Cacheability policy |
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+-----------------------------------------+----------------------------------------+
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| 00 | Non-cacheable |
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+-----------------------------------------+----------------------------------------+
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| 01 | Write-back, write and read allocate |
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+-----------------------------------------+----------------------------------------+
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| 10 | Write-through, no write allocate |
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+-----------------------------------------+----------------------------------------+
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| 11 | Write-back, no write allocate |
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+-----------------------------------------+----------------------------------------+
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*/
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/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for flash
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* region. */
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#ifndef configTEX_S_C_B_FLASH
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/* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
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#define configTEX_S_C_B_FLASH ( 0x07UL )
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#endif
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/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for RAM
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* region. */
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#ifndef configTEX_S_C_B_SRAM
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/* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
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#define configTEX_S_C_B_SRAM ( 0x07UL )
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#endif
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#define portGENERAL_PERIPHERALS_REGION ( configTOTAL_MPU_REGIONS - 5UL )
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#define portSTACK_REGION ( configTOTAL_MPU_REGIONS - 4UL )
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#define portUNPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 3UL )
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#define portPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 2UL )
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#define portPRIVILEGED_RAM_REGION ( configTOTAL_MPU_REGIONS - 1UL )
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#define portFIRST_CONFIGURABLE_REGION ( 0UL )
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#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 6UL )
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#define portNUM_CONFIGURABLE_REGIONS ( configTOTAL_MPU_REGIONS - 5UL )
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#define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus 1 to create space for the stack region. */
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#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )
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typedef struct MPU_REGION_REGISTERS
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{
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uint32_t ulRegionBaseAddress;
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uint32_t ulRegionAttribute;
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} xMPU_REGION_REGISTERS;
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typedef struct MPU_SETTINGS
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{
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xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ];
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} xMPU_SETTINGS;
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/* Architecture specifics. */
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#define portSTACK_GROWTH ( -1 )
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#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
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#define portBYTE_ALIGNMENT 8
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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/* SVC numbers for various services. */
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#define portSVC_START_SCHEDULER 0
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#define portSVC_YIELD 1
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#define portSVC_RAISE_PRIVILEGE 2
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/* Scheduler utilities. */
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#define portYIELD() __asm volatile ( " SVC %0 \n"::"i" ( portSVC_YIELD ) : "memory" )
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#define portYIELD_WITHIN_API() \
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{ \
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/* Set a PendSV to request a context switch. */ \
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portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
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\
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/* Barriers are normally not required but do ensure the code is completely \
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* within the specified behaviour for the architecture. */ \
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__asm volatile ( "dsb" ::: "memory" ); \
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__asm volatile ( "isb" ); \
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}
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#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
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#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
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#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
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#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
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/*-----------------------------------------------------------*/
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/* Critical section management. */
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extern void vPortEnterCritical( void );
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extern void vPortExitCritical( void );
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#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
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#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x )
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#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
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#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 )
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#define portENTER_CRITICAL() vPortEnterCritical()
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#define portEXIT_CRITICAL() vPortExitCritical()
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/*-----------------------------------------------------------*/
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/* Task function macros as described on the FreeRTOS.org WEB site. These are
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* not necessary for to use this port. They are defined so the common demo files
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* (which build with all the ports) will build. */
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#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
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#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
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/*-----------------------------------------------------------*/
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/* Architecture specific optimisations. */
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#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
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#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
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#endif
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#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
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/* Generic helper function. */
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__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
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{
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uint8_t ucReturn;
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__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
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return ucReturn;
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}
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/* Check the configuration. */
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#if ( configMAX_PRIORITIES > 32 )
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#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
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#endif
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/* Store/clear the ready priorities in a bit map. */
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#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
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#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
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/*-----------------------------------------------------------*/
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#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
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#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
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/*-----------------------------------------------------------*/
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#ifdef configASSERT
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void vPortValidateInterruptPriority( void );
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#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
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#endif
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/* portNOP() is not required by this port. */
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#define portNOP()
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#define portINLINE __inline
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#ifndef portFORCE_INLINE
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#define portFORCE_INLINE inline __attribute__( ( always_inline ) )
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#endif
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/*-----------------------------------------------------------*/
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extern BaseType_t xIsPrivileged( void );
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extern void vResetPrivilege( void );
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/**
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* @brief Checks whether or not the processor is privileged.
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*
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* @return 1 if the processor is already privileged, 0 otherwise.
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*/
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#define portIS_PRIVILEGED() xIsPrivileged()
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/**
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* @brief Raise an SVC request to raise privilege.
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*/
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#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
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/**
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* @brief Lowers the privilege level by setting the bit 0 of the CONTROL
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* register.
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*/
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#define portRESET_PRIVILEGE() vResetPrivilege()
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/*-----------------------------------------------------------*/
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portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
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{
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uint32_t ulCurrentInterrupt;
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BaseType_t xReturn;
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/* Obtain the number of the currently executing interrupt. */
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__asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
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if( ulCurrentInterrupt == 0 )
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{
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xReturn = pdFALSE;
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}
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else
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{
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xReturn = pdTRUE;
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}
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return xReturn;
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}
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/*-----------------------------------------------------------*/
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portFORCE_INLINE static void vPortRaiseBASEPRI( void )
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{
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uint32_t ulNewBASEPRI;
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__asm volatile
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(
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" mov %0, %1 \n"
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#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
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" cpsid i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
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#endif
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" msr basepri, %0 \n"
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" isb \n"
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" dsb \n"
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#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
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" cpsie i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
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#endif
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: "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
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);
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}
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/*-----------------------------------------------------------*/
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portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
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{
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uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
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__asm volatile
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(
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" mrs %0, basepri \n"
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" mov %1, %2 \n"
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#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
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" cpsid i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
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#endif
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" msr basepri, %1 \n"
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" isb \n"
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" dsb \n"
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#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
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" cpsie i \n"/* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
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#endif
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: "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
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);
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/* This return will not be reached but is necessary to prevent compiler
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* warnings. */
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return ulOriginalBASEPRI;
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}
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/*-----------------------------------------------------------*/
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portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
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{
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__asm volatile
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(
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" msr basepri, %0 "::"r" ( ulNewMaskValue ) : "memory"
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);
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}
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/*-----------------------------------------------------------*/
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#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
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#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
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#warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
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#define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0
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#endif
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/*-----------------------------------------------------------*/
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/* *INDENT-OFF* */
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#ifdef __cplusplus
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}
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#endif
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/* *INDENT-ON* */
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#endif /* PORTMACRO_H */
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