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698 lines
16 KiB
C
698 lines
16 KiB
C
/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
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* File Name : 75x_map.h
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* Author : MCD Application Team
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* Date First Issued : 03/10/2006
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* Description : This file contains all the peripheral register's definitions
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* and memory mapping.
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********************************************************************************
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* History:
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* 07/17/2006 : V1.0
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* 03/10/2006 : V0.1
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********************************************************************************
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* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
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* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*******************************************************************************/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __75x_MAP_H
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#define __75x_MAP_H
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#ifndef EXT
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#define EXT extern
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#endif /* EXT */
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/* Includes ------------------------------------------------------------------*/
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#include "75x_conf.h"
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#include "75x_type.h"
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/* Exported types ------------------------------------------------------------*/
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/******************************************************************************/
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/* IP registers structures */
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/******************************************************************************/
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/*------------------------ Analog to Digital Converter -----------------------*/
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typedef struct
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{
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vu16 CLR0;
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u16 EMPTY1;
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vu16 CLR1;
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u16 EMPTY2;
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vu16 CLR2;
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u16 EMPTY3;
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vu16 CLR3;
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u16 EMPTY4;
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vu16 CLR4;
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u16 EMPTY5;
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vu16 TRA0;
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u16 EMPTY6;
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vu16 TRA1;
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u16 EMPTY7;
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vu16 TRA2;
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u16 EMPTY8;
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vu16 TRA3;
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u16 EMPTY9;
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vu16 TRB0;
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u16 EMPTY10;
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vu16 TRB1;
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u16 EMPTY11;
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vu16 TRB2;
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u16 EMPTY12;
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vu16 TRB3;
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u16 EMPTY13;
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vu16 DMAR;
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u16 EMPTY14[7];
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vu16 DMAE;
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u16 EMPTY15 ;
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vu16 PBR;
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u16 EMPTY16;
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vu16 IMR;
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u16 EMPTY17;
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vu16 D0;
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u16 EMPTY18;
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vu16 D1;
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u16 EMPTY19;
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vu16 D2;
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u16 EMPTY20;
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vu16 D3;
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u16 EMPTY21;
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vu16 D4;
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u16 EMPTY22;
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vu16 D5;
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u16 EMPTY23;
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vu16 D6;
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u16 EMPTY24;
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vu16 D7;
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u16 EMPTY25;
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vu16 D8;
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u16 EMPTY26;
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vu16 D9;
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u16 EMPTY27;
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vu16 D10;
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u16 EMPTY28;
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vu16 D11;
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u16 EMPTY29;
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vu16 D12;
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u16 EMPTY30;
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vu16 D13;
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u16 EMPTY31;
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vu16 D14;
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u16 EMPTY32;
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vu16 D15;
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u16 EMPTY33;
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} ADC_TypeDef;
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/*------------------------ Controller Area Network ---------------------------*/
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typedef struct
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{
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vu16 CRR;
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u16 EMPTY1;
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vu16 CMR;
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u16 EMPTY2;
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vu16 M1R;
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u16 EMPTY3;
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vu16 M2R;
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u16 EMPTY4;
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vu16 A1R;
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u16 EMPTY5;
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vu16 A2R;
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u16 EMPTY6;
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vu16 MCR;
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u16 EMPTY7;
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vu16 DA1R;
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u16 EMPTY8;
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vu16 DA2R;
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u16 EMPTY9;
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vu16 DB1R;
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u16 EMPTY10;
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vu16 DB2R;
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u16 EMPTY11[27];
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} CAN_MsgObj_TypeDef;
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typedef struct
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{
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vu16 CR;
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u16 EMPTY1;
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vu16 SR;
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u16 EMPTY2;
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vu16 ERR;
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u16 EMPTY3;
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vu16 BTR;
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u16 EMPTY4;
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vu16 IDR;
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u16 EMPTY5;
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vu16 TESTR;
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u16 EMPTY6;
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vu16 BRPR;
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u16 EMPTY7[3];
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CAN_MsgObj_TypeDef sMsgObj[2];
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u16 EMPTY8[16];
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vu16 TXR1R;
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u16 EMPTY9;
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vu16 TXR2R;
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u16 EMPTY10[13];
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vu16 ND1R;
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u16 EMPTY11;
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vu16 ND2R;
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u16 EMPTY12[13];
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vu16 IP1R;
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u16 EMPTY13;
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vu16 IP2R;
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u16 EMPTY14[13];
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vu16 MV1R;
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u16 EMPTY15;
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vu16 MV2R;
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u16 EMPTY16;
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} CAN_TypeDef;
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/*--------------------------- Configuration Register -------------------------*/
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typedef struct
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{
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vu32 GLCONF;
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} CFG_TypeDef;
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/*-------------------------------- DMA Controller ----------------------------*/
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typedef struct
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{
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vu16 SOURCEL;
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u16 EMPTY1;
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vu16 SOURCEH;
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u16 EMPTY2;
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vu16 DESTL;
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u16 EMPTY3;
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vu16 DESTH;
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u16 EMPTY4;
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vu16 MAX;
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u16 EMPTY5;
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vu16 CTRL;
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u16 EMPTY6;
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vuc16 SOCURRH;
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u16 EMPTY7;
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vuc16 SOCURRL;
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u16 EMPTY8;
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vuc16 DECURRH;
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u16 EMPTY9;
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vuc16 DECURRL;
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u16 EMPTY10;
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vuc16 TCNT;
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u16 EMPTY11;
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vu16 LUBUFF;
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u16 EMPTY12;
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} DMA_Stream_TypeDef;
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typedef struct
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{
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vu16 MASK;
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u16 EMPTY4;
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vu16 CLR;
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u16 EMPTY5;
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vuc16 STATUS;
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u16 EMPTY6;
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vu16 LAST;
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u16 EMPTY7;
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} DMA_TypeDef;
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/*----------------------- Enhanced Interrupt Controller ----------------------*/
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typedef struct
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{
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vu32 ICR;
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vuc32 CICR;
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vu32 CIPR;
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u32 EMPTY1;
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vu32 FIER;
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vu32 FIPR;
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vu32 IVR;
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vu32 FIR;
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vu32 IER;
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u32 EMPTY2[7];
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vu32 IPR;
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u32 EMPTY3[7];
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vu32 SIRn[32];
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} EIC_TypeDef;
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/*------------------------- External Interrupt Controller --------------------*/
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typedef struct
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{
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vu32 MR;
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vu32 TSR;
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vu32 SWIR;
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vu32 PR;
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} EXTIT_TypeDef;
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/*-------------------------- General Purpose IO ports ------------------------*/
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typedef struct
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{
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vu32 PC0;
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vu32 PC1;
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vu32 PC2;
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vu32 PD;
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vu32 PM;
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} GPIO_TypeDef;
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typedef struct
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{
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vu32 REMAP0R;
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vu32 REMAP1R;
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} GPIOREMAP_TypeDef;
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/*--------------------------------- I2C interface ----------------------------*/
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typedef struct
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{
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vu8 CR;
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u8 EMPTY1[3];
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vu8 SR1;
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u8 EMPTY2[3];
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vu8 SR2;
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u8 EMPTY3[3];
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vu8 CCR;
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u8 EMPTY4[3];
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vu8 OAR1;
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u8 EMPTY5[3];
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vu8 OAR2;
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u8 EMPTY6[3];
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vu8 DR;
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u8 EMPTY7[3];
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vu8 ECCR;
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u8 EMPTY8[3];
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} I2C_TypeDef;
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/*---------------------------- Power, Reset and Clocks -----------------------*/
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typedef struct
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{
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vu32 CLKCTL;
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vu32 RFSR;
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vu32 PWRCTRL;
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u32 EMPTY1;
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vu32 PCLKEN;
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vu32 PSWRES;
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u32 EMPTY2[2];
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vu32 BKP0;
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vu32 BKP1;
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} MRCC_TypeDef;
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/*-------------------------------- Real Time Clock ---------------------------*/
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typedef struct
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{
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vu16 CRH;
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u16 EMPTY;
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vu16 CRL;
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u16 EMPTY1;
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vu16 PRLH;
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u16 EMPTY2;
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vu16 PRLL;
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u16 EMPTY3;
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vu16 DIVH;
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u16 EMPTY4;
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vu16 DIVL;
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u16 EMPTY5;
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vu16 CNTH;
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u16 EMPTY6;
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vu16 CNTL;
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u16 EMPTY7;
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vu16 ALRH;
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u16 EMPTY8;
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vu16 ALRL;
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u16 EMPTY9;
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} RTC_TypeDef;
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/*---------------------------- Serial Memory Interface -----------------------*/
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typedef struct
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{
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vu32 CR1;
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vu32 CR2;
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vu32 SR;
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vu32 TR;
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vuc32 RR;
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} SMI_TypeDef;
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/*--------------------------------- Timer Base -------------------------------*/
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typedef struct
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{
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vu16 CR;
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u16 EMPTY1;
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vu16 SCR;
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u16 EMPTY2;
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vu16 IMCR;
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u16 EMPTY3[7];
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vu16 RSR;
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u16 EMPTY4;
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vu16 RER;
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u16 EMPTY5;
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vu16 ISR;
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u16 EMPTY6;
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vu16 CNT;
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u16 EMPTY7;
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vu16 PSC;
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u16 EMPTY8[3];
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vu16 ARR;
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u16 EMPTY9[13];
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vu16 ICR1;
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u16 EMPTY10;
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} TB_TypeDef;
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/*------------------------------------ TIM -----------------------------------*/
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typedef struct
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{
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vu16 CR;
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u16 EMPTY1;
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vu16 SCR;
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u16 EMPTY2;
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vu16 IMCR;
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u16 EMPTY3;
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vu16 OMR1;
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u16 EMPTY4[5];
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vu16 RSR;
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u16 EMPTY5;
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vu16 RER;
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u16 EMPTY6;
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vu16 ISR;
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u16 EMPTY7;
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vu16 CNT;
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u16 EMPTY8;
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vu16 PSC;
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u16 EMPTY9[3];
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vu16 ARR;
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u16 EMPTY10;
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vu16 OCR1;
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u16 EMPTY11;
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vu16 OCR2;
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u16 EMPTY12[9];
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vu16 ICR1;
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u16 EMPTY13;
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vu16 ICR2;
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u16 EMPTY14[9];
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vu16 DMAB;
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u16 EMPTY15;
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} TIM_TypeDef;
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/*------------------------------------ PWM -----------------------------------*/
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typedef struct
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{
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vu16 CR;
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u16 EMPTY1;
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vu16 SCR;
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u16 EMPTY2[3];
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vu16 OMR1;
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u16 EMPTY3;
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vu16 OMR2;
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u16 EMPTY4[3];
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vu16 RSR;
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u16 EMPTY5;
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vu16 RER;
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u16 EMPTY6;
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vu16 ISR;
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u16 EMPTY7;
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vu16 CNT;
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u16 EMPTY8;
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vu16 PSC;
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u16 EMPTY9;
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vu16 RCR;
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u16 EMPTY10;
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vu16 ARR;
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u16 EMPTY11;
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vu16 OCR1;
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u16 EMPTY12;
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vu16 OCR2;
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u16 EMPTY13;
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vu16 OCR3;
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u16 EMPTY14[15];
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vu16 DTR;
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u16 EMPTY15;
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vu16 DMAB;
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u16 EMPTY16;
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} PWM_TypeDef;
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/*----------------------- Synchronous Serial Peripheral ----------------------*/
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typedef struct
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{
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vu32 CR0;
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vu32 CR1;
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vu32 DR;
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vu32 SR;
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vu32 PR;
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vu32 IMSCR;
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vu32 RISR;
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vu32 MISR;
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vu32 ICR;
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vu32 DMACR;
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} SSP_TypeDef;
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/*---------------- Universal Asynchronous Receiver Transmitter ---------------*/
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typedef struct
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{
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vu16 DR;
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u16 EMPTY;
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vu16 RSR;
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u16 EMPTY1[9];
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vu16 FR;
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u16 EMPTY2;
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vu16 BKR;
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u16 EMPTY3[3];
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vu16 IBRD;
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u16 EMPTY4;
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vu16 FBRD;
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u16 EMPTY5;
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vu16 LCR;
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u16 EMPTY6;
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vu16 CR;
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u16 EMPTY7;
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vu16 IFLS;
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u16 EMPTY8;
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vu16 IMSC;
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u16 EMPTY9;
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vu16 RIS;
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u16 EMPTY10;
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vu16 MIS;
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u16 EMPTY11;
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vu16 ICR;
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u16 EMPTY12;
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vu16 DMACR;
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u16 EMPTY13;
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} UART_TypeDef;
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/*---------------------------------- WATCHDOG --------------------------------*/
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typedef struct
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{
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vu16 CR;
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u16 EMPTY1;
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vu16 PR;
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u16 EMPTY2;
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vu16 VR;
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u16 EMPTY3;
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vu16 CNT;
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u16 EMPTY4;
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vu16 SR;
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u16 EMPTY5;
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vu16 MR;
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u16 EMPTY6;
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vu16 KR;
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u16 EMPTY7;
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} WDG_TypeDef;
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/*******************************************************************************
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* Peripherals' Base addresses
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*******************************************************************************/
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#define SRAM_BASE 0x40000000
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#define CONFIG_BASE 0x60000000
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#define SMIR_BASE 0x90000000
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#define PERIPH_BASE 0xFFFF0000
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#define CFG_BASE (CONFIG_BASE + 0x0010)
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#define MRCC_BASE (CONFIG_BASE + 0x0020)
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#define ADC_BASE (PERIPH_BASE + 0x8400)
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#define TB_BASE (PERIPH_BASE + 0x8800)
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#define TIM0_BASE (PERIPH_BASE + 0x8C00)
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#define TIM1_BASE (PERIPH_BASE + 0x9000)
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#define TIM2_BASE (PERIPH_BASE + 0x9400)
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#define PWM_BASE (PERIPH_BASE + 0x9800)
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#define WDG_BASE (PERIPH_BASE + 0xB000)
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#define SSP0_BASE (PERIPH_BASE + 0xB800)
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#define SSP1_BASE (PERIPH_BASE + 0xBC00)
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#define CAN_BASE (PERIPH_BASE + 0xC400)
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#define I2C_BASE (PERIPH_BASE + 0xCC00)
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#define UART0_BASE (PERIPH_BASE + 0xD400)
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#define UART1_BASE (PERIPH_BASE + 0xD800)
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#define UART2_BASE (PERIPH_BASE + 0xDC00)
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#define GPIO0_BASE (PERIPH_BASE + 0xE400)
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#define GPIOREMAP_BASE (PERIPH_BASE + 0xE420)
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#define GPIO1_BASE (PERIPH_BASE + 0xE440)
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#define GPIO2_BASE (PERIPH_BASE + 0xE480)
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#define DMA_BASE (PERIPH_BASE + 0xECF0)
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#define DMA_Stream0_BASE (PERIPH_BASE + 0xEC00)
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#define DMA_Stream1_BASE (PERIPH_BASE + 0xEC40)
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#define DMA_Stream2_BASE (PERIPH_BASE + 0xEC80)
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#define DMA_Stream3_BASE (PERIPH_BASE + 0xECC0)
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#define RTC_BASE (PERIPH_BASE + 0xF000)
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#define EXTIT_BASE (PERIPH_BASE + 0xF400)
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#define EIC_BASE (PERIPH_BASE + 0xF800)
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/*******************************************************************************
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IPs' declaration
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*******************************************************************************/
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/*------------------- Non Debug Mode -----------------------------------------*/
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#ifndef DEBUG
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#define SMI ((SMI_TypeDef *) SMIR_BASE)
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#define CFG ((CFG_TypeDef *) CFG_BASE)
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#define MRCC ((MRCC_TypeDef *) MRCC_BASE)
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#define ADC ((ADC_TypeDef *) ADC_BASE)
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#define TB ((TB_TypeDef *) TB_BASE)
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#define TIM0 ((TIM_TypeDef *) TIM0_BASE)
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#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
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#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
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#define PWM ((PWM_TypeDef *) PWM_BASE)
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#define WDG ((WDG_TypeDef *) WDG_BASE)
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#define SSP0 ((SSP_TypeDef *) SSP0_BASE)
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#define SSP1 ((SSP_TypeDef *) SSP1_BASE)
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#define CAN ((CAN_TypeDef *) CAN_BASE)
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#define I2C ((I2C_TypeDef *) I2C_BASE)
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#define UART0 ((UART_TypeDef *) UART0_BASE)
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#define UART1 ((UART_TypeDef *) UART1_BASE)
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#define UART2 ((UART_TypeDef *) UART2_BASE)
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#define GPIO0 ((GPIO_TypeDef *) GPIO0_BASE)
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#define GPIOREMAP ((GPIOREMAP_TypeDef *) GPIOREMAP_BASE)
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#define GPIO1 ((GPIO_TypeDef *) GPIO1_BASE)
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#define GPIO2 ((GPIO_TypeDef *) GPIO2_BASE)
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#define DMA ((DMA_TypeDef *) DMA_BASE)
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#define DMA_Stream0 ((DMA_Stream_TypeDef *) DMA_Stream0_BASE)
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#define DMA_Stream1 ((DMA_Stream_TypeDef *) DMA_Stream1_BASE)
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#define DMA_Stream2 ((DMA_Stream_TypeDef *) DMA_Stream2_BASE)
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#define DMA_Stream3 ((DMA_Stream_TypeDef *) DMA_Stream3_BASE)
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#define RTC ((RTC_TypeDef *) RTC_BASE)
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#define EXTIT ((EXTIT_TypeDef *) EXTIT_BASE)
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#define EIC ((EIC_TypeDef *) EIC_BASE)
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#else /* DEBUG */
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#ifdef _SMI
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EXT SMI_TypeDef *SMI;
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#endif /*_SMI */
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#ifdef _CFG
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EXT CFG_TypeDef *CFG;
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#endif /*_CFG */
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#ifdef _MRCC
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EXT MRCC_TypeDef *MRCC;
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#endif /*_MRCC */
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#ifdef _ADC
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EXT ADC_TypeDef *ADC;
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#endif /*_ADC */
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#ifdef _TB
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EXT TB_TypeDef *TB;
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#endif /*_TB */
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#ifdef _TIM0
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EXT TIM_TypeDef *TIM0;
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#endif /*_TIM0 */
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#ifdef _TIM1
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EXT TIM_TypeDef *TIM1;
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#endif /*_TIM1 */
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#ifdef _TIM2
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EXT TIM_TypeDef *TIM2;
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#endif /*_TIM2 */
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#ifdef _PWM
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EXT PWM_TypeDef *PWM;
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#endif /*_PWM */
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#ifdef _WDG
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EXT WDG_TypeDef *WDG;
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#endif /*_WDG */
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#ifdef _SSP0
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EXT SSP_TypeDef *SSP0;
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#endif /*_SSP0 */
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#ifdef _SSP1
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EXT SSP_TypeDef *SSP1;
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#endif /*_SSP1 */
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#ifdef _CAN
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EXT CAN_TypeDef *CAN;
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#endif /*_CAN */
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#ifdef _I2C
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EXT I2C_TypeDef *I2C;
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#endif /*_I2C */
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#ifdef _UART0
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EXT UART_TypeDef *UART0;
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#endif /*_UART0 */
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#ifdef _UART1
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EXT UART_TypeDef *UART1;
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#endif /*_UART1 */
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#ifdef _UART2
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EXT UART_TypeDef *UART2;
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#endif /*_UART2 */
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#ifdef _GPIO0
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EXT GPIO_TypeDef *GPIO0;
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#endif /*_GPIO0 */
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#ifdef _GPIOREMAP
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EXT GPIOREMAP_TypeDef *GPIOREMAP;
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#endif /*_GPIOREMAP */
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#ifdef _GPIO1
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EXT GPIO_TypeDef *GPIO1;
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#endif /*_GPIO1 */
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#ifdef _GPIO2
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EXT GPIO_TypeDef *GPIO2;
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#endif /*_GPIO2 */
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#ifdef _DMA
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EXT DMA_TypeDef *DMA;
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#endif /*_DMA */
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#ifdef _DMA_Stream0
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EXT DMA_Stream_TypeDef *DMA_Stream0;
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#endif /*_DMA_Stream0 */
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#ifdef _DMA_Stream1
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EXT DMA_Stream_TypeDef *DMA_Stream1;
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#endif /*_DMA_Stream1 */
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#ifdef _DMA_Stream2
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EXT DMA_Stream_TypeDef *DMA_Stream2;
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#endif /*_DMA_Stream2 */
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#ifdef _DMA_Stream3
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EXT DMA_Stream_TypeDef *DMA_Stream3;
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#endif /*_DMA_Stream3 */
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#ifdef _RTC
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EXT RTC_TypeDef *RTC;
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#endif /*_RTC */
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#ifdef _EXTIT
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EXT EXTIT_TypeDef *EXTIT;
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#endif /*_EXTIT */
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#ifdef _EIC
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EXT EIC_TypeDef *EIC;
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#endif /*_EIC */
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#endif /* DEBUG */
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/* Exported constants --------------------------------------------------------*/
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/* Exported macro ------------------------------------------------------------*/
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/* Exported functions ------------------------------------------------------- */
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#endif /* __75x_MAP_H */
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/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
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