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277 lines
9.7 KiB
C
277 lines
9.7 KiB
C
/*
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FreeRTOS.org V5.1.1 - Copyright (C) 2003-2008 Richard Barry.
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This file is part of the FreeRTOS.org distribution.
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FreeRTOS.org is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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FreeRTOS.org is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with FreeRTOS.org; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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A special exception to the GPL can be applied should you wish to distribute
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a combined work that includes FreeRTOS.org, without being obliged to provide
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the source code for any proprietary components. See the licensing section
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of http://www.FreeRTOS.org for full details of how and when the exception
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can be applied.
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***************************************************************************
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***************************************************************************
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* *
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* SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *
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* and even write all or part of your application on your behalf. *
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* See http://www.OpenRTOS.com for details of the services we provide to *
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* expedite your project. *
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* *
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***************************************************************************
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***************************************************************************
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Please ensure to read the configuration and relevant port sections of the
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online documentation.
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http://www.FreeRTOS.org - Documentation, latest information, license and
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contact details.
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http://www.SafeRTOS.com - A version that is certified for use in safety
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critical systems.
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http://www.OpenRTOS.com - Commercial support, development, porting,
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licensing and training services.
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*/
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/*-----------------------------------------------------------
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* Implementation of functions defined in portable.h for the ARM CM3 port.
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*----------------------------------------------------------*/
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
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defined. The value should also ensure backward compatibility.
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FreeRTOS.org versions prior to V4.4.0 did not include this definition. */
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#ifndef configKERNEL_INTERRUPT_PRIORITY
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#define configKERNEL_INTERRUPT_PRIORITY 255
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#endif
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/* Constants required to manipulate the NVIC. */
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#define portNVIC_SYSTICK_CTRL ( ( volatile unsigned portLONG *) 0xe000e010 )
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#define portNVIC_SYSTICK_LOAD ( ( volatile unsigned portLONG *) 0xe000e014 )
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#define portNVIC_INT_CTRL ( ( volatile unsigned portLONG *) 0xe000ed04 )
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#define portNVIC_SYSPRI2 ( ( volatile unsigned portLONG *) 0xe000ed20 )
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#define portNVIC_SYSTICK_CLK 0x00000004
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#define portNVIC_SYSTICK_INT 0x00000002
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#define portNVIC_SYSTICK_ENABLE 0x00000001
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#define portNVIC_PENDSVSET 0x10000000
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#define portNVIC_PENDSV_PRI ( ( ( unsigned portLONG ) configKERNEL_INTERRUPT_PRIORITY ) << 16 )
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#define portNVIC_SYSTICK_PRI ( ( ( unsigned portLONG ) configKERNEL_INTERRUPT_PRIORITY ) << 24 )
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/* Constants required to set up the initial stack. */
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#define portINITIAL_XPSR ( 0x01000000 )
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/* The priority used by the kernel is assigned to a variable to make access
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from inline assembler easier. */
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const unsigned portLONG ulKernelPriority = configKERNEL_INTERRUPT_PRIORITY;
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/* Each task maintains its own interrupt status in the critical nesting
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variable. */
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static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;
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/*
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* Setup the timer to generate the tick interrupts.
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*/
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static void prvSetupTimerInterrupt( void );
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/*
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* Exception handlers.
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*/
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void xPortPendSVHandler( void ) __attribute__ (( naked ));
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void xPortSysTickHandler( void );
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void vPortSVCHandler( void ) __attribute__ (( naked ));
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/*
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* Start first task is a separate function so it can be tested in isolation.
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*/
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void vPortStartFirstTask( void ) __attribute__ (( naked ));
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/*-----------------------------------------------------------*/
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/*
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* See header file for description.
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*/
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portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
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{
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/* Simulate the stack frame as it would be created by a context switch
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interrupt. */
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*pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */
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pxTopOfStack--;
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*pxTopOfStack = 0; /* LR */
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pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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*pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
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pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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return pxTopOfStack;
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}
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/*-----------------------------------------------------------*/
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void vPortSVCHandler( void )
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{
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asm volatile (
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" ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
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" ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
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" ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
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" ldmia r0!, {r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
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" msr psp, r0 \n" /* Restore the task stack pointer. */
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" mov r0, #0 \n"
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" msr basepri, r0 \n"
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" orr r14, #0xd \n"
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" bx r14 \n"
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" \n"
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" .align 2 \n"
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"pxCurrentTCBConst2: .word pxCurrentTCB \n"
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);
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}
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/*-----------------------------------------------------------*/
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void vPortStartFirstTask( void )
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{
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asm volatile(
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" ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
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" ldr r0, [r0] \n"
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" ldr r0, [r0] \n"
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" msr msp, r0 \n" /* Set the msp back to the start of the stack. */
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" svc 0 \n" /* System call to start first task. */
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);
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}
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/*-----------------------------------------------------------*/
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/*
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* See header file for description.
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*/
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portBASE_TYPE xPortStartScheduler( void )
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{
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/* Make PendSV, CallSV and SysTick the same priroity as the kernel. */
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*(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;
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*(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;
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/* Start the timer that generates the tick ISR. Interrupts are disabled
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here already. */
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prvSetupTimerInterrupt();
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/* Initialise the critical nesting count ready for the first task. */
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uxCriticalNesting = 0;
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/* Start the first task. */
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vPortStartFirstTask();
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/* Should not get here! */
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return 0;
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}
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/*-----------------------------------------------------------*/
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void vPortEndScheduler( void )
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{
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/* It is unlikely that the CM3 port will require this function as there
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is nothing to return to. */
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}
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/*-----------------------------------------------------------*/
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void vPortYieldFromISR( void )
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{
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/* Set a PendSV to request a context switch. */
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*(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;
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}
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/*-----------------------------------------------------------*/
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void vPortEnterCritical( void )
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{
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portDISABLE_INTERRUPTS();
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uxCriticalNesting++;
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}
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/*-----------------------------------------------------------*/
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void vPortExitCritical( void )
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{
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uxCriticalNesting--;
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if( uxCriticalNesting == 0 )
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{
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portENABLE_INTERRUPTS();
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}
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}
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/*-----------------------------------------------------------*/
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void xPortPendSVHandler( void )
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{
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/* This is a naked function. */
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__asm volatile
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(
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" mrs r0, psp \n"
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" \n"
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" ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */
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" ldr r2, [r3] \n"
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" \n"
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" stmdb r0!, {r4-r11} \n" /* Save the remaining registers. */
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" str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */
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" \n"
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" stmdb sp!, {r3, r14} \n"
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" mov r0, %0 \n"
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" msr basepri, r0 \n"
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" bl vTaskSwitchContext \n"
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" mov r0, #0 \n"
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" msr basepri, r0 \n"
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" ldmia sp!, {r3, r14} \n"
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" \n" /* Restore the context, including the critical nesting count. */
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" ldr r1, [r3] \n"
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" ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
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" ldmia r0!, {r4-r11} \n" /* Pop the registers. */
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" msr psp, r0 \n"
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" bx r14 \n"
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" \n"
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" .align 2 \n"
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"pxCurrentTCBConst: .word pxCurrentTCB \n"
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::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
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);
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}
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/*-----------------------------------------------------------*/
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void xPortSysTickHandler( void )
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{
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unsigned portLONG ulDummy;
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/* If using preemption, also force a context switch. */
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#if configUSE_PREEMPTION == 1
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*(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;
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#endif
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ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
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{
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vTaskIncrementTick();
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}
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portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
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}
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/*-----------------------------------------------------------*/
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/*
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* Setup the systick timer to generate the tick interrupts at the required
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* frequency.
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*/
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void prvSetupTimerInterrupt( void )
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{
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/* Configure SysTick to interrupt at the requested rate. */
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*(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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*(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
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}
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/*-----------------------------------------------------------*/
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