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233 lines
7.1 KiB
C
233 lines
7.1 KiB
C
#ifndef CGC_SET_VALUES_H_
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#define CGC_SET_VALUES_H_
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/* Do not modify these macros. These values are used to initialise
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the SCKCR and SCKCR2 registers based upon the above values. */
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#if (FCLK_DIV == 64)
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#define FCLK_SCKCR 0x60000000L
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#elif (FCLK_DIV == 32)
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#define FCLK_SCKCR 0x50000000L
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#elif (FCLK_DIV == 16)
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#define FCLK_SCKCR 0x40000000L
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#elif (FCLK_DIV == 8)
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#define FCLK_SCKCR 0x30000000L
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#elif (FCLK_DIV == 4)
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#define FCLK_SCKCR 0x20000000L
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#elif (FCLK_DIV == 2)
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#define FCLK_SCKCR 0x10000000L
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#elif(FCLK_DIV == 1)
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#define FCLK_SCKCR 0x00000000L
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#else
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#define FCLK_SCKCR 0x10000000L
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#endif
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#if (ICLK_DIV == 64)
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#define ICLK_SCKCR 0x06000000L
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#elif (ICLK_DIV == 32)
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#define ICLK_SCKCR 0x05000000L
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#elif (ICLK_DIV == 16)
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#define ICLK_SCKCR 0x04000000L
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#elif (ICLK_DIV == 8)
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#define ICLK_SCKCR 0x03000000L
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#elif (ICLK_DIV == 4)
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#define ICLK_SCKCR 0x02000000L
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#elif (ICLK_DIV == 2)
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#define ICLK_SCKCR 0x01000000L
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#elif (ICLK_DIV == 1)
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#define ICLK_SCKCR 0x00000000L
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#else
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#define ICLK_SCKCR 0x01000000L
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#endif
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#if (BCLK_PIN == 1)
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#define PSTOP1_SCKCR 0x00800000L
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#elif
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#define PSTOP1_SCKCR 0x00000000L
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#endif
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#if (BCLK_DIV == 64)
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#define BCLK_SCKCR 0x00060000L
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#elif (BCLK_DIV == 32)
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#define BCLK_SCKCR 0x00050000L
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#elif (BCLK_DIV == 16)
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#define BCLK_SCKCR 0x00040000L
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#elif (BCLK_DIV == 8)
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#define BCLK_SCKCR 0x00030000L
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#elif (BCLK_DIV == 4)
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#define BCLK_SCKCR 0x00020000L
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#elif (BCLK_DIV == 2)
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#define BCLK_SCKCR 0x00010000L
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#elif (BCLK_DIV == 1)
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#define BCLK_SCKCR 0x00000000L
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#else
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#define BCLK_SCKCR 0x00010000L
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#endif
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#if (PCLK1215_DIV == 64)
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#define PCLK1215_SCKCR 0x00006000L
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#elif (PCLK1215_DIV == 32)
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#define PCLK1215_SCKCR 0x00005000L
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#elif (PCLK1215_DIV == 16)
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#define PCLK1215_SCKCR 0x00004000L
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#elif (PCLK1215_DIV == 8)
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#define PCLK1215_SCKCR 0x00003000L
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#elif (PCLK1215_DIV == 4)
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#define PCLK1215_SCKCR 0x00002000L
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#elif (PCLK1215_DIV == 2)
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#define PCLK1215_SCKCR 0x00001000L
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#elif (PCLK1215_DIV == 1)
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#define PCLK1215_SCKCR 0x00000000L
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#else
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#define PCLK1215_SCKCR 0x00001000L
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#endif
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#if (PCLKB_DIV == 64)
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#define PCLKB_SCKCR 0x00000600L
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#elif (PCLKB_DIV == 32)
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#define PCLKB_SCKCR 0x00000500L
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#elif (PCLKB_DIV == 16)
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#define PCLKB_SCKCR 0x00000400L
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#elif (PCLKB_DIV == 8)
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#define PCLKB_SCKCR 0x00000300L
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#elif (PCLKB_DIV == 4)
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#define PCLKB_SCKCR 0x00000200L
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#elif (PCLKB_DIV == 2)
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#define PCLKB_SCKCR 0x00000100L
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#elif (PCLKB_DIV == 1)
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#define PCLKB_SCKCR 0x00000000L
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#else
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#define PCLKB_SCKCR 0x00000100L
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#endif
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#if (PCLK47_DIV == 64)
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#define PCLK47_SCKCR 0x00000060L
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#elif (PCLK47_DIV == 32)
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#define PCLK47_SCKCR 0x00000050L
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#elif (PCLK47_DIV == 16)
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#define PCLK47_SCKCR 0x00000040L
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#elif (PCLK47_DIV == 8)
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#define PCLK47_SCKCR 0x00000030L
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#elif (PCLK47_DIV == 4)
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#define PCLK47_SCKCR 0x00000020L
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#elif (PCLK47_DIV == 2)
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#define PCLK47_SCKCR 0x00000010L
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#elif (PCLK47_DIV == 1)
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#define PCLK47_SCKCR 0x00000000L
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#else
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#define PCLK47_SCKCR 0x00000010L
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#endif
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#if (PCLK03_DIV == 64)
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#define PCLK03_SCKCR 0x00000006L
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#elif (PCLK03_DIV == 32)
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#define PCLK03_SCKCR 0x00000005L
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#elif (PCLK03_DIV == 16)
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#define PCLK03_SCKCR 0x00000004L
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#elif (PCLK03_DIV == 8)
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#define PCLK03_SCKCR 0x00000003L
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#elif (PCLK03_DIV == 4)
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#define PCLK03_SCKCR 0x00000002L
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#elif (PCLK03_DIV == 2)
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#define PCLK03_SCKCR 0x00000001L
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#elif (PCLK03_DIV == 1)
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#define PCLK03_SCKCR 0x00000000L
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#else
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#define PCLK03_SCKCR 0x00000001L
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#endif
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#if (UCK_DIV == 6)
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#define UCK_SCKCR2 0x00C0L
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#elif (UCK_DIV == 64)
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#define UCK_SCKCR2 0x0060L
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#elif (UCK_DIV == 32)
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#define UCK_SCKCR2 0x0050L
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#elif (UCK_DIV == 16)
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#define UCK_SCKCR2 0x0040L
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#elif (UCK_DIV == 8)
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#define UCK_SCKCR2 0x0030L
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#elif (UCK_DIV == 4)
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#define UCK_SCKCR2 0x0020L
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#elif (UCK_DIV == 2)
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#define UCK_SCKCR2 0x0010L
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#else
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#define UCK_SCKCR2 0x0010L
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#endif
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#if (IEBCK_DIV == 3)
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#define IEBCK_SCKCR2 0x00000020L
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#elif (IEBCK_DIV == 4)
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#define IEBCK_SCKCR2 0x00000030L
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#else
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#define IEBCK_SCKCR2 0x00000030L
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#endif
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#if (CLK_SOURCE == CLK_SOURCE_LOCO)
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/* Internal LOCO circuit - 125kHz*/
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#define CLK_FREQUENCY (125000L)
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#define FCLK_FREQUENCY (CLK_FREQUENCY / FCLK_DIV)
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#define ICLK_FREQUENCY (CLK_FREQUENCY / ICLK_DIV)
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#define BCLK_FREQUENCY (CLK_FREQUENCY / BCLK_DIV)
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#define PCLKA_FREQUENCY (CLK_FREQUENCY / PCLK1215_DIV)
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#define PCLKB_FREQUENCY (CLK_FREQUENCY / PCLKB_DIV)
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#define PCLK47_FREQUENCY (CLK_FREQUENCY / PCLK47_DIV)
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#define PCLK03_FREQUENCY (CLK_FREQUENCY / PCLK03_DIV)
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#elif (CLK_SOURCE == CLK_SOURCE_HOCO)
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/* Internal high speed on-chip oscillator (HOCO) */
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#define CLK_FREQUENCY (50000000L)
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#define FCLK_FREQUENCY (CLK_FREQUENCY / FCLK_DIV)
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#define ICLK_FREQUENCY (CLK_FREQUENCY / ICLK_DIV)
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#define BCLK_FREQUENCY (CLK_FREQUENCY / BCLK_DIV)
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#define PCLKA_FREQUENCY (CLK_FREQUENCY / PCLK1215_DIV)
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#define PCLKB_FREQUENCY (CLK_FREQUENCY / PCLKB_DIV)
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#define PCLK47_FREQUENCY (CLK_FREQUENCY / PCLK47_DIV)
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#define PCLK03_FREQUENCY (CLK_FREQUENCY / PCLK03_DIV)
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#elif (CLK_SOURCE == CLK_SOURCE_MAIN)
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/* External XTAL, but not via the PLL circuit */
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#define FCLK_FREQUENCY (XTAL_FREQUENCY / FCLK_DIV)
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#define ICLK_FREQUENCY (XTAL_FREQUENCY / ICLK_DIV)
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#define BCLK_FREQUENCY (XTAL_FREQUENCY / BCLK_DIV)
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#define PCLKA_FREQUENCY (XTAL_FREQUENCY / PCLK1215_DIV)
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#define PCLKB_FREQUENCY (XTAL_FREQUENCY / PCLKB_DIV)
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#define PCLK47_FREQUENCY (XTAL_FREQUENCY / PCLK47_DIV)
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#define PCLK03_FREQUENCY (XTAL_FREQUENCY / PCLK03_DIV)
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#elif (CLK_SOURCE == CLK_SOURCE_SUB)
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/* External 32khZ XTAL */
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#define FCLK_FREQUENCY (SUB_FREQUENCY / FCLK_DIV)
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#define ICLK_FREQUENCY (SUB_FREQUENCY / ICLK_DIV)
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#define BCLK_FREQUENCY (SUB_FREQUENCY / BCLK_DIV)
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#define PCLKA_FREQUENCY (SUB_FREQUENCY / PCLK1215_DIV)
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#define PCLKB_FREQUENCY (SUB_FREQUENCY / PCLKB_DIV)
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#define PCLK47_FREQUENCY (SUB_FREQUENCY / PCLK47_DIV)
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#define PCLK03_FREQUENCY (SUB_FREQUENCY / PCLK03_DIV)
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#elif (CLK_SOURCE == CLK_SOURCE_PLL)
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/* External XTAL, but using the PLL circuit */
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#define PLL_FREQUENCY (XTAL_FREQUENCY * (PLL_MUL / PLL_INPUT_FREQ_DIV))
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#define FCLK_FREQUENCY (PLL_FREQUENCY / FCLK_DIV)
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#define ICLK_FREQUENCY (PLL_FREQUENCY / ICLK_DIV)
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#define BCLK_FREQUENCY (PLL_FREQUENCY / BCLK_DIV)
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#define PCLKA_FREQUENCY (PLL_FREQUENCY / PCLK1215_DIV)
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#define PCLKB_FREQUENCY (PLL_FREQUENCY / PCLKB_DIV)
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#define PCLK47_FREQUENCY (PLL_FREQUENCY / PCLK47_DIV)
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#define PCLK03_FREQUENCY (PLL_FREQUENCY / PCLK03_DIV)
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#endif
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#endif |