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607 lines
17 KiB
C
607 lines
17 KiB
C
/*
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FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
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***************************************************************************
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* *
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* FreeRTOS tutorial books are available in pdf and paperback. *
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* Complete, revised, and edited pdf reference manuals are also *
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* available. *
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* *
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* Purchasing FreeRTOS documentation will not only help you, by *
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* ensuring you get running as quickly as possible and with an *
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* in-depth knowledge of how to use FreeRTOS, it will also help *
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* the FreeRTOS project to continue with its mission of providing *
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* professional grade, cross platform, de facto standard solutions *
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* for microcontrollers - completely free of charge! *
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* *
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* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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* *
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* Thank you for using FreeRTOS, and thank you for your support! *
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* *
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***************************************************************************
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This file is part of the FreeRTOS distribution.
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FreeRTOS is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License (version 2) as published by the
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Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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>>>NOTE<<< The modification to the GPL is included to allow you to
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distribute a combined work that includes FreeRTOS without being obliged to
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provide the source code for proprietary components outside of the FreeRTOS
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kernel. FreeRTOS is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details. You should have received a copy of the GNU General Public
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License and the FreeRTOS license exception along with FreeRTOS; if not it
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can be viewed here: http://www.freertos.org/a00114.html and also obtained
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by writing to Richard Barry, contact details for whom are available on the
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FreeRTOS WEB site.
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1 tab == 4 spaces!
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http://www.FreeRTOS.org - Documentation, latest information, license and
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contact details.
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http://www.SafeRTOS.com - A version that is certified for use in safety
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critical systems.
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http://www.OpenRTOS.com - Commercial support, development, porting,
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licensing and training services.
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*/
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/* Originally adapted from file written by Andreas Dannenberg. Supplied with permission. */
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/* Kernel includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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#include "semphr.h"
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/* Hardware specific includes. */
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#include "EthDev_LPC17xx.h"
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/* Time to wait between each inspection of the link status. */
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#define emacWAIT_FOR_LINK_TO_ESTABLISH ( 500 / portTICK_RATE_MS )
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/* Short delay used in several places during the initialisation process. */
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#define emacSHORT_DELAY ( 2 )
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/* Hardware specific bit definitions. */
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#define emacLINK_ESTABLISHED ( 0x0020)
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#define emacFULL_DUPLEX_ENABLED ( 0x0010 )
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#define emac10BASE_T_MODE ( 0x0004 )
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#define emacPINSEL2_VALUE ( 0x50150105 )
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#define emacDIV_44 ( 0x28 )
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/* If no buffers are available, then wait this long before looking again.... */
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#define emacBUFFER_WAIT_DELAY ( 3 / portTICK_RATE_MS )
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/* ...and don't look more than this many times. */
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#define emacBUFFER_WAIT_ATTEMPTS ( 30 )
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/* Index to the Tx descriptor that is always used first for every Tx. The second
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descriptor is then used to re-send in order to speed up the uIP Tx process. */
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#define emacTX_DESC_INDEX ( 0 )
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/*-----------------------------------------------------------*/
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/*
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* Configure both the Rx and Tx descriptors during the init process.
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*/
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static void prvInitDescriptors( void );
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/*
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* Setup the IO and peripherals required for Ethernet communication.
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*/
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static void prvSetupEMACHardware( void );
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/*
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* Control the auto negotiate process.
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*/
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static void prvConfigurePHY( void );
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/*
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* Wait for a link to be established, then setup the PHY according to the link
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* parameters.
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*/
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static long prvSetupLinkStatus( void );
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/*
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* Search the pool of buffers to find one that is free. If a buffer is found
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* mark it as in use before returning its address.
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*/
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static unsigned char *prvGetNextBuffer( void );
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/*
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* Return an allocated buffer to the pool of free buffers.
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*/
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static void prvReturnBuffer( unsigned char *pucBuffer );
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/*
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* Send lValue to the lPhyReg within the PHY.
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*/
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static long prvWritePHY( long lPhyReg, long lValue );
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/*
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* Read a value from ucPhyReg within the PHY. *plStatus will be set to
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* pdFALSE if there is an error.
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*/
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static unsigned short prvReadPHY( unsigned char ucPhyReg, long *plStatus );
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/*-----------------------------------------------------------*/
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/* The semaphore used to wake the uIP task when data arrives. */
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extern xSemaphoreHandle xEMACSemaphore;
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/* Each ucBufferInUse index corresponds to a position in the pool of buffers.
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If the index contains a 1 then the buffer within pool is in use, if it
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contains a 0 then the buffer is free. */
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static unsigned char ucBufferInUse[ ETH_NUM_BUFFERS ] = { pdFALSE };
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/* The uip_buffer is not a fixed array, but instead gets pointed to the buffers
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allocated within this file. */
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unsigned char * uip_buf;
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/* Store the length of the data being sent so the data can be sent twice. The
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value will be set back to 0 once the data has been sent twice. */
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static unsigned short usSendLen = 0;
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/*-----------------------------------------------------------*/
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long lEMACInit( void )
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{
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long lReturn = pdPASS;
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unsigned long ulID1, ulID2;
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/* Reset peripherals, configure port pins and registers. */
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prvSetupEMACHardware();
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/* Check the PHY part number is as expected. */
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ulID1 = prvReadPHY( PHY_REG_IDR1, &lReturn );
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ulID2 = prvReadPHY( PHY_REG_IDR2, &lReturn );
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if( ( (ulID1 << 16UL ) | ( ulID2 & 0xFFFFUL ) ) == KS8721_ID )
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{
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/* Set the Ethernet MAC Address registers */
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EMAC->SA0 = ( configMAC_ADDR0 << 8 ) | configMAC_ADDR1;
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EMAC->SA1 = ( configMAC_ADDR2 << 8 ) | configMAC_ADDR3;
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EMAC->SA2 = ( configMAC_ADDR4 << 8 ) | configMAC_ADDR5;
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/* Initialize Tx and Rx DMA Descriptors */
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prvInitDescriptors();
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/* Receive broadcast and perfect match packets */
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EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
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/* Setup the PHY. */
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prvConfigurePHY();
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}
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else
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{
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lReturn = pdFAIL;
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}
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/* Check the link status. */
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if( lReturn == pdPASS )
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{
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lReturn = prvSetupLinkStatus();
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}
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if( lReturn == pdPASS )
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{
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/* Initialise uip_buf to ensure it points somewhere valid. */
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uip_buf = prvGetNextBuffer();
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/* Reset all interrupts */
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EMAC->IntClear = ( INT_RX_OVERRUN | INT_RX_ERR | INT_RX_FIN | INT_RX_DONE | INT_TX_UNDERRUN | INT_TX_ERR | INT_TX_FIN | INT_TX_DONE | INT_SOFT_INT | INT_WAKEUP );
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/* Enable receive and transmit mode of MAC Ethernet core */
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EMAC->Command |= ( CR_RX_EN | CR_TX_EN );
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EMAC->MAC1 |= MAC1_REC_EN;
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}
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return lReturn;
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}
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/*-----------------------------------------------------------*/
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static unsigned char *prvGetNextBuffer( void )
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{
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long x;
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unsigned char *pucReturn = NULL;
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unsigned long ulAttempts = 0;
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while( pucReturn == NULL )
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{
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/* Look through the buffers to find one that is not in use by
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anything else. */
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for( x = 0; x < ETH_NUM_BUFFERS; x++ )
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{
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if( ucBufferInUse[ x ] == pdFALSE )
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{
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ucBufferInUse[ x ] = pdTRUE;
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pucReturn = ( unsigned char * ) ETH_BUF( x );
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break;
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}
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}
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/* Was a buffer found? */
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if( pucReturn == NULL )
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{
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ulAttempts++;
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if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )
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{
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break;
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}
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/* Wait then look again. */
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vTaskDelay( emacBUFFER_WAIT_DELAY );
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}
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}
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return pucReturn;
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}
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/*-----------------------------------------------------------*/
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static void prvInitDescriptors( void )
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{
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long x, lNextBuffer = 0;
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for( x = 0; x < NUM_RX_FRAG; x++ )
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{
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/* Allocate the next Ethernet buffer to this descriptor. */
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RX_DESC_PACKET( x ) = ETH_BUF( lNextBuffer );
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RX_DESC_CTRL( x ) = RCTRL_INT | ( ETH_FRAG_SIZE - 1 );
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RX_STAT_INFO( x ) = 0;
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RX_STAT_HASHCRC( x ) = 0;
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/* The Ethernet buffer is now in use. */
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ucBufferInUse[ lNextBuffer ] = pdTRUE;
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lNextBuffer++;
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}
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/* Set EMAC Receive Descriptor Registers. */
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EMAC->RxDescriptor = RX_DESC_BASE;
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EMAC->RxStatus = RX_STAT_BASE;
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EMAC->RxDescriptorNumber = NUM_RX_FRAG - 1;
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/* Rx Descriptors Point to 0 */
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EMAC->RxConsumeIndex = 0;
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/* A buffer is not allocated to the Tx descriptors until they are actually
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used. */
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for( x = 0; x < NUM_TX_FRAG; x++ )
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{
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TX_DESC_PACKET( x ) = ( unsigned long ) NULL;
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TX_DESC_CTRL( x ) = 0;
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TX_STAT_INFO( x ) = 0;
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}
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/* Set EMAC Transmit Descriptor Registers. */
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EMAC->TxDescriptor = TX_DESC_BASE;
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EMAC->TxStatus = TX_STAT_BASE;
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EMAC->TxDescriptorNumber = NUM_TX_FRAG - 1;
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/* Tx Descriptors Point to 0 */
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EMAC->TxProduceIndex = 0;
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}
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/*-----------------------------------------------------------*/
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static void prvSetupEMACHardware( void )
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{
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unsigned short us;
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long x, lDummy;
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/* Enable P1 Ethernet Pins. */
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PINCON->PINSEL2 = emacPINSEL2_VALUE;
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PINCON->PINSEL3 = ( PINCON->PINSEL3 & ~0x0000000F ) | 0x00000005;
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/* Power Up the EMAC controller. */
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SC->PCONP |= PCONP_PCENET;
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vTaskDelay( emacSHORT_DELAY );
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/* Reset all EMAC internal modules. */
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EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
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EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
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/* A short delay after reset. */
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vTaskDelay( emacSHORT_DELAY );
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/* Initialize MAC control registers. */
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EMAC->MAC1 = MAC1_PASS_ALL;
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EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
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EMAC->MAXF = ETH_MAX_FLEN;
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EMAC->CLRT = CLRT_DEF;
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EMAC->IPGR = IPGR_DEF;
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EMAC->MCFG = emacDIV_44;
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/* Enable Reduced MII interface. */
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EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;
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/* Reset Reduced MII Logic. */
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EMAC->SUPP = SUPP_RES_RMII;
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vTaskDelay( emacSHORT_DELAY );
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EMAC->SUPP = 0;
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/* Put the PHY in reset mode */
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prvWritePHY( PHY_REG_BMCR, MCFG_RES_MII );
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prvWritePHY( PHY_REG_BMCR, MCFG_RES_MII );
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/* Wait for hardware reset to end. */
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for( x = 0; x < 100; x++ )
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{
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vTaskDelay( emacSHORT_DELAY * 5 );
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us = prvReadPHY( PHY_REG_BMCR, &lDummy );
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if( !( us & MCFG_RES_MII ) )
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{
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/* Reset complete */
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break;
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}
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}
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}
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/*-----------------------------------------------------------*/
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static void prvConfigurePHY( void )
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{
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unsigned short us;
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long x, lDummy;
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/* Auto negotiate the configuration. */
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if( prvWritePHY( PHY_REG_BMCR, PHY_AUTO_NEG ) )
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{
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vTaskDelay( emacSHORT_DELAY * 5 );
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for( x = 0; x < 10; x++ )
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{
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us = prvReadPHY( PHY_REG_BMSR, &lDummy );
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if( us & PHY_AUTO_NEG_COMPLETE )
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{
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break;
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}
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vTaskDelay( emacWAIT_FOR_LINK_TO_ESTABLISH );
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}
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}
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}
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/*-----------------------------------------------------------*/
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static long prvSetupLinkStatus( void )
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{
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long lReturn = pdFAIL, x;
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unsigned short usLinkStatus;
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/* Wait with timeout for the link to be established. */
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for( x = 0; x < 10; x++ )
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{
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usLinkStatus = prvReadPHY( PHY_CTRLER, &lReturn );
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if( usLinkStatus != 0x00 )
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{
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/* Link is established. */
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lReturn = pdPASS;
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break;
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}
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vTaskDelay( emacWAIT_FOR_LINK_TO_ESTABLISH );
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}
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if( lReturn == pdPASS )
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{
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/* Configure Full/Half Duplex mode. */
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if( usLinkStatus & emacFULL_DUPLEX_ENABLED )
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{
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/* Full duplex is enabled. */
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EMAC->MAC2 |= MAC2_FULL_DUP;
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EMAC->Command |= CR_FULL_DUP;
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EMAC->IPGT = IPGT_FULL_DUP;
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}
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else
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{
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/* Half duplex mode. */
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EMAC->IPGT = IPGT_HALF_DUP;
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}
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/* Configure 100MBit/10MBit mode. */
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if( usLinkStatus & emac10BASE_T_MODE )
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{
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/* 10MBit mode. */
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EMAC->SUPP = 0;
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}
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else
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{
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/* 100MBit mode. */
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EMAC->SUPP = SUPP_SPEED;
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}
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}
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return lReturn;
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}
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/*-----------------------------------------------------------*/
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static void prvReturnBuffer( unsigned char *pucBuffer )
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{
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unsigned long ul;
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/* Return a buffer to the pool of free buffers. */
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for( ul = 0; ul < ETH_NUM_BUFFERS; ul++ )
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{
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if( ETH_BUF( ul ) == ( unsigned long ) pucBuffer )
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{
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ucBufferInUse[ ul ] = pdFALSE;
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break;
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}
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}
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}
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/*-----------------------------------------------------------*/
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unsigned long ulGetEMACRxData( void )
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{
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unsigned long ulLen = 0;
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long lIndex;
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if( EMAC->RxProduceIndex != EMAC->RxConsumeIndex )
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{
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/* Mark the current buffer as free as uip_buf is going to be set to
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the buffer that contains the received data. */
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prvReturnBuffer( uip_buf );
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ulLen = ( RX_STAT_INFO( EMAC->RxConsumeIndex ) & RINFO_SIZE ) - 3;
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uip_buf = ( unsigned char * ) RX_DESC_PACKET( EMAC->RxConsumeIndex );
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/* Allocate a new buffer to the descriptor. */
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RX_DESC_PACKET( EMAC->RxConsumeIndex ) = ( unsigned long ) prvGetNextBuffer();
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/* Move the consume index onto the next position, ensuring it wraps to
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the beginning at the appropriate place. */
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lIndex = EMAC->RxConsumeIndex;
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lIndex++;
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if( lIndex >= NUM_RX_FRAG )
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{
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lIndex = 0;
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}
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EMAC->RxConsumeIndex = lIndex;
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}
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return ulLen;
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}
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/*-----------------------------------------------------------*/
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void vSendEMACTxData( unsigned short usTxDataLen )
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{
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unsigned long ulAttempts = 0UL;
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/* Check to see if the Tx descriptor is free, indicated by its buffer being
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NULL. */
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while( TX_DESC_PACKET( emacTX_DESC_INDEX ) != ( unsigned long ) NULL )
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{
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/* Wait for the Tx descriptor to become available. */
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vTaskDelay( emacBUFFER_WAIT_DELAY );
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ulAttempts++;
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if( ulAttempts > emacBUFFER_WAIT_ATTEMPTS )
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{
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/* Something has gone wrong as the Tx descriptor is still in use.
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Clear it down manually, the data it was sending will probably be
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lost. */
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prvReturnBuffer( ( unsigned char * ) TX_DESC_PACKET( emacTX_DESC_INDEX ) );
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break;
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}
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}
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/* Setup the Tx descriptor for transmission. Remember the length of the
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data being sent so the second descriptor can be used to send it again from
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within the ISR. */
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usSendLen = usTxDataLen;
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TX_DESC_PACKET( emacTX_DESC_INDEX ) = ( unsigned long ) uip_buf;
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TX_DESC_CTRL( emacTX_DESC_INDEX ) = ( usTxDataLen | TCTRL_LAST | TCTRL_INT );
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EMAC->TxProduceIndex = ( emacTX_DESC_INDEX + 1 );
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/* uip_buf is being sent by the Tx descriptor. Allocate a new buffer. */
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uip_buf = prvGetNextBuffer();
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}
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/*-----------------------------------------------------------*/
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static long prvWritePHY( long lPhyReg, long lValue )
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{
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const long lMaxTime = 10;
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long x;
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EMAC->MADR = KS8721_DEF_ADR | lPhyReg;
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EMAC->MWTD = lValue;
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x = 0;
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for( x = 0; x < lMaxTime; x++ )
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{
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if( ( EMAC->MIND & MIND_BUSY ) == 0 )
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{
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/* Operation has finished. */
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break;
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}
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vTaskDelay( emacSHORT_DELAY );
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}
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if( x < lMaxTime )
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{
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return pdPASS;
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}
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else
|
|
{
|
|
return pdFAIL;
|
|
}
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static unsigned short prvReadPHY( unsigned char ucPhyReg, long *plStatus )
|
|
{
|
|
long x;
|
|
const long lMaxTime = 10;
|
|
|
|
EMAC->MADR = KS8721_DEF_ADR | ucPhyReg;
|
|
EMAC->MCMD = MCMD_READ;
|
|
|
|
for( x = 0; x < lMaxTime; x++ )
|
|
{
|
|
/* Operation has finished. */
|
|
if( ( EMAC->MIND & MIND_BUSY ) == 0 )
|
|
{
|
|
break;
|
|
}
|
|
|
|
vTaskDelay( emacSHORT_DELAY );
|
|
}
|
|
|
|
EMAC->MCMD = 0;
|
|
|
|
if( x >= lMaxTime )
|
|
{
|
|
*plStatus = pdFAIL;
|
|
}
|
|
|
|
return( EMAC->MRDD );
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vEMAC_ISR( void )
|
|
{
|
|
unsigned long ulStatus;
|
|
long lHigherPriorityTaskWoken = pdFALSE;
|
|
|
|
ulStatus = EMAC->IntStatus;
|
|
|
|
/* Clear the interrupt. */
|
|
EMAC->IntClear = ulStatus;
|
|
|
|
if( ulStatus & INT_RX_DONE )
|
|
{
|
|
/* Ensure the uIP task is not blocked as data has arrived. */
|
|
xSemaphoreGiveFromISR( xEMACSemaphore, &lHigherPriorityTaskWoken );
|
|
}
|
|
|
|
if( ulStatus & INT_TX_DONE )
|
|
{
|
|
if( usSendLen > 0 )
|
|
{
|
|
/* Send the data again, using the second descriptor. As there are
|
|
only two descriptors the index is set back to 0. */
|
|
TX_DESC_PACKET( ( emacTX_DESC_INDEX + 1 ) ) = TX_DESC_PACKET( emacTX_DESC_INDEX );
|
|
TX_DESC_CTRL( ( emacTX_DESC_INDEX + 1 ) ) = ( usSendLen | TCTRL_LAST | TCTRL_INT );
|
|
EMAC->TxProduceIndex = ( emacTX_DESC_INDEX );
|
|
|
|
/* This is the second Tx so set usSendLen to 0 to indicate that the
|
|
Tx descriptors will be free again. */
|
|
usSendLen = 0UL;
|
|
}
|
|
else
|
|
{
|
|
/* The Tx buffer is no longer required. */
|
|
prvReturnBuffer( ( unsigned char * ) TX_DESC_PACKET( emacTX_DESC_INDEX ) );
|
|
TX_DESC_PACKET( emacTX_DESC_INDEX ) = ( unsigned long ) NULL;
|
|
}
|
|
}
|
|
|
|
portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );
|
|
}
|