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361 lines
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361 lines
20 KiB
Plaintext
#
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# pin constraints
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#
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NET CLK_N LOC = "K22" | DIFF_TERM = "TRUE" | IOSTANDARD = "LVDS_25";
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NET CLK_P LOC = "K21" | DIFF_TERM = "TRUE" | IOSTANDARD = "LVDS_25";
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NET DIP_Switches_4Bits_TRI_I[0] LOC = "C18" | IOSTANDARD = "LVCMOS25";
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NET DIP_Switches_4Bits_TRI_I[1] LOC = "Y6" | IOSTANDARD = "LVCMOS25";
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NET DIP_Switches_4Bits_TRI_I[2] LOC = "W6" | IOSTANDARD = "LVCMOS25";
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NET DIP_Switches_4Bits_TRI_I[3] LOC = "E4" | IOSTANDARD = "LVCMOS25";
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NET ETHERNET_MDC LOC = "R19" | IOSTANDARD = "LVCMOS25";
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NET ETHERNET_MDIO LOC = "V20" | IOSTANDARD = "LVCMOS25";
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NET ETHERNET_MII_TX_CLK LOC = "L20" | IOSTANDARD = "LVCMOS25";
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NET ETHERNET_PHY_RST_N LOC = "J22" | IOSTANDARD = "LVCMOS25" | TIG;
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NET ETHERNET_RXD[0] LOC = "P19" | IOSTANDARD = "LVCMOS25";
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NET ETHERNET_RXD[1] LOC = "Y22" | IOSTANDARD = "LVCMOS25";
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NET ETHERNET_RXD[2] LOC = "Y21" | IOSTANDARD = "LVCMOS25";
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NET ETHERNET_RXD[3] LOC = "W22" | IOSTANDARD = "LVCMOS25";
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NET ETHERNET_RXD[4] LOC = "W20" | IOSTANDARD = "LVCMOS25";
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NET ETHERNET_RXD[5] LOC = "V22" | IOSTANDARD = "LVCMOS25";
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NET ETHERNET_RXD[6] LOC = "V21" | IOSTANDARD = "LVCMOS25";
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NET ETHERNET_RXD[7] LOC = "U22" | IOSTANDARD = "LVCMOS25";
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NET ETHERNET_RX_CLK LOC = "P20" | IOSTANDARD = "LVCMOS25";
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NET ETHERNET_RX_DV LOC = "T22" | IOSTANDARD = "LVCMOS25";
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NET ETHERNET_RX_ER LOC = "U20" | IOSTANDARD = "LVCMOS25";
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NET ETHERNET_TXD[0] LOC = "U10" | IOSTANDARD = "LVCMOS25";
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NET ETHERNET_TXD[1] LOC = "T10" | IOSTANDARD = "LVCMOS25";
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NET ETHERNET_TXD[2] LOC = "AB8" | IOSTANDARD = "LVCMOS25";
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NET ETHERNET_TXD[3] LOC = "AA8" | IOSTANDARD = "LVCMOS25";
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NET ETHERNET_TXD[4] LOC = "AB9" | IOSTANDARD = "LVCMOS25";
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NET ETHERNET_TXD[5] LOC = "Y9" | IOSTANDARD = "LVCMOS25";
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NET ETHERNET_TXD[6] LOC = "Y12" | IOSTANDARD = "LVCMOS25";
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NET ETHERNET_TXD[7] LOC = "W12" | IOSTANDARD = "LVCMOS25";
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NET ETHERNET_TX_CLK LOC = "AB7" | IOSTANDARD = "LVCMOS25";
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NET ETHERNET_TX_EN LOC = "T8" | IOSTANDARD = "LVCMOS25";
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NET ETHERNET_TX_ER LOC = "U8" | IOSTANDARD = "LVCMOS25";
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NET LEDs_4Bits_TRI_O[0] LOC = "D17" | IOSTANDARD = "LVCMOS25";
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NET LEDs_4Bits_TRI_O[1] LOC = "AB4" | IOSTANDARD = "LVCMOS25";
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NET LEDs_4Bits_TRI_O[2] LOC = "D21" | IOSTANDARD = "LVCMOS25";
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NET LEDs_4Bits_TRI_O[3] LOC = "W15" | IOSTANDARD = "LVCMOS25";
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NET Push_Buttons_4Bits_TRI_I[0] LOC = "F3" | IOSTANDARD = "LVCMOS25";
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NET Push_Buttons_4Bits_TRI_I[1] LOC = "G6" | IOSTANDARD = "LVCMOS25";
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NET Push_Buttons_4Bits_TRI_I[2] LOC = "F5" | IOSTANDARD = "LVCMOS25";
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NET Push_Buttons_4Bits_TRI_I[3] LOC = "C1" | IOSTANDARD = "LVCMOS25";
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NET RESET LOC = "H8" | IOSTANDARD = "LVCMOS15" | TIG;
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NET RS232_Uart_1_sin LOC = "H17" | IOSTANDARD = "LVCMOS25";
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NET RS232_Uart_1_sout LOC = "B21" | IOSTANDARD = "LVCMOS25";
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#
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# additional constraints
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#
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NET "CLK" TNM_NET = sys_clk_pin;
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TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 200000 kHz;
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###### Soft ETHERNET
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# This is a GMII system
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# AXI_STR_*_ACLK is not the same as S_AXI_ACLK from clock generator
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# Rx/Tx Client clocks are Rx/Tx PHY clocks so CORE Gen PHY clock constraints propagate to Rx/Tx client clock periods
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# Time domain crossing constraints (DATAPATHONLY) are set for maximum bus frequency
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# allowed by IP which is the maximum option in BSB. For lower bus frequency choice in BSB,
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# the constraints are over constrained. Relaxing them for your system may reduce build time.
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NET "*ETHERNET*/S_AXI_ACLK" TNM_NET = "axi4lite_clk";
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NET "*ETHERNET*/AXI_STR_TXD_ACLK" TNM_NET = "axistream_clk";
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NET "*ETHERNET*/AXI_STR_TXC_ACLK" TNM_NET = "axistream_clk";
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NET "*ETHERNET*/AXI_STR_RXD_ACLK" TNM_NET = "axistream_clk";
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NET "*ETHERNET*/AXI_STR_RXS_ACLK" TNM_NET = "axistream_clk";
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############################################################
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# Clock Period Constraints #
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############################################################
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############################################################
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# RX Clock period Constraints #
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############################################################
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# Ethernet GMII PHY-side receive clock
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# __________
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# | |
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# --- GMII_RX_CLK-----| BUFR |---Rx_Client_Clk
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# |__________|
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#
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# Receiver clock period constraints: please do not relax
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# Changed NET name
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# Changed TNM_NET name from CoreGen name to be consistent in
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# EDK constraints
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# NET "*/rx_gmii_clk_int" TNM_NET = "clk_rx";
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NET "*/GMII_RX_CLK" TNM_NET = "phy_clk_rx";
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# Added TIMEGRP for later DATAPATHONLY constraint
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TIMEGRP "rx_clock" = "phy_clk_rx";
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TIMESPEC "TS_rx_clk" = PERIOD "rx_clock" 8000 ps HIGH 50 %;
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############################################################
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# TX Clock period Constraints #
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############################################################
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############################################################
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# TIG for BUFGMUX SPEED CLK: please do not edit #
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############################################################
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# Want to TIG any timing paths to the select of the TX clock BUFGMUXs
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# at this point and subsequent constraints can override. MII_TX_CLK
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# will remained TIG so that path is not used in any setup/hold timing
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# analysis.
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# Changed net name in synthesis of axi_ethernet
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# PIN "*clock_inst*BUFGMUX*.I?" TNM="clk_bufgmux";
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PIN "*I_CLOCK_INST*/*BUFGMUX_SPEED_CLK.I?" TNM="clk_bufgmux";
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TIMESPEC "TS_bufgmux" = FROM "async_config" TO "clk_bufgmux" TIG;
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###############################################################################
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# The following two TimeSpecs are from CoreGen Ethernet Core Example Design UCF
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# file. In systems GTX_CLK is driven by clock generator core, then the derived
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# period constraint will override these TimeSpecs.
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###############################################################################
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# Ethernet GTX_CLK high quality 125 MHz reference clock
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# __________
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# -GTX_CLK------------| |
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# | BUFGMUX |---Tx_Client_Clk
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# -MII_TX_CLK---------|__________|
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#
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# Depending on system configuration, the analysis tool may use either gtx_clk
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# or tx_client_clk so both nets are used in defining PERIOD constraint and
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# TNM_NETS for subsequent constraints.
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# The PERIOD constraints may not be analyzed if inferred clock generator
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# constraints are generated for the system.
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# Transmitter clock period constraints: please do not relax
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# Changed NET name
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# NET "gtx_clk*" TNM_NET = "clk_gtx";
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NET "*/GTX_CLK" TNM_NET = "clk_gtx";
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# Added TIMEGRP for later DATAPATHONLY constraint
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TIMEGRP "gtx_clock" = "clk_gtx";
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TIMESPEC "TS_gtx_clk" = PERIOD "gtx_clock" 8000 ps HIGH 50 %;
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# Changed NET name
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# Changed TNM_NET name from CoreGen name to be consistent in
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# EDK constraints
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# NET "*tx_gmii_clk" TNM_NET = "clk_tx_gmii";
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NET "*/GMII.tx_gmii_clk_int" TNM_NET = "phy_clk_tx";
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TIMEGRP "tx_clock_gmii" = "phy_clk_tx";
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TIMESPEC "TS_tx_clk_gmii" = PERIOD "tx_clock_gmii" 8000 ps HIGH 50 %;
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############################################################
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# Host Clock period Constraint #
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############################################################
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# Management Clock period constraints: relax as required
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# Changed NET name
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# NET "host_clk" TNM_NET = "host";
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NET "*/S_AXI_ACLK" TNM_NET = "host_clk";
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TIMEGRP "host" = "host_clk" EXCEPT "mdio_logic";
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TIMESPEC "TS_host_clk" = PERIOD "host" 10000 ps HIGH 50 % PRIORITY 10;
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############################################################
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# External GMII Constraints #
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############################################################
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# GMII Transmitter Constraints: place flip-flops in IOB
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# Changed 'true' to 'force'
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# Shortened INST names to remove internal hierarchy
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# INST "*trimac_block*gmii_interface*gmii_txd*" IOB = true;
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# INST "*trimac_block*gmii_interface*gmii_tx_en" IOB = true;
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# INST "*trimac_block*gmii_interface*gmii_tx_er" IOB = true;
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INST "*gmii_txd*" IOB = force;
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INST "*gmii_tx_en" IOB = force;
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INST "*gmii_tx_er" IOB = force;
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# GMII Receiver Constraints: place flip-flops in IOB
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# Changed 'true' to 'force'
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# Shortened INST names to remove internal hierarchy
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# INST "*trimac_block*gmii_interface*rxd_to_mac*" IOB = true;
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# INST "*trimac_block*gmii_interface*rx_dv_to_mac" IOB = true;
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# INST "*trimac_block*gmii_interface*rx_er_to_mac" IOB = true;
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INST "*rxd_to_mac*" IOB = force;
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INST "*rx_dv_to_mac" IOB = force;
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INST "*rx_er_to_mac" IOB = force;
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############################################################
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# The following are required to maximize setup/hold #
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############################################################
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# Changed to add Drive strength and INST Name
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# INST "gmii_txd<?>" SLEW = FAST;
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# INST "gmii_tx_en" SLEW = FAST;
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# INST "gmii_tx_er" SLEW = FAST;
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# INST "gmii_tx_clk" SLEW = FAST;
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INST "ETHERNET_TXD_?_OBUF" SLEW = FAST;
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INST "ETHERNET_TX_EN_OBUF" SLEW = FAST;
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INST "ETHERNET_TX_ER_OBUF" SLEW = FAST;
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INST "ETHERNET_TX_CLK_OBUF" SLEW = FAST;
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############################################################
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# GMII: IODELAY Constraints #
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############################################################
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# Please modify the value of the IDELAY_VALUE
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# according to your design.
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# For more information on IDELAYCTRL and IODELAY, please
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# refer to the Spartan-6 User Guide.
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#
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INST "*delay_gmii_rx_dv" IDELAY_VALUE = 6;
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INST "*delay_gmii_rx_er" IDELAY_VALUE = 6;
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INST "*data_bus[0].delay_gmii_rxd" IDELAY_VALUE = 6;
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INST "*data_bus[1].delay_gmii_rxd" IDELAY_VALUE = 6;
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INST "*data_bus[2].delay_gmii_rxd" IDELAY_VALUE = 6;
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INST "*data_bus[3].delay_gmii_rxd" IDELAY_VALUE = 6;
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INST "*data_bus[4].delay_gmii_rxd" IDELAY_VALUE = 6;
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INST "*data_bus[5].delay_gmii_rxd" IDELAY_VALUE = 6;
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INST "*data_bus[6].delay_gmii_rxd" IDELAY_VALUE = 6;
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INST "*data_bus[7].delay_gmii_rxd" IDELAY_VALUE = 6;
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# Group IODELAY and IDELAYCTRL components to aid placement
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# INST "*delay_gmii_rx_clk" IODELAY_GROUP = "grp1";
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INST "*delay_gmii_rx_dv" IODELAY_GROUP = "grp1";
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INST "*delay_gmii_rx_er" IODELAY_GROUP = "grp1";
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INST "*delay_gmii_rxd" IODELAY_GROUP = "grp1";
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# INST "*dlyctrl" IODELAY_GROUP = "grp1";
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# Changed to let the tools pick the LOC
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# INST *trimac_block*clock_inst*BUFGMUX_SPEED_CLK LOC = BUFGMUX_X3Y13;
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############################################################
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# For Setup and Hold time analysis on GMII inputs #
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############################################################
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# Identify GMII Rx Pads only.
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# This prevents setup/hold analysis being performed on false inputs,
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# eg, the configuration_vector inputs.
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# Changed to remove TNM and changed INST Names
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# INST "gmii_rxd<?>" TNM = IN_GMII;
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# INST "gmii_rx_er" TNM = IN_GMII;
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# INST "gmii_rx_dv" TNM = IN_GMII;
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# Define data valid window with respect to the clock.
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# The spec states that, worst case, the data is valid 2 ns before the clock edge.
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# The worst case it to provide zero hold time (a 2ns window in total)
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# Changed to remove TIMEGRP
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# TIMEGRP "IN_GMII" OFFSET = IN 2 ns VALID 2 ns BEFORE "gmii_rx_clk";
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# Set to allow for 100ps setup/hold trace delay difference in relation to clock
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OFFSET = IN 2.4 ns VALID 2.8 ns BEFORE "ETHERNET_RX_CLK";
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############################################################
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# Crossing of Clock Domain Constraints: please do not edit #
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############################################################
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# Flow Control logic reclocking - control signal is synchronised
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# Changed net name in synthesis of axi_ethernet
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# INST "*trimac_core*FLOW?RX_PAUSE?PAUSE_REQ_TO_TX" TNM="flow_rx_to_tx";
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# INST "*trimac_core*FLOW?RX_PAUSE?PAUSE_VALUE_TO_TX*" TNM="flow_rx_to_tx";
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INST "*/I_FLOW/I_RX_PAUSE/PAUSE_REQ_TO_TX" TNM="flow_rx_to_tx";
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INST "*/I_FLOW/I_RX_PAUSE/PAUSE_VALUE_TO_TX*" TNM="flow_rx_to_tx";
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TIMESPEC "TS_flow_rx_to_tx" = FROM "flow_rx_to_tx" TO phy_clk_tx 8000 ps DATAPATHONLY;
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# Generate a group of all flops NOT in the host clock domain
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TIMEGRP "all_ffs" = FFS;
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TIMEGRP "ffs_except_host" = "all_ffs" EXCEPT "host";
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# Configuration Register reclocking
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# Changed net name in synthesis of axi_ethernet
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# INST "*trimac_core*MANIFGEN?MANAGEN?CONF?RX0_OUT*" TNM="async_config";
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# INST "*trimac_core*MANIFGEN?MANAGEN?CONF?RX1_OUT*" TNM="async_config";
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# INST "*trimac_core*MANIFGEN?MANAGEN?CONF?FC_OUT_29" TNM="async_config";
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INST "*/MANIFGEN.I_MANAGEN/I_CONF/RX0_OUT*" TNM="async_config";
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INST "*/MANIFGEN.I_MANAGEN/I_CONF/RX1_OUT*" TNM="async_config";
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INST "*/MANIFGEN.I_MANAGEN/I_CONF/FC_OUT_29" TNM="async_config";
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# INST "*trimac_core*MANIFGEN?MANAGEN?CONF?TX_OUT*" TNM="async_config";
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# INST "*trimac_core*MANIFGEN?MANAGEN?CONF?FC_OUT_30" TNM="async_config";
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INST "*/MANIFGEN.I_MANAGEN/I_CONF/TX_OUT*" TNM="async_config";
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INST "*/MANIFGEN.I_MANAGEN/I_CONF/FC_OUT_30" TNM="async_config";
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# Speed change config
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# Changed net name in synthesis of axi_ethernet
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# INST "*trimac_core*MANIFGEN?MANAGEN?CONF?CNFG_SPEED*" TNM="async_config";
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# INST "*trimac_core*SPEED_IS*" TNM="async_config";
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INST "*/MANIFGEN.I_MANAGEN/I_CONF/CNFG_SPEED*" TNM="async_config";
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INST "*/I_?XGEN/*SPEED*" TNM="async_config";
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# Changed to comment out.
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# In BSB systems the Host_clk = S_AXI_ACLK. Since the CORE Gen TIG'd constraints below
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# are affecting axi_ethernet DATAPATHONLY constraints above (at start of Soft_Ethernet_MAC constraints)
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# these paths are commented out in favor of using the DATAPATHONLY constraints. The constraints are:
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# "TS_axi4lite_clk_clk_2_TX_CLIENT_CLK" and "TS_TX_CLIENT_CLK_2_axi4lite_clk_clk"
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# TIMESPEC "TS_host_clk_to_rx_clk" = FROM "host" TO "rx_clock" TIG;
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# TIMESPEC "TS_host_clk_to_tx_clk" = FROM "host" TO "tx_clock_gmii" TIG;
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TIMESPEC "TS_config_to_all" = FROM "async_config" TO "ffs_except_host" TIG;
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# Address filter specific cross clocking
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# Changed net name in synthesis of axi_ethernet
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# INST "*trimac_core*addr_filter_top/dynamic_af_gen.dynamic_config/unicast_addr_*" TNM="addr_config_to_rx";
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INST "*/I_ADDR_FILTER_TOP/dynamic_af_gen.I_DYNAMIC_CONFIG/unicast_addr_*" TNM="addr_config_to_rx";
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TIMESPEC "TS_addr_config_to_rx" = FROM "addr_config_to_rx" TO "ffs_except_host" TIG;
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############################################################
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# Ignore paths to resync flops #
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############################################################
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# Changed to replace TIG with DATAPATHONLY constraints
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# INST "*data_sync" TNM = "resync_reg";
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# TIMESPEC "ts_resync_flops" = TO "resync_reg" TIG;
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######################################################################
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# MDIO Constraints: please do not edit unless TS_host_clk is relaxed #
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# in which case the multiplier needs to be adjusted to give the #
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# required 400ns (or faster) #
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######################################################################
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# Place the MDIO logic in it's own timing groups
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# Changed net name in synthesis of axi_ethernet
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# INST "*trimac_core*MANIFGEN?MANAGEN?PHY?ENABLE_REG" TNM = "mdio_logic";
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# INST "*trimac_core*MANIFGEN?MANAGEN?PHY?READY_INT" TNM = "mdio_logic";
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# INST "*trimac_core*MANIFGEN?MANAGEN?PHY?STATE_COUNT*" TNM = FFS "mdio_logic";
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# INST "*trimac_core*MANIFGEN?MANAGEN?PHY?MDIO_TRISTATE" TNM = "mdio_logic";
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# INST "*trimac_core*MANIFGEN?MANAGEN?PHY?MDIO_OUT" TNM = "mdio_logic";
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INST "*/I_RXGEN/ENABLE_REG" TNM = "mdio_logic";
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INST "*/MANIFGEN.I_MANAGEN/MIIM_READY_INT" TNM = "mdio_logic";
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INST "*/MANIFGEN.I_MANAGEN/I_PHY/STATE_COUNT*" TNM = FFS "mdio_logic";
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INST "*/MANIFGEN.I_MANAGEN/I_PHY/MDIO_TRISTATE" TNM = "mdio_logic";
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INST "*/MANIFGEN.I_MANAGEN/I_PHY/MDIO_OUT" TNM = "mdio_logic";
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# The MDIO logic is constrained to a 400ns period. this is generated by relating the required
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# period to that specified for host_clk. This ensures the two clocks are related timed
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# correctly.
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TIMESPEC "TS_mdio" = PERIOD "mdio_logic" "TS_host_clk" * 40 PRIORITY 0;
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############################################################
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# Crossing of Clock Domain Constraints: please do not edit #
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# In addition to CoreGen constraints #
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############################################################
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# The following TimeSpecs are required only when AXILite clock differs from AXI-Stream clock
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# Data path timing depends on the destination clock period
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TIMESPEC "TS_axistreamclks_2_axi4liteclks" = FROM axistream_clk TO axi4lite_clk 20000 ps DATAPATHONLY; #assumes axi4lite_clk <= 50 MHz
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TIMESPEC "TS_axi4liteclks_2_axistreamclks" = FROM axi4lite_clk TO axistream_clk 8333 ps DATAPATHONLY; #assumes axistream_clk <= 120 MHz
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# TNM_NET phy_clk_rx is rx_client_clk
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# TIMESPECs for AXI streaming clock crossing to/from rx_client_clk
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TIMESPEC "TS_axistreamclks_2_RX_CLIENT_CLK" = FROM axistream_clk TO phy_clk_rx 8000 ps DATAPATHONLY; #assumes phy_clk_rx <= 125 MHz
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TIMESPEC "TS_RX_CLIENT_CLK_2_axistreamclks" = FROM phy_clk_rx TO axistream_clk 8333 ps DATAPATHONLY; #assumes axistream_clk <= 120 MHz
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# TIMESPECs for AXI-Lite clock crossing to/from tx_client_clk
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TIMESPEC "TS_axi4liteclks_2_RX_CLIENT_CLK" = FROM axi4lite_clk TO phy_clk_rx 8000 ps DATAPATHONLY; #assumes phy_clk_rx <= 125 MHz
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TIMESPEC "TS_RX_CLIENT_CLK_2_axi4liteclks" = FROM phy_clk_rx TO axi4lite_clk 20000 ps DATAPATHONLY; #assumes axi4lite_clk <= 50 MHz
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# Depending on system configuration, the analysis tool may use either TNM_NET clk_gtx
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# or TNM_NET phy_clk_tx so only one set will be analyzed
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# TNM_NET phy_clk_tx is tx_client_clk
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# TIMESPECs for AXI streaming clock crossing to/from tx_client_clk
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TIMESPEC "TS_axistreamclks_2_TX_CLIENT_CLK" = FROM axistream_clk TO phy_clk_tx 8000 ps DATAPATHONLY; #assumes phy_clk_tx <= 125 MHz
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TIMESPEC "TS_TX_CLIENT_CLK_2_axistreamclks" = FROM phy_clk_tx TO axistream_clk 8333 ps DATAPATHONLY; #assumes axistream_clk <= 120 MHz
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# TIMESPECs for AXI-Lite clock crossing to/from tx_client_clk
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TIMESPEC "TS_axi4liteclks_2_TX_CLIENT_CLK" = FROM axi4lite_clk TO phy_clk_tx 8000 ps DATAPATHONLY; #assumes phy_clk_tx <= 125 MHz
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TIMESPEC "TS_TX_CLIENT_CLK_2_axi4liteclks" = FROM phy_clk_tx TO axi4lite_clk 20000 ps DATAPATHONLY; #assumes axi4lite_clk <= 50 MHz
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# TNM_NET clk_gtx is */GTX_CLK
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# TIMESPECs for AXI Streaming clock crossing to/from */GTX_CLK
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TIMESPEC "TS_axistreamclks_2_GTX_CLK" = FROM axistream_clk TO clk_gtx 8000 ps DATAPATHONLY; #assumes clk_gtx <= 125 MHz
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TIMESPEC "TS_GTX_CLK_2_axistreamclks" = FROM clk_gtx TO axistream_clk 8333 ps DATAPATHONLY; #assumes axistream_clk <= 120 MHz
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# TIMESPECs for AXI-Lite clock crossing to/from */GTX_CLK
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TIMESPEC "TS_axi4lite_clk_2_GTX_CLK" = FROM axi4lite_clk TO clk_gtx 8000 ps DATAPATHONLY; #assumes clk_gtx <= 125 MHz
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TIMESPEC "TS_GTX_CLK_2_axi4lite_clk" = FROM clk_gtx TO axi4lite_clk 20000 ps DATAPATHONLY; #assumes axi4lite_clk <= 50 MHz
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# Depending on system configuration, the analysis tool may use either TNM_NET clk_gtx
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# or TNM_NET phy_clk_tx so only one set will be analyzed
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# Rx Clock crossings - Some paths are analyzed by the TS_flow_rx_to_tx constraint also
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# Needed since ts_resync_flops is commented out
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TIMESPEC "TS_RX_CLIENT_CLK_2_TX_CLIENT_CLK" = FROM phy_clk_rx TO phy_clk_tx 8000 ps DATAPATHONLY; #assumes phy_clk_tx <= 125 MHz
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TIMESPEC "TS_TX_CLIENT_CLK_2_RX_CLIENT_CLK" = FROM phy_clk_tx TO phy_clk_rx 8000 ps DATAPATHONLY; #assumes phy_clk_rx <= 125 MHz
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TIMESPEC "TS_RX_CLIENT_CLK_2_GTX_CLK" = FROM phy_clk_rx TO clk_gtx 8000 ps DATAPATHONLY; #assumes phy_clk_tx <= 125 MHz
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TIMESPEC "TS_GTX_CLK_2_RX_CLIENT_CLK" = FROM clk_gtx TO phy_clk_rx 8000 ps DATAPATHONLY; #assumes phy_clk_rx <= 125 MHz
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