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341 lines
11 KiB
C
341 lines
11 KiB
C
/*
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FreeRTOS.org V4.1.1 - copyright (C) 2003-2006 Richard Barry.
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This file is part of the FreeRTOS.org distribution.
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FreeRTOS.org is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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FreeRTOS.org is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with FreeRTOS.org; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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A special exception to the GPL can be applied should you wish to distribute
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a combined work that includes FreeRTOS.org, without being obliged to provide
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the source code for any proprietary components. See the licensing section
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of http://www.FreeRTOS.org for full details of how and when the exception
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can be applied.
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***************************************************************************
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See http://www.FreeRTOS.org for documentation, latest information, license
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and contact details. Please ensure to read the configuration and relevant
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port sections of the online documentation.
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***************************************************************************
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*/
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/* Standard includes. */
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#include <stdlib.h>
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/* Scheduler include files. */
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#include "FreeRTOS.h"
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#include "task.h"
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#include "queue.h"
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#include "semphr.h"
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/* Application includes. */
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#include "i2c.h"
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/*-----------------------------------------------------------*/
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/* Bit definitions within the I2CONCLR register. */
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#define i2cSTA_BIT ( ( unsigned portCHAR ) 0x20 )
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#define i2cSI_BIT ( ( unsigned portCHAR ) 0x08 )
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#define i2cSTO_BIT ( ( unsigned portCHAR ) 0x10 )
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#define i2cAA_BIT ( ( unsigned portCHAR ) 0x04 )
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/* Status codes for the I2STAT register. */
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#define i2cSTATUS_START_TXED ( 0x08 )
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#define i2cSTATUS_REP_START_TXED ( 0x10 )
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#define i2cSTATUS_TX_ADDR_ACKED ( 0x18 )
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#define i2cSTATUS_DATA_TXED ( 0x28 )
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#define i2cSTATUS_RX_ADDR_ACKED ( 0x40 )
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#define i2cSTATUS_DATA_RXED ( 0x50 )
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#define i2cSTATUS_LAST_BYTE_RXED ( 0x58 )
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/* Constants for operation of the VIC. */
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#define i2cCLEAR_VIC_INTERRUPT ( 0 )
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/* Misc constants. */
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#define i2cJUST_ONE_BYTE_TO_RX ( 1 )
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#define i2cBUFFER_ADDRESS_BYTES ( 2 )
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/* End the current transmission and free the bus. */
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#define i2cEND_TRANSMISSION( lStatus ) \
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{ \
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I2C_I2CONCLR = i2cAA_BIT; \
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I2C_I2CONSET = i2cSTO_BIT; \
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eCurrentState = eSentStart; \
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lTransactionCompleted = lStatus; \
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}
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/*-----------------------------------------------------------*/
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/* Valid i2c communication states. */
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typedef enum
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{
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eSentStart, /*<< Last action was the transmission of a start bit. */
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eSentAddressForWrite, /*<< Last action was the transmission of the slave address we are to write to. */
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eSentAddressForRead, /*<< Last action was the transmission of the slave address we are to read from. */
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eSentData, /*<< Last action was the transmission of a data byte. */
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eReceiveData /*<< We expected data to be received. */
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} I2C_STATE;
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/*-----------------------------------------------------------*/
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/* Points to the message currently being sent. */
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volatile xI2CMessage *pxCurrentMessage = NULL;
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/* The queue of messages waiting to be transmitted. */
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static xQueueHandle xMessagesForTx;
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/* Flag used to indicate whether or not the ISR is amid sending a message. */
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unsigned portLONG ulBusFree = ( unsigned portLONG ) pdTRUE;
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/* Setting this to true will cause the TCP task to think a message is
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complete and thus restart. It can therefore be used under error states
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to force a restart. */
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volatile portLONG lTransactionCompleted = pdTRUE;
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/*-----------------------------------------------------------*/
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void vI2CISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxTxMessages, unsigned portLONG **ppulBusFree )
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{
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/* Create the queues used to hold Rx and Tx characters. */
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xMessagesForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( xI2CMessage * ) );
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/* Pass back a reference to the queue and bus free flag so the I2C API file
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can post messages. */
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*pxTxMessages = xMessagesForTx;
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*ppulBusFree = &ulBusFree;
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}
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/*-----------------------------------------------------------*/
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void vI2C_ISR( void ) __attribute__ (( naked ));
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void vI2C_ISR( void )
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{
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portENTER_SWITCHING_ISR();
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/* Holds the current transmission state. */
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static I2C_STATE eCurrentState = eSentStart;
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static portLONG lMessageIndex = -i2cBUFFER_ADDRESS_BYTES; /* There are two address bytes to send prior to the data. */
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portBASE_TYPE xTaskWokenByTx = pdFALSE;
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portLONG lBytesLeft;
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/* The action taken for this interrupt depends on our current state. */
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switch( eCurrentState )
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{
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case eSentStart :
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/* We sent a start bit, if it was successful we can
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go on to send the slave address. */
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if( ( I2C_I2STAT == i2cSTATUS_START_TXED ) || ( I2C_I2STAT == i2cSTATUS_REP_START_TXED ) )
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{
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/* Send the slave address. */
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I2C_I2DAT = pxCurrentMessage->ucSlaveAddress;
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if( pxCurrentMessage->ucSlaveAddress & i2cREAD )
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{
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/* We are then going to read bytes back from the
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slave. */
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eCurrentState = eSentAddressForRead;
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/* Initialise the buffer index so the first byte goes
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into the first buffer position. */
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lMessageIndex = 0;
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}
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else
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{
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/* We are then going to write some data to the slave. */
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eCurrentState = eSentAddressForWrite;
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/* When writing bytes we first have to send the two
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byte buffer address so lMessageIndex is set negative,
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when it reaches 0 it is time to send the actual data. */
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lMessageIndex = -i2cBUFFER_ADDRESS_BYTES;
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}
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}
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else
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{
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/* Could not send the start bit so give up. */
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i2cEND_TRANSMISSION( pdFAIL );
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}
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I2C_I2CONCLR = i2cSTA_BIT;
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break;
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case eSentAddressForWrite :
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/* We sent the address of the slave we are going to write to.
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If this was acknowledged we can go on to send the data. */
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if( I2C_I2STAT == i2cSTATUS_TX_ADDR_ACKED )
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{
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/* Start the first byte transmitting which is the
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first byte of the buffer address to which the data will
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be sent. */
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I2C_I2DAT = pxCurrentMessage->ucBufferAddressHighByte;
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eCurrentState = eSentData;
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}
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else
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{
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/* Address was not acknowledged so give up. */
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i2cEND_TRANSMISSION( pdFAIL );
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}
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break;
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case eSentAddressForRead :
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/* We sent the address of the slave we are going to read from.
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If this was acknowledged we can go on to read the data. */
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if( I2C_I2STAT == i2cSTATUS_RX_ADDR_ACKED )
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{
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eCurrentState = eReceiveData;
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if( pxCurrentMessage->lMessageLength > i2cJUST_ONE_BYTE_TO_RX )
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{
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/* Don't ack the last byte of the message. */
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I2C_I2CONSET = i2cAA_BIT;
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}
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}
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else
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{
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/* Something unexpected happened - give up. */
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i2cEND_TRANSMISSION( pdFAIL );
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}
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break;
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case eReceiveData :
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/* We have just received a byte from the slave. */
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if( ( I2C_I2STAT == i2cSTATUS_DATA_RXED ) || ( I2C_I2STAT == i2cSTATUS_LAST_BYTE_RXED ) )
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{
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/* Buffer the byte just received then increment the index
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so it points to the next free space. */
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pxCurrentMessage->pucBuffer[ lMessageIndex ] = I2C_I2DAT;
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lMessageIndex++;
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/* How many more bytes are we expecting to receive? */
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lBytesLeft = pxCurrentMessage->lMessageLength - lMessageIndex;
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if( lBytesLeft == ( unsigned portLONG ) 0 )
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{
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/* This was the last byte in the message. */
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i2cEND_TRANSMISSION( pdPASS );
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/* If xMessageCompleteSemaphore is not null then there
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is a task waiting for this message to complete and we
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must 'give' the semaphore so the task is woken.*/
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if( pxCurrentMessage->xMessageCompleteSemaphore )
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{
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xTaskWokenByTx = xSemaphoreGiveFromISR( pxCurrentMessage->xMessageCompleteSemaphore, xTaskWokenByTx );
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}
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/* Are there any other messages to transact? */
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if( xQueueReceiveFromISR( xMessagesForTx, &pxCurrentMessage, &xTaskWokenByTx ) == pdTRUE )
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{
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/* Start the next message - which was
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retrieved from the queue. */
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I2C_I2CONSET = i2cSTA_BIT;
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}
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else
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{
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/* No more messages were found to be waiting for
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transaction so the bus is free. */
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ulBusFree = ( unsigned portLONG ) pdTRUE;
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}
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}
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else
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{
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/* There are more bytes to receive but don't ack the
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last byte. */
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if( lBytesLeft <= i2cJUST_ONE_BYTE_TO_RX )
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{
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I2C_I2CONCLR = i2cAA_BIT;
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}
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}
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}
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else
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{
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/* Something unexpected happened - give up. */
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i2cEND_TRANSMISSION( pdFAIL );
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}
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break;
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case eSentData :
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/* We sent a data byte, if successful send the next byte in
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the message. */
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if( I2C_I2STAT == i2cSTATUS_DATA_TXED )
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{
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/* Index to the next byte to send. */
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lMessageIndex++;
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if( lMessageIndex < 0 )
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{
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/* lMessage index is still negative so we have so far
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only sent the first byte of the buffer address. Send
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the second byte now, then initialise the buffer index
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to zero so the next byte sent comes from the actual
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data buffer. */
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I2C_I2DAT = pxCurrentMessage->ucBufferAddressLowByte;
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}
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else if( lMessageIndex < pxCurrentMessage->lMessageLength )
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{
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/* Simply send the next byte in the tx buffer. */
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I2C_I2DAT = pxCurrentMessage->pucBuffer[ lMessageIndex ];
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}
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else
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{
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/* No more bytes in this message to be send. Finished
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sending message - send a stop bit. */
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i2cEND_TRANSMISSION( pdPASS );
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/* If xMessageCompleteSemaphore is not null then there
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is a task waiting for this message to be sent and the
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semaphore must be 'given' to wake the task. */
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if( pxCurrentMessage->xMessageCompleteSemaphore )
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{
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xTaskWokenByTx = xSemaphoreGiveFromISR( pxCurrentMessage->xMessageCompleteSemaphore, xTaskWokenByTx );
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}
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/* Are there any other messages to transact? */
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if( xQueueReceiveFromISR( xMessagesForTx, &pxCurrentMessage, &xTaskWokenByTx ) == pdTRUE )
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{
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/* Start the next message from the Tx queue. */
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I2C_I2CONSET = i2cSTA_BIT;
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}
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else
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{
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/* No more message were queues for transaction so
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the bus is free. */
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ulBusFree = ( unsigned portLONG ) pdTRUE;
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}
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}
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}
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else
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{
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/* Something unexpected happened, give up. */
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i2cEND_TRANSMISSION( pdFAIL );
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}
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break;
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default :
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/* Should never get here. */
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eCurrentState = eSentStart;
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break;
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}
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/* Clear the interrupt. */
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I2C_I2CONCLR = i2cSI_BIT;
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VICVectAddr = i2cCLEAR_VIC_INTERRUPT;
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portEXIT_SWITCHING_ISR( ( xTaskWokenByTx ) );
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}
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/*-----------------------------------------------------------*/
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