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9efca75d1e
* Refactor RISCV port Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> * Changes to make re-factoring work on ESP32-C3 Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> * Remove alignment and place handlers in separate sections Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> * Correct section names This is needed so that the assemblers correctly recognizes functions. Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> * Move mtvec programming to the application Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> * Refactor mtimer udpate code Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> * Move critical nesting to port layer Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> * Respect configTASK_RETURN_ADDRESS Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> * Formatting changes Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> |
3 years ago | |
|---|---|---|
| .. | ||
| Pulpino_Vega_RV32M1RM | 4 years ago | |
| RISCV_MTIME_CLINT_no_extensions | 4 years ago | |
| RISCV_no_extensions | 3 years ago | |
| RV32I_CLINT_no_extensions | 4 years ago | |
| readme.txt | 5 years ago | |
readme.txt
/* * The FreeRTOS kernel's RISC-V port is split between the the code that is * common across all currently supported RISC-V chips (implementations of the * RISC-V ISA), and code that tailors the port to a specific RISC-V chip: * * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that * is common to all currently supported RISC-V chips. There is only one * portASM.S file because the same file is built for all RISC-V target chips. * * + Header files called freertos_risc_v_chip_specific_extensions.h contain the * code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V * chip. There are multiple freertos_risc_v_chip_specific_extensions.h files * as there are multiple RISC-V chip implementations. * * !!!NOTE!!! * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h * HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the * compiler's!) include path. For example, if the chip in use includes a core * local interrupter (CLINT) and does not include any chip specific register * extensions then add the path below to the assembler's include path: * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions * */