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173 lines
6.2 KiB
C
173 lines
6.2 KiB
C
/*
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* FreeRTOS Kernel V10.0.1
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* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* http://www.FreeRTOS.org
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* http://aws.amazon.com/freertos
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*
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* 1 tab == 4 spaces!
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*/
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/*
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BASIC INTERRUPT DRIVEN DRIVER FOR USB.
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This file contains all the usb components that must be compiled
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to ARM mode. The components that can be compiled to either ARM or THUMB
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mode are contained in USB-CDC.c.
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*/
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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#include "queue.h"
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/* Demo application includes. */
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#include "Board.h"
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#include "usb.h"
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#include "USB-CDC.h"
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#define usbINT_CLEAR_MASK (AT91C_UDP_TXCOMP | AT91C_UDP_STALLSENT | AT91C_UDP_RXSETUP | AT91C_UDP_RX_DATA_BK0 | AT91C_UDP_RX_DATA_BK1 )
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/*-----------------------------------------------------------*/
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/* Messages and queue used to communicate between the ISR and the USB task. */
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static xISRStatus xISRMessages[ usbQUEUE_LENGTH + 1 ];
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extern QueueHandle_t xUSBInterruptQueue;
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/*-----------------------------------------------------------*/
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/* The ISR can cause a context switch so is declared naked. */
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void vUSB_ISR_Wrapper( void ) __attribute__ ((naked));
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/* The function that actually performs the ISR work. This must be separate
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from the wrapper function to ensure the correct stack frame gets set up. */
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void vUSB_ISR_Handler( void );
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/*-----------------------------------------------------------*/
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void vUSB_ISR_Handler( void )
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{
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portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
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static volatile unsigned long ulNextMessage = 0;
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xISRStatus *pxMessage;
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unsigned long ulRxBytes;
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unsigned char ucFifoIndex;
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/* Use the next message from the array. */
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pxMessage = &( xISRMessages[ ( ulNextMessage & usbQUEUE_LENGTH ) ] );
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ulNextMessage++;
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/* Save UDP ISR state for task-level processing. */
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pxMessage->ulISR = AT91C_BASE_UDP->UDP_ISR;
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pxMessage->ulCSR0 = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ];
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/* Clear interrupts from ICR. */
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AT91C_BASE_UDP->UDP_ICR = AT91C_BASE_UDP->UDP_IMR | AT91C_UDP_ENDBUSRES;
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/* Process incoming FIFO data. Must set DIR (if needed) and clear RXSETUP
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before exit. */
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/* Read CSR and get incoming byte count. */
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ulRxBytes = ( pxMessage->ulCSR0 >> 16 ) & usbRX_COUNT_MASK;
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/* Receive control transfers on endpoint 0. */
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if( pxMessage->ulCSR0 & ( AT91C_UDP_RXSETUP | AT91C_UDP_RX_DATA_BK0 ) )
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{
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/* Save FIFO data buffer for either a SETUP or DATA stage */
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for( ucFifoIndex = 0; ucFifoIndex < ulRxBytes; ucFifoIndex++ )
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{
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pxMessage->ucFifoData[ ucFifoIndex ] = AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_0 ];
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}
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/* Set direction for data stage. Must be done before RXSETUP is
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cleared. */
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if( ( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_RXSETUP ) )
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{
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if( ulRxBytes && ( pxMessage->ucFifoData[ usbREQUEST_TYPE_INDEX ] & 0x80 ) )
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{
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AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] |= AT91C_UDP_DIR;
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/* Might not be wise in an ISR! */
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while( !(AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_DIR) );
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}
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/* Clear RXSETUP */
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AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] &= ~AT91C_UDP_RXSETUP;
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/* Might not be wise in an ISR! */
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while ( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_RXSETUP );
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}
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else
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{
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/* Clear RX_DATA_BK0 */
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AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] &= ~AT91C_UDP_RX_DATA_BK0;
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/* Might not be wise in an ISR! */
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while ( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_RX_DATA_BK0 );
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}
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}
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/* If we received data on endpoint 1, disable its interrupts until it is
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processed in the main loop */
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if( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] & ( AT91C_UDP_RX_DATA_BK0 | AT91C_UDP_RX_DATA_BK1 ) )
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{
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AT91C_BASE_UDP->UDP_IDR = AT91C_UDP_EPINT1;
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}
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AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] &= ~( AT91C_UDP_TXCOMP | AT91C_UDP_STALLSENT );
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/* Clear interrupts for the other endpoints, retain data flags for endpoint
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1. */
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AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] &= ~( AT91C_UDP_TXCOMP | AT91C_UDP_STALLSENT | AT91C_UDP_RXSETUP );
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AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_2 ] &= ~usbINT_CLEAR_MASK;
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AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_3 ] &= ~usbINT_CLEAR_MASK;
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/* Post ISR data to queue for task-level processing */
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xQueueSendFromISR( xUSBInterruptQueue, &pxMessage, &xHigherPriorityTaskWoken );
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/* Clear AIC to complete ISR processing */
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AT91C_BASE_AIC->AIC_EOICR = 0;
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/* Do a task switch if needed */
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if( xHigherPriorityTaskWoken )
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{
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/* This call will ensure that the unblocked task will be executed
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immediately upon completion of the ISR if it has a priority higher
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than the interrupted task. */
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portYIELD_FROM_ISR();
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}
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}
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/*-----------------------------------------------------------*/
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void vUSB_ISR_Wrapper( void )
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{
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/* Save the context of the interrupted task. */
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portSAVE_CONTEXT();
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/* Call the handler to do the work. This must be a separate
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function to ensure the stack frame is set up correctly. */
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vUSB_ISR_Handler();
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/* Restore the context of whichever task will execute next. */
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portRESTORE_CONTEXT();
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}
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