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293 lines
10 KiB
C
293 lines
10 KiB
C
/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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/* Standard includes. */
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#include <stdlib.h>
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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/* Constants required to setup the initial task context. */
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#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
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#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
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#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
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#define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )
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/* Constants required to setup the tick ISR. */
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#define portENABLE_TIMER ( ( uint8_t ) 0x01 )
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#define portPRESCALE_VALUE 0x00
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#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 )
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#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 )
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/* Constants required to setup the VIC for the tick ISR. */
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#define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 )
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#define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 )
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#define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 )
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/* Constants required to handle interrupts. */
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#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 )
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#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 )
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/*-----------------------------------------------------------*/
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/* The code generated by the Keil compiler does not maintain separate
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* stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
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* use the stack as per other ports. Instead a variable is used to keep
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* track of the critical section nesting. This variable has to be stored
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* as part of the task context and must be initialised to a non zero value. */
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#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
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volatile uint32_t ulCriticalNesting = 9999UL;
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/*-----------------------------------------------------------*/
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/* Setup the timer to generate the tick interrupts. */
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static void prvSetupTimerInterrupt( void );
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/*
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* The scheduler can only be started from ARM mode, so
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* vPortStartFirstSTask() is defined in portISR.c.
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*/
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extern __asm void vPortStartFirstTask( void );
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/*-----------------------------------------------------------*/
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/*
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* See header file for description.
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*/
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StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
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TaskFunction_t pxCode,
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void * pvParameters )
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{
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StackType_t * pxOriginalTOS;
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/* Setup the initial stack of the task. The stack is set exactly as
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* expected by the portRESTORE_CONTEXT() macro.
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*
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* Remember where the top of the (simulated) stack is before we place
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* anything on it. */
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pxOriginalTOS = pxTopOfStack;
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/* To ensure asserts in tasks.c don't fail, although in this case the assert
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* is not really required. */
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pxTopOfStack--;
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/* First on the stack is the return address - which in this case is the
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* start of the task. The offset is added to make the return address appear
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* as it would within an IRQ ISR. */
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*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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pxTopOfStack--;
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/* The last thing onto the stack is the status register, which is set for
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* system mode, with interrupts enabled. */
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*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
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if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL )
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{
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/* We want the task to start in thumb mode. */
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*pxTopOfStack |= portTHUMB_MODE_BIT;
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}
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pxTopOfStack--;
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/* The code generated by the Keil compiler does not maintain separate
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* stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
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* use the stack as per other ports. Instead a variable is used to keep
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* track of the critical section nesting. This variable has to be stored
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* as part of the task context and is initially set to zero. */
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*pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
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return pxTopOfStack;
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}
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/*-----------------------------------------------------------*/
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BaseType_t xPortStartScheduler( void )
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{
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/* Start the timer that generates the tick ISR. */
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prvSetupTimerInterrupt();
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/* Start the first task. This is done from portISR.c as ARM mode must be
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* used. */
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vPortStartFirstTask();
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/* Should not get here! */
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return 0;
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}
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/*-----------------------------------------------------------*/
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void vPortEndScheduler( void )
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{
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/* It is unlikely that the ARM port will require this function as there
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* is nothing to return to. If this is required - stop the tick ISR then
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* return back to main. */
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}
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/*-----------------------------------------------------------*/
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#if configUSE_PREEMPTION == 0
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/*
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* The cooperative scheduler requires a normal IRQ service routine to
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* simply increment the system tick.
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*/
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void vNonPreemptiveTick( void ) __irq;
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void vNonPreemptiveTick( void ) __irq
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{
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/* Increment the tick count - this may make a delaying task ready
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* to run - but a context switch is not performed. */
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xTaskIncrementTick();
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T0IR = portTIMER_MATCH_ISR_BIT; /* Clear the timer event */
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VICVectAddr = portCLEAR_VIC_INTERRUPT; /* Acknowledge the Interrupt */
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}
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#else /* if configUSE_PREEMPTION == 0 */
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/*
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**************************************************************************
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* The preemptive scheduler ISR is written in assembler and can be found
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* in the portASM.s file. This will only get used if portUSE_PREEMPTION
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* is set to 1 in portmacro.h
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**************************************************************************
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*/
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void vPreemptiveTick( void );
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#endif /* if configUSE_PREEMPTION == 0 */
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/*-----------------------------------------------------------*/
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static void prvSetupTimerInterrupt( void )
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{
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uint32_t ulCompareMatch;
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/* A 1ms tick does not require the use of the timer prescale. This is
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* defaulted to zero but can be used if necessary. */
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T0PR = portPRESCALE_VALUE;
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/* Calculate the match value required for our wanted tick rate. */
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ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
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/* Protect against divide by zero. Using an if() statement still results
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* in a warning - hence the #if. */
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#if portPRESCALE_VALUE != 0
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{
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ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
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}
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#endif
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T0MR0 = ulCompareMatch;
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/* Generate tick with timer 0 compare match. */
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T0MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH;
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/* Setup the VIC for the timer. */
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VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT );
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VICIntEnable |= portTIMER_VIC_CHANNEL_BIT;
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/* The ISR installed depends on whether the preemptive or cooperative
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* scheduler is being used. */
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#if configUSE_PREEMPTION == 1
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{
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VICVectAddr0 = ( uint32_t ) vPreemptiveTick;
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}
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#else
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{
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VICVectAddr0 = ( uint32_t ) vNonPreemptiveTick;
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}
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#endif
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VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE;
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/* Start the timer - interrupts are disabled when this function is called
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* so it is okay to do this here. */
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T0TCR = portENABLE_TIMER;
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}
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/*-----------------------------------------------------------*/
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void vPortEnterCritical( void )
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{
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/* Disable interrupts as per portDISABLE_INTERRUPTS(); */
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__disable_irq();
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/* Now that interrupts are disabled, ulCriticalNesting can be accessed
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* directly. Increment ulCriticalNesting to keep a count of how many times
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* portENTER_CRITICAL() has been called. */
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ulCriticalNesting++;
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}
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/*-----------------------------------------------------------*/
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void vPortExitCritical( void )
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{
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if( ulCriticalNesting > portNO_CRITICAL_NESTING )
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{
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/* Decrement the nesting count as we are leaving a critical section. */
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ulCriticalNesting--;
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/* If the nesting level has reached zero then interrupts should be
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* re-enabled. */
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if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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{
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/* Enable interrupts as per portEXIT_CRITICAL(). */
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__enable_irq();
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}
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}
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}
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/*-----------------------------------------------------------*/
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