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447 lines
16 KiB
C
447 lines
16 KiB
C
/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT AND BSD-3-Clause
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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/*This file has been prepared for Doxygen automatic documentation generation.*/
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/*! \file *********************************************************************
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*
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* \brief FreeRTOS port source for AVR32 UC3.
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*
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* - Compiler: IAR EWAVR32
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* - Supported devices: All AVR32 devices can be used.
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* - AppNote:
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*
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* \author Atmel Corporation (Now Microchip):
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* https://www.microchip.com \n
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* Support and FAQ: https://www.microchip.com/support/
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*
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*****************************************************************************/
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/*
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* Copyright (c) 2007, Atmel Corporation All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of ATMEL may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
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* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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/* AVR32 UC3 includes. */
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#include <avr32/io.h>
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#include <intrinsics.h>
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#include "gpio.h"
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#if configDBG
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#include "usart.h"
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#endif
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#if ( configTICK_USE_TC == 1 )
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#include "tc.h"
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#endif
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/* Constants required to setup the task context. */
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#define portINITIAL_SR ( ( StackType_t ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */
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#define portINSTRUCTION_SIZE ( ( StackType_t ) 0 )
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/* Each task maintains its own critical nesting variable. */
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#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
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volatile uint32_t ulCriticalNesting = 9999UL;
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#if ( configTICK_USE_TC == 0 )
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static void prvScheduleNextTick( void );
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#else
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static void prvClearTcInt( void );
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#endif
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/* Setup the timer to generate the tick interrupts. */
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static void prvSetupTimerInterrupt( void );
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/*-----------------------------------------------------------*/
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/*
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* Low-level initialization routine called during startup, before the main
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* function.
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*/
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int __low_level_init( void )
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{
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#if configHEAP_INIT
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#pragma segment = "HEAP"
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BaseType_t * pxMem;
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#endif
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/* Enable exceptions. */
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ENABLE_ALL_EXCEPTIONS();
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/* Initialize interrupt handling. */
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INTC_init_interrupts();
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#if configHEAP_INIT
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{
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/* Initialize the heap used by malloc. */
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for( pxMem = __segment_begin( "HEAP" ); pxMem < ( BaseType_t * ) __segment_end( "HEAP" ); )
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{
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*pxMem++ = 0xA5A5A5A5;
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}
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}
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#endif
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/* Code section present if and only if the debug trace is activated. */
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#if configDBG
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{
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static const gpio_map_t DBG_USART_GPIO_MAP =
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{
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{ configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION },
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{ configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION }
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};
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static const usart_options_t DBG_USART_OPTIONS =
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{
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.baudrate = configDBG_USART_BAUDRATE,
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.charlength = 8,
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.paritytype = USART_NO_PARITY,
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.stopbits = USART_1_STOPBIT,
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.channelmode = USART_NORMAL_CHMODE
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};
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/* Initialize the USART used for the debug trace with the configured parameters. */
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extern volatile avr32_usart_t * volatile stdio_usart_base;
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stdio_usart_base = configDBG_USART;
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gpio_enable_module( DBG_USART_GPIO_MAP,
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sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[ 0 ] ) );
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usart_init_rs232( configDBG_USART, &DBG_USART_OPTIONS, configCPU_CLOCK_HZ );
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}
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#endif /* if configDBG */
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/* Request initialization of data segments. */
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return 1;
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}
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/*-----------------------------------------------------------*/
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/* Added as there is no such function in FreeRTOS. */
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void * pvPortRealloc( void * pv,
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size_t xWantedSize )
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{
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void * pvReturn;
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vTaskSuspendAll();
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{
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pvReturn = realloc( pv, xWantedSize );
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}
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xTaskResumeAll();
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return pvReturn;
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}
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/*-----------------------------------------------------------*/
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/* The cooperative scheduler requires a normal IRQ service routine to
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* simply increment the system tick. */
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/* The preemptive scheduler is defined as "naked" as the full context is saved
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* on entry as part of the context switch. */
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#pragma shadow_registers = full /* Naked. */
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static void vTick( void )
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{
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/* Save the context of the interrupted task. */
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portSAVE_CONTEXT_OS_INT();
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#if ( configTICK_USE_TC == 1 )
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/* Clear the interrupt flag. */
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prvClearTcInt();
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#else
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/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
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* clock cycles from now. */
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prvScheduleNextTick();
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#endif
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/* Because FreeRTOS is not supposed to run with nested interrupts, put all OS
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* calls in a critical section . */
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portENTER_CRITICAL();
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xTaskIncrementTick();
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portEXIT_CRITICAL();
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/* Restore the context of the "elected task". */
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portRESTORE_CONTEXT_OS_INT();
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}
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/*-----------------------------------------------------------*/
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#pragma shadow_registers = full /* Naked. */
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void SCALLYield( void )
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{
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/* Save the context of the interrupted task. */
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portSAVE_CONTEXT_SCALL();
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vTaskSwitchContext();
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portRESTORE_CONTEXT_SCALL();
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}
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/*-----------------------------------------------------------*/
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/* The code generated by the GCC compiler uses the stack in different ways at
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* different optimisation levels. The interrupt flags can therefore not always
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* be saved to the stack. Instead the critical section nesting level is stored
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* in a variable, which is then saved as part of the stack context. */
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#pragma optimize = no_inline
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void vPortEnterCritical( void )
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{
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/* Disable interrupts */
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portDISABLE_INTERRUPTS();
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/* Now that interrupts are disabled, ulCriticalNesting can be accessed
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* directly. Increment ulCriticalNesting to keep a count of how many times
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* portENTER_CRITICAL() has been called. */
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ulCriticalNesting++;
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}
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/*-----------------------------------------------------------*/
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#pragma optimize = no_inline
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void vPortExitCritical( void )
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{
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if( ulCriticalNesting > portNO_CRITICAL_NESTING )
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{
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ulCriticalNesting--;
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if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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{
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/* Enable all interrupt/exception. */
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portENABLE_INTERRUPTS();
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}
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}
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}
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/*-----------------------------------------------------------*/
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/*
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* Initialise the stack of a task to look exactly as if a call to
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* portSAVE_CONTEXT had been called.
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*
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* See header file for description.
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*/
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StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
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TaskFunction_t pxCode,
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void * pvParameters )
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{
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/* Setup the initial stack of the task. The stack is set exactly as
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* expected by the portRESTORE_CONTEXT() macro. */
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/* When the task starts, it will expect to find the function parameter in R12. */
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pxTopOfStack--;
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*pxTopOfStack-- = ( StackType_t ) 0x08080808; /* R8 */
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*pxTopOfStack-- = ( StackType_t ) 0x09090909; /* R9 */
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*pxTopOfStack-- = ( StackType_t ) 0x0A0A0A0A; /* R10 */
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*pxTopOfStack-- = ( StackType_t ) 0x0B0B0B0B; /* R11 */
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*pxTopOfStack-- = ( StackType_t ) pvParameters; /* R12 */
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*pxTopOfStack-- = ( StackType_t ) 0xDEADBEEF; /* R14/LR */
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*pxTopOfStack-- = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */
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*pxTopOfStack-- = ( StackType_t ) portINITIAL_SR; /* SR */
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*pxTopOfStack-- = ( StackType_t ) 0xFF0000FF; /* R0 */
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*pxTopOfStack-- = ( StackType_t ) 0x01010101; /* R1 */
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*pxTopOfStack-- = ( StackType_t ) 0x02020202; /* R2 */
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*pxTopOfStack-- = ( StackType_t ) 0x03030303; /* R3 */
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*pxTopOfStack-- = ( StackType_t ) 0x04040404; /* R4 */
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*pxTopOfStack-- = ( StackType_t ) 0x05050505; /* R5 */
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*pxTopOfStack-- = ( StackType_t ) 0x06060606; /* R6 */
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*pxTopOfStack-- = ( StackType_t ) 0x07070707; /* R7 */
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*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING; /* ulCriticalNesting */
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return pxTopOfStack;
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}
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/*-----------------------------------------------------------*/
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BaseType_t xPortStartScheduler( void )
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{
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/* Start the timer that generates the tick ISR. Interrupts are disabled
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* here already. */
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prvSetupTimerInterrupt();
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/* Start the first task. */
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portRESTORE_CONTEXT();
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/* Should not get here! */
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return 0;
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}
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/*-----------------------------------------------------------*/
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void vPortEndScheduler( void )
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{
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/* It is unlikely that the AVR32 port will require this function as there
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* is nothing to return to. */
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}
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/*-----------------------------------------------------------*/
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/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
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* clock cycles from now. */
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#if ( configTICK_USE_TC == 0 )
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static void prvScheduleFirstTick( void )
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{
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uint32_t lCycles;
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lCycles = Get_system_register( AVR32_COUNT );
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lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
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/* If lCycles ends up to be 0, make it 1 so that the COMPARE and exception */
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/* generation feature does not get disabled. */
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if( 0 == lCycles )
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{
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lCycles++;
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}
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Set_system_register( AVR32_COMPARE, lCycles );
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}
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#pragma optimize = no_inline
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static void prvScheduleNextTick( void )
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{
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uint32_t lCycles, lCount;
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lCycles = Get_system_register( AVR32_COMPARE );
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lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
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/* If lCycles ends up to be 0, make it 1 so that the COMPARE and exception */
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/* generation feature does not get disabled. */
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if( 0 == lCycles )
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{
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lCycles++;
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}
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lCount = Get_system_register( AVR32_COUNT );
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if( lCycles < lCount )
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{ /* We missed a tick, recover for the next. */
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lCycles += ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
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}
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Set_system_register( AVR32_COMPARE, lCycles );
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}
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#else /* if ( configTICK_USE_TC == 0 ) */
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#pragma optimize = no_inline
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static void prvClearTcInt( void )
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{
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AVR32_TC.channel[ configTICK_TC_CHANNEL ].sr;
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}
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#endif /* if ( configTICK_USE_TC == 0 ) */
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/*-----------------------------------------------------------*/
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/* Setup the timer to generate the tick interrupts. */
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static void prvSetupTimerInterrupt( void )
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{
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#if ( configTICK_USE_TC == 1 )
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volatile avr32_tc_t * tc = &AVR32_TC;
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/* Options for waveform generation. */
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tc_waveform_opt_t waveform_opt =
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{
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.channel = configTICK_TC_CHANNEL, /* Channel selection. */
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.bswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOB. */
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.beevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOB. */
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.bcpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOB. */
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.bcpb = TC_EVT_EFFECT_NOOP, /* RB compare effect on TIOB. */
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.aswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOA. */
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.aeevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOA. */
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.acpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOA: toggle. */
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.acpa = TC_EVT_EFFECT_NOOP, /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */
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.wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER, /* Waveform selection: Up mode without automatic trigger on RC compare. */
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.enetrg = FALSE, /* External event trigger enable. */
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.eevt = 0, /* External event selection. */
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.eevtedg = TC_SEL_NO_EDGE, /* External event edge selection. */
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.cpcdis = FALSE, /* Counter disable when RC compare. */
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.cpcstop = FALSE, /* Counter clock stopped with RC compare. */
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.burst = FALSE, /* Burst signal selection. */
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.clki = FALSE, /* Clock inversion. */
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.tcclks = TC_CLOCK_SOURCE_TC2 /* Internal source clock 2. */
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};
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tc_interrupt_t tc_interrupt =
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{
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.etrgs = 0,
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.ldrbs = 0,
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.ldras = 0,
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.cpcs = 1,
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.cpbs = 0,
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.cpas = 0,
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.lovrs = 0,
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.covfs = 0,
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};
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#endif /* if ( configTICK_USE_TC == 1 ) */
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/* Disable all interrupt/exception. */
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portDISABLE_INTERRUPTS();
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/* Register the compare interrupt handler to the interrupt controller and
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* enable the compare interrupt. */
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#if ( configTICK_USE_TC == 1 )
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{
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INTC_register_interrupt( ( __int_handler ) & vTick, configTICK_TC_IRQ, INT0 );
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/* Initialize the timer/counter. */
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tc_init_waveform( tc, &waveform_opt );
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/* Set the compare triggers.
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* Remember TC counter is 16-bits, so counting second is not possible!
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* That's why we configure it to count ms. */
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tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4 ) / configTICK_RATE_HZ );
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tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt );
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/* Start the timer/counter. */
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tc_start( tc, configTICK_TC_CHANNEL );
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}
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#else /* if ( configTICK_USE_TC == 1 ) */
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{
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INTC_register_interrupt( ( __int_handler ) & vTick, AVR32_CORE_COMPARE_IRQ, INT0 );
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prvScheduleFirstTick();
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}
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#endif /* if ( configTICK_USE_TC == 1 ) */
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}
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