AXI Interconnect AXI4 Memory-Mapped Interconnect Family Base Family Number of Slave Slots Number of Master Slots AXI ID Widgth AXI Address Widgth AXI Data Maximum Width Slave AXI Data Width Master AXI Data Width Interconnect Crossbar Data Width AXI Protocol Master AXI Protocol Master AXI Base Address Master AXI High Address Slave AXI Base ID Slave AXI Thread ID Width Slave AXI Is Interconnect Slave AXI ACLK Ratio Slvave AXI Is ACLK ASYNC Master AXI ACLK Ratio Master AXI Is ACLK ASYNC Interconnect Crossbar ACLK Frequency Ratio Slave AXI Supports Write Slave AXI Supports Read Master AXI Supports Write Master AXI Supports Read Propagate USER Signals AWUSER Signal Width ARUSER Signal Width WUSER Signal Width RUSER Signal Width BUSER Signal Width AXI Connectivity Slave AXI Single Thread Master AXI Supports Reordering Master generates narrow bursts Slave accepts narrow bursts Slave AXI Write Acceptance Slave AXI Read Acceptance Master AXI Write Issuing Master AXI Read Issuing Slave AXI ARB Priority Master AXI Secure Master AXI Write FIFO Depth Slave AXI Write FIFO Type Slave AXI Write FIFO Delay Slave AXI Read FIFO Depth Slave AXI Read FIFO Type Slave AXI Read FIFO Delay Master AXI Write FIFO Depth Master AXI Write FIFO Type Master AXI Write FIFO Delay Master AXI Read FIFO Depth Master AXI Read FIFO Type Master AXI Read FIFO Delay Slave AXI AW Register Slave AXI AR Register Slave AXI W Register Slave AXI R Register Slave AXI B Register Master AXI AW Register Master AXI AR Register Master AXI W Register Master AXI R Register Master AXI B Register C_INTERCONNECT_R_REGISTER Interconnect Architecture Use Diagnostic Slave Port Generate Interrupts Check for transaction errors (DECERR) Slave AXI CTRL Protocol Slave AXI CTRL Address Width Slave AXI CTRL Data Width Diagnostic Slave Port Base Address Diagnostic Slave Port High Address Simulation debug AXI Interconnect AXI4 Memory-Mapped Interconnect Family Base Family Number of Slave Slots Number of Master Slots AXI ID Widgth AXI Address Widgth AXI Data Maximum Width Slave AXI Data Width Master AXI Data Width Interconnect Crossbar Data Width AXI Protocol Master AXI Protocol Master AXI Base Address Master AXI High Address Slave AXI Base ID Slave AXI Thread ID Width Slave AXI Is Interconnect Slave AXI ACLK Ratio Slvave AXI Is ACLK ASYNC Master AXI ACLK Ratio Master AXI Is ACLK ASYNC Interconnect Crossbar ACLK Frequency Ratio Slave AXI Supports Write Slave AXI Supports Read Master AXI Supports Write Master AXI Supports Read Propagate USER Signals AWUSER Signal Width ARUSER Signal Width WUSER Signal Width RUSER Signal Width BUSER Signal Width AXI Connectivity Slave AXI Single Thread Master AXI Supports Reordering Master generates narrow bursts Slave accepts narrow bursts Slave AXI Write Acceptance Slave AXI Read Acceptance Master AXI Write Issuing Master AXI Read Issuing Slave AXI ARB Priority Master AXI Secure Master AXI Write FIFO Depth Slave AXI Write FIFO Type Slave AXI Write FIFO Delay Slave AXI Read FIFO Depth Slave AXI Read FIFO Type Slave AXI Read FIFO Delay Master AXI Write FIFO Depth Master AXI Write FIFO Type Master AXI Write FIFO Delay Master AXI Read FIFO Depth Master AXI Read FIFO Type Master AXI Read FIFO Delay Slave AXI AW Register Slave AXI AR Register Slave AXI W Register Slave AXI R Register Slave AXI B Register Master AXI AW Register Master AXI AR Register Master AXI W Register Master AXI R Register Master AXI B Register C_INTERCONNECT_R_REGISTER Interconnect Architecture Use Diagnostic Slave Port Generate Interrupts Check for transaction errors (DECERR) Slave AXI CTRL Protocol Slave AXI CTRL Address Width Slave AXI CTRL Data Width Diagnostic Slave Port Base Address Diagnostic Slave Port High Address Simulation debug MicroBlaze The MicroBlaze 32 bit soft processor Enable Fault Tolerance Support Select implementation to optimize area (with lower instruction throughput) Select Bus Interfaces Select Stream Interfaces Enable Additional Machine Status Register Instructions Enable Pattern Comparator Enable Barrel Shifter Enable Integer Divider Enable Integer Multiplier Enable Floating Point Unit Enable Unaligned Data Exception Enable Illegal Instruction Exception Enable Instruction-side AXI Exception Enable Data-side AXI Exception Enable Instruction-side PLB Exception Enable Data-side PLB Exception Enable Integer Divide Exception Enable Floating Point Unit Exceptions Enable Stream Exception <qt>Enable stack protection</qt> Specifies Processor Version Register Specify USER1 Bits in Processor Version Register Specify USER2 Bits in Processor Version Registers Enable MicroBlaze Debug Module Interface Number of PC Breakpoints Number of Read Address Watchpoints Number of Write Address Watchpoints Sense Interrupt on Edge vs. Level Sense Interrupt on Rising vs. Falling Edge Specify Reset Value for Select MSR Bits <qt>Generate Illegal Instruction Exception for NULL Instruction</qt> Number of Stream Links Enable Additional Stream Instructions I-Cache Base Address I-Cache High Address Enable Instruction Cache Enable I-Cache Writes Size of the I-Cache in Bytes Instruction Cache Line Length Use Cache Links for All I-Cache Memory Accesses Number of I-Cache Victims Number of I-Cache Streams Use Distributed RAM for I-Cache Tags D-Cache Base Address D-Cache High Address Enable Data Cache Enable D-Cache Writes Size of D-Cache in Bytes Data Cache Line Length Use Cache Links for All D-Cache Memory Accesses Enable Write-back Storage Policy Number of D-Cache Victims Use Distributed RAM for D-Cache Tags Memory Management Data Shadow Translation Look-Aside Buffer Size Instruction Shadow Translation Look-Aside Buffer Size Enable Access to Memory Management Special Registers Number of Memory Protection Zones Privileged Instructions Enable Branch Target Cache Branch Target Cache Size Local Memory Bus (LMB) 1.0 'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM' Number of Bus Slaves LMB Address Bus Width LMB Data Bus Width Active High External Reset Local Memory Bus (LMB) 1.0 'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM' Number of Bus Slaves LMB Address Bus Width LMB Data Bus Width Active High External Reset LMB BRAM Controller Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus LMB BRAM Base Address LMB BRAM High Address LMB Address Decode Mask LMB Address Bus Width LMB Data Bus Width Error Correction Code Select Interconnect Fault Inject Registers Correctable Error First Failing Register Uncorrectable Error First Failing Register ECC Status and Control Register ECC On/Off Register ECC On/Off Reset Value Correctable Error Counter Register Width Write Access setting Base Address for PLB Interface High Address for PLB Interface PLB Address Bus Width PLB Data Bus Width PLB Slave Uses P2P Topology Master ID Bus Width of PLB Number of PLB Masters PLB Slave is Capable of Bursts Native Data Bus Width of PLB Slave Frequency of PLB Slave S_AXI_CTRL Clock Frequency S_AXI_CTRL Base Address S_AXI_CTRL High Address S_AXI_CTRL Address Width S_AXI_CTRL Data Width S_AXI_CTRL Protocol LMB BRAM Controller Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus LMB BRAM Base Address LMB BRAM High Address LMB Address Decode Mask LMB Address Bus Width LMB Data Bus Width Error Correction Code Select Interconnect Fault Inject Registers Correctable Error First Failing Register Uncorrectable Error First Failing Register ECC Status and Control Register ECC On/Off Register ECC On/Off Reset Value Correctable Error Counter Register Width Write Access setting Base Address for PLB Interface High Address for PLB Interface PLB Address Bus Width PLB Data Bus Width PLB Slave Uses P2P Topology Master ID Bus Width of PLB Number of PLB Masters PLB Slave is Capable of Bursts Native Data Bus Width of PLB Slave Frequency of PLB Slave S_AXI_CTRL Clock Frequency S_AXI_CTRL Base Address S_AXI_CTRL High Address S_AXI_CTRL Address Width S_AXI_CTRL Data Width S_AXI_CTRL Protocol Block RAM (BRAM) Block The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers. Size of BRAM(s) in Bytes Data Width of Port A and B Address Width of Port A and B Number of Byte Write Enables Device Family Processor System Reset Module Reset management module Device Subfamily Number of Clocks Before Input Change is Recognized On The External Reset Input Number of Clocks Before Input Change is Recognized On The Auxiliary Reset Input External Reset Active High Auxiliary Reset Active High Number of Bus Structure Reset Registered Outputs Number of Peripheral Reset Registered Outputs Number of Active Low Interconnect Reset Registered Outputs Number of Active Low Peripheral Reset Registered Outputs Device Family Clock Generator Clock generator for processor system. Family Device Package Speed Grade Input Clock Frequency (Hz) Required Frequency (Hz) Required Phase Required Group Buffered Variable Phase Required Frequency (Hz) Required Phase Required Group Buffered Variable Phase Required Frequency (Hz) Required Phase Required Group Buffered Varaible Phase Required Frequency (Hz) Required Phase Required Group Buffered Variable Phase Required Frequency (Hz) Required Phase Required Group Buffered Variable Phase Required Frequency (Hz) Required Phase Required Group Buffered Variable Phase Required Frequency (Hz) Required Phase Required Group Buffered Variable Phase Required Frequency (Hz) Required Phase Required Group Buffered Variable Phase Required Frequency (Hz) Required Phase Required Group Buffered Variable Phase Required Frequency (Hz) Required Phase Required Group Buffered Varaible Phase Required Frequency (Hz) Required Phase Required Group Buffered Variable Phase Required Frequency (Hz) Required Phase Required Group Buffered Variable Phase Required Frequency (Hz) Required Phase Required Group Buffered Variable Phase Required Frequency (Hz) Required Phase Required Group Buffered Variable Phase Required Frequency (Hz) Required Phase Required Group Buffered Variable Phase Required Frequency (Hz) Required Phase Required Group Buffered Variable Phase Required Frequency (Hz) Clock Deskew Required Frequency (Hz) Required Phase Required Group Buffered Variable Phase Shift Clock Primitive Feedback Buffer MicroBlaze Debug Module (MDM) Debug module for MicroBlaze Soft Processor. Device Family Specifies the JTAG user-defined register used Specifies the Bus Interface for the JTAG UART Base Address High Address PLB Address Bus Width PLB Data Bus Width PLB Slave Uses P2P Topology Master ID Bus Width of PLB Number of PLB Masters Native Data Bus Width of PLB Slave PLB Slave is Capable of Bursts Number of MicroBlaze debug ports Enable JTAG UART AXI Address Width AXI Data Width AXI4LITE protocal AXI UART (Lite) Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI. Device Family AXI Clock Frequency AXI Base Address AXI High Address AXI Address Width AXI Data Width UART Lite Baud Rate Baud Rate Number of Data Bits in a Serial Frame Data Bits Use Parity Parity Type AXI4LITE protocol Serial Data Out Serial Data In AXI General Purpose IO General Purpose Input/Output (GPIO) core for the AXI bus. Device Family AXI Base Address AXI High Address AXI Address Width AXI Data Width GPIO Data Channel Width GPIO Data Width GPIO2 Data Channel Width Channel 1 is Input Only Channel 2 is Input Only GPIO Supports Interrupts Channel 1 Data Out Default Value Channel 1 Tri-state Default Value Enable Channel 2 Channel 2 Data Out Default Value Channel 2 Tri-state Default Value AXI4LITE protocol GPIO1 Data IO GPIO2 Data IO AXI General Purpose IO General Purpose Input/Output (GPIO) core for the AXI bus. Device Family AXI Base Address AXI High Address AXI Address Width AXI Data Width GPIO Data Channel Width GPIO Data Width GPIO2 Data Channel Width Channel 1 is Input Only Channel 2 is Input Only GPIO Supports Interrupts Channel 1 Data Out Default Value Channel 1 Tri-state Default Value Enable Channel 2 Channel 2 Data Out Default Value Channel 2 Tri-state Default Value AXI4LITE protocol GPIO1 Data IO GPIO2 Data IO AXI S6 Memory Controller(DDR/DDR2/DDR3) Spartan-6 memory controller AXI 10/100 Ethernet MAC Lite 'IEEE Std. 802.3 MII interface MAC with AXI interface, lightweight implementation' AXI protocol selection Device Family Ethernetlite Base Address Ethernetlite High Address AXI System Clock Period AXI Interface Addresses Width AXI Interface Data Width Width of ID Bus on AXI4 Include MII Management Module Include Global Buffers for PHY clocks Include Internal Loopback Duplex Mode Include Second Transmitter Buffer Include Second Receiver Buffer Include PHY I/O Constraints Interconnect write acceptance Interconnect read acceptance Support Narrow Burst on AXI4 Ethernet PHY Management Data Ethernet PHY Management Clock Ethernet Transmit Data Output Ethernet Transmit Enable Ethernet Transmit Clock Input Ethernet Collision Input Ethernet Receive Data Input Ethernet Receive Error Input Ethernet Receive Clock Input Ethernet Carrier Sense Input Ethernet Receive Data Valid Ethernet PHY Reset AXI Timer/Counter Timer counter with AXI interface AXI4LITE protocol Device Family The Width of Counter in Timer Count Width Only One Timer is present TRIG0 Active Level TRIG1 Active Level GEN0 Active Level GEN1 Active Level AXI Base Address AXI High Address AXI Address Width AXI Data Width Capture Trig 0 Capture Trig 1 Generate Out 0 Generate Out 1 Pulse Width Modulation 0 AXI Interrupt Controller intc core attached to the AXI Device Family AXI Base Address AXI High Address AXI Address Width AXI Data Width Number of Interrupt Inputs Type of Interrupt for Each Input Type of Each Edge Senstive Interrupt Type of Each Level Sensitive Interrupt Support IPR Support SIE Support CIE Support IVR IRQ Output Use Level The Sense of IRQ Output AXI4LITE protocol Interrupt Request Output Interrupt Inputs