PowerPC 440 Virtex-5 A wrapper to instantiate the PowerPC 440 Processor Block primitive Unique Processor ID Reset Value for Endian Storage Byte Ordering Reset Value for User Defined Storage Attributes: Tattribute[4:7] Interrupt Mask for Crossbar-related Interrupts Arbitration Priority for all CPU Fetch Requests Arbitration Priority for all Speculative CPU Fetch Requests Arbitration Priority for all CPU Fetch Requests Initiated by ICBT Instructions Arbitration Priority for all CPU Cacheable Load Requests Arbitration Priority for CPU Non-cacheable Load Requests Arbitration Priority for all CPU Load Requests Initiated by DCBT Instructions Arbitration Priority for an Urgent CPU Load Request Arbitration Priority for CPU Write Requests Initiated by flush Instruction Arbitration Priority for CPU Write Requests Initiated by store Instructions Arbitration Priority for an Urgent CPU Write Request Internal DCR Register Base Address Internal DCR Register High Address APU Controller Configuration Register Value UDI Configuration Register 0 Value UDI Configuration Register 1 Value UDI Configuration Register 2 Value UDI Configuration Register 3 Value UDI Configuration Register 4 Value UDI Configuration Register 5 Value UDI Configuration Register 6 Value UDI Configuration Register 7 Value UDI Configuration Register 8 Value UDI Configuration Register 9 Value UDI Configuration Register 10 Value UDI Configuration Register 11 Value UDI Configuration Register 12 Value UDI Configuration Register 13 Value UDI Configuration Register 14 Value UDI Configuration Register 15 Value Base Address of Memory High Address of Memory Mask Used to Determine a Row Conflict Mask Used to Determine a Bank Conflict Control and Configuration for the MC Interface Secondary Arbitration Priority for all Instruction Fetches from CPU Secondary Arbitration Priority for all Data Writes from CPU Secondary Arbitration Priority for all Data Reads from CPU Secondary Arbitration Priority for SPLB1, DMA2 and DMA3 Secondary Arbitration Priority for SPLB0, DMA0 and DMA1 Memory Control Interface Arbitration Mode Max Number of Quad-words per Burst thru Xbar to MC Interface C_MPLB_AWIDTH C_MPLB_DWIDTH C_MPLB_NATIVE_DWIDTH Watchdog Counter Threshold Secondary Arbitration Prio for Instr Fetches Secondary Arbitration Prio for Data Writes Secondary Arbitration Prio for Data Reads Secondary Arbitration Prio for SPLB1, DMA2, DMA3 Secondary Arbitration Prio for SPLB0, DMA0, DMA1 MPLB Arbitration Mode Allow MBusy to Block MPLB Max Num of Quad-words in Bursts Allow Locked Transfer Allow Read Addr Pipelining Allow Write Addr Pipelining Allow Posted Writes C_MPLB_P2P Enable Watchdog Timer C_SPLB0_AWIDTH C_SPLB0_DWIDTH C_SPLB0_NATIVE_DWIDTH SPLB Support Bursts Allow SPLB0 to Access MPLB Addr Number of MPLB Addr Ranges Base Addr High Addr Number of Masters Mid Width SPLB Allow Locked Transfer Enable SPLB Read Pipeline Propagate MIRQ Signals from Xbar onto SPLB Use P2P C_SPLB1_AWIDTH C_SPLB1_DWIDTH C_SPLB1_NATIVE_DWIDTH Allow SPLB1 to Access MPLB Addr Number of MPLB Address Ranges Base Addr High Addr Number of Masters Mid Width Number of DMA Channel DMA 0 DMA 1 DMA 2 DMA 3 Enable the Auto-lock Feature for the DCR Indirect Mode Synchronization Mode for the External MDCR Interface Synchronization Mode for the External SDCR Interface Generate Timing Constraint to Resynchronize SPLB MBusy Outputs JTAG HALT JTAG HALT INV JTAG TCK JTAG TDI JTAG TMS JTAG TRST JTAG TDO Trace Trigger Event In Trace Branch Status Trace Clock Trace Execution Status Trace Status Trace Trigger Event Out Processor Local Bus (PLB) 4.6 'Xilinx 64-bit Processor Local Bus (PLB) consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units with a a three-cycle only arbitration feature' Number of PLB Masters Number of PLB Slaves PLB Master ID Bus Width PLB Address Bus Width PLB Data Bus Width Include DCR Interface and Error Registers Base Address High Address DCR Address Bus Width DCR Data Bus Width External Reset Active High IRQ Active State <qt>Number of PLB Clock Periods a PLB Master that Received a Rearbitrate from an OPB2PLB Bridge on a Read Operation is Denied Grant on the PLB Bus</qt> Enable Address Pipelining Type Device Family Optimize PLB for Point-to-point Topology Selects the Arbitration Scheme XPS BRAM Controller Attaches BRAM to the PLBV46 Base Address High Address Native Data Bus Width of PLB Slave PLB Address Bus Width PLB Data Bus Width Number of PLB Masters Master ID Bus Width of PLB PLB Slave is Capable of Bursts PLB Slave Uses P2P Topology Smallest Master Data Bus Width Device Family Block RAM (BRAM) Block The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers. Size of BRAM(s) in Bytes Data Width of Port A and B Address Width of Port A and B Number of Byte Write Enables Device Family XPS UART (Lite) Generic UART (Universal Asynchronous Receiver/Transmitter) for PLBV46 bus. Device Family Clock Frequency of PLB Slave Base Address High Address PLB Address Bus Width PLB Data Bus Width PLB Slave Uses P2P Topology Master ID Bus Width of PLB Number of PLB Masters PLB Slave is Capable of Bursts Native Data Bus Width of PLB Slave UART Lite Baud Rate Baud Rate Number of Data Bits in a Serial Frame Data Bits Use Parity Parity Type Serial Data In Serial Data Out XPS General Purpose IO General Purpose Input/Output (GPIO) core for the PLBV46 bus. Base Address High Address PLB Address Bus Width PLB Data Bus Width PLB Slave Uses P2P Topology Master ID Bus Width of PLB Number of PLB Masters Native Data Bus Width of PLB Slave PLB Slave is Capable of Bursts Device Family Channel 1 is Input Only Channel 2 is Input Only GPIO Data Channel Width GPIO Data Width GPIO2 Data Channel Width GPIO Supports Interrupts Channel 1 Data Out Default Value Channel 1 Tri-state Default Value Enable Channel 2 Channel 2 Data Out Default Value Channel 2 Tri-state Default Value GPIO1 Data IO GPIO2 Data IO XPS General Purpose IO General Purpose Input/Output (GPIO) core for the PLBV46 bus. Base Address High Address PLB Address Bus Width PLB Data Bus Width PLB Slave Uses P2P Topology Master ID Bus Width of PLB Number of PLB Masters Native Data Bus Width of PLB Slave PLB Slave is Capable of Bursts Device Family Channel 1 is Input Only Channel 2 is Input Only GPIO Data Channel Width GPIO Data Width GPIO2 Data Channel Width GPIO Supports Interrupts Channel 1 Data Out Default Value Channel 1 Tri-state Default Value Enable Channel 2 Channel 2 Data Out Default Value Channel 2 Tri-state Default Value GPIO1 Data IO GPIO2 Data IO XPS General Purpose IO General Purpose Input/Output (GPIO) core for the PLBV46 bus. Base Address High Address PLB Address Bus Width PLB Data Bus Width PLB Slave Uses P2P Topology Master ID Bus Width of PLB Number of PLB Masters Native Data Bus Width of PLB Slave PLB Slave is Capable of Bursts Device Family Channel 1 is Input Only Channel 2 is Input Only GPIO Data Channel Width GPIO Data Width GPIO2 Data Channel Width GPIO Supports Interrupts Channel 1 Data Out Default Value Channel 1 Tri-state Default Value Enable Channel 2 Channel 2 Data Out Default Value Channel 2 Tri-state Default Value GPIO1 Data IO GPIO2 Data IO XPS General Purpose IO General Purpose Input/Output (GPIO) core for the PLBV46 bus. Base Address High Address PLB Address Bus Width PLB Data Bus Width PLB Slave Uses P2P Topology Master ID Bus Width of PLB Number of PLB Masters Native Data Bus Width of PLB Slave PLB Slave is Capable of Bursts Device Family Channel 1 is Input Only Channel 2 is Input Only GPIO Data Channel Width GPIO Data Width GPIO2 Data Channel Width GPIO Supports Interrupts Channel 1 Data Out Default Value Channel 1 Tri-state Default Value Enable Channel 2 Channel 2 Data Out Default Value Channel 2 Tri-state Default Value GPIO1 Data IO GPIO2 Data IO XPS IIC Interface PLBV46 interface to Philips I2C bus v2.1 Output Frequency of SCL Signal Use 10-bit Address Width of GPIO PLBv46 Bus Clock Frequency Width of glitches removed on SCL input Width of glitches removed on SDA input Base Address High Address Master ID Bus Width of PLB Number of PLB Masters PLB Address Bus Width PLB Data Bus Width Native Data Bus Width of PLB Slave Device Family IIC Serial Data IIC Serial Clock IIC General Purpose Output XPS Multi-Channel External Memory Controller(SRAM/Flash) Xilinx Multi-CHannel (MCH) PLBV46 external memory controller Device Family Number of Memory Banks Number of MCH Channels Arbitration Mode Between PLB and MCH Interface Include PLB Slave Interface Include Write Buffer Master ID Bus Width of PLB Number of PLB Masters PLB Slave Uses P2P Topology PLB Data Bus Width MCH and PLB Address Bus Width Smallest Master Data Bus Width Data Bus Width of MCH MCH and PLB Clock Period Base Address of Bank 0 High Address of Bank 0 Base Address of Bank 1 High Address of Bank 1 Base Address of Bank 2 High Address of Bank 2 Base Address of Bank 3 High Address of Bank 3 Page mode flash enable of Bank 0 Page mode flash enable of Bank 1 Page mode flash enable of Bank 2 Page mode flash enable of Bank 3 Use Falling Edge IO Register in Interface Signals Data Bus Width of Bank 0 Data Width Data Bus Width of Bank 1 Data Bus Width of Bank 2 Data Bus Width of Bank 3 Maximum Data Bus Width Maximum Data Width Execute Multiple Memory Accesses To Match Bank 0 Data Bus Width To PLB Data Bus Width Execute Multiple Memory Accesses To Match Bank 1 Data Bus Width To PLB Data Bus Width Execute Multiple Memory Accesses To Match Bank 2 Data Bus Width To PLB Data Bus Width Execute Multiple Memory Accesses To Match Bank 3 Data Bus Width To PLB Data Bus Width Bank 0 is Synchronous Pipeline Latency of Bank 0 TCEDV of Bank 0 TAVDV of Bank 0 TPACC of Bank 0 THZCE of Bank 0 THZOE of Bank 0 TWC of Bank 0 TWP of Bank 0 TLZWE of Bank 0 Bank 1 is Synchronous Pipeline Latency of Bank 1 TCEDV of Bank 1 TAVDV of Bank 1 TPACC of Bank 1 THZCE of Bank 1 THZOE of Bank 1 TWC of Bank 1 TWP of Bank 1 TLZWE of Bank 1 Bank 2 is Synchronous Pipeline Latency of Bank 2 TCEDV of Bank 2 TAVDV of Bank 2 TPACC of Bank 2 THZCE of Bank 2 THZOE of Bank 2 TWC of Bank 2 TWP of Bank 2 TLZWE of Bank 2 Bank 3 is Synchronous Pipeline Latency of Bank 3 TCEDV of Bank 3 TAVDV of Bank 3 TPACC of Bank 3 THZCE of Bank 3 THZOE of Bank 3 TWC of Bank 3 TWP of Bank 3 TLZWE of Bank 3 Interface Protocol of Ch 0 Depth of Access Buffer of Ch 0 Depth of Read Data Buffer Depath of Ch 0 Interface Protocol of Ch 1 Depth of Access Buffer of Ch 1 Depth of Read Data Buffer of Ch 1 Interface Protocol of Ch 2 Depth of Access Buffer of Ch 2 Depth of Read Data Buffer of Ch 2 Interface Protocol of Ch 3 Depth of Access Buffer of Ch 3 Depth of Read Data Buffer of Ch 3 Cacheline Size of Ch0 Write Transfer Type of Ch0 Cacheline Size of Ch1 Write Transfer Type of Ch1 Cacheline Size of Ch2 Write Transfer Type of Ch2 Cacheline Size of Ch3 Write Transfer Type of Ch3 Memory Address Bus Memory Chip Enable Active Low Memory Output Enable Memory Write Enable Memory Byte Enable Memory Advanced Burst Address/Load New Address Memory Data Bus Memory Reset/Power Down Memory Qualified Write Enable Memory Chip Enable Active High Memory Linear/Interleaved Burst Order Memory Clock Enable Memory Read Not Write PLBv46 IP Interface (IPIF) to LogicCORE PCI Express Bridge Bridge between the PLBv46 IPIF and the Xilinx LogiCORE PCI Express Interface core Device Family Number of IPIF devices Include Registers for Each IPIF BAR High-order Bits to be Substituted in Translation. Number of PCI Devices Number of Lanes PCI Configuration Space Header Device ID PCI Configuration Space Header Vendor ID PCI Configuration Space Header Class Code PCI Configuration Space Header Rev ID PCI Configuration Space Header Subsystem ID PCI Configuration Space Header Subsystem Vendor ID Completion Timeout Device Sub Family Master Address Bus Width Master Data Bus Width Smallest Master Data Bus Width Native Data Bus Width of PLB Master Master ID Bus Width of PLB Number of PLB Masters Smallest Master Data Bus Width PLB Address Bus Width Base Address High Address PLB Data Bus Width Native Data Bus Width of PLB Slave PLB Slave Uses P2P Topology IPIF BAR0 Base Address IPIF BAR1 Base Address IPIF BAR2 Base Address IPIF BAR3 Base Address IPIF BAR4 Base Address IPIF BAR5 Base Address IPIF BAR0 High Address IPIF BAR1 High Address IPIF BAR2 High Address IPIF BAR3 High Address IPIF BAR4 High Address IPIF BAR5 High Address Remote PCI device BAR to which IPIF BAR0 is translated when configured with FIFOs Remote PCI device BAR to which IPIF BAR1 is translated when configured with FIFOs Remote PCI device BAR to which IPIF BAR2 is translated when configured with FIFOs Remote PCI device BAR to which IPIF BAR3 is translated when configured with FIFOs Remote PCI device BAR to which IPIF BAR4 is translated when configured with FIFOs Remote PCI device BAR to which IPIF BAR5 is translated when configured with FIFOs IPIF BAR 0 Address Size IPIF BAR 1 Address Size IPIF BAR 2 Address Size IPIF BAR 3 Address Size IPIF BAR 4 Address Size IPIF BAR 5 Address Size Remote PLB device BAR to which PCI BAR0 is translated when configured with FIFOs Remote PLB device BAR to which PCI BAR1 is translated when configured with FIFOs Remote PLB device BAR to which PCI BAR2 is translated when configured with FIFOs Power of 2 defining the Size in Bytes of PCI BAR0 Space Power of 2 defining the Size in Bytes of PCI BAR1 Space Power of 2 defining the Size in Bytes of PCI BAR2 Space Type of Board Device Name Processor Local Bus (PLB) 4.6 'Xilinx 64-bit Processor Local Bus (PLB) consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units with a a three-cycle only arbitration feature' Number of PLB Masters Number of PLB Slaves PLB Master ID Bus Width PLB Address Bus Width PLB Data Bus Width Include DCR Interface and Error Registers Base Address High Address DCR Address Bus Width DCR Data Bus Width External Reset Active High IRQ Active State <qt>Number of PLB Clock Periods a PLB Master that Received a Rearbitrate from an OPB2PLB Bridge on a Read Operation is Denied Grant on the PLB Bus</qt> Enable Address Pipelining Type Device Family Optimize PLB for Point-to-point Topology Selects the Arbitration Scheme XPS 10/100 Ethernet MAC Lite 'IEEE Std. 802.3 MII interface MAC with PLBV46 interface, lightweight implementation' Device Family Base Address High Address Clock Period of PLB Slave PLB Address Bus Width PLB Data Bus Width PLB Slave Uses P2P Topology Master ID Bus Width of PLB Number of PLB Masters Native Data Bus Width of PLB Slave PLB Slave is Capable of Bursts Duplex Mode Include Second Transmitter Buffer Include Second Receiver Buffer Ethernet Transmit Clock Input Ethernet Receive Clock Input Ethernet Carrier Sense Input Ethernet Receive Data Valid Ethernet Receive Data Input Ethernet Collision Input Ethernet Receive Error Input Ethernet PHY Reset Ethernet Transmit Enable Ethernet Transmit Data Output PowerPC 440 DDR2 Memory Controller A wrapper to instantiate the PowerPC 440 DDR2 Memory Controller Bank Address Width of DDR Memory Number of Generated DDR Clock Pairs. Data Bus Width of DDR Column Address Width of DDR Memory Number of DDR2 Memory Ranks Number of Chip Select in DDR2 Memory Rank (a.k.a log2C_NUM_RANKS_MEM) DDR2 Data Mask Width C_DQ_BITS DDR2 On Die Termination Width Additive Latency of DDR2 Memory Support ECC Logic Setting for On Die Termination DQS Bit Width DDR2 Strobe Width Row Address Width of DDR Memory Burst Length of DDR Memory CAS Latency of DDR Memory Include Support for Registered DIMMs. Clock Ratio between CPMINTERCONNECTCLK to DDR2 Clock Memory Base Address Memory High Address TREFI of DDR TRAS of DDR TRCD of DDR TRFC of DDR TRP of DDR TRTP of DDR TWR of DDR TWTR of DDR Clock Period(ps) of MIB Clock IDELAY High Performance Mode SKip 200us Power-up Time for Simulation Number of IDELAYCTRL Primitives (V4 only) that are explicitly instantiated LOC Constraints of IDELAYCTRL Primitive Read Data Pipeline IO Column Location of DQS Groups Master Slave Location of DQ IO XPS System ACE Interface Controller(Compact Flash) Interface between the PLBV46 and the Microprocessor Interface (MPU) of the System ACE Compact Flash solution peripheral Base Address High Address Width of System ACE Data Bus PLB Address Bus Width PLB Data Bus Width PLB Slave Uses P2P Topology Master ID Bus Width of PLB Number of PLB Masters Native Data Bus Width of PLB Slave PLB Slave is Capable of Bursts Device Family Address Input Clock Input Active high Interrupt Output Active LOW Chip Enable Active LOW Output Enable Active LOW Write Enable Data Input/Output Clock Generator Clock generator for processor system. PowerPC JTAG Controller JTAGPPC wrapper allows the PowerPC to connect to the JTAG chain of the FPGA. Processor System Reset Module Reset management module Device Subfamily Number of Clocks Before Input Change is Recognized On The External Reset Input Number of Clocks Before Input Change is Recognized On The Auxiliary Reset Input External Reset Active High Auxiliary Reset Active High Number of Bus Structure Reset Registered Outputs Number of Peripheral Reset Registered Outputs Device Family XPS Interrupt Controller intc core attached to the PLBV46 Device Family Base Address High Address PLB Address Bus Width PLB Data Bus Width PLB Slave Uses P2P Topology Number of PLB Masters Master ID Bus Width of PLB Native Data Bus Width of PLB Slave PLB Slave is Capable of Bursts Number of Interrupt Inputs Type of Interrupt for Each Input Type of Each Edge Senstive Interrupt Type of Each Level Sensitive Interrupt Support IPR Support SIE Support CIE Support IVR IRQ Output Use Level The Sense of IRQ Output