b51529a284
Update version number ready for next release.
6 years ago
58ba10eee8
Update version number in readiness for V10.2.0 release.
6 years ago
92ae8e7aff
Update version numbers ready for release.
7 years ago
3a1631fda3
Update copyright date ready for tagging V10.1.0.
7 years ago
fb9de58f56
Update version numbers in preparation for a new release.
7 years ago
10eea4aded
Remove period from the URL that links to the web page that describes the FreeRTOSConfig.h parameters.
7 years ago
26d8c76996
Update Zynq, MPSoc Cortex-A53 and MPSoc Cortex-R5 demo projects to build with the 18.1 version of the Xilinx SDK - building BUT NOT YET TESTED.
7 years ago
13651934be
Roll up the minor changes checked into svn since V10.0.0 into new V10.0.1 ready for release.
7 years ago
cfc268814a
Update to MIT licensed FreeRTOS V10.0.0 - see https://www.freertos.org/History.txt
7 years ago
8d041c8e21
Update version number in preparation for maintenance release.
8 years ago
979e41c9da
Update UltraScale R5 hardware definition and BSP for 2016.4 SDK tools.
8 years ago
992a3c8c71
Update BSP source files for UltraScale Cortex-A53 and Cortex-R5 and Microblaze to the 2016.4 versions.
...
Correct alignment issue in GCC Cortex-R port that was preventing full floating point usage in interrupts (other ports will be updated likewise).
Update the UltraScale R5 demo to test the GCC Cortex-A9 port layer modification mentioned on the line above.
8 years ago
2bd7884ace
Prepare for V9.0.0 release:
...
+ Change version number from V9.0.0rc2 to V9.0.0.
9 years ago
324127837c
Update some more standard demos for use on 64-bit architectures.
...
Update the Xilinx Ultrascale+ Cortex-A53 (64-bit) and Cortex-R5 (32-bit) demos to use version 2016.1 of the SDK.
9 years ago
Richard Barry