Correct alignment issue in GCC Cortex-R port that was preventing full floating point usage in interrupts (other ports will be updated likewise).
Update the UltraScale R5 demo to test the GCC Cortex-A9 port layer modification mentioned on the line above.
+ Add configASSERT() into ARM Cortex-M ports to check the number of priority
bit settings.
+ Clear the 'control' register before starting ARM Cortex-M4F ports in case
the FPU is used before the scheduler is started. This just saves a few
bytes on the main stack as it prevents space being left for a later save
of FPU registers.
+ Added xSemaphoreGetMutexHolderFromISR().
+ Corrected use of portNVIC_PENDSVSET to portNVIC_PENDSVSET_BIT in MPU ports.
- Clear the SysTick current value register before starting the SysTick (only required if something uses SysTick before starting the scheduler).
- Ensure atomic operations are thread safe by executing clrex in the context switch.
+ Set flash wait states on MSP432 demos.
+ Remove use of obsolete IO library in PIC32 demos.
+ Remove obsolete item left on stack of first task to run in the Cortex-M0 ports.
+ Correct IA32 GCC vPortExitCritical() implementation when configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY.
Tidy up CEC1302 demo.
Ensure bit 0 of the task address is clear when setting up stack of initial Cortex-M3/4/7 stacks (for strict compliance, although not practically necessary).
vTaskGetTaskInfo() changed to vTaskGetInfo() - with a macro added for backward compatibility.
- Remove the standard demo files that used the [long since deprecated] alternative API.
- Add standard demo task that tests the new xTaskAbortDelay() function.
- Update the Win32 Visual Studio project to use Visual Studio 2015 Community Edition.
- Rename the xGenericListItem TCB member to xStateListItem as it better describes the member's purpose.
+ Updated all ARM Cortex-M0 ports to include an additional ISB instruction as the scheduler is started.
Demo app files:
+ Fixex build issues in XMC1000 demos.
Kernel source changes:
- Added xTaskNotifyStateClear() API function.
- Added the GCC Cortex-R port (existed for a while) into the main download.
- Improved the IAR RL78 port's handling of different memory model combinations.
- Removed some compiler warnings in heap_5.c.
Demo app changes:
- Added example use of xTaskNotifyStateClear() to the TaskNotify standard demo tasks.
Bug fix - issue introduced in V8.2.2 when the current timer list is empty and the overflow timer list is not empty.
Add PIC32MZ EF (floating point) support and update the MZ demo project to test the flop context switching.
Improve efficiency of the stack overflow checking.
Add CLI to RX71M demo.
General tidy up of new RZ and RX projects - including ensuring the UART driver copes with 0 length strings.
Add stack overflow checking to the [old] PIC24 demo.
- Complete the demo projects for the RX113 using IAR, GCC and Renesas compilers by including a basic UART CLI.
Standard demo tasks:
- Add some volatile qualifiers to variables in IntQueue.c.
Add additional asserts into timers.c.
Trivial changes and changes in demo applications:
RX113 IAR project is not building and running.
Make FreeRTOS_SetupInterrupt() and FreeRTOS_ClearInterrupt() weak symbols in the Zynq SDK repository.
Correct typo in the port layer comments that was cut and paste into multiple files.
+ Added Renesas RXv2 port for IAR.
Demo apps:
+ Demo/Rename the CORTEX_R4F_T_GCC_IAR_ARM directory to just Rename the CORTEX_R4F_T_GCC_IAR.
+ Add IAR project for the RX113.
+ Add RX231 e2studio projects for the RX231.
Exclude the entire croutine.c file when configUSE_CO_ROUTINES is 0.
New ports:
Added Cortex-M7 IAR and Keil port layers that include a minor errata workaround r0p1 Cortex-M7 devices.
Added Cortex-M4F port layer for CCS.
New demo applications:
Added demo application for STM32F7.
Added demo application for SAMv71.
+ Fix a few compiler warnings.
+ Add TickType_t specific critical sections so critical sections are not used when accessing the tick count in cases where the access is atomic (32-bit tick count, 32-bit architecture).
+ Optimise Cortex-M4F ports by inlining some critical section macros.
+ Original ports used a #define to set the path to portmacro.h - that method has been obsolete for years and now all the old definitions have been moved into a separate header files called deprecated_definitions.h.
+ Cortex-M port now check the active vector bits against 0xff when determining if a function is called from an interrupt - previously only a subset of the bits (0x1f) were checked.
+ Add in new standard demo/test files TaskNotify.c/h and include the files in the simulator demos.
+ Update trace recorder code, and some demos to use the new version (more to do).
+ Introduce uxTaskPriorityGetFromISR().
+ Minor typo corrections.
+ Update MingW simulator demo to match the MSVC simulator demo.
Allow the stats formatting functions to be built in without stdio.h being included inside tasks.c.
Kernel port code:
- Slight change to the Cortex-A GIC-less port to move all non portable code to the application level.
SAMA5D4 demo project:
- Update the Atmel provided library to V1.1.
- Create a DDR build configuration.
- Ensure interrupts are all edge sensitive.
- Update the regtest code to use all 32 flop registers.
+ Change how queues are allocated and deleted so only one pvPortMalloc() or vPortFree() is required in place of the previous 2.
+ Where the TCB is allocated in relation to the stack is now dependent on the stack growth direction. The stack will not grow into the TCB.
+ Introduce the configAPPLICATION_ALLOCATED_HEAP constant to allow the application to provide the array used by heap_4.c as its heap. This allows the application writer to use qualifiers on the array to, for example, force the memory into faster RAM.
Demo application:
+ Add demo for SAMA5D4 using IAR.
+ Update the RZ IAR project so it targets the RZ RSK rather than custom hardware.
+ Update the RZ ARM/DS-5 project so it targets the RZ RSK rather than custom hardware.
+ Updated RX64M demos to use the new iodefine.h naming.
Cortex-A9 port related:
+ Update IAR, ARM and GCC Cortex-A9 port layers to include a 'task exit error' function which is called if a task attempts to incorrectly exit its implementing function.
+ Moved the instruction which switches into system mode out of the restore context macro, as it is only needed when starting the first task.
Core kernel files related:
+ Ensure there are no references to the mutexes held count when mutexes are excluded from the build.
- Slight improvement to the save context macro.
- Remove some #warning remarks.
- Enable interrupts before calling the ISR handler rather than in the ISR handler.
- Add in the assert when a task attempts to exit its implementing function without deleting itself.
- Remove obsolete code from the context switch asm code (obsoleted by the fact that there is no mask register).
- Attempt to make code more generic by using definitions for additional register addresses.
Richard Barry