3 Commits (ceeff145245c673d433d6548a83c33727b974486)

Author	SHA1	Message	Date
Richard Barry	b2b1b09ea5	Fix bug in core_cm3.c atomic macros. ... Rename the portable/GCC/RISC-V-RV32 directory to just RISC-V as also adding support for 64-bit cores.	6 years ago
Richard Barry	fb73829148	Ensure eTaskGetState() is brought in automatically if INCLUDE_xTaskAbortDelay is set to 1, as it is a dependency of eTaskGetState(). ... Added the portTASK_FUNCTION_PROTO macros around the timer task, as the macros are already used by the idle task. Add a PDF of the RISC-V documentation into the repo as the web page is not yet live.	6 years ago
Richard Barry	80f6f3e59b	Retarget Softconsole RISC-V demo from IGLOO2 to Renode as it can have more RAM and therefore have more test tasks running.	6 years ago