5 Commits (883541bc8e980790469cf90eb3d253123e65da56)

Author	SHA1	Message	Date
Richard Barry	75ffac21d7	Changes to core code and port layer: ... + Add configASSERT() into ARM Cortex-M ports to check the number of priority bit settings. + Clear the 'control' register before starting ARM Cortex-M4F ports in case the FPU is used before the scheduler is started. This just saves a few bytes on the main stack as it prevents space being left for a later save of FPU registers. + Added xSemaphoreGetMutexHolderFromISR(). + Corrected use of portNVIC_PENDSVSET to portNVIC_PENDSVSET_BIT in MPU ports.	9 years ago
Richard Barry	bdbf347c22	Remove clrex instruction from Cortex-M ports again as it is implicit in interrupt entry.	9 years ago
Richard Barry	c296e2cff8	Improvements to the Cortex-M ports: ... - Clear the SysTick current value register before starting the SysTick (only required if something uses SysTick before starting the scheduler). - Ensure atomic operations are thread safe by executing clrex in the context switch.	9 years ago
Richard Barry	2bd7884ace	Prepare for V9.0.0 release: ... + Change version number from V9.0.0rc2 to V9.0.0.	9 years ago
Richard Barry	ee9cd40b6d	Add GCC ARM Cortex-M4F MPU port. ... Add RVDS ARM Cortex-M4F MPU port. Increase the size of each buffer allocated to pbufs in the Microblaze lwIP demo to prevent pbufs chaining. Use _start as the top of the stack for each Microblaze task, rather than NULL, as NULL was causing the Xilinx SDK to try and unwind the stack too far.	9 years ago