817783d75c
Copyright updates from Cadence.
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e1df894752
6 years ago
11d9c440b8
Move the 'generic' version of freertos_risc_v_chip_specific_extensions.h back to a sub-directory as having it in the RISC-V port's base directory was causing SoftConsole to pick up the wrong version (for an unknown reason).
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Add a project for the Vega board's RI5CY core.
6 years ago
e2af102c80
Re-org of RISC-V file structure and naming step 2.
6 years ago
818eeccc0c
Re-org of RISC-V file structure and naming step 1.
6 years ago
db750d0c82
Update RSIC-V port layer after testing saving and receiving of chip specific registers.
6 years ago
60b133b2c6
Move the RISC-V pxPortInitialiseStack() implementation to the assembly port file from the C port file so it can have access to the number of chip specific registers it needs to save space for on the stack.
6 years ago
d369110167
Allow the size of the stack used by many of the standard demo/test tasks to be overridden by FreeRTOSConfig.h settings.
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Update the Freedom Studio RISC-V project so the 'full' build configuration is now functional.
6 years ago
ce36928ea8
Rename directories in the RISC-V port.
6 years ago
148f588f56
Remove "FromISR' functions from the list of functions that switch to a privileged mode as IRQs are privileged already.
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Add the vTimerSetReloadMode() API function.
6 years ago
101806906d
Rework RISC-V portASM.S to make it easier to add in chip specific RISC-V extensions and accommodate chips that don't include the CLINT.
6 years ago
7cc42b2ab6
Save changes to the RISC-V port layer before making changes necessary to support pulpino too:
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+ Switch positions of the asm functions used to start the kernel and handle traps to enable one to reference to the other.
+ Handle external interrupts (working with Renode emulator).
+ The _sp linker variable is now called __freertos_irq_stack_top.
6 years ago
65f7a2dc19
Update RISC-V port to use a separate interrupt stack.
6 years ago
e85ea96f78
Some efficiency improvements in Risc-V port.
6 years ago
dc99300fa9
First task running in RISC-V-Qemu-sifive_e-FreedomStudio demo.
6 years ago
db64297487
Provide each Risc V task with an initial mstatus register value.
6 years ago
8cef339aec
Update Risc-V port to use environment call in place of software interrupt - still very much a work in progress.
6 years ago
baee711cb6
Continue work on Risc V port.
6 years ago
74d0d16aab
Update xTaskRemoveFromEventList() so when tickless idle is used prvResetNextTaskUnblockTime() only gets called if the scheduler is not locked, as it would get called when the scheduler is unlocked in any case.
6 years ago
55ff89373a
Update the method used to detect if a timer is active. Previously the timer was deemed to be inactive if it was not referenced from a list. However, when a timer is updated it is temporarily removed from, then re-added to a list, so now the timer's active status is stored separately.
6 years ago
6fab2b9e0d
Add xTaskGetApplicationTaskTagFromISR(), which is an interrupt safe version of xTaskGetApplicationTaskTagFrom().
6 years ago
c6de0001fa
Added uxTaskGetStackHighWaterMark2(), which is the same as uxTaskGetStackHighWaterMark() other than the return type.
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Allows the task name parameter passed into xTaskCreate() to be NULL.
6 years ago
e3dc5e934b
RISC-V tasks now context switching to each other using taskYIELD() - not fully tested yet.
6 years ago
2bcb1ab02b
Add trap handler to RISC-V port so there is no dependency on third party code.
6 years ago
32f35e9130
RISC-V:
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Added code to setup the timer interrupt - not tested yet.
Added the taskYIELD() implementation - so far just checked it generates an interrupt.
6 years ago
b11eb3a59c
RISC-V work in progress:
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+ Initialise task stack.
+ Successfully jump to start of first task.
6 years ago
0c0f0d0f8f
Minor synching - no functional changes.
7 years ago
92ae8e7aff
Update version numbers ready for release.
7 years ago
be9c0730c3
Update trace recorder code to the latest.
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Some minor changes to enable the configREMOVE_STATIC_QUALIFIER constant to be used by those debuggers that cannot cope with statics being used.
7 years ago
21a8ff35dd
Two minor updates in the comments to fix html formatting that was preventing doxygen creating documents correctly.
7 years ago
e2750cd388
Case unused return values for memset and memcpy to void in stream_buffer.c to avoid compiler warnings when the warning level is turned up.
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Remove duplicate comment in heap_1.c.
7 years ago
0d6e3df7ec
Minor updates to fix issues with the Segger kernel aware plug since V10.1.0.
7 years ago
893db45834
Changes required for the IAR StateViewer plug-in to work with FreeRTOS V10.1.0.
7 years ago
b0ce1f61c9
Move some variables from function scope back to being file scope for the benefit of some kernel aware debuggers that were left working in a non-functioning mode after the V10.1.0 release - not last change for this purpose.
7 years ago
3a1631fda3
Update copyright date ready for tagging V10.1.0.
7 years ago
fb9de58f56
Update version numbers in preparation for a new release.
7 years ago
722ca8fb2b
Update demo project for Tensilita - work in progres..
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Add support for POSIX style errno - work in progress.
7 years ago
78d20e2854
Only include the static definition of freertos_tasks_c_additions_init if FREERTOS_TASKS_C_ADDITIONS_INIT is defined, matching the guide used to include the function's prototype.
7 years ago
56dc0dd9b4
Merge bug fixes from Cadence
7 years ago
f6cbf20019
Update RISC-V project to used official port stubs in place of third party port.
7 years ago
3bfc32d444
Add stubs for official RISC-V RV32 port.
7 years ago
0887713969
Fix issues whereby vStreamBufferReset() clobbered the flag that indicated the stream buffer was statically allocated.
7 years ago
483f4a8c4b
Small change to the directory name in which the RISC-V port is stored.
7 years ago
3d8d2f3cc8
Add RISCV port layer.
7 years ago
c4b1afc4ef
Add Xtensa port
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The project file is for Xtensa Xplorer simulator.
Also add tests for one size stream buffer.
7 years ago
d6fcd5dbba
Add the option to specify a stack size in the standard demo MessageBuffer tests.
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Add stream and message buffer tests into the Zynq demo project.
7 years ago
4fbcdbf13b
Fix misra violations in queue.c by introducing a union that allows the correct data types to be used in place of void *, then tidy up where the union is used.
7 years ago
4a8c4c9eaf
TimerHandle_t is now type safe instead of void *.
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Remove casts that are no longer required not type safe handles are used.
7 years ago
3d8681de9e
Continue updating to MISRA 2012 from 2004 - currently working on queue.c and committing as working copy prior to making larger change.
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Change QueueHandle_t to be typesafe from void *.
Change StreamBuffer_t to be typesafe from void *.
7 years ago
7a9f453f96
Remove casts from EventGroupHandle_t to EventGroup_t, and corresponding lint comments, which are not required now EventGroupHandle_t is type safe.
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Fix the prototype of prvTimerCallback() in the MPU simulator demo (caught due to the new type safety in tasks.c).
7 years ago
390fb06b49
First pass at updating from MISRA 2004 to MISRA 2012:
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Updated pvContainer member of list items to List_t * rather than void * as they are always contained in a list if anywhere.
Made EventGroupHandle_t typesafe pointer to forward referenced struct rather than void pointer.
Made TaskHandle_t typesafe pointer to forward referenced struct, rather than a void pointer.
7 years ago
Gaurav Aggarwal
Richard Barry