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main
smp
V11.1.0
V11.0.1
V11.0.0
V10.6.2
V10.6.1
V10.6.0
V10.5.1
V10.5.0
V10.4.3-LTS-Patch-3
V10.4.6
V10.4.3-LTS-Patch-2
V202110.00-SMP
V10.4.5
V10.4.3-LTS-Patch-1
V10.4.4
V10.4.0-kernel-only
V10.3.0-kernel-only
V10.3.0
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V10.2.1
V10.2.0
V10.1.1
V10.1.0
V10.0.1
V10.0.0
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V9.0.0rc2
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V7.5.0
V7.4.2
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V7.2.0
V7.1.1
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V7.0.2
V7.0.1
V7.0.0
V6.1.1
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V6.0.5
V6.0.4
V6.0.3
V6.0.1
V6.0.0
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V5.4.1
V5.3.1
V5.3.0
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V5.0.3
V5.0.2
V5.0.0
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V4.7.2
V4.7.1
V4.7.0
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V4.5.0
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V4.2.1
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V4.1.3
V4.1.2
V4.1.1
V4.1.0
V4.0.5
V4.0.3
V4.0.2
V4.0.1
V10.3.1-kernel-only
V10.4.1-kernel-only
V10.4.2
V10.4.3
V8.0.0-rc1
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V9.0.0-rc2
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Commit Graph

4 Commits (7d285f3dcb75fd60901dfc3fd746af38256de5be)

Author SHA1 Message Date
Richard Barry b51529a284 Update version number ready for next release. 6 years ago
Richard Barry 079d081346 Basic 64-bit RISC-V port now functional. RISC-V port layer automatically switches between 32-bit and 64-bit. 6 years ago
Richard Barry 58ba10eee8 Update version number in readiness for V10.2.0 release. 6 years ago
Richard Barry b2b1b09ea5 Fix bug in core_cm3.c atomic macros. 
Rename the portable/GCC/RISC-V-RV32 directory to just RISC-V as also adding support for 64-bit cores.
 6 years ago