Commit Graph

32 Commits (6311ad13b9a66d5ebefede1ee1520533b666da6b)

Author SHA1 Message Date
Jakub Lužný d91cd6fd05
RISC-V: Add support for RV32E extension in GCC port (#543)
Co-authored-by: Joseph Julicher <jjulicher@mac.com>
2 years ago
Ming Yue 09a2c0b324
Remove exception loop tags. (#457) 3 years ago
Ming Yue 25d180a09b
Use a dedicated symbol for in-function loop to avoid the weak symbol JAL range error when a strong symbol is defined outside. (#455) 3 years ago
Gaurav-Aggarwal-AWS d5a10e4595
Add alignment for the direct mode handler (#449)
It is still possible to further relax the alignment using linker script
if needed.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
3 years ago
Gaurav-Aggarwal-AWS 9efca75d1e
Riscv re-factoring (#444)
* Refactor RISCV port

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Changes to make re-factoring work on ESP32-C3

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Remove alignment and place handlers in separate sections

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Correct section names

This is needed so that the assemblers correctly recognizes functions.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Move mtvec programming to the application

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Refactor mtimer udpate code

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Move critical nesting to port layer

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Respect configTASK_RETURN_ADDRESS

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

* Formatting changes

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
3 years ago
Fabian 481c722ef3
RISC-V: No #error on RV64 regarding byte alignment (#367)
Co-authored-by: Joseph Julicher <jjulicher@mac.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
3 years ago
Gaurav-Aggarwal-AWS fa0f5c436c
Add freertos_risc_v_chip_specific_extensions.h for 64-bit ports (#385)
* Add freertos_risc_v_chip_specific_extensions.h for 64-bit ports

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
3 years ago
Paul Bartell eec42331b4 Normalize files with mixed line endings (introduced in commit 3a413d1) 4 years ago
Paul Bartell 3a413d1022 Add SPDX-License-Identifier: MIT to MIT licensed files. 4 years ago
Paul Bartell b286f173e8 Update license text for ports that were previously missed. 4 years ago
Paul Bartell e31dccae80 Remove "1 tab == 4 spaces!" line from files that still contain it. 4 years ago
Paul Bartell adfc53368f Update copyright year from 2020 to 2021 4 years ago
Paul Bartell 08dc6f64ee Change kernel revision in each file header from V10.4.3 to <DEVELOPMENT BRANCH> 4 years ago
j4cbo f37bcd5c14
Wrap macros in do { ... } while( 0 ) (#240) 4 years ago
Cobus van Eeden ec62f69dab [AUTO][RELEASE]: Bump file header version to "10.4.3" 4 years ago
David Chalco 337bca615e [AUTO][RELEASE]: Bump file header version to "10.4.2" 4 years ago
Cobus van Eeden 385e700953
Update History.txt and fix versioning in asm files (#177) 4 years ago
David Chalco 3604527e3b
Update version number to 10.4.1 (#173) 4 years ago
RichardBarry 85768bb3e0
Sets the version number to 10.4.0 in assembly files. The (#166)
assembly files were missed when the other source files had
their version numbers updated.
4 years ago
David Chalco 5dfab0306b
Update version number to 10.4.0 (#153) 4 years ago
Joseph Julicher 2f14899ce8
Revert "RISC-V: Add RV32E / FPU support for GCC (#140)" (#163)
This reverts commit 0037a6c574.
4 years ago
Emmanuel Puerto 0037a6c574
RISC-V: Add RV32E / FPU support for GCC (#140)
* Change vPortSetupTimerInterrupt in order to have 64bits access on rv64

* Support RV32E - RISC-V architecture (GCC)

Signed-off-by: Emmanuel Puerto <emmanuel.puerto@sifive.com>

* Support FPU - RISC-V architecture (GCC)

Signed-off-by: Emmanuel Puerto <emmanuel.puerto@sifive.com>

* Fix interrupt managment and FPU initialization
4 years ago
alfred gedeon a038146915
Style: Make freertos.org = FreeRTOS.org and add https (#134)
* Style: make freertos.org = FreeRTOS.org also add https

* Style: Fix freertos into FreeRTOS

* Style: Fix freertos into FreeRTOS

Co-authored-by: Alfred Gedeon <gedeonag@amazon.com>
5 years ago
alfred gedeon 0b0a2060c0
Style: Change FreeRTOS websites in comments (#131)
* Style: Change FreeRTOS websites in comments

* Style: Change freertos to FreeRTOS in comments

* Style: Remove broken link

Co-authored-by: Alfred Gedeon <gedeonag@amazon.com>
5 years ago
alfred gedeon 86653e2a1f
Style: Revert uncrustify for portable directories (#122)
* Style: revert uncrustify portable directories

* Style: Uncrustify Some Portable files

Co-authored-by: Alfred Gedeon <gedeonag@amazon.com>
5 years ago
Alfred Gedeon 587a83d647 Style: uncrustify kernel files 5 years ago
Alfred Gedeon 2c530ba5c3 Style: uncrustify 5 years ago
Alfred Gedeon 718178c68a Style: uncrusitfy 5 years ago
Alfred Gedeon a5dbc2b1de Style: uncrustify kernel files 5 years ago
RichardBarry bac101c988
Fix/clear MIE bit in initial RISC-V mstatus register. (#57)
* fix: CLEAR MIE BIT IN INITIAL RISC-V MSTATUS VALUE
The MIE bit in the RISC-V MSTATUS register is used to globally enable
or disable interrupts.  It is copied into the MPIE bit and cleared
on entry to an interrupt, and then copied back from the MPIE bit on
exit from an interrupt.

When a task is created it is given an initial MSTATUS value that is
derived from the current MSTATUS value with the MPIE bit force to 1,
but the MIE bit is not forced into any state.  This change forces
the MIE bit to 0 (interrupts disabled).

Why:
If a task is created before the scheduler is started the MIE bit
will happen to be 0 (interrupts disabled), which is fine.  If a
task is created after the scheduler has been started the MIE bit
is set (interrupts enabled), causing interrupts to unintentionally
become enabled inside the interrupt in which the task is first
moved to the running state - effectively breaking a critical
section which in turn could cause a crash if enabling interrupts
causes interrupts to nest.  It is only an issue when starting a
newly created task that was created after the scheduler was started.

Related Issues:
https://forums.freertos.org/t/risc-v-port-pxportinitialisestack-issue-about-mstatus-value-onto-the-stack/9622
Co-authored-by: Cobus van Eeden <35851496+cobusve@users.noreply.github.com>
5 years ago
Yuhui.Zheng 88e32327e9
version bump to v10.3.1 (#16)
* Verion bump from 10.3.0 to 10.3.1.
* version bump in task.h
* change history for 10.3.1.
5 years ago
Yuhui Zheng 210b1ffcc8 Re-sync with upstream and stripping away none kernel related. 5 years ago