5623c69748
Fix Build and Links failure in MPU projects. Minor cosmetic changes in some V8M files.
6 years ago
8b6ab5f197
Add instructions on building the Cortex-M33 secure and non secure projects into the comments of that project and into a readme.txt file.
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Enable configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES setting to be used in statically allocated systems.
6 years ago
ceeff14524
Set default value of configRUN_FREERTOS_SECURE_ONLY to 0.
6 years ago
5849459c65
Add support for running FreeRTOS on Secure Side only in Cortex M33 port. Also, change spaces to tabs.
6 years ago
c3c9c12ce2
Update the common demo death.c to use the updated macro name to give it a secure context.
6 years ago
ce576f3683
First Official Release of ARMV8M Support. This release removes Pre-Release from all the ARMv8M files licensees.
6 years ago
58ba10eee8
Update version number in readiness for V10.2.0 release.
6 years ago
55ad3861c5
Sync the Renesas port to AFR Git Repo
6 years ago
0de2a2758a
Fix definition of tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE
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tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE was not correctly defined resulting in
dynamically allocated TCB not being freed when MPU was enabled. This commit fixes
the definition to ensure that dynamically allocated RAM (Stack and TCB) is freed
always.
6 years ago
2c88fb7fa1
Fix build failure when dynamic allocation is not enabled.
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When dynamic allocation is not enabled, vPortFree is not available. The current code used
vPortFree and this resulted in linker error. This commit removes the use of vPortFree when
dynamic allocation is not enabled.
6 years ago
6844bef74f
Replace the pdf RISC-V documentation with links to the documentation web pages.
6 years ago
b2b1b09ea5
Fix bug in core_cm3.c atomic macros.
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Rename the portable/GCC/RISC-V-RV32 directory to just RISC-V as also adding support for 64-bit cores.
6 years ago
fb73829148
Ensure eTaskGetState() is brought in automatically if INCLUDE_xTaskAbortDelay is set to 1, as it is a dependency of eTaskGetState().
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Added the portTASK_FUNCTION_PROTO macros around the timer task, as the macros are already used by the idle task.
Add a PDF of the RISC-V documentation into the repo as the web page is not yet live.
6 years ago
df5952f655
Add xTaskGetIdleRunTimeCounter() API function to return the run time stats counter for the idle task - useful for POSIX time implementations.
6 years ago
817783d75c
Copyright updates from Cadence.
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e1df894752
6 years ago
11d9c440b8
Move the 'generic' version of freertos_risc_v_chip_specific_extensions.h back to a sub-directory as having it in the RISC-V port's base directory was causing SoftConsole to pick up the wrong version (for an unknown reason).
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Add a project for the Vega board's RI5CY core.
6 years ago
e2af102c80
Re-org of RISC-V file structure and naming step 2.
6 years ago
818eeccc0c
Re-org of RISC-V file structure and naming step 1.
6 years ago
db750d0c82
Update RSIC-V port layer after testing saving and receiving of chip specific registers.
6 years ago
60b133b2c6
Move the RISC-V pxPortInitialiseStack() implementation to the assembly port file from the C port file so it can have access to the number of chip specific registers it needs to save space for on the stack.
6 years ago
d369110167
Allow the size of the stack used by many of the standard demo/test tasks to be overridden by FreeRTOSConfig.h settings.
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Update the Freedom Studio RISC-V project so the 'full' build configuration is now functional.
6 years ago
ce36928ea8
Rename directories in the RISC-V port.
6 years ago
148f588f56
Remove "FromISR' functions from the list of functions that switch to a privileged mode as IRQs are privileged already.
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Add the vTimerSetReloadMode() API function.
6 years ago
101806906d
Rework RISC-V portASM.S to make it easier to add in chip specific RISC-V extensions and accommodate chips that don't include the CLINT.
6 years ago
7cc42b2ab6
Save changes to the RISC-V port layer before making changes necessary to support pulpino too:
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+ Switch positions of the asm functions used to start the kernel and handle traps to enable one to reference to the other.
+ Handle external interrupts (working with Renode emulator).
+ The _sp linker variable is now called __freertos_irq_stack_top.
6 years ago
65f7a2dc19
Update RISC-V port to use a separate interrupt stack.
6 years ago
e85ea96f78
Some efficiency improvements in Risc-V port.
6 years ago
dc99300fa9
First task running in RISC-V-Qemu-sifive_e-FreedomStudio demo.
6 years ago
db64297487
Provide each Risc V task with an initial mstatus register value.
6 years ago
8cef339aec
Update Risc-V port to use environment call in place of software interrupt - still very much a work in progress.
6 years ago
baee711cb6
Continue work on Risc V port.
6 years ago
74d0d16aab
Update xTaskRemoveFromEventList() so when tickless idle is used prvResetNextTaskUnblockTime() only gets called if the scheduler is not locked, as it would get called when the scheduler is unlocked in any case.
6 years ago
55ff89373a
Update the method used to detect if a timer is active. Previously the timer was deemed to be inactive if it was not referenced from a list. However, when a timer is updated it is temporarily removed from, then re-added to a list, so now the timer's active status is stored separately.
6 years ago
6fab2b9e0d
Add xTaskGetApplicationTaskTagFromISR(), which is an interrupt safe version of xTaskGetApplicationTaskTagFrom().
6 years ago
c6de0001fa
Added uxTaskGetStackHighWaterMark2(), which is the same as uxTaskGetStackHighWaterMark() other than the return type.
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Allows the task name parameter passed into xTaskCreate() to be NULL.
6 years ago
e3dc5e934b
RISC-V tasks now context switching to each other using taskYIELD() - not fully tested yet.
6 years ago
2bcb1ab02b
Add trap handler to RISC-V port so there is no dependency on third party code.
6 years ago
32f35e9130
RISC-V:
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Added code to setup the timer interrupt - not tested yet.
Added the taskYIELD() implementation - so far just checked it generates an interrupt.
6 years ago
b11eb3a59c
RISC-V work in progress:
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+ Initialise task stack.
+ Successfully jump to start of first task.
6 years ago
0c0f0d0f8f
Minor synching - no functional changes.
7 years ago
92ae8e7aff
Update version numbers ready for release.
7 years ago
be9c0730c3
Update trace recorder code to the latest.
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Some minor changes to enable the configREMOVE_STATIC_QUALIFIER constant to be used by those debuggers that cannot cope with statics being used.
7 years ago
21a8ff35dd
Two minor updates in the comments to fix html formatting that was preventing doxygen creating documents correctly.
7 years ago
e2750cd388
Case unused return values for memset and memcpy to void in stream_buffer.c to avoid compiler warnings when the warning level is turned up.
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Remove duplicate comment in heap_1.c.
7 years ago
0d6e3df7ec
Minor updates to fix issues with the Segger kernel aware plug since V10.1.0.
7 years ago
893db45834
Changes required for the IAR StateViewer plug-in to work with FreeRTOS V10.1.0.
7 years ago
b0ce1f61c9
Move some variables from function scope back to being file scope for the benefit of some kernel aware debuggers that were left working in a non-functioning mode after the V10.1.0 release - not last change for this purpose.
7 years ago
3a1631fda3
Update copyright date ready for tagging V10.1.0.
7 years ago
fb9de58f56
Update version numbers in preparation for a new release.
7 years ago
722ca8fb2b
Update demo project for Tensilita - work in progres..
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Add support for POSIX style errno - work in progress.
7 years ago
Gaurav Aggarwal
Richard Barry