FreeRTOS-Kernel

Author	SHA1	Message	Date
Richard Barry	6844bef74f	Replace the pdf RISC-V documentation with links to the documentation web pages.	6 years ago
Richard Barry	b2b1b09ea5	Fix bug in core_cm3.c atomic macros. Rename the portable/GCC/RISC-V-RV32 directory to just RISC-V as also adding support for 64-bit cores.	6 years ago
Richard Barry	fb73829148	Ensure eTaskGetState() is brought in automatically if INCLUDE_xTaskAbortDelay is set to 1, as it is a dependency of eTaskGetState(). Added the portTASK_FUNCTION_PROTO macros around the timer task, as the macros are already used by the idle task. Add a PDF of the RISC-V documentation into the repo as the web page is not yet live.	6 years ago
Richard Barry	11d9c440b8	Move the 'generic' version of freertos_risc_v_chip_specific_extensions.h back to a sub-directory as having it in the RISC-V port's base directory was causing SoftConsole to pick up the wrong version (for an unknown reason). Add a project for the Vega board's RI5CY core.	6 years ago
Richard Barry	e2af102c80	Re-org of RISC-V file structure and naming step 2.	6 years ago
Richard Barry	60b133b2c6	Move the RISC-V pxPortInitialiseStack() implementation to the assembly port file from the C port file so it can have access to the number of chip specific registers it needs to save space for on the stack.	6 years ago
Richard Barry	80f6f3e59b	Retarget Softconsole RISC-V demo from IGLOO2 to Renode as it can have more RAM and therefore have more test tasks running.	6 years ago