Commit Graph

77 Commits (3cbe0a724d6963d956369d2428b606b0c5b638e8)

Author SHA1 Message Date
Richard Barry 3cbe0a724d Update version number. 12 years ago
Richard Barry bb2093cf5d Update the header file included in the PIC32 port_asm.S file to use the header for the latest compiler version. 12 years ago
Richard Barry 679a3c670c Update the Cortex-M vPortValidateInterruptPriority() implementation to ensure compatibility with the STM32 standard peripheral library. 12 years ago
Richard Barry 203ae64600 Rename xTaskGetSystemState() uxTaskGetSystemState(). 12 years ago
Richard Barry 7d6758ee1a Minor updates and change version number for V7.5.0 release. 12 years ago
Richard Barry 7d1292ced2 Linting and MISRA checking 12 years ago
Richard Barry ce9c3b7413 Variable name change in the PIC32 port layer only. 12 years ago
Richard Barry da0fff63c9 Update Cortex-M MPU version to include new API functions. 12 years ago
Richard Barry e5d9640863 Update RX ports to only include additional check on the existing IPL (so it is not lowered) if configASSERT() is defined. 12 years ago
Richard Barry 4b964814de Implement portASSERT_IF_INTERRUPT_PRIORITY_INVALID() for PIC32. 12 years ago
Richard Barry ad8fa53043 Kernel optimisations. 12 years ago
Richard Barry 5d902f2b9c Complete additions of portASSERT_IF_INTERRUPT_PRIORITY_INVALID() for all RX compiler ports. 12 years ago
Richard Barry 65704174c9 Add portASSERT_IF_INTERRUPT_PRIORITY_INVALID() implementation to the RX ports that use the Renesas compiler.
Add portASSERT_IF_INTERRUPT_PRIORITY_INVALID() implementation to the Cortex-A9 ports.
12 years ago
Richard Barry 0f6b0d3a59 Enhance heap_4.c to prevent blocks accidentally being freed twice, or blocks that don't have a valid block link descriptor being freed.
Update the Cortex-A9 port to include asserts if an ISR safe FreeRTOS function is called from an interrupt that has a higher logical priority than configMAX_SYSCALL_INTERRUPT_PRIORITY (or whatever the CA9 equivalent is called), and also assert if the binary point is not set correctly.
12 years ago
Richard Barry c4eef61d39 Added portASSERT_IF_INTERRUPT_PRIORITY_INVALID() implementation to Cortex-M3 and Cortex-M4F ports. 12 years ago
Richard Barry 0c0b54c175 Refine the default tickless idle implementation in the Cortex-M3 port layers. 12 years ago
Richard Barry a7c47131fa Remove portALIGNMENT_ASSERT_pxCurrentTCB() macro, which serves no purpose. 12 years ago
Richard Barry 6cbbfd2eb5 Slight correction to coding standard in heap_2.c and heap_4.c. 12 years ago
Richard Barry fb47260e80 Improve efficiency of memory allocation when the memory block is already aligned correctly. 12 years ago
Richard Barry c3f9e3c5ff Update RVDS port layer to match IAR port layer. 12 years ago
Richard Barry 5013baa2cd RVDS ARM Cortex-A port layer. 12 years ago
Richard Barry 04dafed839 IAR ARM Cortex-A port layer. 12 years ago
Richard Barry 2fd431e971 Modify the GCC/AVR port to make use of the xTaskIncrementTick return value.
Add pre-processor directives in the dsPIC and PIC24 port layers that allows both port files to be included in the same project.
12 years ago
Richard Barry 62c0ae0926 Update port layers to make better use of the xTaskIncrementTick() return value. 12 years ago
Richard Barry 59a834eb86 Update ports that have their tick configuration in an application callback to use xTaskIncrementTick() in place of vTaskIncrementTick(). 12 years ago
Richard Barry c04b074707 Convert the remaining ports to use xTaskIncrementTick() in place of vTaskIncremenTick(). 12 years ago
Richard Barry 2fc9d033c6 Update the PIC32 port to use xTaskIncrementTick() and change the macro used to detect if XC is being used. 12 years ago
Richard Barry 51d9ee0c1c Add configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS mechanism to the relevant port.c file to allow the user to define functions that will execute in privileged mode. 12 years ago
Richard Barry f904d26957 Convert more ports to use xTaskIncrementTick() in place of vTaskIncrementTick(). 12 years ago
Richard Barry 15ec6c87f7 Convert mpre ports to use xTaskIncrementTick() in place of vTaskIncrementTick(). 12 years ago
Richard Barry 686d190798 Convert some ports to use xTaskIncrementTick() in place of vTaskIncrementTick().
Move DSB instructions to before WFI instructions in line with ARM recommendations.
12 years ago
Richard Barry 06953169ba Update RM48/TMS570 port to use xTaskIncrementTick in place of vTaskIncrementTick. 12 years ago
Richard Barry a03b171992 Fix compiler warning in psp_test.c when compiled with ARM compiler.
Add portYIELD_FROM_ISR() macros to Cortex-M ports.  The new macro just calls the exiting portEND_SWITCHING_ISR() macro.
Remove code from the MSVC port layer that was left over from a previous implementation and become obsolete.
12 years ago
Richard Barry fb9662009a Update comments in Atmel Studio CreateProjectDirectoryStructure.bat files to remove references to replace references to Eclipse with references to Atmel Studio.
Update the tickless idle implementations that use up counters for tick interrupt generate to ensure they remain in low power mode for the desired time instead of one tick less than the desired time.
12 years ago
Richard Barry 96ceae8edd Update version number ready to release the FAT file system demo. 12 years ago
Richard Barry f9918345e1 Update version numbers to V7.4.1. 12 years ago
Richard Barry 2b41be4cb9 Update yield code in RX200/Renesas compiler port. 12 years ago
Richard Barry 0013028c7a Update yield code in RX600/IAR compiler port. 12 years ago
Richard Barry 4f5f527c73 Update yield code in RX600/Renesas compiler port. 12 years ago
Richard Barry b7487b8dc2 Update yield code in RX600/GCC port. 12 years ago
Richard Barry a69933782d Add RX100 Renesas compiler port layer. 12 years ago
Richard Barry 74290b4425 Add RX100 IAR port layer. 12 years ago
Richard Barry a0056e8fd3 Add RX100 GCC port layer. 12 years ago
Richard Barry 9a15f50b00 Add memory barrier instructions to Tasking CM4F port. 12 years ago
Richard Barry 7132e88685 Add memory barrier instructions to the RVDS CM3 ports. 12 years ago
Richard Barry 895ee2bb3e Add barrier instructions to IAR CM3 ports. 12 years ago
Richard Barry d135e45676 Replace the read back of the software interrupt register with barrier instructions (CCS/RM48/TMS570). 12 years ago
Richard Barry 0527099b51 Add barrier instructions to the GCC CM3 ports. 12 years ago
Richard Barry 6d20e2b5cd Add barrier instructions to GCC CM3/4 code. 12 years ago
Richard Barry 3762630f27 RL78/IAR port - Allow the end user to define their own tick interrupt configuration by defining configSETUP_TIMER_INTERRUPT(). 12 years ago