27ca5c8341
Added portMEMORY_BARRIER() implemented as __asm volatile( "" ::: "memory" ) into ARM Cortex-M33 ports to assist with link time optimisation.
6 years ago
84377442fc
Added portMEMORY_BARRIER() implemented as __asm volatile( "" ::: "memory" ) into ARM GCC ports to assist with link time optimisation.
6 years ago
606845492b
Fix potential memory leak in the Win32 FreeRTOS+TCP network interface initialisation sequence.
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Introduce portMEMORY_BARRIER() macro to assist with memory access ordering when suspending the scheduler if link time optimization is used.
6 years ago
dd9a9710c6
Export port architecture name for COrtex-M33. This can be used by debuggers to find the port in-use to be able to correctly decode the context stored on the stack.
6 years ago
ba39a958b5
Fix spelling of priority in comments.
6 years ago
2265d70499
Correcting spelling mistakes in comments only.
6 years ago
06596c3192
Prepare the RISC-V port layer for addition of 64-bit port.
6 years ago
5623c69748
Fix Build and Links failure in MPU projects. Minor cosmetic changes in some V8M files.
6 years ago
8b6ab5f197
Add instructions on building the Cortex-M33 secure and non secure projects into the comments of that project and into a readme.txt file.
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Enable configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES setting to be used in statically allocated systems.
6 years ago
5849459c65
Add support for running FreeRTOS on Secure Side only in Cortex M33 port. Also, change spaces to tabs.
6 years ago
ce576f3683
First Official Release of ARMV8M Support. This release removes Pre-Release from all the ARMv8M files licensees.
6 years ago
58ba10eee8
Update version number in readiness for V10.2.0 release.
6 years ago
6844bef74f
Replace the pdf RISC-V documentation with links to the documentation web pages.
6 years ago
b2b1b09ea5
Fix bug in core_cm3.c atomic macros.
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Rename the portable/GCC/RISC-V-RV32 directory to just RISC-V as also adding support for 64-bit cores.
6 years ago
fb73829148
Ensure eTaskGetState() is brought in automatically if INCLUDE_xTaskAbortDelay is set to 1, as it is a dependency of eTaskGetState().
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Added the portTASK_FUNCTION_PROTO macros around the timer task, as the macros are already used by the idle task.
Add a PDF of the RISC-V documentation into the repo as the web page is not yet live.
6 years ago
df5952f655
Add xTaskGetIdleRunTimeCounter() API function to return the run time stats counter for the idle task - useful for POSIX time implementations.
6 years ago
11d9c440b8
Move the 'generic' version of freertos_risc_v_chip_specific_extensions.h back to a sub-directory as having it in the RISC-V port's base directory was causing SoftConsole to pick up the wrong version (for an unknown reason).
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Add a project for the Vega board's RI5CY core.
6 years ago
e2af102c80
Re-org of RISC-V file structure and naming step 2.
6 years ago
818eeccc0c
Re-org of RISC-V file structure and naming step 1.
6 years ago
db750d0c82
Update RSIC-V port layer after testing saving and receiving of chip specific registers.
6 years ago
60b133b2c6
Move the RISC-V pxPortInitialiseStack() implementation to the assembly port file from the C port file so it can have access to the number of chip specific registers it needs to save space for on the stack.
6 years ago
d369110167
Allow the size of the stack used by many of the standard demo/test tasks to be overridden by FreeRTOSConfig.h settings.
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Update the Freedom Studio RISC-V project so the 'full' build configuration is now functional.
6 years ago
ce36928ea8
Rename directories in the RISC-V port.
6 years ago
101806906d
Rework RISC-V portASM.S to make it easier to add in chip specific RISC-V extensions and accommodate chips that don't include the CLINT.
6 years ago
7cc42b2ab6
Save changes to the RISC-V port layer before making changes necessary to support pulpino too:
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+ Switch positions of the asm functions used to start the kernel and handle traps to enable one to reference to the other.
+ Handle external interrupts (working with Renode emulator).
+ The _sp linker variable is now called __freertos_irq_stack_top.
6 years ago
65f7a2dc19
Update RISC-V port to use a separate interrupt stack.
6 years ago
e85ea96f78
Some efficiency improvements in Risc-V port.
6 years ago
dc99300fa9
First task running in RISC-V-Qemu-sifive_e-FreedomStudio demo.
6 years ago
db64297487
Provide each Risc V task with an initial mstatus register value.
6 years ago
8cef339aec
Update Risc-V port to use environment call in place of software interrupt - still very much a work in progress.
6 years ago
baee711cb6
Continue work on Risc V port.
6 years ago
e3dc5e934b
RISC-V tasks now context switching to each other using taskYIELD() - not fully tested yet.
7 years ago
2bcb1ab02b
Add trap handler to RISC-V port so there is no dependency on third party code.
7 years ago
32f35e9130
RISC-V:
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Added code to setup the timer interrupt - not tested yet.
Added the taskYIELD() implementation - so far just checked it generates an interrupt.
7 years ago
b11eb3a59c
RISC-V work in progress:
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+ Initialise task stack.
+ Successfully jump to start of first task.
7 years ago
92ae8e7aff
Update version numbers ready for release.
7 years ago
3a1631fda3
Update copyright date ready for tagging V10.1.0.
7 years ago
fb9de58f56
Update version numbers in preparation for a new release.
7 years ago
f6cbf20019
Update RISC-V project to used official port stubs in place of third party port.
7 years ago
3bfc32d444
Add stubs for official RISC-V RV32 port.
7 years ago
5bebf10fa4
Minor updates to comments only.
7 years ago
7ddb8b342d
Microblaze port: Place critical section around XIntc_Enable() to protect read/modify/write operation performed inside the library.
7 years ago
13651934be
Roll up the minor changes checked into svn since V10.0.0 into new V10.0.1 ready for release.
7 years ago
cfc268814a
Update to MIT licensed FreeRTOS V10.0.0 - see https://www.freertos.org/History.txt
7 years ago
037abdddf2
Update TriCore port to work with latest GCC compiler.
8 years ago
6eea3d8d4b
Correct long time mis-spelled portINITIAL_EXEC_RETURN to portINITIAL_EXC_RETURN
8 years ago
b080f13543
Add more "memory" clobbers into the MPU ports to make them robust to more aggressive optimisation in newer GCC version.
8 years ago
0f85ead175
Add more "memory" clobbers into asm code of GCC/ARM_CRx_No_GIC port to make it robust with higher optimisation in newer versions of GCC.
8 years ago
0a7a0a79d6
Updates to prevent warnings when compiled with LLVM.
8 years ago
464c2660ad
Updates to the Cortex-M tickless idle code to reduce clock slippage.
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Updates to prevent the vTaskSwitchContext() function being removed from GCC builds when link time optimisation is used.
8 years ago
Richard Barry
Gaurav Aggarwal