FreeRTOS-Kernel

Commit Graph

Author	SHA1	Message	Date
Gaurav-Aggarwal-AWS	06fb777e43	Update comments for the ARM_CA53_64_BIT_SRE port (#403 ) Mention that FreeRTOS_IRQ_Handler should not be used for FIQs and the reason for assuming Group 1 for Interrupt Acknowledge and End Of Interrupt registers. Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>	3 years ago
Stephane Viau	68ddb32b55	Handle interrupt acknowledge register in Cortex-A53 SRE port (#392 ) Let the FreeRTOS IRQ handler properly store and restore the ICCIAR register value around the vApplicationIRQHandler() call. Signed-off-by: Stephane Viau <stephane.viau@oss.nxp.com> Co-authored-by: Stephane Viau <stephane.viau@oss.nxp.com> Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>	3 years ago
Gaurav-Aggarwal-AWS	4e3bf0f5c0	Add Cortex-A53 port with system register interface for CPU interface access (#357 ) The difference between this port and portable/GCC/ARM_CA53_64_BIT is that this port uses System Register interface to access CPU interface while the other one uses Memory-mapped interface. Signed-off-by: Gaurav Aggarwal Co-authored-by: Cobus van Eeden <35851496+cobusve@users.noreply.github.com>	4 years ago

Author

SHA1

Message

Date

Gaurav-Aggarwal-AWS

06fb777e43

Update comments for the ARM_CA53_64_BIT_SRE port (#403 )

Mention that FreeRTOS_IRQ_Handler should not be used for FIQs and the
reason for assuming Group 1 for Interrupt Acknowledge and End Of
Interrupt registers.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

Stephane Viau

68ddb32b55

Handle interrupt acknowledge register in Cortex-A53 SRE port (#392 )

Let the FreeRTOS IRQ handler properly store and restore the ICCIAR
register value around the vApplicationIRQHandler() call.

Signed-off-by: Stephane Viau <stephane.viau@oss.nxp.com>

Co-authored-by: Stephane Viau <stephane.viau@oss.nxp.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

Gaurav-Aggarwal-AWS

4e3bf0f5c0

Add Cortex-A53 port with system register interface for CPU interface access (#357 )

The difference between this port and portable/GCC/ARM_CA53_64_BIT is
that this port uses System Register interface to access CPU interface
while the other one uses Memory-mapped interface.

Signed-off-by: Gaurav Aggarwal 
Co-authored-by: Cobus van Eeden <35851496+cobusve@users.noreply.github.com>

3 Commits (030e76681b981335ca4f25f0adce09612bf757a5)