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+ + + + + + + + + + + + + + + EXAMINING POTENTIAL INTERFACE . + + + + + + + + + + + + + + + PROC CONNECTIONS + MAST CONNECTIONS + PERI CONNECTIONS + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + TRUE + TRUE + TRUE + FALSE + + + + + + + __NONE__ + + + + + PLACING POTENTIAL INTERFACE . + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + PROJECT + BUSINTERFACE + TREE + + + + + + + + + + PLACING BUS + + + + + + + + + + + + MODULE + + Name + TEXTBOX + INSTANCE + + + + IP Type + STATIC + MODTYPE + + + + IP Version + STATIC + HWVERSION + + + + IP Classification + STATIC + IPCLASS + BUS + + + + + + + + + + + + + + + + + + MODULE + + + Name + TEXTBOX + INSTANCE + + + + IP Type + STATIC + MODTYPE + + + + IP Version + STATIC + HWVERSION + + + + IP Classification + STATIC + IPCLASS + + + + + + + + + + PLACING BIF + TYPE + BUS + + + + TEXTBOX + BUTTON + BUTTON + BUTTON + DROPDOWN + + + + + + & + + + + + + + VIEWTYPE + BUSNAME + + + BUSINTERFACE + + NAME + STATIC + NAME + + + + Bus Name + + BUSNAME + + + + Type + STATIC + TYPE + + + + Bus Standard + STATIC + BUSSTD + + + + + + + + + + PROCESSOR GROUP + + + + + GROUP + + NAME + STATIC + INSTANCE + Subsystem of + + + + + + + + + + MASTER GROUP + + + + + GROUP + + NAME + STATIC + INSTANCE + Subsystem of + + + + + + + + + + + PLACING SHARED PERIPHERALS + + + GROUP + + NAME + STATIC + INSTANCE + Peripherals shared by + + + + + + + + + PLACING MEMORY + + + + GROUP + + NAME + STATIC + INSTANCE + (Memory) + + + + + + + + + PLACING PERIPHERAL + + + + + + + PLACING SLAVES + + + + + + + + + + + + + + diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/edw2xtl_sav_view_port.xsl b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/edw2xtl_sav_view_port.xsl new file mode 100644 index 000000000..5cfc3be61 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/edw2xtl_sav_view_port.xsl @@ -0,0 +1,771 @@ + + + + + + + + + + + + +]> + + + + + + + + + + + + + WRITING PORT in MODE : + + + + + + + + + + + + + + + + + + + + + + + + ExternalPorts + MODULE + + + + + Name + External Ports + Name + STATIC + + + + + + + + + PORT + + + + + + + + + + + + + + + + [:] + + + + [:] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + TRUE + TRUE + FALSE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + __NONE__ + + + + + + + + __NONE__ + + + + + + + __NONE__ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + __NONE__ + + + + + + + + __NONE__ + + + + + + + __NONE__ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Connected to BUS + Connected to External Ports + Not connected to BUS or External Ports + + + + + + + + BUSINTERFACE.PORTS + + + TRUE + + + + + + + + + + + + + + + + + + + __NONE__ + + + + + + + + __NONE__ + + + + + + + __NONE__ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Connected to External Ports + Not connected to External Ports + + + + + + + IOINTERFACE.PORTS + + + TRUE + + + + + + + + + + + + + + + + + + + + + __NONE__ + + + + + + + + __NONE__ + + + + + + + __NONE__ + + + + + + + + + + + + + + + + + + + + + + + + + WRITING PORT MODE + + + + + + + + + + + + + + + + + + + + + + + + + + + TRUE + FALSE + + + + + + + + + + [:] + + + + [:] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + TRUE + TRUE + FALSE + + + + + + + + + + has valid ports + + + + + + + + + + + + FALSE + TRUE + TRUE + FALSE + + + + + + + + + + + + + + + + + + + + + + + + + + + + TRUE + FALSE + + + + + TRUE + TRUE + TRUE + FALSE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + TRUE + FALSE + + + + + TRUE + TRUE + TRUE + FALSE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/gensav_cmd.xml b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/gensav_cmd.xml new file mode 100644 index 000000000..42f1efa6c --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/gensav_cmd.xml @@ -0,0 +1,2 @@ + + \ No newline at end of file diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/_xmsgs/platgen.xmsgs b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/_xmsgs/platgen.xmsgs new file mode 100644 index 000000000..a52da2680 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/_xmsgs/platgen.xmsgs @@ -0,0 +1,141 @@ + + + +IPNAME: axi_interconnect, INSTANCE:axi4_0 - tcl is overriding PARAMETER C_BASEFAMILY value to spartan6 - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_02_a\data\axi_interconnect_v2_1_0.mpd line 69 + + +IPNAME: axi_interconnect, INSTANCE:axi4lite_0 - tcl is overriding PARAMETER C_BASEFAMILY value to spartan6 - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_02_a\data\axi_interconnect_v2_1_0.mpd line 69 + + +IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding PARAMETER C_ENDIANNESS value to 1 - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_10_a\data\microblaze_v2_1_0.mpd line 183 + + +IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding PARAMETER C_ICACHE_USE_FSL value to 0 - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_10_a\data\microblaze_v2_1_0.mpd line 322 + + +IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding PARAMETER C_DCACHE_USE_FSL value to 0 - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_10_a\data\microblaze_v2_1_0.mpd line 352 + + +IPNAME: axi_s6_ddrx, INSTANCE:MCB_DDR3 - tcl is overriding PARAMETER C_SYS_RST_PRESENT value to 1 - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_02_a\data\axi_s6_ddrx_v2_1_0.mpd line 228 + + +Cannot determine the input clock associated with port : microblaze_0_i_bram_ctrl:BRAM_Clk_A. Clock DRCs will not be performed on this core and cores connected to it. + + +Cannot determine the input clock associated with port : microblaze_0_d_bram_ctrl:BRAM_Clk_A. Clock DRCs will not be performed on this core and cores connected to it. + + +IPNAME: axi_ethernetlite, INSTANCE: Ethernet_Lite - This design requires design constraints to guarantee performance. +Please refer to the data sheet for details. +The AXI clock frequency must be greater than or equal to 50 MHz for 100 Mbs Ethernet operation and greater than or equal to 5.0 MHz for 10 Mbs Ethernet operation. - C:\E\Dev\FreeRTOS\WorkingCopy\Demo\MicroBlaze_Spartan-6_SP605\system.mhs line 324 + + +IPNAME: lmb_v10, INSTANCE:microblaze_0_ilmb - tool is overriding PARAMETER C_LMB_NUM_SLAVES value to 1 - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v2_00_a\data\lmb_v10_v2_1_0.mpd line 70 + + +IPNAME: lmb_v10, INSTANCE:microblaze_0_dlmb - tool is overriding PARAMETER C_LMB_NUM_SLAVES value to 1 - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v2_00_a\data\lmb_v10_v2_1_0.mpd line 70 + + +IPNAME: bram_block, INSTANCE:microblaze_0_bram_block - tool is overriding PARAMETER C_MEMSIZE value to 0x2000 - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.mpd line 67 + + +PORT: bscan_tdo1, CONNECTOR: bscan_tdo1 - No driver found. Port will be driven to GND - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v2_00_b\data\mdm_v2_1_0.mpd line 230 + + +PORT: bscan_tdi, CONNECTOR: bscan_tdi - floating connection - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v2_00_b\data\mdm_v2_1_0.mpd line 223 + + +PORT: bscan_reset, CONNECTOR: bscan_reset - floating connection - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v2_00_b\data\mdm_v2_1_0.mpd line 224 + + +PORT: bscan_shift, CONNECTOR: bscan_shift - floating connection - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v2_00_b\data\mdm_v2_1_0.mpd line 225 + + +PORT: bscan_update, CONNECTOR: bscan_update - floating connection - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v2_00_b\data\mdm_v2_1_0.mpd line 226 + + +PORT: bscan_capture, CONNECTOR: bscan_capture - floating connection - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v2_00_b\data\mdm_v2_1_0.mpd line 227 + + +PORT: bscan_sel1, CONNECTOR: bscan_sel1 - floating connection - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v2_00_b\data\mdm_v2_1_0.mpd line 228 + + +PORT: bscan_drck1, CONNECTOR: bscan_drck1 - floating connection - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v2_00_b\data\mdm_v2_1_0.mpd line 229 + + +IPNAME: axi_interconnect, INSTANCE:axi4_0 - tcl is overriding PARAMETER C_RANGE_CHECK value to 0 - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_02_a\data\axi_interconnect_v2_1_0.mpd line 137 + + +IPNAME: axi_interconnect, INSTANCE:axi4lite_0 - tcl is overriding PARAMETER C_RANGE_CHECK value to 1 - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_02_a\data\axi_interconnect_v2_1_0.mpd line 137 + + +IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding PARAMETER C_D_AXI value to 1 - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_10_a\data\microblaze_v2_1_0.mpd line 216 + + +IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding PARAMETER C_ADDR_TAG_BITS value to 13 - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_10_a\data\microblaze_v2_1_0.mpd line 320 + + +IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding PARAMETER C_DCACHE_ADDR_TAG value to 13 - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_10_a\data\microblaze_v2_1_0.mpd line 350 + + +IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding PARAMETER C_USE_INTERRUPT value to 1 - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_10_a\data\microblaze_v2_1_0.mpd line 384 + + +IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding PARAMETER C_USE_EXT_BRK value to 1 - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_10_a\data\microblaze_v2_1_0.mpd line 385 + + +IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding PARAMETER C_USE_EXT_NM_BRK value to 1 - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_10_a\data\microblaze_v2_1_0.mpd line 386 + + +IPNAME: lmb_bram_if_cntlr, INSTANCE:microblaze_0_i_bram_ctrl - tcl is overriding PARAMETER C_MASK value to 0x40000000 - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v3_00_a\data\lmb_bram_if_cntlr_v2_1_0.mpd line 78 + + +IPNAME: lmb_bram_if_cntlr, INSTANCE:microblaze_0_d_bram_ctrl - tcl is overriding PARAMETER C_MASK value to 0x40000000 - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v3_00_a\data\lmb_bram_if_cntlr_v2_1_0.mpd line 78 + + +IPNAME: axi_s6_ddrx, INSTANCE:MCB_DDR3 - tcl is overriding PARAMETER C_MEMCLK_PERIOD value to 3333 - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_02_a\data\axi_s6_ddrx_v2_1_0.mpd line 110 + + +IPNAME: axi_s6_ddrx, INSTANCE:MCB_DDR3 - tcl is overriding PARAMETER C_S0_AXI_STRICT_COHERENCY value to 0 - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_02_a\data\axi_s6_ddrx_v2_1_0.mpd line 153 + + +IPNAME: axi_s6_ddrx, INSTANCE:MCB_DDR3 - tcl is overriding PARAMETER C_S1_AXI_REG_EN0 value to 0x0000F - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_02_a\data\axi_s6_ddrx_v2_1_0.mpd line 165 + + +IPNAME: axi_s6_ddrx, INSTANCE:MCB_DDR3 - tcl is overriding PARAMETER C_S2_AXI_REG_EN0 value to 0x0000F - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_02_a\data\axi_s6_ddrx_v2_1_0.mpd line 179 + + +IPNAME: axi_s6_ddrx, INSTANCE:MCB_DDR3 - tcl is overriding PARAMETER C_S3_AXI_REG_EN0 value to 0x0000F - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_02_a\data\axi_s6_ddrx_v2_1_0.mpd line 193 + + +IPNAME: axi_s6_ddrx, INSTANCE:MCB_DDR3 - tcl is overriding PARAMETER C_S4_AXI_REG_EN0 value to 0x0000F - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_02_a\data\axi_s6_ddrx_v2_1_0.mpd line 207 + + +IPNAME: axi_s6_ddrx, INSTANCE:MCB_DDR3 - tcl is overriding PARAMETER C_S5_AXI_REG_EN0 value to 0x0000F - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_02_a\data\axi_s6_ddrx_v2_1_0.mpd line 221 + + +IPNAME: axi_intc, INSTANCE:microblaze_0_intc - tcl is overriding PARAMETER C_NUM_INTR_INPUTS value to 4 - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_intc_v1_01_a\data\axi_intc_v2_1_0.mpd line 71 + + +IPNAME: axi_intc, INSTANCE:microblaze_0_intc - tcl is overriding PARAMETER C_KIND_OF_INTR value to 0b11111111111111111111111111111011 - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_intc_v1_01_a\data\axi_intc_v2_1_0.mpd line 72 + + +IPNAME: axi_intc, INSTANCE:microblaze_0_intc - tcl is overriding PARAMETER C_KIND_OF_EDGE value to 0b11111111111111111111111111111111 - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_intc_v1_01_a\data\axi_intc_v2_1_0.mpd line 73 + + +IPNAME: axi_intc, INSTANCE:microblaze_0_intc - tcl is overriding PARAMETER C_KIND_OF_LVL value to 0b11111111111111111111111111111111 - C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_intc_v1_01_a\data\axi_intc_v2_1_0.mpd line 74 + + +The following instances are synthesized with XST. The MPD option IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized. + + +NCF files should not be modified as they will be regenerated. +If any constraint needs to be overridden, this should be done by modifying the data/system.ucf file. + + + + diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/system.xreport b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/system.xreport new file mode 100644 index 000000000..6ff58f4fa --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/system.xreport @@ -0,0 +1,218 @@ + + +
+ 2011-05-31T10:04:43 + system + 2011-05-31T10:04:43 + C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/system.xreport + filter.filter + C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise + 2011-05-30T21:44:59 + false +
+ + + + + + + + + + + + + + + + + + + + + + + diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/xmsgprops.lst b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/xmsgprops.lst new file mode 100644 index 000000000..10c9bb7ac --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/xmsgprops.lst @@ -0,0 +1,3 @@ +MessageCaptureEnabled: TRUE +MessageFilteringEnabled: FALSE +IncrementalMessagingEnabled: TRUE diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/platgen.opt b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/platgen.opt new file mode 100644 index 000000000..761753810 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/platgen.opt @@ -0,0 +1,2 @@ + -p xc6slx45tfgg484-3 -lang vhdl$(PROJECT_SEARCHPATHOPT) $(GLOBAL_SEARCHPATHOPT) -msg __xps/ise/xmsgprops.lst + diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/simgen.opt b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/simgen.opt new file mode 100644 index 000000000..9fbb0051c --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/simgen.opt @@ -0,0 +1 @@ + -p spartan6 -lang vhdl$(PROJECT_SEARCHPATHOPT) $(GLOBAL_SEARCHPATHOPT) -msg __xps/ise/xmsgprops.lst -s isim diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/system.xml b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/system.xml new file mode 100644 index 000000000..992659d8b --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/system.xml @@ -0,0 +1,5243 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AXI Interconnect + AXI4 Memory-Mapped Interconnect + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + Ethernet PHY Management Clock + + + Ethernet Transmit Data Output + + + Ethernet Transmit Enable + + + Ethernet Transmit Clock Input + + + Ethernet Collision Input + + + Ethernet Receive Data Input + + + Ethernet Receive Error Input + + + Ethernet Receive Clock Input + + + Ethernet Carrier Sense Input + + + Ethernet Receive Data Valid + + + Ethernet PHY Reset + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AXI Timer/Counter + Timer counter with AXI interface + + + + + + + + + + + + + + + + + + + + + + + + + + + + Capture Trig 0 + + + Capture Trig 1 + + + Generate Out 0 + + + Generate Out 1 + + + Pulse Width Modulation 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AXI Interrupt Controller + intc core attached to the AXI + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Interrupt Request Output + + + + + + + + + + Interrupt Inputs + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/xplorer.opt b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/xplorer.opt new file mode 100644 index 000000000..1ba7dad07 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/xplorer.opt @@ -0,0 +1 @@ + -device xc6slx45tfgg484-3 data/system.ucf 7 0 diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/xpsxflow.opt b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/xpsxflow.opt new file mode 100644 index 000000000..51c612843 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/xpsxflow.opt @@ -0,0 +1 @@ + -device xc6slx45tfgg484-3 data/system.ucf 0 diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/data/system.ucf b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/data/system.ucf new file mode 100644 index 000000000..681ad6274 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/data/system.ucf @@ -0,0 +1,41 @@ +# +# pin constraints +# +NET CLK_N LOC = "K22" | DIFF_TERM = "TRUE" | IOSTANDARD = "LVDS_25"; +NET CLK_P LOC = "K21" | DIFF_TERM = "TRUE" | IOSTANDARD = "LVDS_25"; +NET Ethernet_Lite_COL LOC = "M16" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_CRS LOC = "N15" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_MDC LOC = "R19" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_MDIO LOC = "V20" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_PHY_RST_N LOC = "J22" | IOSTANDARD = "LVCMOS25" | TIG; +NET Ethernet_Lite_RXD[0] LOC = "P19" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_RXD[1] LOC = "Y22" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_RXD[2] LOC = "Y21" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_RXD[3] LOC = "W22" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_RX_CLK LOC = "P20" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_RX_DV LOC = "T22" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_RX_ER LOC = "U20" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_TXD[0] LOC = "U10" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_TXD[1] LOC = "T10" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_TXD[2] LOC = "AB8" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_TXD[3] LOC = "AA8" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_TX_CLK LOC = "L20" | IOSTANDARD = "LVCMOS25"; +NET Ethernet_Lite_TX_EN LOC = "T8" | IOSTANDARD = "LVCMOS25"; +NET LEDs_4Bits_TRI_O[0] LOC = "D17" | IOSTANDARD = "LVCMOS25"; +NET LEDs_4Bits_TRI_O[1] LOC = "AB4" | IOSTANDARD = "LVCMOS25"; +NET LEDs_4Bits_TRI_O[2] LOC = "D21" | IOSTANDARD = "LVCMOS25"; +NET LEDs_4Bits_TRI_O[3] LOC = "W15" | IOSTANDARD = "LVCMOS25"; +NET Push_Buttons_4Bits_TRI_I[0] LOC = "F3" | IOSTANDARD = "LVCMOS25"; +NET Push_Buttons_4Bits_TRI_I[1] LOC = "G6" | IOSTANDARD = "LVCMOS25"; +NET Push_Buttons_4Bits_TRI_I[2] LOC = "F5" | IOSTANDARD = "LVCMOS25"; +NET Push_Buttons_4Bits_TRI_I[3] LOC = "C1" | IOSTANDARD = "LVCMOS25"; +NET RESET LOC = "H8" | IOSTANDARD = "LVCMOS15" | TIG; +NET RS232_Uart_1_sin LOC = "H17" | IOSTANDARD = "LVCMOS25"; +NET RS232_Uart_1_sout LOC = "B21" | IOSTANDARD = "LVCMOS25"; +# +# additional constraints +# + +NET "CLK" TNM_NET = sys_clk_pin; +TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 200000 kHz; + diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/etc/bitgen.ut b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/etc/bitgen.ut new file mode 100644 index 000000000..bca21c81b --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/etc/bitgen.ut @@ -0,0 +1,3 @@ +-g TdoPin:PULLNONE +-g StartUpClk:JTAGCLK +#add other options here. diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/etc/download.cmd b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/etc/download.cmd new file mode 100644 index 000000000..da4d7717e --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/etc/download.cmd @@ -0,0 +1,6 @@ +setMode -bscan +setCable -p auto +identify +assignfile -p 2 -file implementation/download.bit +program -p 2 +quit diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/etc/fast_runtime.opt b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/etc/fast_runtime.opt new file mode 100644 index 000000000..994a6d2f8 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/etc/fast_runtime.opt @@ -0,0 +1,84 @@ +FLOWTYPE = FPGA; +############################################################### +## Filename: fast_runtime.opt +## +## Option File For Xilinx FPGA Implementation Flow for Fast +## Runtime. +## +## Version: 4.1.1 +############################################################### +# +# Options for Translator +# +# Type "ngdbuild -h" for a detailed list of ngdbuild command line options +# +Program ngdbuild +-p ; # Partname to use - picked from xflow commandline +-nt timestamp; # NGO File generation. Regenerate only when + # source netlist is newer than existing + # NGO file (default) +-bm .bmm # Block RAM memory map file +; # User design - pick from xflow command line +-uc .ucf; # ucf constraints +.ngd; # Name of NGD file. Filebase same as design filebase +End Program ngdbuild + +# +# Options for Mapper +# +# Type "map -h " for a detailed list of map command line options +# +Program map +-o _map.ncd; # Output Mapped ncd file +-w; # Overwrite output files. +-pr b; # Pack internal FF/latches into IOBs +#-fp .mfp; # Floorplan file +-ol high; +-timing; +-detail; +.ngd; # Input NGD file +.pcf; # Physical constraints file +END Program map + +# +# Options for Post Map Trace +# +# Type "trce -h" for a detailed list of trce command line options +# +Program post_map_trce +-e 3; # Produce error report limited to 3 items per constraint +#-o _map.twr; # Output trace report file +-xml _map.twx; # Output XML version of the timing report +#-tsi _map.tsi; # Produce Timing Specification Interaction report +_map.ncd; # Input mapped ncd +.pcf; # Physical constraints file +END Program post_map_trce + +# +# Options for Place and Route +# +# Type "par -h" for a detailed list of par command line options +# +Program par +-w; # Overwrite existing placed and routed ncd +-ol high; # Overall effort level +_map.ncd; # Input mapped NCD file +.ncd; # Output placed and routed NCD +.pcf; # Input physical constraints file +END Program par + +# +# Options for Post Par Trace +# +# Type "trce -h" for a detailed list of trce command line options +# +Program post_par_trce +-e 3; # Produce error report limited to 3 items per constraint +#-o .twr; # Output trace report file +-xml .twx; # Output XML version of the timing report +#-tsi .tsi; # Produce Timing Specification Interaction report +.ncd; # Input placed and routed ncd +.pcf; # Physical constraints file +END Program post_par_trce + + diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/etc/system.filters b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/etc/system.filters new file mode 100644 index 000000000..db9a31b74 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/etc/system.filters @@ -0,0 +1,158 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/etc/system.gui b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/etc/system.gui new file mode 100644 index 000000000..cc7d6cf4a --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/etc/system.gui @@ -0,0 +1,195 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/implementation/system_summary.html b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/implementation/system_summary.html new file mode 100644 index 000000000..0ff23f2cf --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/implementation/system_summary.html @@ -0,0 +1,66 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + +
system Project Status
Project File:system.xmpImplementation State:New
Module Name:system
  • Errors:
 
Product Version:EDK 13.1
  • Warnings:
 
+ + + + 
+ + + + + + + + +
XPS Reports [-]
Report NameGeneratedErrorsWarningsInfos
Platgen Log File    
Libgen Log File    
Simgen Log File    
BitInit Log File    
System Log File    
+ 
+ + +
XPS Synthesis Summary (estimated values) [-]
ReportGeneratedFlip Flops UsedLUTs UsedBRAMS UsedErrors
+ + + + + + + + + 
+ + + + + + + + +
Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Translation Report     
Map Report     
Place and Route Report     
Post-PAR Static Timing Report     
Bitgen Report     
+ 
+ + +
Secondary Reports [-]
Report NameStatusGenerated
+ + +
Date Generated: 05/31/2011 - 10:04:43
+ \ No newline at end of file diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/system.bsb b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/system.bsb new file mode 100644 index 000000000..61ea89e9e --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/system.bsb @@ -0,0 +1 @@ +Įtt@Dbb\b\`bDv*Įtt@D\D@Dl`jD@DDv.Įttʄ@DD@DlDv.Įttʄ@DD@DlhjDv'Įttʄ@DD@DhphDv'Įttʄ@DD@DbDv&Įttʄ@DD@DZfDv%Įtt@DľҾbD@Db\`Dv;Įttʦ@D־D@Dd````````D@Dʾ`Dv@ĮttȠ@Dʾ`D@DD@Dʾ`DvHĮttʆ@Dʾ`D@D¾ʾھD@DfDvAĮttʆ@Dʾ`D@D¾ʾD@DblfphDvIĮttʆ@Dʾ`D@DʾھD@DfDvBĮttʆ@Dʾ`D@DʾD@DblfphDvHĮttʆ@Dʾ`D@Dľ־D@Db````````Dv>Įttʆ@Dʾ`D@DľD@DDvEĮttʆ@Dʾ`D@DľؾD@DpbrdDvHĮttȠ@D辘D@DҾD@Dʾ`DvBĮttʆ@D辘D@DʾD@DDv=ĮttȠ@DhD@DҾD@Dʾ`Dv@Įttʆ@DhD@DʾD@DDv>ĮttȠ@DfD@DҾlD@Dʾ`DvEĮttȠ@DоhD@DҾD@Dʾ`DvGĮttʆ@DоhD@DʾD@DDvCĮttȠ@DdfdbD@DҾD@Dʾ`DvCĮttʆ@DdfdbD@D`ȾD@Dbbjd``Dv>Įttʆ@DdfdbD@D`D@DpDv>Įttʆ@DdfdbD@D`D@DDvAĮttʆ@DdfdbD@DʾD@DDv?ĮttȠ@DҾ`D@DҾD@Dʾ`Dv@Įttʆ@DҾ`D@DʾD@DDv \ No newline at end of file diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/system.make b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/system.make new file mode 100644 index 000000000..ca8e6d0f4 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/system.make @@ -0,0 +1,216 @@ +################################################################# +# Makefile generated by Xilinx Platform Studio +# Project:C:\E\Dev\FreeRTOS\WorkingCopy\Demo\MicroBlaze_Spartan-6_EthernetLite\PlatformStudioProject\system.xmp +# +# WARNING : This file will be re-generated every time a command +# to run a make target is invoked. So, any changes made to this +# file manually, will be lost when make is invoked next. +################################################################# + +# Name of the Microprocessor system +# The hardware specification of the system is in file : +# C:\E\Dev\FreeRTOS\WorkingCopy\Demo\MicroBlaze_Spartan-6_EthernetLite\PlatformStudioProject\system.mhs + +include system_incl.make + +################################################################# +# PHONY TARGETS +################################################################# +.PHONY: dummy +.PHONY: netlistclean +.PHONY: bitsclean +.PHONY: simclean +.PHONY: exporttosdk + +################################################################# +# EXTERNAL TARGETS +################################################################# +all: + @echo "Makefile to build a Microprocessor system :" + @echo "Run make with any of the following targets" + @echo " " + @echo " netlist : Generates the netlist for the given MHS " + @echo " bits : Runs Implementation tools to generate the bitstream" + @echo " exporttosdk: Export files to SDK" + @echo " " + @echo " init_bram: Initializes bitstream with BRAM data" + @echo " ace : Generate ace file from bitstream and elf" + @echo " download : Downloads the bitstream onto the board" + @echo " " + @echo " sim : Generates HDL simulation models and runs simulator for chosen simulation mode" + @echo " simmodel : Generates HDL simulation models for chosen simulation mode" + @echo " " + @echo " netlistclean: Deletes netlist" + @echo " bitsclean: Deletes bit, ncd, bmm files" + @echo " hwclean : Deletes implementation dir" + @echo " simclean : Deletes simulation dir" + @echo " clean : Deletes all generated files/directories" + @echo " " + +bits: $(SYSTEM_BIT) + +ace: $(SYSTEM_ACE) + +exporttosdk: $(SYSTEM_HW_HANDOFF_DEP) + +netlist: $(POSTSYN_NETLIST) + +download: $(DOWNLOAD_BIT) dummy + @echo "*********************************************" + @echo "Downloading Bitstream onto the target board" + @echo "*********************************************" + impact -batch etc/download.cmd + +init_bram: $(DOWNLOAD_BIT) + +sim: $(DEFAULT_SIM_SCRIPT) + cd simulation/behavioral & \ + system_fuse.cmd + cd simulation/behavioral & \ + start /B $(SIM_CMD) -gui -tclbatch system_setup.tcl + +simmodel: $(DEFAULT_SIM_SCRIPT) + +behavioral_model: $(BEHAVIORAL_SIM_SCRIPT) + +structural_model: $(STRUCTURAL_SIM_SCRIPT) + +clean: hwclean simclean + rm -f _impact.cmd + +hwclean: netlistclean bitsclean + rm -rf implementation synthesis xst hdl + rm -rf xst.srp $(SYSTEM).srp + rm -f __xps/ise/_xmsgs/bitinit.xmsgs + +netlistclean: + rm -f $(POSTSYN_NETLIST) + rm -f platgen.log + rm -f __xps/ise/_xmsgs/platgen.xmsgs + rm -f $(BMM_FILE) + +bitsclean: + rm -f $(SYSTEM_BIT) + rm -f implementation/$(SYSTEM).ncd + rm -f implementation/$(SYSTEM)_bd.bmm + rm -f implementation/$(SYSTEM)_map.ncd + rm -f implementation/download.bit + rm -f __xps/$(SYSTEM)_routed + +simclean: + rm -rf simulation/behavioral + rm -f simgen.log + rm -f __xps/ise/_xmsgs/simgen.xmsgs + +################################################################# +# BOOTLOOP ELF FILES +################################################################# + + +$(MICROBLAZE_0_BOOTLOOP): $(MICROBLAZE_BOOTLOOP_LE) + IF NOT EXIST "$(BOOTLOOP_DIR)" @mkdir "$(BOOTLOOP_DIR)" + cp -f $(MICROBLAZE_BOOTLOOP_LE) $(MICROBLAZE_0_BOOTLOOP) + +################################################################# +# HARDWARE IMPLEMENTATION FLOW +################################################################# + + +$(BMM_FILE) \ +$(WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \ + $(CORE_STATE_DEVELOPMENT_FILES) + @echo "****************************************************" + @echo "Creating system netlist for hardware specification.." + @echo "****************************************************" + platgen $(PLATGEN_OPTIONS) $(MHSFILE) + +$(POSTSYN_NETLIST): $(WRAPPER_NGC_FILES) + @echo "Running synthesis..." + cd synthesis & synthesis.cmd + +__xps/$(SYSTEM)_routed: $(FPGA_IMP_DEPENDENCY) + @echo "*********************************************" + @echo "Running Xilinx Implementation tools.." + @echo "*********************************************" + @cp -f $(UCF_FILE) implementation/$(SYSTEM).ucf + @cp -f etc/fast_runtime.opt implementation/xflow.opt + xflow -wd implementation -p $(DEVICE) -implement xflow.opt $(SYSTEM).ngc + touch __xps/$(SYSTEM)_routed + +$(SYSTEM_BIT): __xps/$(SYSTEM)_routed $(BITGEN_UT_FILE) + xilperl $(XILINX_EDK_DIR)/data/fpga_impl/observe_par.pl $(OBSERVE_PAR_OPTIONS) implementation/$(SYSTEM).par + @echo "*********************************************" + @echo "Running Bitgen.." + @echo "*********************************************" + @cp -f $(BITGEN_UT_FILE) implementation/bitgen.ut + cd implementation & bitgen -w -f bitgen.ut $(SYSTEM) & cd .. + +$(DOWNLOAD_BIT): $(SYSTEM_BIT) $(BRAMINIT_ELF_IMP_FILES) __xps/bitinit.opt + @cp -f implementation/$(SYSTEM)_bd.bmm . + @echo "*********************************************" + @echo "Initializing BRAM contents of the bitstream" + @echo "*********************************************" + bitinit -p $(DEVICE) $(MHSFILE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_IMP_FILE_ARGS) \ + -bt $(SYSTEM_BIT) -o $(DOWNLOAD_BIT) + @rm -f $(SYSTEM)_bd.bmm + +$(SYSTEM_ACE): + @echo "In order to generate ace file, you must have:-" + @echo "- exactly one processor." + @echo "- opb_mdm, if using microblaze." + +################################################################# +# EXPORT_TO_SDK FLOW +################################################################# + +$(SYSTEM_HW_HANDOFF): $(MHSFILE) __xps/platgen.opt + IF NOT EXIST "$(SDK_EXPORT_DIR)" @mkdir "$(SDK_EXPORT_DIR)" + psf2Edward -inp $(SYSTEM).xmp -exit_on_error -edwver 1.2 -xml $(SDK_EXPORT_DIR)/$(SYSTEM).xml $(GLOBAL_SEARCHPATHOPT) + xdsgen -inp $(SYSTEM).xmp -report $(SDK_EXPORT_DIR)/$(SYSTEM).html $(GLOBAL_SEARCHPATHOPT) -make_docs_local + +$(SYSTEM_HW_HANDOFF_BIT): $(SYSTEM_BIT) + @rm -rf $(SYSTEM_HW_HANDOFF_BIT) + @cp -f $(SYSTEM_BIT) $(SDK_EXPORT_DIR) + +$(SYSTEM_HW_HANDOFF_BMM): implementation/$(SYSTEM)_bd.bmm + @rm -rf $(SYSTEM_HW_HANDOFF_BMM) + @cp -f implementation/$(SYSTEM)_bd.bmm $(SDK_EXPORT_DIR) + +################################################################# +# SIMULATION FLOW +################################################################# + + +################## BEHAVIORAL SIMULATION ################## + +$(BEHAVIORAL_SIM_SCRIPT): $(MHSFILE) __xps/simgen.opt \ + $(BRAMINIT_ELF_SIM_FILES) + @echo "*********************************************" + @echo "Creating behavioral simulation models..." + @echo "*********************************************" + simgen $(SIMGEN_OPTIONS) -m behavioral $(MHSFILE) + +################## STRUCTURAL SIMULATION ################## + +$(STRUCTURAL_SIM_SCRIPT): $(WRAPPER_NGC_FILES) __xps/simgen.opt \ + $(BRAMINIT_ELF_SIM_FILES) + @echo "*********************************************" + @echo "Creating structural simulation models..." + @echo "*********************************************" + simgen $(SIMGEN_OPTIONS) -sd implementation -m structural $(MHSFILE) + + +################## TIMING SIMULATION ################## + +implementation/$(SYSTEM).ncd: __xps/$(SYSTEM)_routed + +$(TIMING_SIM_SCRIPT): implementation/$(SYSTEM).ncd __xps/simgen.opt \ + $(BRAMINIT_ELF_SIM_FILES) + @echo "*********************************************" + @echo "Creating timing simulation models..." + @echo "*********************************************" + simgen $(SIMGEN_OPTIONS) -sd implementation -m timing $(MHSFILE) + +dummy: + @echo "" + diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/system.mhs b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/system.mhs new file mode 100644 index 000000000..c4fd90865 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/system.mhs @@ -0,0 +1,387 @@ + +# ############################################################################## +# Created by Base System Builder Wizard for Xilinx EDK 13.1 Build EDK_O.40d +# Mon May 30 21:43:34 2011 +# Target Board: xilinx.com sp605 Rev C +# Family: spartan6 +# Device: xc6slx45t +# Package: fgg484 +# Speed Grade: -3 +# ############################################################################## + PARAMETER VERSION = 2.1.0 + + + PORT RESET = RESET, DIR = I, SIGIS = RST, RST_POLARITY = 1 + PORT CLK_P = CLK, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 200000000 + PORT CLK_N = CLK, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 200000000 + PORT RS232_Uart_1_sout = RS232_Uart_1_sout, DIR = O + PORT RS232_Uart_1_sin = RS232_Uart_1_sin, DIR = I + PORT LEDs_4Bits_TRI_O = LEDs_4Bits_TRI_O, DIR = O, VEC = [0:3] + PORT Push_Buttons_4Bits_TRI_I = Push_Buttons_4Bits_TRI_I, DIR = I, VEC = [3:0] + PORT mcbx_dram_clk = mcbx_dram_clk, DIR = O + PORT mcbx_dram_clk_n = mcbx_dram_clk_n, DIR = O + PORT mcbx_dram_cke = mcbx_dram_cke, DIR = O + PORT mcbx_dram_odt = mcbx_dram_odt, DIR = O + PORT mcbx_dram_ras_n = mcbx_dram_ras_n, DIR = O + PORT mcbx_dram_cas_n = mcbx_dram_cas_n, DIR = O + PORT mcbx_dram_we_n = mcbx_dram_we_n, DIR = O + PORT mcbx_dram_udm = mcbx_dram_udm, DIR = O + PORT mcbx_dram_ldm = mcbx_dram_ldm, DIR = O + PORT mcbx_dram_ba = mcbx_dram_ba, DIR = O, VEC = [2:0] + PORT mcbx_dram_addr = mcbx_dram_addr, DIR = O, VEC = [12:0] + PORT mcbx_dram_ddr3_rst = mcbx_dram_ddr3_rst, DIR = O + PORT mcbx_dram_dq = mcbx_dram_dq, DIR = IO, VEC = [15:0] + PORT mcbx_dram_dqs = mcbx_dram_dqs, DIR = IO + PORT mcbx_dram_dqs_n = mcbx_dram_dqs_n, DIR = IO + PORT mcbx_dram_udqs = mcbx_dram_udqs, DIR = IO + PORT mcbx_dram_udqs_n = mcbx_dram_udqs_n, DIR = IO + PORT rzq = rzq, DIR = IO + PORT zio = zio, DIR = IO + PORT Ethernet_Lite_MDIO = Ethernet_Lite_MDIO, DIR = IO + PORT Ethernet_Lite_MDC = Ethernet_Lite_MDC, DIR = O + PORT Ethernet_Lite_TXD = Ethernet_Lite_TXD, DIR = O, VEC = [3:0] + PORT Ethernet_Lite_TX_EN = Ethernet_Lite_TX_EN, DIR = O + PORT Ethernet_Lite_TX_CLK = Ethernet_Lite_TX_CLK, DIR = I + PORT Ethernet_Lite_COL = Ethernet_Lite_COL, DIR = I + PORT Ethernet_Lite_RXD = Ethernet_Lite_RXD, DIR = I, VEC = [3:0] + PORT Ethernet_Lite_RX_ER = Ethernet_Lite_RX_ER, DIR = I + PORT Ethernet_Lite_RX_CLK = Ethernet_Lite_RX_CLK, DIR = I + PORT Ethernet_Lite_CRS = Ethernet_Lite_CRS, DIR = I + PORT Ethernet_Lite_RX_DV = Ethernet_Lite_RX_DV, DIR = I + PORT Ethernet_Lite_PHY_RST_N = Ethernet_Lite_PHY_RST_N, DIR = O + + +BEGIN axi_interconnect + PARAMETER INSTANCE = axi4_0 + PARAMETER HW_VER = 1.02.a + PORT interconnect_aclk = clk_100_0000MHzPLL0 + PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn +END + +BEGIN axi_interconnect + PARAMETER INSTANCE = axi4lite_0 + PARAMETER HW_VER = 1.02.a + PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0 + PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn + PORT INTERCONNECT_ACLK = clk_50_0000MHzPLL0 +END + +BEGIN microblaze + PARAMETER INSTANCE = microblaze_0 + PARAMETER HW_VER = 8.10.a + PARAMETER C_INTERCONNECT = 2 + PARAMETER C_USE_BARREL = 1 + PARAMETER C_USE_FPU = 1 + PARAMETER C_DEBUG_ENABLED = 1 + PARAMETER C_ICACHE_BASEADDR = 0xc0000000 + PARAMETER C_ICACHE_HIGHADDR = 0xc7ffffff + PARAMETER C_USE_ICACHE = 1 + PARAMETER C_ICACHE_ALWAYS_USED = 1 + PARAMETER C_DCACHE_BASEADDR = 0xc0000000 + PARAMETER C_DCACHE_HIGHADDR = 0xc7ffffff + PARAMETER C_USE_DCACHE = 1 + PARAMETER C_DCACHE_ALWAYS_USED = 1 + PARAMETER C_INTERCONNECT_M_AXI_DC_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_DC_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_DP_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_DP_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_DP_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_DP_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_DP_B_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_DC_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_DC_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_DC_B_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_IC_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_IC_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_IC_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_IC_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_M_AXI_IC_B_REGISTER = 1 + PARAMETER C_NUMBER_OF_PC_BRK = 7 + PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 2 + PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 2 + PARAMETER C_CACHE_BYTE_SIZE = 16384 + PARAMETER C_DCACHE_BYTE_SIZE = 16384 + PARAMETER C_FPU_EXCEPTION = 1 + PARAMETER C_DIV_ZERO_EXCEPTION = 1 + PARAMETER C_M_AXI_I_BUS_EXCEPTION = 1 + PARAMETER C_M_AXI_D_BUS_EXCEPTION = 1 + PARAMETER C_ILL_OPCODE_EXCEPTION = 1 + PARAMETER C_OPCODE_0x0_ILLEGAL = 1 + PARAMETER C_UNALIGNED_EXCEPTIONS = 1 + PARAMETER C_USE_DIV = 1 + BUS_INTERFACE M_AXI_DP = axi4lite_0 + BUS_INTERFACE M_AXI_DC = axi4_0 + BUS_INTERFACE M_AXI_IC = axi4_0 + BUS_INTERFACE DEBUG = microblaze_0_debug + BUS_INTERFACE DLMB = microblaze_0_dlmb + BUS_INTERFACE ILMB = microblaze_0_ilmb + PORT MB_RESET = proc_sys_reset_0_MB_Reset + PORT CLK = clk_100_0000MHzPLL0 + PORT INTERRUPT = microblaze_0_interrupt +END + +BEGIN lmb_v10 + PARAMETER INSTANCE = microblaze_0_ilmb + PARAMETER HW_VER = 2.00.a + PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET + PORT LMB_CLK = clk_100_0000MHzPLL0 +END + +BEGIN lmb_v10 + PARAMETER INSTANCE = microblaze_0_dlmb + PARAMETER HW_VER = 2.00.a + PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET + PORT LMB_CLK = clk_100_0000MHzPLL0 +END + +BEGIN lmb_bram_if_cntlr + PARAMETER INSTANCE = microblaze_0_i_bram_ctrl + PARAMETER HW_VER = 3.00.a + PARAMETER C_BASEADDR = 0x00000000 + PARAMETER C_HIGHADDR = 0x00001fff + BUS_INTERFACE SLMB = microblaze_0_ilmb + BUS_INTERFACE BRAM_PORT = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block +END + +BEGIN lmb_bram_if_cntlr + PARAMETER INSTANCE = microblaze_0_d_bram_ctrl + PARAMETER HW_VER = 3.00.a + PARAMETER C_BASEADDR = 0x00000000 + PARAMETER C_HIGHADDR = 0x00001fff + BUS_INTERFACE SLMB = microblaze_0_dlmb + BUS_INTERFACE BRAM_PORT = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block +END + +BEGIN bram_block + PARAMETER INSTANCE = microblaze_0_bram_block + PARAMETER HW_VER = 1.00.a + BUS_INTERFACE PORTA = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block + BUS_INTERFACE PORTB = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block +END + +BEGIN proc_sys_reset + PARAMETER INSTANCE = proc_sys_reset_0 + PARAMETER HW_VER = 3.00.a + PARAMETER C_EXT_RESET_HIGH = 1 + PORT Ext_Reset_In = RESET + PORT MB_Reset = proc_sys_reset_0_MB_Reset + PORT Slowest_sync_clk = clk_50_0000MHzPLL0 + PORT Interconnect_aresetn = proc_sys_reset_0_Interconnect_aresetn + PORT Dcm_locked = proc_sys_reset_0_Dcm_locked + PORT MB_Debug_Sys_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst + PORT BUS_STRUCT_RESET = proc_sys_reset_0_BUS_STRUCT_RESET +END + +BEGIN clock_generator + PARAMETER INSTANCE = clock_generator_0 + PARAMETER HW_VER = 4.01.a + PARAMETER C_CLKIN_FREQ = 200000000 + PARAMETER C_CLKOUT0_FREQ = 600000000 + PARAMETER C_CLKOUT0_GROUP = PLL0 + PARAMETER C_CLKOUT0_BUF = FALSE + PARAMETER C_CLKOUT1_FREQ = 600000000 + PARAMETER C_CLKOUT1_PHASE = 180 + PARAMETER C_CLKOUT1_GROUP = PLL0 + PARAMETER C_CLKOUT1_BUF = FALSE + PARAMETER C_CLKOUT2_FREQ = 100000000 + PARAMETER C_CLKOUT2_GROUP = PLL0 + PARAMETER C_CLKOUT3_FREQ = 50000000 + PARAMETER C_CLKOUT3_GROUP = PLL0 + PORT RST = RESET + PORT CLKIN = CLK + PORT CLKOUT2 = clk_100_0000MHzPLL0 + PORT CLKOUT3 = clk_50_0000MHzPLL0 + PORT CLKOUT0 = clk_600_0000MHzPLL0_nobuf + PORT CLKOUT1 = clk_600_0000MHz180PLL0_nobuf + PORT LOCKED = proc_sys_reset_0_Dcm_locked +END + +BEGIN mdm + PARAMETER INSTANCE = debug_module + PARAMETER HW_VER = 2.00.b + PARAMETER C_INTERCONNECT = 2 + PARAMETER C_USE_UART = 1 + PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1 + PARAMETER C_BASEADDR = 0x74800000 + PARAMETER C_HIGHADDR = 0x7480ffff + BUS_INTERFACE S_AXI = axi4lite_0 + BUS_INTERFACE MBDEBUG_0 = microblaze_0_debug + PORT S_AXI_ACLK = clk_50_0000MHzPLL0 + PORT Debug_SYS_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst +END + +BEGIN axi_uartlite + PARAMETER INSTANCE = RS232_Uart_1 + PARAMETER HW_VER = 1.01.a + PARAMETER C_BAUDRATE = 115200 + PARAMETER C_DATA_BITS = 8 + PARAMETER C_USE_PARITY = 0 + PARAMETER C_ODD_PARITY = 1 + PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1 + PARAMETER C_BASEADDR = 0x40600000 + PARAMETER C_HIGHADDR = 0x4060ffff + BUS_INTERFACE S_AXI = axi4lite_0 + PORT TX = RS232_Uart_1_sout + PORT RX = RS232_Uart_1_sin + PORT S_AXI_ACLK = clk_50_0000MHzPLL0 + PORT Interrupt = RS232_Uart_1_Interrupt +END + +BEGIN axi_gpio + PARAMETER INSTANCE = LEDs_4Bits + PARAMETER HW_VER = 1.01.a + PARAMETER C_GPIO_WIDTH = 4 + PARAMETER C_ALL_INPUTS = 0 + PARAMETER C_INTERRUPT_PRESENT = 0 + PARAMETER C_IS_DUAL = 0 + PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1 + PARAMETER C_BASEADDR = 0x40020000 + PARAMETER C_HIGHADDR = 0x4002ffff + BUS_INTERFACE S_AXI = axi4lite_0 + PORT GPIO_IO_O = LEDs_4Bits_TRI_O + PORT S_AXI_ACLK = clk_50_0000MHzPLL0 +END + +BEGIN axi_gpio + PARAMETER INSTANCE = Push_Buttons_4Bits + PARAMETER HW_VER = 1.01.a + PARAMETER C_GPIO_WIDTH = 4 + PARAMETER C_ALL_INPUTS = 1 + PARAMETER C_INTERRUPT_PRESENT = 1 + PARAMETER C_IS_DUAL = 0 + PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1 + PARAMETER C_BASEADDR = 0x40000000 + PARAMETER C_HIGHADDR = 0x4000ffff + BUS_INTERFACE S_AXI = axi4lite_0 + PORT GPIO_IO_I = Push_Buttons_4Bits_TRI_I + PORT S_AXI_ACLK = clk_50_0000MHzPLL0 + PORT IP2INTC_Irpt = Push_Buttons_4Bits_IP2INTC_Irpt +END + +BEGIN axi_s6_ddrx + PARAMETER INSTANCE = MCB_DDR3 + PARAMETER HW_VER = 1.02.a + PARAMETER C_MCB_RZQ_LOC = K7 + PARAMETER C_MCB_ZIO_LOC = R7 + PARAMETER C_MEM_TYPE = DDR3 + PARAMETER C_MEM_PARTNO = MT41J64M16XX-187E + PARAMETER C_MEM_BANKADDR_WIDTH = 3 + PARAMETER C_MEM_NUM_COL_BITS = 10 + PARAMETER C_SKIP_IN_TERM_CAL = 0 + PARAMETER C_S0_AXI_ENABLE = 1 + PARAMETER C_INTERCONNECT_S0_AXI_MASTERS = microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC + PARAMETER C_INTERCONNECT_S0_AXI_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_S0_AXI_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_S0_AXI_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_S0_AXI_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_S0_AXI_B_REGISTER = 1 + PARAMETER C_S0_AXI_BASEADDR = 0xc0000000 + PARAMETER C_S0_AXI_HIGHADDR = 0xc7ffffff + BUS_INTERFACE S0_AXI = axi4_0 + PORT mcbx_dram_clk = mcbx_dram_clk + PORT mcbx_dram_clk_n = mcbx_dram_clk_n + PORT mcbx_dram_cke = mcbx_dram_cke + PORT mcbx_dram_odt = mcbx_dram_odt + PORT mcbx_dram_ras_n = mcbx_dram_ras_n + PORT mcbx_dram_cas_n = mcbx_dram_cas_n + PORT mcbx_dram_we_n = mcbx_dram_we_n + PORT mcbx_dram_udm = mcbx_dram_udm + PORT mcbx_dram_ldm = mcbx_dram_ldm + PORT mcbx_dram_ba = mcbx_dram_ba + PORT mcbx_dram_addr = mcbx_dram_addr + PORT mcbx_dram_ddr3_rst = mcbx_dram_ddr3_rst + PORT mcbx_dram_dq = mcbx_dram_dq + PORT mcbx_dram_dqs = mcbx_dram_dqs + PORT mcbx_dram_dqs_n = mcbx_dram_dqs_n + PORT mcbx_dram_udqs = mcbx_dram_udqs + PORT mcbx_dram_udqs_n = mcbx_dram_udqs_n + PORT rzq = rzq + PORT zio = zio + PORT s0_axi_aclk = clk_100_0000MHzPLL0 + PORT ui_clk = clk_100_0000MHzPLL0 + PORT sysclk_2x = clk_600_0000MHzPLL0_nobuf + PORT sysclk_2x_180 = clk_600_0000MHz180PLL0_nobuf + PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET + PORT PLL_LOCK = proc_sys_reset_0_Dcm_locked +END + +BEGIN axi_ethernetlite + PARAMETER INSTANCE = Ethernet_Lite + PARAMETER HW_VER = 1.00.a + PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1 + PARAMETER C_BASEADDR = 0x40e00000 + PARAMETER C_HIGHADDR = 0x40e0ffff + PARAMETER C_S_AXI_PROTOCOL = AXI4LITE + PARAMETER C_RX_PING_PONG = 1 + PARAMETER C_TX_PING_PONG = 1 + PARAMETER C_S_AXI_ID_WIDTH = 1 + BUS_INTERFACE S_AXI = axi4lite_0 + PORT PHY_MDIO = Ethernet_Lite_MDIO + PORT PHY_MDC = Ethernet_Lite_MDC + PORT PHY_tx_data = Ethernet_Lite_TXD + PORT PHY_tx_en = Ethernet_Lite_TX_EN + PORT PHY_tx_clk = Ethernet_Lite_TX_CLK + PORT PHY_col = Ethernet_Lite_COL + PORT PHY_rx_data = Ethernet_Lite_RXD + PORT PHY_rx_er = Ethernet_Lite_RX_ER + PORT PHY_rx_clk = Ethernet_Lite_RX_CLK + PORT PHY_crs = Ethernet_Lite_CRS + PORT PHY_dv = Ethernet_Lite_RX_DV + PORT PHY_rst_n = Ethernet_Lite_PHY_RST_N + PORT S_AXI_ACLK = clk_50_0000MHzPLL0 + PORT IP2INTC_Irpt = Ethernet_Lite_IP2INTC_Irpt +END + +BEGIN axi_timer + PARAMETER INSTANCE = axi_timer_0 + PARAMETER HW_VER = 1.01.a + PARAMETER C_COUNT_WIDTH = 32 + PARAMETER C_ONE_TIMER_ONLY = 0 + PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1 + PARAMETER C_BASEADDR = 0x41c00000 + PARAMETER C_HIGHADDR = 0x41c0ffff + BUS_INTERFACE S_AXI = axi4lite_0 + PORT S_AXI_ACLK = clk_50_0000MHzPLL0 + PORT Interrupt = axi_timer_0_Interrupt +END + +BEGIN axi_intc + PARAMETER INSTANCE = microblaze_0_intc + PARAMETER HW_VER = 1.01.a + PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1 + PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1 + PARAMETER C_BASEADDR = 0x41200000 + PARAMETER C_HIGHADDR = 0x4120ffff + BUS_INTERFACE S_AXI = axi4lite_0 + PORT IRQ = microblaze_0_interrupt + PORT S_AXI_ACLK = clk_50_0000MHzPLL0 + PORT INTR = RS232_Uart_1_Interrupt & Push_Buttons_4Bits_IP2INTC_Irpt & Ethernet_Lite_IP2INTC_Irpt & axi_timer_0_Interrupt +END + diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/system.xmp b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/system.xmp new file mode 100644 index 000000000..3862cd3d6 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/system.xmp @@ -0,0 +1,38 @@ +#Please do not modify this file by hand +XmpVersion: 13.1 +VerMgmt: 13.1 +IntStyle: default +MHS File: system.mhs +Architecture: spartan6 +Device: xc6slx45t +Package: fgg484 +SpeedGrade: -3 +UserCmd1: +UserCmd1Type: 0 +UserCmd2: +UserCmd2Type: 0 +GenSimTB: 0 +SdkExportBmmBit: 1 +SdkExportDir: SDK/SDK_Export +InsertNoPads: 0 +WarnForEAArch: 1 +HdlLang: VHDL +SimModel: BEHAVIORAL +UcfFile: data/system.ucf +EnableParTimingError: 1 +ShowLicenseDialog: 1 +ICacheAddr: MCB_DDR3,C_S0_AXI_BASEADDR +ICacheAddr: MCB_DDR3,C_S1_AXI_BASEADDR +ICacheAddr: MCB_DDR3,C_S2_AXI_BASEADDR +ICacheAddr: MCB_DDR3,C_S3_AXI_BASEADDR +ICacheAddr: MCB_DDR3,C_S4_AXI_BASEADDR +ICacheAddr: MCB_DDR3,C_S5_AXI_BASEADDR +DCacheAddr: MCB_DDR3,C_S0_AXI_BASEADDR +DCacheAddr: MCB_DDR3,C_S1_AXI_BASEADDR +DCacheAddr: MCB_DDR3,C_S2_AXI_BASEADDR +DCacheAddr: MCB_DDR3,C_S3_AXI_BASEADDR +DCacheAddr: MCB_DDR3,C_S4_AXI_BASEADDR +DCacheAddr: MCB_DDR3,C_S5_AXI_BASEADDR +Processor: microblaze_0 +ElfImp: +ElfSim: diff --git a/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/system_incl.make b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/system_incl.make new file mode 100644 index 000000000..0bd70abe4 --- /dev/null +++ b/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/system_incl.make @@ -0,0 +1,110 @@ +################################################################# +# Makefile generated by Xilinx Platform Studio +# Project:C:\E\Dev\FreeRTOS\WorkingCopy\Demo\MicroBlaze_Spartan-6_EthernetLite\PlatformStudioProject\system.xmp +# +# WARNING : This file will be re-generated every time a command +# to run a make target is invoked. So, any changes made to this +# file manually, will be lost when make is invoked next. +################################################################# + +SHELL = CMD + +XILINX_EDK_DIR = C:/devtools/Xilinx/13.1/ISE_DS/EDK + +SYSTEM = system + +MHSFILE = system.mhs + +FPGA_ARCH = spartan6 + +DEVICE = xc6slx45tfgg484-3 + +LANGUAGE = vhdl +GLOBAL_SEARCHPATHOPT = +PROJECT_SEARCHPATHOPT = + +SEARCHPATHOPT = $(PROJECT_SEARCHPATHOPT) $(GLOBAL_SEARCHPATHOPT) + +SUBMODULE_OPT = + +PLATGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(SUBMODULE_OPT) -msg __xps/ise/xmsgprops.lst + +OBSERVE_PAR_OPTIONS = -error yes + +MICROBLAZE_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop.elf +MICROBLAZE_BOOTLOOP_LE = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop_le.elf +PPC405_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc405/ppc_bootloop.elf +PPC440_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc440/ppc440_bootloop.elf +BOOTLOOP_DIR = bootloops + +MICROBLAZE_0_BOOTLOOP = $(BOOTLOOP_DIR)/microblaze_0.elf + +BRAMINIT_ELF_IMP_FILES = $(MICROBLAZE_0_BOOTLOOP) +BRAMINIT_ELF_IMP_FILE_ARGS = -pe microblaze_0 $(MICROBLAZE_0_BOOTLOOP) + +BRAMINIT_ELF_SIM_FILES = $(MICROBLAZE_0_BOOTLOOP) +BRAMINIT_ELF_SIM_FILE_ARGS = -pe microblaze_0 $(MICROBLAZE_0_BOOTLOOP) + +SIM_CMD = isim_system + +BEHAVIORAL_SIM_SCRIPT = simulation/behavioral/$(SYSTEM)_setup.tcl + +STRUCTURAL_SIM_SCRIPT = simulation/structural/$(SYSTEM)_setup.tcl + +TIMING_SIM_SCRIPT = simulation/timing/$(SYSTEM)_setup.tcl + +DEFAULT_SIM_SCRIPT = $(BEHAVIORAL_SIM_SCRIPT) + +MIX_LANG_SIM_OPT = -mixed yes + +SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_SIM_FILE_ARGS) $(MIX_LANG_SIM_OPT) -msg __xps/ise/xmsgprops.lst -s isim + + +CORE_STATE_DEVELOPMENT_FILES = + +WRAPPER_NGC_FILES = implementation/axi4_0_wrapper.ngc \ +implementation/axi4lite_0_wrapper.ngc \ +implementation/microblaze_0_wrapper.ngc \ +implementation/microblaze_0_ilmb_wrapper.ngc \ +implementation/microblaze_0_dlmb_wrapper.ngc \ +implementation/microblaze_0_i_bram_ctrl_wrapper.ngc \ +implementation/microblaze_0_d_bram_ctrl_wrapper.ngc \ +implementation/microblaze_0_bram_block_wrapper.ngc \ +implementation/proc_sys_reset_0_wrapper.ngc \ +implementation/clock_generator_0_wrapper.ngc \ +implementation/debug_module_wrapper.ngc \ +implementation/rs232_uart_1_wrapper.ngc \ +implementation/leds_4bits_wrapper.ngc \ +implementation/push_buttons_4bits_wrapper.ngc \ +implementation/mcb_ddr3_wrapper.ngc \ +implementation/ethernet_lite_wrapper.ngc \ +implementation/axi_timer_0_wrapper.ngc \ +implementation/microblaze_0_intc_wrapper.ngc + +POSTSYN_NETLIST = implementation/$(SYSTEM).ngc + +SYSTEM_BIT = implementation/$(SYSTEM).bit + +DOWNLOAD_BIT = implementation/download.bit + +SYSTEM_ACE = implementation/$(SYSTEM).ace + +UCF_FILE = data/system.ucf + +BMM_FILE = implementation/$(SYSTEM).bmm + +BITGEN_UT_FILE = etc/bitgen.ut + +XFLOW_OPT_FILE = etc/fast_runtime.opt +XFLOW_DEPENDENCY = __xps/xpsxflow.opt $(XFLOW_OPT_FILE) + +XPLORER_DEPENDENCY = __xps/xplorer.opt +XPLORER_OPTIONS = -p $(DEVICE) -uc $(SYSTEM).ucf -bm $(SYSTEM).bmm -max_runs 7 + +FPGA_IMP_DEPENDENCY = $(BMM_FILE) $(POSTSYN_NETLIST) $(UCF_FILE) $(XFLOW_DEPENDENCY) + +SDK_EXPORT_DIR = SDK\SDK_Export\hw +SYSTEM_HW_HANDOFF = $(SDK_EXPORT_DIR)/$(SYSTEM).xml +SYSTEM_HW_HANDOFF_BIT = $(SDK_EXPORT_DIR)/$(SYSTEM).bit +SYSTEM_HW_HANDOFF_BMM = $(SDK_EXPORT_DIR)/$(SYSTEM)_bd.bmm +SYSTEM_HW_HANDOFF_DEP = $(SYSTEM_HW_HANDOFF) $(SYSTEM_HW_HANDOFF_BIT) $(SYSTEM_HW_HANDOFF_BMM)