Add FreeRTOS+CLI examples to the Renesas RZ/T demos.
Fix some compiler warnings. Correct spellings in comments.pull/4/head
Richard Barry
9 years ago
parent
96ff3925d2
commit
c6a4e3191e
@ -1,2 +1,2 @@
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[MainWindow]
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WindowPlacement=_ 519 0 1619 872 3
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WindowPlacement=_ 367 9 1633 963 3
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@ -0,0 +1,272 @@
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/***********************************************************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
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* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
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* applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
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* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
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* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
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* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
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* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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*
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* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
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***********************************************************************************************************************/
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/***********************************************************************************************************************
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* File Name : r_cg_scifa.c
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* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
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* Device(s) : R7S910018CBG
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* Tool-Chain : GCCARM
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* Description : This file implements device driver for SCIF module.
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* Creation Date: 19/04/2015
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***********************************************************************************************************************/
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/***********************************************************************************************************************
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Pragma directive
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***********************************************************************************************************************/
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/* Start user code for pragma. Do not edit comment generated here */
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/* End user code. Do not edit comment generated here */
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/***********************************************************************************************************************
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Includes
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***********************************************************************************************************************/
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#include "r_cg_macrodriver.h"
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#include "r_cg_scifa.h"
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/* Start user code for include. Do not edit comment generated here */
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/* End user code. Do not edit comment generated here */
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#include "r_cg_userdefine.h"
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/***********************************************************************************************************************
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Global variables and functions
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***********************************************************************************************************************/
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const uint8_t * gp_scifa2_tx_address; /* SCIFA2 transmit buffer address */
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uint16_t g_scifa2_tx_count; /* SCIFA2 transmit data number */
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uint8_t * gp_scifa2_rx_address; /* SCIFA2 receive buffer address */
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uint16_t g_scifa2_rx_count; /* SCIFA2 receive data number */
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uint16_t g_scifa2_rx_length; /* SCIFA2 receive data length */
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/* Start user code for global. Do not edit comment generated here */
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/* End user code. Do not edit comment generated here */
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/***********************************************************************************************************************
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* Function Name: R_SCIFA2_Create
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* Description : This function initializes SCIFA2.
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* Arguments : None
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* Return Value : None
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***********************************************************************************************************************/
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void R_SCIFA2_Create(void)
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{
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volatile uint16_t dummy;
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uint16_t w_count;
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/* Cancel SCIFA2 module stop state */
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MSTP(SCIFA2) = 0U;
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/* Disable TXIF2 interrupt */
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VIC.IEC3.LONG = 0x00008000UL;
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/* Disable RXIF2 interrupt */
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VIC.IEC3.LONG = 0x00004000UL;
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/* Disable BRIF2 interrupt */
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VIC.IEC3.LONG = 0x00002000UL;
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/* Disable DRIF2 interrupt */
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VIC.IEC3.LONG = 0x00010000UL;
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/* Clear transmit/receive enable bits */
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SCIFA2.SCR.BIT.TE = 0U;
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SCIFA2.SCR.BIT.RE = 0U;
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/* Reset transmit/receive FIFO data register operation */
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SCIFA2.FCR.BIT.TFRST = 1U;
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SCIFA2.FCR.BIT.RFRST = 1U;
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/* Read and clear status flags */
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dummy = SCIFA2.FSR.WORD;
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/* Remove compiler warnings. */
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( void ) dummy;
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SCIFA2.FSR.WORD = 0x00U;
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dummy = (uint16_t) SCIFA2.LSR.BIT.ORER;
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/* Remove compiler warnings. */
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( void ) dummy;
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SCIFA2.LSR.BIT.ORER = 0U;
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/* Set clock enable bits */
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SCIFA2.SCR.WORD = _SCIF_INTERNAL_SCK_UNUSED;
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/* Set transmission/reception format */
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SCIFA2.SMR.WORD = _SCIF_CLOCK_SERICLK_4 | _SCIF_STOP_1 | _SCIF_PARITY_DISABLE | _SCIF_DATA_LENGTH_8 |
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_SCIF_ASYNCHRONOUS_MODE;
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SCIFA2.SEMR.BYTE = _SCIF_16_BASE_CLOCK | _SCIF_NOISE_FILTER_ENABLE | _SCIF_DATA_TRANSFER_LSB_FIRST |
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_SCIF_BAUDRATE_SINGLE;
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/* Clear modulation duty register select */
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SCIFA2.SEMR.BIT.MDDRS = 0U;
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/* Set bit rate */
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SCIFA2.BRR_MDDR.BRR = 0x3CU;
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/* Wait for at least 1-bit interval */
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for (w_count = 0U; w_count < _SCIF_1BIT_INTERVAL_2; w_count++)
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{
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nop();
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}
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/* Set FIFO trigger conditions */
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SCIFA2.FTCR.WORD = _SCIF_TX_FIFO_TRIGGER_NUM_0 | _SCIF_TX_TRIGGER_TFTC_VALID | _SCIF_RX_FIFO_TRIGGER_NUM_1 |
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_SCIF_RX_TRIGGER_RFTC_VALID;
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SCIFA2.FCR.WORD = _SCIF_LOOPBACK_DISABLE | _SCIF_MODEM_CONTROL_DISABLE;
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/* Disable transmit/receive FIFO data register reset operation */
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SCIFA2.FCR.BIT.TFRST = 0U;
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SCIFA2.FCR.BIT.RFRST = 0U;
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/* Set TXIF2 interrupt priority */
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VIC.PRL111.LONG = _SCIF_PRIORITY_LEVEL2;
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/* Set TXIF2 interrupt address */
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VIC.VAD111.LONG = (uint32_t)r_scifa2_txif2_interrupt_entry;
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/* Set RXIF2 interrupt priority */
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VIC.PRL110.LONG = _SCIF_PRIORITY_LEVEL3;
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/* Set RXIF2 interrupt address */
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VIC.VAD110.LONG = (uint32_t)r_scifa2_rxif2_interrupt_entry;
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/* Set BRIF2 interrupt priority */
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VIC.PRL109.LONG = _SCIF_PRIORITY_LEVEL5;
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/* Set BRIF2 interrupt address */
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VIC.VAD109.LONG = (uint32_t)r_scifa2_brif2_interrupt_entry;
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/* Set DRIF2 interrupt priority */
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VIC.PRL112.LONG = _SCIF_PRIORITY_LEVEL4;
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/* Set DRIF2 interrupt address */
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VIC.VAD112.LONG = (uint32_t)r_scifa2_drif2_interrupt_entry;
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}
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/***********************************************************************************************************************
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* Function Name: R_SCIFA2_Start
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* Description : This function starts SCIFA2.
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* Arguments : None
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* Return Value : None
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***********************************************************************************************************************/
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void R_SCIFA2_Start(void)
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{
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/* Enable TXIF2 interrupt */
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VIC.IEN3.LONG |= 0x00008000UL;
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/* Enable RXIF2 interrupt */
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VIC.IEN3.LONG |= 0x00004000UL;
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/* Enable BRIF2 interrupt */
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VIC.IEN3.LONG |= 0x00002000UL;
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/* Enable DRIF2 interrupt */
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VIC.IEN3.LONG |= 0x00010000UL;
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}
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/***********************************************************************************************************************
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* Function Name: R_SCIFA2_Stop
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* Description : This function stops SCIFA2.
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* Arguments : None
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* Return Value : None
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***********************************************************************************************************************/
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void R_SCIFA2_Stop(void)
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{
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/* Disable serial transmit */
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SCIFA2.SCR.BIT.TE = 0U;
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/* Disable serial receive */
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SCIFA2.SCR.BIT.RE = 0U;
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/* Disable TXI interrupt */
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SCIFA2.SCR.BIT.TIE = 0U;
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/* Disable RXI and ERI interrupt */
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SCIFA2.SCR.BIT.RIE = 0U;
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/* Disable TXIF2 interrupt */
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VIC.IEC3.LONG = 0x00008000UL;
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/* Disable RXIF2 interrupt */
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VIC.IEC3.LONG = 0x00004000UL;
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/* Disable BRIF2 interrupt */
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VIC.IEC3.LONG = 0x00002000UL;
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/* Disable DRIF2 interrupt */
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VIC.IEC3.LONG = 0x00010000UL;
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}
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/***********************************************************************************************************************
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* Function Name: R_SCIFA2_Serial_Receive
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* Description : This function receives SCIFA2 data.
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* Arguments : rx_buf -
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* receive buffer pointer (Not used when receive data handled by DMAC)
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* rx_num -
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* buffer size (Not used when receive data handled by DMAC)
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* Return Value : status -
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* MD_OK or MD_ARGERROR
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***********************************************************************************************************************/
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MD_STATUS R_SCIFA2_Serial_Receive(uint8_t * rx_buf, uint16_t rx_num)
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{
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MD_STATUS status = MD_OK;
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if (rx_num < 1U)
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{
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status = MD_ARGERROR;
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}
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else
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{
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g_scifa2_rx_count = 0U;
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g_scifa2_rx_length = rx_num;
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gp_scifa2_rx_address = rx_buf;
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SCIFA2.FTCR.BIT.RFTC = _SCIF_RX_TRIG_NUM_2;
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SCIFA2.SCR.BIT.RE = 1U;
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SCIFA2.SCR.BIT.RIE = 1U;
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SCIFA2.SCR.BIT.REIE = 1U;
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}
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return (status);
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}
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/***********************************************************************************************************************
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* Function Name: R_SCIFA2_Serial_Send
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* Description : This function transmits SCIFA2 data.
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* Arguments : tx_buf -
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* transfer buffer pointer (Not used when transmit data handled by DMAC)
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* tx_num -
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* buffer size (Not used when transmit data handled by DMAC)
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* Return Value : status -
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* MD_OK or MD_ARGERROR
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***********************************************************************************************************************/
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MD_STATUS R_SCIFA2_Serial_Send(const uint8_t * tx_buf, uint16_t tx_num)
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{
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MD_STATUS status = MD_OK;
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if (tx_num < 1U)
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{
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status = MD_ARGERROR;
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}
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else
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{
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gp_scifa2_tx_address = tx_buf;
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g_scifa2_tx_count = tx_num;
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SCIFA2.SCR.BIT.TE = 1U;
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SCIFA2.SCR.BIT.TIE = 1U;
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}
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return (status);
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}
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/* Start user code for adding. Do not edit comment generated here */
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/* End user code. Do not edit comment generated here */
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@ -0,0 +1,275 @@
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/***********************************************************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
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* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
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* applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
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* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
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* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
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* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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*
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* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
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***********************************************************************************************************************/
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/***********************************************************************************************************************
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* File Name : r_cg_scifa.h
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* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
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* Device(s) : R7S910018CBG
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* Tool-Chain : GCCARM
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* Description : This file implements device driver for SCIF module.
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* Creation Date: 19/04/2015
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***********************************************************************************************************************/
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#ifndef SCIF_H
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#define SCIF_H
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/***********************************************************************************************************************
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Macro definitions (Register bit)
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***********************************************************************************************************************/
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/*
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Serial mode register (SMR)
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*/
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/* Clock select (CKS[1:0]) */
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#define _SCIF_CLOCK_SERICLK (0x0000U) /* SERICLK */
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#define _SCIF_CLOCK_SERICLK_4 (0x0001U) /* SERICLK/4 */
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#define _SCIF_CLOCK_SERICLK_16 (0x0002U) /* SERICLK/16 */
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#define _SCIF_CLOCK_SERICLK_64 (0x0003U) /* SERICLK/64 */
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/* Stop bit length (STOP) */
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#define _SCIF_STOP_1 (0x0000U) /* 1 stop bit */
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#define _SCIF_STOP_2 (0x0008U) /* 2 stop bits */
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/* Parity mode (PM) */
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#define _SCIF_PARITY_EVEN (0x0000U) /* Parity even */
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#define _SCIF_PARITY_ODD (0x0010U) /* Parity odd */
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/* Parity enable (PE) */
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#define _SCIF_PARITY_DISABLE (0x0000U) /* Parity disable */
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#define _SCIF_PARITY_ENABLE (0x0020U) /* Parity enable */
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/* Character length (CHR) */
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#define _SCIF_DATA_LENGTH_8 (0x0000U) /* Data length 8 bits */
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#define _SCIF_DATA_LENGTH_7 (0x0040U) /* Data length 7 bits */
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/* Communications mode (CM) */
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#define _SCIF_ASYNCHRONOUS_MODE (0x0000U) /* Asynchronous mode */
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#define _SCIF_CLOCK_SYNCHRONOUS_MODE (0x0080U) /* Clock synchronous mode */
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/*
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Serial control register (SCR)
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*/
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/* Clock enable (CKE) */
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#define _SCIF_INTERNAL_SCK_UNUSED (0x0000U) /* Internal clock selected, SCK pin unused */
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#define _SCIF_INTERNAL_SCK_OUTPUT (0x0001U) /* Internal clock selected, SCK pin as clock output */
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/* Clock enable (CKE) for clock synchronous mode */
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#define _SCIF_INTERNAL_SCK_OUTPUT_SYNC (0x0000U) /* Internal clock, SCK pin is used for clock output */
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#define _SCIF_EXTERNAL_SCK_INPUT_SYNC (0x0002U) /* External clock, SCK pin is used for clock input */
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/* Transmit end interrupt enable (TEIE) */
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#define _SCIF_TEI_INTERRUPT_DISABLE (0x0000U) /* TEI interrupt request disable */
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#define _SCIF_TEI_INTERRUPT_ENABLE (0x0004U) /* TEI interrupt request enable */
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/* Receive error interrupt enable (REIE) */
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#define _SCIF_ERI_BRI_INTERRUPT_DISABLE (0x0000U) /* Disable receive-error interrupt and break interrupt */
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#define _SCIF_ERI_BRI_INTERRUPT_ENABLE (0x0008U) /* Enable receive-error interrupt and break interrupt */
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/* Receive enable (RE) */
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#define _SCIF_RECEIVE_DISABLE (0x0000U) /* Disable receive mode */
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#define _SCIF_RECEIVE_ENABLE (0x0010U) /* Enable receive mode */
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/* Transmit enable (TE) */
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#define _SCIF_TRANSMIT_DISABLE (0x0000U) /* Disable transmit mode */
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#define _SCIF_TRANSMIT_ENABLE (0x0020U) /* Enable transmit mode */
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/* Receive interrupt enable (RIE) */
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#define _SCIF_RXI_ERI_DISABLE (0x0000U) /* Disable RXI and ERI interrupt requests */
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#define _SCIF_RXI_ERI_ENABLE (0x0040U) /* Enable RXI and ERI interrupt requests */
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/* Transmit interrupt enable (TIE) */
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#define _SCIF_TXI_DISABLE (0x0000U) /* Disable TXI interrupt requests */
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#define _SCIF_TXI_ENABLE (0x0080U) /* Enable TXI interrupt requests */
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/*
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FIFO control register (FCR)
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*/
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/* Loop-Back test (LOOP) */
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#define _SCIF_LOOPBACK_DISABLE (0x0000U) /* Loop back test is disabled */
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#define _SCIF_LOOPBACK_ENABLE (0x0001U) /* Loop back test is enabled */
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/* Receive FIFO Data Register Reset (RFRST) */
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#define _SCIF_RX_FIFO_RESET_DISABLE (0x0000U) /* FRDR reset operation is disabled */
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#define _SCIF_RX_FIFO_RESET_ENABLE (0x0002U) /* FRDR reset operation is enabled */
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/* Transmit FIFO Data Register Reset (TFRST) */
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#define _SCIF_TX_FIFO_RESET_DISABLE (0x0000U) /* FTDR reset operation is disabled */
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#define _SCIF_TX_FIFO_RESET_ENABLE (0x0004U) /* FTDR reset operation is enabled */
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/* Modem control enable (MCE) */
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#define _SCIF_MODEM_CONTROL_DISABLE (0x0000U) /* Model signal is disabled */
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#define _SCIF_MODEM_CONTROL_ENABLE (0x0008U) /* Model signal is enabled */
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/* Transmit FIFO Data Trigger Number (TTRG[1:0]) */
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#define _SCIF_TX_TRIGGER_NUMBER_8 (0x0000U) /* 8 (or 8 when TDFE flag is 1) */
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#define _SCIF_TX_TRIGGER_NUMBER_4 (0x0010U) /* 4 (or 12 when TDFE flag is 1) */
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#define _SCIF_TX_TRIGGER_NUMBER_2 (0x0020U) /* 2 (or 14 when TDFE flag is 1) */
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#define _SCIF_TX_TRIGGER_NUMBER_0 (0x0030U) /* 0 (or 16 when TDFE flag is 1) */
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/* Receive FIFO Data Trigger Number (RTRG[1:0]) */
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#define _SCIF_RX_TRIGGER_NUMBER_1 (0x0000U) /* 1 */
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#define _SCIF_RX_TRIGGER_NUMBER_4 (0x0040U) /* 4 (for asynchronous mode) */
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#define _SCIF_RX_TRIGGER_NUMBER_2 (0x0040U) /* 2 (for clock synchronous mode */
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#define _SCIF_RX_TRIGGER_NUMBER_8 (0x0080U) /* 8 */
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#define _SCIF_RX_TRIGGER_NUMBER_14 (0x00C0U) /* 14 */
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/* RTS# Output Active Trigger Number Select (RSTRG[2:0]) */
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#define _SCIF_RTS_TRIGGER_NUMBER_15 (0x0000U) /* 15 */
|
||||
#define _SCIF_RTS_TRIGGER_NUMBER_1 (0x0100U) /* 1 */
|
||||
#define _SCIF_RTS_TRIGGER_NUMBER_4 (0x0200U) /* 4 */
|
||||
#define _SCIF_RTS_TRIGGER_NUMBER_6 (0x0300U) /* 6 */
|
||||
#define _SCIF_RTS_TRIGGER_NUMBER_8 (0x0400U) /* 8 */
|
||||
#define _SCIF_RTS_TRIGGER_NUMBER_10 (0x0500U) /* 10 */
|
||||
#define _SCIF_RTS_TRIGGER_NUMBER_12 (0x0600U) /* 12 */
|
||||
#define _SCIF_RTS_TRIGGER_NUMBER_14 (0x0700U) /* 14 */
|
||||
|
||||
/*
|
||||
Serial port register (SPTR)
|
||||
*/
|
||||
/* Serial Port Break Data (SPB2DT) */
|
||||
#define _SCIF_SERIAL_BREAK_DATA_LOW (0x0000U) /* Input/output data is at low */
|
||||
#define _SCIF_SERIAL_BREAK_DATA_HIGH (0x0001U) /* Input/output data is at high */
|
||||
/* Serial Port Break input/output (SPB2IO) */
|
||||
#define _SCIF_SERIAL_BREAK_TXD_NO_OUTPUT (0x0000U) /* SPB2DT bit value is not output to TXD pin */
|
||||
#define _SCIF_SERIAL_BREAK_TXD_OUTPUT (0x0002U) /* SPB2DT bit value is output to TXD pin */
|
||||
/* SCK Port Data (SCKDT) */
|
||||
#define _SCIF_SCK_DATA_LOW (0x0000U) /* Input/output data is at low */
|
||||
#define _SCIF_SCK_DATA_HIGH (0x0004U) /* Input/output data is at high */
|
||||
/* SCK Port input/output (SCKIO) */
|
||||
#define _SCIF_SCK_PORT_NO_OUTPUT (0x0000U) /* SCKDT bit value is not output to SCK pin */
|
||||
#define _SCIF_SCK_PORT_OUTPUT (0x0008U) /* SCKDT bit value is output to SCK pin */
|
||||
/* CTS# Port Data Select (CTS2DT) */
|
||||
#define _SCIF_CTS_DATA_0 (0x0000U) /* Set b4 to 0. Controls CTS# pin with MCE, CTS2IO bit */
|
||||
#define _SCIF_CTS_DATA_1 (0x0010U) /* Set b4 to 1. Controls CTS# pin with MCE, CTS2IO bit */
|
||||
/* CTS# Port Output Specify (CTS2IO) */
|
||||
#define _SCIF_CTS_OUTPUT_0 (0x0000U) /* Set b5 to 0. Controls CTS# pin with MCE, CTS2IO bit */
|
||||
#define _SCIF_CTS_OUTPUT_1 (0x0020U) /* Set b5 to 1. Controls CTS# pin with MCE, CTS2IO bit */
|
||||
/* RTS# Port Data Select (RTS2DT) */
|
||||
#define _SCIF_RTS_DATA_0 (0x0000U) /* Set b6 to 0. Controls RTS# pin with MCE, RTS2IO bit */
|
||||
#define _SCIF_RTS_DATA_1 (0x0040U) /* Set b6 to 1. Controls RTS# pin with MCE, RTS2IO bit */
|
||||
/* RTS# Port Output Specify (RTS2IO) */
|
||||
#define _SCIF_RTS_OUTPUT_0 (0x0000U) /* Set b7 to 0. Controls RTS# pin with MCE, RTS2IO bit */
|
||||
#define _SCIF_RTS_OUTPUT_1 (0x0080U) /* Set b7 to 1. Controls RTS# pin with MCE, RTS2IO bit */
|
||||
|
||||
/*
|
||||
FIFO Trigger Control Register (FTCR)
|
||||
*/
|
||||
/* Transmit FIFO Data Trigger Number (TFTC[4:0]) */
|
||||
#define _SCIF_TX_FIFO_TRIGGER_NUM_0 (0x0000U) /* 0 (no transmit data trigger) */
|
||||
#define _SCIF_TX_FIFO_TRIGGER_NUM_1 (0x0001U) /* 1 (transmit data triggers) */
|
||||
#define _SCIF_TX_FIFO_TRIGGER_NUM_2 (0x0002U) /* 2 (transmit data triggers) */
|
||||
#define _SCIF_TX_FIFO_TRIGGER_NUM_3 (0x0003U) /* 3 (transmit data triggers) */
|
||||
#define _SCIF_TX_FIFO_TRIGGER_NUM_4 (0x0004U) /* 4 (transmit data triggers) */
|
||||
#define _SCIF_TX_FIFO_TRIGGER_NUM_5 (0x0005U) /* 5 (transmit data triggers) */
|
||||
#define _SCIF_TX_FIFO_TRIGGER_NUM_6 (0x0006U) /* 6 (transmit data triggers) */
|
||||
#define _SCIF_TX_FIFO_TRIGGER_NUM_7 (0x0007U) /* 7 (transmit data triggers) */
|
||||
#define _SCIF_TX_FIFO_TRIGGER_NUM_8 (0x0008U) /* 8 (transmit data triggers) */
|
||||
#define _SCIF_TX_FIFO_TRIGGER_NUM_9 (0x0009U) /* 9 (transmit data triggers) */
|
||||
#define _SCIF_TX_FIFO_TRIGGER_NUM_10 (0x000AU) /* 10 (transmit data triggers) */
|
||||
#define _SCIF_TX_FIFO_TRIGGER_NUM_11 (0x000BU) /* 11 (transmit data triggers) */
|
||||
#define _SCIF_TX_FIFO_TRIGGER_NUM_12 (0x000CU) /* 12 (transmit data triggers) */
|
||||
#define _SCIF_TX_FIFO_TRIGGER_NUM_13 (0x000DU) /* 13 (transmit data triggers) */
|
||||
#define _SCIF_TX_FIFO_TRIGGER_NUM_14 (0x000EU) /* 14 (transmit data triggers) */
|
||||
#define _SCIF_TX_FIFO_TRIGGER_NUM_15 (0x000FU) /* 15 (transmit data triggers) */
|
||||
/* Transmit Trigger Select (TTRGS) */
|
||||
#define _SCIF_TX_TRIGGER_TTRG_VALID (0x0000U) /* TTRG[1:0] bits in FCR are valid */
|
||||
#define _SCIF_TX_TRIGGER_TFTC_VALID (0x0080U) /* TFTC[4:0] bits in FTCR are valid */
|
||||
/* Receive FIFO Data Trigger Number (RFTC[4:0]) */
|
||||
#define _SCIF_RX_FIFO_TRIGGER_NUM_1 (0x0100U) /* 1 (no receive data trigger) */
|
||||
#define _SCIF_RX_FIFO_TRIGGER_NUM_2 (0x0200U) /* 2 (receive data triggers) */
|
||||
#define _SCIF_RX_FIFO_TRIGGER_NUM_3 (0x0300U) /* 3 (receive data triggers) */
|
||||
#define _SCIF_RX_FIFO_TRIGGER_NUM_4 (0x0400U) /* 4 (receive data triggers) */
|
||||
#define _SCIF_RX_FIFO_TRIGGER_NUM_5 (0x0500U) /* 5 (receive data triggers) */
|
||||
#define _SCIF_RX_FIFO_TRIGGER_NUM_6 (0x0600U) /* 6 (receive data triggers) */
|
||||
#define _SCIF_RX_FIFO_TRIGGER_NUM_7 (0x0700U) /* 7 (receive data triggers) */
|
||||
#define _SCIF_RX_FIFO_TRIGGER_NUM_8 (0x0800U) /* 8 (receive data triggers) */
|
||||
#define _SCIF_RX_FIFO_TRIGGER_NUM_9 (0x0900U) /* 9 (receive data triggers) */
|
||||
#define _SCIF_RX_FIFO_TRIGGER_NUM_10 (0x0A00U) /* 10 (receive data triggers) */
|
||||
#define _SCIF_RX_FIFO_TRIGGER_NUM_11 (0x0B00U) /* 11 (receive data triggers) */
|
||||
#define _SCIF_RX_FIFO_TRIGGER_NUM_12 (0x0C00U) /* 12 (receive data triggers) */
|
||||
#define _SCIF_RX_FIFO_TRIGGER_NUM_13 (0x0D00U) /* 13 (receive data triggers) */
|
||||
#define _SCIF_RX_FIFO_TRIGGER_NUM_14 (0x0E00U) /* 14 (receive data triggers) */
|
||||
#define _SCIF_RX_FIFO_TRIGGER_NUM_15 (0x0F00U) /* 15 (receive data triggers) */
|
||||
#define _SCIF_RX_FIFO_TRIGGER_NUM_16 (0x1000U) /* 16 (receive data triggers) */
|
||||
/* Transmit Trigger Select (RTRGS) */
|
||||
#define _SCIF_RX_TRIGGER_RTRG_VALID (0x0000U) /* RTRG[1:0] bits in FCR are valid */
|
||||
#define _SCIF_RX_TRIGGER_RFTC_VALID (0x8000U) /* RFTC[4:0] bits in FTCR are valid */
|
||||
|
||||
/*
|
||||
Serial extended mode register (SEMR)
|
||||
*/
|
||||
/* Asynchronous base clock select (ABCS0) */
|
||||
#define _SCIF_16_BASE_CLOCK (0x00U) /* Selects 16 base clock cycles for 1 bit period */
|
||||
#define _SCIF_8_BASE_CLOCK (0x01U) /* Selects 8 base clock cycles for 1 bit period */
|
||||
/* Noise Cancellation Enable (NFEN) */
|
||||
#define _SCIF_NOISE_FILTER_DISABLE (0x00U) /* Noise cancellation for the RxD pin input is disabled */
|
||||
#define _SCIF_NOISE_FILTER_ENABLE (0x04U) /* Noise cancellation for the RxD pin input is enabled */
|
||||
/* Data Transfer Direction Select (DIR) */
|
||||
#define _SCIF_DATA_TRANSFER_LSB_FIRST (0x00U) /* Transmits the data in FTDR by the LSB-first method */
|
||||
#define _SCIF_DATA_TRANSFER_MSB_FIRST (0x08U) /* Transmits the data in FTDR by the MSB-first method */
|
||||
/* Modulation Duty Register Select (MDDRS) */
|
||||
#define _SCIF_BRR_USED (0x00U) /* BRR register can be accessed */
|
||||
#define _SCIF_MDDR_USED (0x10U) /* MDDR register can be accessed. */
|
||||
/* Bit Rate Modulation Enable (BRME) */
|
||||
#define _SCIF_BIT_RATE_MODULATION_DISABLE (0x00U) /* Bit rate modulation function is disabled */
|
||||
#define _SCIF_BIT_RATE_MODULATION_ENABLE (0x20U) /* Bit rate modulation function is enabled */
|
||||
/* Baud Rate Generator Double-Speed Mode Select (BGDM) */
|
||||
#define _SCIF_BAUDRATE_SINGLE (0x00U) /* Baud rate generator outputs normal frequency */
|
||||
#define _SCIF_BAUDRATE_DOUBLE (0x80U) /* Baud rate generator doubles output frequency */
|
||||
|
||||
/*
|
||||
Interrupt Source Priority Register n (PRLn)
|
||||
*/
|
||||
/* Interrupt Priority Level Select (PRL[3:0]) */
|
||||
#define _SCIF_PRIORITY_LEVEL0 (0x00000000UL) /* Level 0 (highest) */
|
||||
#define _SCIF_PRIORITY_LEVEL1 (0x00000001UL) /* Level 1 */
|
||||
#define _SCIF_PRIORITY_LEVEL2 (0x00000002UL) /* Level 2 */
|
||||
#define _SCIF_PRIORITY_LEVEL3 (0x00000003UL) /* Level 3 */
|
||||
#define _SCIF_PRIORITY_LEVEL4 (0x00000004UL) /* Level 4 */
|
||||
#define _SCIF_PRIORITY_LEVEL5 (0x00000005UL) /* Level 5 */
|
||||
#define _SCIF_PRIORITY_LEVEL6 (0x00000006UL) /* Level 6 */
|
||||
#define _SCIF_PRIORITY_LEVEL7 (0x00000007UL) /* Level 7 */
|
||||
#define _SCIF_PRIORITY_LEVEL8 (0x00000008UL) /* Level 8 */
|
||||
#define _SCIF_PRIORITY_LEVEL9 (0x00000009UL) /* Level 9 */
|
||||
#define _SCIF_PRIORITY_LEVEL10 (0x0000000AUL) /* Level 10 */
|
||||
#define _SCIF_PRIORITY_LEVEL11 (0x0000000BUL) /* Level 11 */
|
||||
#define _SCIF_PRIORITY_LEVEL12 (0x0000000CUL) /* Level 12 */
|
||||
#define _SCIF_PRIORITY_LEVEL13 (0x0000000DUL) /* Level 13 */
|
||||
#define _SCIF_PRIORITY_LEVEL14 (0x0000000EUL) /* Level 14 */
|
||||
#define _SCIF_PRIORITY_LEVEL15 (0x0000000FUL) /* Level 15 */
|
||||
|
||||
/* FIFO buffer maximum size */
|
||||
#define _SCIF_FIFO_MAX_SIZE (0x10U) /* Size of 16-stage FIFO buffer */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
#define _SCIF_1BIT_INTERVAL_2 (0x0619U) /* Wait time for 1-bit interval */
|
||||
#define _SCIF_RX_TRIG_NUM_2 (0x01U) /* Receive FIFO data trigger number */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Typedef definitions
|
||||
***********************************************************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
OVERRUN_ERROR,
|
||||
BREAK_DETECT,
|
||||
RECEIVE_ERROR
|
||||
} scif_error_type_t;
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global functions
|
||||
***********************************************************************************************************************/
|
||||
void R_SCIFA2_Create(void);
|
||||
void R_SCIFA2_Start(void);
|
||||
void R_SCIFA2_Stop(void);
|
||||
MD_STATUS R_SCIFA2_Serial_Send(const uint8_t * tx_buf, uint16_t tx_num);
|
||||
MD_STATUS R_SCIFA2_Serial_Receive(uint8_t * rx_buf, uint16_t rx_num);
|
||||
void r_scifa2_callback_transmitend(void);
|
||||
void r_scifa2_callback_receiveend(void);
|
||||
void r_scifa2_callback_error(scif_error_type_t error_type);
|
||||
|
||||
/* Start user code for function. Do not edit comment generated here */
|
||||
|
||||
/* Declared volatile to prevent it being optimised out in Release build mode */
|
||||
extern volatile uint8_t g_uart_in;
|
||||
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#endif
|
||||
@ -0,0 +1,497 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_scifa_user.c
|
||||
* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015]
|
||||
* Device(s) : R7S910018CBG
|
||||
* Tool-Chain : GCCARM
|
||||
* Description : This file implements device driver for SCIF module.
|
||||
* Creation Date: 19/04/2015
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_scifa.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
#include "r_typedefs.h"
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
#include "queue.h"
|
||||
#include "serial.h"
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
extern const uint8_t * gp_scifa2_tx_address; /* SCIFA2 send buffer address */
|
||||
extern uint16_t g_scifa2_tx_count; /* SCIFA2 send data number */
|
||||
extern uint8_t * gp_scifa2_rx_address; /* SCIFA2 receive buffer address */
|
||||
extern uint16_t g_scifa2_rx_count; /* SCIFA2 receive data number */
|
||||
extern uint16_t g_scifa2_rx_length; /* SCIFA2 receive data length */
|
||||
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
|
||||
/* Characters received from the UART are stored in this queue, ready to be
|
||||
received by the application. ***NOTE*** Using a queue in this way is very
|
||||
convenient, but also very inefficient. It can be used here because characters
|
||||
will only arrive slowly. In a higher bandwidth system a circular RAM buffer or
|
||||
DMA should be used in place of this queue. */
|
||||
static QueueHandle_t xRxQueue = NULL;
|
||||
|
||||
/* When a task calls vSerialPutString() its handle is stored in xSendingTask,
|
||||
before being placed into the Blocked state (so does not use any CPU time) to
|
||||
wait for the transmission to end. The task handle is then used from the UART
|
||||
transmit end interrupt to remove the task from the Blocked state. */
|
||||
static TaskHandle_t xSendingTask = NULL;
|
||||
|
||||
/*
|
||||
* Entry point for the handlers. These set the pxISRFunction variable to point
|
||||
* to the C handler for each timer, then branch to the FreeRTOS IRQ handler.
|
||||
*/
|
||||
#ifdef __GNUC__
|
||||
void r_scifa2_txif2_interrupt_entry( void ) __attribute__((naked));
|
||||
void r_scifa2_rxif2_interrupt_entry( void ) __attribute__((naked));
|
||||
void r_scifa2_drif2_interrupt_entry( void ) __attribute__((naked));
|
||||
void r_scifa2_brif2_interrupt_entry( void ) __attribute__((naked));
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
#ifdef __ICCARM__
|
||||
/* IAR requires the entry point to be in an assembly file. The functions
|
||||
are implemented in $PROJ_DIR$/System/IAR/Interrupt_Entry_Stubs.asm. */
|
||||
extern void r_scifa2_txif2_interrupt_entry( void );
|
||||
extern void r_scifa2_rxif2_interrupt_entry( void );
|
||||
extern void r_scifa2_drif2_interrupt_entry( void );
|
||||
extern void r_scifa2_brif2_interrupt_entry( void );
|
||||
#endif /* __ICCARM__ */
|
||||
|
||||
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_scifa2_txif2_interrupt
|
||||
* Description : This function is TXIF2 interrupt service routine.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void r_scifa2_txif2_interrupt(void)
|
||||
{
|
||||
uint16_t count = 0;
|
||||
|
||||
/* Get the amount of untransmitted data stored in the FRDR register */
|
||||
uint16_t dummy_fdr = SCIFA2.FDR.BIT.T;
|
||||
|
||||
/* Write data to the transmit FIFO data register */
|
||||
while ((g_scifa2_tx_count > 0U) && (count < _SCIF_FIFO_MAX_SIZE - dummy_fdr))
|
||||
{
|
||||
SCIFA2.FTDR = *gp_scifa2_tx_address;
|
||||
gp_scifa2_tx_address++;
|
||||
g_scifa2_tx_count--;
|
||||
count++;
|
||||
}
|
||||
|
||||
if (SCIFA2.FSR.BIT.TDFE == 1U)
|
||||
{
|
||||
SCIFA2.FSR.BIT.TDFE = 0U;
|
||||
}
|
||||
|
||||
if (g_scifa2_tx_count <= 0U)
|
||||
{
|
||||
SCIFA2.SCR.BIT.TIE = 0U;
|
||||
SCIFA2.SCR.BIT.TEIE = 1U;
|
||||
}
|
||||
|
||||
/* Wait the interrupt signal is disabled */
|
||||
while (0U != (VIC.IRQS3.LONG & 0x00008000UL))
|
||||
{
|
||||
VIC.IEC3.LONG = 0x00008000UL;
|
||||
}
|
||||
|
||||
VIC.IEN3.LONG |= 0x00008000UL;
|
||||
|
||||
/* Dummy write */
|
||||
VIC.HVA0.LONG = 0x00000000UL;
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_scifa2_rxif2_interrupt
|
||||
* Description : This function is RXIF2 interrupt service routine.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void r_scifa2_rxif2_interrupt(void)
|
||||
{
|
||||
uint16_t count = 0;
|
||||
|
||||
/* Get the amount of receive data stored in FRDR register */
|
||||
uint16_t dummy_fdr = SCIFA2.FDR.BIT.R;
|
||||
|
||||
/* Read data from the receive FIFO data register */
|
||||
while ((g_scifa2_rx_length > g_scifa2_rx_count) && (count < dummy_fdr))
|
||||
{
|
||||
*gp_scifa2_rx_address = SCIFA2.FRDR;
|
||||
gp_scifa2_rx_address++;
|
||||
g_scifa2_rx_count++;
|
||||
count++;
|
||||
}
|
||||
|
||||
/* If remaining data is less than the receive trigger number, receive interrupt will not occur.
|
||||
In this case, set trigger number to 1 to force receive interrupt for each one byte of data in FRDR */
|
||||
if ((g_scifa2_rx_length - g_scifa2_rx_count < _SCIF_RX_TRIG_NUM_2) && (SCIFA2.FTCR.BIT.RFTC != 1U))
|
||||
{
|
||||
SCIFA2.FTCR.BIT.RFTC = 1U;
|
||||
}
|
||||
|
||||
/* Clear receive FIFO data full flag */
|
||||
if (SCIFA2.FSR.BIT.RDF == 1U)
|
||||
{
|
||||
SCIFA2.FSR.BIT.RDF = 0U;
|
||||
}
|
||||
|
||||
if (g_scifa2_rx_length <= g_scifa2_rx_count)
|
||||
{
|
||||
/* All data received */
|
||||
SCIFA2.SCR.BIT.RE = 0U;
|
||||
r_scifa2_callback_receiveend();
|
||||
}
|
||||
|
||||
/* Wait the interrupt signal is disabled */
|
||||
while (0U != (VIC.IRQS3.LONG & 0x00004000UL))
|
||||
{
|
||||
VIC.IEC3.LONG = 0x00004000UL;
|
||||
}
|
||||
|
||||
VIC.IEN3.LONG |= 0x00004000UL;
|
||||
|
||||
/* Dummy write */
|
||||
VIC.HVA0.LONG = 0x00000000UL;
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_scifa2_drif2_interrupt
|
||||
* Description : This function is TEIF 2 or DRIF2 interrupt service routine.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void r_scifa2_drif2_interrupt(void)
|
||||
{
|
||||
if (1U == SCIFA2.FSR.BIT.TEND)
|
||||
{
|
||||
SCIFA2.SPTR.BIT.SPB2DT = 0U;
|
||||
SCIFA2.SPTR.BIT.SPB2IO = 1U;
|
||||
SCIFA2.SCR.BIT.TE = 0U;
|
||||
SCIFA2.SCR.BIT.TEIE = 0U;
|
||||
}
|
||||
r_scifa2_callback_transmitend();
|
||||
|
||||
/* Clear data ready detect flag */
|
||||
if (1U == SCIFA2.FSR.BIT.DR)
|
||||
{
|
||||
/* Start user code. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
SCIFA2.FSR.BIT.DR = 0U;
|
||||
}
|
||||
|
||||
/* Wait the interrupt signal is disabled */
|
||||
while (0U != (VIC.IRQS3.LONG & 0x00010000UL))
|
||||
{
|
||||
VIC.IEC3.LONG = 0x00010000UL;
|
||||
}
|
||||
|
||||
VIC.IEN3.LONG |= 0x00010000UL;
|
||||
|
||||
/* Dummy write */
|
||||
VIC.HVA0.LONG = 0x00000000UL;
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_scifa2_brif2_interrupt
|
||||
* Description : This function is BRIF2 or ERIF2 interrupt service routine.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void r_scifa2_brif2_interrupt(void)
|
||||
{
|
||||
if (1U == SCIFA2.FSR.BIT.BRK)
|
||||
{
|
||||
r_scifa2_callback_error(BREAK_DETECT);
|
||||
/* Clear break detect flag */
|
||||
SCIFA2.FSR.BIT.BRK = 0U;
|
||||
}
|
||||
|
||||
if (1U == SCIFA2.FSR.BIT.ER)
|
||||
{
|
||||
r_scifa2_callback_error(RECEIVE_ERROR);
|
||||
/* Clear receive error flag */
|
||||
SCIFA2.FSR.BIT.ER = 0U;
|
||||
}
|
||||
|
||||
if (1U == SCIFA2.LSR.BIT.ORER)
|
||||
{
|
||||
r_scifa2_callback_error(OVERRUN_ERROR);
|
||||
/* Clear overrun error flag */
|
||||
SCIFA2.LSR.BIT.ORER = 0U;
|
||||
}
|
||||
|
||||
/* Wait the interrupt signal is disabled */
|
||||
while (0U != (VIC.IRQS3.LONG & 0x00002000UL))
|
||||
{
|
||||
VIC.IEC3.LONG = 0x00002000UL;
|
||||
}
|
||||
|
||||
VIC.IEN3.LONG |= 0x00002000UL;
|
||||
|
||||
/* Dummy write */
|
||||
VIC.HVA0.LONG = 0x00000000UL;
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_scifa2_callback_transmitend
|
||||
* Description : This function is a callback function when SCIFA2 finishes transmission.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void r_scifa2_callback_transmitend(void)
|
||||
{
|
||||
/* Start user code. Do not edit comment generated here */
|
||||
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
|
||||
|
||||
if( xSendingTask != NULL )
|
||||
{
|
||||
/* A task is waiting for the end of the Tx, unblock it now.
|
||||
http://www.freertos.org/vTaskNotifyGiveFromISR.html */
|
||||
vTaskNotifyGiveFromISR( xSendingTask, &xHigherPriorityTaskWoken );
|
||||
xSendingTask = NULL;
|
||||
|
||||
portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
|
||||
}
|
||||
|
||||
/* End user code. Do not edit comment generated here */
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_scifa2_callback_receiveend
|
||||
* Description : This function is a callback function when SCIFA2 finishes reception.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void r_scifa2_callback_receiveend(void)
|
||||
{
|
||||
/* Start user code. Do not edit comment generated here */
|
||||
uint8_t ucRxedChar = 0;
|
||||
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
|
||||
|
||||
/* Read the received data */
|
||||
ucRxedChar = SCIFA2.FRDR;
|
||||
|
||||
/* Characters received from the UART are stored in this queue, ready to be
|
||||
received by the application. ***NOTE*** Using a queue in this way is very
|
||||
convenient, but also very inefficient. It can be used here because
|
||||
characters will only arrive slowly. In a higher bandwidth system a circular
|
||||
RAM buffer or DMA should be used in place of this queue. */
|
||||
xQueueSendFromISR( xRxQueue, ( void * ) &ucRxedChar, &xHigherPriorityTaskWoken );
|
||||
|
||||
/* Re-enable receptions */
|
||||
SCIFA2.SCR.BIT.RE = 1U;
|
||||
|
||||
/* End user code. Do not edit comment generated here */
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_scifa2_callback_error
|
||||
* Description : This function is a callback function when SCIFA2 reception encounters error.
|
||||
* Arguments : error_type -
|
||||
* reception error type
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void r_scifa2_callback_error(scif_error_type_t error_type)
|
||||
{
|
||||
/* Start user code. Do not edit comment generated here */
|
||||
|
||||
/* Used to suppress the warning message generated for unused variables */
|
||||
UNUSED_PARAM(error_type);
|
||||
|
||||
/* End user code. Do not edit comment generated here */
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
|
||||
/* Function required in order to link UARTCommandConsole.c - which is used by
|
||||
multiple different demo application. */
|
||||
xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
|
||||
{
|
||||
( void ) ulWantedBaud;
|
||||
( void ) uxQueueLength;
|
||||
|
||||
/* Characters received from the UART are stored in this queue, ready to be
|
||||
received by the application. ***NOTE*** Using a queue in this way is very
|
||||
convenient, but also very inefficient. It can be used here because
|
||||
characters will only arrive slowly. In a higher bandwidth system a circular
|
||||
RAM buffer or DMA should be used in place of this queue. */
|
||||
xRxQueue = xQueueCreate( uxQueueLength, sizeof( char ) );
|
||||
configASSERT( xRxQueue );
|
||||
|
||||
/* Enable the receive. */
|
||||
SCIFA2.FTCR.BIT.RFTC = _SCIF_RX_TRIG_NUM_2;
|
||||
|
||||
SCIFA2.SCR.BIT.RE = 1U;
|
||||
SCIFA2.SCR.BIT.RIE = 1U;
|
||||
SCIFA2.SCR.BIT.REIE = 1U;
|
||||
|
||||
/* Enable SCI1 operations */
|
||||
R_SCIFA2_Start();
|
||||
|
||||
/* Only one UART is supported, so it doesn't matter what is returned
|
||||
here. */
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Function required in order to link UARTCommandConsole.c - which is used by
|
||||
multiple different demo application. */
|
||||
void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength )
|
||||
{
|
||||
const TickType_t xMaxBlockTime = pdMS_TO_TICKS( 5000 );
|
||||
|
||||
/* Only one port is supported. */
|
||||
( void ) pxPort;
|
||||
|
||||
/* Don't send the string unless the previous string has been sent. */
|
||||
if( xSendingTask == NULL )
|
||||
{
|
||||
/* Ensure the calling task's notification state is not already
|
||||
pending. */
|
||||
vTaskNotifyStateClear( NULL );
|
||||
|
||||
/* Store the handle of the transmitting task. This is used to unblock
|
||||
the task when the transmission has completed. */
|
||||
xSendingTask = xTaskGetCurrentTaskHandle();
|
||||
|
||||
/* Send the string using the auto-generated API. */
|
||||
R_SCIFA2_Serial_Send( ( uint8_t * ) pcString, usStringLength );
|
||||
|
||||
/* Wait in the Blocked state (so not using any CPU time) until the
|
||||
transmission has completed. */
|
||||
ulTaskNotifyTake( pdTRUE, xMaxBlockTime );
|
||||
}
|
||||
}
|
||||
|
||||
/* Function required in order to link UARTCommandConsole.c - which is used by
|
||||
multiple different demo application. */
|
||||
signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, TickType_t xBlockTime )
|
||||
{
|
||||
/* Only one UART is supported. */
|
||||
( void ) pxPort;
|
||||
|
||||
/* Return a received character, if any are available. Otherwise block to
|
||||
wait for a character. */
|
||||
return xQueueReceive( xRxQueue, pcRxedChar, xBlockTime );
|
||||
}
|
||||
|
||||
/* Function required in order to link UARTCommandConsole.c - which is used by
|
||||
multiple different demo application. */
|
||||
signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, TickType_t xBlockTime )
|
||||
{
|
||||
/* Just mapped to vSerialPutString() so the block time is not used. */
|
||||
( void ) xBlockTime;
|
||||
|
||||
vSerialPutString( pxPort, &cOutChar, sizeof( cOutChar ) );
|
||||
return pdPASS;
|
||||
}
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/*
|
||||
* The RZ/T vectors directly to a peripheral specific interrupt handler, rather
|
||||
* than using the Cortex-R IRQ vector. Therefore each interrupt handler
|
||||
* installed by the application must follow the examples below, which save a
|
||||
* pointer to a standard C function in the pxISRFunction variable, before
|
||||
* branching to the FreeRTOS IRQ handler. The FreeRTOS IRQ handler then manages
|
||||
* interrupt entry (including interrupt nesting), before calling the C function
|
||||
* saved in the pxISRFunction variable. NOTE: The entry points are naked
|
||||
* functions - do not add C code to these functions.
|
||||
*/
|
||||
#ifdef __GNUC__
|
||||
/* The IAR equivalent is implemented in
|
||||
$PROJ_DIR$/System/IAR/Interrupt_Entry_Stubs.asm */
|
||||
void r_scifa2_txif2_interrupt_entry( void )
|
||||
{
|
||||
__asm volatile ( \
|
||||
"PUSH {r0-r1} \t\n" \
|
||||
"LDR r0, =pxISRFunction \t\n" \
|
||||
"LDR r1, =r_scifa2_txif2_interrupt \t\n" \
|
||||
"STR r1, [r0] \t\n" \
|
||||
"POP {r0-r1} \t\n" \
|
||||
"B FreeRTOS_IRQ_Handler "
|
||||
);
|
||||
}
|
||||
#endif /* __GNUC__ */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#ifdef __GNUC__
|
||||
/* The IAR equivalent is implemented in
|
||||
$PROJ_DIR$/System/IAR/Interrupt_Entry_Stubs.asm */
|
||||
void r_scifa2_rxif2_interrupt_entry( void )
|
||||
{
|
||||
__asm volatile ( \
|
||||
"PUSH {r0-r1} \t\n" \
|
||||
"LDR r0, =pxISRFunction \t\n" \
|
||||
"LDR r1, =r_scifa2_rxif2_interrupt \t\n" \
|
||||
"STR r1, [r0] \t\n" \
|
||||
"POP {r0-r1} \t\n" \
|
||||
"B FreeRTOS_IRQ_Handler "
|
||||
);
|
||||
}
|
||||
#endif /* __GNUC__ */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#ifdef __GNUC__
|
||||
/* The IAR equivalent is implemented in
|
||||
$PROJ_DIR$/System/IAR/Interrupt_Entry_Stubs.asm */
|
||||
void r_scifa2_drif2_interrupt_entry( void )
|
||||
{
|
||||
__asm volatile ( \
|
||||
"PUSH {r0-r1} \t\n" \
|
||||
"LDR r0, =pxISRFunction \t\n" \
|
||||
"LDR r1, =r_scifa2_drif2_interrupt \t\n" \
|
||||
"STR r1, [r0] \t\n" \
|
||||
"POP {r0-r1} \t\n" \
|
||||
"B FreeRTOS_IRQ_Handler "
|
||||
);
|
||||
}
|
||||
#endif /* __GNUC__ */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#ifdef __GNUC__
|
||||
/* The IAR equivalent is implemented in
|
||||
$PROJ_DIR$/System/IAR/Interrupt_Entry_Stubs.asm */
|
||||
void r_scifa2_brif2_interrupt_entry( void )
|
||||
{
|
||||
__asm volatile ( \
|
||||
"PUSH {r0-r1} \t\n" \
|
||||
"LDR r0, =pxISRFunction \t\n" \
|
||||
"LDR r1, =r_scifa2_brif2_interrupt \t\n" \
|
||||
"STR r1, [r0] \t\n" \
|
||||
"POP {r0-r1} \t\n" \
|
||||
"B FreeRTOS_IRQ_Handler "
|
||||
);
|
||||
}
|
||||
#endif /* __GNUC__ */
|
||||
/*-----------------------------------------------------------*/
|
||||
Loading…
Reference in New Issue