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@ -194,7 +194,7 @@ extern void vPortRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION;
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/**
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* @brief Enter critical section.
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*/
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#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
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#if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
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void vPortEnterCritical( void ) FREERTOS_SYSTEM_CALL;
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#else
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void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
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@ -203,7 +203,7 @@ extern void vPortRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION;
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/**
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* @brief Exit from critical section.
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*/
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#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
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#if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
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void vPortExitCritical( void ) FREERTOS_SYSTEM_CALL;
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#else
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void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
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@ -316,9 +316,9 @@ void vPortSVCHandler_C( uint32_t * pulParam )
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{
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__asm volatile
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(
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" mrs r1, control \n"/* Obtain current control value. */
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" bic r1, r1, #1 \n"/* Set privilege bit. */
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" msr control, r1 \n"/* Write back new control value. */
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" mrs r1, control \n" /* Obtain current control value. */
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" bic r1, r1, #1 \n" /* Set privilege bit. */
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" msr control, r1 \n" /* Write back new control value. */
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::: "r1", "memory"
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);
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}
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@ -328,9 +328,9 @@ void vPortSVCHandler_C( uint32_t * pulParam )
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case portSVC_RAISE_PRIVILEGE:
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__asm volatile
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(
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" mrs r1, control \n"/* Obtain current control value. */
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" bic r1, r1, #1 \n"/* Set privilege bit. */
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" msr control, r1 \n"/* Write back new control value. */
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" mrs r1, control \n" /* Obtain current control value. */
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" bic r1, r1, #1 \n" /* Set privilege bit. */
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" msr control, r1 \n" /* Write back new control value. */
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::: "r1", "memory"
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);
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break;
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@ -352,6 +352,7 @@ BaseType_t xPortStartScheduler( void )
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#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
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configASSERT( ( portCPUID == portCORTEX_M7_r0p1_ID ) || ( portCPUID == portCORTEX_M7_r0p0_ID ) );
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#else
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/* When using this port on a Cortex-M7 r0p0 or r0p1 core, define
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* configENABLE_ERRATA_837070_WORKAROUND to 1 in your
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* FreeRTOSConfig.h. */
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@ -360,74 +361,101 @@ BaseType_t xPortStartScheduler( void )
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#endif
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#if ( configASSERT_DEFINED == 1 )
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{
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volatile uint32_t ulOriginalPriority;
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volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
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volatile uint8_t ucMaxPriorityValue;
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/* Determine the maximum priority from which ISR safe FreeRTOS API
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* functions can be called. ISR safe functions are those that end in
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* "FromISR". FreeRTOS maintains separate thread and ISR API functions to
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* ensure interrupt entry is as fast and simple as possible.
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*
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* Save the interrupt priority value that is about to be clobbered. */
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ulOriginalPriority = *pucFirstUserPriorityRegister;
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{
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volatile uint32_t ulOriginalPriority;
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volatile uint32_t ulImplementedPrioBits = 0;
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volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
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volatile uint8_t ucMaxPriorityValue;
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/* Determine the maximum priority from which ISR safe FreeRTOS API
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* functions can be called. ISR safe functions are those that end in
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* "FromISR". FreeRTOS maintains separate thread and ISR API functions to
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* ensure interrupt entry is as fast and simple as possible.
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*
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* Save the interrupt priority value that is about to be clobbered. */
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ulOriginalPriority = *pucFirstUserPriorityRegister;
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/* Determine the number of priority bits available. First write to all
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* possible bits. */
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*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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/* Determine the number of priority bits available. First write to all
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* possible bits. */
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*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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/* Read the value back to see how many bits stuck. */
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ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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/* Read the value back to see how many bits stuck. */
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ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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/* Use the same mask on the maximum system call priority. */
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ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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/* Use the same mask on the maximum system call priority. */
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ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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/* Check that the maximum system call priority is nonzero after
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* accounting for the number of priority bits supported by the
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* hardware. A priority of 0 is invalid because setting the BASEPRI
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* register to 0 unmasks all interrupts, and interrupts with priority 0
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* cannot be masked using BASEPRI.
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* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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configASSERT( ucMaxSysCallPriority );
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/* Check that the maximum system call priority is nonzero after
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* accounting for the number of priority bits supported by the
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* hardware. A priority of 0 is invalid because setting the BASEPRI
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* register to 0 unmasks all interrupts, and interrupts with priority 0
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* cannot be masked using BASEPRI.
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* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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configASSERT( ucMaxSysCallPriority );
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/* Calculate the maximum acceptable priority group value for the number
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* of bits read back. */
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ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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/* Calculate the maximum acceptable priority group value for the number
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* of bits read back. */
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while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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{
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ulMaxPRIGROUPValue--;
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ucMaxPriorityValue <<= ( uint8_t ) 0x01;
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}
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while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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{
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ulImplementedPrioBits++;
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ucMaxPriorityValue <<= ( uint8_t ) 0x01;
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}
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#ifdef __NVIC_PRIO_BITS
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{
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/* Check the CMSIS configuration that defines the number of
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* priority bits matches the number of priority bits actually queried
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* from the hardware. */
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configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
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}
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#endif
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#ifdef configPRIO_BITS
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{
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/* Check the FreeRTOS configuration that defines the number of
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* priority bits matches the number of priority bits actually queried
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* from the hardware. */
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configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
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}
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#endif
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/* Shift the priority group value back to its position within the AIRCR
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* register. */
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ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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/* Restore the clobbered interrupt priority register to its original
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* value. */
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*pucFirstUserPriorityRegister = ulOriginalPriority;
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if( ulImplementedPrioBits == 8 )
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{
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/* When the hardware implements 8 priority bits, there is no way for
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* the software to configure PRIGROUP to not have sub-priorities. As
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* a result, the least significant bit is always used for sub-priority
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* and there are 128 preemption priorities and 2 sub-priorities.
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*
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* This may cause some confusion in some cases - for example, if
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* configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4
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* priority interrupts will be masked in Critical Sections as those
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* are at the same preemption priority. This may appear confusing as
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* 4 is higher (numerically lower) priority than
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* configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not
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* have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY
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* to 4, this confusion does not happen and the behaviour remains the same.
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*
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* The following assert ensures that the sub-priority bit in the
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* configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned
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* confusion. */
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configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U );
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ulMaxPRIGROUPValue = 0;
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}
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else
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{
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ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
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}
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#ifdef __NVIC_PRIO_BITS
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{
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/* Check the CMSIS configuration that defines the number of
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* priority bits matches the number of priority bits actually queried
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* from the hardware. */
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configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
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}
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#endif
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#ifdef configPRIO_BITS
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{
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/* Check the FreeRTOS configuration that defines the number of
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* priority bits matches the number of priority bits actually queried
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* from the hardware. */
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configASSERT( ulImplementedPrioBits == configPRIO_BITS );
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}
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#endif
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/* Shift the priority group value back to its position within the AIRCR
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* register. */
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ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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/* Restore the clobbered interrupt priority register to its original
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* value. */
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*pucFirstUserPriorityRegister = ulOriginalPriority;
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}
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#endif /* configASSERT_DEFINED */
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/* Make PendSV and SysTick the lowest priority interrupts. */
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@ -468,32 +496,49 @@ void vPortEndScheduler( void )
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void vPortEnterCritical( void )
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{
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#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
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if( portIS_PRIVILEGED() == pdFALSE )
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{
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portRAISE_PRIVILEGE();
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portMEMORY_BARRIER();
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#if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
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if( portIS_PRIVILEGED() == pdFALSE )
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{
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portRAISE_PRIVILEGE();
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portMEMORY_BARRIER();
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portDISABLE_INTERRUPTS();
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uxCriticalNesting++;
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/* This is not the interrupt safe version of the enter critical function so
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* assert() if it is being called from an interrupt context. Only API
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* functions that end in "FromISR" can be used in an interrupt. Only assert if
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* the critical nesting count is 1 to protect against recursive calls if the
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* assert function also uses a critical section. */
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if( uxCriticalNesting == 1 )
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{
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configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
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}
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portDISABLE_INTERRUPTS();
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uxCriticalNesting++;
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/* This is not the interrupt safe version of the enter critical function so
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* assert() if it is being called from an interrupt context. Only API
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* functions that end in "FromISR" can be used in an interrupt. Only assert if
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* the critical nesting count is 1 to protect against recursive calls if the
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* assert function also uses a critical section. */
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if( uxCriticalNesting == 1 )
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portMEMORY_BARRIER();
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portRESET_PRIVILEGE();
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portMEMORY_BARRIER();
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}
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else
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{
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configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
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portDISABLE_INTERRUPTS();
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uxCriticalNesting++;
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/* This is not the interrupt safe version of the enter critical function so
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* assert() if it is being called from an interrupt context. Only API
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* functions that end in "FromISR" can be used in an interrupt. Only assert if
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* the critical nesting count is 1 to protect against recursive calls if the
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* assert function also uses a critical section. */
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if( uxCriticalNesting == 1 )
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{
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configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
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}
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}
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portMEMORY_BARRIER();
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portRESET_PRIVILEGE();
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portMEMORY_BARRIER();
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}
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else
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{
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#else /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
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portDISABLE_INTERRUPTS();
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uxCriticalNesting++;
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/* This is not the interrupt safe version of the enter critical function so
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* assert() if it is being called from an interrupt context. Only API
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* functions that end in "FromISR" can be used in an interrupt. Only assert if
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@ -503,45 +548,42 @@ void vPortEnterCritical( void )
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{
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configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
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}
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}
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#else
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portDISABLE_INTERRUPTS();
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uxCriticalNesting++;
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/* This is not the interrupt safe version of the enter critical function so
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* assert() if it is being called from an interrupt context. Only API
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* functions that end in "FromISR" can be used in an interrupt. Only assert if
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* the critical nesting count is 1 to protect against recursive calls if the
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* assert function also uses a critical section. */
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if( uxCriticalNesting == 1 )
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{
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configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
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}
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#endif
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#endif /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
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}
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/*-----------------------------------------------------------*/
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void vPortExitCritical( void )
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{
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#if( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
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if( portIS_PRIVILEGED() == pdFALSE )
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{
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portRAISE_PRIVILEGE();
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portMEMORY_BARRIER();
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#if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 )
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if( portIS_PRIVILEGED() == pdFALSE )
|
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{
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portRAISE_PRIVILEGE();
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portMEMORY_BARRIER();
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configASSERT( uxCriticalNesting );
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uxCriticalNesting--;
|
|
|
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|
configASSERT( uxCriticalNesting );
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uxCriticalNesting--;
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if( uxCriticalNesting == 0 )
|
|
|
|
|
{
|
|
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|
|
portENABLE_INTERRUPTS();
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|
|
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|
if( uxCriticalNesting == 0 )
|
|
|
|
|
{
|
|
|
|
|
portENABLE_INTERRUPTS();
|
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|
}
|
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portMEMORY_BARRIER();
|
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|
portRESET_PRIVILEGE();
|
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|
|
|
portMEMORY_BARRIER();
|
|
|
|
|
}
|
|
|
|
|
portMEMORY_BARRIER();
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
configASSERT( uxCriticalNesting );
|
|
|
|
|
uxCriticalNesting--;
|
|
|
|
|
|
|
|
|
|
portRESET_PRIVILEGE();
|
|
|
|
|
portMEMORY_BARRIER();
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
if( uxCriticalNesting == 0 )
|
|
|
|
|
{
|
|
|
|
|
portENABLE_INTERRUPTS();
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
#else /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
|
|
|
|
|
configASSERT( uxCriticalNesting );
|
|
|
|
|
uxCriticalNesting--;
|
|
|
|
|
|
|
|
|
|
@ -549,16 +591,7 @@ void vPortExitCritical( void )
|
|
|
|
|
{
|
|
|
|
|
portENABLE_INTERRUPTS();
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
#else
|
|
|
|
|
configASSERT( uxCriticalNesting );
|
|
|
|
|
uxCriticalNesting--;
|
|
|
|
|
|
|
|
|
|
if( uxCriticalNesting == 0 )
|
|
|
|
|
{
|
|
|
|
|
portENABLE_INTERRUPTS();
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* if ( configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS == 1 ) */
|
|
|
|
|
}
|
|
|
|
|
/*-----------------------------------------------------------*/
|
|
|
|
|
|
|
|
|
|
@ -710,7 +743,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
|
|
|
|
|
xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
|
|
|
|
|
( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
|
|
|
|
|
( portMPU_REGION_VALID ) |
|
|
|
|
|
( portSTACK_REGION ); /* Region number. */
|
|
|
|
|
( portSTACK_REGION ); /* Region number. */
|
|
|
|
|
|
|
|
|
|
xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
|
|
|
|
|
( portMPU_REGION_READ_WRITE ) |
|
|
|
|
|
|
kar-rahul-aws
2 years ago
committed by
GitHub