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Richard Barry 14 years ago
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commit 983e91b440
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1102
Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS/a2fxxxm3.h
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Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS/core_cm3.c
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/**************************************************************************//**
* @file core_cm3.c
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
* @version V1.30
* @date 30. October 2009
*
* @note
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
/* define compiler specific symbols */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#endif
/* ################### Compiler specific Intrinsics ########################### */
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
__ASM uint32_t __get_PSP(void)
{
mrs r0, psp
bx lr
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
__ASM void __set_PSP(uint32_t topOfProcStack)
{
msr psp, r0
bx lr
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
__ASM uint32_t __get_MSP(void)
{
mrs r0, msp
bx lr
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
__ASM void __set_MSP(uint32_t mainStackPointer)
{
msr msp, r0
bx lr
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
__ASM uint32_t __REV16(uint16_t value)
{
rev16 r0, r0
bx lr
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
__ASM int32_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#if (__ARMCC_VERSION < 400000)
/**
* @brief Remove the exclusive lock created by ldrex
*
* Removes the exclusive lock which is created by ldrex.
*/
__ASM void __CLREX(void)
{
clrex
}
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
__ASM uint32_t __get_BASEPRI(void)
{
mrs r0, basepri
bx lr
}
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
__ASM void __set_BASEPRI(uint32_t basePri)
{
msr basepri, r0
bx lr
}
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
__ASM uint32_t __get_PRIMASK(void)
{
mrs r0, primask
bx lr
}
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
__ASM void __set_PRIMASK(uint32_t priMask)
{
msr primask, r0
bx lr
}
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
__ASM uint32_t __get_FAULTMASK(void)
{
mrs r0, faultmask
bx lr
}
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
__ASM void __set_FAULTMASK(uint32_t faultMask)
{
msr faultmask, r0
bx lr
}
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
__ASM uint32_t __get_CONTROL(void)
{
mrs r0, control
bx lr
}
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
__ASM void __set_CONTROL(uint32_t control)
{
msr control, r0
bx lr
}
#endif /* __ARMCC_VERSION */
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#pragma diag_suppress=Pe940
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
uint32_t __get_PSP(void)
{
__ASM("mrs r0, psp");
__ASM("bx lr");
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
void __set_PSP(uint32_t topOfProcStack)
{
__ASM("msr psp, r0");
__ASM("bx lr");
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
uint32_t __get_MSP(void)
{
__ASM("mrs r0, msp");
__ASM("bx lr");
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
void __set_MSP(uint32_t topOfMainStack)
{
__ASM("msr msp, r0");
__ASM("bx lr");
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
uint32_t __REV16(uint16_t value)
{
__ASM("rev16 r0, r0");
__ASM("bx lr");
}
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
uint32_t __RBIT(uint32_t value)
{
__ASM("rbit r0, r0");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit values)
*/
uint8_t __LDREXB(uint8_t *addr)
{
__ASM("ldrexb r0, [r0]");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
uint16_t __LDREXH(uint16_t *addr)
{
__ASM("ldrexh r0, [r0]");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
uint32_t __LDREXW(uint32_t *addr)
{
__ASM("ldrex r0, [r0]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
__ASM("strexb r0, r0, [r1]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
__ASM("strexh r0, r0, [r1]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
__ASM("strex r0, r0, [r1]");
__ASM("bx lr");
}
#pragma diag_default=Pe940
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
uint32_t __get_PSP(void) __attribute__( ( naked ) );
uint32_t __get_PSP(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, psp\n\t"
"MOV r0, %0 \n\t"
"BX lr \n\t" : "=r" (result) );
return(result);
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n\t"
"BX lr \n\t" : : "r" (topOfProcStack) );
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
uint32_t __get_MSP(void) __attribute__( ( naked ) );
uint32_t __get_MSP(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, msp\n\t"
"MOV r0, %0 \n\t"
"BX lr \n\t" : "=r" (result) );
return(result);
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n\t"
"BX lr \n\t" : : "r" (topOfMainStack) );
}
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
uint32_t __get_BASEPRI(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
}
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
uint32_t __get_PRIMASK(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
uint32_t __get_FAULTMASK(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
}
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
uint32_t __get_CONTROL(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) );
}
/**
* @brief Reverse byte order in integer value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in integer value
*/
uint32_t __REV(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
uint32_t __REV16(uint16_t value)
{
uint32_t result=0;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
int32_t __REVSH(int16_t value)
{
uint32_t result=0;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
uint32_t __RBIT(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit value
*/
uint8_t __LDREXB(uint8_t *addr)
{
uint8_t result=0;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
uint16_t __LDREXH(uint16_t *addr)
{
uint16_t result=0;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
uint32_t __LDREXW(uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif

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Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS/core_cm3.h
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Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS/mss_assert.h
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/*******************************************************************************
* (c) Copyright 2009 Actel Corporation. All rights reserved.
*
* Assertion implementation.
*
* This file provides the implementation of the ASSERT macro. This file can be
* modified to cater for project specific requirements regarding the way
* assertions are handled.
*
* SVN $Revision: 1676 $
* SVN $Date: 2009-12-02 16:47:03 +0000 (Wed, 02 Dec 2009) $
*/
#ifndef __MSS_ASSERT_H_
#define __MSS_ASSERT_H_
#include <assert.h>
#if defined ( __GNUC__ )
#if defined(NDEBUG)
#define ASSERT(CHECK)
#else /* NDEBUG */
/*
* SoftConsole assertion handling
*/
#define ASSERT(CHECK) \
do { \
if (!(CHECK)) \
{ \
__asm volatile ("BKPT\n\t"); \
} \
} while (0);
#endif /* NDEBUG */
#else
/*
* IAR Embedded Workbench or Keil assertion handling.
* Call C library assert function which should result in error message
* displayed in debugger.
*/
#define ASSERT(X) assert(X)
#endif
#endif /* __MSS_ASSERT_H_ */

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Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS/startup_iar/startup_a2fxxxm3.s
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/*******************************************************************************
* (c) Copyright 2009 Actel Corporation. All rights reserved.
*
* Startup code for SmartFusion A2FM3Fxxx
*
* SVN $Revision: 2068 $
* SVN $Date: 2010-01-27 17:27:41 +0000 (Wed, 27 Jan 2010) $
*/
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
; EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler
DCD NMI_Handler
DCD HardFault_Handler
DCD MemManage_Handler
DCD BusFault_Handler
DCD UsageFault_Handler
DCD 0
DCD 0
DCD 0
DCD 0
DCD SVC_Handler
DCD DebugMon_Handler
DCD 0
DCD PendSV_Handler
DCD SysTick_Handler
; External Interrupts
DCD WdogWakeup_IRQHandler
DCD BrownOut_1_5V_IRQHandler
DCD BrownOut_3_3V_IRQHandler
DCD RTC_Match_IRQHandler
DCD RTCIF_Pub_IRQHandler
DCD EthernetMAC_IRQHandler
DCD IAP_IRQHandler
DCD ENVM0_IRQHandler
DCD ENVM1_IRQHandler
DCD DMA_IRQHandler
DCD UART0_IRQHandler
DCD UART1_IRQHandler
DCD SPI0_IRQHandler
DCD SPI1_IRQHandler
DCD I2C0_IRQHandler
DCD I2C0_SMBAlert_IRQHandler
DCD I2C0_SMBus_IRQHandler
DCD I2C1_IRQHandler
DCD I2C1_SMBAlert_IRQHandler
DCD I2C1_SMBus_IRQHandler
DCD Timer1_IRQHandler
DCD Timer2_IRQHandler
DCD PLL_Lock_IRQHandler
DCD PLL_LockLost_IRQHandler
DCD CommError_IRQHandler
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD Fabric_IRQHandler
DCD GPIO0_IRQHandler
DCD GPIO1_IRQHandler
DCD GPIO2_IRQHandler
DCD GPIO3_IRQHandler
DCD GPIO4_IRQHandler
DCD GPIO5_IRQHandler
DCD GPIO6_IRQHandler
DCD GPIO7_IRQHandler
DCD GPIO8_IRQHandler
DCD GPIO9_IRQHandler
DCD GPIO10_IRQHandler
DCD GPIO11_IRQHandler
DCD GPIO12_IRQHandler
DCD GPIO13_IRQHandler
DCD GPIO14_IRQHandler
DCD GPIO15_IRQHandler
DCD GPIO16_IRQHandler
DCD GPIO17_IRQHandler
DCD GPIO18_IRQHandler
DCD GPIO19_IRQHandler
DCD GPIO20_IRQHandler
DCD GPIO21_IRQHandler
DCD GPIO22_IRQHandler
DCD GPIO23_IRQHandler
DCD GPIO24_IRQHandler
DCD GPIO25_IRQHandler
DCD GPIO26_IRQHandler
DCD GPIO27_IRQHandler
DCD GPIO28_IRQHandler
DCD GPIO29_IRQHandler
DCD GPIO30_IRQHandler
DCD GPIO31_IRQHandler
DCD ACE_PC0_Flag0_IRQHandler
DCD ACE_PC0_Flag1_IRQHandler
DCD ACE_PC0_Flag2_IRQHandler
DCD ACE_PC0_Flag3_IRQHandler
DCD ACE_PC1_Flag0_IRQHandler
DCD ACE_PC1_Flag1_IRQHandler
DCD ACE_PC1_Flag2_IRQHandler
DCD ACE_PC1_Flag3_IRQHandler
DCD ACE_PC2_Flag0_IRQHandler
DCD ACE_PC2_Flag1_IRQHandler
DCD ACE_PC2_Flag2_IRQHandler
DCD ACE_PC2_Flag3_IRQHandler
DCD ACE_ADC0_DataValid_IRQHandler
DCD ACE_ADC1_DataValid_IRQHandler
DCD ACE_ADC2_DataValid_IRQHandler
DCD ACE_ADC0_CalDone_IRQHandler
DCD ACE_ADC1_CalDone_IRQHandler
DCD ACE_ADC2_CalDone_IRQHandler
DCD ACE_ADC0_CalStart_IRQHandler
DCD ACE_ADC1_CalStart_IRQHandler
DCD ACE_ADC2_CalStart_IRQHandler
DCD ACE_Comp0_Fall_IRQHandler
DCD ACE_Comp1_Fall_IRQHandler
DCD ACE_Comp2_Fall_IRQHandler
DCD ACE_Comp3_Fall_IRQHandler
DCD ACE_Comp4_Fall_IRQHandler
DCD ACE_Comp5_Fall_IRQHandler
DCD ACE_Comp6_Fall_IRQHandler
DCD ACE_Comp7_Fall_IRQHandler
DCD ACE_Comp8_Fall_IRQHandler
DCD ACE_Comp9_Fall_IRQHandler
DCD ACE_Comp10_Fall_IRQHandler
DCD ACE_Comp11_Fall_IRQHandler
DCD ACE_Comp0_Rise_IRQHandler
DCD ACE_Comp1_Rise_IRQHandler
DCD ACE_Comp2_Rise_IRQHandler
DCD ACE_Comp3_Rise_IRQHandler
DCD ACE_Comp4_Rise_IRQHandler
DCD ACE_Comp5_Rise_IRQHandler
DCD ACE_Comp6_Rise_IRQHandler
DCD ACE_Comp7_Rise_IRQHandler
DCD ACE_Comp8_Rise_IRQHandler
DCD ACE_Comp9_Rise_IRQHandler
DCD ACE_Comp10_Rise_IRQHandler
DCD ACE_Comp11_Rise_IRQHandler
DCD ACE_ADC0_FifoFull_IRQHandler
DCD ACE_ADC0_FifoAFull_IRQHandler
DCD ACE_ADC0_FifoEmpty_IRQHandler
DCD ACE_ADC1_FifoFull_IRQHandler
DCD ACE_ADC1_FifoAFull_IRQHandler
DCD ACE_ADC1_FifoEmpty_IRQHandler
DCD ACE_ADC2_FifoFull_IRQHandler
DCD ACE_ADC2_FifoAFull_IRQHandler
DCD ACE_ADC2_FifoEmpty_IRQHandler
DCD ACE_PPE_Flag0_IRQHandler
DCD ACE_PPE_Flag1_IRQHandler
DCD ACE_PPE_Flag2_IRQHandler
DCD ACE_PPE_Flag3_IRQHandler
DCD ACE_PPE_Flag4_IRQHandler
DCD ACE_PPE_Flag5_IRQHandler
DCD ACE_PPE_Flag6_IRQHandler
DCD ACE_PPE_Flag7_IRQHandler
DCD ACE_PPE_Flag8_IRQHandler
DCD ACE_PPE_Flag9_IRQHandler
DCD ACE_PPE_Flag10_IRQHandler
DCD ACE_PPE_Flag11_IRQHandler
DCD ACE_PPE_Flag12_IRQHandler
DCD ACE_PPE_Flag13_IRQHandler
DCD ACE_PPE_Flag14_IRQHandler
DCD ACE_PPE_Flag15_IRQHandler
DCD ACE_PPE_Flag16_IRQHandler
DCD ACE_PPE_Flag17_IRQHandler
DCD ACE_PPE_Flag18_IRQHandler
DCD ACE_PPE_Flag19_IRQHandler
DCD ACE_PPE_Flag20_IRQHandler
DCD ACE_PPE_Flag21_IRQHandler
DCD ACE_PPE_Flag22_IRQHandler
DCD ACE_PPE_Flag23_IRQHandler
DCD ACE_PPE_Flag24_IRQHandler
DCD ACE_PPE_Flag25_IRQHandler
DCD ACE_PPE_Flag26_IRQHandler
DCD ACE_PPE_Flag27_IRQHandler
DCD ACE_PPE_Flag28_IRQHandler
DCD ACE_PPE_Flag29_IRQHandler
DCD ACE_PPE_Flag30_IRQHandler
DCD ACE_PPE_Flag31_IRQHandler
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
; LDR R0, =SystemInit
; BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WdogWakeup_IRQHandler
SECTION .text:CODE:REORDER(1)
WdogWakeup_IRQHandler
B WdogWakeup_IRQHandler
PUBWEAK BrownOut_1_5V_IRQHandler
SECTION .text:CODE:REORDER(1)
BrownOut_1_5V_IRQHandler
B BrownOut_1_5V_IRQHandler
PUBWEAK BrownOut_3_3V_IRQHandler
SECTION .text:CODE:REORDER(1)
BrownOut_3_3V_IRQHandler
B BrownOut_3_3V_IRQHandler
PUBWEAK RTC_Match_IRQHandler
SECTION .text:CODE:REORDER(1)
RTC_Match_IRQHandler
B RTC_Match_IRQHandler
PUBWEAK RTCIF_Pub_IRQHandler
SECTION .text:CODE:REORDER(1)
RTCIF_Pub_IRQHandler
B RTCIF_Pub_IRQHandler
PUBWEAK EthernetMAC_IRQHandler
SECTION .text:CODE:REORDER(1)
EthernetMAC_IRQHandler
B EthernetMAC_IRQHandler
PUBWEAK IAP_IRQHandler
SECTION .text:CODE:REORDER(1)
IAP_IRQHandler
B IAP_IRQHandler
PUBWEAK ENVM0_IRQHandler
SECTION .text:CODE:REORDER(1)
ENVM0_IRQHandler
B ENVM0_IRQHandler
PUBWEAK ENVM1_IRQHandler
SECTION .text:CODE:REORDER(1)
ENVM1_IRQHandler
B ENVM1_IRQHandler
PUBWEAK DMA_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA_IRQHandler
B DMA_IRQHandler
PUBWEAK UART0_IRQHandler
SECTION .text:CODE:REORDER(1)
UART0_IRQHandler
B UART0_IRQHandler
PUBWEAK UART1_IRQHandler
SECTION .text:CODE:REORDER(1)
UART1_IRQHandler
B UART1_IRQHandler
PUBWEAK SPI0_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI0_IRQHandler
B SPI0_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK I2C0_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C0_IRQHandler
B I2C0_IRQHandler
PUBWEAK I2C0_SMBAlert_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C0_SMBAlert_IRQHandler
B I2C0_SMBAlert_IRQHandler
PUBWEAK I2C0_SMBus_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C0_SMBus_IRQHandler
B I2C0_SMBus_IRQHandler
PUBWEAK I2C1_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_IRQHandler
B I2C1_IRQHandler
PUBWEAK I2C1_SMBAlert_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_SMBAlert_IRQHandler
B I2C1_SMBAlert_IRQHandler
PUBWEAK I2C1_SMBus_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_SMBus_IRQHandler
B I2C1_SMBus_IRQHandler
PUBWEAK Timer1_IRQHandler
SECTION .text:CODE:REORDER(1)
Timer1_IRQHandler
B Timer1_IRQHandler
PUBWEAK Timer2_IRQHandler
SECTION .text:CODE:REORDER(1)
Timer2_IRQHandler
B Timer2_IRQHandler
PUBWEAK PLL_Lock_IRQHandler
SECTION .text:CODE:REORDER(1)
PLL_Lock_IRQHandler
B PLL_Lock_IRQHandler
PUBWEAK PLL_LockLost_IRQHandler
SECTION .text:CODE:REORDER(1)
PLL_LockLost_IRQHandler
B PLL_LockLost_IRQHandler
PUBWEAK CommError_IRQHandler
SECTION .text:CODE:REORDER(1)
CommError_IRQHandler
B CommError_IRQHandler
PUBWEAK Fabric_IRQHandler
SECTION .text:CODE:REORDER(1)
Fabric_IRQHandler
B Fabric_IRQHandler
PUBWEAK GPIO0_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO0_IRQHandler
B GPIO0_IRQHandler
PUBWEAK GPIO1_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO1_IRQHandler
B GPIO1_IRQHandler
PUBWEAK GPIO2_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO2_IRQHandler
B GPIO2_IRQHandler
PUBWEAK GPIO3_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO3_IRQHandler
B GPIO3_IRQHandler
PUBWEAK GPIO4_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO4_IRQHandler
B GPIO4_IRQHandler
PUBWEAK GPIO5_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO5_IRQHandler
B GPIO5_IRQHandler
PUBWEAK GPIO6_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO6_IRQHandler
B GPIO6_IRQHandler
PUBWEAK GPIO7_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO7_IRQHandler
B GPIO7_IRQHandler
PUBWEAK GPIO8_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO8_IRQHandler
B GPIO8_IRQHandler
PUBWEAK GPIO9_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO9_IRQHandler
B GPIO9_IRQHandler
PUBWEAK GPIO10_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO10_IRQHandler
B GPIO10_IRQHandler
PUBWEAK GPIO11_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO11_IRQHandler
B GPIO11_IRQHandler
PUBWEAK GPIO12_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO12_IRQHandler
B GPIO12_IRQHandler
PUBWEAK GPIO13_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO13_IRQHandler
B GPIO13_IRQHandler
PUBWEAK GPIO14_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO14_IRQHandler
B GPIO14_IRQHandler
PUBWEAK GPIO15_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO15_IRQHandler
B GPIO15_IRQHandler
PUBWEAK GPIO16_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO16_IRQHandler
B GPIO16_IRQHandler
PUBWEAK GPIO17_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO17_IRQHandler
B GPIO17_IRQHandler
PUBWEAK GPIO18_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO18_IRQHandler
B GPIO18_IRQHandler
PUBWEAK GPIO19_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO19_IRQHandler
B GPIO19_IRQHandler
PUBWEAK GPIO20_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO20_IRQHandler
B GPIO20_IRQHandler
PUBWEAK GPIO21_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO21_IRQHandler
B GPIO21_IRQHandler
PUBWEAK GPIO22_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO22_IRQHandler
B GPIO22_IRQHandler
PUBWEAK GPIO23_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO23_IRQHandler
B GPIO23_IRQHandler
PUBWEAK GPIO24_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO24_IRQHandler
B GPIO24_IRQHandler
PUBWEAK GPIO25_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO25_IRQHandler
B GPIO25_IRQHandler
PUBWEAK GPIO26_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO26_IRQHandler
B GPIO26_IRQHandler
PUBWEAK GPIO27_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO27_IRQHandler
B GPIO27_IRQHandler
PUBWEAK GPIO28_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO28_IRQHandler
B GPIO28_IRQHandler
PUBWEAK GPIO29_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO29_IRQHandler
B GPIO29_IRQHandler
PUBWEAK GPIO30_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO30_IRQHandler
B GPIO30_IRQHandler
PUBWEAK GPIO31_IRQHandler
SECTION .text:CODE:REORDER(1)
GPIO31_IRQHandler
B GPIO31_IRQHandler
PUBWEAK ACE_PC0_Flag0_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PC0_Flag0_IRQHandler
B ACE_PC0_Flag0_IRQHandler
PUBWEAK ACE_PC0_Flag1_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PC0_Flag1_IRQHandler
B ACE_PC0_Flag1_IRQHandler
PUBWEAK ACE_PC0_Flag2_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PC0_Flag2_IRQHandler
B ACE_PC0_Flag2_IRQHandler
PUBWEAK ACE_PC0_Flag3_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PC0_Flag3_IRQHandler
B ACE_PC0_Flag3_IRQHandler
PUBWEAK ACE_PC1_Flag0_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PC1_Flag0_IRQHandler
B ACE_PC1_Flag0_IRQHandler
PUBWEAK ACE_PC1_Flag1_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PC1_Flag1_IRQHandler
B ACE_PC1_Flag1_IRQHandler
PUBWEAK ACE_PC1_Flag2_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PC1_Flag2_IRQHandler
B ACE_PC1_Flag2_IRQHandler
PUBWEAK ACE_PC1_Flag3_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PC1_Flag3_IRQHandler
B ACE_PC1_Flag3_IRQHandler
PUBWEAK ACE_PC2_Flag0_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PC2_Flag0_IRQHandler
B ACE_PC2_Flag0_IRQHandler
PUBWEAK ACE_PC2_Flag1_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PC2_Flag1_IRQHandler
B ACE_PC2_Flag1_IRQHandler
PUBWEAK ACE_PC2_Flag2_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PC2_Flag2_IRQHandler
B ACE_PC2_Flag2_IRQHandler
PUBWEAK ACE_PC2_Flag3_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PC2_Flag3_IRQHandler
B ACE_PC2_Flag3_IRQHandler
PUBWEAK ACE_ADC0_DataValid_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_ADC0_DataValid_IRQHandler
B ACE_ADC0_DataValid_IRQHandler
PUBWEAK ACE_ADC1_DataValid_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_ADC1_DataValid_IRQHandler
B ACE_ADC1_DataValid_IRQHandler
PUBWEAK ACE_ADC2_DataValid_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_ADC2_DataValid_IRQHandler
B ACE_ADC2_DataValid_IRQHandler
PUBWEAK ACE_ADC0_CalDone_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_ADC0_CalDone_IRQHandler
B ACE_ADC0_CalDone_IRQHandler
PUBWEAK ACE_ADC1_CalDone_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_ADC1_CalDone_IRQHandler
B ACE_ADC1_CalDone_IRQHandler
PUBWEAK ACE_ADC2_CalDone_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_ADC2_CalDone_IRQHandler
B ACE_ADC2_CalDone_IRQHandler
PUBWEAK ACE_ADC0_CalStart_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_ADC0_CalStart_IRQHandler
B ACE_ADC0_CalStart_IRQHandler
PUBWEAK ACE_ADC1_CalStart_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_ADC1_CalStart_IRQHandler
B ACE_ADC1_CalStart_IRQHandler
PUBWEAK ACE_ADC2_CalStart_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_ADC2_CalStart_IRQHandler
B ACE_ADC2_CalStart_IRQHandler
PUBWEAK ACE_Comp0_Fall_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_Comp0_Fall_IRQHandler
B ACE_Comp0_Fall_IRQHandler
PUBWEAK ACE_Comp1_Fall_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_Comp1_Fall_IRQHandler
B ACE_Comp1_Fall_IRQHandler
PUBWEAK ACE_Comp2_Fall_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_Comp2_Fall_IRQHandler
B ACE_Comp2_Fall_IRQHandler
PUBWEAK ACE_Comp3_Fall_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_Comp3_Fall_IRQHandler
B ACE_Comp3_Fall_IRQHandler
PUBWEAK ACE_Comp4_Fall_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_Comp4_Fall_IRQHandler
B ACE_Comp4_Fall_IRQHandler
PUBWEAK ACE_Comp5_Fall_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_Comp5_Fall_IRQHandler
B ACE_Comp5_Fall_IRQHandler
PUBWEAK ACE_Comp6_Fall_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_Comp6_Fall_IRQHandler
B ACE_Comp6_Fall_IRQHandler
PUBWEAK ACE_Comp7_Fall_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_Comp7_Fall_IRQHandler
B ACE_Comp7_Fall_IRQHandler
PUBWEAK ACE_Comp8_Fall_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_Comp8_Fall_IRQHandler
B ACE_Comp8_Fall_IRQHandler
PUBWEAK ACE_Comp9_Fall_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_Comp9_Fall_IRQHandler
B ACE_Comp9_Fall_IRQHandler
PUBWEAK ACE_Comp10_Fall_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_Comp10_Fall_IRQHandler
B ACE_Comp10_Fall_IRQHandler
PUBWEAK ACE_Comp11_Fall_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_Comp11_Fall_IRQHandler
B ACE_Comp11_Fall_IRQHandler
PUBWEAK ACE_Comp0_Rise_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_Comp0_Rise_IRQHandler
B ACE_Comp0_Rise_IRQHandler
PUBWEAK ACE_Comp1_Rise_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_Comp1_Rise_IRQHandler
B ACE_Comp1_Rise_IRQHandler
PUBWEAK ACE_Comp2_Rise_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_Comp2_Rise_IRQHandler
B ACE_Comp2_Rise_IRQHandler
PUBWEAK ACE_Comp3_Rise_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_Comp3_Rise_IRQHandler
B ACE_Comp3_Rise_IRQHandler
PUBWEAK ACE_Comp4_Rise_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_Comp4_Rise_IRQHandler
B ACE_Comp4_Rise_IRQHandler
PUBWEAK ACE_Comp5_Rise_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_Comp5_Rise_IRQHandler
B ACE_Comp5_Rise_IRQHandler
PUBWEAK ACE_Comp6_Rise_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_Comp6_Rise_IRQHandler
B ACE_Comp6_Rise_IRQHandler
PUBWEAK ACE_Comp7_Rise_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_Comp7_Rise_IRQHandler
B ACE_Comp7_Rise_IRQHandler
PUBWEAK ACE_Comp8_Rise_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_Comp8_Rise_IRQHandler
B ACE_Comp8_Rise_IRQHandler
PUBWEAK ACE_Comp9_Rise_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_Comp9_Rise_IRQHandler
B ACE_Comp9_Rise_IRQHandler
PUBWEAK ACE_Comp10_Rise_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_Comp10_Rise_IRQHandler
B ACE_Comp10_Rise_IRQHandler
PUBWEAK ACE_Comp11_Rise_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_Comp11_Rise_IRQHandler
B ACE_Comp11_Rise_IRQHandler
PUBWEAK ACE_ADC0_FifoFull_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_ADC0_FifoFull_IRQHandler
B ACE_ADC0_FifoFull_IRQHandler
PUBWEAK ACE_ADC0_FifoAFull_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_ADC0_FifoAFull_IRQHandler
B ACE_ADC0_FifoAFull_IRQHandler
PUBWEAK ACE_ADC0_FifoEmpty_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_ADC0_FifoEmpty_IRQHandler
B ACE_ADC0_FifoEmpty_IRQHandler
PUBWEAK ACE_ADC1_FifoFull_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_ADC1_FifoFull_IRQHandler
B ACE_ADC1_FifoFull_IRQHandler
PUBWEAK ACE_ADC1_FifoAFull_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_ADC1_FifoAFull_IRQHandler
B ACE_ADC1_FifoAFull_IRQHandler
PUBWEAK ACE_ADC1_FifoEmpty_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_ADC1_FifoEmpty_IRQHandler
B ACE_ADC1_FifoEmpty_IRQHandler
PUBWEAK ACE_ADC2_FifoFull_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_ADC2_FifoFull_IRQHandler
B ACE_ADC2_FifoFull_IRQHandler
PUBWEAK ACE_ADC2_FifoAFull_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_ADC2_FifoAFull_IRQHandler
B ACE_ADC2_FifoAFull_IRQHandler
PUBWEAK ACE_ADC2_FifoEmpty_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_ADC2_FifoEmpty_IRQHandler
B ACE_ADC2_FifoEmpty_IRQHandler
PUBWEAK ACE_PPE_Flag0_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PPE_Flag0_IRQHandler
B ACE_PPE_Flag0_IRQHandler
PUBWEAK ACE_PPE_Flag1_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PPE_Flag1_IRQHandler
B ACE_PPE_Flag1_IRQHandler
PUBWEAK ACE_PPE_Flag2_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PPE_Flag2_IRQHandler
B ACE_PPE_Flag2_IRQHandler
PUBWEAK ACE_PPE_Flag3_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PPE_Flag3_IRQHandler
B ACE_PPE_Flag3_IRQHandler
PUBWEAK ACE_PPE_Flag4_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PPE_Flag4_IRQHandler
B ACE_PPE_Flag4_IRQHandler
PUBWEAK ACE_PPE_Flag5_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PPE_Flag5_IRQHandler
B ACE_PPE_Flag5_IRQHandler
PUBWEAK ACE_PPE_Flag6_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PPE_Flag6_IRQHandler
B ACE_PPE_Flag6_IRQHandler
PUBWEAK ACE_PPE_Flag7_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PPE_Flag7_IRQHandler
B ACE_PPE_Flag7_IRQHandler
PUBWEAK ACE_PPE_Flag8_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PPE_Flag8_IRQHandler
B ACE_PPE_Flag8_IRQHandler
PUBWEAK ACE_PPE_Flag9_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PPE_Flag9_IRQHandler
B ACE_PPE_Flag9_IRQHandler
PUBWEAK ACE_PPE_Flag10_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PPE_Flag10_IRQHandler
B ACE_PPE_Flag10_IRQHandler
PUBWEAK ACE_PPE_Flag11_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PPE_Flag11_IRQHandler
B ACE_PPE_Flag11_IRQHandler
PUBWEAK ACE_PPE_Flag12_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PPE_Flag12_IRQHandler
B ACE_PPE_Flag12_IRQHandler
PUBWEAK ACE_PPE_Flag13_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PPE_Flag13_IRQHandler
B ACE_PPE_Flag13_IRQHandler
PUBWEAK ACE_PPE_Flag14_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PPE_Flag14_IRQHandler
B ACE_PPE_Flag14_IRQHandler
PUBWEAK ACE_PPE_Flag15_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PPE_Flag15_IRQHandler
B ACE_PPE_Flag15_IRQHandler
PUBWEAK ACE_PPE_Flag16_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PPE_Flag16_IRQHandler
B ACE_PPE_Flag16_IRQHandler
PUBWEAK ACE_PPE_Flag17_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PPE_Flag17_IRQHandler
B ACE_PPE_Flag17_IRQHandler
PUBWEAK ACE_PPE_Flag18_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PPE_Flag18_IRQHandler
B ACE_PPE_Flag18_IRQHandler
PUBWEAK ACE_PPE_Flag19_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PPE_Flag19_IRQHandler
B ACE_PPE_Flag19_IRQHandler
PUBWEAK ACE_PPE_Flag20_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PPE_Flag20_IRQHandler
B ACE_PPE_Flag20_IRQHandler
PUBWEAK ACE_PPE_Flag21_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PPE_Flag21_IRQHandler
B ACE_PPE_Flag21_IRQHandler
PUBWEAK ACE_PPE_Flag22_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PPE_Flag22_IRQHandler
B ACE_PPE_Flag22_IRQHandler
PUBWEAK ACE_PPE_Flag23_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PPE_Flag23_IRQHandler
B ACE_PPE_Flag23_IRQHandler
PUBWEAK ACE_PPE_Flag24_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PPE_Flag24_IRQHandler
B ACE_PPE_Flag24_IRQHandler
PUBWEAK ACE_PPE_Flag25_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PPE_Flag25_IRQHandler
B ACE_PPE_Flag25_IRQHandler
PUBWEAK ACE_PPE_Flag26_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PPE_Flag26_IRQHandler
B ACE_PPE_Flag26_IRQHandler
PUBWEAK ACE_PPE_Flag27_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PPE_Flag27_IRQHandler
B ACE_PPE_Flag27_IRQHandler
PUBWEAK ACE_PPE_Flag28_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PPE_Flag28_IRQHandler
B ACE_PPE_Flag28_IRQHandler
PUBWEAK ACE_PPE_Flag29_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PPE_Flag29_IRQHandler
B ACE_PPE_Flag29_IRQHandler
PUBWEAK ACE_PPE_Flag30_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PPE_Flag30_IRQHandler
B ACE_PPE_Flag30_IRQHandler
PUBWEAK ACE_PPE_Flag31_IRQHandler
SECTION .text:CODE:REORDER(1)
ACE_PPE_Flag31_IRQHandler
B ACE_PPE_Flag31_IRQHandler
END

199
Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS/system_a2fxxxm3.c
Unescape Escape View File

@ -1,199 +0,0 @@
/*******************************************************************************
* (c) Copyright 2009 Actel Corporation. All rights reserved.
*
* SmartFusion A2FxxxM3 CMSIS system initialization.
*
* SVN $Revision: 2069 $
* SVN $Date: 2010-01-28 00:23:48 +0000 (Thu, 28 Jan 2010) $
*/
#include "a2fxxxm3.h"
#include "mss_assert.h"
/* System frequency (FCLK) coming out of reset is 25MHz. */
#define RESET_SYSCLCK_FREQ 25000000uL
/*
* SmartFusion Microcontroller Subsystem FLCK frequency.
* The value of SMARTFUSION_FCLK_FREQ is used to report the system's clock
* frequency in system's which either do not use the Actel System Boot or
* a version of the Actel System Boot older than 1.3.1. In eitehr of these cases
* SMARTFUSION_FCLK_FREQ should be defined in the projects settings to reflect
* the FCLK frequency selected in the Libero MSS configurator.
* Systems using the Actel System Boot version 1.3.1 or later do not require this
* define since the system's frequency is retrieved from eNVM spare pages where
* the MSS Configurator stored the frequency selected during hardware design/configuration.
*/
#ifdef SMARTFUSION_FCLK_FREQ
#define SMARTFUSION_FCLK_FREQ_DEFINED 1
#else
#define SMARTFUSION_FCLK_FREQ_DEFINED 0
#define SMARTFUSION_FCLK_FREQ RESET_SYSCLCK_FREQ
#endif
/* Divider values for APB0, APB1 and ACE clocks. */
#define RESET_PCLK0_DIV 4uL
#define RESET_PCLK1_DIV 4uL
#define RESET_ACE_DIV 4uL
#define RESET_FPGA_CLK_DIV 4uL
/* System register clock control mask and shift for PCLK dividers. */
#define PCLK_DIV_MASK 0x00000003uL
#define PCLK0_DIV_SHIFT 2uL
#define PCLK1_DIV_SHIFT 4uL
#define ACE_DIV_SHIFT 6uL
/* System register MSS_CCC_DIV_CR mask and shift for GLB (FPGA fabric clock). */
#define OBDIV_SHIFT 8uL
#define OBDIV_MASK 0x0000001FuL
#define OBDIVHALF_SHIFT 13uL
#define OBDIVHALF_MASK 0x00000001uL
/*
* Actel system boot version defines used to extract the system clock from eNVM
* spare pages.
* These defines allow detecting the presence of Actel system boot in eNVM spare
* pages and the version of that system boot executable and associated
* configuration data.
*/
#define SYSBOOT_KEY_ADDR (uint32_t *)0x6008081C
#define SYSBOOT_KEY_VALUE 0x4C544341uL
#define SYSBOOT_VERSION_ADDR (uint32_t *)0x60080840
#define SYSBOOT_1_3_FCLK_ADDR (uint32_t *)0x6008162C
#define SYSBOOT_2_x_FCLK_ADDR (uint32_t *)0x60081EAC
/*
* The system boot version is stored in the least significant 24 bits of a word.
* The FCLK is stored in eNVM from version 1.3.1 of the system boot. We expect
* that the major version number of the system boot version will change if the
* system boot configuration data layout needs to change.
*/
#define SYSBOOT_VERSION_MASK 0x00FFFFFFuL
#define MIN_SYSBOOT_VERSION 0x00010301uL
#define SYSBOOT_VERSION_2_X 0x00020000uL
#define MAX_SYSBOOT_VERSION 0x00030000uL
/* Standard CMSIS global variables. */
uint32_t SystemFrequency = SMARTFUSION_FCLK_FREQ; /*!< System Clock Frequency (Core Clock) */
uint32_t SystemCoreClock = SMARTFUSION_FCLK_FREQ; /*!< System Clock Frequency (Core Clock) */
/* SmartFusion specific clocks. */
uint32_t g_FrequencyPCLK0 = (SMARTFUSION_FCLK_FREQ / RESET_PCLK0_DIV); /*!< Clock frequency of APB bus 0. */
uint32_t g_FrequencyPCLK1 = (SMARTFUSION_FCLK_FREQ / RESET_PCLK1_DIV); /*!< Clock frequency of APB bus 1. */
uint32_t g_FrequencyACE = (SMARTFUSION_FCLK_FREQ / RESET_ACE_DIV); /*!< Clock frequency of Analog Compute Engine. */
uint32_t g_FrequencyFPGA = (SMARTFUSION_FCLK_FREQ / RESET_FPGA_CLK_DIV); /*!< Clock frequecny of FPGA fabric */
/* Local functions */
static uint32_t GetSystemClock( void );
/***************************************************************************//**
* See system_a2fm3fxxx.h for details.
*/
void SystemInit(void)
{
}
/***************************************************************************//**
*
*/
void SystemCoreClockUpdate (void)
{
uint32_t PclkDiv0;
uint32_t PclkDiv1;
uint32_t AceDiv;
uint32_t FabDiv;
const uint32_t pclk_div_lut[4] = { 1uL, 2uL, 4uL, 1uL };
/* Read PCLK dividers from system registers. Multiply the value read from
* system register by two to get actual divider value. */
PclkDiv0 = pclk_div_lut[((SYSREG->MSS_CLK_CR >> PCLK0_DIV_SHIFT) & PCLK_DIV_MASK)];
PclkDiv1 = pclk_div_lut[((SYSREG->MSS_CLK_CR >> PCLK1_DIV_SHIFT) & PCLK_DIV_MASK)];
AceDiv = pclk_div_lut[((SYSREG->MSS_CLK_CR >> ACE_DIV_SHIFT) & PCLK_DIV_MASK)];
{
/* Compute the FPGA fabric frequency divider. */
uint32_t obdiv;
uint32_t obdivhalf;
obdiv = (SYSREG->MSS_CCC_DIV_CR >> OBDIV_SHIFT) & OBDIV_MASK;
obdivhalf = (SYSREG->MSS_CCC_DIV_CR >> OBDIVHALF_SHIFT) & OBDIVHALF_MASK;
FabDiv = obdiv + 1uL;
if ( obdivhalf != 0uL )
{
FabDiv = FabDiv * 2uL;
}
}
/* Retrieve FCLK from eNVM spare pages if Actel system boot programmed as part of the system. */
/* Read system clock from eNVM spare pages. */
SystemCoreClock = GetSystemClock();
g_FrequencyPCLK0 = SystemCoreClock / PclkDiv0;
g_FrequencyPCLK1 = SystemCoreClock / PclkDiv1;
g_FrequencyACE = SystemCoreClock / AceDiv;
g_FrequencyFPGA = SystemCoreClock / FabDiv;
/* Keep SystemFrequency as well as SystemCoreClock for legacy reasons. */
SystemFrequency = SystemCoreClock;
}
/***************************************************************************//**
* Retrieve the system clock frequency from eNVM spare page if available.
* Returns the frequency defined through SMARTFUSION_FCLK_FREQ if FCLK cannot be
* retrieved from eNVM spare pages.
* The FCLK frequency value selected in the MSS Configurator software tool is
* stored in eNVM spare pages as part of the Actel system boot configuration data.
*/
uint32_t GetSystemClock( void )
{
uint32_t fclk = 0uL;
uint32_t * p_sysboot_key = SYSBOOT_KEY_ADDR;
if ( SYSBOOT_KEY_VALUE == *p_sysboot_key )
{
/* Actel system boot programmed, check if it has the FCLK value stored. */
uint32_t *p_sysboot_version = SYSBOOT_VERSION_ADDR;
uint32_t sysboot_version = *p_sysboot_version;
sysboot_version &= SYSBOOT_VERSION_MASK;
if ( sysboot_version >= MIN_SYSBOOT_VERSION )
{
/* Handle change of eNVM location of FCLK between 1.3.x and 2.x.x versions of the system boot. */
if ( sysboot_version < SYSBOOT_VERSION_2_X )
{
/* Read FCLK value from MSS configurator generated configuration
* data stored in eNVM spare pages as part of system boot version 1.3.x
* configuration tables. */
uint32_t *p_fclk = SYSBOOT_1_3_FCLK_ADDR;
fclk = *p_fclk;
}
else if ( sysboot_version < MAX_SYSBOOT_VERSION )
{
/* Read FCLK value from MSS configurator generated configuration
* data stored in eNVM spare pages as part of system boot version 2.x.x
* configuration tables. */
uint32_t *p_fclk = SYSBOOT_2_x_FCLK_ADDR;
fclk = *p_fclk;
}
else
{
fclk = 0uL;
}
}
}
if ( 0uL == fclk )
{
/*
* Could not retrieve FCLK from system boot configuration data. Fall back
* to using SMARTFUSION_FCLK_FREQ which must then be defined as part of
* project settings.
*/
ASSERT( SMARTFUSION_FCLK_FREQ_DEFINED );
fclk = SMARTFUSION_FCLK_FREQ;
}
return fclk;
}

49
Demo/CORTEX_A2F200_IAR_and_Keil/MicroSemi_Code/CMSIS/system_a2fxxxm3.h
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@ -1,49 +0,0 @@
/*******************************************************************************
* (c) Copyright 2009 Actel Corporation. All rights reserved.
*
* SmartFusion A2FxxxM3 CMSIS system initialization.
*
* SVN $Revision: 2064 $
* SVN $Date: 2010-01-27 15:05:58 +0000 (Wed, 27 Jan 2010) $
*/
#ifndef __SYSTEM_A2FM3FXX_H__
#define __SYSTEM_A2FM3FXX_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Standard CMSIS global variables. */
extern uint32_t SystemFrequency; /*!< System Clock Frequency (Core Clock) */
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/* SmartFusion specific clocks. */
extern uint32_t g_FrequencyPCLK0; /*!< Clock frequency of APB bus 0. */
extern uint32_t g_FrequencyPCLK1; /*!< Clock frequency of APB bus 1. */
extern uint32_t g_FrequencyACE; /*!< Clock frequency of Analog Compute Engine. */
extern uint32_t g_FrequencyFPGA; /*!< Clock frequecny of FPGA fabric */
/***************************************************************************//**
* The SystemInit() is a standard CMSIS function called during system startup.
* It is meant to perform low level hardware setup such as configuring PLLs. In
* the case of SmartFusion these hardware setup operations are performed by the
* chip boot which executed before the application started. Therefore this
* function does not need to perform any hardware setup.
*/
void SystemInit(void);
/***************************************************************************//**
* The SystemCoreClockUpdate() is a standard CMSIS function which can be called
* by the application in order to ensure that the SystemCoreClock global
* variable contains the up to date Cortex-M3 core frequency. Calling this
* function also updates the global variables containing the frequencies of the
* APB busses connecting the peripherals and the ACE frequency.
*/
void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif
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