Updated ESP32 port-layer to ESP-IDF `v4.4.2` (#572)
* Xtensa_ESP32: Added esp-idf v4.4.2 specific changes * Xtensa_ESP32: Updated SPDX license identifierspull/575/head^2
Laukik Hase
2 years ago
committed by
GitHub
parent
195a351ec7
commit
963abe6c48
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/*
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* SPDX-FileCopyrightText: 2022 Amazon.com, Inc. or its affiliates
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*
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* SPDX-License-Identifier: MIT
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*
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* SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
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*/
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/*
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* FreeRTOS Kernel V10.4.3
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* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software. If you wish to use our Amazon
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* FreeRTOS name, please do so in a fair use way that does not cause confusion.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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* 1 tab == 4 spaces!
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*/
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#ifndef FREERTOS_CONFIG_XTENSA_H
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#define FREERTOS_CONFIG_XTENSA_H
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#include "sdkconfig.h"
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/* enable use of optimized task selection by the scheduler */
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#if defined (CONFIG_FREERTOS_OPTIMIZED_SCHEDULER) && !defined(configUSE_PORT_OPTIMISED_TASK_SELECTION)
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#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
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#endif
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#define XT_USE_THREAD_SAFE_CLIB 0
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#undef XT_USE_SWPRI
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#if CONFIG_FREERTOS_CORETIMER_0
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#define XT_TIMER_INDEX 0
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#elif CONFIG_FREERTOS_CORETIMER_1
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#define XT_TIMER_INDEX 1
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#endif
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#ifndef __ASSEMBLER__
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/**
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* This function is defined to provide a deprecation warning whenever
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* XT_CLOCK_FREQ macro is used.
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* Update the code to use esp_clk_cpu_freq function instead.
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* @return current CPU clock frequency, in Hz
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*/
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int xt_clock_freq(void) __attribute__((deprecated));
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#define XT_CLOCK_FREQ (xt_clock_freq())
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#endif // __ASSEMBLER__
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/* Required for configuration-dependent settings */
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#include <xtensa_config.h>
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/* configASSERT behaviour */
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#ifndef __ASSEMBLER__
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#include <assert.h>
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#include "esp_rom_sys.h"
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/rom/ets_sys.h" // will be removed in idf v5.0
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/ets_sys.h"
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#elif CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/rom/ets_sys.h"
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#endif
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#endif // __ASSEMBLER__
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// If CONFIG_FREERTOS_ASSERT_DISABLE is set then configASSERT is defined empty later in FreeRTOS.h and the macro
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// configASSERT_DEFINED remains unset (meaning some warnings are avoided)
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#ifdef configASSERT
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#undef configASSERT
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#if defined(CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE)
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#define configASSERT(a) if (unlikely(!(a))) { \
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esp_rom_printf("%s:%d (%s)- assert failed!\n", __FILE__, __LINE__, \
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__FUNCTION__); \
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}
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#elif defined(CONFIG_FREERTOS_ASSERT_FAIL_ABORT)
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#define configASSERT(a) assert(a)
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#endif
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#endif
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#if CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION
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#define UNTESTED_FUNCTION() { esp_rom_printf("Untested FreeRTOS function %s\r\n", __FUNCTION__); configASSERT(false); } while(0)
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#else
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#define UNTESTED_FUNCTION()
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#endif
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#define configXT_BOARD 1 /* Board mode */
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#define configXT_SIMULATOR 0
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/* The maximum interrupt priority from which FreeRTOS.org API functions can
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be called. Only API functions that end in ...FromISR() can be used within
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interrupts. */
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#define configMAX_SYSCALL_INTERRUPT_PRIORITY XCHAL_EXCM_LEVEL
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/* Stack alignment, architecture specifc. Must be a power of two. */
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#define configSTACK_ALIGNMENT 16
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/* The Xtensa port uses a separate interrupt stack. Adjust the stack size
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* to suit the needs of your specific application.
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* Size needs to be aligned to the stack increment, since the location of
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* the stack for the 2nd CPU will be calculated using configISR_STACK_SIZE.
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*/
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#ifndef configISR_STACK_SIZE
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#define configISR_STACK_SIZE ((CONFIG_FREERTOS_ISR_STACKSIZE + configSTACK_ALIGNMENT - 1) & (~(configSTACK_ALIGNMENT - 1)))
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#endif
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#ifndef __ASSEMBLER__
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#if CONFIG_APPTRACE_SV_ENABLE
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extern uint32_t port_switch_flag[];
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#define os_task_switch_is_pended(_cpu_) (port_switch_flag[_cpu_])
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#else
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#define os_task_switch_is_pended(_cpu_) (false)
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#endif
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#endif
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#endif // FREERTOS_CONFIG_XTENSA_H
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@ -0,0 +1,20 @@
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/*
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* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Set up the SysTick interrupt
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*/
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void vPortSetupTimer(void);
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#ifdef __cplusplus
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}
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#endif
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@ -0,0 +1,159 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <string.h>
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#include "FreeRTOS.h"
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#include "task.h"
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#include "portmacro.h"
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#include "esp_system.h"
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#include "esp_heap_caps_init.h"
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#include "esp_int_wdt.h"
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#include "esp_task_wdt.h"
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#include "esp_task.h"
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#include "esp_private/crosscore_int.h"
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#include "esp_private/startup_internal.h" /* Required by g_spiram_ok. [refactor-todo] for g_spiram_ok */
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#include "esp_log.h"
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#include "soc/soc_memory_types.h"
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#include "soc/dport_access.h"
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#include "sdkconfig.h"
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#include "esp_freertos_hooks.h"
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/spiram.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/spiram.h"
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#elif CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/spiram.h"
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#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
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// SPIRAM is not supported on ESP32-C3
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#endif
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#if CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL
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static const char* TAG = "cpu_start";
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#endif
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/* Architecture-agnostic parts of the FreeRTOS ESP-IDF port layer can go here.
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*
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* The actual call flow will be to call esp_startup_start_app() in <ARCH>/port.c,
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* which will then call esp_startup_start_app_common()
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*/
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// Duplicate of inaccessible xSchedulerRunning; needed at startup to avoid counting nesting
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volatile unsigned port_xSchedulerRunning[portNUM_PROCESSORS] = {0};
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// For now, running FreeRTOS on one core and a bare metal on the other (or other OSes)
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// is not supported. For now CONFIG_FREERTOS_UNICORE and CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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// should mirror each other's values.
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//
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// And since this should be true, we can just check for CONFIG_FREERTOS_UNICORE.
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#if CONFIG_FREERTOS_UNICORE != CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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#error "FreeRTOS and system configuration mismatch regarding the use of multiple cores."
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#endif
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static void main_task(void* args);
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#ifdef CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
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void esp_gdbstub_init(void);
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#endif // CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
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extern void app_main(void);
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void esp_startup_start_app_common(void)
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{
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#if CONFIG_ESP_INT_WDT
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esp_int_wdt_init();
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//Initialize the interrupt watch dog for CPU0.
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esp_int_wdt_cpu_init();
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#endif
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esp_crosscore_int_init();
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#ifdef CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
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esp_gdbstub_init();
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#endif // CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
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portBASE_TYPE res = xTaskCreatePinnedToCore(&main_task, "main",
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ESP_TASK_MAIN_STACK, NULL,
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ESP_TASK_MAIN_PRIO, NULL, ESP_TASK_MAIN_CORE);
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assert(res == pdTRUE);
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(void)res;
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}
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#if !CONFIG_FREERTOS_UNICORE
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static volatile bool s_other_cpu_startup_done = false;
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static bool other_cpu_startup_idle_hook_cb(void)
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{
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s_other_cpu_startup_done = true;
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return true;
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}
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#endif
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static void main_task(void* args)
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{
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#if !CONFIG_FREERTOS_UNICORE
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// Wait for FreeRTOS initialization to finish on other core, before replacing its startup stack
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esp_register_freertos_idle_hook_for_cpu(other_cpu_startup_idle_hook_cb, !xPortGetCoreID());
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while (!s_other_cpu_startup_done) {
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;
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}
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esp_deregister_freertos_idle_hook_for_cpu(other_cpu_startup_idle_hook_cb, !xPortGetCoreID());
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#endif
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// [refactor-todo] check if there is a way to move the following block to esp_system startup
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heap_caps_enable_nonos_stack_heaps();
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// Now we have startup stack RAM available for heap, enable any DMA pool memory
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#if CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL
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if (g_spiram_ok) {
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esp_err_t r = esp_spiram_reserve_dma_pool(CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL);
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if (r != ESP_OK) {
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ESP_EARLY_LOGE(TAG, "Could not reserve internal/DMA pool (error 0x%x)", r);
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abort();
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}
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}
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#endif
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//Initialize task wdt if configured to do so
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#ifdef CONFIG_ESP_TASK_WDT_PANIC
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ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_ESP_TASK_WDT_TIMEOUT_S, true));
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#elif CONFIG_ESP_TASK_WDT
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ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_ESP_TASK_WDT_TIMEOUT_S, false));
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#endif
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//Add IDLE 0 to task wdt
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#ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
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TaskHandle_t idle_0 = xTaskGetIdleTaskHandleForCPU(0);
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if(idle_0 != NULL){
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ESP_ERROR_CHECK(esp_task_wdt_add(idle_0));
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}
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#endif
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//Add IDLE 1 to task wdt
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#ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1
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TaskHandle_t idle_1 = xTaskGetIdleTaskHandleForCPU(1);
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if(idle_1 != NULL){
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ESP_ERROR_CHECK(esp_task_wdt_add(idle_1));
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}
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#endif
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app_main();
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vTaskDelete(NULL);
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}
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// -------------------- Heap Related -----------------------
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bool xPortCheckValidTCBMem(const void *ptr)
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{
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return esp_ptr_internal(ptr) && esp_ptr_byte_accessible(ptr);
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}
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bool xPortcheckValidStackMem(const void *ptr)
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{
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#ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
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return esp_ptr_byte_accessible(ptr);
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#else
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return esp_ptr_internal(ptr) && esp_ptr_byte_accessible(ptr);
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#endif
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}
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@ -0,0 +1,174 @@
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/*
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* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdlib.h>
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#include <string.h>
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#include "soc/cpu.h"
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#include "FreeRTOS.h"
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#include "task.h"
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#include "esp_intr_alloc.h"
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#include "esp_err.h"
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#include "esp_log.h"
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#include "sdkconfig.h"
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#ifdef CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER
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#include "soc/periph_defs.h"
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#include "soc/system_reg.h"
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#include "hal/systimer_hal.h"
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#include "hal/systimer_ll.h"
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#endif
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#ifdef CONFIG_PM_TRACE
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#include "esp_private/pm_trace.h"
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#endif //CONFIG_PM_TRACE
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BaseType_t xPortSysTickHandler(void);
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#ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
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extern void _frxt_tick_timer_init(void);
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extern void _xt_tick_divisor_init(void);
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#ifdef CONFIG_FREERTOS_CORETIMER_0
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#define SYSTICK_INTR_ID (ETS_INTERNAL_TIMER0_INTR_SOURCE+ETS_INTERNAL_INTR_SOURCE_OFF)
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#endif
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#ifdef CONFIG_FREERTOS_CORETIMER_1
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#define SYSTICK_INTR_ID (ETS_INTERNAL_TIMER1_INTR_SOURCE+ETS_INTERNAL_INTR_SOURCE_OFF)
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#endif
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/**
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* @brief Initialize CCONT timer to generate the tick interrupt
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*
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*/
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void vPortSetupTimer(void)
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{
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/* Init the tick divisor value */
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_xt_tick_divisor_init();
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_frxt_tick_timer_init();
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}
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#elif CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER
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_Static_assert(SOC_CPU_CORES_NUM <= SOC_SYSTIMER_ALARM_NUM - 1, "the number of cores must match the number of core alarms in SYSTIMER");
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void SysTickIsrHandler(void *arg);
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static uint32_t s_handled_systicks[portNUM_PROCESSORS] = { 0 };
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#define SYSTICK_INTR_ID (ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE)
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/**
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* @brief Set up the systimer peripheral to generate the tick interrupt
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*
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* Both timer alarms are configured in periodic mode.
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* It is done at the same time so SysTicks for both CPUs occur at the same time or very close.
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* Shifts a time of triggering interrupts for core 0 and core 1.
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*/
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void vPortSetupTimer(void)
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{
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unsigned cpuid = xPortGetCoreID();
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#ifdef CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL3
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const unsigned level = ESP_INTR_FLAG_LEVEL3;
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#else
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const unsigned level = ESP_INTR_FLAG_LEVEL1;
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#endif
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/* Systimer HAL layer object */
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static systimer_hal_context_t systimer_hal;
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/* set system timer interrupt vector */
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ESP_ERROR_CHECK(esp_intr_alloc(ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE + cpuid, ESP_INTR_FLAG_IRAM | level, SysTickIsrHandler, &systimer_hal, NULL));
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if (cpuid == 0) {
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systimer_hal_init(&systimer_hal);
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systimer_ll_set_counter_value(systimer_hal.dev, SYSTIMER_LL_COUNTER_OS_TICK, 0);
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systimer_ll_apply_counter_value(systimer_hal.dev, SYSTIMER_LL_COUNTER_OS_TICK);
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for (cpuid = 0; cpuid < SOC_CPU_CORES_NUM; cpuid++) {
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systimer_hal_counter_can_stall_by_cpu(&systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK, cpuid, false);
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}
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for (cpuid = 0; cpuid < portNUM_PROCESSORS; ++cpuid) {
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uint32_t alarm_id = SYSTIMER_LL_ALARM_OS_TICK_CORE0 + cpuid;
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/* configure the timer */
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systimer_hal_connect_alarm_counter(&systimer_hal, alarm_id, SYSTIMER_LL_COUNTER_OS_TICK);
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systimer_hal_set_alarm_period(&systimer_hal, alarm_id, 1000000UL / CONFIG_FREERTOS_HZ);
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systimer_hal_select_alarm_mode(&systimer_hal, alarm_id, SYSTIMER_ALARM_MODE_PERIOD);
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systimer_hal_counter_can_stall_by_cpu(&systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK, cpuid, true);
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if (cpuid == 0) {
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systimer_hal_enable_alarm_int(&systimer_hal, alarm_id);
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systimer_hal_enable_counter(&systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK);
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#ifndef CONFIG_FREERTOS_UNICORE
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// SysTick of core 0 and core 1 are shifted by half of period
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systimer_hal_counter_value_advance(&systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK, 1000000UL / CONFIG_FREERTOS_HZ / 2);
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#endif
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}
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}
|
||||
} else {
|
||||
uint32_t alarm_id = SYSTIMER_LL_ALARM_OS_TICK_CORE0 + cpuid;
|
||||
systimer_hal_enable_alarm_int(&systimer_hal, alarm_id);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Systimer interrupt handler.
|
||||
*
|
||||
* The Systimer interrupt for SysTick works in periodic mode no need to calc the next alarm.
|
||||
* If a timer interrupt is ever serviced more than one tick late, it is necessary to process multiple ticks.
|
||||
*/
|
||||
IRAM_ATTR void SysTickIsrHandler(void *arg)
|
||||
{
|
||||
uint32_t cpuid = xPortGetCoreID();
|
||||
systimer_hal_context_t *systimer_hal = (systimer_hal_context_t *)arg;
|
||||
#ifdef CONFIG_PM_TRACE
|
||||
ESP_PM_TRACE_ENTER(TICK, cpuid);
|
||||
#endif
|
||||
|
||||
uint32_t alarm_id = SYSTIMER_LL_ALARM_OS_TICK_CORE0 + cpuid;
|
||||
do {
|
||||
systimer_ll_clear_alarm_int(systimer_hal->dev, alarm_id);
|
||||
|
||||
uint32_t diff = systimer_hal_get_counter_value(systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK) / systimer_ll_get_alarm_period(systimer_hal->dev, alarm_id) - s_handled_systicks[cpuid];
|
||||
if (diff > 0) {
|
||||
if (s_handled_systicks[cpuid] == 0) {
|
||||
s_handled_systicks[cpuid] = diff;
|
||||
diff = 1;
|
||||
} else {
|
||||
s_handled_systicks[cpuid] += diff;
|
||||
}
|
||||
|
||||
do {
|
||||
xPortSysTickHandler();
|
||||
} while (--diff);
|
||||
}
|
||||
} while (systimer_ll_is_alarm_int_fired(systimer_hal->dev, alarm_id));
|
||||
|
||||
#ifdef CONFIG_PM_TRACE
|
||||
ESP_PM_TRACE_EXIT(TICK, cpuid);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif // CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
|
||||
|
||||
/**
|
||||
* @brief Handler of SysTick
|
||||
*
|
||||
* The function is called from:
|
||||
* - _frxt_timer_int for xtensa with CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
|
||||
* - SysTickIsrHandler for xtensa with CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER
|
||||
* - SysTickIsrHandler for riscv
|
||||
*/
|
||||
BaseType_t xPortSysTickHandler(void)
|
||||
{
|
||||
portbenchmarkIntLatency();
|
||||
traceISR_ENTER(SYSTICK_INTR_ID);
|
||||
BaseType_t ret = xTaskIncrementTick();
|
||||
if(ret != pdFALSE) {
|
||||
portYIELD_FROM_ISR();
|
||||
} else {
|
||||
traceISR_EXIT();
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
@ -1,190 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*/
|
||||
/*
|
||||
* Copyright (c) 2015-2019 Cadence Design Systems, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sublicense, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* Xtensa-specific interrupt and exception functions for RTOS ports.
|
||||
* Also see xtensa_intr_asm.S.
|
||||
******************************************************************************/
|
||||
|
||||
#include <stdlib.h>
|
||||
|
||||
#include <xtensa/config/core.h>
|
||||
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/xtensa_api.h"
|
||||
#include "freertos/portable.h"
|
||||
#include "esp_idf_version.h"
|
||||
|
||||
#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
|
||||
#include "rom/ets_sys.h"
|
||||
#else
|
||||
#if CONFIG_IDF_TARGET_ESP32S2
|
||||
#include "esp32s2/rom/ets_sys.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32
|
||||
#include "esp32/rom/ets_sys.h"
|
||||
#endif
|
||||
#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */
|
||||
|
||||
#if XCHAL_HAVE_EXCEPTIONS
|
||||
|
||||
/* Handler table is in xtensa_intr_asm.S */
|
||||
|
||||
extern xt_exc_handler _xt_exception_table[ XCHAL_EXCCAUSE_NUM * portNUM_PROCESSORS ];
|
||||
|
||||
|
||||
/*
|
||||
* Default handler for unhandled exceptions.
|
||||
* CHANGED: We do this in panic.c now
|
||||
*/
|
||||
|
||||
/*void xt_unhandled_exception(XtExcFrame *frame) */
|
||||
/*{ */
|
||||
/*exit(-1); */
|
||||
/*} */
|
||||
extern void xt_unhandled_exception( XtExcFrame * frame );
|
||||
|
||||
|
||||
/*
|
||||
* This function registers a handler for the specified exception.
|
||||
* The function returns the address of the previous handler.
|
||||
* On error, it returns 0.
|
||||
*/
|
||||
xt_exc_handler xt_set_exception_handler( int n,
|
||||
xt_exc_handler f )
|
||||
{
|
||||
xt_exc_handler old;
|
||||
|
||||
if( ( n < 0 ) || ( n >= XCHAL_EXCCAUSE_NUM ) )
|
||||
{
|
||||
return 0; /* invalid exception number */
|
||||
}
|
||||
|
||||
/* Convert exception number to _xt_exception_table name */
|
||||
n = n * portNUM_PROCESSORS + xPortGetCoreID();
|
||||
old = _xt_exception_table[ n ];
|
||||
|
||||
if( f )
|
||||
{
|
||||
_xt_exception_table[ n ] = f;
|
||||
}
|
||||
else
|
||||
{
|
||||
_xt_exception_table[ n ] = &xt_unhandled_exception;
|
||||
}
|
||||
|
||||
return( ( old == &xt_unhandled_exception ) ? 0 : old );
|
||||
}
|
||||
|
||||
#endif /* if XCHAL_HAVE_EXCEPTIONS */
|
||||
|
||||
#if XCHAL_HAVE_INTERRUPTS
|
||||
|
||||
/* Handler table is in xtensa_intr_asm.S */
|
||||
|
||||
typedef struct xt_handler_table_entry
|
||||
{
|
||||
void * handler;
|
||||
void * arg;
|
||||
} xt_handler_table_entry;
|
||||
|
||||
extern xt_handler_table_entry _xt_interrupt_table[ XCHAL_NUM_INTERRUPTS * portNUM_PROCESSORS ];
|
||||
|
||||
|
||||
/*
|
||||
* Default handler for unhandled interrupts.
|
||||
*/
|
||||
void xt_unhandled_interrupt( void * arg )
|
||||
{
|
||||
ets_printf( "Unhandled interrupt %d on cpu %d!\n", ( int ) arg, xPortGetCoreID() );
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* This function registers a handler for the specified interrupt. The "arg"
|
||||
* parameter specifies the argument to be passed to the handler when it is
|
||||
* invoked. The function returns the address of the previous handler.
|
||||
* On error, it returns 0.
|
||||
*/
|
||||
xt_handler xt_set_interrupt_handler( int n,
|
||||
xt_handler f,
|
||||
void * arg )
|
||||
{
|
||||
xt_handler_table_entry * entry;
|
||||
xt_handler old;
|
||||
|
||||
if( ( n < 0 ) || ( n >= XCHAL_NUM_INTERRUPTS ) )
|
||||
{
|
||||
return 0; /* invalid interrupt number */
|
||||
}
|
||||
|
||||
if( Xthal_intlevel[ n ] > XCHAL_EXCM_LEVEL )
|
||||
{
|
||||
return 0; /* priority level too high to safely handle in C */
|
||||
}
|
||||
|
||||
/* Convert exception number to _xt_exception_table name */
|
||||
n = n * portNUM_PROCESSORS + xPortGetCoreID();
|
||||
|
||||
entry = _xt_interrupt_table + n;
|
||||
old = entry->handler;
|
||||
|
||||
if( f )
|
||||
{
|
||||
entry->handler = f;
|
||||
entry->arg = arg;
|
||||
}
|
||||
else
|
||||
{
|
||||
entry->handler = &xt_unhandled_interrupt;
|
||||
entry->arg = ( void * ) n;
|
||||
}
|
||||
|
||||
return( ( old == &xt_unhandled_interrupt ) ? 0 : old );
|
||||
}
|
||||
|
||||
#if CONFIG_SYSVIEW_ENABLE
|
||||
void * xt_get_interrupt_handler_arg( int n )
|
||||
{
|
||||
xt_handler_table_entry * entry;
|
||||
|
||||
if( ( n < 0 ) || ( n >= XCHAL_NUM_INTERRUPTS ) )
|
||||
{
|
||||
return 0; /* invalid interrupt number */
|
||||
}
|
||||
|
||||
/* Convert exception number to _xt_exception_table name */
|
||||
n = n * portNUM_PROCESSORS + xPortGetCoreID();
|
||||
|
||||
entry = _xt_interrupt_table + n;
|
||||
return entry->arg;
|
||||
}
|
||||
#endif /* if CONFIG_SYSVIEW_ENABLE */
|
||||
|
||||
#endif /* XCHAL_HAVE_INTERRUPTS */
|
||||
@ -1,232 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*/
|
||||
/*
|
||||
* Copyright (c) 2015-2019 Cadence Design Systems, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sublicense, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
Xtensa interrupt handling data and assembly routines.
|
||||
Also see xtensa_intr.c and xtensa_vectors.S.
|
||||
******************************************************************************/
|
||||
|
||||
#include <xtensa/hal.h>
|
||||
#include <xtensa/config/core.h>
|
||||
|
||||
#include "xtensa_context.h"
|
||||
#include "FreeRTOSConfig.h"
|
||||
|
||||
#if XCHAL_HAVE_INTERRUPTS
|
||||
|
||||
/*
|
||||
-------------------------------------------------------------------------------
|
||||
INTENABLE virtualization information.
|
||||
-------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
#if XT_USE_SWPRI
|
||||
/* Warning - this is not multicore-compatible. */
|
||||
.data
|
||||
.global _xt_intdata
|
||||
.align 8
|
||||
_xt_intdata:
|
||||
.global _xt_intenable
|
||||
.type _xt_intenable,@object
|
||||
.size _xt_intenable,4
|
||||
.global _xt_vpri_mask
|
||||
.type _xt_vpri_mask,@object
|
||||
.size _xt_vpri_mask,4
|
||||
|
||||
_xt_intenable: .word 0 /* Virtual INTENABLE */
|
||||
_xt_vpri_mask: .word 0xFFFFFFFF /* Virtual priority mask */
|
||||
#endif
|
||||
|
||||
/*
|
||||
-------------------------------------------------------------------------------
|
||||
Table of C-callable interrupt handlers for each interrupt. Note that not all
|
||||
slots can be filled, because interrupts at level > EXCM_LEVEL will not be
|
||||
dispatched to a C handler by default.
|
||||
|
||||
Stored as:
|
||||
int 0 cpu 0
|
||||
int 0 cpu 1
|
||||
...
|
||||
int 0 cpu n
|
||||
int 1 cpu 0
|
||||
int 1 cpu 1
|
||||
etc
|
||||
-------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
.data
|
||||
.global _xt_interrupt_table
|
||||
.align 8
|
||||
|
||||
_xt_interrupt_table:
|
||||
|
||||
.set i, 0
|
||||
.rept XCHAL_NUM_INTERRUPTS*portNUM_PROCESSORS
|
||||
.word xt_unhandled_interrupt /* handler address */
|
||||
.word i /* handler arg (default: intnum) */
|
||||
.set i, i+1
|
||||
.endr
|
||||
|
||||
#endif /* XCHAL_HAVE_INTERRUPTS */
|
||||
|
||||
|
||||
#if XCHAL_HAVE_EXCEPTIONS
|
||||
|
||||
/*
|
||||
-------------------------------------------------------------------------------
|
||||
Table of C-callable exception handlers for each exception. Note that not all
|
||||
slots will be active, because some exceptions (e.g. coprocessor exceptions)
|
||||
are always handled by the OS and cannot be hooked by user handlers.
|
||||
|
||||
Stored as:
|
||||
exc 0 cpu 0
|
||||
exc 0 cpu 1
|
||||
...
|
||||
exc 0 cpu n
|
||||
exc 1 cpu 0
|
||||
exc 1 cpu 1
|
||||
etc
|
||||
-------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
.data
|
||||
.global _xt_exception_table
|
||||
.align 4
|
||||
|
||||
_xt_exception_table:
|
||||
.rept XCHAL_EXCCAUSE_NUM * portNUM_PROCESSORS
|
||||
.word xt_unhandled_exception /* handler address */
|
||||
.endr
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
-------------------------------------------------------------------------------
|
||||
unsigned int xt_ints_on ( unsigned int mask )
|
||||
|
||||
Enables a set of interrupts. Does not simply set INTENABLE directly, but
|
||||
computes it as a function of the current virtual priority if XT_USE_SWPRI is
|
||||
enabled.
|
||||
Can be called from interrupt handlers.
|
||||
-------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
.text
|
||||
.align 4
|
||||
.global xt_ints_on
|
||||
.type xt_ints_on,@function
|
||||
|
||||
xt_ints_on:
|
||||
|
||||
ENTRY0
|
||||
|
||||
#if XCHAL_HAVE_INTERRUPTS
|
||||
#if XT_USE_SWPRI
|
||||
movi a3, 0
|
||||
movi a4, _xt_intdata
|
||||
xsr a3, INTENABLE /* Disables all interrupts */
|
||||
rsync
|
||||
l32i a3, a4, 0 /* a3 = _xt_intenable */
|
||||
l32i a6, a4, 4 /* a6 = _xt_vpri_mask */
|
||||
or a5, a3, a2 /* a5 = _xt_intenable | mask */
|
||||
s32i a5, a4, 0 /* _xt_intenable |= mask */
|
||||
and a5, a5, a6 /* a5 = _xt_intenable & _xt_vpri_mask */
|
||||
wsr a5, INTENABLE /* Reenable interrupts */
|
||||
mov a2, a3 /* Previous mask */
|
||||
#else
|
||||
movi a3, 0
|
||||
xsr a3, INTENABLE /* Disables all interrupts */
|
||||
rsync
|
||||
or a2, a3, a2 /* set bits in mask */
|
||||
wsr a2, INTENABLE /* Re-enable ints */
|
||||
rsync
|
||||
mov a2, a3 /* return prev mask */
|
||||
#endif
|
||||
#else
|
||||
movi a2, 0 /* Return zero */
|
||||
#endif
|
||||
RET0
|
||||
|
||||
.size xt_ints_on, . - xt_ints_on
|
||||
|
||||
|
||||
/*
|
||||
-------------------------------------------------------------------------------
|
||||
unsigned int xt_ints_off ( unsigned int mask )
|
||||
|
||||
Disables a set of interrupts. Does not simply set INTENABLE directly,
|
||||
but computes it as a function of the current virtual priority if XT_USE_SWPRI is
|
||||
enabled.
|
||||
Can be called from interrupt handlers.
|
||||
-------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
.text
|
||||
.align 4
|
||||
.global xt_ints_off
|
||||
.type xt_ints_off,@function
|
||||
|
||||
xt_ints_off:
|
||||
|
||||
ENTRY0
|
||||
#if XCHAL_HAVE_INTERRUPTS
|
||||
#if XT_USE_SWPRI
|
||||
movi a3, 0
|
||||
movi a4, _xt_intdata
|
||||
xsr a3, INTENABLE /* Disables all interrupts */
|
||||
rsync
|
||||
l32i a3, a4, 0 /* a3 = _xt_intenable */
|
||||
l32i a6, a4, 4 /* a6 = _xt_vpri_mask */
|
||||
or a5, a3, a2 /* a5 = _xt_intenable | mask */
|
||||
xor a5, a5, a2 /* a5 = _xt_intenable & ~mask */
|
||||
s32i a5, a4, 0 /* _xt_intenable &= ~mask */
|
||||
and a5, a5, a6 /* a5 = _xt_intenable & _xt_vpri_mask */
|
||||
wsr a5, INTENABLE /* Reenable interrupts */
|
||||
mov a2, a3 /* Previous mask */
|
||||
#else
|
||||
movi a4, 0
|
||||
xsr a4, INTENABLE /* Disables all interrupts */
|
||||
rsync
|
||||
or a3, a4, a2 /* set bits in mask */
|
||||
xor a3, a3, a2 /* invert bits in mask set in mask, essentially clearing them */
|
||||
wsr a3, INTENABLE /* Re-enable ints */
|
||||
rsync
|
||||
mov a2, a4 /* return prev mask */
|
||||
#endif
|
||||
#else
|
||||
movi a2, 0 /* return zero */
|
||||
#endif
|
||||
RET0
|
||||
|
||||
.size xt_ints_off, . - xt_ints_off
|
||||
|
||||
|
||||
Loading…
Reference in New Issue