diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/Blinky_Demo/main_blinky.c new file mode 100644 index 000000000..0cb9fa988 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/Blinky_Demo/main_blinky.c @@ -0,0 +1,236 @@ +/* + FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky + * style project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select + * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY + * in main.c. This file implements the simply blinky style version. + * + * NOTE 2: This file only contains the source code that is specific to the + * basic demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware are defined in main.c. + ****************************************************************************** + * + * main_blinky() creates one queue, and two tasks. It then starts the + * scheduler. + * + * The Queue Send Task: + * The queue send task is implemented by the prvQueueSendTask() function in + * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly + * block for 200 milliseconds, before sending the value 100 to the queue that + * was created within main_blinky(). Once the value is sent, the task loops + * back around to block for another 200 milliseconds...and so on. + * + * The Queue Receive Task: + * The queue receive task is implemented by the prvQueueReceiveTask() function + * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly + * blocks on attempts to read data from the queue that was created within + * main_blinky(). When data is received, the task checks the value of the + * data, and if the value equals the expected 100, toggles an LED. The 'block + * time' parameter passed to the queue receive function specifies that the + * task should be held in the Blocked state indefinitely to wait for data to + * be available on the queue. The queue receive task will only leave the + * Blocked state when the queue send task writes to the queue. As the queue + * send task writes to the queue every 200 milliseconds, the queue receive + * task leaves the Blocked state every 200 milliseconds, and therefore toggles + * the LED every 200 milliseconds. + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Standard demo includes. */ +#include "partest.h" + +/* Priorities at which the tasks are created. */ +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The rate at which data is sent to the queue. The 200ms value is converted +to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( pdMS_TO_TICKS( 200 ) ) + +/* The number of items the queue can hold. This is 1 as the receive task +will remove items as they are added, meaning the send task should always find +the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) + +/* The LED toggled by the Rx task. */ +#define mainTASK_LED ( 0 ) + +/*-----------------------------------------------------------*/ + +/* + * Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in + * main.c. + */ +void main_blinky( void ); + +/* + * The tasks as described in the comments at the top of this file. + */ +static void prvQueueReceiveTask( void *pvParameters ); +static void prvQueueSendTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The queue used by both tasks. */ +static QueueHandle_t xQueue = NULL; + +/*-----------------------------------------------------------*/ + +void main_blinky( void ) +{ + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + NULL, /* The parameter passed to the task - not used in this case. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ + + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was either insufficient FreeRTOS heap memory available for the idle + and/or timer tasks to be created, or vTaskStartScheduler() was called from + User mode. See the memory management section on the FreeRTOS web site for + more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + mode from which main() is called is set in the C start up code and must be + a privileged mode (not user mode). */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvQueueSendTask( void *pvParameters ) +{ +TickType_t xNextWakeTime; +const unsigned long ulValueToSend = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Place this task in the blocked state until it is time to run again. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + toggle the LED. 0 is used as the block time so the sending operation + will not block - it shouldn't need to block as the queue should always + be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } +} +/*-----------------------------------------------------------*/ + +static void prvQueueReceiveTask( void *pvParameters ) +{ +unsigned long ulReceivedValue; +const unsigned long ulExpectedValue = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + for( ;; ) + { + /* Wait until something arrives in the queue - this task will block + indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + is it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == ulExpectedValue ) + { + vParTestToggleLED( mainTASK_LED ); + ulReceivedValue = 0U; + } + } +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/FreeRTOSConfig.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/FreeRTOSConfig.h new file mode 100644 index 000000000..a5aeeed9d --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/FreeRTOSConfig.h @@ -0,0 +1,169 @@ +/* + FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * http://www.freertos.org/a00110.html + *----------------------------------------------------------*/ + +/* The array used as the heap is declared by the application to allow the +__persistent keyword to be used. See http://www.freertos.org/a00111.html#heap_4 */ +#define configAPPLICATION_ALLOCATED_HEAP 1 + +#define configUSE_PREEMPTION 1 +#define configMAX_PRIORITIES ( 5 ) +#define configTICK_RATE_HZ ( 1000 ) /* In this non-real time simulated environment the tick frequency has to be at least a multiple of the Win32 tick frequency, and therefore very slow. */ +#define configTOTAL_HEAP_SIZE ( 5 * 1024 ) +#define configMAX_TASK_NAME_LEN ( 15 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_CO_ROUTINES 0 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 0 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_ALTERNATIVE_API 0 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0 +#define configENABLE_BACKWARD_COMPATIBILITY 0 + +#if __DATA_MODEL__ == __DATA_MODEL_SMALL__ + #define configMINIMAL_STACK_SIZE ( ( unsigned short ) 110 ) +#else + #define configMINIMAL_STACK_SIZE ( ( unsigned short ) 80 ) +#endif + +/* Hook function related definitions. */ +#define configUSE_TICK_HOOK 0 +#define configUSE_IDLE_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configCHECK_FOR_STACK_OVERFLOW 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 0 +#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 ) + +/* Event group related definitions. */ +#define configUSE_EVENT_GROUPS 0 + +/* Run time stats gathering definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. The IAR linker will remove unused functions +anyway, so any INCLUDE_ definition that doesn't have another dependency can be +left at 1 with no impact on the code size. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTimerGetTimerTaskHandle 1 +#define INCLUDE_xTaskGetIdleTaskHandle 1 +#define INCLUDE_xQueueGetMutexHolder 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 +#define INCLUDE_pcTaskGetTaskName 1 + +/* Not using stats, so no need to include the formatting functions. */ +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Assert call defined for debug builds. */ +#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } + +/* The MSP430X port uses a callback function to configure its tick interrupt. +This allows the application to choose the tick interrupt source. +configTICK_VECTOR must also be set in FreeRTOSConfig.h to the correct +interrupt vector for the chosen tick interrupt source. This implementation of +vApplicationSetupTimerInterrupt() generates the tick from timer A0, so in this +case configTICK__VECTOR is set to TIMER0_A0_VECTOR. */ +#define configTICK_VECTOR TIMER0_A0_VECTOR + +#endif /* FREERTOS_CONFIG_H */ + diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/LEDs.c b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/LEDs.c new file mode 100644 index 000000000..cab40defc --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/LEDs.c @@ -0,0 +1,115 @@ +/* + FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +/*----------------------------------------------------------- + * Simple IO routines to control the LEDs. + *-----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo includes. */ +#include "partest.h" + +/* TI includes. */ +#include "driverlib.h" + +/* Port/pin definitions. */ +#define partstNUM_LEDS 2 +const uint8_t ucPorts[ partstNUM_LEDS ] = { GPIO_PORT_P1, GPIO_PORT_P4 }; +const uint16_t usPins[ partstNUM_LEDS ] = { GPIO_PIN0, GPIO_PIN6 }; + +/*-----------------------------------------------------------*/ + +void vParTestSetLED( UBaseType_t uxLED, BaseType_t xValue ) +{ + if( uxLED < partstNUM_LEDS ) + { + if( xValue == pdFALSE ) + { + GPIO_setOutputLowOnPin( ucPorts[ uxLED ], usPins[ uxLED ] ); + } + else + { + GPIO_setOutputHighOnPin( ucPorts[ uxLED ], usPins[ uxLED ] ); + } + } +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ + if( uxLED < partstNUM_LEDS ) + { + GPIO_toggleOutputOnPin( ucPorts[ uxLED ], usPins[ uxLED ] ); + } +} + diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/RTOSDemo.ewd b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/RTOSDemo.ewd new file mode 100644 index 000000000..e52103baf --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/RTOSDemo.ewd @@ -0,0 +1,417 @@ + + + + 2 + + Debug + + MSP430 + + 1 + + C-SPY + 5 + + 27 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 430FET + 1 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + SIM430 + 1 + + 4 + 1 + 1 + + + + + + + + + + + $TOOLKIT_DIR$\plugins\lcd\lcd.ewplugin + 1 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/RTOSDemo.ewp b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/RTOSDemo.ewp new file mode 100644 index 000000000..435c766cb --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/RTOSDemo.ewp @@ -0,0 +1,1411 @@ + + + + 2 + + Debug + + MSP430 + + 1 + + General + 17 + + 33 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICC430 + 4 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + A430 + 5 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + XLINK + 4 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + XAR + 4 + + 0 + 1 + 1 + + + + + + + ULP430 + 1 + + 1 + 1 + 1 + + + + + + + + + BILINK + 0 + + + + + Blinky_Demo + + $PROJ_DIR$\Blinky_Demo\main_blinky.c + + + + driverlib + + MSP430FR5xx_6xx + + deprecated + + CCS + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\deprecated\CCS\msp430fr5xx_6xxgeneric.h + + + + IAR + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\deprecated\IAR\msp430fr5xx_6xxgeneric.h + + + + + inc + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\inc\hw_memmap.h + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\inc\hw_regaccess.h + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\inc\hw_types.h + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\inc\version.h + + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\adc12_b.c + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\adc12_b.h + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\aes256.c + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\aes256.h + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\comp_e.c + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\comp_e.h + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\crc.c + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\crc.h + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\crc32.c + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\crc32.h + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\cs.c + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\cs.h + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\dma.c + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\dma.h + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\driverlib.h + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\esi.c + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\esi.h + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\eusci_a_spi.c + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\eusci_a_spi.h + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\eusci_a_uart.c + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\eusci_a_uart.h + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\eusci_b_i2c.c + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\eusci_b_i2c.h + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\eusci_b_spi.c + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\eusci_b_spi.h + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\framctl.c + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\framctl.h + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\gpio.c + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\gpio.h + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\lcd_c.c + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\lcd_c.h + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\mpu.c + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\mpu.h + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\mpy32.c + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\mpy32.h + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\pmm.c + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\pmm.h + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\ram.c + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\ram.h + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\ref_a.c + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\ref_a.h + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\rtc_b.c + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\rtc_b.h + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\rtc_c.c + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\rtc_c.h + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\sfr.c + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\sfr.h + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\sysctl.c + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\sysctl.h + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\timer_a.c + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\timer_a.h + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\timer_b.c + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\timer_b.h + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\tlv.c + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\tlv.h + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\wdt_a.c + + + $PROJ_DIR$\driverlib\MSP430FR5xx_6xx\wdt_a.h + + + + + FreeRTOS_Source + + portable + + $PROJ_DIR$\..\..\Source\portable\MemMang\heap_4.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\MSP430X\port.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\MSP430X\portext.s43 + + + + $PROJ_DIR$\..\..\Source\event_groups.c + + + $PROJ_DIR$\..\..\Source\list.c + + + $PROJ_DIR$\..\..\Source\queue.c + + + $PROJ_DIR$\..\..\Source\tasks.c + + + $PROJ_DIR$\..\..\Source\timers.c + + + + $PROJ_DIR$\FRAMLogMode.c + + Debug + + + + $PROJ_DIR$\FRAMLogMode.h + + + $PROJ_DIR$\FreeRTOSConfig.h + + + $PROJ_DIR$\LEDs.c + + + $PROJ_DIR$\LiveTempMode.c + + + $PROJ_DIR$\LiveTempMode.h + + + $PROJ_DIR$\low_level_init_iar.c + + + $PROJ_DIR$\main.c + + + $PROJ_DIR$\main.h + + + + diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/RTOSDemo.eww b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/RTOSDemo.eww new file mode 100644 index 000000000..239a9381e --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/RTOSDemo.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\RTOSDemo.ewp + + + + + diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/adc12_b.c b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/adc12_b.c new file mode 100644 index 000000000..acf733833 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/adc12_b.c @@ -0,0 +1,290 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// adc12_b.c - Driver for the adc12_b Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup adc12_b_api adc12_b +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_ADC12_B__ +#include "adc12_b.h" + +#include + +bool ADC12_B_init(uint16_t baseAddress, + ADC12_B_initParam *param) +{ + //Make sure the ENC bit is cleared before initializing the ADC12 + HWREG8(baseAddress + OFS_ADC12CTL0_L) &= ~ADC12ENC; + + bool retVal = STATUS_SUCCESS; + + //Turn OFF ADC12B Module & Clear Interrupt Registers + HWREG16(baseAddress + OFS_ADC12CTL0) &= ~(ADC12ON + ADC12ENC + ADC12SC); + HWREG16(baseAddress + OFS_ADC12IER0) &= 0x0000; //Reset ALL interrupt enables + HWREG16(baseAddress + OFS_ADC12IER1) &= 0x0000; + HWREG16(baseAddress + OFS_ADC12IER2) &= 0x0000; + HWREG16(baseAddress + OFS_ADC12IFGR0) &= 0x0000; //Reset ALL interrupt flags + HWREG16(baseAddress + OFS_ADC12IFGR1) &= 0x0000; + HWREG16(baseAddress + OFS_ADC12IFGR2) &= 0x0000; + + //Set ADC12B Control 1 + HWREG16(baseAddress + OFS_ADC12CTL1) = + param->sampleHoldSignalSourceSelect //Setup the Sample-and-Hold Source + + (param->clockSourceDivider & ADC12DIV_7) //Set Clock Divider + + (param->clockSourcePredivider & ADC12PDIV__64) + + param->clockSourceSelect; //Setup Clock Source + + //Set ADC12B Control 2 + HWREG16(baseAddress + OFS_ADC12CTL2) = + ADC12RES_2; //Default resolution to 12-bits + + //Set ADC12B Control 3 + HWREG16(baseAddress + OFS_ADC12CTL3) = + param->internalChannelMap; // Map internal channels + + return (retVal); +} + +void ADC12_B_enable(uint16_t baseAddress) +{ + // Clear ENC bit + HWREG8(baseAddress + OFS_ADC12CTL0_L) &= ~ADC12ENC; + + //Enable the ADC12B Module + HWREG8(baseAddress + OFS_ADC12CTL0_L) |= ADC12ON; +} + +void ADC12_B_disable(uint16_t baseAddress) +{ + // Clear ENC bit + HWREG8(baseAddress + OFS_ADC12CTL0_L) &= ~ADC12ENC; + + //Disable ADC12B module + HWREG8(baseAddress + OFS_ADC12CTL0_L) &= ~ADC12ON; +} + +void ADC12_B_setupSamplingTimer(uint16_t baseAddress, + uint16_t clockCycleHoldCountLowMem, + uint16_t clockCycleHoldCountHighMem, + uint16_t multipleSamplesEnabled) +{ + HWREG16(baseAddress + OFS_ADC12CTL1) |= ADC12SHP; + + //Reset clock cycle hold counts and msc bit before setting them + HWREG16(baseAddress + OFS_ADC12CTL0) &= + ~(ADC12SHT0_15 + ADC12SHT1_15 + ADC12MSC); + + //Set clock cycle hold counts and msc bit + HWREG16(baseAddress + OFS_ADC12CTL0) |= clockCycleHoldCountLowMem + + (clockCycleHoldCountHighMem << 4) + + multipleSamplesEnabled; +} + +void ADC12_B_disableSamplingTimer(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_ADC12CTL1) &= ~(ADC12SHP); +} + +void ADC12_B_configureMemory(uint16_t baseAddress, + ADC12_B_configureMemoryParam *param) +{ + //Set the offset in respect to ADC12MCTL0 + uint16_t memoryBufferControlOffset = + (OFS_ADC12MCTL0 + param->memoryBufferControlIndex); + + //Reset the memory buffer control and Set the input source + HWREG16(baseAddress + memoryBufferControlOffset) = + param->inputSourceSelect //Set Input Source + + param->refVoltageSourceSelect //Set Vref+/- + + param->endOfSequence; //Set End of Sequence + + HWREG16(baseAddress + memoryBufferControlOffset) + &= ~(ADC12WINC); + + HWREG16(baseAddress + memoryBufferControlOffset) + |= param->windowComparatorSelect; + //(OFS_ADC12MCTL0_H + memoryIndex) == offset of OFS_ADC12MCTLX_H + + HWREG16(baseAddress + memoryBufferControlOffset) + &= ~(ADC12DIF); + + HWREG16(baseAddress + memoryBufferControlOffset) + |= param->differentialModeSelect; + //(OFS_ADC12MCTL0_H + memoryIndex) == offset of OFS_ADC12MCTLX_H +} + +void ADC12_B_setWindowCompAdvanced(uint16_t baseAddress, + uint16_t highThreshold, + uint16_t lowThreshold) +{ + HWREG16(baseAddress + OFS_ADC12HI) = highThreshold; + HWREG16(baseAddress + OFS_ADC12LO) = lowThreshold; +} + +void ADC12_B_enableInterrupt(uint16_t baseAddress, + uint16_t interruptMask0, + uint16_t interruptMask1, + uint16_t interruptMask2) +{ + HWREG16(baseAddress + OFS_ADC12IER0) |= interruptMask0; + HWREG16(baseAddress + OFS_ADC12IER1) |= interruptMask1; + HWREG16(baseAddress + OFS_ADC12IER2) |= interruptMask2; +} + +void ADC12_B_disableInterrupt(uint16_t baseAddress, + uint16_t interruptMask0, + uint16_t interruptMask1, + uint16_t interruptMask2) +{ + HWREG16(baseAddress + OFS_ADC12IER0) &= ~(interruptMask0); + HWREG16(baseAddress + OFS_ADC12IER1) &= ~(interruptMask1); + HWREG16(baseAddress + OFS_ADC12IER2) &= ~(interruptMask2); +} + +void ADC12_B_clearInterrupt(uint16_t baseAddress, + uint8_t interruptRegisterChoice, + uint16_t memoryInterruptFlagMask) +{ + HWREG16(baseAddress + OFS_ADC12IFGR0 + 2 * interruptRegisterChoice) &= + ~(memoryInterruptFlagMask); +} + +uint16_t ADC12_B_getInterruptStatus(uint16_t baseAddress, + uint8_t interruptRegisterChoice, + uint16_t memoryInterruptFlagMask) +{ + return (HWREG16(baseAddress + OFS_ADC12IFGR0 + 2 * interruptRegisterChoice) + & memoryInterruptFlagMask); +} + +void ADC12_B_startConversion(uint16_t baseAddress, + uint16_t startingMemoryBufferIndex, + uint8_t conversionSequenceModeSelect) +{ + //Reset the ENC bit to set the starting memory address and conversion mode + //sequence + HWREG8(baseAddress + OFS_ADC12CTL0_L) &= ~(ADC12ENC); + //Reset the bits about to be set + HWREG16(baseAddress + OFS_ADC12CTL3) &= ~(ADC12CSTARTADD_31); + HWREG16(baseAddress + OFS_ADC12CTL1) &= ~(ADC12CONSEQ_3); + + HWREG16(baseAddress + OFS_ADC12CTL3) |= startingMemoryBufferIndex; + HWREG16(baseAddress + OFS_ADC12CTL1) |= conversionSequenceModeSelect; + HWREG8(baseAddress + OFS_ADC12CTL0_L) |= ADC12ENC + ADC12SC; +} + +void ADC12_B_disableConversions(uint16_t baseAddress, + bool preempt) +{ + if(ADC12_B_PREEMPTCONVERSION == preempt) + { + HWREG8(baseAddress + OFS_ADC12CTL1_L) &= ~(ADC12CONSEQ_3); + //Reset conversion sequence mode to single-channel, single-conversion + } + else if(~(HWREG8(baseAddress + OFS_ADC12CTL1_L) & ADC12CONSEQ_3)) + { + //To prevent preemption of a single-channel, single-conversion we must + //wait for the ADC core to finish the conversion. + while(ADC12_B_isBusy(baseAddress)) + { + ; + } + } + + HWREG8(baseAddress + OFS_ADC12CTL0_L) &= ~(ADC12ENC); +} + +uint16_t ADC12_B_getResults(uint16_t baseAddress, + uint8_t memoryBufferIndex) +{ + return (HWREG16(baseAddress + (OFS_ADC12MEM0 + memoryBufferIndex))); + //(0x60 + memoryBufferIndex) == offset of ADC12MEMx +} + +void ADC12_B_setResolution(uint16_t baseAddress, + uint8_t resolutionSelect) +{ + HWREG8(baseAddress + OFS_ADC12CTL2_L) &= ~(ADC12RES_3); + HWREG8(baseAddress + OFS_ADC12CTL2_L) |= resolutionSelect; +} + +void ADC12_B_setSampleHoldSignalInversion(uint16_t baseAddress, + uint16_t invertedSignal) +{ + HWREG16(baseAddress + OFS_ADC12CTL1) &= ~(ADC12ISSH); + HWREG16(baseAddress + OFS_ADC12CTL1) |= invertedSignal; +} + +void ADC12_B_setDataReadBackFormat(uint16_t baseAddress, + uint8_t readBackFormat) +{ + HWREG8(baseAddress + OFS_ADC12CTL2_L) &= ~(ADC12DF); + HWREG8(baseAddress + OFS_ADC12CTL2_L) |= readBackFormat; +} + +void ADC12_B_setAdcPowerMode(uint16_t baseAddress, + uint8_t powerMode) +{ + HWREG8(baseAddress + OFS_ADC12CTL2_L) &= ~(ADC12PWRMD); + HWREG8(baseAddress + OFS_ADC12CTL2_L) |= powerMode; +} + +uint32_t ADC12_B_getMemoryAddressForDMA(uint16_t baseAddress, + uint8_t memoryIndex) +{ + return (baseAddress + (OFS_ADC12MEM0 + memoryIndex)); + //(0x60 + memoryIndex) == offset of ADC12MEMx +} + +uint8_t ADC12_B_isBusy(uint16_t baseAddress) +{ + return (HWREG8(baseAddress + OFS_ADC12CTL1_L) & ADC12BUSY); +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for adc12_b_api +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/adc12_b.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/adc12_b.h new file mode 100644 index 000000000..5a9b8b7d2 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/adc12_b.h @@ -0,0 +1,1491 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// adc12_b.h - Driver for the ADC12_B Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_ADC12_B_H__ +#define __MSP430WARE_ADC12_B_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_ADC12_B__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "inc/hw_regaccess.h" +//***************************************************************************** +// +//! \brief Used in the ADC12_B_init() function as the param parameter. +// +//***************************************************************************** +typedef struct ADC12_B_initParam +{ + //! Is the signal that will trigger a sample-and-hold for an input signal + //! to be converted. + //! \n Valid values are: + //! - \b ADC12_B_SAMPLEHOLDSOURCE_SC [Default] + //! - \b ADC12_B_SAMPLEHOLDSOURCE_1 + //! - \b ADC12_B_SAMPLEHOLDSOURCE_2 + //! - \b ADC12_B_SAMPLEHOLDSOURCE_3 + //! - \b ADC12_B_SAMPLEHOLDSOURCE_4 + //! - \b ADC12_B_SAMPLEHOLDSOURCE_5 + //! - \b ADC12_B_SAMPLEHOLDSOURCE_6 + //! - \b ADC12_B_SAMPLEHOLDSOURCE_7 + uint16_t sampleHoldSignalSourceSelect; + //! Selects the clock that will be used by the ADC12B core, and the + //! sampling timer if a sampling pulse mode is enabled. + //! \n Valid values are: + //! - \b ADC12_B_CLOCKSOURCE_ADC12OSC [Default] + //! - \b ADC12_B_CLOCKSOURCE_ACLK + //! - \b ADC12_B_CLOCKSOURCE_MCLK + //! - \b ADC12_B_CLOCKSOURCE_SMCLK + uint8_t clockSourceSelect; + //! Selects the amount that the clock will be divided. + //! \n Valid values are: + //! - \b ADC12_B_CLOCKDIVIDER_1 [Default] + //! - \b ADC12_B_CLOCKDIVIDER_2 + //! - \b ADC12_B_CLOCKDIVIDER_3 + //! - \b ADC12_B_CLOCKDIVIDER_4 + //! - \b ADC12_B_CLOCKDIVIDER_5 + //! - \b ADC12_B_CLOCKDIVIDER_6 + //! - \b ADC12_B_CLOCKDIVIDER_7 + //! - \b ADC12_B_CLOCKDIVIDER_8 + uint16_t clockSourceDivider; + //! Selects the amount that the clock will be predivided. + //! \n Valid values are: + //! - \b ADC12_B_CLOCKPREDIVIDER__1 [Default] + //! - \b ADC12_B_CLOCKPREDIVIDER__4 + //! - \b ADC12_B_CLOCKPREDIVIDER__32 + //! - \b ADC12_B_CLOCKPREDIVIDER__64 + uint16_t clockSourcePredivider; + //! Selects what internal channel to map for ADC input channels + //! \n Valid values are: + //! - \b ADC12_B_MAPINTCH3 + //! - \b ADC12_B_MAPINTCH2 + //! - \b ADC12_B_MAPINTCH1 + //! - \b ADC12_B_MAPINTCH0 + //! - \b ADC12_B_TEMPSENSEMAP + //! - \b ADC12_B_BATTMAP + //! - \b ADC12_B_NOINTCH + uint16_t internalChannelMap; +} ADC12_B_initParam; + +//***************************************************************************** +// +//! \brief Used in the ADC12_B_configureMemory() function as the param +//! parameter. +// +//***************************************************************************** +typedef struct ADC12_B_configureMemoryParam +{ + //! Is the selected memory buffer to set the configuration for. + //! \n Valid values are: + //! - \b ADC12_B_MEMORY_0 + //! - \b ADC12_B_MEMORY_1 + //! - \b ADC12_B_MEMORY_2 + //! - \b ADC12_B_MEMORY_3 + //! - \b ADC12_B_MEMORY_4 + //! - \b ADC12_B_MEMORY_5 + //! - \b ADC12_B_MEMORY_6 + //! - \b ADC12_B_MEMORY_7 + //! - \b ADC12_B_MEMORY_8 + //! - \b ADC12_B_MEMORY_9 + //! - \b ADC12_B_MEMORY_10 + //! - \b ADC12_B_MEMORY_11 + //! - \b ADC12_B_MEMORY_12 + //! - \b ADC12_B_MEMORY_13 + //! - \b ADC12_B_MEMORY_14 + //! - \b ADC12_B_MEMORY_15 + //! - \b ADC12_B_MEMORY_16 + //! - \b ADC12_B_MEMORY_17 + //! - \b ADC12_B_MEMORY_18 + //! - \b ADC12_B_MEMORY_19 + //! - \b ADC12_B_MEMORY_20 + //! - \b ADC12_B_MEMORY_21 + //! - \b ADC12_B_MEMORY_22 + //! - \b ADC12_B_MEMORY_23 + //! - \b ADC12_B_MEMORY_24 + //! - \b ADC12_B_MEMORY_25 + //! - \b ADC12_B_MEMORY_26 + //! - \b ADC12_B_MEMORY_27 + //! - \b ADC12_B_MEMORY_28 + //! - \b ADC12_B_MEMORY_29 + //! - \b ADC12_B_MEMORY_30 + //! - \b ADC12_B_MEMORY_31 + uint8_t memoryBufferControlIndex; + //! Is the input that will store the converted data into the specified + //! memory buffer. + //! \n Valid values are: + //! - \b ADC12_B_INPUT_A0 [Default] + //! - \b ADC12_B_INPUT_A1 + //! - \b ADC12_B_INPUT_A2 + //! - \b ADC12_B_INPUT_A3 + //! - \b ADC12_B_INPUT_A4 + //! - \b ADC12_B_INPUT_A5 + //! - \b ADC12_B_INPUT_A6 + //! - \b ADC12_B_INPUT_A7 + //! - \b ADC12_B_INPUT_A8 + //! - \b ADC12_B_INPUT_A9 + //! - \b ADC12_B_INPUT_A10 + //! - \b ADC12_B_INPUT_A11 + //! - \b ADC12_B_INPUT_A12 + //! - \b ADC12_B_INPUT_A13 + //! - \b ADC12_B_INPUT_A14 + //! - \b ADC12_B_INPUT_A15 + //! - \b ADC12_B_INPUT_A16 + //! - \b ADC12_B_INPUT_A17 + //! - \b ADC12_B_INPUT_A18 + //! - \b ADC12_B_INPUT_A19 + //! - \b ADC12_B_INPUT_A20 + //! - \b ADC12_B_INPUT_A21 + //! - \b ADC12_B_INPUT_A22 + //! - \b ADC12_B_INPUT_A23 + //! - \b ADC12_B_INPUT_A24 + //! - \b ADC12_B_INPUT_A25 + //! - \b ADC12_B_INPUT_A26 + //! - \b ADC12_B_INPUT_A27 + //! - \b ADC12_B_INPUT_A28 + //! - \b ADC12_B_INPUT_A29 + //! - \b ADC12_B_INPUT_TCMAP + //! - \b ADC12_B_INPUT_BATMAP + uint8_t inputSourceSelect; + //! Is the reference voltage source to set as the upper/lower limits for + //! the conversion stored in the specified memory. + //! \n Valid values are: + //! - \b ADC12_B_VREFPOS_AVCC_VREFNEG_VSS [Default] + //! - \b ADC12_B_VREFPOS_INTBUF_VREFNEG_VSS + //! - \b ADC12_B_VREFPOS_EXTNEG_VREFNEG_VSS + //! - \b ADC12_B_VREFPOS_EXTBUF_VREFNEG_VSS + //! - \b ADC12_B_VREFPOS_EXTPOS_VREFNEG_VSS + //! - \b ADC12_B_VREFPOS_AVCC_VREFNEG_EXTBUF + //! - \b ADC12_B_VREFPOS_AVCC_VREFNEG_EXTPOS + //! - \b ADC12_B_VREFPOS_INTBUF_VREFNEG_EXTPOS + //! - \b ADC12_B_VREFPOS_AVCC_VREFNEG_INTBUF + //! - \b ADC12_B_VREFPOS_EXTPOS_VREFNEG_INTBUF + //! - \b ADC12_B_VREFPOS_AVCC_VREFNEG_EXTNEG + //! - \b ADC12_B_VREFPOS_INTBUF_VREFNEG_EXTNEG + //! - \b ADC12_B_VREFPOS_EXTPOS_VREFNEG_EXTNEG + //! - \b ADC12_B_VREFPOS_EXTBUF_VREFNEG_EXTNEG + uint16_t refVoltageSourceSelect; + //! Indicates that the specified memory buffer will be the end of the + //! sequence if a sequenced conversion mode is selected + //! \n Valid values are: + //! - \b ADC12_B_NOTENDOFSEQUENCE [Default] + //! - \b ADC12_B_ENDOFSEQUENCE + uint16_t endOfSequence; + //! Sets the window comparator mode + //! \n Valid values are: + //! - \b ADC12_B_WINDOW_COMPARATOR_DISABLE [Default] + //! - \b ADC12_B_WINDOW_COMPARATOR_ENABLE + uint16_t windowComparatorSelect; + //! Sets the differential mode + //! \n Valid values are: + //! - \b ADC12_B_DIFFERENTIAL_MODE_DISABLE [Default] + //! - \b ADC12_B_DIFFERENTIAL_MODE_ENABLE + uint16_t differentialModeSelect; +} ADC12_B_configureMemoryParam; + +//***************************************************************************** +// +// The following are values that can be passed to the clockSourceDivider +// parameter for functions: ADC12_B_init(); the param parameter for functions: +// ADC12_B_init(). +// +//***************************************************************************** +#define ADC12_B_CLOCKDIVIDER_1 (ADC12DIV_0) +#define ADC12_B_CLOCKDIVIDER_2 (ADC12DIV_1) +#define ADC12_B_CLOCKDIVIDER_3 (ADC12DIV_2) +#define ADC12_B_CLOCKDIVIDER_4 (ADC12DIV_3) +#define ADC12_B_CLOCKDIVIDER_5 (ADC12DIV_4) +#define ADC12_B_CLOCKDIVIDER_6 (ADC12DIV_5) +#define ADC12_B_CLOCKDIVIDER_7 (ADC12DIV_6) +#define ADC12_B_CLOCKDIVIDER_8 (ADC12DIV_7) + +//***************************************************************************** +// +// The following are values that can be passed to the clockSourceSelect +// parameter for functions: ADC12_B_init(); the param parameter for functions: +// ADC12_B_init(). +// +//***************************************************************************** +#define ADC12_B_CLOCKSOURCE_ADC12OSC (ADC12SSEL_0) +#define ADC12_B_CLOCKSOURCE_ACLK (ADC12SSEL_1) +#define ADC12_B_CLOCKSOURCE_MCLK (ADC12SSEL_2) +#define ADC12_B_CLOCKSOURCE_SMCLK (ADC12SSEL_3) + +//***************************************************************************** +// +// The following are values that can be passed to the clockSourcePredivider +// parameter for functions: ADC12_B_init(); the param parameter for functions: +// ADC12_B_init(). +// +//***************************************************************************** +#define ADC12_B_CLOCKPREDIVIDER__1 (ADC12PDIV__1) +#define ADC12_B_CLOCKPREDIVIDER__4 (ADC12PDIV__4) +#define ADC12_B_CLOCKPREDIVIDER__32 (ADC12PDIV__32) +#define ADC12_B_CLOCKPREDIVIDER__64 (ADC12PDIV__64) + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: ADC12_B_init(); the sampleHoldSignalSourceSelect parameter for +// functions: ADC12_B_init(). +// +//***************************************************************************** +#define ADC12_B_SAMPLEHOLDSOURCE_SC (ADC12SHS_0) +#define ADC12_B_SAMPLEHOLDSOURCE_1 (ADC12SHS_1) +#define ADC12_B_SAMPLEHOLDSOURCE_2 (ADC12SHS_2) +#define ADC12_B_SAMPLEHOLDSOURCE_3 (ADC12SHS_3) +#define ADC12_B_SAMPLEHOLDSOURCE_4 (ADC12SHS_4) +#define ADC12_B_SAMPLEHOLDSOURCE_5 (ADC12SHS_5) +#define ADC12_B_SAMPLEHOLDSOURCE_6 (ADC12SHS_6) +#define ADC12_B_SAMPLEHOLDSOURCE_7 (ADC12SHS_7) + +//***************************************************************************** +// +// The following are values that can be passed to the internalChannelMap +// parameter for functions: ADC12_B_init(); the param parameter for functions: +// ADC12_B_init(). +// +//***************************************************************************** +#define ADC12_B_MAPINTCH3 (ADC12ICH3MAP) +#define ADC12_B_MAPINTCH2 (ADC12ICH2MAP) +#define ADC12_B_MAPINTCH1 (ADC12ICH1MAP) +#define ADC12_B_MAPINTCH0 (ADC12ICH0MAP) +#define ADC12_B_TEMPSENSEMAP (ADC12TCMAP) +#define ADC12_B_BATTMAP (ADC12BATMAP) +#define ADC12_B_NOINTCH (0x00) + +//***************************************************************************** +// +// The following are values that can be passed to the clockCycleHoldCountLowMem +// parameter for functions: ADC12_B_setupSamplingTimer(); the +// clockCycleHoldCountHighMem parameter for functions: +// ADC12_B_setupSamplingTimer(). +// +//***************************************************************************** +#define ADC12_B_CYCLEHOLD_4_CYCLES (ADC12SHT0_0) +#define ADC12_B_CYCLEHOLD_8_CYCLES (ADC12SHT0_1) +#define ADC12_B_CYCLEHOLD_16_CYCLES (ADC12SHT0_2) +#define ADC12_B_CYCLEHOLD_32_CYCLES (ADC12SHT0_3) +#define ADC12_B_CYCLEHOLD_64_CYCLES (ADC12SHT0_4) +#define ADC12_B_CYCLEHOLD_96_CYCLES (ADC12SHT0_5) +#define ADC12_B_CYCLEHOLD_128_CYCLES (ADC12SHT0_6) +#define ADC12_B_CYCLEHOLD_192_CYCLES (ADC12SHT0_7) +#define ADC12_B_CYCLEHOLD_256_CYCLES (ADC12SHT0_8) +#define ADC12_B_CYCLEHOLD_384_CYCLES (ADC12SHT0_9) +#define ADC12_B_CYCLEHOLD_512_CYCLES (ADC12SHT0_10) +#define ADC12_B_CYCLEHOLD_768_CYCLES (ADC12SHT0_11) +#define ADC12_B_CYCLEHOLD_1024_CYCLES (ADC12SHT0_12) + +//***************************************************************************** +// +// The following are values that can be passed to the multipleSamplesEnabled +// parameter for functions: ADC12_B_setupSamplingTimer(). +// +//***************************************************************************** +#define ADC12_B_MULTIPLESAMPLESDISABLE (!(ADC12MSC)) +#define ADC12_B_MULTIPLESAMPLESENABLE (ADC12MSC) + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: ADC12_B_configureMemory(). +// +//***************************************************************************** +#define ADC12_B_DIFFERENTIAL_MODE_DISABLE (0x00) +#define ADC12_B_DIFFERENTIAL_MODE_ENABLE (ADC12DIF) + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: ADC12_B_configureMemory(). +// +//***************************************************************************** +#define ADC12_B_NOTENDOFSEQUENCE (!(ADC12EOS)) +#define ADC12_B_ENDOFSEQUENCE (ADC12EOS) + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: ADC12_B_configureMemory(). +// +//***************************************************************************** +#define ADC12_B_VREFPOS_AVCC_VREFNEG_VSS (ADC12VRSEL_0) +#define ADC12_B_VREFPOS_INTBUF_VREFNEG_VSS (ADC12VRSEL_1) +#define ADC12_B_VREFPOS_EXTNEG_VREFNEG_VSS (ADC12VRSEL_2) +#define ADC12_B_VREFPOS_EXTBUF_VREFNEG_VSS (ADC12VRSEL_3) +#define ADC12_B_VREFPOS_EXTPOS_VREFNEG_VSS (ADC12VRSEL_4) +#define ADC12_B_VREFPOS_AVCC_VREFNEG_EXTBUF (ADC12VRSEL_5) +#define ADC12_B_VREFPOS_AVCC_VREFNEG_EXTPOS (ADC12VRSEL_6) +#define ADC12_B_VREFPOS_INTBUF_VREFNEG_EXTPOS (ADC12VRSEL_7) +#define ADC12_B_VREFPOS_AVCC_VREFNEG_INTBUF (ADC12VRSEL_9) +#define ADC12_B_VREFPOS_EXTPOS_VREFNEG_INTBUF (ADC12VRSEL_11) +#define ADC12_B_VREFPOS_AVCC_VREFNEG_EXTNEG (ADC12VRSEL_12) +#define ADC12_B_VREFPOS_INTBUF_VREFNEG_EXTNEG (ADC12VRSEL_13) +#define ADC12_B_VREFPOS_EXTPOS_VREFNEG_EXTNEG (ADC12VRSEL_14) +#define ADC12_B_VREFPOS_EXTBUF_VREFNEG_EXTNEG (ADC12VRSEL_15) + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: ADC12_B_configureMemory(). +// +//***************************************************************************** +#define ADC12_B_INPUT_A0 (ADC12INCH_0) +#define ADC12_B_INPUT_A1 (ADC12INCH_1) +#define ADC12_B_INPUT_A2 (ADC12INCH_2) +#define ADC12_B_INPUT_A3 (ADC12INCH_3) +#define ADC12_B_INPUT_A4 (ADC12INCH_4) +#define ADC12_B_INPUT_A5 (ADC12INCH_5) +#define ADC12_B_INPUT_A6 (ADC12INCH_6) +#define ADC12_B_INPUT_A7 (ADC12INCH_7) +#define ADC12_B_INPUT_A8 (ADC12INCH_8) +#define ADC12_B_INPUT_A9 (ADC12INCH_9) +#define ADC12_B_INPUT_A10 (ADC12INCH_10) +#define ADC12_B_INPUT_A11 (ADC12INCH_11) +#define ADC12_B_INPUT_A12 (ADC12INCH_12) +#define ADC12_B_INPUT_A13 (ADC12INCH_13) +#define ADC12_B_INPUT_A14 (ADC12INCH_14) +#define ADC12_B_INPUT_A15 (ADC12INCH_15) +#define ADC12_B_INPUT_A16 (ADC12INCH_16) +#define ADC12_B_INPUT_A17 (ADC12INCH_17) +#define ADC12_B_INPUT_A18 (ADC12INCH_18) +#define ADC12_B_INPUT_A19 (ADC12INCH_19) +#define ADC12_B_INPUT_A20 (ADC12INCH_20) +#define ADC12_B_INPUT_A21 (ADC12INCH_21) +#define ADC12_B_INPUT_A22 (ADC12INCH_22) +#define ADC12_B_INPUT_A23 (ADC12INCH_23) +#define ADC12_B_INPUT_A24 (ADC12INCH_24) +#define ADC12_B_INPUT_A25 (ADC12INCH_25) +#define ADC12_B_INPUT_A26 (ADC12INCH_26) +#define ADC12_B_INPUT_A27 (ADC12INCH_27) +#define ADC12_B_INPUT_A28 (ADC12INCH_28) +#define ADC12_B_INPUT_A29 (ADC12INCH_29) +#define ADC12_B_INPUT_TCMAP (ADC12INCH_30) +#define ADC12_B_INPUT_BATMAP (ADC12INCH_31) + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: ADC12_B_configureMemory(). +// +//***************************************************************************** +#define ADC12_B_WINDOW_COMPARATOR_DISABLE (0x00) +#define ADC12_B_WINDOW_COMPARATOR_ENABLE (ADC12WINC) + +//***************************************************************************** +// +// The following are values that can be passed to the memoryIndex parameter for +// functions: ADC12_B_getMemoryAddressForDMA(); the memoryBufferIndex parameter +// for functions: ADC12_B_getResults(); the param parameter for functions: +// ADC12_B_configureMemory(). +// +//***************************************************************************** +#define ADC12_B_MEMORY_0 (0x00) +#define ADC12_B_MEMORY_1 (0x02) +#define ADC12_B_MEMORY_2 (0x04) +#define ADC12_B_MEMORY_3 (0x06) +#define ADC12_B_MEMORY_4 (0x08) +#define ADC12_B_MEMORY_5 (0x0A) +#define ADC12_B_MEMORY_6 (0x0C) +#define ADC12_B_MEMORY_7 (0x0E) +#define ADC12_B_MEMORY_8 (0x10) +#define ADC12_B_MEMORY_9 (0x12) +#define ADC12_B_MEMORY_10 (0x14) +#define ADC12_B_MEMORY_11 (0x16) +#define ADC12_B_MEMORY_12 (0x18) +#define ADC12_B_MEMORY_13 (0x1A) +#define ADC12_B_MEMORY_14 (0x1C) +#define ADC12_B_MEMORY_15 (0x1E) +#define ADC12_B_MEMORY_16 (0x20) +#define ADC12_B_MEMORY_17 (0x22) +#define ADC12_B_MEMORY_18 (0x24) +#define ADC12_B_MEMORY_19 (0x26) +#define ADC12_B_MEMORY_20 (0x28) +#define ADC12_B_MEMORY_21 (0x2A) +#define ADC12_B_MEMORY_22 (0x2C) +#define ADC12_B_MEMORY_23 (0x2E) +#define ADC12_B_MEMORY_24 (0x30) +#define ADC12_B_MEMORY_25 (0x32) +#define ADC12_B_MEMORY_26 (0x34) +#define ADC12_B_MEMORY_27 (0x36) +#define ADC12_B_MEMORY_28 (0x38) +#define ADC12_B_MEMORY_29 (0x3A) +#define ADC12_B_MEMORY_30 (0x3C) +#define ADC12_B_MEMORY_31 (0x3E) + +//***************************************************************************** +// +// The following are values that can be passed to the interruptMask0 parameter +// for functions: ADC12_B_enableInterrupt(), and ADC12_B_disableInterrupt(). +// +//***************************************************************************** +#define ADC12_B_IE0 (ADC12IE0) +#define ADC12_B_IE1 (ADC12IE1) +#define ADC12_B_IE2 (ADC12IE2) +#define ADC12_B_IE3 (ADC12IE3) +#define ADC12_B_IE4 (ADC12IE4) +#define ADC12_B_IE5 (ADC12IE5) +#define ADC12_B_IE6 (ADC12IE6) +#define ADC12_B_IE7 (ADC12IE7) +#define ADC12_B_IE8 (ADC12IE8) +#define ADC12_B_IE9 (ADC12IE9) +#define ADC12_B_IE10 (ADC12IE10) +#define ADC12_B_IE11 (ADC12IE11) +#define ADC12_B_IE12 (ADC12IE12) +#define ADC12_B_IE13 (ADC12IE13) +#define ADC12_B_IE14 (ADC12IE14) +#define ADC12_B_IE15 (ADC12IE15) + +//***************************************************************************** +// +// The following are values that can be passed to the interruptMask1 parameter +// for functions: ADC12_B_enableInterrupt(), and ADC12_B_disableInterrupt(). +// +//***************************************************************************** +#define ADC12_B_IE16 (ADC12IE16) +#define ADC12_B_IE17 (ADC12IE17) +#define ADC12_B_IE18 (ADC12IE18) +#define ADC12_B_IE19 (ADC12IE19) +#define ADC12_B_IE20 (ADC12IE20) +#define ADC12_B_IE21 (ADC12IE21) +#define ADC12_B_IE22 (ADC12IE22) +#define ADC12_B_IE23 (ADC12IE23) +#define ADC12_B_IE24 (ADC12IE24) +#define ADC12_B_IE25 (ADC12IE25) +#define ADC12_B_IE26 (ADC12IE26) +#define ADC12_B_IE27 (ADC12IE27) +#define ADC12_B_IE28 (ADC12IE28) +#define ADC12_B_IE29 (ADC12IE29) +#define ADC12_B_IE30 (ADC12IE30) +#define ADC12_B_IE31 (ADC12IE31) + +//***************************************************************************** +// +// The following are values that can be passed to the interruptMask2 parameter +// for functions: ADC12_B_enableInterrupt(), and ADC12_B_disableInterrupt(). +// +//***************************************************************************** +#define ADC12_B_INIE (ADC12INIE) +#define ADC12_B_LOIE (ADC12LOIE) +#define ADC12_B_HIIE (ADC12HIIE) +#define ADC12_B_OVIE (ADC12OVIE) +#define ADC12_B_TOVIE (ADC12TOVIE) +#define ADC12_B_RDYIE (ADC12RDYIE) + +//***************************************************************************** +// +// The following are values that can be passed to the memoryInterruptFlagMask +// parameter for functions: ADC12_B_clearInterrupt(), and +// ADC12_B_getInterruptStatus(). +// +//***************************************************************************** +#define ADC12_B_IFG0 (ADC12IFG0) +#define ADC12_B_IFG1 (ADC12IFG1) +#define ADC12_B_IFG2 (ADC12IFG2) +#define ADC12_B_IFG3 (ADC12IFG3) +#define ADC12_B_IFG4 (ADC12IFG4) +#define ADC12_B_IFG5 (ADC12IFG5) +#define ADC12_B_IFG6 (ADC12IFG6) +#define ADC12_B_IFG7 (ADC12IFG7) +#define ADC12_B_IFG8 (ADC12IFG8) +#define ADC12_B_IFG9 (ADC12IFG9) +#define ADC12_B_IFG10 (ADC12IFG10) +#define ADC12_B_IFG11 (ADC12IFG11) +#define ADC12_B_IFG12 (ADC12IFG12) +#define ADC12_B_IFG13 (ADC12IFG13) +#define ADC12_B_IFG14 (ADC12IFG14) +#define ADC12_B_IFG15 (ADC12IFG15) +#define ADC12_B_IFG16 (ADC12IFG16) +#define ADC12_B_IFG17 (ADC12IFG17) +#define ADC12_B_IFG18 (ADC12IFG18) +#define ADC12_B_IFG19 (ADC12IFG19) +#define ADC12_B_IFG20 (ADC12IFG20) +#define ADC12_B_IFG21 (ADC12IFG21) +#define ADC12_B_IFG22 (ADC12IFG22) +#define ADC12_B_IFG23 (ADC12IFG23) +#define ADC12_B_IFG24 (ADC12IFG24) +#define ADC12_B_IFG25 (ADC12IFG25) +#define ADC12_B_IFG26 (ADC12IFG26) +#define ADC12_B_IFG27 (ADC12IFG27) +#define ADC12_B_IFG28 (ADC12IFG28) +#define ADC12_B_IFG29 (ADC12IFG29) +#define ADC12_B_IFG30 (ADC12IFG30) +#define ADC12_B_IFG31 (ADC12IFG31) +#define ADC12_B_INIFG (ADC12INIFG) +#define ADC12_B_LOIFG (ADC12LOIFG) +#define ADC12_B_HIIFG (ADC12HIIFG) +#define ADC12_B_OVIFG (ADC12OVIFG) +#define ADC12_B_TOVIFG (ADC12TOVIFG) +#define ADC12_B_RDYIFG (ADC12RDYIFG) + +//***************************************************************************** +// +// The following are values that can be passed to the startingMemoryBufferIndex +// parameter for functions: ADC12_B_startConversion(). +// +//***************************************************************************** +#define ADC12_B_START_AT_ADC12MEM0 (ADC12CSTARTADD_0) +#define ADC12_B_START_AT_ADC12MEM1 (ADC12CSTARTADD_1) +#define ADC12_B_START_AT_ADC12MEM2 (ADC12CSTARTADD_2) +#define ADC12_B_START_AT_ADC12MEM3 (ADC12CSTARTADD_3) +#define ADC12_B_START_AT_ADC12MEM4 (ADC12CSTARTADD_4) +#define ADC12_B_START_AT_ADC12MEM5 (ADC12CSTARTADD_5) +#define ADC12_B_START_AT_ADC12MEM6 (ADC12CSTARTADD_6) +#define ADC12_B_START_AT_ADC12MEM7 (ADC12CSTARTADD_7) +#define ADC12_B_START_AT_ADC12MEM8 (ADC12CSTARTADD_8) +#define ADC12_B_START_AT_ADC12MEM9 (ADC12CSTARTADD_9) +#define ADC12_B_START_AT_ADC12MEM10 (ADC12CSTARTADD_10) +#define ADC12_B_START_AT_ADC12MEM11 (ADC12CSTARTADD_11) +#define ADC12_B_START_AT_ADC12MEM12 (ADC12CSTARTADD_12) +#define ADC12_B_START_AT_ADC12MEM13 (ADC12CSTARTADD_13) +#define ADC12_B_START_AT_ADC12MEM14 (ADC12CSTARTADD_14) +#define ADC12_B_START_AT_ADC12MEM15 (ADC12CSTARTADD_15) +#define ADC12_B_START_AT_ADC12MEM16 (ADC12CSTARTADD_16) +#define ADC12_B_START_AT_ADC12MEM17 (ADC12CSTARTADD_17) +#define ADC12_B_START_AT_ADC12MEM18 (ADC12CSTARTADD_18) +#define ADC12_B_START_AT_ADC12MEM19 (ADC12CSTARTADD_19) +#define ADC12_B_START_AT_ADC12MEM20 (ADC12CSTARTADD_20) +#define ADC12_B_START_AT_ADC12MEM21 (ADC12CSTARTADD_21) +#define ADC12_B_START_AT_ADC12MEM22 (ADC12CSTARTADD_22) +#define ADC12_B_START_AT_ADC12MEM23 (ADC12CSTARTADD_23) +#define ADC12_B_START_AT_ADC12MEM24 (ADC12CSTARTADD_24) +#define ADC12_B_START_AT_ADC12MEM25 (ADC12CSTARTADD_25) +#define ADC12_B_START_AT_ADC12MEM26 (ADC12CSTARTADD_26) +#define ADC12_B_START_AT_ADC12MEM27 (ADC12CSTARTADD_27) +#define ADC12_B_START_AT_ADC12MEM28 (ADC12CSTARTADD_28) +#define ADC12_B_START_AT_ADC12MEM29 (ADC12CSTARTADD_29) +#define ADC12_B_START_AT_ADC12MEM30 (ADC12CSTARTADD_30) +#define ADC12_B_START_AT_ADC12MEM31 (ADC12CSTARTADD_31) + +//***************************************************************************** +// +// The following are values that can be passed to the +// conversionSequenceModeSelect parameter for functions: +// ADC12_B_startConversion(). +// +//***************************************************************************** +#define ADC12_B_SINGLECHANNEL (ADC12CONSEQ_0) +#define ADC12_B_SEQOFCHANNELS (ADC12CONSEQ_1) +#define ADC12_B_REPEATED_SINGLECHANNEL (ADC12CONSEQ_2) +#define ADC12_B_REPEATED_SEQOFCHANNELS (ADC12CONSEQ_3) + +//***************************************************************************** +// +// The following are values that can be passed to the preempt parameter for +// functions: ADC12_B_disableConversions(). +// +//***************************************************************************** +#define ADC12_B_COMPLETECONVERSION false +#define ADC12_B_PREEMPTCONVERSION true + +//***************************************************************************** +// +// The following are values that can be passed to the resolutionSelect +// parameter for functions: ADC12_B_setResolution(). +// +//***************************************************************************** +#define ADC12_B_RESOLUTION_8BIT (ADC12RES__8BIT) +#define ADC12_B_RESOLUTION_10BIT (ADC12RES__10BIT) +#define ADC12_B_RESOLUTION_12BIT (ADC12RES__12BIT) + +//***************************************************************************** +// +// The following are values that can be passed to the invertedSignal parameter +// for functions: ADC12_B_setSampleHoldSignalInversion(). +// +//***************************************************************************** +#define ADC12_B_NONINVERTEDSIGNAL (!(ADC12ISSH)) +#define ADC12_B_INVERTEDSIGNAL (ADC12ISSH) + +//***************************************************************************** +// +// The following are values that can be passed to the readBackFormat parameter +// for functions: ADC12_B_setDataReadBackFormat(). +// +//***************************************************************************** +#define ADC12_B_UNSIGNED_BINARY (!(ADC12DF)) +#define ADC12_B_SIGNED_2SCOMPLEMENT (ADC12DF) + +//***************************************************************************** +// +// The following are values that can be passed to the powerMode parameter for +// functions: ADC12_B_setAdcPowerMode(). +// +//***************************************************************************** +#define ADC12_B_REGULARPOWERMODE (!(ADC12PWRMD)) +#define ADC12_B_LOWPOWERMODE (ADC12PWRMD) + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the ADC12_B_isBusy() function. +// +//***************************************************************************** +#define ADC12_B_NOTBUSY 0x00 +#define ADC12_B_BUSY ADC12BUSY + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Initializes the ADC12B Module. +//! +//! This function initializes the ADC module to allow for analog-to-digital +//! conversions. Specifically this function sets up the sample-and-hold signal +//! and clock sources for the ADC core to use for conversions. Upon successful +//! completion of the initialization all of the ADC control registers will be +//! reset, excluding the memory controls and reference module bits, the given +//! parameters will be set, and the ADC core will be turned on (Note, that the +//! ADC core only draws power during conversions and remains off when not +//! converting).Note that sample/hold signal sources are device dependent. Note +//! that if re-initializing the ADC after starting a conversion with the +//! startConversion() function, the disableConversion() must be called BEFORE +//! this function can be called. +//! +//! \param baseAddress is the base address of the ADC12B module. +//! \param param is the pointer to struct for initialization. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the initialization process. +// +//***************************************************************************** +extern bool ADC12_B_init(uint16_t baseAddress, + ADC12_B_initParam *param); + +//***************************************************************************** +// +//! \brief Enables the ADC12B block. +//! +//! This will enable operation of the ADC12B block. +//! +//! \param baseAddress is the base address of the ADC12B module. +//! +//! Modified bits are \b ADC12ON of \b ADC12CTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void ADC12_B_enable(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Disables the ADC12B block. +//! +//! This will disable operation of the ADC12B block. +//! +//! \param baseAddress is the base address of the ADC12B module. +//! +//! Modified bits are \b ADC12ON of \b ADC12CTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void ADC12_B_disable(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Sets up and enables the Sampling Timer Pulse Mode. +//! +//! This function sets up the sampling timer pulse mode which allows the +//! sample/hold signal to trigger a sampling timer to sample-and-hold an input +//! signal for a specified number of clock cycles without having to hold the +//! sample/hold signal for the entire period of sampling. Note that if a +//! conversion has been started with the startConversion() function, then a +//! call to disableConversions() is required before this function may be +//! called. +//! +//! \param baseAddress is the base address of the ADC12B module. +//! \param clockCycleHoldCountLowMem sets the amount of clock cycles to sample- +//! and-hold for the higher memory buffers 0-7. +//! Valid values are: +//! - \b ADC12_B_CYCLEHOLD_4_CYCLES [Default] +//! - \b ADC12_B_CYCLEHOLD_8_CYCLES +//! - \b ADC12_B_CYCLEHOLD_16_CYCLES +//! - \b ADC12_B_CYCLEHOLD_32_CYCLES +//! - \b ADC12_B_CYCLEHOLD_64_CYCLES +//! - \b ADC12_B_CYCLEHOLD_96_CYCLES +//! - \b ADC12_B_CYCLEHOLD_128_CYCLES +//! - \b ADC12_B_CYCLEHOLD_192_CYCLES +//! - \b ADC12_B_CYCLEHOLD_256_CYCLES +//! - \b ADC12_B_CYCLEHOLD_384_CYCLES +//! - \b ADC12_B_CYCLEHOLD_512_CYCLES +//! - \b ADC12_B_CYCLEHOLD_768_CYCLES +//! - \b ADC12_B_CYCLEHOLD_1024_CYCLES +//! \n Modified bits are \b ADC12SHT0x of \b ADC12CTL0 register. +//! \param clockCycleHoldCountHighMem sets the amount of clock cycles to +//! sample-and-hold for the higher memory buffers 8-15. +//! Valid values are: +//! - \b ADC12_B_CYCLEHOLD_4_CYCLES [Default] +//! - \b ADC12_B_CYCLEHOLD_8_CYCLES +//! - \b ADC12_B_CYCLEHOLD_16_CYCLES +//! - \b ADC12_B_CYCLEHOLD_32_CYCLES +//! - \b ADC12_B_CYCLEHOLD_64_CYCLES +//! - \b ADC12_B_CYCLEHOLD_96_CYCLES +//! - \b ADC12_B_CYCLEHOLD_128_CYCLES +//! - \b ADC12_B_CYCLEHOLD_192_CYCLES +//! - \b ADC12_B_CYCLEHOLD_256_CYCLES +//! - \b ADC12_B_CYCLEHOLD_384_CYCLES +//! - \b ADC12_B_CYCLEHOLD_512_CYCLES +//! - \b ADC12_B_CYCLEHOLD_768_CYCLES +//! - \b ADC12_B_CYCLEHOLD_1024_CYCLES +//! \n Modified bits are \b ADC12SHT1x of \b ADC12CTL0 register. +//! \param multipleSamplesEnabled allows multiple conversions to start without +//! a trigger signal from the sample/hold signal +//! Valid values are: +//! - \b ADC12_B_MULTIPLESAMPLESDISABLE [Default] - a timer trigger will +//! be needed to start every ADC conversion. +//! - \b ADC12_B_MULTIPLESAMPLESENABLE - during a sequenced and/or +//! repeated conversion mode, after the first conversion, no +//! sample/hold signal is necessary to start subsequent sample/hold +//! and convert processes. +//! \n Modified bits are \b ADC12MSC of \b ADC12CTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void ADC12_B_setupSamplingTimer(uint16_t baseAddress, + uint16_t clockCycleHoldCountLowMem, + uint16_t clockCycleHoldCountHighMem, + uint16_t multipleSamplesEnabled); + +//***************************************************************************** +// +//! \brief Disables Sampling Timer Pulse Mode. +//! +//! Disables the Sampling Timer Pulse Mode. Note that if a conversion has been +//! started with the startConversion() function, then a call to +//! disableConversions() is required before this function may be called. +//! +//! \param baseAddress is the base address of the ADC12B module. +//! +//! \return None +// +//***************************************************************************** +extern void ADC12_B_disableSamplingTimer(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Configures the controls of the selected memory buffer. +//! +//! Maps an input signal conversion into the selected memory buffer, as well as +//! the positive and negative reference voltages for each conversion being +//! stored into this memory buffer. If the internal reference is used for the +//! positive reference voltage, the internal REF module must be used to control +//! the voltage level. Note that if a conversion has been started with the +//! startConversion() function, then a call to disableConversions() is required +//! before this function may be called. +//! +//! \param baseAddress is the base address of the ADC12B module. +//! \param param is the pointer to struct for ADC12B memory configuration. +//! +//! \return None +// +//***************************************************************************** +extern void ADC12_B_configureMemory(uint16_t baseAddress, + ADC12_B_configureMemoryParam *param); + +//***************************************************************************** +// +//! \brief Sets the high and low threshold for the window comparator feature. +//! +//! Sets the high and low threshold for the window comparator feature. Use the +//! ADC12HIIE, ADC12INIE, ADC12LOIE interrupts to utilize this feature. +//! +//! \param baseAddress is the base address of the ADC12B module. +//! \param highThreshold is the upper bound that could trip an interrupt for +//! the window comparator. +//! \param lowThreshold is the lower bound that could trip on interrupt for the +//! window comparator. +//! +//! \return None +// +//***************************************************************************** +extern void ADC12_B_setWindowCompAdvanced(uint16_t baseAddress, + uint16_t highThreshold, + uint16_t lowThreshold); + +//***************************************************************************** +// +//! \brief Enables selected ADC12B interrupt sources. +//! +//! Enables the indicated ADC12B interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. Does not clear interrupt flags. +//! +//! \param baseAddress is the base address of the ADC12B module. +//! \param interruptMask0 is the bit mask of the memory buffer and overflow +//! interrupt sources to be enabled. If the desired interrupt is not +//! available in the selection for interruptMask0, then simply pass in a +//! '0' for this value. +//! Valid values are: +//! - \b ADC12_B_IE0 +//! - \b ADC12_B_IE1 +//! - \b ADC12_B_IE2 +//! - \b ADC12_B_IE3 +//! - \b ADC12_B_IE4 +//! - \b ADC12_B_IE5 +//! - \b ADC12_B_IE6 +//! - \b ADC12_B_IE7 +//! - \b ADC12_B_IE8 +//! - \b ADC12_B_IE9 +//! - \b ADC12_B_IE10 +//! - \b ADC12_B_IE11 +//! - \b ADC12_B_IE12 +//! - \b ADC12_B_IE13 +//! - \b ADC12_B_IE14 +//! - \b ADC12_B_IE15 +//! \param interruptMask1 is the bit mask of the memory buffer and overflow +//! interrupt sources to be enabled. If the desired interrupt is not +//! available in the selection for interruptMask1, then simply pass in a +//! '0' for this value. +//! Valid values are: +//! - \b ADC12_B_IE16 +//! - \b ADC12_B_IE17 +//! - \b ADC12_B_IE18 +//! - \b ADC12_B_IE19 +//! - \b ADC12_B_IE20 +//! - \b ADC12_B_IE21 +//! - \b ADC12_B_IE22 +//! - \b ADC12_B_IE23 +//! - \b ADC12_B_IE24 +//! - \b ADC12_B_IE25 +//! - \b ADC12_B_IE26 +//! - \b ADC12_B_IE27 +//! - \b ADC12_B_IE28 +//! - \b ADC12_B_IE29 +//! - \b ADC12_B_IE30 +//! - \b ADC12_B_IE31 +//! \param interruptMask2 is the bit mask of the memory buffer and overflow +//! interrupt sources to be enabled. If the desired interrupt is not +//! available in the selection for interruptMask2, then simply pass in a +//! '0' for this value. +//! Valid values are: +//! - \b ADC12_B_INIE - Interrupt enable for a conversion in the result +//! register is either greater than the ADC12LO or lower than the +//! ADC12HI threshold. GIE bit must be set to enable the interrupt. +//! - \b ADC12_B_LOIE - Interrupt enable for the falling short of the +//! lower limit interrupt of the window comparator for the result +//! register. GIE bit must be set to enable the interrupt. +//! - \b ADC12_B_HIIE - Interrupt enable for the exceeding the upper +//! limit of the window comparator for the result register. GIE bit +//! must be set to enable the interrupt. +//! - \b ADC12_B_OVIE - Interrupt enable for a conversion that is about +//! to save to a memory buffer that has not been read out yet. GIE +//! bit must be set to enable the interrupt. +//! - \b ADC12_B_TOVIE - enable for a conversion that is about to start +//! before the previous conversion has been completed. GIE bit must +//! be set to enable the interrupt. +//! - \b ADC12_B_RDYIE - enable for the local buffered reference ready +//! signal. GIE bit must be set to enable the interrupt. +//! +//! Modified bits of \b ADC12IERx register. +//! +//! \return None +// +//***************************************************************************** +extern void ADC12_B_enableInterrupt(uint16_t baseAddress, + uint16_t interruptMask0, + uint16_t interruptMask1, + uint16_t interruptMask2); + +//***************************************************************************** +// +//! \brief Disables selected ADC12B interrupt sources. +//! +//! Disables the indicated ADC12B interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! \param baseAddress is the base address of the ADC12B module. +//! \param interruptMask0 is the bit mask of the memory buffer and overflow +//! interrupt sources to be disabled. If the desired interrupt is not +//! available in the selection for interruptMask0, then simply pass in a +//! '0' for this value. +//! Valid values are: +//! - \b ADC12_B_IE0 +//! - \b ADC12_B_IE1 +//! - \b ADC12_B_IE2 +//! - \b ADC12_B_IE3 +//! - \b ADC12_B_IE4 +//! - \b ADC12_B_IE5 +//! - \b ADC12_B_IE6 +//! - \b ADC12_B_IE7 +//! - \b ADC12_B_IE8 +//! - \b ADC12_B_IE9 +//! - \b ADC12_B_IE10 +//! - \b ADC12_B_IE11 +//! - \b ADC12_B_IE12 +//! - \b ADC12_B_IE13 +//! - \b ADC12_B_IE14 +//! - \b ADC12_B_IE15 +//! \param interruptMask1 is the bit mask of the memory buffer and overflow +//! interrupt sources to be disabled. If the desired interrupt is not +//! available in the selection for interruptMask1, then simply pass in a +//! '0' for this value. +//! Valid values are: +//! - \b ADC12_B_IE16 +//! - \b ADC12_B_IE17 +//! - \b ADC12_B_IE18 +//! - \b ADC12_B_IE19 +//! - \b ADC12_B_IE20 +//! - \b ADC12_B_IE21 +//! - \b ADC12_B_IE22 +//! - \b ADC12_B_IE23 +//! - \b ADC12_B_IE24 +//! - \b ADC12_B_IE25 +//! - \b ADC12_B_IE26 +//! - \b ADC12_B_IE27 +//! - \b ADC12_B_IE28 +//! - \b ADC12_B_IE29 +//! - \b ADC12_B_IE30 +//! - \b ADC12_B_IE31 +//! \param interruptMask2 is the bit mask of the memory buffer and overflow +//! interrupt sources to be disabled. If the desired interrupt is not +//! available in the selection for interruptMask2, then simply pass in a +//! '0' for this value. +//! Valid values are: +//! - \b ADC12_B_INIE - Interrupt enable for a conversion in the result +//! register is either greater than the ADC12LO or lower than the +//! ADC12HI threshold. GIE bit must be set to enable the interrupt. +//! - \b ADC12_B_LOIE - Interrupt enable for the falling short of the +//! lower limit interrupt of the window comparator for the result +//! register. GIE bit must be set to enable the interrupt. +//! - \b ADC12_B_HIIE - Interrupt enable for the exceeding the upper +//! limit of the window comparator for the result register. GIE bit +//! must be set to enable the interrupt. +//! - \b ADC12_B_OVIE - Interrupt enable for a conversion that is about +//! to save to a memory buffer that has not been read out yet. GIE +//! bit must be set to enable the interrupt. +//! - \b ADC12_B_TOVIE - enable for a conversion that is about to start +//! before the previous conversion has been completed. GIE bit must +//! be set to enable the interrupt. +//! - \b ADC12_B_RDYIE - enable for the local buffered reference ready +//! signal. GIE bit must be set to enable the interrupt. +//! +//! Modified bits of \b ADC12IERx register. +//! +//! \return None +// +//***************************************************************************** +extern void ADC12_B_disableInterrupt(uint16_t baseAddress, + uint16_t interruptMask0, + uint16_t interruptMask1, + uint16_t interruptMask2); + +//***************************************************************************** +// +//! \brief Clears ADC12B selected interrupt flags. +//! +//! Modified registers are ADC12IFG . +//! +//! \param baseAddress is the base address of the ADC12B module. +//! \param interruptRegisterChoice is either 0, 1, or 2, to choose the correct +//! interrupt register to update +//! \param memoryInterruptFlagMask is the bit mask of the memory buffer and +//! overflow interrupt flags to be cleared. +//! Valid values are: +//! - \b ADC12_B_IFG0 - interruptRegisterChoice = 0 +//! - \b ADC12_B_IFG1 +//! - \b ADC12_B_IFG2 +//! - \b ADC12_B_IFG3 +//! - \b ADC12_B_IFG4 +//! - \b ADC12_B_IFG5 +//! - \b ADC12_B_IFG6 +//! - \b ADC12_B_IFG7 +//! - \b ADC12_B_IFG8 +//! - \b ADC12_B_IFG9 +//! - \b ADC12_B_IFG10 +//! - \b ADC12_B_IFG11 +//! - \b ADC12_B_IFG12 +//! - \b ADC12_B_IFG13 +//! - \b ADC12_B_IFG14 +//! - \b ADC12_B_IFG15 +//! - \b ADC12_B_IFG16 - interruptRegisterChoice = 1 +//! - \b ADC12_B_IFG17 +//! - \b ADC12_B_IFG18 +//! - \b ADC12_B_IFG19 +//! - \b ADC12_B_IFG20 +//! - \b ADC12_B_IFG21 +//! - \b ADC12_B_IFG22 +//! - \b ADC12_B_IFG23 +//! - \b ADC12_B_IFG24 +//! - \b ADC12_B_IFG25 +//! - \b ADC12_B_IFG26 +//! - \b ADC12_B_IFG27 +//! - \b ADC12_B_IFG28 +//! - \b ADC12_B_IFG29 +//! - \b ADC12_B_IFG30 +//! - \b ADC12_B_IFG31 +//! - \b ADC12_B_INIFG - interruptRegisterChoice = 2 +//! - \b ADC12_B_LOIFG +//! - \b ADC12_B_HIIFG +//! - \b ADC12_B_OVIFG +//! - \b ADC12_B_TOVIFG +//! - \b ADC12_B_RDYIFG - The selected ADC12B interrupt flags are +//! cleared, so that it no longer asserts. The memory buffer +//! interrupt flags are only cleared when the memory buffer is +//! accessed. Note that the overflow interrupts do not have an +//! interrupt flag to clear; they must be accessed directly from the +//! interrupt vector. +//! +//! \return None +// +//***************************************************************************** +extern void ADC12_B_clearInterrupt(uint16_t baseAddress, + uint8_t interruptRegisterChoice, + uint16_t memoryInterruptFlagMask); + +//***************************************************************************** +// +//! \brief Returns the status of the selected memory interrupt flags. +//! +//! Returns the status of the selected memory interrupt flags. Note that the +//! overflow interrupts do not have an interrupt flag to clear; they must be +//! accessed directly from the interrupt vector. +//! +//! \param baseAddress is the base address of the ADC12B module. +//! \param interruptRegisterChoice is either 0, 1, or 2, to choose the correct +//! interrupt register to update +//! \param memoryInterruptFlagMask is the bit mask of the memory buffer and +//! overflow interrupt flags to be cleared. +//! Valid values are: +//! - \b ADC12_B_IFG0 - interruptRegisterChoice = 0 +//! - \b ADC12_B_IFG1 +//! - \b ADC12_B_IFG2 +//! - \b ADC12_B_IFG3 +//! - \b ADC12_B_IFG4 +//! - \b ADC12_B_IFG5 +//! - \b ADC12_B_IFG6 +//! - \b ADC12_B_IFG7 +//! - \b ADC12_B_IFG8 +//! - \b ADC12_B_IFG9 +//! - \b ADC12_B_IFG10 +//! - \b ADC12_B_IFG11 +//! - \b ADC12_B_IFG12 +//! - \b ADC12_B_IFG13 +//! - \b ADC12_B_IFG14 +//! - \b ADC12_B_IFG15 +//! - \b ADC12_B_IFG16 - interruptRegisterChoice = 1 +//! - \b ADC12_B_IFG17 +//! - \b ADC12_B_IFG18 +//! - \b ADC12_B_IFG19 +//! - \b ADC12_B_IFG20 +//! - \b ADC12_B_IFG21 +//! - \b ADC12_B_IFG22 +//! - \b ADC12_B_IFG23 +//! - \b ADC12_B_IFG24 +//! - \b ADC12_B_IFG25 +//! - \b ADC12_B_IFG26 +//! - \b ADC12_B_IFG27 +//! - \b ADC12_B_IFG28 +//! - \b ADC12_B_IFG29 +//! - \b ADC12_B_IFG30 +//! - \b ADC12_B_IFG31 +//! - \b ADC12_B_INIFG - interruptRegisterChoice = 2 +//! - \b ADC12_B_LOIFG +//! - \b ADC12_B_HIIFG +//! - \b ADC12_B_OVIFG +//! - \b ADC12_B_TOVIFG +//! - \b ADC12_B_RDYIFG - The selected ADC12B interrupt flags are +//! cleared, so that it no longer asserts. The memory buffer +//! interrupt flags are only cleared when the memory buffer is +//! accessed. Note that the overflow interrupts do not have an +//! interrupt flag to clear; they must be accessed directly from the +//! interrupt vector. +//! +//! \return The current interrupt flag status for the corresponding mask. +// +//***************************************************************************** +extern uint16_t ADC12_B_getInterruptStatus(uint16_t baseAddress, + uint8_t interruptRegisterChoice, + uint16_t memoryInterruptFlagMask); + +//***************************************************************************** +// +//! \brief Enables/Starts an Analog-to-Digital Conversion. +//! +//! Enables/starts the conversion process of the ADC. If the sample/hold signal +//! source chosen during initialization was ADC12OSC, then the conversion is +//! started immediately, otherwise the chosen sample/hold signal source starts +//! the conversion by a rising edge of the signal. Keep in mind when selecting +//! conversion modes, that for sequenced and/or repeated modes, to keep the +//! sample/hold-and-convert process continuing without a trigger from the +//! sample/hold signal source, the multiple samples must be enabled using the +//! ADC12_B_setupSamplingTimer() function. Note that after this function is +//! called, the ADC12_B_stopConversions() has to be called to re-initialize the +//! ADC, reconfigure a memory buffer control, enable/disable the sampling +//! timer, or to change the internal reference voltage. +//! +//! \param baseAddress is the base address of the ADC12B module. +//! \param startingMemoryBufferIndex is the memory buffer that will hold the +//! first or only conversion. +//! Valid values are: +//! - \b ADC12_B_START_AT_ADC12MEM0 [Default] +//! - \b ADC12_B_START_AT_ADC12MEM1 +//! - \b ADC12_B_START_AT_ADC12MEM2 +//! - \b ADC12_B_START_AT_ADC12MEM3 +//! - \b ADC12_B_START_AT_ADC12MEM4 +//! - \b ADC12_B_START_AT_ADC12MEM5 +//! - \b ADC12_B_START_AT_ADC12MEM6 +//! - \b ADC12_B_START_AT_ADC12MEM7 +//! - \b ADC12_B_START_AT_ADC12MEM8 +//! - \b ADC12_B_START_AT_ADC12MEM9 +//! - \b ADC12_B_START_AT_ADC12MEM10 +//! - \b ADC12_B_START_AT_ADC12MEM11 +//! - \b ADC12_B_START_AT_ADC12MEM12 +//! - \b ADC12_B_START_AT_ADC12MEM13 +//! - \b ADC12_B_START_AT_ADC12MEM14 +//! - \b ADC12_B_START_AT_ADC12MEM15 +//! - \b ADC12_B_START_AT_ADC12MEM16 +//! - \b ADC12_B_START_AT_ADC12MEM17 +//! - \b ADC12_B_START_AT_ADC12MEM18 +//! - \b ADC12_B_START_AT_ADC12MEM19 +//! - \b ADC12_B_START_AT_ADC12MEM20 +//! - \b ADC12_B_START_AT_ADC12MEM21 +//! - \b ADC12_B_START_AT_ADC12MEM22 +//! - \b ADC12_B_START_AT_ADC12MEM23 +//! - \b ADC12_B_START_AT_ADC12MEM24 +//! - \b ADC12_B_START_AT_ADC12MEM25 +//! - \b ADC12_B_START_AT_ADC12MEM26 +//! - \b ADC12_B_START_AT_ADC12MEM27 +//! - \b ADC12_B_START_AT_ADC12MEM28 +//! - \b ADC12_B_START_AT_ADC12MEM29 +//! - \b ADC12_B_START_AT_ADC12MEM30 +//! - \b ADC12_B_START_AT_ADC12MEM31 +//! \n Modified bits are \b ADC12CSTARTADDx of \b ADC12CTL1 register. +//! \param conversionSequenceModeSelect determines the ADC operating mode. +//! Valid values are: +//! - \b ADC12_B_SINGLECHANNEL [Default] - one-time conversion of a +//! single channel into a single memory buffer. +//! - \b ADC12_B_SEQOFCHANNELS - one time conversion of multiple +//! channels into the specified starting memory buffer and each +//! subsequent memory buffer up until the conversion is stored in a +//! memory buffer dedicated as the end-of-sequence by the memory's +//! control register. +//! - \b ADC12_B_REPEATED_SINGLECHANNEL - repeated conversions of one +//! channel into a single memory buffer. +//! - \b ADC12_B_REPEATED_SEQOFCHANNELS - repeated conversions of +//! multiple channels into the specified starting memory buffer and +//! each subsequent memory buffer up until the conversion is stored +//! in a memory buffer dedicated as the end-of-sequence by the +//! memory's control register. +//! \n Modified bits are \b ADC12CONSEQx of \b ADC12CTL1 register. +//! +//! Modified bits of \b ADC12CTL1 register and bits of \b ADC12CTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void ADC12_B_startConversion(uint16_t baseAddress, + uint16_t startingMemoryBufferIndex, + uint8_t conversionSequenceModeSelect); + +//***************************************************************************** +// +//! \brief Disables the ADC from converting any more signals. +//! +//! Disables the ADC from converting any more signals. If there is a conversion +//! in progress, this function can stop it immediately if the preempt parameter +//! is set as ADC12_B_PREEMPTCONVERSION, by changing the conversion mode to +//! single-channel, single-conversion and disabling conversions. If the +//! conversion mode is set as single-channel, single-conversion and this +//! function is called without preemption, then the ADC core conversion status +//! is polled until the conversion is complete before disabling conversions to +//! prevent unpredictable data. If the ADC12_B_startConversion() has been +//! called, then this function has to be called to re-initialize the ADC, +//! reconfigure a memory buffer control, enable/disable the sampling pulse +//! mode, or change the internal reference voltage. +//! +//! \param baseAddress is the base address of the ADC12B module. +//! \param preempt specifies if the current conversion should be preemptively +//! stopped before the end of the conversion. +//! Valid values are: +//! - \b ADC12_B_COMPLETECONVERSION - Allows the ADC12B to end the +//! current conversion before disabling conversions. +//! - \b ADC12_B_PREEMPTCONVERSION - Stops the ADC12B immediately, with +//! unpredictable results of the current conversion. +//! +//! Modified bits of \b ADC12CTL1 register and bits of \b ADC12CTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void ADC12_B_disableConversions(uint16_t baseAddress, + bool preempt); + +//***************************************************************************** +// +//! \brief Returns the raw contents of the specified memory buffer. +//! +//! Returns the raw contents of the specified memory buffer. The format of the +//! content depends on the read-back format of the data: if the data is in +//! signed 2's complement format then the contents in the memory buffer will be +//! left-justified with the least-significant bits as 0's, whereas if the data +//! is in unsigned format then the contents in the memory buffer will be right- +//! justified with the most-significant bits as 0's. +//! +//! \param baseAddress is the base address of the ADC12B module. +//! \param memoryBufferIndex is the specified memory buffer to read. +//! Valid values are: +//! - \b ADC12_B_MEMORY_0 +//! - \b ADC12_B_MEMORY_1 +//! - \b ADC12_B_MEMORY_2 +//! - \b ADC12_B_MEMORY_3 +//! - \b ADC12_B_MEMORY_4 +//! - \b ADC12_B_MEMORY_5 +//! - \b ADC12_B_MEMORY_6 +//! - \b ADC12_B_MEMORY_7 +//! - \b ADC12_B_MEMORY_8 +//! - \b ADC12_B_MEMORY_9 +//! - \b ADC12_B_MEMORY_10 +//! - \b ADC12_B_MEMORY_11 +//! - \b ADC12_B_MEMORY_12 +//! - \b ADC12_B_MEMORY_13 +//! - \b ADC12_B_MEMORY_14 +//! - \b ADC12_B_MEMORY_15 +//! - \b ADC12_B_MEMORY_16 +//! - \b ADC12_B_MEMORY_17 +//! - \b ADC12_B_MEMORY_18 +//! - \b ADC12_B_MEMORY_19 +//! - \b ADC12_B_MEMORY_20 +//! - \b ADC12_B_MEMORY_21 +//! - \b ADC12_B_MEMORY_22 +//! - \b ADC12_B_MEMORY_23 +//! - \b ADC12_B_MEMORY_24 +//! - \b ADC12_B_MEMORY_25 +//! - \b ADC12_B_MEMORY_26 +//! - \b ADC12_B_MEMORY_27 +//! - \b ADC12_B_MEMORY_28 +//! - \b ADC12_B_MEMORY_29 +//! - \b ADC12_B_MEMORY_30 +//! - \b ADC12_B_MEMORY_31 +//! +//! \return A signed integer of the contents of the specified memory buffer. +// +//***************************************************************************** +extern uint16_t ADC12_B_getResults(uint16_t baseAddress, + uint8_t memoryBufferIndex); + +//***************************************************************************** +// +//! \brief Use to change the resolution of the converted data. +//! +//! This function can be used to change the resolution of the converted data +//! from the default of 12-bits. +//! +//! \param baseAddress is the base address of the ADC12B module. +//! \param resolutionSelect determines the resolution of the converted data. +//! Valid values are: +//! - \b ADC12_B_RESOLUTION_8BIT +//! - \b ADC12_B_RESOLUTION_10BIT +//! - \b ADC12_B_RESOLUTION_12BIT [Default] +//! \n Modified bits are \b ADC12RESx of \b ADC12CTL2 register. +//! +//! \return None +// +//***************************************************************************** +extern void ADC12_B_setResolution(uint16_t baseAddress, + uint8_t resolutionSelect); + +//***************************************************************************** +// +//! \brief Use to invert or un-invert the sample/hold signal. +//! +//! This function can be used to invert or un-invert the sample/hold signal. +//! Note that if a conversion has been started with the startConversion() +//! function, then a call to disableConversions() is required before this +//! function may be called. +//! +//! \param baseAddress is the base address of the ADC12B module. +//! \param invertedSignal set if the sample/hold signal should be inverted +//! Valid values are: +//! - \b ADC12_B_NONINVERTEDSIGNAL [Default] - a sample-and-hold of an +//! input signal for conversion will be started on a rising edge of +//! the sample/hold signal. +//! - \b ADC12_B_INVERTEDSIGNAL - a sample-and-hold of an input signal +//! for conversion will be started on a falling edge of the +//! sample/hold signal. +//! \n Modified bits are \b ADC12ISSH of \b ADC12CTL1 register. +//! +//! \return None +// +//***************************************************************************** +extern void ADC12_B_setSampleHoldSignalInversion(uint16_t baseAddress, + uint16_t invertedSignal); + +//***************************************************************************** +// +//! \brief Use to set the read-back format of the converted data. +//! +//! Sets the format of the converted data: how it will be stored into the +//! memory buffer, and how it should be read back. The format can be set as +//! right-justified (default), which indicates that the number will be +//! unsigned, or left-justified, which indicates that the number will be signed +//! in 2's complement format. This change affects all memory buffers for +//! subsequent conversions. +//! +//! \param baseAddress is the base address of the ADC12B module. +//! \param readBackFormat is the specified format to store the conversions in +//! the memory buffer. +//! Valid values are: +//! - \b ADC12_B_UNSIGNED_BINARY [Default] +//! - \b ADC12_B_SIGNED_2SCOMPLEMENT +//! \n Modified bits are \b ADC12DF of \b ADC12CTL2 register. +//! +//! \return None +// +//***************************************************************************** +extern void ADC12_B_setDataReadBackFormat(uint16_t baseAddress, + uint8_t readBackFormat); + +//***************************************************************************** +// +//! \brief Use to set the ADC's power conservation mode if the sampling rate is +//! at 50-ksps or less. +//! +//! Sets ADC's power mode. If the user has a sampling rate greater than +//! 50-ksps, then he/she can only enable ADC12_B_REGULARPOWERMODE. If the +//! sampling rate is 50-ksps or less, the user can enable ADC12_B_LOWPOWERMODE +//! granting additional power savings. +//! +//! \param baseAddress is the base address of the ADC12B module. +//! \param powerMode is the specified maximum sampling rate. +//! Valid values are: +//! - \b ADC12_B_REGULARPOWERMODE [Default] - If sampling rate is +//! greater than 50-ksps, there is no power saving feature available. +//! - \b ADC12_B_LOWPOWERMODE - If sampling rate is less than or equal +//! to 50-ksps, select this value to save power +//! \n Modified bits are \b ADC12SR of \b ADC12CTL2 register. +//! +//! \return None +// +//***************************************************************************** +extern void ADC12_B_setAdcPowerMode(uint16_t baseAddress, + uint8_t powerMode); + +//***************************************************************************** +// +//! \brief Returns the address of the specified memory buffer for the DMA +//! module. +//! +//! Returns the address of the specified memory buffer. This can be used in +//! conjunction with the DMA to store the converted data directly to memory. +//! +//! \param baseAddress is the base address of the ADC12B module. +//! \param memoryIndex is the memory buffer to return the address of. +//! Valid values are: +//! - \b ADC12_B_MEMORY_0 +//! - \b ADC12_B_MEMORY_1 +//! - \b ADC12_B_MEMORY_2 +//! - \b ADC12_B_MEMORY_3 +//! - \b ADC12_B_MEMORY_4 +//! - \b ADC12_B_MEMORY_5 +//! - \b ADC12_B_MEMORY_6 +//! - \b ADC12_B_MEMORY_7 +//! - \b ADC12_B_MEMORY_8 +//! - \b ADC12_B_MEMORY_9 +//! - \b ADC12_B_MEMORY_10 +//! - \b ADC12_B_MEMORY_11 +//! - \b ADC12_B_MEMORY_12 +//! - \b ADC12_B_MEMORY_13 +//! - \b ADC12_B_MEMORY_14 +//! - \b ADC12_B_MEMORY_15 +//! - \b ADC12_B_MEMORY_16 +//! - \b ADC12_B_MEMORY_17 +//! - \b ADC12_B_MEMORY_18 +//! - \b ADC12_B_MEMORY_19 +//! - \b ADC12_B_MEMORY_20 +//! - \b ADC12_B_MEMORY_21 +//! - \b ADC12_B_MEMORY_22 +//! - \b ADC12_B_MEMORY_23 +//! - \b ADC12_B_MEMORY_24 +//! - \b ADC12_B_MEMORY_25 +//! - \b ADC12_B_MEMORY_26 +//! - \b ADC12_B_MEMORY_27 +//! - \b ADC12_B_MEMORY_28 +//! - \b ADC12_B_MEMORY_29 +//! - \b ADC12_B_MEMORY_30 +//! - \b ADC12_B_MEMORY_31 +//! +//! \return address of the specified memory buffer +// +//***************************************************************************** +extern uint32_t ADC12_B_getMemoryAddressForDMA(uint16_t baseAddress, + uint8_t memoryIndex); + +//***************************************************************************** +// +//! \brief Returns the busy status of the ADC12B core. +//! +//! Returns the status of the ADC core if there is a conversion currently +//! taking place. +//! +//! \param baseAddress is the base address of the ADC12B module. +//! +//! \return ADC12_B_BUSY or ADC12_B_NOTBUSY dependent if there is a conversion +//! currently taking place. +//! Return one of the following: +//! - \b ADC12_B_NOTBUSY +//! - \b ADC12_B_BUSY +//! \n indicating if a conversion is taking place +// +//***************************************************************************** +extern uint8_t ADC12_B_isBusy(uint16_t baseAddress); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_ADC12_B_H__ diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/aes256.c b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/aes256.c new file mode 100644 index 000000000..265d61b86 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/aes256.c @@ -0,0 +1,375 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// aes256.c - Driver for the aes256 Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup aes256_api aes256 +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_AES256__ +#include "aes256.h" + +#include + +uint8_t AES256_setCipherKey(uint16_t baseAddress, + const uint8_t * cipherKey, + uint16_t keyLength) +{ + uint8_t i; + uint16_t sCipherKey; + + HWREG16(baseAddress + OFS_AESACTL0) &= (~(AESKL_1 + AESKL_2)); + + switch(keyLength) + { + case AES256_KEYLENGTH_128BIT: + HWREG16(baseAddress + OFS_AESACTL0) |= AESKL__128; + break; + + case AES256_KEYLENGTH_192BIT: + HWREG16(baseAddress + OFS_AESACTL0) |= AESKL__192; + break; + + case AES256_KEYLENGTH_256BIT: + HWREG16(baseAddress + OFS_AESACTL0) |= AESKL__256; + break; + + default: + return(STATUS_FAIL); + } + + keyLength = keyLength / 8; + + for(i = 0; i < keyLength; i = i + 2) + { + sCipherKey = (uint16_t)(cipherKey[i]); + sCipherKey = sCipherKey | ((uint16_t)(cipherKey[i + 1]) << 8); + HWREG16(baseAddress + OFS_AESAKEY) = sCipherKey; + } + + // Wait until key is written + while(0x00 == (HWREG16(baseAddress + OFS_AESASTAT) & AESKEYWR)) + { + ; + } + return(STATUS_SUCCESS); +} + +void AES256_encryptData(uint16_t baseAddress, + const uint8_t * data, + uint8_t * encryptedData) +{ + uint8_t i; + uint16_t tempData = 0; + uint16_t tempVariable = 0; + + // Set module to encrypt mode + HWREG16(baseAddress + OFS_AESACTL0) &= ~AESOP_3; + + // Write data to encrypt to module + for(i = 0; i < 16; i = i + 2) + { + tempVariable = (uint16_t)(data[i]); + tempVariable = tempVariable | ((uint16_t)(data[i + 1]) << 8); + HWREG16(baseAddress + OFS_AESADIN) = tempVariable; + } + + // Key that is already written shall be used + // Encryption is initialized by setting AESKEYWR to 1 + HWREG16(baseAddress + OFS_AESASTAT) |= AESKEYWR; + + // Wait unit finished ~167 MCLK + while(AESBUSY == (HWREG16(baseAddress + OFS_AESASTAT) & AESBUSY)) + { + ; + } + + // Write encrypted data back to variable + for(i = 0; i < 16; i = i + 2) + { + tempData = HWREG16(baseAddress + OFS_AESADOUT); + *(encryptedData + i) = (uint8_t)tempData; + *(encryptedData + i + 1) = (uint8_t)(tempData >> 8); + } +} + +void AES256_decryptData(uint16_t baseAddress, + const uint8_t * data, + uint8_t * decryptedData) +{ + uint8_t i; + uint16_t tempData = 0; + uint16_t tempVariable = 0; + + // Set module to decrypt mode + HWREG16(baseAddress + OFS_AESACTL0) |= (AESOP_3); + + // Write data to decrypt to module + for(i = 0; i < 16; i = i + 2) + { + tempVariable = (uint16_t)(data[i + 1] << 8); + tempVariable = tempVariable | ((uint16_t)(data[i])); + HWREG16(baseAddress + OFS_AESADIN) = tempVariable; + } + + // Key that is already written shall be used + // Now decryption starts + HWREG16(baseAddress + OFS_AESASTAT) |= AESKEYWR; + + // Wait unit finished ~167 MCLK + while(AESBUSY == (HWREG16(baseAddress + OFS_AESASTAT) & AESBUSY)) + { + ; + } + + // Write encrypted data back to variable + for(i = 0; i < 16; i = i + 2) + { + tempData = HWREG16(baseAddress + OFS_AESADOUT); + *(decryptedData + i) = (uint8_t)tempData; + *(decryptedData + i + 1) = (uint8_t)(tempData >> 8); + } +} + +uint8_t AES256_setDecipherKey(uint16_t baseAddress, + const uint8_t * cipherKey, + uint16_t keyLength) +{ + uint8_t i; + uint16_t tempVariable = 0; + + // Set module to decrypt mode + HWREG16(baseAddress + OFS_AESACTL0) &= ~(AESOP0); + HWREG16(baseAddress + OFS_AESACTL0) |= AESOP1; + + switch(keyLength) + { + case AES256_KEYLENGTH_128BIT: + HWREG16(baseAddress + OFS_AESACTL0) |= AESKL__128; + break; + + case AES256_KEYLENGTH_192BIT: + HWREG16(baseAddress + OFS_AESACTL0) |= AESKL__192; + break; + + case AES256_KEYLENGTH_256BIT: + HWREG16(baseAddress + OFS_AESACTL0) |= AESKL__256; + break; + + default: + return(STATUS_FAIL); + } + + keyLength = keyLength / 8; + + // Write cipher key to key register + for(i = 0; i < keyLength; i = i + 2) + { + tempVariable = (uint16_t)(cipherKey[i]); + tempVariable = tempVariable | ((uint16_t)(cipherKey[i + 1]) << 8); + HWREG16(baseAddress + OFS_AESAKEY) = tempVariable; + } + + // Wait until key is processed ~52 MCLK + while((HWREG16(baseAddress + OFS_AESASTAT) & AESBUSY) == AESBUSY) + { + ; + } + + return(STATUS_SUCCESS); +} + +void AES256_clearInterrupt(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_AESACTL0) &= ~AESRDYIFG; +} + +uint32_t AES256_getInterruptStatus(uint16_t baseAddress) +{ + return ((HWREG16(baseAddress + OFS_AESACTL0) & AESRDYIFG) << 0x04); +} + +void AES256_enableInterrupt(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_AESACTL0) |= AESRDYIE; +} + +void AES256_disableInterrupt(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_AESACTL0) &= ~AESRDYIE; +} + +void AES256_reset(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_AESACTL0) |= AESSWRST; +} + +void AES256_startEncryptData(uint16_t baseAddress, + const uint8_t * data) +{ + uint8_t i; + uint16_t tempVariable = 0; + + // Set module to encrypt mode + HWREG16(baseAddress + OFS_AESACTL0) &= ~AESOP_3; + + // Write data to encrypt to module + for(i = 0; i < 16; i = i + 2) + { + tempVariable = (uint16_t)(data[i]); + tempVariable = tempVariable | ((uint16_t)(data[i + 1 ]) << 8); + HWREG16(baseAddress + OFS_AESADIN) = tempVariable; + } + + // Key that is already written shall be used + // Encryption is initialized by setting AESKEYWR to 1 + HWREG16(baseAddress + OFS_AESASTAT) |= AESKEYWR; +} + +void AES256_startDecryptData(uint16_t baseAddress, + const uint8_t * data) +{ + uint8_t i; + uint16_t tempVariable = 0; + + // Set module to decrypt mode + HWREG16(baseAddress + OFS_AESACTL0) |= (AESOP_3); + + // Write data to decrypt to module + for(i = 0; i < 16; i = i + 2) + { + tempVariable = (uint16_t)(data[i + 1] << 8); + tempVariable = tempVariable | ((uint16_t)(data[i])); + HWREG16(baseAddress + OFS_AESADIN) = tempVariable; + } + + // Key that is already written shall be used + // Now decryption starts + HWREG16(baseAddress + OFS_AESASTAT) |= AESKEYWR; +} + +uint8_t AES256_startSetDecipherKey(uint16_t baseAddress, + const uint8_t * cipherKey, + uint16_t keyLength) +{ + uint8_t i; + uint16_t tempVariable = 0; + + HWREG16(baseAddress + OFS_AESACTL0) &= ~(AESOP0); + HWREG16(baseAddress + OFS_AESACTL0) |= AESOP1; + + switch(keyLength) + { + case AES256_KEYLENGTH_128BIT: + HWREG16(baseAddress + OFS_AESACTL0) |= AESKL__128; + break; + + case AES256_KEYLENGTH_192BIT: + HWREG16(baseAddress + OFS_AESACTL0) |= AESKL__192; + break; + + case AES256_KEYLENGTH_256BIT: + HWREG16(baseAddress + OFS_AESACTL0) |= AESKL__256; + break; + + default: + return(STATUS_FAIL); + } + + keyLength = keyLength / 8; + + // Write cipher key to key register + for(i = 0; i < keyLength; i = i + 2) + { + tempVariable = (uint16_t)(cipherKey[i]); + tempVariable = tempVariable | ((uint16_t)(cipherKey[i + 1]) << 8); + HWREG16(baseAddress + OFS_AESAKEY) = tempVariable; + } + + return(STATUS_SUCCESS); +} + +uint8_t AES256_getDataOut(uint16_t baseAddress, + uint8_t *outputData) +{ + uint8_t i; + uint16_t tempData = 0; + + // If module is busy, exit and return failure + if(AESBUSY == (HWREG16(baseAddress + OFS_AESASTAT) & AESBUSY)) + { + return(STATUS_FAIL); + } + + // Write encrypted data back to variable + for(i = 0; i < 16; i = i + 2) + { + tempData = HWREG16(baseAddress + OFS_AESADOUT); + *(outputData + i) = (uint8_t)tempData; + *(outputData + i + 1) = (uint8_t)(tempData >> 8); + } + + return(STATUS_SUCCESS); +} + +uint16_t AES256_isBusy(uint16_t baseAddress) +{ + return (HWREG16(baseAddress + OFS_AESASTAT) & AESBUSY); +} + +void AES256_clearErrorFlag(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_AESACTL0) &= ~AESERRFG; +} + +uint32_t AES256_getErrorFlagStatus(uint16_t baseAddress) +{ + return (HWREG16(baseAddress + OFS_AESACTL0) & AESERRFG); +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for aes256_api +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/aes256.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/aes256.h new file mode 100644 index 000000000..4a89cf055 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/aes256.h @@ -0,0 +1,418 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// aes256.h - Driver for the AES256 Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_AES256_H__ +#define __MSP430WARE_AES256_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_AES256__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the keyLength parameter for +// functions: AES256_setCipherKey(), AES256_setDecipherKey(), and +// AES256_startSetDecipherKey(). +// +//***************************************************************************** +#define AES256_KEYLENGTH_128BIT 128 +#define AES256_KEYLENGTH_192BIT 192 +#define AES256_KEYLENGTH_256BIT 256 + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the AES256_getErrorFlagStatus() function. +// +//***************************************************************************** +#define AES256_ERROR_OCCURRED AESERRFG +#define AES256_NO_ERROR 0x00 + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the AES256_isBusy() function. +// +//***************************************************************************** +#define AES256_BUSY AESBUSY +#define AES256_NOT_BUSY 0x00 + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the AES256_getInterruptStatus() function. +// +//***************************************************************************** +#define AES256_READY_INTERRUPT AESRDYIE +#define AES256_NOTREADY_INTERRUPT 0x00 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Loads a 128, 192 or 256 bit cipher key to AES256 module. +//! +//! This function loads a 128, 192 or 256 bit cipher key to AES256 module. +//! Requires both a key as well as the length of the key provided. Acceptable +//! key lengths are AES256_KEYLENGTH_128BIT, AES256_KEYLENGTH_192BIT, or +//! AES256_KEYLENGTH_256BIT +//! +//! \param baseAddress is the base address of the AES256 module. +//! \param cipherKey is a pointer to an uint8_t array with a length of 16 bytes +//! that contains a 128 bit cipher key. +//! \param keyLength is the length of the key. +//! Valid values are: +//! - \b AES256_KEYLENGTH_128BIT +//! - \b AES256_KEYLENGTH_192BIT +//! - \b AES256_KEYLENGTH_256BIT +//! +//! \return STATUS_SUCCESS or STATUS_FAIL of key loading +// +//***************************************************************************** +extern uint8_t AES256_setCipherKey(uint16_t baseAddress, + const uint8_t *cipherKey, + uint16_t keyLength); + +//***************************************************************************** +// +//! \brief Encrypts a block of data using the AES256 module. +//! +//! The cipher key that is used for encryption should be loaded in advance by +//! using function AES256_setCipherKey() +//! +//! \param baseAddress is the base address of the AES256 module. +//! \param data is a pointer to an uint8_t array with a length of 16 bytes that +//! contains data to be encrypted. +//! \param encryptedData is a pointer to an uint8_t array with a length of 16 +//! bytes in that the encrypted data will be written. +//! +//! \return None +// +//***************************************************************************** +extern void AES256_encryptData(uint16_t baseAddress, + const uint8_t *data, + uint8_t *encryptedData); + +//***************************************************************************** +// +//! \brief Decrypts a block of data using the AES256 module. +//! +//! This function requires a pregenerated decryption key. A key can be loaded +//! and pregenerated by using function AES256_setDecipherKey() or +//! AES256_startSetDecipherKey(). The decryption takes 167 MCLK. +//! +//! \param baseAddress is the base address of the AES256 module. +//! \param data is a pointer to an uint8_t array with a length of 16 bytes that +//! contains encrypted data to be decrypted. +//! \param decryptedData is a pointer to an uint8_t array with a length of 16 +//! bytes in that the decrypted data will be written. +//! +//! \return None +// +//***************************************************************************** +extern void AES256_decryptData(uint16_t baseAddress, + const uint8_t *data, + uint8_t *decryptedData); + +//***************************************************************************** +// +//! \brief Sets the decipher key. +//! +//! The API AES256_startSetDecipherKey or AES256_setDecipherKey must be invoked +//! before invoking AES256_startDecryptData. +//! +//! \param baseAddress is the base address of the AES256 module. +//! \param cipherKey is a pointer to an uint8_t array with a length of 16 bytes +//! that contains a 128 bit cipher key. +//! \param keyLength is the length of the key. +//! Valid values are: +//! - \b AES256_KEYLENGTH_128BIT +//! - \b AES256_KEYLENGTH_192BIT +//! - \b AES256_KEYLENGTH_256BIT +//! +//! \return STATUS_SUCCESS or STATUS_FAIL of key loading +// +//***************************************************************************** +extern uint8_t AES256_setDecipherKey(uint16_t baseAddress, + const uint8_t *cipherKey, + uint16_t keyLength); + +//***************************************************************************** +// +//! \brief Clears the AES256 ready interrupt flag. +//! +//! This function clears the AES256 ready interrupt flag. This flag is +//! automatically cleared when AES256ADOUT is read, or when AES256AKEY or +//! AES256ADIN is written. This function should be used when the flag needs to +//! be reset and it has not been automatically cleared by one of the previous +//! actions. +//! +//! \param baseAddress is the base address of the AES256 module. +//! +//! Modified bits are \b AESRDYIFG of \b AESACTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void AES256_clearInterrupt(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Gets the AES256 ready interrupt flag status. +//! +//! This function checks the AES256 ready interrupt flag. This flag is +//! automatically cleared when AES256ADOUT is read, or when AES256AKEY or +//! AES256ADIN is written. This function can be used to confirm that this has +//! been done. +//! +//! \param baseAddress is the base address of the AES256 module. +//! +//! \return One of the following: +//! - \b AES256_READY_INTERRUPT +//! - \b AES256_NOTREADY_INTERRUPT +//! \n indicating the status of the AES256 ready status +// +//***************************************************************************** +extern uint32_t AES256_getInterruptStatus(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Enables AES256 ready interrupt. +//! +//! Enables AES256 ready interrupt. This interrupt is reset by a PUC, but not +//! reset by AES256_reset. +//! +//! \param baseAddress is the base address of the AES256 module. +//! +//! Modified bits are \b AESRDYIE of \b AESACTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void AES256_enableInterrupt(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Disables AES256 ready interrupt. +//! +//! Disables AES256 ready interrupt. This interrupt is reset by a PUC, but not +//! reset by AES256_reset. +//! +//! \param baseAddress is the base address of the AES256 module. +//! +//! Modified bits are \b AESRDYIE of \b AESACTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void AES256_disableInterrupt(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Resets AES256 Module immediately. +//! +//! This function performs a software reset on the AES256 Module, note that +//! this does not affect the AES256 ready interrupt. +//! +//! \param baseAddress is the base address of the AES256 module. +//! +//! Modified bits are \b AESSWRST of \b AESACTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void AES256_reset(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Starts an encryption process on the AES256 module. +//! +//! The cipher key that is used for decryption should be loaded in advance by +//! using function AES256_setCipherKey(). This is a non-blocking equivalent of +//! AES256_encryptData(). It is recommended to use the interrupt functionality +//! to check for procedure completion then use the AES256_getDataOut() API to +//! retrieve the encrypted data. +//! +//! \param baseAddress is the base address of the AES256 module. +//! \param data is a pointer to an uint8_t array with a length of 16 bytes that +//! contains data to be encrypted. +//! +//! \return None +// +//***************************************************************************** +extern void AES256_startEncryptData(uint16_t baseAddress, + const uint8_t *data); + +//***************************************************************************** +// +//! \brief Decrypts a block of data using the AES256 module. +//! +//! This is the non-blocking equivalent of AES256_decryptData(). This function +//! requires a pregenerated decryption key. A key can be loaded and +//! pregenerated by using function AES256_setDecipherKey() or +//! AES256_startSetDecipherKey(). The decryption takes 167 MCLK. It is +//! recommended to use interrupt to check for procedure completion then use the +//! AES256_getDataOut() API to retrieve the decrypted data. +//! +//! \param baseAddress is the base address of the AES256 module. +//! \param data is a pointer to an uint8_t array with a length of 16 bytes that +//! contains encrypted data to be decrypted. +//! +//! \return None +// +//***************************************************************************** +extern void AES256_startDecryptData(uint16_t baseAddress, + const uint8_t *data); + +//***************************************************************************** +// +//! \brief Sets the decipher key +//! +//! The API AES256_startSetDecipherKey() or AES256_setDecipherKey() must be +//! invoked before invoking AES256_startDecryptData. +//! +//! \param baseAddress is the base address of the AES256 module. +//! \param cipherKey is a pointer to an uint8_t array with a length of 16 bytes +//! that contains a 128 bit cipher key. +//! \param keyLength is the length of the key. +//! Valid values are: +//! - \b AES256_KEYLENGTH_128BIT +//! - \b AES256_KEYLENGTH_192BIT +//! - \b AES256_KEYLENGTH_256BIT +//! +//! \return STATUS_SUCCESS or STATUS_FAIL of key loading +// +//***************************************************************************** +extern uint8_t AES256_startSetDecipherKey(uint16_t baseAddress, + const uint8_t *cipherKey, + uint16_t keyLength); + +//***************************************************************************** +// +//! \brief Reads back the output data from AES256 module. +//! +//! This function is meant to use after an encryption or decryption process +//! that was started and finished by initiating an interrupt by use of +//! AES256_startEncryptData or AES256_startDecryptData functions. +//! +//! \param baseAddress is the base address of the AES256 module. +//! \param outputData is a pointer to an uint8_t array with a length of 16 +//! bytes in that the data will be written. +//! +//! \return STATUS_SUCCESS if data is valid, otherwise STATUS_FAIL +// +//***************************************************************************** +extern uint8_t AES256_getDataOut(uint16_t baseAddress, + uint8_t *outputData); + +//***************************************************************************** +// +//! \brief Gets the AES256 module busy status. +//! +//! Gets the AES256 module busy status. If a key or data are written while the +//! AES256 module is busy, an error flag will be thrown. +//! +//! \param baseAddress is the base address of the AES256 module. +//! +//! \return One of the following: +//! - \b AES256_BUSY +//! - \b AES256_NOT_BUSY +//! \n indicating if the AES256 module is busy +// +//***************************************************************************** +extern uint16_t AES256_isBusy(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Clears the AES256 error flag. +//! +//! Clears the AES256 error flag that results from a key or data being written +//! while the AES256 module is busy. +//! +//! \param baseAddress is the base address of the AES256 module. +//! +//! Modified bits are \b AESERRFG of \b AESACTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void AES256_clearErrorFlag(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Gets the AES256 error flag status. +//! +//! Checks the AES256 error flag that results from a key or data being written +//! while the AES256 module is busy. If the flag is set, it needs to be cleared +//! using AES256_clearErrorFlag. +//! +//! \param baseAddress is the base address of the AES256 module. +//! +//! \return One of the following: +//! - \b AES256_ERROR_OCCURRED +//! - \b AES256_NO_ERROR +//! \n indicating the error flag status +// +//***************************************************************************** +extern uint32_t AES256_getErrorFlagStatus(uint16_t baseAddress); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_AES256_H__ diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/comp_e.c b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/comp_e.c new file mode 100644 index 000000000..76e416cbe --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/comp_e.c @@ -0,0 +1,293 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// comp_e.c - Driver for the comp_e Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup comp_e_api comp_e +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_COMP_E__ +#include "comp_e.h" + +#include + +static uint16_t __getRegisterSettingForInput(uint32_t input) +{ + switch(input) + { + case COMP_E_INPUT0: + return(CEIPSEL_0); + case COMP_E_INPUT1: + return(CEIPSEL_1); + case COMP_E_INPUT2: + return(CEIPSEL_2); + case COMP_E_INPUT3: + return(CEIPSEL_3); + case COMP_E_INPUT4: + return(CEIPSEL_4); + case COMP_E_INPUT5: + return(CEIPSEL_5); + case COMP_E_INPUT6: + return(CEIPSEL_6); + case COMP_E_INPUT7: + return(CEIPSEL_7); + case COMP_E_INPUT8: + return(CEIPSEL_8); + case COMP_E_INPUT9: + return(CEIPSEL_9); + case COMP_E_INPUT10: + return(CEIPSEL_10); + case COMP_E_INPUT11: + return(CEIPSEL_11); + case COMP_E_INPUT12: + return(CEIPSEL_12); + case COMP_E_INPUT13: + return(CEIPSEL_13); + case COMP_E_INPUT14: + return(CEIPSEL_14); + case COMP_E_INPUT15: + return(CEIPSEL_15); + case COMP_E_VREF: + return(COMP_E_VREF); + default: + return(0x11); + } +} + +bool Comp_E_init(uint16_t baseAddress, + Comp_E_initParam *param) +{ + uint8_t positiveTerminalInput = __getRegisterSettingForInput( + param->posTerminalInput); + uint8_t negativeTerminalInput = __getRegisterSettingForInput( + param->negTerminalInput); + bool retVal = STATUS_SUCCESS; + + //Reset COMPE Control 1 & Interrupt Registers for initialization (OFS_CECTL3 + //is not reset because it controls the input buffers of the analog signals + //and may cause parasitic effects if an analog signal is still attached and + //the buffer is re-enabled + HWREG16(baseAddress + OFS_CECTL0) &= 0x0000; + HWREG16(baseAddress + OFS_CEINT) &= 0x0000; + + //Set the Positive Terminal + if(COMP_E_VREF != positiveTerminalInput) + { + //Enable Positive Terminal Input Mux and Set it to the appropriate input + HWREG16(baseAddress + OFS_CECTL0) |= CEIPEN + positiveTerminalInput; + + //Disable the input buffer + HWREG16(baseAddress + OFS_CECTL3) |= (1 << positiveTerminalInput); + } + else + { + //Reset and Set COMPE Control 2 Register + HWREG16(baseAddress + OFS_CECTL2) &= ~(CERSEL); //Set Vref to go to (+)terminal + } + + //Set the Negative Terminal + if(COMP_E_VREF != negativeTerminalInput) + { + //Enable Negative Terminal Input Mux and Set it to the appropriate input + HWREG16(baseAddress + + OFS_CECTL0) |= CEIMEN + (negativeTerminalInput << 8); + + //Disable the input buffer + HWREG16(baseAddress + OFS_CECTL3) |= (1 << negativeTerminalInput); + } + else + { + //Reset and Set COMPE Control 2 Register + HWREG16(baseAddress + OFS_CECTL2) |= CERSEL; //Set Vref to go to (-) terminal + } + + //Reset and Set COMPE Control 1 Register + HWREG16(baseAddress + OFS_CECTL1) = + +param->outputFilterEnableAndDelayLevel //Set the filter enable bit and delay + + param->invertedOutputPolarity; //Set the polarity of the output + + return (retVal); +} + +void Comp_E_setReferenceVoltage(uint16_t baseAddress, + uint16_t supplyVoltageReferenceBase, + uint16_t lowerLimitSupplyVoltageFractionOf32, + uint16_t upperLimitSupplyVoltageFractionOf32) +{ + HWREG16(baseAddress + OFS_CECTL1) &= ~(CEMRVS); //Set to VREF0 + + //Reset COMPE Control 2 Bits (Except for CERSEL which is set in Comp_Init() ) + HWREG16(baseAddress + OFS_CECTL2) &= CERSEL; + + //Set Voltage Source (Vcc | Vref, resistor ladder or not) + if(COMP_E_REFERENCE_AMPLIFIER_DISABLED == supplyVoltageReferenceBase) + { + HWREG16(baseAddress + OFS_CECTL2) |= CERS_1; //Vcc with resistor ladder + } + else if(lowerLimitSupplyVoltageFractionOf32 == 32) + { + //If the lower limit is 32, then the upper limit has to be 32 due to the + //assertion that upper must be >= to the lower limit. If the numerator is + //equal to 32, then the equation would be 32/32 == 1, therefore no resistor + //ladder is needed + HWREG16(baseAddress + OFS_CECTL2) |= CERS_3; //Vref, no resistor ladder + } + else + { + HWREG16(baseAddress + OFS_CECTL2) |= CERS_2; //Vref with resistor ladder + } + + //Set COMPE Control 2 Register + HWREG16(baseAddress + OFS_CECTL2) |= + supplyVoltageReferenceBase //Set Supply Voltage Base + + ((upperLimitSupplyVoltageFractionOf32 - 1) << 8) //Set Supply Voltage Num. + + (lowerLimitSupplyVoltageFractionOf32 - 1); +} + +void Comp_E_setReferenceAccuracy(uint16_t baseAddress, + uint16_t referenceAccuracy) +{ + HWREG16(baseAddress + OFS_CECTL2) &= ~(CEREFACC); + HWREG16(baseAddress + OFS_CECTL2) |= referenceAccuracy; +} + +void Comp_E_setPowerMode(uint16_t baseAddress, + uint16_t powerMode) +{ + HWREG16(baseAddress + + OFS_CECTL1) &= ~(COMP_E_NORMAL_MODE | COMP_E_ULTRA_LOW_POWER_MODE); + HWREG16(baseAddress + OFS_CECTL1) |= powerMode; +} + +void Comp_E_enableInterrupt(uint16_t baseAddress, + uint16_t interruptMask) +{ + //Set the Interrupt enable bit + HWREG16(baseAddress + OFS_CEINT) |= interruptMask; +} + +void Comp_E_disableInterrupt(uint16_t baseAddress, + uint16_t interruptMask) +{ + HWREG16(baseAddress + OFS_CEINT) &= ~(interruptMask); +} + +void Comp_E_clearInterrupt(uint16_t baseAddress, + uint16_t interruptFlagMask) +{ + HWREG16(baseAddress + OFS_CEINT) &= ~(interruptFlagMask); +} + +uint8_t Comp_E_getInterruptStatus(uint16_t baseAddress, + uint16_t interruptFlagMask) +{ + return (HWREG16(baseAddress + OFS_CEINT) & interruptFlagMask); +} + +void Comp_E_setInterruptEdgeDirection(uint16_t baseAddress, + uint16_t edgeDirection) +{ + //Set the edge direction that will trigger an interrupt + if(COMP_E_RISINGEDGE == edgeDirection) + { + HWREG16(baseAddress + OFS_CECTL1) |= CEIES; + } + else if(COMP_E_FALLINGEDGE == edgeDirection) + { + HWREG16(baseAddress + OFS_CECTL1) &= ~(CEIES); + } +} + +void Comp_E_toggleInterruptEdgeDirection(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_CECTL1) ^= CEIES; +} + +void Comp_E_enable(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_CECTL1) |= CEON; +} + +void Comp_E_disable(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_CECTL1) &= ~(CEON); +} + +void Comp_E_shortInputs(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_CECTL1) |= CESHORT; +} + +void Comp_E_unshortInputs(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_CECTL1) &= ~(CESHORT); +} + +void Comp_E_disableInputBuffer(uint16_t baseAddress, + uint16_t inputPort) +{ + HWREG16(baseAddress + OFS_CECTL3) |= (inputPort); +} + +void Comp_E_enableInputBuffer(uint16_t baseAddress, + uint16_t inputPort) +{ + HWREG16(baseAddress + OFS_CECTL3) &= ~(inputPort); +} + +void Comp_E_swapIO(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_CECTL1) ^= CEEX; //Toggle CEEX bit +} + +uint16_t Comp_E_outputValue(uint16_t baseAddress) +{ + return (HWREG16(baseAddress + OFS_CECTL1) & CEOUT); +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for comp_e_api +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/comp_e.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/comp_e.h new file mode 100644 index 000000000..4e8185097 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/comp_e.h @@ -0,0 +1,664 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// comp_e.h - Driver for the COMP_E Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_COMP_E_H__ +#define __MSP430WARE_COMP_E_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_COMP_E__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "inc/hw_regaccess.h" +//***************************************************************************** +// +//! \brief Used in the Comp_E_init() function as the param parameter. +// +//***************************************************************************** +typedef struct Comp_E_initParam +{ + //! Selects the input to the positive terminal. + //! \n Valid values are: + //! - \b COMP_E_INPUT0 [Default] + //! - \b COMP_E_INPUT1 + //! - \b COMP_E_INPUT2 + //! - \b COMP_E_INPUT3 + //! - \b COMP_E_INPUT4 + //! - \b COMP_E_INPUT5 + //! - \b COMP_E_INPUT6 + //! - \b COMP_E_INPUT7 + //! - \b COMP_E_INPUT8 + //! - \b COMP_E_INPUT9 + //! - \b COMP_E_INPUT10 + //! - \b COMP_E_INPUT11 + //! - \b COMP_E_INPUT12 + //! - \b COMP_E_INPUT13 + //! - \b COMP_E_INPUT14 + //! - \b COMP_E_INPUT15 + //! - \b COMP_E_VREF + uint16_t posTerminalInput; + //! Selects the input to the negative terminal. + //! \n Valid values are: + //! - \b COMP_E_INPUT0 [Default] + //! - \b COMP_E_INPUT1 + //! - \b COMP_E_INPUT2 + //! - \b COMP_E_INPUT3 + //! - \b COMP_E_INPUT4 + //! - \b COMP_E_INPUT5 + //! - \b COMP_E_INPUT6 + //! - \b COMP_E_INPUT7 + //! - \b COMP_E_INPUT8 + //! - \b COMP_E_INPUT9 + //! - \b COMP_E_INPUT10 + //! - \b COMP_E_INPUT11 + //! - \b COMP_E_INPUT12 + //! - \b COMP_E_INPUT13 + //! - \b COMP_E_INPUT14 + //! - \b COMP_E_INPUT15 + //! - \b COMP_E_VREF + uint16_t negTerminalInput; + //! Controls the output filter delay state, which is either off or enabled + //! with a specified delay level. This parameter is device specific and + //! delay levels should be found in the device's datasheet. + //! \n Valid values are: + //! - \b COMP_E_FILTEROUTPUT_OFF [Default] + //! - \b COMP_E_FILTEROUTPUT_DLYLVL1 + //! - \b COMP_E_FILTEROUTPUT_DLYLVL2 + //! - \b COMP_E_FILTEROUTPUT_DLYLVL3 + //! - \b COMP_E_FILTEROUTPUT_DLYLVL4 + uint8_t outputFilterEnableAndDelayLevel; + //! Controls if the output will be inverted or not + //! \n Valid values are: + //! - \b COMP_E_NORMALOUTPUTPOLARITY + //! - \b COMP_E_INVERTEDOUTPUTPOLARITY + uint16_t invertedOutputPolarity; +} Comp_E_initParam; + +//***************************************************************************** +// +// The following are values that can be passed to the +// outputFilterEnableAndDelayLevel parameter for functions: Comp_E_init(); the +// param parameter for functions: Comp_E_init(). +// +//***************************************************************************** +#define COMP_E_FILTEROUTPUT_OFF 0x00 +#define COMP_E_FILTEROUTPUT_DLYLVL1 (CEF + CEFDLY_0) +#define COMP_E_FILTEROUTPUT_DLYLVL2 (CEF + CEFDLY_1) +#define COMP_E_FILTEROUTPUT_DLYLVL3 (CEF + CEFDLY_2) +#define COMP_E_FILTEROUTPUT_DLYLVL4 (CEF + CEFDLY_3) + +//***************************************************************************** +// +// The following are values that can be passed to the posTerminalInput +// parameter for functions: Comp_E_init(); the inputPort parameter for +// functions: Comp_E_disableInputBuffer(), and Comp_E_enableInputBuffer(); the +// param parameter for functions: Comp_E_init(), and Comp_E_init(); the +// negTerminalInput parameter for functions: Comp_E_init(). +// +//***************************************************************************** +#define COMP_E_INPUT0 (0x01) +#define COMP_E_INPUT1 (0x02) +#define COMP_E_INPUT2 (0x04) +#define COMP_E_INPUT3 (0x08) +#define COMP_E_INPUT4 (0x10) +#define COMP_E_INPUT5 (0x20) +#define COMP_E_INPUT6 (0x40) +#define COMP_E_INPUT7 (0x80) +#define COMP_E_INPUT8 (0x100) +#define COMP_E_INPUT9 (0x200) +#define COMP_E_INPUT10 (0x400) +#define COMP_E_INPUT11 (0x800) +#define COMP_E_INPUT12 (0x1000) +#define COMP_E_INPUT13 (0x2000) +#define COMP_E_INPUT14 (0x4000) +#define COMP_E_INPUT15 (0x8000) +#define COMP_E_VREF (0x9F) + +//***************************************************************************** +// +// The following are values that can be passed to the invertedOutputPolarity +// parameter for functions: Comp_E_init(); the param parameter for functions: +// Comp_E_init(). +// +//***************************************************************************** +#define COMP_E_NORMALOUTPUTPOLARITY (!(CEOUTPOL)) +#define COMP_E_INVERTEDOUTPUTPOLARITY (CEOUTPOL) + +//***************************************************************************** +// +// The following are values that can be passed to the +// supplyVoltageReferenceBase parameter for functions: +// Comp_E_setReferenceVoltage(). +// +//***************************************************************************** +#define COMP_E_REFERENCE_AMPLIFIER_DISABLED (CEREFL_0) +#define COMP_E_VREFBASE1_2V (CEREFL_1) +#define COMP_E_VREFBASE2_0V (CEREFL_2) +#define COMP_E_VREFBASE2_5V (CEREFL_3) + +//***************************************************************************** +// +// The following are values that can be passed to the referenceAccuracy +// parameter for functions: Comp_E_setReferenceAccuracy(). +// +//***************************************************************************** +#define COMP_E_ACCURACY_STATIC (!CEREFACC) +#define COMP_E_ACCURACY_CLOCKED (CEREFACC) + +//***************************************************************************** +// +// The following are values that can be passed to the powerMode parameter for +// functions: Comp_E_setPowerMode(). +// +//***************************************************************************** +#define COMP_E_HIGH_SPEED_MODE (CEPWRMD_0) +#define COMP_E_NORMAL_MODE (CEPWRMD_1) +#define COMP_E_ULTRA_LOW_POWER_MODE (CEPWRMD_2) + +//***************************************************************************** +// +// The following are values that can be passed to the interruptMask parameter +// for functions: Comp_E_enableInterrupt(), and Comp_E_disableInterrupt(). +// +//***************************************************************************** +#define COMP_E_OUTPUT_INTERRUPT (CEIE) +#define COMP_E_INVERTED_POLARITY_INTERRUPT (CEIIE) +#define COMP_E_READY_INTERRUPT (CERDYIE) + +//***************************************************************************** +// +// The following are values that can be passed to the interruptFlagMask +// parameter for functions: Comp_E_clearInterrupt(), and +// Comp_E_getInterruptStatus() as well as returned by the +// Comp_E_getInterruptStatus() function. +// +//***************************************************************************** +#define COMP_E_OUTPUT_INTERRUPT_FLAG (CEIFG) +#define COMP_E_INTERRUPT_FLAG_INVERTED_POLARITY (CEIIFG) +#define COMP_E_INTERRUPT_FLAG_READY (CERDYIFG) + +//***************************************************************************** +// +// The following are values that can be passed to the edgeDirection parameter +// for functions: Comp_E_setInterruptEdgeDirection(). +// +//***************************************************************************** +#define COMP_E_FALLINGEDGE (!(CEIES)) +#define COMP_E_RISINGEDGE (CEIES) + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the Comp_E_outputValue() function. +// +//***************************************************************************** +#define COMP_E_LOW (0x0) +#define COMP_E_HIGH (CEOUT) + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Initializes the Comp_E Module. +//! +//! Upon successful initialization of the Comp_E module, this function will +//! have reset all necessary register bits and set the given options in the +//! registers. To actually use the Comp_E module, the Comp_E_enable() function +//! must be explicitly called before use. If a Reference Voltage is set to a +//! terminal, the Voltage should be set using the setReferenceVoltage() +//! function. +//! +//! \param baseAddress is the base address of the COMP_E module. +//! \param param is the pointer to struct for initialization. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the initialization process +// +//***************************************************************************** +extern bool Comp_E_init(uint16_t baseAddress, + Comp_E_initParam *param); + +//***************************************************************************** +// +//! \brief Generates a Reference Voltage to the terminal selected during +//! initialization. +//! +//! Use this function to generate a voltage to serve as a reference to the +//! terminal selected at initialization. The voltage is determined by the +//! equation: Vbase * (Numerator / 32). If the upper and lower limit voltage +//! numerators are equal, then a static reference is defined, whereas they are +//! different then a hysteresis effect is generated. +//! +//! \param baseAddress is the base address of the COMP_E module. +//! \param supplyVoltageReferenceBase decides the source and max amount of +//! Voltage that can be used as a reference. +//! Valid values are: +//! - \b COMP_E_REFERENCE_AMPLIFIER_DISABLED +//! - \b COMP_E_VREFBASE1_2V +//! - \b COMP_E_VREFBASE2_0V +//! - \b COMP_E_VREFBASE2_5V +//! \n Modified bits are \b CEREFL of \b CECTL2 register. +//! \param lowerLimitSupplyVoltageFractionOf32 is the numerator of the equation +//! to generate the reference voltage for the lower limit reference +//! voltage. +//! \n Modified bits are \b CEREF0 of \b CECTL2 register. +//! \param upperLimitSupplyVoltageFractionOf32 is the numerator of the equation +//! to generate the reference voltage for the upper limit reference +//! voltage. +//! \n Modified bits are \b CEREF1 of \b CECTL2 register. +//! +//! \return None +// +//***************************************************************************** +extern void Comp_E_setReferenceVoltage(uint16_t baseAddress, + uint16_t supplyVoltageReferenceBase, + uint16_t lowerLimitSupplyVoltageFractionOf32, + uint16_t upperLimitSupplyVoltageFractionOf32); + +//***************************************************************************** +// +//! \brief Sets the reference accuracy +//! +//! The reference accuracy is set to the desired setting. Clocked is better for +//! low power operations but has a lower accuracy. +//! +//! \param baseAddress is the base address of the COMP_E module. +//! \param referenceAccuracy is the reference accuracy setting of the COMP_E. +//! Valid values are: +//! - \b COMP_E_ACCURACY_STATIC +//! - \b COMP_E_ACCURACY_CLOCKED - for low power / low accuracy +//! \n Modified bits are \b CEREFACC of \b CECTL2 register. +//! +//! \return None +// +//***************************************************************************** +extern void Comp_E_setReferenceAccuracy(uint16_t baseAddress, + uint16_t referenceAccuracy); + +//***************************************************************************** +// +//! \brief Sets the power mode +//! +//! \param baseAddress is the base address of the COMP_E module. +//! \param powerMode decides the power mode +//! Valid values are: +//! - \b COMP_E_HIGH_SPEED_MODE +//! - \b COMP_E_NORMAL_MODE +//! - \b COMP_E_ULTRA_LOW_POWER_MODE +//! \n Modified bits are \b CEPWRMD of \b CECTL1 register. +//! +//! \return None +// +//***************************************************************************** +extern void Comp_E_setPowerMode(uint16_t baseAddress, + uint16_t powerMode); + +//***************************************************************************** +// +//! \brief Enables selected Comp_E interrupt sources. +//! +//! Enables the indicated Comp_E interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. Does not clear interrupt flags. +//! +//! \param baseAddress is the base address of the COMP_E module. +//! \param interruptMask +//! Mask value is the logical OR of any of the following: +//! - \b COMP_E_OUTPUT_INTERRUPT - Output interrupt +//! - \b COMP_E_INVERTED_POLARITY_INTERRUPT - Output interrupt inverted +//! polarity +//! - \b COMP_E_READY_INTERRUPT - Ready interrupt +//! +//! \return None +// +//***************************************************************************** +extern void Comp_E_enableInterrupt(uint16_t baseAddress, + uint16_t interruptMask); + +//***************************************************************************** +// +//! \brief Disables selected Comp_E interrupt sources. +//! +//! Disables the indicated Comp_E interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! \param baseAddress is the base address of the COMP_E module. +//! \param interruptMask +//! Mask value is the logical OR of any of the following: +//! - \b COMP_E_OUTPUT_INTERRUPT - Output interrupt +//! - \b COMP_E_INVERTED_POLARITY_INTERRUPT - Output interrupt inverted +//! polarity +//! - \b COMP_E_READY_INTERRUPT - Ready interrupt +//! +//! \return None +// +//***************************************************************************** +extern void Comp_E_disableInterrupt(uint16_t baseAddress, + uint16_t interruptMask); + +//***************************************************************************** +// +//! \brief Clears Comp_E interrupt flags. +//! +//! The Comp_E interrupt source is cleared, so that it no longer asserts. The +//! highest interrupt flag is automatically cleared when an interrupt vector +//! generator is used. +//! +//! \param baseAddress is the base address of the COMP_E module. +//! \param interruptFlagMask +//! Mask value is the logical OR of any of the following: +//! - \b COMP_E_OUTPUT_INTERRUPT_FLAG - Output interrupt flag +//! - \b COMP_E_INTERRUPT_FLAG_INVERTED_POLARITY - Output interrupt flag +//! inverted polarity +//! - \b COMP_E_INTERRUPT_FLAG_READY - Ready interrupt flag +//! +//! \return None +// +//***************************************************************************** +extern void Comp_E_clearInterrupt(uint16_t baseAddress, + uint16_t interruptFlagMask); + +//***************************************************************************** +// +//! \brief Gets the current Comp_E interrupt status. +//! +//! This returns the interrupt status for the Comp_E module based on which flag +//! is passed. +//! +//! \param baseAddress is the base address of the COMP_E module. +//! \param interruptFlagMask +//! Mask value is the logical OR of any of the following: +//! - \b COMP_E_OUTPUT_INTERRUPT_FLAG - Output interrupt flag +//! - \b COMP_E_INTERRUPT_FLAG_INVERTED_POLARITY - Output interrupt flag +//! inverted polarity +//! - \b COMP_E_INTERRUPT_FLAG_READY - Ready interrupt flag +//! +//! \return Logical OR of any of the following: +//! - \b Comp_E_OUTPUT_INTERRUPT_FLAG Output interrupt flag +//! - \b Comp_E_INTERRUPT_FLAG_INVERTED_POLARITY Output interrupt flag +//! inverted polarity +//! - \b Comp_E_INTERRUPT_FLAG_READY Ready interrupt flag +//! \n indicating the status of the masked flags +// +//***************************************************************************** +extern uint8_t Comp_E_getInterruptStatus(uint16_t baseAddress, + uint16_t interruptFlagMask); + +//***************************************************************************** +// +//! \brief Explicitly sets the edge direction that would trigger an interrupt. +//! +//! This function will set which direction the output will have to go, whether +//! rising or falling, to generate an interrupt based on a non-inverted +//! interrupt. +//! +//! \param baseAddress is the base address of the COMP_E module. +//! \param edgeDirection determines which direction the edge would have to go +//! to generate an interrupt based on the non-inverted interrupt flag. +//! Valid values are: +//! - \b COMP_E_FALLINGEDGE [Default] - sets the bit to generate an +//! interrupt when the output of the Comp_E falls from HIGH to LOW if +//! the normal interrupt bit is set(and LOW to HIGH if the inverted +//! interrupt enable bit is set). +//! - \b COMP_E_RISINGEDGE - sets the bit to generate an interrupt when +//! the output of the Comp_E rises from LOW to HIGH if the normal +//! interrupt bit is set(and HIGH to LOW if the inverted interrupt +//! enable bit is set). +//! \n Modified bits are \b CEIES of \b CECTL1 register. +//! +//! \return None +// +//***************************************************************************** +extern void Comp_E_setInterruptEdgeDirection(uint16_t baseAddress, + uint16_t edgeDirection); + +//***************************************************************************** +// +//! \brief Toggles the edge direction that would trigger an interrupt. +//! +//! This function will toggle which direction the output will have to go, +//! whether rising or falling, to generate an interrupt based on a non-inverted +//! interrupt. If the direction was rising, it is now falling, if it was +//! falling, it is now rising. +//! +//! \param baseAddress is the base address of the COMP_E module. +//! +//! Modified bits are \b CEIES of \b CECTL1 register. +//! +//! \return None +// +//***************************************************************************** +extern void Comp_E_toggleInterruptEdgeDirection(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Turns on the Comp_E module. +//! +//! This function sets the bit that enables the operation of the Comp_E module. +//! +//! \param baseAddress is the base address of the COMP_E module. +//! +//! \return None +// +//***************************************************************************** +extern void Comp_E_enable(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Turns off the Comp_E module. +//! +//! This function clears the CEON bit disabling the operation of the Comp_E +//! module, saving from excess power consumption. +//! +//! \param baseAddress is the base address of the COMP_E module. +//! +//! Modified bits are \b CEON of \b CECTL1 register. +//! +//! \return None +// +//***************************************************************************** +extern void Comp_E_disable(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Shorts the two input pins chosen during initialization. +//! +//! This function sets the bit that shorts the devices attached to the input +//! pins chosen from the initialization of the Comp_E. +//! +//! \param baseAddress is the base address of the COMP_E module. +//! +//! Modified bits are \b CESHORT of \b CECTL1 register. +//! +//! \return None +// +//***************************************************************************** +extern void Comp_E_shortInputs(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Disables the short of the two input pins chosen during +//! initialization. +//! +//! This function clears the bit that shorts the devices attached to the input +//! pins chosen from the initialization of the Comp_E. +//! +//! \param baseAddress is the base address of the COMP_E module. +//! +//! Modified bits are \b CESHORT of \b CECTL1 register. +//! +//! \return None +// +//***************************************************************************** +extern void Comp_E_unshortInputs(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Disables the input buffer of the selected input port to effectively +//! allow for analog signals. +//! +//! This function sets the bit to disable the buffer for the specified input +//! port to allow for analog signals from any of the Comp_E input pins. This +//! bit is automatically set when the input is initialized to be used with the +//! Comp_E module. This function should be used whenever an analog input is +//! connected to one of these pins to prevent parasitic voltage from causing +//! unexpected results. +//! +//! \param baseAddress is the base address of the COMP_E module. +//! \param inputPort is the port in which the input buffer will be disabled. +//! Mask value is the logical OR of any of the following: +//! - \b COMP_E_INPUT0 [Default] +//! - \b COMP_E_INPUT1 +//! - \b COMP_E_INPUT2 +//! - \b COMP_E_INPUT3 +//! - \b COMP_E_INPUT4 +//! - \b COMP_E_INPUT5 +//! - \b COMP_E_INPUT6 +//! - \b COMP_E_INPUT7 +//! - \b COMP_E_INPUT8 +//! - \b COMP_E_INPUT9 +//! - \b COMP_E_INPUT10 +//! - \b COMP_E_INPUT11 +//! - \b COMP_E_INPUT12 +//! - \b COMP_E_INPUT13 +//! - \b COMP_E_INPUT14 +//! - \b COMP_E_INPUT15 +//! - \b COMP_E_VREF +//! \n Modified bits are \b CEPDx of \b CECTL3 register. +//! +//! \return None +// +//***************************************************************************** +extern void Comp_E_disableInputBuffer(uint16_t baseAddress, + uint16_t inputPort); + +//***************************************************************************** +// +//! \brief Enables the input buffer of the selected input port to allow for +//! digital signals. +//! +//! This function clears the bit to enable the buffer for the specified input +//! port to allow for digital signals from any of the Comp_E input pins. This +//! should not be reset if there is an analog signal connected to the specified +//! input pin to prevent from unexpected results. +//! +//! \param baseAddress is the base address of the COMP_E module. +//! \param inputPort is the port in which the input buffer will be enabled. +//! Mask value is the logical OR of any of the following: +//! - \b COMP_E_INPUT0 [Default] +//! - \b COMP_E_INPUT1 +//! - \b COMP_E_INPUT2 +//! - \b COMP_E_INPUT3 +//! - \b COMP_E_INPUT4 +//! - \b COMP_E_INPUT5 +//! - \b COMP_E_INPUT6 +//! - \b COMP_E_INPUT7 +//! - \b COMP_E_INPUT8 +//! - \b COMP_E_INPUT9 +//! - \b COMP_E_INPUT10 +//! - \b COMP_E_INPUT11 +//! - \b COMP_E_INPUT12 +//! - \b COMP_E_INPUT13 +//! - \b COMP_E_INPUT14 +//! - \b COMP_E_INPUT15 +//! - \b COMP_E_VREF +//! \n Modified bits are \b CEPDx of \b CECTL3 register. +//! +//! \return None +// +//***************************************************************************** +extern void Comp_E_enableInputBuffer(uint16_t baseAddress, + uint16_t inputPort); + +//***************************************************************************** +// +//! \brief Toggles the bit that swaps which terminals the inputs go to, while +//! also inverting the output of the Comp_E. +//! +//! This function toggles the bit that controls which input goes to which +//! terminal. After initialization, this bit is set to 0, after toggling it +//! once the inputs are routed to the opposite terminal and the output is +//! inverted. +//! +//! \param baseAddress is the base address of the COMP_E module. +//! +//! \return None +// +//***************************************************************************** +extern void Comp_E_swapIO(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Returns the output value of the Comp_E module. +//! +//! Returns the output value of the Comp_E module. +//! +//! \param baseAddress is the base address of the COMP_E module. +//! +//! \return One of the following: +//! - \b Comp_E_LOW +//! - \b Comp_E_HIGH +//! \n indicating the output value of the Comp_E module +// +//***************************************************************************** +extern uint16_t Comp_E_outputValue(uint16_t baseAddress); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_COMP_E_H__ diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/crc.c b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/crc.c new file mode 100644 index 000000000..babb0cfde --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/crc.c @@ -0,0 +1,104 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// crc.c - Driver for the crc Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup crc_api crc +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_CRC__ +#include "crc.h" + +#include + +void CRC_setSeed(uint16_t baseAddress, + uint16_t seed) +{ + HWREG16(baseAddress + OFS_CRCINIRES) = seed; +} + +void CRC_set16BitData(uint16_t baseAddress, + uint16_t dataIn) +{ + HWREG16(baseAddress + OFS_CRCDI) = dataIn; +} + +void CRC_set8BitData(uint16_t baseAddress, + uint8_t dataIn) +{ + HWREG8(baseAddress + OFS_CRCDI_L) = dataIn; +} + +void CRC_set16BitDataReversed(uint16_t baseAddress, + uint16_t dataIn) +{ + HWREG16(baseAddress + OFS_CRCDIRB) = dataIn; +} + +void CRC_set8BitDataReversed(uint16_t baseAddress, + uint8_t dataIn) +{ + HWREG8(baseAddress + OFS_CRCDIRB_L) = dataIn; +} + +uint16_t CRC_getData(uint16_t baseAddress) +{ + return (HWREG16(baseAddress + OFS_CRCDI)); +} + +uint16_t CRC_getResult(uint16_t baseAddress) +{ + return (HWREG16(baseAddress + OFS_CRCINIRES)); +} + +uint16_t CRC_getResultBitsReversed(uint16_t baseAddress) +{ + return (HWREG16(baseAddress + OFS_CRCRESR)); +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for crc_api +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/crc.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/crc.h new file mode 100644 index 000000000..18cc751da --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/crc.h @@ -0,0 +1,209 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// crc.h - Driver for the CRC Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_CRC_H__ +#define __MSP430WARE_CRC_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_CRC__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Sets the seed for the CRC. +//! +//! This function sets the seed for the CRC to begin generating a signature +//! with the given seed and all passed data. Using this function resets the CRC +//! signature. +//! +//! \param baseAddress is the base address of the CRC module. +//! \param seed is the seed for the CRC to start generating a signature from. +//! \n Modified bits are \b CRCINIRES of \b CRCINIRES register. +//! +//! \return None +// +//***************************************************************************** +extern void CRC_setSeed(uint16_t baseAddress, + uint16_t seed); + +//***************************************************************************** +// +//! \brief Sets the 16 bit data to add into the CRC module to generate a new +//! signature. +//! +//! This function sets the given data into the CRC module to generate the new +//! signature from the current signature and new data. +//! +//! \param baseAddress is the base address of the CRC module. +//! \param dataIn is the data to be added, through the CRC module, to the +//! signature. +//! \n Modified bits are \b CRCDI of \b CRCDI register. +//! +//! \return None +// +//***************************************************************************** +extern void CRC_set16BitData(uint16_t baseAddress, + uint16_t dataIn); + +//***************************************************************************** +// +//! \brief Sets the 8 bit data to add into the CRC module to generate a new +//! signature. +//! +//! This function sets the given data into the CRC module to generate the new +//! signature from the current signature and new data. +//! +//! \param baseAddress is the base address of the CRC module. +//! \param dataIn is the data to be added, through the CRC module, to the +//! signature. +//! \n Modified bits are \b CRCDI of \b CRCDI register. +//! +//! \return None +// +//***************************************************************************** +extern void CRC_set8BitData(uint16_t baseAddress, + uint8_t dataIn); + +//***************************************************************************** +// +//! \brief Translates the 16 bit data by reversing the bits in each byte and +//! then sets this data to add into the CRC module to generate a new signature. +//! +//! This function first reverses the bits in each byte of the data and then +//! generates the new signature from the current signature and new translated +//! data. +//! +//! \param baseAddress is the base address of the CRC module. +//! \param dataIn is the data to be added, through the CRC module, to the +//! signature. +//! \n Modified bits are \b CRCDIRB of \b CRCDIRB register. +//! +//! \return None +// +//***************************************************************************** +extern void CRC_set16BitDataReversed(uint16_t baseAddress, + uint16_t dataIn); + +//***************************************************************************** +// +//! \brief Translates the 8 bit data by reversing the bits in each byte and +//! then sets this data to add into the CRC module to generate a new signature. +//! +//! This function first reverses the bits in each byte of the data and then +//! generates the new signature from the current signature and new translated +//! data. +//! +//! \param baseAddress is the base address of the CRC module. +//! \param dataIn is the data to be added, through the CRC module, to the +//! signature. +//! \n Modified bits are \b CRCDIRB of \b CRCDIRB register. +//! +//! \return None +// +//***************************************************************************** +extern void CRC_set8BitDataReversed(uint16_t baseAddress, + uint8_t dataIn); + +//***************************************************************************** +// +//! \brief Returns the value currently in the Data register. +//! +//! This function returns the value currently in the data register. If set in +//! byte bits reversed format, then the translated data would be returned. +//! +//! \param baseAddress is the base address of the CRC module. +//! +//! \return The value currently in the data register +// +//***************************************************************************** +extern uint16_t CRC_getData(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Returns the value pf the Signature Result. +//! +//! This function returns the value of the signature result generated by the +//! CRC. +//! +//! \param baseAddress is the base address of the CRC module. +//! +//! \return The value currently in the data register +// +//***************************************************************************** +extern uint16_t CRC_getResult(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Returns the bit-wise reversed format of the Signature Result. +//! +//! This function returns the bit-wise reversed format of the Signature Result. +//! +//! \param baseAddress is the base address of the CRC module. +//! +//! \return The bit-wise reversed format of the Signature Result +// +//***************************************************************************** +extern uint16_t CRC_getResultBitsReversed(uint16_t baseAddress); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_CRC_H__ diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/crc32.c b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/crc32.c new file mode 100644 index 000000000..9d5866af6 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/crc32.c @@ -0,0 +1,172 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// crc32.c - Driver for the crc32 Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup crc32_api crc32 +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_CRC32__ +#include "crc32.h" + +#include + +void CRC32_setSeed(uint32_t seed, + uint8_t crcMode) +{ + if(CRC16_MODE == crcMode) + { + HWREG16(CRC32_BASE + OFS_CRC16INIRESW0) = seed; + } + else + { + HWREG16(CRC32_BASE + OFS_CRC32INIRESW1) = ((seed & 0xFFFF0000) + >> 16); + HWREG16(CRC32_BASE + OFS_CRC32INIRESW0) = (seed & 0xFFFF); + } +} + +void CRC32_set8BitData(uint8_t dataIn, + uint8_t crcMode) +{ + if(CRC16_MODE == crcMode) + { + HWREG8(CRC32_BASE + OFS_CRC16DIW0_L) = dataIn; + } + else + { + HWREG8(CRC32_BASE + OFS_CRC32DIW0_L) = dataIn; + } +} + +void CRC32_set16BitData(uint16_t dataIn, + uint8_t crcMode) +{ + if(CRC16_MODE == crcMode) + { + HWREG16(CRC32_BASE + OFS_CRC16DIW0) = dataIn; + } + else + { + HWREG16(CRC32_BASE + OFS_CRC32DIW0) = dataIn; + } +} + +void CRC32_set32BitData(uint32_t dataIn) +{ + HWREG16(CRC32_BASE + OFS_CRC32DIW0) = dataIn & 0xFFFF; + HWREG16(CRC32_BASE + OFS_CRC32DIW1) = (uint16_t) ((dataIn & 0xFFFF0000) + >> 16); +} + +void CRC32_set8BitDataReversed(uint8_t dataIn, + uint8_t crcMode) +{ + if(CRC16_MODE == crcMode) + { + HWREG8(CRC32_BASE + OFS_CRC16DIRBW1_L) = dataIn; + } + else + { + HWREG8(CRC32_BASE + OFS_CRC32DIRBW1_L) = dataIn; + } +} + +void CRC32_set16BitDataReversed(uint16_t dataIn, + uint8_t crcMode) +{ + if(CRC16_MODE == crcMode) + { + HWREG16(CRC32_BASE + OFS_CRC16DIRBW1) = dataIn; + } + else + { + HWREG16(CRC32_BASE + OFS_CRC32DIRBW1) = dataIn; + } +} + +void CRC32_set32BitDataReversed(uint32_t dataIn) +{ + HWREG16(CRC32_BASE + OFS_CRC32DIRBW1) = dataIn & 0xFFFF; + HWREG16(CRC32_BASE + OFS_CRC32DIRBW0) = (uint16_t) ((dataIn & 0xFFFF0000) + >> 16); +} + +uint32_t CRC32_getResult(uint8_t crcMode) +{ + if(CRC16_MODE == crcMode) + { + return (HWREG16(CRC32_BASE + OFS_CRC16INIRESW0)); + } + else + { + uint32_t result = 0; + result = HWREG16(CRC32_BASE + OFS_CRC32INIRESW1); + result = (result << 16); + result |= HWREG16(CRC32_BASE + OFS_CRC32INIRESW0); + return (result); + } +} + +uint32_t CRC32_getResultReversed(uint8_t crcMode) +{ + if(CRC16_MODE == crcMode) + { + return (HWREG16(CRC32_BASE + OFS_CRC16RESRW0)); + } + else + { + uint32_t result = 0; + result = HWREG16(CRC32_BASE + OFS_CRC32RESRW0); + result = (result << 16); + result |= HWREG16(CRC32_BASE + OFS_CRC32RESRW1); + return (result); + } +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for crc32_api +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/crc32.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/crc32.h new file mode 100644 index 000000000..2c28132e7 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/crc32.h @@ -0,0 +1,263 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// crc32.h - Driver for the CRC32 Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_CRC32_H__ +#define __MSP430WARE_CRC32_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_CRC32__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the crcMode parameter for +// functions: CRC32_setSeed(), CRC32_getResult(), CRC32_getResultReversed(), +// CRC32_set8BitDataReversed(), CRC32_set16BitDataReversed(), +// CRC32_set8BitData(), and CRC32_set16BitData(). +// +//***************************************************************************** +#define CRC32_MODE (0x01) +#define CRC16_MODE (0x00) + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Sets the seed for the CRC32. +//! +//! This function sets the seed for the CRC32 to begin generating a signature +//! with the given seed and all passed data. Using this function resets the +//! CRC32 signature. +//! +//! \param seed is the seed for the CRC32 to start generating a signature from. +//! \n Modified bits are \b CRC32INIRESL0 of \b CRC32INIRESL0 register. +//! \param crcMode selects the mode of operation for the CRC32 +//! Valid values are: +//! - \b CRC32_MODE - 32 Bit Mode +//! - \b CRC16_MODE - 16 Bit Mode +//! +//! \return None +// +//***************************************************************************** +extern void CRC32_setSeed(uint32_t seed, + uint8_t crcMode); + +//***************************************************************************** +// +//! \brief Sets the 8 bit data to add into the CRC32 module to generate a new +//! signature. +//! +//! This function sets the given data into the CRC32 module to generate the new +//! signature from the current signature and new data. Bit 0 is treated as the +//! LSB. +//! +//! \param dataIn is the data to be added, through the CRC32 module, to the +//! signature. +//! \param crcMode selects the mode of operation for the CRC32 +//! Valid values are: +//! - \b CRC32_MODE - 32 Bit Mode +//! - \b CRC16_MODE - 16 Bit Mode +//! +//! \return None +// +//***************************************************************************** +extern void CRC32_set8BitData(uint8_t dataIn, + uint8_t crcMode); + +//***************************************************************************** +// +//! \brief Sets the 16 bit data to add into the CRC32 module to generate a new +//! signature. +//! +//! This function sets the given data into the CRC32 module to generate the new +//! signature from the current signature and new data. Bit 0 is treated as the +//! LSB. +//! +//! \param dataIn is the data to be added, through the CRC32 module, to the +//! signature. +//! \param crcMode selects the mode of operation for the CRC32 +//! Valid values are: +//! - \b CRC32_MODE - 32 Bit Mode +//! - \b CRC16_MODE - 16 Bit Mode +//! +//! \return None +// +//***************************************************************************** +extern void CRC32_set16BitData(uint16_t dataIn, + uint8_t crcMode); + +//***************************************************************************** +// +//! \brief Sets the 32 bit data to add into the CRC32 module to generate a new +//! signature. +//! +//! This function sets the given data into the CRC32 module to generate the new +//! signature from the current signature and new data. Bit 0 is treated as the +//! LSB. +//! +//! \param dataIn is the data to be added, through the CRC32 module, to the +//! signature. +//! +//! \return None +// +//***************************************************************************** +extern void CRC32_set32BitData(uint32_t dataIn); + +//***************************************************************************** +// +//! \brief Translates the data by reversing the bits in each 8 bit data and +//! then sets this data to add into the CRC32 module to generate a new +//! signature. +//! +//! This function first reverses the bits in each byte of the data and then +//! generates the new signature from the current signature and new translated +//! data. Bit 0 is treated as the MSB. +//! +//! \param dataIn is the data to be added, through the CRC32 module, to the +//! signature. +//! \param crcMode selects the mode of operation for the CRC32 +//! Valid values are: +//! - \b CRC32_MODE - 32 Bit Mode +//! - \b CRC16_MODE - 16 Bit Mode +//! +//! \return None +// +//***************************************************************************** +extern void CRC32_set8BitDataReversed(uint8_t dataIn, + uint8_t crcMode); + +//***************************************************************************** +// +//! \brief Translates the data by reversing the bits in each 16 bit data and +//! then sets this data to add into the CRC32 module to generate a new +//! signature. +//! +//! This function first reverses the bits in each byte of the data and then +//! generates the new signature from the current signature and new translated +//! data. Bit 0 is treated as the MSB. +//! +//! \param dataIn is the data to be added, through the CRC32 module, to the +//! signature. +//! \param crcMode selects the mode of operation for the CRC32 +//! Valid values are: +//! - \b CRC32_MODE - 32 Bit Mode +//! - \b CRC16_MODE - 16 Bit Mode +//! +//! \return None +// +//***************************************************************************** +extern void CRC32_set16BitDataReversed(uint16_t dataIn, + uint8_t crcMode); + +//***************************************************************************** +// +//! \brief Translates the data by reversing the bits in each 32 bit data and +//! then sets this data to add into the CRC32 module to generate a new +//! signature. +//! +//! This function first reverses the bits in each byte of the data and then +//! generates the new signature from the current signature and new translated +//! data. Bit 0 is treated as the MSB. +//! +//! \param dataIn is the data to be added, through the CRC32 module, to the +//! signature. +//! +//! \return None +// +//***************************************************************************** +extern void CRC32_set32BitDataReversed(uint32_t dataIn); + +//***************************************************************************** +// +//! \brief Returns the value of the signature result. +//! +//! This function returns the value of the signature result generated by the +//! CRC32. Bit 0 is treated as LSB. +//! +//! \param crcMode selects the mode of operation for the CRC32 +//! Valid values are: +//! - \b CRC32_MODE - 32 Bit Mode +//! - \b CRC16_MODE - 16 Bit Mode +//! +//! \return The signature result +// +//***************************************************************************** +extern uint32_t CRC32_getResult(uint8_t crcMode); + +//***************************************************************************** +// +//! \brief Returns the bit-wise reversed format of the 32 bit signature result. +//! +//! This function returns the bit-wise reversed format of the signature result. +//! Bit 0 is treated as MSB. +//! +//! \param crcMode selects the mode of operation for the CRC32 +//! Valid values are: +//! - \b CRC32_MODE - 32 Bit Mode +//! - \b CRC16_MODE - 16 Bit Mode +//! +//! \return The bit-wise reversed format of the signature result +// +//***************************************************************************** +extern uint32_t CRC32_getResultReversed(uint8_t crcMode); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_CRC32_H__ diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/cs.c b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/cs.c new file mode 100644 index 000000000..ce324d190 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/cs.c @@ -0,0 +1,939 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// cs.c - Driver for the cs Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup cs_api cs +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#if defined(__MSP430_HAS_CS__) || defined(__MSP430_HAS_SFR__) +#include "cs.h" + +#include + +//***************************************************************************** +// +// The following value is used by CS_getACLK, CS_getSMCLK, CS_getMCLK to +// determine the operating frequency based on the available DCO frequencies. +// +//***************************************************************************** +#define CS_DCO_FREQ_1 1000000 +#define CS_DCO_FREQ_2 2670000 +#define CS_DCO_FREQ_3 3330000 +#define CS_DCO_FREQ_4 4000000 +#define CS_DCO_FREQ_5 5330000 +#define CS_DCO_FREQ_6 6670000 +#define CS_DCO_FREQ_7 8000000 +#define CS_DCO_FREQ_8 16000000 +#define CS_DCO_FREQ_9 20000000 +#define CS_DCO_FREQ_10 24000000 + +//***************************************************************************** +// +// Internal very low power VLOCLK, low frequency oscillator with 10kHz typical +// frequency, internal low-power oscillator MODCLK with 5 MHz typical +// frequency and LFMODCLK is MODCLK divided by 128. +// +//***************************************************************************** +#define CS_VLOCLK_FREQUENCY 10000 +#define CS_MODCLK_FREQUENCY 5000000 +#define CS_LFMODCLK_FREQUENCY 39062 + +//***************************************************************************** +// +// The following value is used by CS_XT1Start, CS_bypassXT1, +// CS_XT1StartWithTimeout, CS_bypassXT1WithTimeout to properly set the XTS +// bit. This frequnecy threshold is specified in the User's Guide. +// +//***************************************************************************** +#define LFXT_FREQUENCY_THRESHOLD 50000 + +//***************************************************************************** +// +// LFXT crystal frequency. Should be set with +// CS_externalClockSourceInit if LFXT is used and user intends to invoke +// CS_getSMCLK, CS_getMCLK, CS_getACLK and +// CS_turnOnLFXT, CS_LFXTByPass, CS_turnOnLFXTWithTimeout, +// CS_LFXTByPassWithTimeout. +// +//***************************************************************************** +static uint32_t privateLFXTClockFrequency = 0; + +//***************************************************************************** +// +// The HFXT crystal frequency. Should be set with +// CS_externalClockSourceInit if HFXT is used and user intends to invoke +// CS_getSMCLK, CS_getMCLK, CS_getACLK, +// CS_turnOnLFXT, CS_LFXTByPass, CS_turnOnLFXTWithTimeout, +// CS_LFXTByPassWithTimeout. +// +//***************************************************************************** +static uint32_t privateHFXTClockFrequency = 0; + +static uint32_t privateCSASourceClockFromDCO(uint8_t clockdivider) +{ + uint32_t CLKFrequency = 0; + + if(HWREG16(CS_BASE + OFS_CSCTL1) & DCORSEL) + { + switch(HWREG16(CS_BASE + OFS_CSCTL1) & DCOFSEL_7) + { + case DCOFSEL_0: + CLKFrequency = CS_DCO_FREQ_1 / clockdivider; + break; + case DCOFSEL_1: + CLKFrequency = CS_DCO_FREQ_5 / clockdivider; + break; + case DCOFSEL_2: + CLKFrequency = CS_DCO_FREQ_6 / clockdivider; + break; + case DCOFSEL_3: + CLKFrequency = CS_DCO_FREQ_7 / clockdivider; + break; + case DCOFSEL_4: + CLKFrequency = CS_DCO_FREQ_8 / clockdivider; + break; + case DCOFSEL_5: + CLKFrequency = CS_DCO_FREQ_9 / clockdivider; + break; + case DCOFSEL_6: + case DCOFSEL_7: + CLKFrequency = CS_DCO_FREQ_10 / clockdivider; + break; + default: + CLKFrequency = 0; + break; + } + } + else + { + switch(HWREG16(CS_BASE + OFS_CSCTL1) & DCOFSEL_7) + { + case DCOFSEL_0: + CLKFrequency = CS_DCO_FREQ_1 / clockdivider; + break; + case DCOFSEL_1: + CLKFrequency = CS_DCO_FREQ_2 / clockdivider; + break; + case DCOFSEL_2: + CLKFrequency = CS_DCO_FREQ_3 / clockdivider; + break; + case DCOFSEL_3: + CLKFrequency = CS_DCO_FREQ_4 / clockdivider; + break; + case DCOFSEL_4: + CLKFrequency = CS_DCO_FREQ_5 / clockdivider; + break; + case DCOFSEL_5: + CLKFrequency = CS_DCO_FREQ_6 / clockdivider; + break; + case DCOFSEL_6: + case DCOFSEL_7: + CLKFrequency = CS_DCO_FREQ_7 / clockdivider; + break; + default: + CLKFrequency = 0; + break; + } + } + + return (CLKFrequency); +} + +static uint32_t privateCSAComputeCLKFrequency(uint16_t CLKSource, + uint16_t CLKSourceDivider) +{ + uint32_t CLKFrequency = 0; + uint8_t CLKSourceFrequencyDivider = 1; + uint8_t i = 0; + + // Determine Frequency divider + for(i = 0; i < CLKSourceDivider; i++) + { + CLKSourceFrequencyDivider *= 2; + } + + // Unlock CS control register + HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY; + + // Determine clock source based on CLKSource + switch(CLKSource) + { + // If LFXT is selected as clock source + case SELM__LFXTCLK: + CLKFrequency = (privateLFXTClockFrequency / + CLKSourceFrequencyDivider); + + //Check if LFXTOFFG is not set. If fault flag is set + //VLO is used as source clock + if(HWREG8(CS_BASE + OFS_CSCTL5) & LFXTOFFG) + { + HWREG8(CS_BASE + OFS_CSCTL5) &= ~(LFXTOFFG); + //Clear OFIFG fault flag + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + + if(HWREG8(CS_BASE + OFS_CSCTL5) & LFXTOFFG) + { + CLKFrequency = CS_LFMODCLK_FREQUENCY; + } + } + break; + + case SELM__VLOCLK: + CLKFrequency = + (CS_VLOCLK_FREQUENCY / CLKSourceFrequencyDivider); + break; + + case SELM__LFMODOSC: + CLKFrequency = + (CS_LFMODCLK_FREQUENCY / CLKSourceFrequencyDivider); + + break; + + case SELM__DCOCLK: + CLKFrequency = + privateCSASourceClockFromDCO(CLKSourceFrequencyDivider); + + break; + + case SELM__MODOSC: + CLKFrequency = + (CS_MODCLK_FREQUENCY / CLKSourceFrequencyDivider); + + break; + + case SELM__HFXTCLK: + CLKFrequency = + (privateHFXTClockFrequency / CLKSourceFrequencyDivider); + + if(HWREG8(CS_BASE + OFS_CSCTL5) & HFXTOFFG) + { + HWREG8(CS_BASE + OFS_CSCTL5) &= ~HFXTOFFG; + //Clear OFIFG fault flag + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + } + + if(HWREG8(CS_BASE + OFS_CSCTL5) & HFXTOFFG) + { + CLKFrequency = CS_MODCLK_FREQUENCY; + } + break; + } + + // Lock CS control register + HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00; + + return (CLKFrequency); +} + +void CS_setExternalClockSource(uint32_t LFXTCLK_frequency, + uint32_t HFXTCLK_frequency) +{ + privateLFXTClockFrequency = LFXTCLK_frequency; + privateHFXTClockFrequency = HFXTCLK_frequency; +} + +void CS_initClockSignal(uint8_t selectedClockSignal, + uint16_t clockSource, + uint16_t clockSourceDivider) +{ + //Verify User has selected a valid Frequency divider + assert( + (CS_CLOCK_DIVIDER_1 == clockSourceDivider) || + (CS_CLOCK_DIVIDER_2 == clockSourceDivider) || + (CS_CLOCK_DIVIDER_4 == clockSourceDivider) || + (CS_CLOCK_DIVIDER_8 == clockSourceDivider) || + (CS_CLOCK_DIVIDER_16 == clockSourceDivider) || + (CS_CLOCK_DIVIDER_32 == clockSourceDivider) + ); + + // Unlock CS control register + HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY; + + switch(selectedClockSignal) + { + case CS_ACLK: + assert( + (CS_LFXTCLK_SELECT == clockSource) || + (CS_VLOCLK_SELECT == clockSource) || + (CS_LFMODOSC_SELECT == clockSource) + ); + + clockSourceDivider = clockSourceDivider << 8; + clockSource = clockSource << 8; + + HWREG16(CS_BASE + OFS_CSCTL2) &= ~(SELA_7); + HWREG16(CS_BASE + OFS_CSCTL2) |= (clockSource); + HWREG16(CS_BASE + OFS_CSCTL3) &= ~(DIVA0 + DIVA1 + DIVA2); + HWREG16(CS_BASE + OFS_CSCTL3) |= clockSourceDivider; + break; + case CS_SMCLK: + assert( + (CS_LFXTCLK_SELECT == clockSource) || + (CS_VLOCLK_SELECT == clockSource) || + (CS_DCOCLK_SELECT == clockSource) || + (CS_HFXTCLK_SELECT == clockSource) || + (CS_LFMODOSC_SELECT == clockSource)|| + (CS_MODOSC_SELECT == clockSource) + ); + + clockSource = clockSource << 4; + clockSourceDivider = clockSourceDivider << 4; + + HWREG16(CS_BASE + OFS_CSCTL2) &= ~(SELS_7); + HWREG16(CS_BASE + OFS_CSCTL2) |= clockSource; + HWREG16(CS_BASE + OFS_CSCTL3) &= ~(DIVS0 + DIVS1 + DIVS2); + HWREG16(CS_BASE + OFS_CSCTL3) |= clockSourceDivider; + break; + case CS_MCLK: + assert( + (CS_LFXTCLK_SELECT == clockSource) || + (CS_VLOCLK_SELECT == clockSource) || + (CS_DCOCLK_SELECT == clockSource) || + (CS_HFXTCLK_SELECT == clockSource) || + (CS_LFMODOSC_SELECT == clockSource)|| + (CS_MODOSC_SELECT == clockSource) + ); + + HWREG16(CS_BASE + OFS_CSCTL2) &= ~(SELM_7); + HWREG16(CS_BASE + OFS_CSCTL2) |= clockSource; + HWREG16(CS_BASE + OFS_CSCTL3) &= ~(DIVM0 + DIVM1 + DIVM2); + HWREG16(CS_BASE + OFS_CSCTL3) |= clockSourceDivider; + break; + } + + // Lock CS control register + HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00; +} + +void CS_turnOnLFXT(uint16_t lfxtdrive) +{ + assert(privateLFXTClockFrequency != 0); + + assert((lfxtdrive == CS_LFXT_DRIVE_0) || + (lfxtdrive == CS_LFXT_DRIVE_1) || + (lfxtdrive == CS_LFXT_DRIVE_2) || + (lfxtdrive == CS_LFXT_DRIVE_3)); + + // Unlock CS control register + HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY; + + //Switch ON LFXT oscillator + HWREG16(CS_BASE + OFS_CSCTL4) &= ~LFXTOFF; + + //Highest drive setting for LFXTstartup + HWREG16(CS_BASE + OFS_CSCTL4_L) |= LFXTDRIVE1_L + LFXTDRIVE0_L; + + HWREG16(CS_BASE + OFS_CSCTL4) &= ~LFXTBYPASS; + + //Wait for Crystal to stabilize + while(HWREG8(CS_BASE + OFS_CSCTL5) & LFXTOFFG) + { + //Clear OSC flaut Flags fault flags + HWREG8(CS_BASE + OFS_CSCTL5) &= ~(LFXTOFFG); + + //Clear OFIFG fault flag + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + } + + //set requested Drive mode + HWREG16(CS_BASE + OFS_CSCTL4) = (HWREG16(CS_BASE + OFS_CSCTL4) & + ~(LFXTDRIVE_3) + ) | + (lfxtdrive); + + // Lock CS control register + HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00; +} + +void CS_bypassLFXT(void) +{ + //Verify user has set frequency of LFXT with SetExternalClockSource + assert(privateLFXTClockFrequency != 0); + + // Unlock CS control register + HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY; + + assert(privateLFXTClockFrequency < LFXT_FREQUENCY_THRESHOLD); + + // Set LFXT in LF mode Switch off LFXT oscillator and enable BYPASS mode + HWREG16(CS_BASE + OFS_CSCTL4) |= (LFXTBYPASS + LFXTOFF); + + //Wait until LFXT stabilizes + while(HWREG8(CS_BASE + OFS_CSCTL5) & LFXTOFFG) + { + //Clear OSC flaut Flags fault flags + HWREG8(CS_BASE + OFS_CSCTL5) &= ~(LFXTOFFG); + + // Clear the global fault flag. In case the LFXT caused the global fault + // flag to get set this will clear the global error condition. If any + // error condition persists, global flag will get again. + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + } + + // Lock CS control register + HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00; +} + +bool CS_turnOnLFXTWithTimeout(uint16_t lfxtdrive, + uint32_t timeout) +{ + assert(privateLFXTClockFrequency != 0); + + assert((lfxtdrive == CS_LFXT_DRIVE_0) || + (lfxtdrive == CS_LFXT_DRIVE_1) || + (lfxtdrive == CS_LFXT_DRIVE_2) || + (lfxtdrive == CS_LFXT_DRIVE_3)); + + assert(timeout > 0); + + // Unlock CS control register + HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY; + + //Switch ON LFXT oscillator + HWREG16(CS_BASE + OFS_CSCTL4) &= ~LFXTOFF; + + //Highest drive setting for LFXTstartup + HWREG16(CS_BASE + OFS_CSCTL4_L) |= LFXTDRIVE1_L + LFXTDRIVE0_L; + + HWREG16(CS_BASE + OFS_CSCTL4) &= ~LFXTBYPASS; + + while((HWREG8(CS_BASE + OFS_CSCTL5) & LFXTOFFG) && --timeout) + { + //Clear OSC fault Flags fault flags + HWREG8(CS_BASE + OFS_CSCTL5) &= ~(LFXTOFFG); + + // Clear the global fault flag. In case the LFXT caused the global fault + // flag to get set this will clear the global error condition. If any + // error condition persists, global flag will get again. + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + } + + if(timeout) + { + //set requested Drive mode + HWREG16(CS_BASE + OFS_CSCTL4) = (HWREG16(CS_BASE + OFS_CSCTL4) & + ~(LFXTDRIVE_3) + ) | + (lfxtdrive); + // Lock CS control register + HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00; + return (STATUS_SUCCESS); + } + else + { + // Lock CS control register + HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00; + return (STATUS_FAIL); + } +} + +bool CS_bypassLFXTWithTimeout(uint32_t timeout) +{ + assert(privateLFXTClockFrequency != 0); + + assert(privateLFXTClockFrequency < LFXT_FREQUENCY_THRESHOLD); + + assert(timeout > 0); + + // Unlock CS control register + HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY; + + // Set LFXT in LF mode Switch off LFXT oscillator and enable BYPASS mode + HWREG16(CS_BASE + OFS_CSCTL4) |= (LFXTBYPASS + LFXTOFF); + + while((HWREG8(CS_BASE + OFS_CSCTL5) & LFXTOFFG) && --timeout) + { + //Clear OSC fault Flags fault flags + HWREG8(CS_BASE + OFS_CSCTL5) &= ~(LFXTOFFG); + + // Clear the global fault flag. In case the LFXT caused the global fault + // flag to get set this will clear the global error condition. If any + // error condition persists, global flag will get again. + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + } + + // Lock CS control register + HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00; + + if(timeout) + { + return (STATUS_SUCCESS); + } + else + { + return (STATUS_FAIL); + } +} + +void CS_turnOffLFXT(void) +{ + // Unlock CS control register + HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY; + + //Switch off LFXT oscillator + HWREG16(CS_BASE + OFS_CSCTL4) |= LFXTOFF; + + // Lock CS control register + HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00; +} + +void CS_turnOnHFXT(uint16_t hfxtdrive) +{ + assert(privateHFXTClockFrequency != 0); + + assert((hfxtdrive == CS_HFXT_DRIVE_4MHZ_8MHZ) || + (hfxtdrive == CS_HFXT_DRIVE_8MHZ_16MHZ) || + (hfxtdrive == CS_HFXT_DRIVE_16MHZ_24MHZ)|| + (hfxtdrive == CS_HFXT_DRIVE_24MHZ_32MHZ)); + + // Unlock CS control register + HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY; + + // Switch ON HFXT oscillator + HWREG16(CS_BASE + OFS_CSCTL4) &= ~HFXTOFF; + + //Disable HFXTBYPASS mode and Switch on HFXT oscillator + HWREG16(CS_BASE + OFS_CSCTL4) &= ~HFXTBYPASS; + + //If HFFrequency is 16MHz or above + if(privateHFXTClockFrequency > 16000000) + { + HWREG16(CS_BASE + OFS_CSCTL4) = HFFREQ_3; + } + //If HFFrequency is between 8MHz and 16MHz + else if(privateHFXTClockFrequency > 8000000) + { + HWREG16(CS_BASE + OFS_CSCTL4) = HFFREQ_2; + } + //If HFFrequency is between 0MHz and 4MHz + else if(privateHFXTClockFrequency < 4000000) + { + HWREG16(CS_BASE + OFS_CSCTL4) = HFFREQ_0; + } + //If HFFrequency is between 4MHz and 8MHz + else + { + HWREG16(CS_BASE + OFS_CSCTL4) = HFFREQ_1; + } + + while(HWREG8(CS_BASE + OFS_CSCTL5) & HFXTOFFG) + { + //Clear OSC flaut Flags + HWREG8(CS_BASE + OFS_CSCTL5) &= ~(HFXTOFFG); + + //Clear OFIFG fault flag + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + } + + HWREG16(CS_BASE + OFS_CSCTL4) = (HWREG16(CS_BASE + OFS_CSCTL4) & + ~(CS_HFXT_DRIVE_24MHZ_32MHZ) + ) | + (hfxtdrive); + + // Lock CS control register + HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00; +} + +void CS_bypassHFXT(void) +{ + //Verify user has initialized value of HFXTClock + assert(privateHFXTClockFrequency != 0); + + // Unlock CS control register + HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY; + + //Switch off HFXT oscillator and set it to BYPASS mode + HWREG16(CS_BASE + OFS_CSCTL4) |= (HFXTBYPASS + HFXTOFF); + + //Set correct HFFREQ bit for FR58xx/FR59xx devices + + //If HFFrequency is 16MHz or above + if(privateHFXTClockFrequency > 16000000) + { + HWREG16(CS_BASE + OFS_CSCTL4) = HFFREQ_3; + } + //If HFFrequency is between 8MHz and 16MHz + else if(privateHFXTClockFrequency > 8000000) + { + HWREG16(CS_BASE + OFS_CSCTL4) = HFFREQ_2; + } + //If HFFrequency is between 0MHz and 4MHz + else if(privateHFXTClockFrequency < 4000000) + { + HWREG16(CS_BASE + OFS_CSCTL4) = HFFREQ_0; + } + //If HFFrequency is between 4MHz and 8MHz + else + { + HWREG16(CS_BASE + OFS_CSCTL4) = HFFREQ_1; + } + + while(HWREG8(CS_BASE + OFS_CSCTL5) & HFXTOFFG) + { + //Clear OSC fault Flags + HWREG8(CS_BASE + OFS_CSCTL5) &= ~(HFXTOFFG); + + //Clear OFIFG fault flag + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + } + + // Lock CS control register + HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00; +} + +bool CS_turnOnHFXTWithTimeout(uint16_t hfxtdrive, + uint32_t timeout) +{ + //Verify user has initialized value of HFXTClock + assert(privateHFXTClockFrequency != 0); + + assert(timeout > 0); + + // Unlock CS control register + HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY; + + //Switch on HFXT oscillator + HWREG16(CS_BASE + OFS_CSCTL4) &= ~HFXTOFF; + + // Disable HFXTBYPASS mode + HWREG16(CS_BASE + OFS_CSCTL4) &= ~HFXTBYPASS; + + //Set correct HFFREQ bit for FR58xx/FR59xx devices based + //on HFXTClockFrequency + + //If HFFrequency is 16MHz or above + if(privateHFXTClockFrequency > 16000000) + { + HWREG16(CS_BASE + OFS_CSCTL4) = HFFREQ_3; + } + //If HFFrequency is between 8MHz and 16MHz + else if(privateHFXTClockFrequency > 8000000) + { + HWREG16(CS_BASE + OFS_CSCTL4) = HFFREQ_2; + } + //If HFFrequency is between 0MHz and 4MHz + else if(privateHFXTClockFrequency < 4000000) + { + HWREG16(CS_BASE + OFS_CSCTL4) = HFFREQ_0; + } + //If HFFrequency is between 4MHz and 8MHz + else + { + HWREG16(CS_BASE + OFS_CSCTL4) = HFFREQ_1; + } + + while((HWREG8(CS_BASE + OFS_CSCTL5) & HFXTOFFG) && --timeout) + { + //Clear OSC fault Flags fault flags + HWREG8(CS_BASE + OFS_CSCTL5) &= ~(HFXTOFFG); + + // Clear the global fault flag. In case the LFXT caused the global fault + // flag to get set this will clear the global error condition. If any + // error condition persists, global flag will get again. + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + } + + if(timeout) + { + //Set drive strength for HFXT + HWREG16(CS_BASE + OFS_CSCTL4) = (HWREG16(CS_BASE + OFS_CSCTL4) & + ~(CS_HFXT_DRIVE_24MHZ_32MHZ) + ) | + (hfxtdrive); + // Lock CS control register + HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00; + return (STATUS_SUCCESS); + } + else + { + // Lock CS control register + HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00; + return (STATUS_FAIL); + } +} + +bool CS_bypassHFXTWithTimeout(uint32_t timeout) +{ + //Verify user has initialized value of HFXTClock + assert(privateHFXTClockFrequency != 0); + + assert(timeout > 0); + + // Unlock CS control register + HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY; + + //If HFFrequency is 16MHz or above + if(privateHFXTClockFrequency > 16000000) + { + HWREG16(CS_BASE + OFS_CSCTL4) = HFFREQ_3; + } + //If HFFrequency is between 8MHz and 16MHz + else if(privateHFXTClockFrequency > 8000000) + { + HWREG16(CS_BASE + OFS_CSCTL4) = HFFREQ_2; + } + //If HFFrequency is between 0MHz and 4MHz + else if(privateHFXTClockFrequency < 4000000) + { + HWREG16(CS_BASE + OFS_CSCTL4) = HFFREQ_0; + } + //If HFFrequency is between 4MHz and 8MHz + else + { + HWREG16(CS_BASE + OFS_CSCTL4) = HFFREQ_1; + } + + //Switch off HFXT oscillator and enable BYPASS mode + HWREG16(CS_BASE + OFS_CSCTL4) |= (HFXTBYPASS + HFXTOFF); + + while((HWREG8(CS_BASE + OFS_CSCTL5) & HFXTOFFG) && --timeout) + { + //Clear OSC fault Flags fault flags + HWREG8(CS_BASE + OFS_CSCTL5) &= ~(HFXTOFFG); + + // Clear the global fault flag. In case the LFXT caused the global fault + // flag to get set this will clear the global error condition. If any + // error condition persists, global flag will get again. + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + } + + // Lock CS control register + HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00; + + if(timeout) + { + return (STATUS_SUCCESS); + } + else + { + return (STATUS_FAIL); + } +} + +void CS_turnOffHFXT(void) +{ + // Unlock CS control register + HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY; + + //Switch off HFXT oscillator + HWREG16(CS_BASE + OFS_CSCTL4) |= HFXTOFF; + + // Lock CS control register + HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00; +} + +void CS_enableClockRequest(uint8_t selectClock) +{ + assert( + (CS_ACLK == selectClock)|| + (CS_SMCLK == selectClock)|| + (CS_MCLK == selectClock)|| + (CS_MODOSC == selectClock)); + + // Unlock CS control register + HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY; + + HWREG8(CS_BASE + OFS_CSCTL6) |= selectClock; + + // Lock CS control register + HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00; +} + +void CS_disableClockRequest(uint8_t selectClock) +{ + assert( + (CS_ACLK == selectClock)|| + (CS_SMCLK == selectClock)|| + (CS_MCLK == selectClock)|| + (CS_MODOSC == selectClock)); + + // Unlock CS control register + HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY; + + HWREG8(CS_BASE + OFS_CSCTL6) &= ~selectClock; + + // Lock CS control register + HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00; +} + +uint8_t CS_getFaultFlagStatus(uint8_t mask) +{ + assert( + (CS_HFXTOFFG == mask)|| + (CS_LFXTOFFG == mask) + ); + return (HWREG8(CS_BASE + OFS_CSCTL5) & mask); +} + +void CS_clearFaultFlag(uint8_t mask) +{ + assert( + (CS_HFXTOFFG == mask)|| + (CS_LFXTOFFG == mask) + ); + + // Unlock CS control register + HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY; + + HWREG8(CS_BASE + OFS_CSCTL5) &= ~mask; + + // Lock CS control register + HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00; +} + +uint32_t CS_getACLK(void) +{ + //Find ACLK source + uint16_t ACLKSource = (HWREG16(CS_BASE + OFS_CSCTL2) & SELA_7); + ACLKSource = ACLKSource >> 8; + + //Find ACLK frequency divider + uint16_t ACLKSourceDivider = HWREG16(CS_BASE + OFS_CSCTL3) & SELA_7; + ACLKSourceDivider = ACLKSourceDivider >> 8; + + return (privateCSAComputeCLKFrequency( + ACLKSource, + ACLKSourceDivider)); +} + +uint32_t CS_getSMCLK(void) +{ + //Find SMCLK source + uint16_t SMCLKSource = HWREG8(CS_BASE + OFS_CSCTL2) & SELS_7; + + SMCLKSource = SMCLKSource >> 4; + + //Find SMCLK frequency divider + uint16_t SMCLKSourceDivider = HWREG16(CS_BASE + OFS_CSCTL3) & SELS_7; + SMCLKSourceDivider = SMCLKSourceDivider >> 4; + + return (privateCSAComputeCLKFrequency( + SMCLKSource, + SMCLKSourceDivider) + ); +} + +uint32_t CS_getMCLK(void) +{ + //Find MCLK source + uint16_t MCLKSource = (HWREG16(CS_BASE + OFS_CSCTL2) & SELM_7); + //Find MCLK frequency divider + uint16_t MCLKSourceDivider = HWREG16(CS_BASE + OFS_CSCTL3) & SELM_7; + + return (privateCSAComputeCLKFrequency( + MCLKSource, + MCLKSourceDivider) + ); +} + +void CS_turnOffVLO(void) +{ + // Unlock CS control register + HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY; + + HWREG16(CS_BASE + OFS_CSCTL4) |= VLOOFF; + + // Lock CS control register + HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00; +} + +uint16_t CS_clearAllOscFlagsWithTimeout(uint32_t timeout) +{ + assert(timeout > 0); + + // Unlock CS control register + HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY; + + do + { + // Clear all osc fault flags + HWREG8(CS_BASE + OFS_CSCTL5) &= ~(LFXTOFFG + HFXTOFFG); + + // Clear the global osc fault flag. + HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; + + // Check LFXT fault flags + } + while((HWREG8(SFR_BASE + OFS_SFRIFG1) & OFIFG) && --timeout); + + // Lock CS control register + HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00; + + return (HWREG8(CS_BASE + OFS_CSCTL5) & (LFXTOFFG + HFXTOFFG)); +} + +void CS_setDCOFreq(uint16_t dcorsel, + uint16_t dcofsel) +{ + assert( + (dcofsel == CS_DCOFSEL_0)|| + (dcofsel == CS_DCOFSEL_1)|| + (dcofsel == CS_DCOFSEL_2)|| + (dcofsel == CS_DCOFSEL_3)|| + (dcofsel == CS_DCOFSEL_4)|| + (dcofsel == CS_DCOFSEL_5)|| + (dcofsel == CS_DCOFSEL_6) + ); + + //Verify user has selected a valid DCO Frequency Range option + assert( + (dcorsel == CS_DCORSEL_0)|| + (dcorsel == CS_DCORSEL_1)); + + //Unlock CS control register + HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY; + + // Set user's frequency selection for DCO + HWREG16(CS_BASE + OFS_CSCTL1) = (dcorsel + dcofsel); + + // Lock CS control register + HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00; +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for cs_api +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/cs.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/cs.h new file mode 100644 index 000000000..3a5c1a5d8 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/cs.h @@ -0,0 +1,620 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// cs.h - Driver for the CS Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_CS_H__ +#define __MSP430WARE_CS_H__ + +#include "inc/hw_memmap.h" + +#if defined(__MSP430_HAS_CS__) || defined(__MSP430_HAS_SFR__) + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the clockSourceDivider +// parameter for functions: CS_initClockSignal(). +// +//***************************************************************************** +#define CS_CLOCK_DIVIDER_1 DIVM__1 +#define CS_CLOCK_DIVIDER_2 DIVM__2 +#define CS_CLOCK_DIVIDER_4 DIVM__4 +#define CS_CLOCK_DIVIDER_8 DIVM__8 +#define CS_CLOCK_DIVIDER_16 DIVM__16 +#define CS_CLOCK_DIVIDER_32 DIVM__32 + +//***************************************************************************** +// +// The following are values that can be passed to the selectClock parameter for +// functions: CS_enableClockRequest(), and CS_disableClockRequest(); the +// selectedClockSignal parameter for functions: CS_initClockSignal(). +// +//***************************************************************************** +#define CS_ACLK 0x01 +#define CS_MCLK 0x02 +#define CS_SMCLK 0x04 +#define CS_MODOSC MODCLKREQEN + +//***************************************************************************** +// +// The following are values that can be passed to the clockSource parameter for +// functions: CS_initClockSignal(). +// +//***************************************************************************** +#define CS_VLOCLK_SELECT SELM__VLOCLK +#define CS_DCOCLK_SELECT SELM__DCOCLK +#define CS_LFXTCLK_SELECT SELM__LFXTCLK +#define CS_HFXTCLK_SELECT SELM__HFXTCLK +#define CS_LFMODOSC_SELECT SELM__LFMODOSC +#define CS_MODOSC_SELECT SELM__MODOSC + +//***************************************************************************** +// +// The following are values that can be passed to the lfxtdrive parameter for +// functions: CS_turnOnLFXT(), and CS_turnOnLFXTWithTimeout(). +// +//***************************************************************************** +#define CS_LFXT_DRIVE_0 LFXTDRIVE_0 +#define CS_LFXT_DRIVE_1 LFXTDRIVE_1 +#define CS_LFXT_DRIVE_2 LFXTDRIVE_2 +#define CS_LFXT_DRIVE_3 LFXTDRIVE_3 + +//***************************************************************************** +// +// The following are values that can be passed to the hfxtdrive parameter for +// functions: CS_turnOnHFXT(), and CS_turnOnHFXTWithTimeout(). +// +//***************************************************************************** +#define CS_HFXT_DRIVE_4MHZ_8MHZ HFXTDRIVE_0 +#define CS_HFXT_DRIVE_8MHZ_16MHZ HFXTDRIVE_1 +#define CS_HFXT_DRIVE_16MHZ_24MHZ HFXTDRIVE_2 +#define CS_HFXT_DRIVE_24MHZ_32MHZ HFXTDRIVE_3 + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: CS_getFaultFlagStatus(), and CS_clearFaultFlag() as well as +// returned by the CS_getFaultFlagStatus() function. +// +//***************************************************************************** +#define CS_LFXTOFFG LFXTOFFG +#define CS_HFXTOFFG HFXTOFFG + +//***************************************************************************** +// +// The following are values that can be passed to the dcorsel parameter for +// functions: CS_setDCOFreq(). +// +//***************************************************************************** +#define CS_DCORSEL_0 0x00 +#define CS_DCORSEL_1 DCORSEL + +//***************************************************************************** +// +// The following are values that can be passed to the dcofsel parameter for +// functions: CS_setDCOFreq(). +// +//***************************************************************************** +#define CS_DCOFSEL_0 DCOFSEL_0 +#define CS_DCOFSEL_1 DCOFSEL_1 +#define CS_DCOFSEL_2 DCOFSEL_2 +#define CS_DCOFSEL_3 DCOFSEL_3 +#define CS_DCOFSEL_4 DCOFSEL_4 +#define CS_DCOFSEL_5 DCOFSEL_5 +#define CS_DCOFSEL_6 DCOFSEL_6 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Sets the external clock source +//! +//! This function sets the external clock sources LFXT and HFXT crystal +//! oscillator frequency values. This function must be called if an external +//! crystal LFXT or HFXT is used and the user intends to call CS_getMCLK, +//! CS_getSMCLK, CS_getACLK and CS_turnOnLFXT, CS_LFXTByPass, +//! CS_turnOnLFXTWithTimeout, CS_LFXTByPassWithTimeout, CS_turnOnHFXT, +//! CS_HFXTByPass, CS_turnOnHFXTWithTimeout, CS_HFXTByPassWithTimeout. +//! +//! \param LFXTCLK_frequency is the LFXT crystal frequencies in Hz +//! \param HFXTCLK_frequency is the HFXT crystal frequencies in Hz +//! +//! \return None +// +//***************************************************************************** +extern void CS_setExternalClockSource(uint32_t LFXTCLK_frequency, + uint32_t HFXTCLK_frequency); + +//***************************************************************************** +// +//! \brief Initializes clock signal +//! +//! This function initializes each of the clock signals. The user must ensure +//! that this function is called for each clock signal. If not, the default +//! state is assumed for the particular clock signal. Refer to MSP430ware +//! documentation for CS module or Device Family User's Guide for details of +//! default clock signal states. +//! +//! \param selectedClockSignal Selected clock signal +//! Valid values are: +//! - \b CS_ACLK +//! - \b CS_MCLK +//! - \b CS_SMCLK +//! - \b CS_MODOSC +//! \param clockSource is the selected clock signal +//! Valid values are: +//! - \b CS_VLOCLK_SELECT +//! - \b CS_DCOCLK_SELECT - [Not available for ACLK] +//! - \b CS_LFXTCLK_SELECT +//! - \b CS_HFXTCLK_SELECT - [Not available for ACLK] +//! - \b CS_LFMODOSC_SELECT +//! - \b CS_MODOSC_SELECT - [Not available for ACLK] +//! \param clockSourceDivider is the selected clock divider to calculate clock +//! signal from clock source. +//! Valid values are: +//! - \b CS_CLOCK_DIVIDER_1 - [Default for ACLK] +//! - \b CS_CLOCK_DIVIDER_2 +//! - \b CS_CLOCK_DIVIDER_4 +//! - \b CS_CLOCK_DIVIDER_8 - [Default for SMCLK and MCLK] +//! - \b CS_CLOCK_DIVIDER_16 +//! - \b CS_CLOCK_DIVIDER_32 +//! +//! Modified bits of \b CSCTL0 register, bits of \b CSCTL3 register and bits of +//! \b CSCTL2 register. +//! +//! \return None +// +//***************************************************************************** +extern void CS_initClockSignal(uint8_t selectedClockSignal, + uint16_t clockSource, + uint16_t clockSourceDivider); + +//***************************************************************************** +// +//! \brief Initializes the LFXT crystal in low frequency mode. +//! +//! Initializes the LFXT crystal oscillator in low frequency mode. Loops until +//! all oscillator fault flags are cleared, with no timeout. See the device- +//! specific data sheet for appropriate drive settings. IMPORTANT: User must +//! call CS_setExternalClockSource function to set frequency of external clocks +//! before calling this function. +//! +//! \param lfxtdrive is the target drive strength for the LFXT crystal +//! oscillator. +//! Valid values are: +//! - \b CS_LFXT_DRIVE_0 +//! - \b CS_LFXT_DRIVE_1 +//! - \b CS_LFXT_DRIVE_2 +//! - \b CS_LFXT_DRIVE_3 [Default] +//! +//! Modified bits of \b CSCTL0 register, bits of \b CSCTL5 register, bits of \b +//! CSCTL4 register and bits of \b SFRIFG1 register. +//! +//! \return None +// +//***************************************************************************** +extern void CS_turnOnLFXT(uint16_t lfxtdrive); + +//***************************************************************************** +// +//! \brief Bypasses the LFXT crystal oscillator. +//! +//! Bypasses the LFXT crystal oscillator. Loops until all oscillator fault +//! flags are cleared, with no timeout. IMPORTANT: User must call +//! CS_setExternalClockSource function to set frequency of external clocks +//! before calling this function. +//! +//! +//! Modified bits of \b CSCTL0 register, bits of \b CSCTL5 register, bits of \b +//! CSCTL4 register and bits of \b SFRIFG register. +//! +//! \return None +// +//***************************************************************************** +extern void CS_bypassLFXT(void); + +//***************************************************************************** +// +//! \brief Initializes the LFXT crystal oscillator in low frequency mode with +//! timeout. +//! +//! Initializes the LFXT crystal oscillator in low frequency mode with timeout. +//! Loops until all oscillator fault flags are cleared or until a timeout +//! counter is decremented and equals to zero. See the device-specific +//! datasheet for appropriate drive settings. IMPORTANT: User must call +//! CS_setExternalClockSource to set frequency of external clocks before +//! calling this function. +//! +//! \param lfxtdrive is the target drive strength for the LFXT crystal +//! oscillator. +//! Valid values are: +//! - \b CS_LFXT_DRIVE_0 +//! - \b CS_LFXT_DRIVE_1 +//! - \b CS_LFXT_DRIVE_2 +//! - \b CS_LFXT_DRIVE_3 [Default] +//! \param timeout is the count value that gets decremented every time the loop +//! that clears oscillator fault flags gets executed. +//! +//! Modified bits of \b CSCTL0 register, bits of \b CSCTL5 register, bits of \b +//! CSCTL4 register and bits of \b SFRIFG1 register. +//! +//! \return STATUS_SUCCESS or STATUS_FAIL indicating if the LFXT crystal +//! oscillator was initialized successfully +// +//***************************************************************************** +extern bool CS_turnOnLFXTWithTimeout(uint16_t lfxtdrive, + uint32_t timeout); + +//***************************************************************************** +// +//! \brief Bypass the LFXT crystal oscillator with timeout. +//! +//! Bypasses the LFXT crystal oscillator with timeout. Loops until all +//! oscillator fault flags are cleared or until a timeout counter is +//! decremented and equals to zero. NOTE: User must call +//! CS_setExternalClockSource to set frequency of external clocks before +//! calling this function. +//! +//! \param timeout is the count value that gets decremented every time the loop +//! that clears oscillator fault flags gets executed. +//! +//! Modified bits of \b CSCTL0 register, bits of \b CSCTL5 register, bits of \b +//! CSCTL4 register and bits of \b SFRIFG register. +//! +//! \return STATUS_SUCCESS or STATUS_FAIL +// +//***************************************************************************** +extern bool CS_bypassLFXTWithTimeout(uint32_t timeout); + +//***************************************************************************** +// +//! \brief Stops the LFXT oscillator using the LFXTOFF bit. +//! +//! +//! Modified bits of \b CSCTL4 register. +//! +//! \return None +// +//***************************************************************************** +extern void CS_turnOffLFXT(void); + +//***************************************************************************** +// +//! \brief Starts the HFXFT crystal +//! +//! Initializes the HFXT crystal oscillator, which supports crystal frequencies +//! between 0 MHz and 24 MHz, depending on the selected drive strength. Loops +//! until all oscillator fault flags are cleared, with no timeout. See the +//! device-specific data sheet for appropriate drive settings. NOTE: User must +//! call CS_setExternalClockSource to set frequency of external clocks before +//! calling this function. +//! +//! \param hfxtdrive is the target drive strength for the HFXT crystal +//! oscillator. +//! Valid values are: +//! - \b CS_HFXT_DRIVE_4MHZ_8MHZ +//! - \b CS_HFXT_DRIVE_8MHZ_16MHZ +//! - \b CS_HFXT_DRIVE_16MHZ_24MHZ +//! - \b CS_HFXT_DRIVE_24MHZ_32MHZ [Default] +//! +//! Modified bits of \b CSCTL5 register, bits of \b CSCTL4 register and bits of +//! \b SFRIFG1 register. +//! +//! \return None +// +//***************************************************************************** +extern void CS_turnOnHFXT(uint16_t hfxtdrive); + +//***************************************************************************** +// +//! \brief Bypasses the HFXT crystal oscillator +//! +//! Bypasses the HFXT crystal oscillator, which supports crystal frequencies +//! between 0 MHz and 24 MHz. Loops until all oscillator fault flags are +//! cleared, with no timeout.NOTE: User must call CS_setExternalClockSource to +//! set frequency of external clocks before calling this function. +//! +//! +//! Modified bits of \b CSCTL5 register, bits of \b CSCTL4 register and bits of +//! \b SFRIFG register. +//! +//! \return None +// +//***************************************************************************** +extern void CS_bypassHFXT(void); + +//***************************************************************************** +// +//! \brief Initializes the HFXT crystal oscillator with timeout. +//! +//! Initializes the HFXT crystal oscillator, which supports crystal frequencies +//! between 0 MHz and 24 MHz, depending on the selected drive strength. Loops +//! until all oscillator fault flags are cleared or until a timeout counter is +//! decremented and equals to zero. See the device-specific data sheet for +//! appropriate drive settings. NOTE: User must call CS_setExternalClockSource +//! to set frequency of external clocks before calling this function. +//! +//! \param hfxtdrive is the target drive strength for the HFXT crystal +//! oscillator. +//! Valid values are: +//! - \b CS_HFXT_DRIVE_4MHZ_8MHZ +//! - \b CS_HFXT_DRIVE_8MHZ_16MHZ +//! - \b CS_HFXT_DRIVE_16MHZ_24MHZ +//! - \b CS_HFXT_DRIVE_24MHZ_32MHZ [Default] +//! \param timeout is the count value that gets decremented every time the loop +//! that clears oscillator fault flags gets executed. +//! +//! Modified bits of \b CSCTL5 register, bits of \b CSCTL4 register and bits of +//! \b SFRIFG1 register. +//! +//! \return STATUS_SUCCESS or STATUS_FAIL +// +//***************************************************************************** +extern bool CS_turnOnHFXTWithTimeout(uint16_t hfxtdrive, + uint32_t timeout); + +//***************************************************************************** +// +//! \brief Bypasses the HFXT crustal oscillator with timeout +//! +//! Bypasses the HFXT crystal oscillator, which supports crystal frequencies +//! between 0 MHz and 24 MHz. Loops until all oscillator fault flags are +//! cleared or until a timeout counter is decremented and equals to zero. NOTE: +//! User must call CS_setExternalClockSource to set frequency of external +//! clocks before calling this function. +//! +//! \param timeout is the count value that gets decremented every time the loop +//! that clears oscillator fault flags gets executed. +//! +//! Modified bits of \b CSCTL5 register, bits of \b CSCTL4 register and bits of +//! \b SFRIFG1 register. +//! +//! \return STATUS_SUCCESS or STATUS_FAIL +// +//***************************************************************************** +extern bool CS_bypassHFXTWithTimeout(uint32_t timeout); + +//***************************************************************************** +// +//! \brief Stops the HFXT oscillator using the HFXTOFF bit. +//! +//! +//! Modified bits of \b CSCTL4 register. +//! +//! \return None +// +//***************************************************************************** +extern void CS_turnOffHFXT(void); + +//***************************************************************************** +// +//! \brief Enables conditional module requests +//! +//! \param selectClock selects specific request enables. +//! Valid values are: +//! - \b CS_ACLK +//! - \b CS_MCLK +//! - \b CS_SMCLK +//! - \b CS_MODOSC +//! +//! Modified bits of \b CSCTL6 register. +//! +//! \return None +// +//***************************************************************************** +extern void CS_enableClockRequest(uint8_t selectClock); + +//***************************************************************************** +// +//! \brief Disables conditional module requests +//! +//! \param selectClock selects specific request enables. +//! Valid values are: +//! - \b CS_ACLK +//! - \b CS_MCLK +//! - \b CS_SMCLK +//! - \b CS_MODOSC +//! +//! Modified bits of \b CSCTL6 register. +//! +//! \return None +// +//***************************************************************************** +extern void CS_disableClockRequest(uint8_t selectClock); + +//***************************************************************************** +// +//! \brief Gets the current CS fault flag status. +//! +//! \param mask is the masked interrupt flag status to be returned. Mask +//! parameter can be either any of the following selection. +//! Mask value is the logical OR of any of the following: +//! - \b CS_LFXTOFFG - LFXT oscillator fault flag +//! - \b CS_HFXTOFFG - HFXT oscillator fault flag +//! +//! \return Logical OR of any of the following: +//! - \b CS_LFXTOFFG LFXT oscillator fault flag +//! - \b CS_HFXTOFFG HFXT oscillator fault flag +//! \n indicating the status of the masked interrupts +// +//***************************************************************************** +extern uint8_t CS_getFaultFlagStatus(uint8_t mask); + +//***************************************************************************** +// +//! \brief Clears the current CS fault flag status for the masked bit. +//! +//! \param mask is the masked interrupt flag status to be returned. mask +//! parameter can be any one of the following +//! Mask value is the logical OR of any of the following: +//! - \b CS_LFXTOFFG - LFXT oscillator fault flag +//! - \b CS_HFXTOFFG - HFXT oscillator fault flag +//! +//! Modified bits of \b CSCTL5 register. +//! +//! \return None +// +//***************************************************************************** +extern void CS_clearFaultFlag(uint8_t mask); + +//***************************************************************************** +// +//! \brief Get the current ACLK frequency. +//! +//! If a oscillator fault is set, the frequency returned will be based on the +//! fail safe mechanism of CS module. The user of this API must ensure that +//! CS_externalClockSourceInit API was invoked before in case LFXT or HFXT is +//! being used. +//! +//! +//! \return Current ACLK frequency in Hz +// +//***************************************************************************** +extern uint32_t CS_getACLK(void); + +//***************************************************************************** +// +//! \brief Get the current SMCLK frequency. +//! +//! If a oscillator fault is set, the frequency returned will be based on the +//! fail safe mechanism of CS module. The user of this API must ensure that +//! CS_externalClockSourceInit API was invoked before in case LFXT or HFXT is +//! being used. +//! +//! +//! \return Current SMCLK frequency in Hz +// +//***************************************************************************** +extern uint32_t CS_getSMCLK(void); + +//***************************************************************************** +// +//! \brief Get the current MCLK frequency. +//! +//! If a oscillator fault is set, the frequency returned will be based on the +//! fail safe mechanism of CS module. The user of this API must ensure that +//! CS_externalClockSourceInit API was invoked before in case LFXT or HFXT is +//! being used. +//! +//! +//! \return Current MCLK frequency in Hz +// +//***************************************************************************** +extern uint32_t CS_getMCLK(void); + +//***************************************************************************** +// +//! \brief Turns off VLO +//! +//! +//! Modified bits of \b CSCTL4 register. +//! +//! \return None +// +//***************************************************************************** +extern void CS_turnOffVLO(void); + +//***************************************************************************** +// +//! \brief Clears all the Oscillator Flags +//! +//! \param timeout is the count value that gets decremented every time the loop +//! that clears oscillator fault flags gets executed. +//! +//! Modified bits of \b CSCTL5 register and bits of \b SFRIFG1 register. +//! +//! \return the mask of the oscillator flag status +// +//***************************************************************************** +extern uint16_t CS_clearAllOscFlagsWithTimeout(uint32_t timeout); + +//***************************************************************************** +// +//! \brief Set DCO frequency +//! +//! \param dcorsel selects frequency range option. +//! Valid values are: +//! - \b CS_DCORSEL_0 [Default] - Low Frequency Option +//! - \b CS_DCORSEL_1 - High Frequency Option +//! \param dcofsel selects valid frequency options based on dco frequency range +//! selection (dcorsel) +//! Valid values are: +//! - \b CS_DCOFSEL_0 - Low frequency option 1MHz. High frequency option +//! 1MHz. +//! - \b CS_DCOFSEL_1 - Low frequency option 2.67MHz. High frequency +//! option 5.33MHz. +//! - \b CS_DCOFSEL_2 - Low frequency option 3.33MHz. High frequency +//! option 6.67MHz. +//! - \b CS_DCOFSEL_3 - Low frequency option 4MHz. High frequency option +//! 8MHz. +//! - \b CS_DCOFSEL_4 - Low frequency option 5.33MHz. High frequency +//! option 16MHz. +//! - \b CS_DCOFSEL_5 - Low frequency option 6.67MHz. High frequency +//! option 20MHz. +//! - \b CS_DCOFSEL_6 - Low frequency option 8MHz. High frequency option +//! 24MHz. +//! +//! \return None +// +//***************************************************************************** +extern void CS_setDCOFreq(uint16_t dcorsel, + uint16_t dcofsel); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_CS_H__ diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/deprecated/CCS/msp430fr5xx_6xxgeneric.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/deprecated/CCS/msp430fr5xx_6xxgeneric.h new file mode 100644 index 000000000..8fc25337e --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/deprecated/CCS/msp430fr5xx_6xxgeneric.h @@ -0,0 +1,6542 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +/* ============================================================================ */ +/* Copyright (c) 2013, Texas Instruments Incorporated */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of Texas Instruments Incorporated nor the names of */ +/* its contributors may be used to endorse or promote products derived */ +/* from this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ +/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ +/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ +/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ +/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ +/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ +/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ============================================================================ */ + +/******************************************************************** +* +* Standard register and bit definitions for the Texas Instruments +* MSP430 microcontroller. +* +* This file supports assembler and C development for +* MSP430FR5XX_FR6XXGENERIC device. +* +* Texas Instruments, Version 1.0 +* +* Rev. 1.0, Setup +* +* +********************************************************************/ + +#ifndef __msp430FR5XX_FR6XXGENERIC +#define __msp430FR5XX_FR6XXGENERIC + +//#define __MSP430_HEADER_VERSION__ 1125 + +#ifdef __cplusplus +extern "C" { +#endif + + +/*----------------------------------------------------------------------------*/ +/* PERIPHERAL FILE MAP */ +/*----------------------------------------------------------------------------*/ + +#ifndef SFR_8BIT +/* External references resolved by a device-specific linker command file */ +#define SFR_8BIT(address) extern volatile unsigned char address +#define SFR_16BIT(address) extern volatile unsigned int address +//#define SFR_20BIT(address) extern volatile unsigned int address +typedef void (* __SFR_FARPTR)(); +#define SFR_20BIT(address) extern __SFR_FARPTR address +#define SFR_32BIT(address) extern volatile unsigned long address + +#endif + + +/************************************************************ +* STANDARD BITS +************************************************************/ + +#define BIT0 (0x0001) +#define BIT1 (0x0002) +#define BIT2 (0x0004) +#define BIT3 (0x0008) +#define BIT4 (0x0010) +#define BIT5 (0x0020) +#define BIT6 (0x0040) +#define BIT7 (0x0080) +#define BIT8 (0x0100) +#define BIT9 (0x0200) +#define BITA (0x0400) +#define BITB (0x0800) +#define BITC (0x1000) +#define BITD (0x2000) +#define BITE (0x4000) +#define BITF (0x8000) + +/************************************************************ +* STATUS REGISTER BITS +************************************************************/ + +#define C (0x0001) +#define Z (0x0002) +#define N (0x0004) +#define V (0x0100) +#define GIE (0x0008) +#define CPUOFF (0x0010) +#define OSCOFF (0x0020) +#define SCG0 (0x0040) +#define SCG1 (0x0080) + +/* Low Power Modes coded with Bits 4-7 in SR */ + +#ifdef __ASM_HEADER__ /* Begin #defines for assembler */ +#define LPM0 (CPUOFF) +#define LPM1 (SCG0+CPUOFF) +#define LPM2 (SCG1+CPUOFF) +#define LPM3 (SCG1+SCG0+CPUOFF) +#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF) +/* End #defines for assembler */ + +#else /* Begin #defines for C */ +#define LPM0_bits (CPUOFF) +#define LPM1_bits (SCG0+CPUOFF) +#define LPM2_bits (SCG1+CPUOFF) +#define LPM3_bits (SCG1+SCG0+CPUOFF) +#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF) + +#include "in430.h" +#include + +#if __MSP430_HEADER_VERSION__ < 1107 + #define LPM0 _bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */ + #define LPM0_EXIT _bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */ + #define LPM1 _bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */ + #define LPM1_EXIT _bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */ + #define LPM2 _bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */ + #define LPM2_EXIT _bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */ + #define LPM3 _bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */ + #define LPM3_EXIT _bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */ + #define LPM4 _bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */ + #define LPM4_EXIT _bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */ +#else + #define LPM0 __bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */ + #define LPM0_EXIT __bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */ + #define LPM1 __bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */ + #define LPM1_EXIT __bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */ + #define LPM2 __bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */ + #define LPM2_EXIT __bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */ + #define LPM3 __bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */ + #define LPM3_EXIT __bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */ + #define LPM4 __bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */ + #define LPM4_EXIT __bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */ +#endif +#endif /* End #defines for C */ + +/************************************************************ +* CPU +************************************************************/ +#define __MSP430_HAS_MSP430XV2_CPU__ /* Definition to show that it has MSP430XV2 CPU */ + +#if defined(__MSP430_HAS_T0A2__) || defined(__MSP430_HAS_T1A2__) || defined(__MSP430_HAS_T2A2__) || defined(__MSP430_HAS_T3A2__) \ + || defined(__MSP430_HAS_T0A3__) || defined(__MSP430_HAS_T1A3__) || defined(__MSP430_HAS_T2A3__) || defined(__MSP430_HAS_T3A3__) \ + || defined(__MSP430_HAS_T0A5__) || defined(__MSP430_HAS_T1A5__) || defined(__MSP430_HAS_T2A5__) || defined(__MSP430_HAS_T3A5__) \ + || defined(__MSP430_HAS_T0A7__) || defined(__MSP430_HAS_T1A7__) || defined(__MSP430_HAS_T2A7__) || defined(__MSP430_HAS_T3A7__) + #define __MSP430_HAS_TxA7__ +#endif +#if defined(__MSP430_HAS_T0B3__) || defined(__MSP430_HAS_T0B5__) || defined(__MSP430_HAS_T0B7__) \ + || defined(__MSP430_HAS_T1B3__) || defined(__MSP430_HAS_T1B5__) || defined(__MSP430_HAS_T1B7__) + #define __MSP430_HAS_TxB7__ +#endif +#if defined(__MSP430_HAS_T0D3__) || defined(__MSP430_HAS_T0D5__) || defined(__MSP430_HAS_T0D7__) \ + || defined(__MSP430_HAS_T1D3__) || defined(__MSP430_HAS_T1D5__) || defined(__MSP430_HAS_T1D7__) + #define __MSP430_HAS_TxD7__ +#endif +#if defined(__MSP430_HAS_USCI_A0__) || defined(__MSP430_HAS_USCI_A1__) || defined(__MSP430_HAS_USCI_A2__) || defined(__MSP430_HAS_USCI_A3__) + #define __MSP430_HAS_USCI_Ax__ +#endif +#if defined(__MSP430_HAS_USCI_B0__) || defined(__MSP430_HAS_USCI_B1__) || defined(__MSP430_HAS_USCI_B2__) || defined(__MSP430_HAS_USCI_B3__) + #define __MSP430_HAS_USCI_Bx__ +#endif +#if defined(__MSP430_HAS_EUSCI_A0__) || defined(__MSP430_HAS_EUSCI_A1__) || defined(__MSP430_HAS_EUSCI_A2__) || defined(__MSP430_HAS_EUSCI_A3__) + #define __MSP430_HAS_EUSCI_Ax__ +#endif +#if defined(__MSP430_HAS_EUSCI_B0__) || defined(__MSP430_HAS_EUSCI_B1__) || defined(__MSP430_HAS_EUSCI_B2__) || defined(__MSP430_HAS_EUSCI_B3__) + #define __MSP430_HAS_EUSCI_Bx__ +#endif +#ifdef __MSP430_HAS_EUSCI_B0__ + #define __MSP430_HAS_EUSCI_Bx__ +#endif + +/************************************************************ +* ADC12_B +************************************************************/ +#ifdef __MSP430_HAS_ADC12_B__ /* Definition to show that Module is available */ + +#define OFS_ADC12CTL0 (0x0000) /* ADC12 B Control 0 */ +#define OFS_ADC12CTL0_L OFS_ADC12CTL0 +#define OFS_ADC12CTL0_H OFS_ADC12CTL0+1 +#define OFS_ADC12CTL1 (0x0002) /* ADC12 B Control 1 */ +#define OFS_ADC12CTL1_L OFS_ADC12CTL1 +#define OFS_ADC12CTL1_H OFS_ADC12CTL1+1 +#define OFS_ADC12CTL2 (0x0004) /* ADC12 B Control 2 */ +#define OFS_ADC12CTL2_L OFS_ADC12CTL2 +#define OFS_ADC12CTL2_H OFS_ADC12CTL2+1 +#define OFS_ADC12CTL3 (0x0006) /* ADC12 B Control 3 */ +#define OFS_ADC12CTL3_L OFS_ADC12CTL3 +#define OFS_ADC12CTL3_H OFS_ADC12CTL3+1 +#define OFS_ADC12LO (0x0008) /* ADC12 B Window Comparator High Threshold */ +#define OFS_ADC12LO_L OFS_ADC12LO +#define OFS_ADC12LO_H OFS_ADC12LO+1 +#define OFS_ADC12HI (0x000A) /* ADC12 B Window Comparator High Threshold */ +#define OFS_ADC12HI_L OFS_ADC12HI +#define OFS_ADC12HI_H OFS_ADC12HI+1 +#define OFS_ADC12IFGR0 (0x000C) /* ADC12 B Interrupt Flag 0 */ +#define OFS_ADC12IFGR0_L OFS_ADC12IFGR0 +#define OFS_ADC12IFGR0_H OFS_ADC12IFGR0+1 +#define OFS_ADC12IFGR1 (0x000E) /* ADC12 B Interrupt Flag 1 */ +#define OFS_ADC12IFGR1_L OFS_ADC12IFGR1 +#define OFS_ADC12IFGR1_H OFS_ADC12IFGR1+1 +#define OFS_ADC12IFGR2 (0x0010) /* ADC12 B Interrupt Flag 2 */ +#define OFS_ADC12IFGR2_L OFS_ADC12IFGR2 +#define OFS_ADC12IFGR2_H OFS_ADC12IFGR2+1 +#define OFS_ADC12IER0 (0x0012) /* ADC12 B Interrupt Enable 0 */ +#define OFS_ADC12IER0_L OFS_ADC12IER0 +#define OFS_ADC12IER0_H OFS_ADC12IER0+1 +#define OFS_ADC12IER1 (0x0014) /* ADC12 B Interrupt Enable 1 */ +#define OFS_ADC12IER1_L OFS_ADC12IER1 +#define OFS_ADC12IER1_H OFS_ADC12IER1+1 +#define OFS_ADC12IER2 (0x0016) /* ADC12 B Interrupt Enable 2 */ +#define OFS_ADC12IER2_L OFS_ADC12IER2 +#define OFS_ADC12IER2_H OFS_ADC12IER2+1 +#define OFS_ADC12IV (0x0018) /* ADC12 B Interrupt Vector Word */ +#define OFS_ADC12IV_L OFS_ADC12IV +#define OFS_ADC12IV_H OFS_ADC12IV+1 + +#define OFS_ADC12MCTL0 (0x0020) /* ADC12 Memory Control 0 */ +#define OFS_ADC12MCTL0_L OFS_ADC12MCTL0 +#define OFS_ADC12MCTL0_H OFS_ADC12MCTL0+1 +#define OFS_ADC12MCTL1 (0x0022) /* ADC12 Memory Control 1 */ +#define OFS_ADC12MCTL1_L OFS_ADC12MCTL1 +#define OFS_ADC12MCTL1_H OFS_ADC12MCTL1+1 +#define OFS_ADC12MCTL2 (0x0024) /* ADC12 Memory Control 2 */ +#define OFS_ADC12MCTL2_L OFS_ADC12MCTL2 +#define OFS_ADC12MCTL2_H OFS_ADC12MCTL2+1 +#define OFS_ADC12MCTL3 (0x0026) /* ADC12 Memory Control 3 */ +#define OFS_ADC12MCTL3_L OFS_ADC12MCTL3 +#define OFS_ADC12MCTL3_H OFS_ADC12MCTL3+1 +#define OFS_ADC12MCTL4 (0x0028) /* ADC12 Memory Control 4 */ +#define OFS_ADC12MCTL4_L OFS_ADC12MCTL4 +#define OFS_ADC12MCTL4_H OFS_ADC12MCTL4+1 +#define OFS_ADC12MCTL5 (0x002A) /* ADC12 Memory Control 5 */ +#define OFS_ADC12MCTL5_L OFS_ADC12MCTL5 +#define OFS_ADC12MCTL5_H OFS_ADC12MCTL5+1 +#define OFS_ADC12MCTL6 (0x002C) /* ADC12 Memory Control 6 */ +#define OFS_ADC12MCTL6_L OFS_ADC12MCTL6 +#define OFS_ADC12MCTL6_H OFS_ADC12MCTL6+1 +#define OFS_ADC12MCTL7 (0x002E) /* ADC12 Memory Control 7 */ +#define OFS_ADC12MCTL7_L OFS_ADC12MCTL7 +#define OFS_ADC12MCTL7_H OFS_ADC12MCTL7+1 +#define OFS_ADC12MCTL8 (0x0030) /* ADC12 Memory Control 8 */ +#define OFS_ADC12MCTL8_L OFS_ADC12MCTL8 +#define OFS_ADC12MCTL8_H OFS_ADC12MCTL8+1 +#define OFS_ADC12MCTL9 (0x0032) /* ADC12 Memory Control 9 */ +#define OFS_ADC12MCTL9_L OFS_ADC12MCTL9 +#define OFS_ADC12MCTL9_H OFS_ADC12MCTL9+1 +#define OFS_ADC12MCTL10 (0x0034) /* ADC12 Memory Control 10 */ +#define OFS_ADC12MCTL10_L OFS_ADC12MCTL10 +#define OFS_ADC12MCTL10_H OFS_ADC12MCTL10+1 +#define OFS_ADC12MCTL11 (0x0036) /* ADC12 Memory Control 11 */ +#define OFS_ADC12MCTL11_L OFS_ADC12MCTL11 +#define OFS_ADC12MCTL11_H OFS_ADC12MCTL11+1 +#define OFS_ADC12MCTL12 (0x0038) /* ADC12 Memory Control 12 */ +#define OFS_ADC12MCTL12_L OFS_ADC12MCTL12 +#define OFS_ADC12MCTL12_H OFS_ADC12MCTL12+1 +#define OFS_ADC12MCTL13 (0x003A) /* ADC12 Memory Control 13 */ +#define OFS_ADC12MCTL13_L OFS_ADC12MCTL13 +#define OFS_ADC12MCTL13_H OFS_ADC12MCTL13+1 +#define OFS_ADC12MCTL14 (0x003C) /* ADC12 Memory Control 14 */ +#define OFS_ADC12MCTL14_L OFS_ADC12MCTL14 +#define OFS_ADC12MCTL14_H OFS_ADC12MCTL14+1 +#define OFS_ADC12MCTL15 (0x003E) /* ADC12 Memory Control 15 */ +#define OFS_ADC12MCTL15_L OFS_ADC12MCTL15 +#define OFS_ADC12MCTL15_H OFS_ADC12MCTL15+1 +#define OFS_ADC12MCTL16 (0x0040) /* ADC12 Memory Control 16 */ +#define OFS_ADC12MCTL16_L OFS_ADC12MCTL16 +#define OFS_ADC12MCTL16_H OFS_ADC12MCTL16+1 +#define OFS_ADC12MCTL17 (0x0042) /* ADC12 Memory Control 17 */ +#define OFS_ADC12MCTL17_L OFS_ADC12MCTL17 +#define OFS_ADC12MCTL17_H OFS_ADC12MCTL17+1 +#define OFS_ADC12MCTL18 (0x0044) /* ADC12 Memory Control 18 */ +#define OFS_ADC12MCTL18_L OFS_ADC12MCTL18 +#define OFS_ADC12MCTL18_H OFS_ADC12MCTL18+1 +#define OFS_ADC12MCTL19 (0x0046) /* ADC12 Memory Control 19 */ +#define OFS_ADC12MCTL19_L OFS_ADC12MCTL19 +#define OFS_ADC12MCTL19_H OFS_ADC12MCTL19+1 +#define OFS_ADC12MCTL20 (0x0048) /* ADC12 Memory Control 20 */ +#define OFS_ADC12MCTL20_L OFS_ADC12MCTL20 +#define OFS_ADC12MCTL20_H OFS_ADC12MCTL20+1 +#define OFS_ADC12MCTL21 (0x004A) /* ADC12 Memory Control 21 */ +#define OFS_ADC12MCTL21_L OFS_ADC12MCTL21 +#define OFS_ADC12MCTL21_H OFS_ADC12MCTL21+1 +#define OFS_ADC12MCTL22 (0x004C) /* ADC12 Memory Control 22 */ +#define OFS_ADC12MCTL22_L OFS_ADC12MCTL22 +#define OFS_ADC12MCTL22_H OFS_ADC12MCTL22+1 +#define OFS_ADC12MCTL23 (0x004E) /* ADC12 Memory Control 23 */ +#define OFS_ADC12MCTL23_L OFS_ADC12MCTL23 +#define OFS_ADC12MCTL23_H OFS_ADC12MCTL23+1 +#define OFS_ADC12MCTL24 (0x0050) /* ADC12 Memory Control 24 */ +#define OFS_ADC12MCTL24_L OFS_ADC12MCTL24 +#define OFS_ADC12MCTL24_H OFS_ADC12MCTL24+1 +#define OFS_ADC12MCTL25 (0x0052) /* ADC12 Memory Control 25 */ +#define OFS_ADC12MCTL25_L OFS_ADC12MCTL25 +#define OFS_ADC12MCTL25_H OFS_ADC12MCTL25+1 +#define OFS_ADC12MCTL26 (0x0054) /* ADC12 Memory Control 26 */ +#define OFS_ADC12MCTL26_L OFS_ADC12MCTL26 +#define OFS_ADC12MCTL26_H OFS_ADC12MCTL26+1 +#define OFS_ADC12MCTL27 (0x0056) /* ADC12 Memory Control 27 */ +#define OFS_ADC12MCTL27_L OFS_ADC12MCTL27 +#define OFS_ADC12MCTL27_H OFS_ADC12MCTL27+1 +#define OFS_ADC12MCTL28 (0x0058) /* ADC12 Memory Control 28 */ +#define OFS_ADC12MCTL28_L OFS_ADC12MCTL28 +#define OFS_ADC12MCTL28_H OFS_ADC12MCTL28+1 +#define OFS_ADC12MCTL29 (0x005A) /* ADC12 Memory Control 29 */ +#define OFS_ADC12MCTL29_L OFS_ADC12MCTL29 +#define OFS_ADC12MCTL29_H OFS_ADC12MCTL29+1 +#define OFS_ADC12MCTL30 (0x005C) /* ADC12 Memory Control 30 */ +#define OFS_ADC12MCTL30_L OFS_ADC12MCTL30 +#define OFS_ADC12MCTL30_H OFS_ADC12MCTL30+1 +#define OFS_ADC12MCTL31 (0x005E) /* ADC12 Memory Control 31 */ +#define OFS_ADC12MCTL31_L OFS_ADC12MCTL31 +#define OFS_ADC12MCTL31_H OFS_ADC12MCTL31+1 +#define ADC12MCTL_ ADC12MCTL /* ADC12 Memory Control */ +#ifdef __ASM_HEADER__ +#define ADC12MCTL ADC12MCTL0 /* ADC12 Memory Control (for assembler) */ +#else +#define ADC12MCTL ((char*) &ADC12MCTL0) /* ADC12 Memory Control (for C) */ +#endif + +#define OFS_ADC12MEM0 (0x0060) /* ADC12 Conversion Memory 0 */ +#define OFS_ADC12MEM0_L OFS_ADC12MEM0 +#define OFS_ADC12MEM0_H OFS_ADC12MEM0+1 +#define OFS_ADC12MEM1 (0x0062) /* ADC12 Conversion Memory 1 */ +#define OFS_ADC12MEM1_L OFS_ADC12MEM1 +#define OFS_ADC12MEM1_H OFS_ADC12MEM1+1 +#define OFS_ADC12MEM2 (0x0064) /* ADC12 Conversion Memory 2 */ +#define OFS_ADC12MEM2_L OFS_ADC12MEM2 +#define OFS_ADC12MEM2_H OFS_ADC12MEM2+1 +#define OFS_ADC12MEM3 (0x0066) /* ADC12 Conversion Memory 3 */ +#define OFS_ADC12MEM3_L OFS_ADC12MEM3 +#define OFS_ADC12MEM3_H OFS_ADC12MEM3+1 +#define OFS_ADC12MEM4 (0x0068) /* ADC12 Conversion Memory 4 */ +#define OFS_ADC12MEM4_L OFS_ADC12MEM4 +#define OFS_ADC12MEM4_H OFS_ADC12MEM4+1 +#define OFS_ADC12MEM5 (0x006A) /* ADC12 Conversion Memory 5 */ +#define OFS_ADC12MEM5_L OFS_ADC12MEM5 +#define OFS_ADC12MEM5_H OFS_ADC12MEM5+1 +#define OFS_ADC12MEM6 (0x006C) /* ADC12 Conversion Memory 6 */ +#define OFS_ADC12MEM6_L OFS_ADC12MEM6 +#define OFS_ADC12MEM6_H OFS_ADC12MEM6+1 +#define OFS_ADC12MEM7 (0x006E) /* ADC12 Conversion Memory 7 */ +#define OFS_ADC12MEM7_L OFS_ADC12MEM7 +#define OFS_ADC12MEM7_H OFS_ADC12MEM7+1 +#define OFS_ADC12MEM8 (0x0070) /* ADC12 Conversion Memory 8 */ +#define OFS_ADC12MEM8_L OFS_ADC12MEM8 +#define OFS_ADC12MEM8_H OFS_ADC12MEM8+1 +#define OFS_ADC12MEM9 (0x0072) /* ADC12 Conversion Memory 9 */ +#define OFS_ADC12MEM9_L OFS_ADC12MEM9 +#define OFS_ADC12MEM9_H OFS_ADC12MEM9+1 +#define OFS_ADC12MEM10 (0x0074) /* ADC12 Conversion Memory 10 */ +#define OFS_ADC12MEM10_L OFS_ADC12MEM10 +#define OFS_ADC12MEM10_H OFS_ADC12MEM10+1 +#define OFS_ADC12MEM11 (0x0076) /* ADC12 Conversion Memory 11 */ +#define OFS_ADC12MEM11_L OFS_ADC12MEM11 +#define OFS_ADC12MEM11_H OFS_ADC12MEM11+1 +#define OFS_ADC12MEM12 (0x0078) /* ADC12 Conversion Memory 12 */ +#define OFS_ADC12MEM12_L OFS_ADC12MEM12 +#define OFS_ADC12MEM12_H OFS_ADC12MEM12+1 +#define OFS_ADC12MEM13 (0x007A) /* ADC12 Conversion Memory 13 */ +#define OFS_ADC12MEM13_L OFS_ADC12MEM13 +#define OFS_ADC12MEM13_H OFS_ADC12MEM13+1 +#define OFS_ADC12MEM14 (0x007C) /* ADC12 Conversion Memory 14 */ +#define OFS_ADC12MEM14_L OFS_ADC12MEM14 +#define OFS_ADC12MEM14_H OFS_ADC12MEM14+1 +#define OFS_ADC12MEM15 (0x007E) /* ADC12 Conversion Memory 15 */ +#define OFS_ADC12MEM15_L OFS_ADC12MEM15 +#define OFS_ADC12MEM15_H OFS_ADC12MEM15+1 +#define OFS_ADC12MEM16 (0x0080) /* ADC12 Conversion Memory 16 */ +#define OFS_ADC12MEM16_L OFS_ADC12MEM16 +#define OFS_ADC12MEM16_H OFS_ADC12MEM16+1 +#define OFS_ADC12MEM17 (0x0082) /* ADC12 Conversion Memory 17 */ +#define OFS_ADC12MEM17_L OFS_ADC12MEM17 +#define OFS_ADC12MEM17_H OFS_ADC12MEM17+1 +#define OFS_ADC12MEM18 (0x0084) /* ADC12 Conversion Memory 18 */ +#define OFS_ADC12MEM18_L OFS_ADC12MEM18 +#define OFS_ADC12MEM18_H OFS_ADC12MEM18+1 +#define OFS_ADC12MEM19 (0x0086) /* ADC12 Conversion Memory 19 */ +#define OFS_ADC12MEM19_L OFS_ADC12MEM19 +#define OFS_ADC12MEM19_H OFS_ADC12MEM19+1 +#define OFS_ADC12MEM20 (0x0088) /* ADC12 Conversion Memory 20 */ +#define OFS_ADC12MEM20_L OFS_ADC12MEM20 +#define OFS_ADC12MEM20_H OFS_ADC12MEM20+1 +#define OFS_ADC12MEM21 (0x008A) /* ADC12 Conversion Memory 21 */ +#define OFS_ADC12MEM21_L OFS_ADC12MEM21 +#define OFS_ADC12MEM21_H OFS_ADC12MEM21+1 +#define OFS_ADC12MEM22 (0x008C) /* ADC12 Conversion Memory 22 */ +#define OFS_ADC12MEM22_L OFS_ADC12MEM22 +#define OFS_ADC12MEM22_H OFS_ADC12MEM22+1 +#define OFS_ADC12MEM23 (0x008E) /* ADC12 Conversion Memory 23 */ +#define OFS_ADC12MEM23_L OFS_ADC12MEM23 +#define OFS_ADC12MEM23_H OFS_ADC12MEM23+1 +#define OFS_ADC12MEM24 (0x0090) /* ADC12 Conversion Memory 24 */ +#define OFS_ADC12MEM24_L OFS_ADC12MEM24 +#define OFS_ADC12MEM24_H OFS_ADC12MEM24+1 +#define OFS_ADC12MEM25 (0x0092) /* ADC12 Conversion Memory 25 */ +#define OFS_ADC12MEM25_L OFS_ADC12MEM25 +#define OFS_ADC12MEM25_H OFS_ADC12MEM25+1 +#define OFS_ADC12MEM26 (0x0094) /* ADC12 Conversion Memory 26 */ +#define OFS_ADC12MEM26_L OFS_ADC12MEM26 +#define OFS_ADC12MEM26_H OFS_ADC12MEM26+1 +#define OFS_ADC12MEM27 (0x0096) /* ADC12 Conversion Memory 27 */ +#define OFS_ADC12MEM27_L OFS_ADC12MEM27 +#define OFS_ADC12MEM27_H OFS_ADC12MEM27+1 +#define OFS_ADC12MEM28 (0x0098) /* ADC12 Conversion Memory 28 */ +#define OFS_ADC12MEM28_L OFS_ADC12MEM28 +#define OFS_ADC12MEM28_H OFS_ADC12MEM28+1 +#define OFS_ADC12MEM29 (0x009A) /* ADC12 Conversion Memory 29 */ +#define OFS_ADC12MEM29_L OFS_ADC12MEM29 +#define OFS_ADC12MEM29_H OFS_ADC12MEM29+1 +#define OFS_ADC12MEM30 (0x009C) /* ADC12 Conversion Memory 30 */ +#define OFS_ADC12MEM30_L OFS_ADC12MEM30 +#define OFS_ADC12MEM30_H OFS_ADC12MEM30+1 +#define OFS_ADC12MEM31 (0x009E) /* ADC12 Conversion Memory 31 */ +#define OFS_ADC12MEM31_L OFS_ADC12MEM31 +#define OFS_ADC12MEM31_H OFS_ADC12MEM31+1 +#define ADC12MEM_ ADC12MEM /* ADC12 Conversion Memory */ +#ifdef __ASM_HEADER__ +#define ADC12MEM ADC12MEM0 /* ADC12 Conversion Memory (for assembler) */ +#else +#define ADC12MEM ((int*) &ADC12MEM0) /* ADC12 Conversion Memory (for C) */ +#endif + +/* ADC12CTL0 Control Bits */ +#define ADC12SC (0x0001) /* ADC12 Start Conversion */ +#define ADC12ENC (0x0002) /* ADC12 Enable Conversion */ +#define ADC12ON (0x0010) /* ADC12 On/enable */ +#define ADC12MSC (0x0080) /* ADC12 Multiple SampleConversion */ +#define ADC12SHT00 (0x0100) /* ADC12 Sample Hold 0 Select Bit: 0 */ +#define ADC12SHT01 (0x0200) /* ADC12 Sample Hold 0 Select Bit: 1 */ +#define ADC12SHT02 (0x0400) /* ADC12 Sample Hold 0 Select Bit: 2 */ +#define ADC12SHT03 (0x0800) /* ADC12 Sample Hold 0 Select Bit: 3 */ +#define ADC12SHT10 (0x1000) /* ADC12 Sample Hold 1 Select Bit: 0 */ +#define ADC12SHT11 (0x2000) /* ADC12 Sample Hold 1 Select Bit: 1 */ +#define ADC12SHT12 (0x4000) /* ADC12 Sample Hold 1 Select Bit: 2 */ +#define ADC12SHT13 (0x8000) /* ADC12 Sample Hold 1 Select Bit: 3 */ + +/* ADC12CTL0 Control Bits */ +#define ADC12SC_L (0x0001) /* ADC12 Start Conversion */ +#define ADC12ENC_L (0x0002) /* ADC12 Enable Conversion */ +#define ADC12ON_L (0x0010) /* ADC12 On/enable */ +#define ADC12MSC_L (0x0080) /* ADC12 Multiple SampleConversion */ + +/* ADC12CTL0 Control Bits */ +#define ADC12SHT00_H (0x0001) /* ADC12 Sample Hold 0 Select Bit: 0 */ +#define ADC12SHT01_H (0x0002) /* ADC12 Sample Hold 0 Select Bit: 1 */ +#define ADC12SHT02_H (0x0004) /* ADC12 Sample Hold 0 Select Bit: 2 */ +#define ADC12SHT03_H (0x0008) /* ADC12 Sample Hold 0 Select Bit: 3 */ +#define ADC12SHT10_H (0x0010) /* ADC12 Sample Hold 1 Select Bit: 0 */ +#define ADC12SHT11_H (0x0020) /* ADC12 Sample Hold 1 Select Bit: 1 */ +#define ADC12SHT12_H (0x0040) /* ADC12 Sample Hold 1 Select Bit: 2 */ +#define ADC12SHT13_H (0x0080) /* ADC12 Sample Hold 1 Select Bit: 3 */ + +#define ADC12SHT0_0 (0*0x100u) /* ADC12 Sample Hold 0 Select Bit: 0 */ +#define ADC12SHT0_1 (1*0x100u) /* ADC12 Sample Hold 0 Select Bit: 1 */ +#define ADC12SHT0_2 (2*0x100u) /* ADC12 Sample Hold 0 Select Bit: 2 */ +#define ADC12SHT0_3 (3*0x100u) /* ADC12 Sample Hold 0 Select Bit: 3 */ +#define ADC12SHT0_4 (4*0x100u) /* ADC12 Sample Hold 0 Select Bit: 4 */ +#define ADC12SHT0_5 (5*0x100u) /* ADC12 Sample Hold 0 Select Bit: 5 */ +#define ADC12SHT0_6 (6*0x100u) /* ADC12 Sample Hold 0 Select Bit: 6 */ +#define ADC12SHT0_7 (7*0x100u) /* ADC12 Sample Hold 0 Select Bit: 7 */ +#define ADC12SHT0_8 (8*0x100u) /* ADC12 Sample Hold 0 Select Bit: 8 */ +#define ADC12SHT0_9 (9*0x100u) /* ADC12 Sample Hold 0 Select Bit: 9 */ +#define ADC12SHT0_10 (10*0x100u) /* ADC12 Sample Hold 0 Select Bit: 10 */ +#define ADC12SHT0_11 (11*0x100u) /* ADC12 Sample Hold 0 Select Bit: 11 */ +#define ADC12SHT0_12 (12*0x100u) /* ADC12 Sample Hold 0 Select Bit: 12 */ +#define ADC12SHT0_13 (13*0x100u) /* ADC12 Sample Hold 0 Select Bit: 13 */ +#define ADC12SHT0_14 (14*0x100u) /* ADC12 Sample Hold 0 Select Bit: 14 */ +#define ADC12SHT0_15 (15*0x100u) /* ADC12 Sample Hold 0 Select Bit: 15 */ + +#define ADC12SHT1_0 (0*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 0 */ +#define ADC12SHT1_1 (1*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 1 */ +#define ADC12SHT1_2 (2*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 2 */ +#define ADC12SHT1_3 (3*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 3 */ +#define ADC12SHT1_4 (4*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 4 */ +#define ADC12SHT1_5 (5*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 5 */ +#define ADC12SHT1_6 (6*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 6 */ +#define ADC12SHT1_7 (7*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 7 */ +#define ADC12SHT1_8 (8*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 8 */ +#define ADC12SHT1_9 (9*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 9 */ +#define ADC12SHT1_10 (10*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 10 */ +#define ADC12SHT1_11 (11*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 11 */ +#define ADC12SHT1_12 (12*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 12 */ +#define ADC12SHT1_13 (13*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 13 */ +#define ADC12SHT1_14 (14*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 14 */ +#define ADC12SHT1_15 (15*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 15 */ + +/* ADC12CTL1 Control Bits */ +#define ADC12BUSY (0x0001) /* ADC12 Busy */ +#define ADC12CONSEQ0 (0x0002) /* ADC12 Conversion Sequence Select Bit: 0 */ +#define ADC12CONSEQ1 (0x0004) /* ADC12 Conversion Sequence Select Bit: 1 */ +#define ADC12SSEL0 (0x0008) /* ADC12 Clock Source Select Bit: 0 */ +#define ADC12SSEL1 (0x0010) /* ADC12 Clock Source Select Bit: 1 */ +#define ADC12DIV0 (0x0020) /* ADC12 Clock Divider Select Bit: 0 */ +#define ADC12DIV1 (0x0040) /* ADC12 Clock Divider Select Bit: 1 */ +#define ADC12DIV2 (0x0080) /* ADC12 Clock Divider Select Bit: 2 */ +#define ADC12ISSH (0x0100) /* ADC12 Invert Sample Hold Signal */ +#define ADC12SHP (0x0200) /* ADC12 Sample/Hold Pulse Mode */ +#define ADC12SHS0 (0x0400) /* ADC12 Sample/Hold Source Bit: 0 */ +#define ADC12SHS1 (0x0800) /* ADC12 Sample/Hold Source Bit: 1 */ +#define ADC12SHS2 (0x1000) /* ADC12 Sample/Hold Source Bit: 2 */ +#define ADC12PDIV0 (0x2000) /* ADC12 Predivider Bit: 0 */ +#define ADC12PDIV1 (0x4000) /* ADC12 Predivider Bit: 1 */ + +/* ADC12CTL1 Control Bits */ +#define ADC12BUSY_L (0x0001) /* ADC12 Busy */ +#define ADC12CONSEQ0_L (0x0002) /* ADC12 Conversion Sequence Select Bit: 0 */ +#define ADC12CONSEQ1_L (0x0004) /* ADC12 Conversion Sequence Select Bit: 1 */ +#define ADC12SSEL0_L (0x0008) /* ADC12 Clock Source Select Bit: 0 */ +#define ADC12SSEL1_L (0x0010) /* ADC12 Clock Source Select Bit: 1 */ +#define ADC12DIV0_L (0x0020) /* ADC12 Clock Divider Select Bit: 0 */ +#define ADC12DIV1_L (0x0040) /* ADC12 Clock Divider Select Bit: 1 */ +#define ADC12DIV2_L (0x0080) /* ADC12 Clock Divider Select Bit: 2 */ + +/* ADC12CTL1 Control Bits */ +#define ADC12ISSH_H (0x0001) /* ADC12 Invert Sample Hold Signal */ +#define ADC12SHP_H (0x0002) /* ADC12 Sample/Hold Pulse Mode */ +#define ADC12SHS0_H (0x0004) /* ADC12 Sample/Hold Source Bit: 0 */ +#define ADC12SHS1_H (0x0008) /* ADC12 Sample/Hold Source Bit: 1 */ +#define ADC12SHS2_H (0x0010) /* ADC12 Sample/Hold Source Bit: 2 */ +#define ADC12PDIV0_H (0x0020) /* ADC12 Predivider Bit: 0 */ +#define ADC12PDIV1_H (0x0040) /* ADC12 Predivider Bit: 1 */ + +#define ADC12CONSEQ_0 (0*0x0002u) /* ADC12 Conversion Sequence Select: 0 */ +#define ADC12CONSEQ_1 (1*0x0002u) /* ADC12 Conversion Sequence Select: 1 */ +#define ADC12CONSEQ_2 (2*0x0002u) /* ADC12 Conversion Sequence Select: 2 */ +#define ADC12CONSEQ_3 (3*0x0002u) /* ADC12 Conversion Sequence Select: 3 */ + +#define ADC12SSEL_0 (0*0x0008u) /* ADC12 Clock Source Select: 0 */ +#define ADC12SSEL_1 (1*0x0008u) /* ADC12 Clock Source Select: 1 */ +#define ADC12SSEL_2 (2*0x0008u) /* ADC12 Clock Source Select: 2 */ +#define ADC12SSEL_3 (3*0x0008u) /* ADC12 Clock Source Select: 3 */ + +#define ADC12DIV_0 (0*0x0020u) /* ADC12 Clock Divider Select: 0 */ +#define ADC12DIV_1 (1*0x0020u) /* ADC12 Clock Divider Select: 1 */ +#define ADC12DIV_2 (2*0x0020u) /* ADC12 Clock Divider Select: 2 */ +#define ADC12DIV_3 (3*0x0020u) /* ADC12 Clock Divider Select: 3 */ +#define ADC12DIV_4 (4*0x0020u) /* ADC12 Clock Divider Select: 4 */ +#define ADC12DIV_5 (5*0x0020u) /* ADC12 Clock Divider Select: 5 */ +#define ADC12DIV_6 (6*0x0020u) /* ADC12 Clock Divider Select: 6 */ +#define ADC12DIV_7 (7*0x0020u) /* ADC12 Clock Divider Select: 7 */ + +#define ADC12SHS_0 (0*0x0400u) /* ADC12 Sample/Hold Source: 0 */ +#define ADC12SHS_1 (1*0x0400u) /* ADC12 Sample/Hold Source: 1 */ +#define ADC12SHS_2 (2*0x0400u) /* ADC12 Sample/Hold Source: 2 */ +#define ADC12SHS_3 (3*0x0400u) /* ADC12 Sample/Hold Source: 3 */ +#define ADC12SHS_4 (4*0x0400u) /* ADC12 Sample/Hold Source: 4 */ +#define ADC12SHS_5 (5*0x0400u) /* ADC12 Sample/Hold Source: 5 */ +#define ADC12SHS_6 (6*0x0400u) /* ADC12 Sample/Hold Source: 6 */ +#define ADC12SHS_7 (7*0x0400u) /* ADC12 Sample/Hold Source: 7 */ + +#define ADC12PDIV_0 (0*0x2000u) /* ADC12 Clock predivider Select 0 */ +#define ADC12PDIV_1 (1*0x2000u) /* ADC12 Clock predivider Select 1 */ +#define ADC12PDIV_2 (2*0x2000u) /* ADC12 Clock predivider Select 2 */ +#define ADC12PDIV_3 (3*0x2000u) /* ADC12 Clock predivider Select 3 */ +#define ADC12PDIV__1 (0*0x2000u) /* ADC12 Clock predivider Select: /1 */ +#define ADC12PDIV__4 (1*0x2000u) /* ADC12 Clock predivider Select: /4 */ +#define ADC12PDIV__32 (2*0x2000u) /* ADC12 Clock predivider Select: /32 */ +#define ADC12PDIV__64 (3*0x2000u) /* ADC12 Clock predivider Select: /64 */ + +/* ADC12CTL2 Control Bits */ +#define ADC12PWRMD (0x0001) /* ADC12 Power Mode */ +#define ADC12DF (0x0008) /* ADC12 Data Format */ +#define ADC12RES0 (0x0010) /* ADC12 Resolution Bit: 0 */ +#define ADC12RES1 (0x0020) /* ADC12 Resolution Bit: 1 */ + +/* ADC12CTL2 Control Bits */ +#define ADC12PWRMD_L (0x0001) /* ADC12 Power Mode */ +#define ADC12DF_L (0x0008) /* ADC12 Data Format */ +#define ADC12RES0_L (0x0010) /* ADC12 Resolution Bit: 0 */ +#define ADC12RES1_L (0x0020) /* ADC12 Resolution Bit: 1 */ + +#define ADC12RES_0 (0x0000) /* ADC12+ Resolution : 8 Bit */ +#define ADC12RES_1 (0x0010) /* ADC12+ Resolution : 10 Bit */ +#define ADC12RES_2 (0x0020) /* ADC12+ Resolution : 12 Bit */ +#define ADC12RES_3 (0x0030) /* ADC12+ Resolution : reserved */ + +#define ADC12RES__8BIT (0x0000) /* ADC12+ Resolution : 8 Bit */ +#define ADC12RES__10BIT (0x0010) /* ADC12+ Resolution : 10 Bit */ +#define ADC12RES__12BIT (0x0020) /* ADC12+ Resolution : 12 Bit */ + +/* ADC12CTL3 Control Bits */ +#define ADC12CSTARTADD0 (0x0001) /* ADC12 Conversion Start Address Bit: 0 */ +#define ADC12CSTARTADD1 (0x0002) /* ADC12 Conversion Start Address Bit: 1 */ +#define ADC12CSTARTADD2 (0x0004) /* ADC12 Conversion Start Address Bit: 2 */ +#define ADC12CSTARTADD3 (0x0008) /* ADC12 Conversion Start Address Bit: 3 */ +#define ADC12CSTARTADD4 (0x0010) /* ADC12 Conversion Start Address Bit: 4 */ +#define ADC12BATMAP (0x0040) /* ADC12 Internal AVCC/2 select */ +#define ADC12TCMAP (0x0080) /* ADC12 Internal TempSensor select */ +#define ADC12ICH0MAP (0x0100) /* ADC12 Internal Channel 0 select */ +#define ADC12ICH1MAP (0x0200) /* ADC12 Internal Channel 1 select */ +#define ADC12ICH2MAP (0x0400) /* ADC12 Internal Channel 2 select */ +#define ADC12ICH3MAP (0x0800) /* ADC12 Internal Channel 3 select */ + +/* ADC12CTL3 Control Bits */ +#define ADC12CSTARTADD0_L (0x0001) /* ADC12 Conversion Start Address Bit: 0 */ +#define ADC12CSTARTADD1_L (0x0002) /* ADC12 Conversion Start Address Bit: 1 */ +#define ADC12CSTARTADD2_L (0x0004) /* ADC12 Conversion Start Address Bit: 2 */ +#define ADC12CSTARTADD3_L (0x0008) /* ADC12 Conversion Start Address Bit: 3 */ +#define ADC12CSTARTADD4_L (0x0010) /* ADC12 Conversion Start Address Bit: 4 */ +#define ADC12BATMAP_L (0x0040) /* ADC12 Internal AVCC/2 select */ +#define ADC12TCMAP_L (0x0080) /* ADC12 Internal TempSensor select */ + +/* ADC12CTL3 Control Bits */ +#define ADC12ICH0MAP_H (0x0001) /* ADC12 Internal Channel 0 select */ +#define ADC12ICH1MAP_H (0x0002) /* ADC12 Internal Channel 1 select */ +#define ADC12ICH2MAP_H (0x0004) /* ADC12 Internal Channel 2 select */ +#define ADC12ICH3MAP_H (0x0008) /* ADC12 Internal Channel 3 select */ + +#define ADC12CSTARTADD_0 ( 0*0x0001u) /* ADC12 Conversion Start Address: 0 */ +#define ADC12CSTARTADD_1 ( 1*0x0001u) /* ADC12 Conversion Start Address: 1 */ +#define ADC12CSTARTADD_2 ( 2*0x0001u) /* ADC12 Conversion Start Address: 2 */ +#define ADC12CSTARTADD_3 ( 3*0x0001u) /* ADC12 Conversion Start Address: 3 */ +#define ADC12CSTARTADD_4 ( 4*0x0001u) /* ADC12 Conversion Start Address: 4 */ +#define ADC12CSTARTADD_5 ( 5*0x0001u) /* ADC12 Conversion Start Address: 5 */ +#define ADC12CSTARTADD_6 ( 6*0x0001u) /* ADC12 Conversion Start Address: 6 */ +#define ADC12CSTARTADD_7 ( 7*0x0001u) /* ADC12 Conversion Start Address: 7 */ +#define ADC12CSTARTADD_8 ( 8*0x0001u) /* ADC12 Conversion Start Address: 8 */ +#define ADC12CSTARTADD_9 ( 9*0x0001u) /* ADC12 Conversion Start Address: 9 */ +#define ADC12CSTARTADD_10 (10*0x0001u) /* ADC12 Conversion Start Address: 10 */ +#define ADC12CSTARTADD_11 (11*0x0001u) /* ADC12 Conversion Start Address: 11 */ +#define ADC12CSTARTADD_12 (12*0x0001u) /* ADC12 Conversion Start Address: 12 */ +#define ADC12CSTARTADD_13 (13*0x0001u) /* ADC12 Conversion Start Address: 13 */ +#define ADC12CSTARTADD_14 (14*0x0001u) /* ADC12 Conversion Start Address: 14 */ +#define ADC12CSTARTADD_15 (15*0x0001u) /* ADC12 Conversion Start Address: 15 */ +#define ADC12CSTARTADD_16 (16*0x0001u) /* ADC12 Conversion Start Address: 16 */ +#define ADC12CSTARTADD_17 (17*0x0001u) /* ADC12 Conversion Start Address: 17 */ +#define ADC12CSTARTADD_18 (18*0x0001u) /* ADC12 Conversion Start Address: 18 */ +#define ADC12CSTARTADD_19 (19*0x0001u) /* ADC12 Conversion Start Address: 19 */ +#define ADC12CSTARTADD_20 (20*0x0001u) /* ADC12 Conversion Start Address: 20 */ +#define ADC12CSTARTADD_21 (21*0x0001u) /* ADC12 Conversion Start Address: 21 */ +#define ADC12CSTARTADD_22 (22*0x0001u) /* ADC12 Conversion Start Address: 22 */ +#define ADC12CSTARTADD_23 (23*0x0001u) /* ADC12 Conversion Start Address: 23 */ +#define ADC12CSTARTADD_24 (24*0x0001u) /* ADC12 Conversion Start Address: 24 */ +#define ADC12CSTARTADD_25 (25*0x0001u) /* ADC12 Conversion Start Address: 25 */ +#define ADC12CSTARTADD_26 (26*0x0001u) /* ADC12 Conversion Start Address: 26 */ +#define ADC12CSTARTADD_27 (27*0x0001u) /* ADC12 Conversion Start Address: 27 */ +#define ADC12CSTARTADD_28 (28*0x0001u) /* ADC12 Conversion Start Address: 28 */ +#define ADC12CSTARTADD_29 (29*0x0001u) /* ADC12 Conversion Start Address: 29 */ +#define ADC12CSTARTADD_30 (30*0x0001u) /* ADC12 Conversion Start Address: 30 */ +#define ADC12CSTARTADD_31 (31*0x0001u) /* ADC12 Conversion Start Address: 31 */ + +/* ADC12MCTLx Control Bits */ +#define ADC12INCH0 (0x0001) /* ADC12 Input Channel Select Bit 0 */ +#define ADC12INCH1 (0x0002) /* ADC12 Input Channel Select Bit 1 */ +#define ADC12INCH2 (0x0004) /* ADC12 Input Channel Select Bit 2 */ +#define ADC12INCH3 (0x0008) /* ADC12 Input Channel Select Bit 3 */ +#define ADC12INCH4 (0x0010) /* ADC12 Input Channel Select Bit 4 */ +#define ADC12EOS (0x0080) /* ADC12 End of Sequence */ +#define ADC12VRSEL0 (0x0100) /* ADC12 VR Select Bit 0 */ +#define ADC12VRSEL1 (0x0200) /* ADC12 VR Select Bit 1 */ +#define ADC12VRSEL2 (0x0400) /* ADC12 VR Select Bit 2 */ +#define ADC12VRSEL3 (0x0800) /* ADC12 VR Select Bit 3 */ +#define ADC12DIF (0x2000) /* ADC12 Differential mode (only for even Registers) */ +#define ADC12WINC (0x4000) /* ADC12 Comparator window enable */ + +/* ADC12MCTLx Control Bits */ +#define ADC12INCH0_L (0x0001) /* ADC12 Input Channel Select Bit 0 */ +#define ADC12INCH1_L (0x0002) /* ADC12 Input Channel Select Bit 1 */ +#define ADC12INCH2_L (0x0004) /* ADC12 Input Channel Select Bit 2 */ +#define ADC12INCH3_L (0x0008) /* ADC12 Input Channel Select Bit 3 */ +#define ADC12INCH4_L (0x0010) /* ADC12 Input Channel Select Bit 4 */ +#define ADC12EOS_L (0x0080) /* ADC12 End of Sequence */ + +/* ADC12MCTLx Control Bits */ +#define ADC12VRSEL0_H (0x0001) /* ADC12 VR Select Bit 0 */ +#define ADC12VRSEL1_H (0x0002) /* ADC12 VR Select Bit 1 */ +#define ADC12VRSEL2_H (0x0004) /* ADC12 VR Select Bit 2 */ +#define ADC12VRSEL3_H (0x0008) /* ADC12 VR Select Bit 3 */ +#define ADC12DIF_H (0x0020) /* ADC12 Differential mode (only for even Registers) */ +#define ADC12WINC_H (0x0040) /* ADC12 Comparator window enable */ + +#define ADC12INCH_0 (0x0000) /* ADC12 Input Channel 0 */ +#define ADC12INCH_1 (0x0001) /* ADC12 Input Channel 1 */ +#define ADC12INCH_2 (0x0002) /* ADC12 Input Channel 2 */ +#define ADC12INCH_3 (0x0003) /* ADC12 Input Channel 3 */ +#define ADC12INCH_4 (0x0004) /* ADC12 Input Channel 4 */ +#define ADC12INCH_5 (0x0005) /* ADC12 Input Channel 5 */ +#define ADC12INCH_6 (0x0006) /* ADC12 Input Channel 6 */ +#define ADC12INCH_7 (0x0007) /* ADC12 Input Channel 7 */ +#define ADC12INCH_8 (0x0008) /* ADC12 Input Channel 8 */ +#define ADC12INCH_9 (0x0009) /* ADC12 Input Channel 9 */ +#define ADC12INCH_10 (0x000A) /* ADC12 Input Channel 10 */ +#define ADC12INCH_11 (0x000B) /* ADC12 Input Channel 11 */ +#define ADC12INCH_12 (0x000C) /* ADC12 Input Channel 12 */ +#define ADC12INCH_13 (0x000D) /* ADC12 Input Channel 13 */ +#define ADC12INCH_14 (0x000E) /* ADC12 Input Channel 14 */ +#define ADC12INCH_15 (0x000F) /* ADC12 Input Channel 15 */ +#define ADC12INCH_16 (0x0010) /* ADC12 Input Channel 16 */ +#define ADC12INCH_17 (0x0011) /* ADC12 Input Channel 17 */ +#define ADC12INCH_18 (0x0012) /* ADC12 Input Channel 18 */ +#define ADC12INCH_19 (0x0013) /* ADC12 Input Channel 19 */ +#define ADC12INCH_20 (0x0014) /* ADC12 Input Channel 20 */ +#define ADC12INCH_21 (0x0015) /* ADC12 Input Channel 21 */ +#define ADC12INCH_22 (0x0016) /* ADC12 Input Channel 22 */ +#define ADC12INCH_23 (0x0017) /* ADC12 Input Channel 23 */ +#define ADC12INCH_24 (0x0018) /* ADC12 Input Channel 24 */ +#define ADC12INCH_25 (0x0019) /* ADC12 Input Channel 25 */ +#define ADC12INCH_26 (0x001A) /* ADC12 Input Channel 26 */ +#define ADC12INCH_27 (0x001B) /* ADC12 Input Channel 27 */ +#define ADC12INCH_28 (0x001C) /* ADC12 Input Channel 28 */ +#define ADC12INCH_29 (0x001D) /* ADC12 Input Channel 29 */ +#define ADC12INCH_30 (0x001E) /* ADC12 Input Channel 30 */ +#define ADC12INCH_31 (0x001F) /* ADC12 Input Channel 31 */ + +#define ADC12VRSEL_0 (0*0x100u) /* ADC12 Select Reference 0 */ +#define ADC12VRSEL_1 (1*0x100u) /* ADC12 Select Reference 1 */ +#define ADC12VRSEL_2 (2*0x100u) /* ADC12 Select Reference 2 */ +#define ADC12VRSEL_3 (3*0x100u) /* ADC12 Select Reference 3 */ +#define ADC12VRSEL_4 (4*0x100u) /* ADC12 Select Reference 4 */ +#define ADC12VRSEL_5 (5*0x100u) /* ADC12 Select Reference 5 */ +#define ADC12VRSEL_6 (6*0x100u) /* ADC12 Select Reference 6 */ +#define ADC12VRSEL_7 (7*0x100u) /* ADC12 Select Reference 7 */ +#define ADC12VRSEL_8 (8*0x100u) /* ADC12 Select Reference 8 */ +#define ADC12VRSEL_9 (9*0x100u) /* ADC12 Select Reference 9 */ +#define ADC12VRSEL_10 (10*0x100u) /* ADC12 Select Reference 10 */ +#define ADC12VRSEL_11 (11*0x100u) /* ADC12 Select Reference 11 */ +#define ADC12VRSEL_12 (12*0x100u) /* ADC12 Select Reference 12 */ +#define ADC12VRSEL_13 (13*0x100u) /* ADC12 Select Reference 13 */ +#define ADC12VRSEL_14 (14*0x100u) /* ADC12 Select Reference 14 */ +#define ADC12VRSEL_15 (15*0x100u) /* ADC12 Select Reference 15 */ + +/* ADC12HI Control Bits */ + +/* ADC12LO Control Bits */ + +/* ADC12IER0 Control Bits */ +#define ADC12IE0 (0x0001) /* ADC12 Memory 0 Interrupt Enable */ +#define ADC12IE1 (0x0002) /* ADC12 Memory 1 Interrupt Enable */ +#define ADC12IE2 (0x0004) /* ADC12 Memory 2 Interrupt Enable */ +#define ADC12IE3 (0x0008) /* ADC12 Memory 3 Interrupt Enable */ +#define ADC12IE4 (0x0010) /* ADC12 Memory 4 Interrupt Enable */ +#define ADC12IE5 (0x0020) /* ADC12 Memory 5 Interrupt Enable */ +#define ADC12IE6 (0x0040) /* ADC12 Memory 6 Interrupt Enable */ +#define ADC12IE7 (0x0080) /* ADC12 Memory 7 Interrupt Enable */ +#define ADC12IE8 (0x0100) /* ADC12 Memory 8 Interrupt Enable */ +#define ADC12IE9 (0x0200) /* ADC12 Memory 9 Interrupt Enable */ +#define ADC12IE10 (0x0400) /* ADC12 Memory 10 Interrupt Enable */ +#define ADC12IE11 (0x0800) /* ADC12 Memory 11 Interrupt Enable */ +#define ADC12IE12 (0x1000) /* ADC12 Memory 12 Interrupt Enable */ +#define ADC12IE13 (0x2000) /* ADC12 Memory 13 Interrupt Enable */ +#define ADC12IE14 (0x4000) /* ADC12 Memory 14 Interrupt Enable */ +#define ADC12IE15 (0x8000) /* ADC12 Memory 15 Interrupt Enable */ + +/* ADC12IER0 Control Bits */ +#define ADC12IE0_L (0x0001) /* ADC12 Memory 0 Interrupt Enable */ +#define ADC12IE1_L (0x0002) /* ADC12 Memory 1 Interrupt Enable */ +#define ADC12IE2_L (0x0004) /* ADC12 Memory 2 Interrupt Enable */ +#define ADC12IE3_L (0x0008) /* ADC12 Memory 3 Interrupt Enable */ +#define ADC12IE4_L (0x0010) /* ADC12 Memory 4 Interrupt Enable */ +#define ADC12IE5_L (0x0020) /* ADC12 Memory 5 Interrupt Enable */ +#define ADC12IE6_L (0x0040) /* ADC12 Memory 6 Interrupt Enable */ +#define ADC12IE7_L (0x0080) /* ADC12 Memory 7 Interrupt Enable */ + +/* ADC12IER0 Control Bits */ +#define ADC12IE8_H (0x0001) /* ADC12 Memory 8 Interrupt Enable */ +#define ADC12IE9_H (0x0002) /* ADC12 Memory 9 Interrupt Enable */ +#define ADC12IE10_H (0x0004) /* ADC12 Memory 10 Interrupt Enable */ +#define ADC12IE11_H (0x0008) /* ADC12 Memory 11 Interrupt Enable */ +#define ADC12IE12_H (0x0010) /* ADC12 Memory 12 Interrupt Enable */ +#define ADC12IE13_H (0x0020) /* ADC12 Memory 13 Interrupt Enable */ +#define ADC12IE14_H (0x0040) /* ADC12 Memory 14 Interrupt Enable */ +#define ADC12IE15_H (0x0080) /* ADC12 Memory 15 Interrupt Enable */ + +/* ADC12IER1 Control Bits */ +#define ADC12IE16 (0x0001) /* ADC12 Memory 16 Interrupt Enable */ +#define ADC12IE17 (0x0002) /* ADC12 Memory 17 Interrupt Enable */ +#define ADC12IE18 (0x0004) /* ADC12 Memory 18 Interrupt Enable */ +#define ADC12IE19 (0x0008) /* ADC12 Memory 19 Interrupt Enable */ +#define ADC12IE20 (0x0010) /* ADC12 Memory 20 Interrupt Enable */ +#define ADC12IE21 (0x0020) /* ADC12 Memory 21 Interrupt Enable */ +#define ADC12IE22 (0x0040) /* ADC12 Memory 22 Interrupt Enable */ +#define ADC12IE23 (0x0080) /* ADC12 Memory 23 Interrupt Enable */ +#define ADC12IE24 (0x0100) /* ADC12 Memory 24 Interrupt Enable */ +#define ADC12IE25 (0x0200) /* ADC12 Memory 25 Interrupt Enable */ +#define ADC12IE26 (0x0400) /* ADC12 Memory 26 Interrupt Enable */ +#define ADC12IE27 (0x0800) /* ADC12 Memory 27 Interrupt Enable */ +#define ADC12IE28 (0x1000) /* ADC12 Memory 28 Interrupt Enable */ +#define ADC12IE29 (0x2000) /* ADC12 Memory 29 Interrupt Enable */ +#define ADC12IE30 (0x4000) /* ADC12 Memory 30 Interrupt Enable */ +#define ADC12IE31 (0x8000) /* ADC12 Memory 31 Interrupt Enable */ + +/* ADC12IER1 Control Bits */ +#define ADC12IE16_L (0x0001) /* ADC12 Memory 16 Interrupt Enable */ +#define ADC12IE17_L (0x0002) /* ADC12 Memory 17 Interrupt Enable */ +#define ADC12IE18_L (0x0004) /* ADC12 Memory 18 Interrupt Enable */ +#define ADC12IE19_L (0x0008) /* ADC12 Memory 19 Interrupt Enable */ +#define ADC12IE20_L (0x0010) /* ADC12 Memory 20 Interrupt Enable */ +#define ADC12IE21_L (0x0020) /* ADC12 Memory 21 Interrupt Enable */ +#define ADC12IE22_L (0x0040) /* ADC12 Memory 22 Interrupt Enable */ +#define ADC12IE23_L (0x0080) /* ADC12 Memory 23 Interrupt Enable */ + +/* ADC12IER1 Control Bits */ +#define ADC12IE24_H (0x0001) /* ADC12 Memory 24 Interrupt Enable */ +#define ADC12IE25_H (0x0002) /* ADC12 Memory 25 Interrupt Enable */ +#define ADC12IE26_H (0x0004) /* ADC12 Memory 26 Interrupt Enable */ +#define ADC12IE27_H (0x0008) /* ADC12 Memory 27 Interrupt Enable */ +#define ADC12IE28_H (0x0010) /* ADC12 Memory 28 Interrupt Enable */ +#define ADC12IE29_H (0x0020) /* ADC12 Memory 29 Interrupt Enable */ +#define ADC12IE30_H (0x0040) /* ADC12 Memory 30 Interrupt Enable */ +#define ADC12IE31_H (0x0080) /* ADC12 Memory 31 Interrupt Enable */ + +/* ADC12IER2 Control Bits */ +#define ADC12INIE (0x0002) /* ADC12 Interrupt enable for the inside of window of the Window comparator */ +#define ADC12LOIE (0x0004) /* ADC12 Interrupt enable for lower threshold of the Window comparator */ +#define ADC12HIIE (0x0008) /* ADC12 Interrupt enable for upper threshold of the Window comparator */ +#define ADC12OVIE (0x0010) /* ADC12 ADC12MEMx Overflow interrupt enable */ +#define ADC12TOVIE (0x0020) /* ADC12 Timer Overflow interrupt enable */ +#define ADC12RDYIE (0x0040) /* ADC12 local buffered reference ready interrupt enable */ + +/* ADC12IER2 Control Bits */ +#define ADC12INIE_L (0x0002) /* ADC12 Interrupt enable for the inside of window of the Window comparator */ +#define ADC12LOIE_L (0x0004) /* ADC12 Interrupt enable for lower threshold of the Window comparator */ +#define ADC12HIIE_L (0x0008) /* ADC12 Interrupt enable for upper threshold of the Window comparator */ +#define ADC12OVIE_L (0x0010) /* ADC12 ADC12MEMx Overflow interrupt enable */ +#define ADC12TOVIE_L (0x0020) /* ADC12 Timer Overflow interrupt enable */ +#define ADC12RDYIE_L (0x0040) /* ADC12 local buffered reference ready interrupt enable */ + +/* ADC12IFGR0 Control Bits */ +#define ADC12IFG0 (0x0001) /* ADC12 Memory 0 Interrupt Flag */ +#define ADC12IFG1 (0x0002) /* ADC12 Memory 1 Interrupt Flag */ +#define ADC12IFG2 (0x0004) /* ADC12 Memory 2 Interrupt Flag */ +#define ADC12IFG3 (0x0008) /* ADC12 Memory 3 Interrupt Flag */ +#define ADC12IFG4 (0x0010) /* ADC12 Memory 4 Interrupt Flag */ +#define ADC12IFG5 (0x0020) /* ADC12 Memory 5 Interrupt Flag */ +#define ADC12IFG6 (0x0040) /* ADC12 Memory 6 Interrupt Flag */ +#define ADC12IFG7 (0x0080) /* ADC12 Memory 7 Interrupt Flag */ +#define ADC12IFG8 (0x0100) /* ADC12 Memory 8 Interrupt Flag */ +#define ADC12IFG9 (0x0200) /* ADC12 Memory 9 Interrupt Flag */ +#define ADC12IFG10 (0x0400) /* ADC12 Memory 10 Interrupt Flag */ +#define ADC12IFG11 (0x0800) /* ADC12 Memory 11 Interrupt Flag */ +#define ADC12IFG12 (0x1000) /* ADC12 Memory 12 Interrupt Flag */ +#define ADC12IFG13 (0x2000) /* ADC12 Memory 13 Interrupt Flag */ +#define ADC12IFG14 (0x4000) /* ADC12 Memory 14 Interrupt Flag */ +#define ADC12IFG15 (0x8000) /* ADC12 Memory 15 Interrupt Flag */ + +/* ADC12IFGR0 Control Bits */ +#define ADC12IFG0_L (0x0001) /* ADC12 Memory 0 Interrupt Flag */ +#define ADC12IFG1_L (0x0002) /* ADC12 Memory 1 Interrupt Flag */ +#define ADC12IFG2_L (0x0004) /* ADC12 Memory 2 Interrupt Flag */ +#define ADC12IFG3_L (0x0008) /* ADC12 Memory 3 Interrupt Flag */ +#define ADC12IFG4_L (0x0010) /* ADC12 Memory 4 Interrupt Flag */ +#define ADC12IFG5_L (0x0020) /* ADC12 Memory 5 Interrupt Flag */ +#define ADC12IFG6_L (0x0040) /* ADC12 Memory 6 Interrupt Flag */ +#define ADC12IFG7_L (0x0080) /* ADC12 Memory 7 Interrupt Flag */ + +/* ADC12IFGR0 Control Bits */ +#define ADC12IFG8_H (0x0001) /* ADC12 Memory 8 Interrupt Flag */ +#define ADC12IFG9_H (0x0002) /* ADC12 Memory 9 Interrupt Flag */ +#define ADC12IFG10_H (0x0004) /* ADC12 Memory 10 Interrupt Flag */ +#define ADC12IFG11_H (0x0008) /* ADC12 Memory 11 Interrupt Flag */ +#define ADC12IFG12_H (0x0010) /* ADC12 Memory 12 Interrupt Flag */ +#define ADC12IFG13_H (0x0020) /* ADC12 Memory 13 Interrupt Flag */ +#define ADC12IFG14_H (0x0040) /* ADC12 Memory 14 Interrupt Flag */ +#define ADC12IFG15_H (0x0080) /* ADC12 Memory 15 Interrupt Flag */ + +/* ADC12IFGR1 Control Bits */ +#define ADC12IFG16 (0x0001) /* ADC12 Memory 16 Interrupt Flag */ +#define ADC12IFG17 (0x0002) /* ADC12 Memory 17 Interrupt Flag */ +#define ADC12IFG18 (0x0004) /* ADC12 Memory 18 Interrupt Flag */ +#define ADC12IFG19 (0x0008) /* ADC12 Memory 19 Interrupt Flag */ +#define ADC12IFG20 (0x0010) /* ADC12 Memory 20 Interrupt Flag */ +#define ADC12IFG21 (0x0020) /* ADC12 Memory 21 Interrupt Flag */ +#define ADC12IFG22 (0x0040) /* ADC12 Memory 22 Interrupt Flag */ +#define ADC12IFG23 (0x0080) /* ADC12 Memory 23 Interrupt Flag */ +#define ADC12IFG24 (0x0100) /* ADC12 Memory 24 Interrupt Flag */ +#define ADC12IFG25 (0x0200) /* ADC12 Memory 25 Interrupt Flag */ +#define ADC12IFG26 (0x0400) /* ADC12 Memory 26 Interrupt Flag */ +#define ADC12IFG27 (0x0800) /* ADC12 Memory 27 Interrupt Flag */ +#define ADC12IFG28 (0x1000) /* ADC12 Memory 28 Interrupt Flag */ +#define ADC12IFG29 (0x2000) /* ADC12 Memory 29 Interrupt Flag */ +#define ADC12IFG30 (0x4000) /* ADC12 Memory 30 Interrupt Flag */ +#define ADC12IFG31 (0x8000) /* ADC12 Memory 31 Interrupt Flag */ + +/* ADC12IFGR1 Control Bits */ +#define ADC12IFG16_L (0x0001) /* ADC12 Memory 16 Interrupt Flag */ +#define ADC12IFG17_L (0x0002) /* ADC12 Memory 17 Interrupt Flag */ +#define ADC12IFG18_L (0x0004) /* ADC12 Memory 18 Interrupt Flag */ +#define ADC12IFG19_L (0x0008) /* ADC12 Memory 19 Interrupt Flag */ +#define ADC12IFG20_L (0x0010) /* ADC12 Memory 20 Interrupt Flag */ +#define ADC12IFG21_L (0x0020) /* ADC12 Memory 21 Interrupt Flag */ +#define ADC12IFG22_L (0x0040) /* ADC12 Memory 22 Interrupt Flag */ +#define ADC12IFG23_L (0x0080) /* ADC12 Memory 23 Interrupt Flag */ + +/* ADC12IFGR1 Control Bits */ +#define ADC12IFG24_H (0x0001) /* ADC12 Memory 24 Interrupt Flag */ +#define ADC12IFG25_H (0x0002) /* ADC12 Memory 25 Interrupt Flag */ +#define ADC12IFG26_H (0x0004) /* ADC12 Memory 26 Interrupt Flag */ +#define ADC12IFG27_H (0x0008) /* ADC12 Memory 27 Interrupt Flag */ +#define ADC12IFG28_H (0x0010) /* ADC12 Memory 28 Interrupt Flag */ +#define ADC12IFG29_H (0x0020) /* ADC12 Memory 29 Interrupt Flag */ +#define ADC12IFG30_H (0x0040) /* ADC12 Memory 30 Interrupt Flag */ +#define ADC12IFG31_H (0x0080) /* ADC12 Memory 31 Interrupt Flag */ + +/* ADC12IFGR2 Control Bits */ +#define ADC12INIFG (0x0002) /* ADC12 Interrupt Flag for the inside of window of the Window comparator */ +#define ADC12LOIFG (0x0004) /* ADC12 Interrupt Flag for lower threshold of the Window comparator */ +#define ADC12HIIFG (0x0008) /* ADC12 Interrupt Flag for upper threshold of the Window comparator */ +#define ADC12OVIFG (0x0010) /* ADC12 ADC12MEMx Overflow interrupt Flag */ +#define ADC12TOVIFG (0x0020) /* ADC12 Timer Overflow interrupt Flag */ +#define ADC12RDYIFG (0x0040) /* ADC12 local buffered reference ready interrupt Flag */ + +/* ADC12IFGR2 Control Bits */ +#define ADC12INIFG_L (0x0002) /* ADC12 Interrupt Flag for the inside of window of the Window comparator */ +#define ADC12LOIFG_L (0x0004) /* ADC12 Interrupt Flag for lower threshold of the Window comparator */ +#define ADC12HIIFG_L (0x0008) /* ADC12 Interrupt Flag for upper threshold of the Window comparator */ +#define ADC12OVIFG_L (0x0010) /* ADC12 ADC12MEMx Overflow interrupt Flag */ +#define ADC12TOVIFG_L (0x0020) /* ADC12 Timer Overflow interrupt Flag */ +#define ADC12RDYIFG_L (0x0040) /* ADC12 local buffered reference ready interrupt Flag */ + +/* ADC12IV Definitions */ +#define ADC12IV_NONE (0x0000) /* No Interrupt pending */ +#define ADC12IV_ADC12OVIFG (0x0002) /* ADC12OVIFG */ +#define ADC12IV_ADC12TOVIFG (0x0004) /* ADC12TOVIFG */ +#define ADC12IV_ADC12HIIFG (0x0006) /* ADC12HIIFG */ +#define ADC12IV_ADC12LOIFG (0x0008) /* ADC12LOIFG */ +#define ADC12IV_ADC12INIFG (0x000A) /* ADC12INIFG */ +#define ADC12IV_ADC12IFG0 (0x000C) /* ADC12IFG0 */ +#define ADC12IV_ADC12IFG1 (0x000E) /* ADC12IFG1 */ +#define ADC12IV_ADC12IFG2 (0x0010) /* ADC12IFG2 */ +#define ADC12IV_ADC12IFG3 (0x0012) /* ADC12IFG3 */ +#define ADC12IV_ADC12IFG4 (0x0014) /* ADC12IFG4 */ +#define ADC12IV_ADC12IFG5 (0x0016) /* ADC12IFG5 */ +#define ADC12IV_ADC12IFG6 (0x0018) /* ADC12IFG6 */ +#define ADC12IV_ADC12IFG7 (0x001A) /* ADC12IFG7 */ +#define ADC12IV_ADC12IFG8 (0x001C) /* ADC12IFG8 */ +#define ADC12IV_ADC12IFG9 (0x001E) /* ADC12IFG9 */ +#define ADC12IV_ADC12IFG10 (0x0020) /* ADC12IFG10 */ +#define ADC12IV_ADC12IFG11 (0x0022) /* ADC12IFG11 */ +#define ADC12IV_ADC12IFG12 (0x0024) /* ADC12IFG12 */ +#define ADC12IV_ADC12IFG13 (0x0026) /* ADC12IFG13 */ +#define ADC12IV_ADC12IFG14 (0x0028) /* ADC12IFG14 */ +#define ADC12IV_ADC12IFG15 (0x002A) /* ADC12IFG15 */ +#define ADC12IV_ADC12IFG16 (0x002C) /* ADC12IFG16 */ +#define ADC12IV_ADC12IFG17 (0x002E) /* ADC12IFG17 */ +#define ADC12IV_ADC12IFG18 (0x0030) /* ADC12IFG18 */ +#define ADC12IV_ADC12IFG19 (0x0032) /* ADC12IFG19 */ +#define ADC12IV_ADC12IFG20 (0x0034) /* ADC12IFG20 */ +#define ADC12IV_ADC12IFG21 (0x0036) /* ADC12IFG21 */ +#define ADC12IV_ADC12IFG22 (0x0038) /* ADC12IFG22 */ +#define ADC12IV_ADC12IFG23 (0x003A) /* ADC12IFG23 */ +#define ADC12IV_ADC12IFG24 (0x003C) /* ADC12IFG24 */ +#define ADC12IV_ADC12IFG25 (0x003E) /* ADC12IFG25 */ +#define ADC12IV_ADC12IFG26 (0x0040) /* ADC12IFG26 */ +#define ADC12IV_ADC12IFG27 (0x0042) /* ADC12IFG27 */ +#define ADC12IV_ADC12IFG28 (0x0044) /* ADC12IFG28 */ +#define ADC12IV_ADC12IFG29 (0x0046) /* ADC12IFG29 */ +#define ADC12IV_ADC12IFG30 (0x0048) /* ADC12IFG30 */ +#define ADC12IV_ADC12IFG31 (0x004A) /* ADC12IFG31 */ +#define ADC12IV_ADC12RDYIFG (0x004C) /* ADC12RDYIFG */ + + +#endif +/************************************************************ +* AES256 Accelerator +************************************************************/ +#ifdef __MSP430_HAS_AES256__ /* Definition to show that Module is available */ + +#define OFS_AESACTL0 (0x0000) /* AES accelerator control register 0 */ +#define OFS_AESACTL0_L OFS_AESACTL0 +#define OFS_AESACTL0_H OFS_AESACTL0+1 +#define OFS_AESACTL1 (0x0002) /* AES accelerator control register 1 */ +#define OFS_AESACTL1_L OFS_AESACTL1 +#define OFS_AESACTL1_H OFS_AESACTL1+1 +#define OFS_AESASTAT (0x0004) /* AES accelerator status register */ +#define OFS_AESASTAT_L OFS_AESASTAT +#define OFS_AESASTAT_H OFS_AESASTAT+1 +#define OFS_AESAKEY (0x0006) /* AES accelerator key register */ +#define OFS_AESAKEY_L OFS_AESAKEY +#define OFS_AESAKEY_H OFS_AESAKEY+1 +#define OFS_AESADIN (0x0008) /* AES accelerator data in register */ +#define OFS_AESADIN_L OFS_AESADIN +#define OFS_AESADIN_H OFS_AESADIN+1 +#define OFS_AESADOUT (0x000A) /* AES accelerator data out register */ +#define OFS_AESADOUT_L OFS_AESADOUT +#define OFS_AESADOUT_H OFS_AESADOUT+1 +#define OFS_AESAXDIN (0x000C) /* AES accelerator XORed data in register */ +#define OFS_AESAXDIN_L OFS_AESAXDIN +#define OFS_AESAXDIN_H OFS_AESAXDIN+1 +#define OFS_AESAXIN (0x000E) /* AES accelerator XORed data in register (no trigger) */ +#define OFS_AESAXIN_L OFS_AESAXIN +#define OFS_AESAXIN_H OFS_AESAXIN+1 + +/* AESACTL0 Control Bits */ +#define AESOP0 (0x0001) /* AES Operation Bit: 0 */ +#define AESOP1 (0x0002) /* AES Operation Bit: 1 */ +#define AESKL0 (0x0004) /* AES Key length Bit: 0 */ +#define AESKL1 (0x0008) /* AES Key length Bit: 1 */ +#define AESTRIG (0x0010) /* AES Trigger Select */ +#define AESCM0 (0x0020) /* AES Cipher mode select Bit: 0 */ +#define AESCM1 (0x0040) /* AES Cipher mode select Bit: 1 */ +#define AESSWRST (0x0080) /* AES Software Reset */ +#define AESRDYIFG (0x0100) /* AES ready interrupt flag */ +#define AESERRFG (0x0800) /* AES Error Flag */ +#define AESRDYIE (0x1000) /* AES ready interrupt enable*/ +#define AESCMEN (0x8000) /* AES DMA cipher mode enable*/ + +/* AESACTL0 Control Bits */ +#define AESOP0_L (0x0001) /* AES Operation Bit: 0 */ +#define AESOP1_L (0x0002) /* AES Operation Bit: 1 */ +#define AESKL0_L (0x0004) /* AES Key length Bit: 0 */ +#define AESKL1_L (0x0008) /* AES Key length Bit: 1 */ +#define AESTRIG_L (0x0010) /* AES Trigger Select */ +#define AESCM0_L (0x0020) /* AES Cipher mode select Bit: 0 */ +#define AESCM1_L (0x0040) /* AES Cipher mode select Bit: 1 */ +#define AESSWRST_L (0x0080) /* AES Software Reset */ + +/* AESACTL0 Control Bits */ +#define AESRDYIFG_H (0x0001) /* AES ready interrupt flag */ +#define AESERRFG_H (0x0008) /* AES Error Flag */ +#define AESRDYIE_H (0x0010) /* AES ready interrupt enable*/ +#define AESCMEN_H (0x0080) /* AES DMA cipher mode enable*/ + +#define AESOP_0 (0x0000) /* AES Operation: Encrypt */ +#define AESOP_1 (0x0001) /* AES Operation: Decrypt (same Key) */ +#define AESOP_2 (0x0002) /* AES Operation: Decrypt (frist round Key) */ +#define AESOP_3 (0x0003) /* AES Operation: Generate first round Key */ + +#define AESKL_0 (0x0000) /* AES Key length: AES128 */ +#define AESKL_1 (0x0004) /* AES Key length: AES192 */ +#define AESKL_2 (0x0008) /* AES Key length: AES256 */ +#define AESKL__128 (0x0000) /* AES Key length: AES128 */ +#define AESKL__192 (0x0004) /* AES Key length: AES192 */ +#define AESKL__256 (0x0008) /* AES Key length: AES256 */ + +#define AESCM_0 (0x0000) /* AES Cipher mode select: ECB */ +#define AESCM_1 (0x0020) /* AES Cipher mode select: CBC */ +#define AESCM_2 (0x0040) /* AES Cipher mode select: OFB */ +#define AESCM_3 (0x0060) /* AES Cipher mode select: CFB */ +#define AESCM__ECB (0x0000) /* AES Cipher mode select: ECB */ +#define AESCM__CBC (0x0020) /* AES Cipher mode select: CBC */ +#define AESCM__OFB (0x0040) /* AES Cipher mode select: OFB */ +#define AESCM__CFB (0x0060) /* AES Cipher mode select: CFB */ + +/* AESACTL1 Control Bits */ +#define AESBLKCNT0 (0x0001) /* AES Cipher Block Counter Bit: 0 */ +#define AESBLKCNT1 (0x0002) /* AES Cipher Block Counter Bit: 1 */ +#define AESBLKCNT2 (0x0004) /* AES Cipher Block Counter Bit: 2 */ +#define AESBLKCNT3 (0x0008) /* AES Cipher Block Counter Bit: 3 */ +#define AESBLKCNT4 (0x0010) /* AES Cipher Block Counter Bit: 4 */ +#define AESBLKCNT5 (0x0020) /* AES Cipher Block Counter Bit: 5 */ +#define AESBLKCNT6 (0x0040) /* AES Cipher Block Counter Bit: 6 */ +#define AESBLKCNT7 (0x0080) /* AES Cipher Block Counter Bit: 7 */ + +/* AESACTL1 Control Bits */ +#define AESBLKCNT0_L (0x0001) /* AES Cipher Block Counter Bit: 0 */ +#define AESBLKCNT1_L (0x0002) /* AES Cipher Block Counter Bit: 1 */ +#define AESBLKCNT2_L (0x0004) /* AES Cipher Block Counter Bit: 2 */ +#define AESBLKCNT3_L (0x0008) /* AES Cipher Block Counter Bit: 3 */ +#define AESBLKCNT4_L (0x0010) /* AES Cipher Block Counter Bit: 4 */ +#define AESBLKCNT5_L (0x0020) /* AES Cipher Block Counter Bit: 5 */ +#define AESBLKCNT6_L (0x0040) /* AES Cipher Block Counter Bit: 6 */ +#define AESBLKCNT7_L (0x0080) /* AES Cipher Block Counter Bit: 7 */ + +/* AESASTAT Control Bits */ +#define AESBUSY (0x0001) /* AES Busy */ +#define AESKEYWR (0x0002) /* AES All 16 bytes written to AESAKEY */ +#define AESDINWR (0x0004) /* AES All 16 bytes written to AESADIN */ +#define AESDOUTRD (0x0008) /* AES All 16 bytes read from AESADOUT */ +#define AESKEYCNT0 (0x0010) /* AES Bytes written via AESAKEY Bit: 0 */ +#define AESKEYCNT1 (0x0020) /* AES Bytes written via AESAKEY Bit: 1 */ +#define AESKEYCNT2 (0x0040) /* AES Bytes written via AESAKEY Bit: 2 */ +#define AESKEYCNT3 (0x0080) /* AES Bytes written via AESAKEY Bit: 3 */ +#define AESDINCNT0 (0x0100) /* AES Bytes written via AESADIN Bit: 0 */ +#define AESDINCNT1 (0x0200) /* AES Bytes written via AESADIN Bit: 1 */ +#define AESDINCNT2 (0x0400) /* AES Bytes written via AESADIN Bit: 2 */ +#define AESDINCNT3 (0x0800) /* AES Bytes written via AESADIN Bit: 3 */ +#define AESDOUTCNT0 (0x1000) /* AES Bytes read via AESADOUT Bit: 0 */ +#define AESDOUTCNT1 (0x2000) /* AES Bytes read via AESADOUT Bit: 1 */ +#define AESDOUTCNT2 (0x4000) /* AES Bytes read via AESADOUT Bit: 2 */ +#define AESDOUTCNT3 (0x8000) /* AES Bytes read via AESADOUT Bit: 3 */ + +/* AESASTAT Control Bits */ +#define AESBUSY_L (0x0001) /* AES Busy */ +#define AESKEYWR_L (0x0002) /* AES All 16 bytes written to AESAKEY */ +#define AESDINWR_L (0x0004) /* AES All 16 bytes written to AESADIN */ +#define AESDOUTRD_L (0x0008) /* AES All 16 bytes read from AESADOUT */ +#define AESKEYCNT0_L (0x0010) /* AES Bytes written via AESAKEY Bit: 0 */ +#define AESKEYCNT1_L (0x0020) /* AES Bytes written via AESAKEY Bit: 1 */ +#define AESKEYCNT2_L (0x0040) /* AES Bytes written via AESAKEY Bit: 2 */ +#define AESKEYCNT3_L (0x0080) /* AES Bytes written via AESAKEY Bit: 3 */ + +/* AESASTAT Control Bits */ +#define AESDINCNT0_H (0x0001) /* AES Bytes written via AESADIN Bit: 0 */ +#define AESDINCNT1_H (0x0002) /* AES Bytes written via AESADIN Bit: 1 */ +#define AESDINCNT2_H (0x0004) /* AES Bytes written via AESADIN Bit: 2 */ +#define AESDINCNT3_H (0x0008) /* AES Bytes written via AESADIN Bit: 3 */ +#define AESDOUTCNT0_H (0x0010) /* AES Bytes read via AESADOUT Bit: 0 */ +#define AESDOUTCNT1_H (0x0020) /* AES Bytes read via AESADOUT Bit: 1 */ +#define AESDOUTCNT2_H (0x0040) /* AES Bytes read via AESADOUT Bit: 2 */ +#define AESDOUTCNT3_H (0x0080) /* AES Bytes read via AESADOUT Bit: 3 */ + +#endif +/************************************************************ +* Capacitive_Touch_IO 0 +************************************************************/ +#ifdef __MSP430_HAS_CAP_TOUCH_IO_0__ /* Definition to show that Module is available */ + +#define OFS_CAPTIO0CTL (0x000E) /* Capacitive_Touch_IO 0 control register */ +#define OFS_CAPTIO0CTL_L OFS_CAPTIO0CTL +#define OFS_CAPTIO0CTL_H OFS_CAPTIO0CTL+1 + +#define CAPSIO0CTL CAPTIO0CTL /* legacy define */ + +/* CAPTIOxCTL Control Bits */ +#define CAPTIOPISEL0 (0x0002) /* CapTouchIO Pin Select Bit: 0 */ +#define CAPTIOPISEL1 (0x0004) /* CapTouchIO Pin Select Bit: 1 */ +#define CAPTIOPISEL2 (0x0008) /* CapTouchIO Pin Select Bit: 2 */ +#define CAPTIOPOSEL0 (0x0010) /* CapTouchIO Port Select Bit: 0 */ +#define CAPTIOPOSEL1 (0x0020) /* CapTouchIO Port Select Bit: 1 */ +#define CAPTIOPOSEL2 (0x0040) /* CapTouchIO Port Select Bit: 2 */ +#define CAPTIOPOSEL3 (0x0080) /* CapTouchIO Port Select Bit: 3 */ +#define CAPTIOEN (0x0100) /* CapTouchIO Enable */ +#define CAPTIO (0x0200) /* CapTouchIO state */ + +/* CAPTIOxCTL Control Bits */ +#define CAPTIOPISEL0_L (0x0002) /* CapTouchIO Pin Select Bit: 0 */ +#define CAPTIOPISEL1_L (0x0004) /* CapTouchIO Pin Select Bit: 1 */ +#define CAPTIOPISEL2_L (0x0008) /* CapTouchIO Pin Select Bit: 2 */ +#define CAPTIOPOSEL0_L (0x0010) /* CapTouchIO Port Select Bit: 0 */ +#define CAPTIOPOSEL1_L (0x0020) /* CapTouchIO Port Select Bit: 1 */ +#define CAPTIOPOSEL2_L (0x0040) /* CapTouchIO Port Select Bit: 2 */ +#define CAPTIOPOSEL3_L (0x0080) /* CapTouchIO Port Select Bit: 3 */ + +/* CAPTIOxCTL Control Bits */ +#define CAPTIOEN_H (0x0001) /* CapTouchIO Enable */ +#define CAPTIO_H (0x0002) /* CapTouchIO state */ + +/* Legacy defines */ +#define CAPSIOPISEL0 (0x0002) /* CapTouchIO Pin Select Bit: 0 */ +#define CAPSIOPISEL1 (0x0004) /* CapTouchIO Pin Select Bit: 1 */ +#define CAPSIOPISEL2 (0x0008) /* CapTouchIO Pin Select Bit: 2 */ +#define CAPSIOPOSEL0 (0x0010) /* CapTouchIO Port Select Bit: 0 */ +#define CAPSIOPOSEL1 (0x0020) /* CapTouchIO Port Select Bit: 1 */ +#define CAPSIOPOSEL2 (0x0040) /* CapTouchIO Port Select Bit: 2 */ +#define CAPSIOPOSEL3 (0x0080) /* CapTouchIO Port Select Bit: 3 */ +#define CAPSIOEN (0x0100) /* CapTouchIO Enable */ +#define CAPSIO (0x0200) /* CapTouchIO state */ + +#endif +/************************************************************ +* Capacitive_Touch_IO 1 +************************************************************/ +#ifdef __MSP430_HAS_CAP_TOUCH_IO_1__ /* Definition to show that Module is available */ + +#define OFS_CAPTIO1CTL (0x000E) /* Capacitive_Touch_IO 1 control register */ +#define OFS_CAPTIO1CTL_L OFS_CAPTIO1CTL +#define OFS_CAPTIO1CTL_H OFS_CAPTIO1CTL+1 + +#define CAPSIO1CTL CAPTIO1CTL /* legacy define */ + +#endif +/************************************************************ +* Comparator E +************************************************************/ +#ifdef __MSP430_HAS_COMP_E__ /* Definition to show that Module is available */ + +#define OFS_CECTL0 (0x0000) /* Comparator E Control Register 0 */ +#define OFS_CECTL0_L OFS_CECTL0 +#define OFS_CECTL0_H OFS_CECTL0+1 +#define OFS_CECTL1 (0x0002) /* Comparator E Control Register 1 */ +#define OFS_CECTL1_L OFS_CECTL1 +#define OFS_CECTL1_H OFS_CECTL1+1 +#define OFS_CECTL2 (0x0004) /* Comparator E Control Register 2 */ +#define OFS_CECTL2_L OFS_CECTL2 +#define OFS_CECTL2_H OFS_CECTL2+1 +#define OFS_CECTL3 (0x0006) /* Comparator E Control Register 3 */ +#define OFS_CECTL3_L OFS_CECTL3 +#define OFS_CECTL3_H OFS_CECTL3+1 +#define OFS_CEINT (0x000C) /* Comparator E Interrupt Register */ +#define OFS_CEINT_L OFS_CEINT +#define OFS_CEINT_H OFS_CEINT+1 +#define OFS_CEIV (0x000E) /* Comparator E Interrupt Vector Word */ +#define OFS_CEIV_L OFS_CEIV +#define OFS_CEIV_H OFS_CEIV+1 + +/* CECTL0 Control Bits */ +#define CEIPSEL0 (0x0001) /* Comp. E Pos. Channel Input Select 0 */ +#define CEIPSEL1 (0x0002) /* Comp. E Pos. Channel Input Select 1 */ +#define CEIPSEL2 (0x0004) /* Comp. E Pos. Channel Input Select 2 */ +#define CEIPSEL3 (0x0008) /* Comp. E Pos. Channel Input Select 3 */ +//#define RESERVED (0x0010) /* Comp. E */ +//#define RESERVED (0x0020) /* Comp. E */ +//#define RESERVED (0x0040) /* Comp. E */ +#define CEIPEN (0x0080) /* Comp. E Pos. Channel Input Enable */ +#define CEIMSEL0 (0x0100) /* Comp. E Neg. Channel Input Select 0 */ +#define CEIMSEL1 (0x0200) /* Comp. E Neg. Channel Input Select 1 */ +#define CEIMSEL2 (0x0400) /* Comp. E Neg. Channel Input Select 2 */ +#define CEIMSEL3 (0x0800) /* Comp. E Neg. Channel Input Select 3 */ +//#define RESERVED (0x1000) /* Comp. E */ +//#define RESERVED (0x2000) /* Comp. E */ +//#define RESERVED (0x4000) /* Comp. E */ +#define CEIMEN (0x8000) /* Comp. E Neg. Channel Input Enable */ + +/* CECTL0 Control Bits */ +#define CEIPSEL0_L (0x0001) /* Comp. E Pos. Channel Input Select 0 */ +#define CEIPSEL1_L (0x0002) /* Comp. E Pos. Channel Input Select 1 */ +#define CEIPSEL2_L (0x0004) /* Comp. E Pos. Channel Input Select 2 */ +#define CEIPSEL3_L (0x0008) /* Comp. E Pos. Channel Input Select 3 */ +//#define RESERVED (0x0010) /* Comp. E */ +//#define RESERVED (0x0020) /* Comp. E */ +//#define RESERVED (0x0040) /* Comp. E */ +#define CEIPEN_L (0x0080) /* Comp. E Pos. Channel Input Enable */ +//#define RESERVED (0x1000) /* Comp. E */ +//#define RESERVED (0x2000) /* Comp. E */ +//#define RESERVED (0x4000) /* Comp. E */ + +/* CECTL0 Control Bits */ +//#define RESERVED (0x0010) /* Comp. E */ +//#define RESERVED (0x0020) /* Comp. E */ +//#define RESERVED (0x0040) /* Comp. E */ +#define CEIMSEL0_H (0x0001) /* Comp. E Neg. Channel Input Select 0 */ +#define CEIMSEL1_H (0x0002) /* Comp. E Neg. Channel Input Select 1 */ +#define CEIMSEL2_H (0x0004) /* Comp. E Neg. Channel Input Select 2 */ +#define CEIMSEL3_H (0x0008) /* Comp. E Neg. Channel Input Select 3 */ +//#define RESERVED (0x1000) /* Comp. E */ +//#define RESERVED (0x2000) /* Comp. E */ +//#define RESERVED (0x4000) /* Comp. E */ +#define CEIMEN_H (0x0080) /* Comp. E Neg. Channel Input Enable */ + +#define CEIPSEL_0 (0x0000) /* Comp. E V+ terminal Input Select: Channel 0 */ +#define CEIPSEL_1 (0x0001) /* Comp. E V+ terminal Input Select: Channel 1 */ +#define CEIPSEL_2 (0x0002) /* Comp. E V+ terminal Input Select: Channel 2 */ +#define CEIPSEL_3 (0x0003) /* Comp. E V+ terminal Input Select: Channel 3 */ +#define CEIPSEL_4 (0x0004) /* Comp. E V+ terminal Input Select: Channel 4 */ +#define CEIPSEL_5 (0x0005) /* Comp. E V+ terminal Input Select: Channel 5 */ +#define CEIPSEL_6 (0x0006) /* Comp. E V+ terminal Input Select: Channel 6 */ +#define CEIPSEL_7 (0x0007) /* Comp. E V+ terminal Input Select: Channel 7 */ +#define CEIPSEL_8 (0x0008) /* Comp. E V+ terminal Input Select: Channel 8 */ +#define CEIPSEL_9 (0x0009) /* Comp. E V+ terminal Input Select: Channel 9 */ +#define CEIPSEL_10 (0x000A) /* Comp. E V+ terminal Input Select: Channel 10 */ +#define CEIPSEL_11 (0x000B) /* Comp. E V+ terminal Input Select: Channel 11 */ +#define CEIPSEL_12 (0x000C) /* Comp. E V+ terminal Input Select: Channel 12 */ +#define CEIPSEL_13 (0x000D) /* Comp. E V+ terminal Input Select: Channel 13 */ +#define CEIPSEL_14 (0x000E) /* Comp. E V+ terminal Input Select: Channel 14 */ +#define CEIPSEL_15 (0x000F) /* Comp. E V+ terminal Input Select: Channel 15 */ + +#define CEIMSEL_0 (0x0000) /* Comp. E V- Terminal Input Select: Channel 0 */ +#define CEIMSEL_1 (0x0100) /* Comp. E V- Terminal Input Select: Channel 1 */ +#define CEIMSEL_2 (0x0200) /* Comp. E V- Terminal Input Select: Channel 2 */ +#define CEIMSEL_3 (0x0300) /* Comp. E V- Terminal Input Select: Channel 3 */ +#define CEIMSEL_4 (0x0400) /* Comp. E V- Terminal Input Select: Channel 4 */ +#define CEIMSEL_5 (0x0500) /* Comp. E V- Terminal Input Select: Channel 5 */ +#define CEIMSEL_6 (0x0600) /* Comp. E V- Terminal Input Select: Channel 6 */ +#define CEIMSEL_7 (0x0700) /* Comp. E V- Terminal Input Select: Channel 7 */ +#define CEIMSEL_8 (0x0800) /* Comp. E V- terminal Input Select: Channel 8 */ +#define CEIMSEL_9 (0x0900) /* Comp. E V- terminal Input Select: Channel 9 */ +#define CEIMSEL_10 (0x0A00) /* Comp. E V- terminal Input Select: Channel 10 */ +#define CEIMSEL_11 (0x0B00) /* Comp. E V- terminal Input Select: Channel 11 */ +#define CEIMSEL_12 (0x0C00) /* Comp. E V- terminal Input Select: Channel 12 */ +#define CEIMSEL_13 (0x0D00) /* Comp. E V- terminal Input Select: Channel 13 */ +#define CEIMSEL_14 (0x0E00) /* Comp. E V- terminal Input Select: Channel 14 */ +#define CEIMSEL_15 (0x0F00) /* Comp. E V- terminal Input Select: Channel 15 */ + +/* CECTL1 Control Bits */ +#define CEOUT (0x0001) /* Comp. E Output */ +#define CEOUTPOL (0x0002) /* Comp. E Output Polarity */ +#define CEF (0x0004) /* Comp. E Enable Output Filter */ +#define CEIES (0x0008) /* Comp. E Interrupt Edge Select */ +#define CESHORT (0x0010) /* Comp. E Input Short */ +#define CEEX (0x0020) /* Comp. E Exchange Inputs */ +#define CEFDLY0 (0x0040) /* Comp. E Filter delay Bit 0 */ +#define CEFDLY1 (0x0080) /* Comp. E Filter delay Bit 1 */ +#define CEPWRMD0 (0x0100) /* Comp. E Power mode Bit 0 */ +#define CEPWRMD1 (0x0200) /* Comp. E Power mode Bit 1 */ +#define CEON (0x0400) /* Comp. E enable */ +#define CEMRVL (0x0800) /* Comp. E CEMRV Level */ +#define CEMRVS (0x1000) /* Comp. E Output selects between VREF0 or VREF1*/ +//#define RESERVED (0x2000) /* Comp. E */ +//#define RESERVED (0x4000) /* Comp. E */ +//#define RESERVED (0x8000) /* Comp. E */ + +/* CECTL1 Control Bits */ +#define CEOUT_L (0x0001) /* Comp. E Output */ +#define CEOUTPOL_L (0x0002) /* Comp. E Output Polarity */ +#define CEF_L (0x0004) /* Comp. E Enable Output Filter */ +#define CEIES_L (0x0008) /* Comp. E Interrupt Edge Select */ +#define CESHORT_L (0x0010) /* Comp. E Input Short */ +#define CEEX_L (0x0020) /* Comp. E Exchange Inputs */ +#define CEFDLY0_L (0x0040) /* Comp. E Filter delay Bit 0 */ +#define CEFDLY1_L (0x0080) /* Comp. E Filter delay Bit 1 */ +//#define RESERVED (0x2000) /* Comp. E */ +//#define RESERVED (0x4000) /* Comp. E */ +//#define RESERVED (0x8000) /* Comp. E */ + +/* CECTL1 Control Bits */ +#define CEPWRMD0_H (0x0001) /* Comp. E Power mode Bit 0 */ +#define CEPWRMD1_H (0x0002) /* Comp. E Power mode Bit 1 */ +#define CEON_H (0x0004) /* Comp. E enable */ +#define CEMRVL_H (0x0008) /* Comp. E CEMRV Level */ +#define CEMRVS_H (0x0010) /* Comp. E Output selects between VREF0 or VREF1*/ +//#define RESERVED (0x2000) /* Comp. E */ +//#define RESERVED (0x4000) /* Comp. E */ +//#define RESERVED (0x8000) /* Comp. E */ + +#define CEPWRMD_0 (0x0000) /* Comp. E Power mode 0 */ +#define CEPWRMD_1 (0x0100) /* Comp. E Power mode 1 */ +#define CEPWRMD_2 (0x0200) /* Comp. E Power mode 2 */ +#define CEPWRMD_3 (0x0300) /* Comp. E Power mode 3*/ + +#define CEFDLY_0 (0x0000) /* Comp. E Filter delay 0 : 450ns */ +#define CEFDLY_1 (0x0040) /* Comp. E Filter delay 1 : 900ns */ +#define CEFDLY_2 (0x0080) /* Comp. E Filter delay 2 : 1800ns */ +#define CEFDLY_3 (0x00C0) /* Comp. E Filter delay 3 : 3600ns */ + +/* CECTL2 Control Bits */ +#define CEREF00 (0x0001) /* Comp. E Reference 0 Resistor Select Bit : 0 */ +#define CEREF01 (0x0002) /* Comp. E Reference 0 Resistor Select Bit : 1 */ +#define CEREF02 (0x0004) /* Comp. E Reference 0 Resistor Select Bit : 2 */ +#define CEREF03 (0x0008) /* Comp. E Reference 0 Resistor Select Bit : 3 */ +#define CEREF04 (0x0010) /* Comp. E Reference 0 Resistor Select Bit : 4 */ +#define CERSEL (0x0020) /* Comp. E Reference select */ +#define CERS0 (0x0040) /* Comp. E Reference Source Bit : 0 */ +#define CERS1 (0x0080) /* Comp. E Reference Source Bit : 1 */ +#define CEREF10 (0x0100) /* Comp. E Reference 1 Resistor Select Bit : 0 */ +#define CEREF11 (0x0200) /* Comp. E Reference 1 Resistor Select Bit : 1 */ +#define CEREF12 (0x0400) /* Comp. E Reference 1 Resistor Select Bit : 2 */ +#define CEREF13 (0x0800) /* Comp. E Reference 1 Resistor Select Bit : 3 */ +#define CEREF14 (0x1000) /* Comp. E Reference 1 Resistor Select Bit : 4 */ +#define CEREFL0 (0x2000) /* Comp. E Reference voltage level Bit : 0 */ +#define CEREFL1 (0x4000) /* Comp. E Reference voltage level Bit : 1 */ +#define CEREFACC (0x8000) /* Comp. E Reference Accuracy */ + +/* CECTL2 Control Bits */ +#define CEREF00_L (0x0001) /* Comp. E Reference 0 Resistor Select Bit : 0 */ +#define CEREF01_L (0x0002) /* Comp. E Reference 0 Resistor Select Bit : 1 */ +#define CEREF02_L (0x0004) /* Comp. E Reference 0 Resistor Select Bit : 2 */ +#define CEREF03_L (0x0008) /* Comp. E Reference 0 Resistor Select Bit : 3 */ +#define CEREF04_L (0x0010) /* Comp. E Reference 0 Resistor Select Bit : 4 */ +#define CERSEL_L (0x0020) /* Comp. E Reference select */ +#define CERS0_L (0x0040) /* Comp. E Reference Source Bit : 0 */ +#define CERS1_L (0x0080) /* Comp. E Reference Source Bit : 1 */ + +/* CECTL2 Control Bits */ +#define CEREF10_H (0x0001) /* Comp. E Reference 1 Resistor Select Bit : 0 */ +#define CEREF11_H (0x0002) /* Comp. E Reference 1 Resistor Select Bit : 1 */ +#define CEREF12_H (0x0004) /* Comp. E Reference 1 Resistor Select Bit : 2 */ +#define CEREF13_H (0x0008) /* Comp. E Reference 1 Resistor Select Bit : 3 */ +#define CEREF14_H (0x0010) /* Comp. E Reference 1 Resistor Select Bit : 4 */ +#define CEREFL0_H (0x0020) /* Comp. E Reference voltage level Bit : 0 */ +#define CEREFL1_H (0x0040) /* Comp. E Reference voltage level Bit : 1 */ +#define CEREFACC_H (0x0080) /* Comp. E Reference Accuracy */ + +#define CEREF0_0 (0x0000) /* Comp. E Int. Ref.0 Select 0 : 1/32 */ +#define CEREF0_1 (0x0001) /* Comp. E Int. Ref.0 Select 1 : 2/32 */ +#define CEREF0_2 (0x0002) /* Comp. E Int. Ref.0 Select 2 : 3/32 */ +#define CEREF0_3 (0x0003) /* Comp. E Int. Ref.0 Select 3 : 4/32 */ +#define CEREF0_4 (0x0004) /* Comp. E Int. Ref.0 Select 4 : 5/32 */ +#define CEREF0_5 (0x0005) /* Comp. E Int. Ref.0 Select 5 : 6/32 */ +#define CEREF0_6 (0x0006) /* Comp. E Int. Ref.0 Select 6 : 7/32 */ +#define CEREF0_7 (0x0007) /* Comp. E Int. Ref.0 Select 7 : 8/32 */ +#define CEREF0_8 (0x0008) /* Comp. E Int. Ref.0 Select 0 : 9/32 */ +#define CEREF0_9 (0x0009) /* Comp. E Int. Ref.0 Select 1 : 10/32 */ +#define CEREF0_10 (0x000A) /* Comp. E Int. Ref.0 Select 2 : 11/32 */ +#define CEREF0_11 (0x000B) /* Comp. E Int. Ref.0 Select 3 : 12/32 */ +#define CEREF0_12 (0x000C) /* Comp. E Int. Ref.0 Select 4 : 13/32 */ +#define CEREF0_13 (0x000D) /* Comp. E Int. Ref.0 Select 5 : 14/32 */ +#define CEREF0_14 (0x000E) /* Comp. E Int. Ref.0 Select 6 : 15/32 */ +#define CEREF0_15 (0x000F) /* Comp. E Int. Ref.0 Select 7 : 16/32 */ +#define CEREF0_16 (0x0010) /* Comp. E Int. Ref.0 Select 0 : 17/32 */ +#define CEREF0_17 (0x0011) /* Comp. E Int. Ref.0 Select 1 : 18/32 */ +#define CEREF0_18 (0x0012) /* Comp. E Int. Ref.0 Select 2 : 19/32 */ +#define CEREF0_19 (0x0013) /* Comp. E Int. Ref.0 Select 3 : 20/32 */ +#define CEREF0_20 (0x0014) /* Comp. E Int. Ref.0 Select 4 : 21/32 */ +#define CEREF0_21 (0x0015) /* Comp. E Int. Ref.0 Select 5 : 22/32 */ +#define CEREF0_22 (0x0016) /* Comp. E Int. Ref.0 Select 6 : 23/32 */ +#define CEREF0_23 (0x0017) /* Comp. E Int. Ref.0 Select 7 : 24/32 */ +#define CEREF0_24 (0x0018) /* Comp. E Int. Ref.0 Select 0 : 25/32 */ +#define CEREF0_25 (0x0019) /* Comp. E Int. Ref.0 Select 1 : 26/32 */ +#define CEREF0_26 (0x001A) /* Comp. E Int. Ref.0 Select 2 : 27/32 */ +#define CEREF0_27 (0x001B) /* Comp. E Int. Ref.0 Select 3 : 28/32 */ +#define CEREF0_28 (0x001C) /* Comp. E Int. Ref.0 Select 4 : 29/32 */ +#define CEREF0_29 (0x001D) /* Comp. E Int. Ref.0 Select 5 : 30/32 */ +#define CEREF0_30 (0x001E) /* Comp. E Int. Ref.0 Select 6 : 31/32 */ +#define CEREF0_31 (0x001F) /* Comp. E Int. Ref.0 Select 7 : 32/32 */ + +#define CERS_0 (0x0000) /* Comp. E Reference Source 0 : Off */ +#define CERS_1 (0x0040) /* Comp. E Reference Source 1 : Vcc */ +#define CERS_2 (0x0080) /* Comp. E Reference Source 2 : Shared Ref. */ +#define CERS_3 (0x00C0) /* Comp. E Reference Source 3 : Shared Ref. / Off */ + +#define CEREF1_0 (0x0000) /* Comp. E Int. Ref.1 Select 0 : 1/32 */ +#define CEREF1_1 (0x0100) /* Comp. E Int. Ref.1 Select 1 : 2/32 */ +#define CEREF1_2 (0x0200) /* Comp. E Int. Ref.1 Select 2 : 3/32 */ +#define CEREF1_3 (0x0300) /* Comp. E Int. Ref.1 Select 3 : 4/32 */ +#define CEREF1_4 (0x0400) /* Comp. E Int. Ref.1 Select 4 : 5/32 */ +#define CEREF1_5 (0x0500) /* Comp. E Int. Ref.1 Select 5 : 6/32 */ +#define CEREF1_6 (0x0600) /* Comp. E Int. Ref.1 Select 6 : 7/32 */ +#define CEREF1_7 (0x0700) /* Comp. E Int. Ref.1 Select 7 : 8/32 */ +#define CEREF1_8 (0x0800) /* Comp. E Int. Ref.1 Select 0 : 9/32 */ +#define CEREF1_9 (0x0900) /* Comp. E Int. Ref.1 Select 1 : 10/32 */ +#define CEREF1_10 (0x0A00) /* Comp. E Int. Ref.1 Select 2 : 11/32 */ +#define CEREF1_11 (0x0B00) /* Comp. E Int. Ref.1 Select 3 : 12/32 */ +#define CEREF1_12 (0x0C00) /* Comp. E Int. Ref.1 Select 4 : 13/32 */ +#define CEREF1_13 (0x0D00) /* Comp. E Int. Ref.1 Select 5 : 14/32 */ +#define CEREF1_14 (0x0E00) /* Comp. E Int. Ref.1 Select 6 : 15/32 */ +#define CEREF1_15 (0x0F00) /* Comp. E Int. Ref.1 Select 7 : 16/32 */ +#define CEREF1_16 (0x1000) /* Comp. E Int. Ref.1 Select 0 : 17/32 */ +#define CEREF1_17 (0x1100) /* Comp. E Int. Ref.1 Select 1 : 18/32 */ +#define CEREF1_18 (0x1200) /* Comp. E Int. Ref.1 Select 2 : 19/32 */ +#define CEREF1_19 (0x1300) /* Comp. E Int. Ref.1 Select 3 : 20/32 */ +#define CEREF1_20 (0x1400) /* Comp. E Int. Ref.1 Select 4 : 21/32 */ +#define CEREF1_21 (0x1500) /* Comp. E Int. Ref.1 Select 5 : 22/32 */ +#define CEREF1_22 (0x1600) /* Comp. E Int. Ref.1 Select 6 : 23/32 */ +#define CEREF1_23 (0x1700) /* Comp. E Int. Ref.1 Select 7 : 24/32 */ +#define CEREF1_24 (0x1800) /* Comp. E Int. Ref.1 Select 0 : 25/32 */ +#define CEREF1_25 (0x1900) /* Comp. E Int. Ref.1 Select 1 : 26/32 */ +#define CEREF1_26 (0x1A00) /* Comp. E Int. Ref.1 Select 2 : 27/32 */ +#define CEREF1_27 (0x1B00) /* Comp. E Int. Ref.1 Select 3 : 28/32 */ +#define CEREF1_28 (0x1C00) /* Comp. E Int. Ref.1 Select 4 : 29/32 */ +#define CEREF1_29 (0x1D00) /* Comp. E Int. Ref.1 Select 5 : 30/32 */ +#define CEREF1_30 (0x1E00) /* Comp. E Int. Ref.1 Select 6 : 31/32 */ +#define CEREF1_31 (0x1F00) /* Comp. E Int. Ref.1 Select 7 : 32/32 */ + +#define CEREFL_0 (0x0000) /* Comp. E Reference voltage level 0 : None */ +#define CEREFL_1 (0x2000) /* Comp. E Reference voltage level 1 : 1.2V */ +#define CEREFL_2 (0x4000) /* Comp. E Reference voltage level 2 : 2.0V */ +#define CEREFL_3 (0x6000) /* Comp. E Reference voltage level 3 : 2.5V */ + +#define CEPD0 (0x0001) /* Comp. E Disable Input Buffer of Port Register .0 */ +#define CEPD1 (0x0002) /* Comp. E Disable Input Buffer of Port Register .1 */ +#define CEPD2 (0x0004) /* Comp. E Disable Input Buffer of Port Register .2 */ +#define CEPD3 (0x0008) /* Comp. E Disable Input Buffer of Port Register .3 */ +#define CEPD4 (0x0010) /* Comp. E Disable Input Buffer of Port Register .4 */ +#define CEPD5 (0x0020) /* Comp. E Disable Input Buffer of Port Register .5 */ +#define CEPD6 (0x0040) /* Comp. E Disable Input Buffer of Port Register .6 */ +#define CEPD7 (0x0080) /* Comp. E Disable Input Buffer of Port Register .7 */ +#define CEPD8 (0x0100) /* Comp. E Disable Input Buffer of Port Register .8 */ +#define CEPD9 (0x0200) /* Comp. E Disable Input Buffer of Port Register .9 */ +#define CEPD10 (0x0400) /* Comp. E Disable Input Buffer of Port Register .10 */ +#define CEPD11 (0x0800) /* Comp. E Disable Input Buffer of Port Register .11 */ +#define CEPD12 (0x1000) /* Comp. E Disable Input Buffer of Port Register .12 */ +#define CEPD13 (0x2000) /* Comp. E Disable Input Buffer of Port Register .13 */ +#define CEPD14 (0x4000) /* Comp. E Disable Input Buffer of Port Register .14 */ +#define CEPD15 (0x8000) /* Comp. E Disable Input Buffer of Port Register .15 */ + +#define CEPD0_L (0x0001) /* Comp. E Disable Input Buffer of Port Register .0 */ +#define CEPD1_L (0x0002) /* Comp. E Disable Input Buffer of Port Register .1 */ +#define CEPD2_L (0x0004) /* Comp. E Disable Input Buffer of Port Register .2 */ +#define CEPD3_L (0x0008) /* Comp. E Disable Input Buffer of Port Register .3 */ +#define CEPD4_L (0x0010) /* Comp. E Disable Input Buffer of Port Register .4 */ +#define CEPD5_L (0x0020) /* Comp. E Disable Input Buffer of Port Register .5 */ +#define CEPD6_L (0x0040) /* Comp. E Disable Input Buffer of Port Register .6 */ +#define CEPD7_L (0x0080) /* Comp. E Disable Input Buffer of Port Register .7 */ + +#define CEPD8_H (0x0001) /* Comp. E Disable Input Buffer of Port Register .8 */ +#define CEPD9_H (0x0002) /* Comp. E Disable Input Buffer of Port Register .9 */ +#define CEPD10_H (0x0004) /* Comp. E Disable Input Buffer of Port Register .10 */ +#define CEPD11_H (0x0008) /* Comp. E Disable Input Buffer of Port Register .11 */ +#define CEPD12_H (0x0010) /* Comp. E Disable Input Buffer of Port Register .12 */ +#define CEPD13_H (0x0020) /* Comp. E Disable Input Buffer of Port Register .13 */ +#define CEPD14_H (0x0040) /* Comp. E Disable Input Buffer of Port Register .14 */ +#define CEPD15_H (0x0080) /* Comp. E Disable Input Buffer of Port Register .15 */ + +/* CEINT Control Bits */ +#define CEIFG (0x0001) /* Comp. E Interrupt Flag */ +#define CEIIFG (0x0002) /* Comp. E Interrupt Flag Inverted Polarity */ +//#define RESERVED (0x0004) /* Comp. E */ +//#define RESERVED (0x0008) /* Comp. E */ +#define CERDYIFG (0x0010) /* Comp. E Comparator_E ready interrupt flag */ +//#define RESERVED (0x0020) /* Comp. E */ +//#define RESERVED (0x0040) /* Comp. E */ +//#define RESERVED (0x0080) /* Comp. E */ +#define CEIE (0x0100) /* Comp. E Interrupt Enable */ +#define CEIIE (0x0200) /* Comp. E Interrupt Enable Inverted Polarity */ +//#define RESERVED (0x0400) /* Comp. E */ +//#define RESERVED (0x0800) /* Comp. E */ +#define CERDYIE (0x1000) /* Comp. E Comparator_E ready interrupt enable */ +//#define RESERVED (0x2000) /* Comp. E */ +//#define RESERVED (0x4000) /* Comp. E */ +//#define RESERVED (0x8000) /* Comp. E */ + +/* CEINT Control Bits */ +#define CEIFG_L (0x0001) /* Comp. E Interrupt Flag */ +#define CEIIFG_L (0x0002) /* Comp. E Interrupt Flag Inverted Polarity */ +//#define RESERVED (0x0004) /* Comp. E */ +//#define RESERVED (0x0008) /* Comp. E */ +#define CERDYIFG_L (0x0010) /* Comp. E Comparator_E ready interrupt flag */ +//#define RESERVED (0x0020) /* Comp. E */ +//#define RESERVED (0x0040) /* Comp. E */ +//#define RESERVED (0x0080) /* Comp. E */ +//#define RESERVED (0x0400) /* Comp. E */ +//#define RESERVED (0x0800) /* Comp. E */ +//#define RESERVED (0x2000) /* Comp. E */ +//#define RESERVED (0x4000) /* Comp. E */ +//#define RESERVED (0x8000) /* Comp. E */ + +/* CEINT Control Bits */ +//#define RESERVED (0x0004) /* Comp. E */ +//#define RESERVED (0x0008) /* Comp. E */ +//#define RESERVED (0x0020) /* Comp. E */ +//#define RESERVED (0x0040) /* Comp. E */ +//#define RESERVED (0x0080) /* Comp. E */ +#define CEIE_H (0x0001) /* Comp. E Interrupt Enable */ +#define CEIIE_H (0x0002) /* Comp. E Interrupt Enable Inverted Polarity */ +//#define RESERVED (0x0400) /* Comp. E */ +//#define RESERVED (0x0800) /* Comp. E */ +#define CERDYIE_H (0x0010) /* Comp. E Comparator_E ready interrupt enable */ +//#define RESERVED (0x2000) /* Comp. E */ +//#define RESERVED (0x4000) /* Comp. E */ +//#define RESERVED (0x8000) /* Comp. E */ + +/* CEIV Definitions */ +#define CEIV_NONE (0x0000) /* No Interrupt pending */ +#define CEIV_CEIFG (0x0002) /* CEIFG */ +#define CEIV_CEIIFG (0x0004) /* CEIIFG */ +#define CEIV_CERDYIFG (0x000A) /* CERDYIFG */ + +#endif +/************************************************************* +* CRC Module +*************************************************************/ +#ifdef __MSP430_HAS_CRC__ /* Definition to show that Module is available */ + +#define OFS_CRCDI (0x0000) /* CRC Data In Register */ +#define OFS_CRCDI_L OFS_CRCDI +#define OFS_CRCDI_H OFS_CRCDI+1 +#define OFS_CRCDIRB (0x0002) /* CRC data in reverse byte Register */ +#define OFS_CRCDIRB_L OFS_CRCDIRB +#define OFS_CRCDIRB_H OFS_CRCDIRB+1 +#define OFS_CRCINIRES (0x0004) /* CRC Initialisation Register and Result Register */ +#define OFS_CRCINIRES_L OFS_CRCINIRES +#define OFS_CRCINIRES_H OFS_CRCINIRES+1 +#define OFS_CRCRESR (0x0006) /* CRC reverse result Register */ +#define OFS_CRCRESR_L OFS_CRCRESR +#define OFS_CRCRESR_H OFS_CRCRESR+1 + +#endif +/************************************************************* +* CRC Module +*************************************************************/ +#ifdef __MSP430_HAS_CRC32__ /* Definition to show that Module is available */ + + +//#define CRC32DIL0_O (0x0000) /* CRC32 Data In */ +#define OFS_CRC32DIW0 (0x0000) /* CRC32 Data In */ +#define OFS_CRC32DIW0_L OFS_CRC32DIW0 +#define OFS_CRC32DIW0_H OFS_CRC32DIW0+1 +#define OFS_CRC32DIW1 (0x0002) /* CRC32 Data In */ +#define OFS_CRC32DIW1_L OFS_CRC32DIW1 +#define OFS_CRC32DIW1_H OFS_CRC32DIW1+1 +#define CRC32DIB0 CRC32DIW0_L + +//#define CRC32DIRBL0_O (0x0004) /* CRC32 Data In Reversed Bit */ +#define OFS_CRC32DIRBW1 (0x0004) /* CRC32 Data In Reversed Bit */ +#define OFS_CRC32DIRBW1_L OFS_CRC32DIRBW1 +#define OFS_CRC32DIRBW1_H OFS_CRC32DIRBW1+1 +#define OFS_CRC32DIRBW0 (0x0006) /* CRC32 Data In Reversed Bit */ +#define OFS_CRC32DIRBW0_L OFS_CRC32DIRBW0 +#define OFS_CRC32DIRBW0_H OFS_CRC32DIRBW0+1 +#define CRC32DIRBB0 CRC32DIRBW0_H + +//#define CRC32INIRESL0_O (0x0008) /* CRC32 Initialization and Result */ +#define OFS_CRC32INIRESW0 (0x0008) /* CRC32 Initialization and Result */ +#define OFS_CRC32INIRESW0_L OFS_CRC32INIRESW0 +#define OFS_CRC32INIRESW0_H OFS_CRC32INIRESW0+1 +#define OFS_CRC32INIRESW1 (0x000A) /* CRC32 Initialization and Result */ +#define OFS_CRC32INIRESW1_L OFS_CRC32INIRESW1 +#define OFS_CRC32INIRESW1_H OFS_CRC32INIRESW1+1 +#define CRC32RESB0 CRC32INIRESW0_L +#define CRC32RESB1 CRC32INIRESW0_H +#define CRC32RESB2 CRC32INIRESW1_L +#define CRC32RESB3 CRC32INIRESW1_H + +//#define CRC32RESRL0_O (0x000C) /* CRC32 Result Reverse */ +#define OFS_CRC32RESRW1 (0x000C) /* CRC32 Result Reverse */ +#define OFS_CRC32RESRW1_L OFS_CRC32RESRW1 +#define OFS_CRC32RESRW1_H OFS_CRC32RESRW1+1 +#define OFS_CRC32RESRW0 (0x000E) /* CRC32 Result Reverse */ +#define OFS_CRC32RESRW0_L OFS_CRC32RESRW0 +#define OFS_CRC32RESRW0_H OFS_CRC32RESRW0+1 +#define CRC32RESRB3 CRC32RESRW1_L +#define CRC32RESRB2 CRC32RESRW1_H +#define CRC32RESRB1 CRC32RESRW0_L +#define CRC32RESRB0 CRC32RESRW0_H + +//#define CRC16DIL0_O (0x0010) /* CRC16 Data Input */ +#define OFS_CRC16DIW0 (0x0010) /* CRC16 Data Input */ +#define OFS_CRC16DIW0_L OFS_CRC16DIW0 +#define OFS_CRC16DIW0_H OFS_CRC16DIW0+1 +#define OFS_CRC16DIW1 (0x0012) /* CRC16 Data Input */ +#define OFS_CRC16DIW1_L OFS_CRC16DIW1 +#define OFS_CRC16DIW1_H OFS_CRC16DIW1+1 +#define CRC16DIB0 CRC16DIW0_L +//#define CRC16DIRBL0_O (0x0014) /* CRC16 Data In Reverse */ +#define OFS_CRC16DIRBW1 (0x0014) /* CRC16 Data In Reverse */ +#define OFS_CRC16DIRBW1_L OFS_CRC16DIRBW1 +#define OFS_CRC16DIRBW1_H OFS_CRC16DIRBW1+1 +#define OFS_CRC16DIRBW0 (0x0016) /* CRC16 Data In Reverse */ +#define OFS_CRC16DIRBW0_L OFS_CRC16DIRBW0 +#define OFS_CRC16DIRBW0_H OFS_CRC16DIRBW0+1 +#define CRC16DIRBB0 CRC16DIRBW0_L + +//#define CRC16INIRESL0_O (0x0018) /* CRC16 Init and Result */ +#define OFS_CRC16INIRESW0 (0x0018) /* CRC16 Init and Result */ +#define OFS_CRC16INIRESW0_L OFS_CRC16INIRESW0 +#define OFS_CRC16INIRESW0_H OFS_CRC16INIRESW0+1 +#define CRC16INIRESB1 CRC16INIRESW0_H +#define CRC16INIRESB0 CRC16INIRESW0_L + +//#define CRC16RESRL0_O (0x001E) /* CRC16 Result Reverse */ +#define OFS_CRC16RESRW0 (0x001E) /* CRC16 Result Reverse */ +#define OFS_CRC16RESRW0_L OFS_CRC16RESRW0 +#define OFS_CRC16RESRW0_H OFS_CRC16RESRW0+1 +#define OFS_CRC16RESRW1 (0x001C) /* CRC16 Result Reverse */ +#define OFS_CRC16RESRW1_L OFS_CRC16RESRW1 +#define OFS_CRC16RESRW1_H OFS_CRC16RESRW1+1 +#define CRC16RESRB1 CRC16RESRW0_L +#define CRC16RESRB0 CRC16RESRW0_H + +#endif +/************************************************************ +* CLOCK SYSTEM +************************************************************/ +#ifdef __MSP430_HAS_CS__ /* Definition to show that Module is available */ + +#define OFS_CSCTL0 (0x0000) /* CS Control Register 0 */ +#define OFS_CSCTL0_L OFS_CSCTL0 +#define OFS_CSCTL0_H OFS_CSCTL0+1 +#define OFS_CSCTL1 (0x0002) /* CS Control Register 1 */ +#define OFS_CSCTL1_L OFS_CSCTL1 +#define OFS_CSCTL1_H OFS_CSCTL1+1 +#define OFS_CSCTL2 (0x0004) /* CS Control Register 2 */ +#define OFS_CSCTL2_L OFS_CSCTL2 +#define OFS_CSCTL2_H OFS_CSCTL2+1 +#define OFS_CSCTL3 (0x0006) /* CS Control Register 3 */ +#define OFS_CSCTL3_L OFS_CSCTL3 +#define OFS_CSCTL3_H OFS_CSCTL3+1 +#define OFS_CSCTL4 (0x0008) /* CS Control Register 4 */ +#define OFS_CSCTL4_L OFS_CSCTL4 +#define OFS_CSCTL4_H OFS_CSCTL4+1 +#define OFS_CSCTL5 (0x000A) /* CS Control Register 5 */ +#define OFS_CSCTL5_L OFS_CSCTL5 +#define OFS_CSCTL5_H OFS_CSCTL5+1 +#define OFS_CSCTL6 (0x000C) /* CS Control Register 6 */ +#define OFS_CSCTL6_L OFS_CSCTL6 +#define OFS_CSCTL6_H OFS_CSCTL6+1 + +/* CSCTL0 Control Bits */ + +#define CSKEY (0xA500) /* CS Password */ +#define CSKEY_H (0xA5) /* CS Password for high byte access */ + +/* CSCTL1 Control Bits */ +#define DCOFSEL0 (0x0002) /* DCO frequency select Bit: 0 */ +#define DCOFSEL1 (0x0004) /* DCO frequency select Bit: 1 */ +#define DCOFSEL2 (0x0008) /* DCO frequency select Bit: 2 */ +#define DCORSEL (0x0040) /* DCO range select. */ + +/* CSCTL1 Control Bits */ +#define DCOFSEL0_L (0x0002) /* DCO frequency select Bit: 0 */ +#define DCOFSEL1_L (0x0004) /* DCO frequency select Bit: 1 */ +#define DCOFSEL2_L (0x0008) /* DCO frequency select Bit: 2 */ +#define DCORSEL_L (0x0040) /* DCO range select. */ + +#define DCOFSEL_0 (0x0000) /* DCO frequency select: 0 */ +#define DCOFSEL_1 (0x0002) /* DCO frequency select: 1 */ +#define DCOFSEL_2 (0x0004) /* DCO frequency select: 2 */ +#define DCOFSEL_3 (0x0006) /* DCO frequency select: 3 */ +#define DCOFSEL_4 (0x0008) /* DCO frequency select: 4 */ +#define DCOFSEL_5 (0x000A) /* DCO frequency select: 5 */ +#define DCOFSEL_6 (0x000C) /* DCO frequency select: 6 */ +#define DCOFSEL_7 (0x000E) /* DCO frequency select: 7 */ + +/* CSCTL2 Control Bits */ +#define SELM0 (0x0001) /* MCLK Source Select Bit: 0 */ +#define SELM1 (0x0002) /* MCLK Source Select Bit: 1 */ +#define SELM2 (0x0004) /* MCLK Source Select Bit: 2 */ +//#define RESERVED (0x0004) /* RESERVED */ +//#define RESERVED (0x0008) /* RESERVED */ +#define SELS0 (0x0010) /* SMCLK Source Select Bit: 0 */ +#define SELS1 (0x0020) /* SMCLK Source Select Bit: 1 */ +#define SELS2 (0x0040) /* SMCLK Source Select Bit: 2 */ +//#define RESERVED (0x0040) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +#define SELA0 (0x0100) /* ACLK Source Select Bit: 0 */ +#define SELA1 (0x0200) /* ACLK Source Select Bit: 1 */ +#define SELA2 (0x0400) /* ACLK Source Select Bit: 2 */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* CSCTL2 Control Bits */ +#define SELM0_L (0x0001) /* MCLK Source Select Bit: 0 */ +#define SELM1_L (0x0002) /* MCLK Source Select Bit: 1 */ +#define SELM2_L (0x0004) /* MCLK Source Select Bit: 2 */ +//#define RESERVED (0x0004) /* RESERVED */ +//#define RESERVED (0x0008) /* RESERVED */ +#define SELS0_L (0x0010) /* SMCLK Source Select Bit: 0 */ +#define SELS1_L (0x0020) /* SMCLK Source Select Bit: 1 */ +#define SELS2_L (0x0040) /* SMCLK Source Select Bit: 2 */ +//#define RESERVED (0x0040) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* CSCTL2 Control Bits */ +//#define RESERVED (0x0004) /* RESERVED */ +//#define RESERVED (0x0008) /* RESERVED */ +//#define RESERVED (0x0040) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +#define SELA0_H (0x0001) /* ACLK Source Select Bit: 0 */ +#define SELA1_H (0x0002) /* ACLK Source Select Bit: 1 */ +#define SELA2_H (0x0004) /* ACLK Source Select Bit: 2 */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +#define SELM_0 (0x0000) /* MCLK Source Select 0 */ +#define SELM_1 (0x0001) /* MCLK Source Select 1 */ +#define SELM_2 (0x0002) /* MCLK Source Select 2 */ +#define SELM_3 (0x0003) /* MCLK Source Select 3 */ +#define SELM_4 (0x0004) /* MCLK Source Select 4 */ +#define SELM_5 (0x0005) /* MCLK Source Select 5 */ +#define SELM_6 (0x0006) /* MCLK Source Select 6 */ +#define SELM_7 (0x0007) /* MCLK Source Select 7 */ +#define SELM__LFXTCLK (0x0000) /* MCLK Source Select LFXTCLK */ +#define SELM__VLOCLK (0x0001) /* MCLK Source Select VLOCLK */ +#define SELM__LFMODOSC (0x0002) /* MCLK Source Select LFMODOSC */ +#define SELM__DCOCLK (0x0003) /* MCLK Source Select DCOCLK */ +#define SELM__MODOSC (0x0004) /* MCLK Source Select MODOSC */ +#define SELM__HFXTCLK (0x0005) /* MCLK Source Select HFXTCLK */ + +#define SELS_0 (0x0000) /* SMCLK Source Select 0 */ +#define SELS_1 (0x0010) /* SMCLK Source Select 1 */ +#define SELS_2 (0x0020) /* SMCLK Source Select 2 */ +#define SELS_3 (0x0030) /* SMCLK Source Select 3 */ +#define SELS_4 (0x0040) /* SMCLK Source Select 4 */ +#define SELS_5 (0x0050) /* SMCLK Source Select 5 */ +#define SELS_6 (0x0060) /* SMCLK Source Select 6 */ +#define SELS_7 (0x0070) /* SMCLK Source Select 7 */ +#define SELS__LFXTCLK (0x0000) /* SMCLK Source Select LFXTCLK */ +#define SELS__VLOCLK (0x0010) /* SMCLK Source Select VLOCLK */ +#define SELS__LFMODOSC (0x0020) /* SMCLK Source Select LFMODOSC */ +#define SELS__DCOCLK (0x0030) /* SMCLK Source Select DCOCLK */ +#define SELS__MODOSC (0x0040) /* SMCLK Source Select MODOSC */ +#define SELS__HFXTCLK (0x0050) /* SMCLK Source Select HFXTCLK */ + +#define SELA_0 (0x0000) /* ACLK Source Select 0 */ +#define SELA_1 (0x0100) /* ACLK Source Select 1 */ +#define SELA_2 (0x0200) /* ACLK Source Select 2 */ +#define SELA_3 (0x0300) /* ACLK Source Select 3 */ +#define SELA_4 (0x0400) /* ACLK Source Select 4 */ +#define SELA_5 (0x0500) /* ACLK Source Select 5 */ +#define SELA_6 (0x0600) /* ACLK Source Select 6 */ +#define SELA_7 (0x0700) /* ACLK Source Select 7 */ +#define SELA__LFXTCLK (0x0000) /* ACLK Source Select LFXTCLK */ +#define SELA__VLOCLK (0x0100) /* ACLK Source Select VLOCLK */ +#define SELA__LFMODOSC (0x0200) /* ACLK Source Select LFMODOSC */ + +/* CSCTL3 Control Bits */ +#define DIVM0 (0x0001) /* MCLK Divider Bit: 0 */ +#define DIVM1 (0x0002) /* MCLK Divider Bit: 1 */ +#define DIVM2 (0x0004) /* MCLK Divider Bit: 2 */ +//#define RESERVED (0x0004) /* RESERVED */ +//#define RESERVED (0x0008) /* RESERVED */ +#define DIVS0 (0x0010) /* SMCLK Divider Bit: 0 */ +#define DIVS1 (0x0020) /* SMCLK Divider Bit: 1 */ +#define DIVS2 (0x0040) /* SMCLK Divider Bit: 2 */ +//#define RESERVED (0x0040) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +#define DIVA0 (0x0100) /* ACLK Divider Bit: 0 */ +#define DIVA1 (0x0200) /* ACLK Divider Bit: 1 */ +#define DIVA2 (0x0400) /* ACLK Divider Bit: 2 */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* CSCTL3 Control Bits */ +#define DIVM0_L (0x0001) /* MCLK Divider Bit: 0 */ +#define DIVM1_L (0x0002) /* MCLK Divider Bit: 1 */ +#define DIVM2_L (0x0004) /* MCLK Divider Bit: 2 */ +//#define RESERVED (0x0004) /* RESERVED */ +//#define RESERVED (0x0008) /* RESERVED */ +#define DIVS0_L (0x0010) /* SMCLK Divider Bit: 0 */ +#define DIVS1_L (0x0020) /* SMCLK Divider Bit: 1 */ +#define DIVS2_L (0x0040) /* SMCLK Divider Bit: 2 */ +//#define RESERVED (0x0040) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* CSCTL3 Control Bits */ +//#define RESERVED (0x0004) /* RESERVED */ +//#define RESERVED (0x0008) /* RESERVED */ +//#define RESERVED (0x0040) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +#define DIVA0_H (0x0001) /* ACLK Divider Bit: 0 */ +#define DIVA1_H (0x0002) /* ACLK Divider Bit: 1 */ +#define DIVA2_H (0x0004) /* ACLK Divider Bit: 2 */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +#define DIVM_0 (0x0000) /* MCLK Source Divider 0 */ +#define DIVM_1 (0x0001) /* MCLK Source Divider 1 */ +#define DIVM_2 (0x0002) /* MCLK Source Divider 2 */ +#define DIVM_3 (0x0003) /* MCLK Source Divider 3 */ +#define DIVM_4 (0x0004) /* MCLK Source Divider 4 */ +#define DIVM_5 (0x0005) /* MCLK Source Divider 5 */ +#define DIVM__1 (0x0000) /* MCLK Source Divider f(MCLK)/1 */ +#define DIVM__2 (0x0001) /* MCLK Source Divider f(MCLK)/2 */ +#define DIVM__4 (0x0002) /* MCLK Source Divider f(MCLK)/4 */ +#define DIVM__8 (0x0003) /* MCLK Source Divider f(MCLK)/8 */ +#define DIVM__16 (0x0004) /* MCLK Source Divider f(MCLK)/16 */ +#define DIVM__32 (0x0005) /* MCLK Source Divider f(MCLK)/32 */ + +#define DIVS_0 (0x0000) /* SMCLK Source Divider 0 */ +#define DIVS_1 (0x0010) /* SMCLK Source Divider 1 */ +#define DIVS_2 (0x0020) /* SMCLK Source Divider 2 */ +#define DIVS_3 (0x0030) /* SMCLK Source Divider 3 */ +#define DIVS_4 (0x0040) /* SMCLK Source Divider 4 */ +#define DIVS_5 (0x0050) /* SMCLK Source Divider 5 */ +#define DIVS__1 (0x0000) /* SMCLK Source Divider f(SMCLK)/1 */ +#define DIVS__2 (0x0010) /* SMCLK Source Divider f(SMCLK)/2 */ +#define DIVS__4 (0x0020) /* SMCLK Source Divider f(SMCLK)/4 */ +#define DIVS__8 (0x0030) /* SMCLK Source Divider f(SMCLK)/8 */ +#define DIVS__16 (0x0040) /* SMCLK Source Divider f(SMCLK)/16 */ +#define DIVS__32 (0x0050) /* SMCLK Source Divider f(SMCLK)/32 */ + +#define DIVA_0 (0x0000) /* ACLK Source Divider 0 */ +#define DIVA_1 (0x0100) /* ACLK Source Divider 1 */ +#define DIVA_2 (0x0200) /* ACLK Source Divider 2 */ +#define DIVA_3 (0x0300) /* ACLK Source Divider 3 */ +#define DIVA_4 (0x0400) /* ACLK Source Divider 4 */ +#define DIVA_5 (0x0500) /* ACLK Source Divider 5 */ +#define DIVA__1 (0x0000) /* ACLK Source Divider f(ACLK)/1 */ +#define DIVA__2 (0x0100) /* ACLK Source Divider f(ACLK)/2 */ +#define DIVA__4 (0x0200) /* ACLK Source Divider f(ACLK)/4 */ +#define DIVA__8 (0x0300) /* ACLK Source Divider f(ACLK)/8 */ +#define DIVA__16 (0x0400) /* ACLK Source Divider f(ACLK)/16 */ +#define DIVA__32 (0x0500) /* ACLK Source Divider f(ACLK)/32 */ + +/* CSCTL4 Control Bits */ +#define LFXTOFF (0x0001) /* High Frequency Oscillator 1 (XT1) disable */ +#define SMCLKOFF (0x0002) /* SMCLK Off */ +#define VLOOFF (0x0008) /* VLO Off */ +#define LFXTBYPASS (0x0010) /* LFXT bypass mode : 0: internal 1:sourced from external pin */ +#define LFXTAGCOFF (0x0020) /* LFXT automatic gain control off */ +#define LFXTDRIVE0 (0x0040) /* LFXT Drive Level mode Bit 0 */ +#define LFXTDRIVE1 (0x0080) /* LFXT Drive Level mode Bit 1 */ +#define HFXTOFF (0x0100) /* High Frequency Oscillator disable */ +#define HFFREQ0 (0x0400) /* HFXT frequency selection Bit 1 */ +#define HFFREQ1 (0x0800) /* HFXT frequency selection Bit 0 */ +#define HFXTBYPASS (0x1000) /* HFXT bypass mode : 0: internal 1:sourced from external pin */ +#define HFXTDRIVE0 (0x4000) /* HFXT Drive Level mode Bit 0 */ +#define HFXTDRIVE1 (0x8000) /* HFXT Drive Level mode Bit 1 */ + +/* CSCTL4 Control Bits */ +#define LFXTOFF_L (0x0001) /* High Frequency Oscillator 1 (XT1) disable */ +#define SMCLKOFF_L (0x0002) /* SMCLK Off */ +#define VLOOFF_L (0x0008) /* VLO Off */ +#define LFXTBYPASS_L (0x0010) /* LFXT bypass mode : 0: internal 1:sourced from external pin */ +#define LFXTAGCOFF_L (0x0020) /* LFXT automatic gain control off */ +#define LFXTDRIVE0_L (0x0040) /* LFXT Drive Level mode Bit 0 */ +#define LFXTDRIVE1_L (0x0080) /* LFXT Drive Level mode Bit 1 */ + +/* CSCTL4 Control Bits */ +#define HFXTOFF_H (0x0001) /* High Frequency Oscillator disable */ +#define HFFREQ0_H (0x0004) /* HFXT frequency selection Bit 1 */ +#define HFFREQ1_H (0x0008) /* HFXT frequency selection Bit 0 */ +#define HFXTBYPASS_H (0x0010) /* HFXT bypass mode : 0: internal 1:sourced from external pin */ +#define HFXTDRIVE0_H (0x0040) /* HFXT Drive Level mode Bit 0 */ +#define HFXTDRIVE1_H (0x0080) /* HFXT Drive Level mode Bit 1 */ + +#define LFXTDRIVE_0 (0x0000) /* LFXT Drive Level mode: 0 */ +#define LFXTDRIVE_1 (0x0040) /* LFXT Drive Level mode: 1 */ +#define LFXTDRIVE_2 (0x0080) /* LFXT Drive Level mode: 2 */ +#define LFXTDRIVE_3 (0x00C0) /* LFXT Drive Level mode: 3 */ + +#define HFFREQ_0 (0x0000) /* HFXT frequency selection: 0 */ +#define HFFREQ_1 (0x0400) /* HFXT frequency selection: 1 */ +#define HFFREQ_2 (0x0800) /* HFXT frequency selection: 2 */ +#define HFFREQ_3 (0x0C00) /* HFXT frequency selection: 3 */ + +#define HFXTDRIVE_0 (0x0000) /* HFXT Drive Level mode: 0 */ +#define HFXTDRIVE_1 (0x4000) /* HFXT Drive Level mode: 1 */ +#define HFXTDRIVE_2 (0x8000) /* HFXT Drive Level mode: 2 */ +#define HFXTDRIVE_3 (0xC000) /* HFXT Drive Level mode: 3 */ + +/* CSCTL5 Control Bits */ +#define LFXTOFFG (0x0001) /* LFXT Low Frequency Oscillator Fault Flag */ +#define HFXTOFFG (0x0002) /* HFXT High Frequency Oscillator Fault Flag */ +#define ENSTFCNT1 (0x0040) /* Enable start counter for XT1 */ +#define ENSTFCNT2 (0x0080) /* Enable start counter for XT2 */ + +/* CSCTL5 Control Bits */ +#define LFXTOFFG_L (0x0001) /* LFXT Low Frequency Oscillator Fault Flag */ +#define HFXTOFFG_L (0x0002) /* HFXT High Frequency Oscillator Fault Flag */ +#define ENSTFCNT1_L (0x0040) /* Enable start counter for XT1 */ +#define ENSTFCNT2_L (0x0080) /* Enable start counter for XT2 */ + +/* CSCTL6 Control Bits */ +#define ACLKREQEN (0x0001) /* ACLK Clock Request Enable */ +#define MCLKREQEN (0x0002) /* MCLK Clock Request Enable */ +#define SMCLKREQEN (0x0004) /* SMCLK Clock Request Enable */ +#define MODCLKREQEN (0x0008) /* MODOSC Clock Request Enable */ + +/* CSCTL6 Control Bits */ +#define ACLKREQEN_L (0x0001) /* ACLK Clock Request Enable */ +#define MCLKREQEN_L (0x0002) /* MCLK Clock Request Enable */ +#define SMCLKREQEN_L (0x0004) /* SMCLK Clock Request Enable */ +#define MODCLKREQEN_L (0x0008) /* MODOSC Clock Request Enable */ + +#endif +/************************************************************ +* DMA_X +************************************************************/ +#ifdef __MSP430_HAS_DMAX_3__ /* Definition to show that Module is available */ + +#define OFS_DMACTL0 (0x0000) /* DMA Module Control 0 */ +#define OFS_DMACTL0_L OFS_DMACTL0 +#define OFS_DMACTL0_H OFS_DMACTL0+1 +#define OFS_DMACTL1 (0x0002) /* DMA Module Control 1 */ +#define OFS_DMACTL1_L OFS_DMACTL1 +#define OFS_DMACTL1_H OFS_DMACTL1+1 +#define OFS_DMACTL2 (0x0004) /* DMA Module Control 2 */ +#define OFS_DMACTL2_L OFS_DMACTL2 +#define OFS_DMACTL2_H OFS_DMACTL2+1 +#define OFS_DMACTL3 (0x0006) /* DMA Module Control 3 */ +#define OFS_DMACTL3_L OFS_DMACTL3 +#define OFS_DMACTL3_H OFS_DMACTL3+1 +#define OFS_DMACTL4 (0x0008) /* DMA Module Control 4 */ +#define OFS_DMACTL4_L OFS_DMACTL4 +#define OFS_DMACTL4_H OFS_DMACTL4+1 +#define OFS_DMAIV (0x000E) /* DMA Interrupt Vector Word */ +#define OFS_DMAIV_L OFS_DMAIV +#define OFS_DMAIV_H OFS_DMAIV+1 + +#define OFS_DMA0CTL (0x0010) /* DMA Channel 0 Control */ +#define OFS_DMA0CTL_L OFS_DMA0CTL +#define OFS_DMA0CTL_H OFS_DMA0CTL+1 +#define OFS_DMA0SA (0x0012) /* DMA Channel 0 Source Address */ +#define OFS_DMA0DA (0x0016) /* DMA Channel 0 Destination Address */ +#define OFS_DMA0SZ (0x001A) /* DMA Channel 0 Transfer Size */ + +#define OFS_DMA1CTL (0x0020) /* DMA Channel 1 Control */ +#define OFS_DMA1CTL_L OFS_DMA1CTL +#define OFS_DMA1CTL_H OFS_DMA1CTL+1 +#define OFS_DMA1SA (0x0022) /* DMA Channel 1 Source Address */ +#define OFS_DMA1DA (0x0026) /* DMA Channel 1 Destination Address */ +#define OFS_DMA1SZ (0x002A) /* DMA Channel 1 Transfer Size */ + +#define OFS_DMA2CTL (0x0030) /* DMA Channel 2 Control */ +#define OFS_DMA2CTL_L OFS_DMA2CTL +#define OFS_DMA2CTL_H OFS_DMA2CTL+1 +#define OFS_DMA2SA (0x0032) /* DMA Channel 2 Source Address */ +#define OFS_DMA2DA (0x0036) /* DMA Channel 2 Destination Address */ +#define OFS_DMA2SZ (0x003A) /* DMA Channel 2 Transfer Size */ + +/* DMACTL0 Control Bits */ +#define DMA0TSEL0 (0x0001) /* DMA channel 0 transfer select bit 0 */ +#define DMA0TSEL1 (0x0002) /* DMA channel 0 transfer select bit 1 */ +#define DMA0TSEL2 (0x0004) /* DMA channel 0 transfer select bit 2 */ +#define DMA0TSEL3 (0x0008) /* DMA channel 0 transfer select bit 3 */ +#define DMA0TSEL4 (0x0010) /* DMA channel 0 transfer select bit 4 */ +#define DMA1TSEL0 (0x0100) /* DMA channel 1 transfer select bit 0 */ +#define DMA1TSEL1 (0x0200) /* DMA channel 1 transfer select bit 1 */ +#define DMA1TSEL2 (0x0400) /* DMA channel 1 transfer select bit 2 */ +#define DMA1TSEL3 (0x0800) /* DMA channel 1 transfer select bit 3 */ +#define DMA1TSEL4 (0x1000) /* DMA channel 1 transfer select bit 4 */ + +/* DMACTL0 Control Bits */ +#define DMA0TSEL0_L (0x0001) /* DMA channel 0 transfer select bit 0 */ +#define DMA0TSEL1_L (0x0002) /* DMA channel 0 transfer select bit 1 */ +#define DMA0TSEL2_L (0x0004) /* DMA channel 0 transfer select bit 2 */ +#define DMA0TSEL3_L (0x0008) /* DMA channel 0 transfer select bit 3 */ +#define DMA0TSEL4_L (0x0010) /* DMA channel 0 transfer select bit 4 */ + +/* DMACTL0 Control Bits */ +#define DMA1TSEL0_H (0x0001) /* DMA channel 1 transfer select bit 0 */ +#define DMA1TSEL1_H (0x0002) /* DMA channel 1 transfer select bit 1 */ +#define DMA1TSEL2_H (0x0004) /* DMA channel 1 transfer select bit 2 */ +#define DMA1TSEL3_H (0x0008) /* DMA channel 1 transfer select bit 3 */ +#define DMA1TSEL4_H (0x0010) /* DMA channel 1 transfer select bit 4 */ + +/* DMACTL01 Control Bits */ +#define DMA2TSEL0 (0x0001) /* DMA channel 2 transfer select bit 0 */ +#define DMA2TSEL1 (0x0002) /* DMA channel 2 transfer select bit 1 */ +#define DMA2TSEL2 (0x0004) /* DMA channel 2 transfer select bit 2 */ +#define DMA2TSEL3 (0x0008) /* DMA channel 2 transfer select bit 3 */ +#define DMA2TSEL4 (0x0010) /* DMA channel 2 transfer select bit 4 */ + +/* DMACTL01 Control Bits */ +#define DMA2TSEL0_L (0x0001) /* DMA channel 2 transfer select bit 0 */ +#define DMA2TSEL1_L (0x0002) /* DMA channel 2 transfer select bit 1 */ +#define DMA2TSEL2_L (0x0004) /* DMA channel 2 transfer select bit 2 */ +#define DMA2TSEL3_L (0x0008) /* DMA channel 2 transfer select bit 3 */ +#define DMA2TSEL4_L (0x0010) /* DMA channel 2 transfer select bit 4 */ + +/* DMACTL4 Control Bits */ +#define ENNMI (0x0001) /* Enable NMI interruption of DMA */ +#define ROUNDROBIN (0x0002) /* Round-Robin DMA channel priorities */ +#define DMARMWDIS (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */ + +/* DMACTL4 Control Bits */ +#define ENNMI_L (0x0001) /* Enable NMI interruption of DMA */ +#define ROUNDROBIN_L (0x0002) /* Round-Robin DMA channel priorities */ +#define DMARMWDIS_L (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */ + +/* DMAxCTL Control Bits */ +#define DMAREQ (0x0001) /* Initiate DMA transfer with DMATSEL */ +#define DMAABORT (0x0002) /* DMA transfer aborted by NMI */ +#define DMAIE (0x0004) /* DMA interrupt enable */ +#define DMAIFG (0x0008) /* DMA interrupt flag */ +#define DMAEN (0x0010) /* DMA enable */ +#define DMALEVEL (0x0020) /* DMA level sensitive trigger select */ +#define DMASRCBYTE (0x0040) /* DMA source byte */ +#define DMADSTBYTE (0x0080) /* DMA destination byte */ +#define DMASRCINCR0 (0x0100) /* DMA source increment bit 0 */ +#define DMASRCINCR1 (0x0200) /* DMA source increment bit 1 */ +#define DMADSTINCR0 (0x0400) /* DMA destination increment bit 0 */ +#define DMADSTINCR1 (0x0800) /* DMA destination increment bit 1 */ +#define DMADT0 (0x1000) /* DMA transfer mode bit 0 */ +#define DMADT1 (0x2000) /* DMA transfer mode bit 1 */ +#define DMADT2 (0x4000) /* DMA transfer mode bit 2 */ + +/* DMAxCTL Control Bits */ +#define DMAREQ_L (0x0001) /* Initiate DMA transfer with DMATSEL */ +#define DMAABORT_L (0x0002) /* DMA transfer aborted by NMI */ +#define DMAIE_L (0x0004) /* DMA interrupt enable */ +#define DMAIFG_L (0x0008) /* DMA interrupt flag */ +#define DMAEN_L (0x0010) /* DMA enable */ +#define DMALEVEL_L (0x0020) /* DMA level sensitive trigger select */ +#define DMASRCBYTE_L (0x0040) /* DMA source byte */ +#define DMADSTBYTE_L (0x0080) /* DMA destination byte */ + +/* DMAxCTL Control Bits */ +#define DMASRCINCR0_H (0x0001) /* DMA source increment bit 0 */ +#define DMASRCINCR1_H (0x0002) /* DMA source increment bit 1 */ +#define DMADSTINCR0_H (0x0004) /* DMA destination increment bit 0 */ +#define DMADSTINCR1_H (0x0008) /* DMA destination increment bit 1 */ +#define DMADT0_H (0x0010) /* DMA transfer mode bit 0 */ +#define DMADT1_H (0x0020) /* DMA transfer mode bit 1 */ +#define DMADT2_H (0x0040) /* DMA transfer mode bit 2 */ + +#define DMASWDW (0*0x0040u) /* DMA transfer: source word to destination word */ +#define DMASBDW (1*0x0040u) /* DMA transfer: source byte to destination word */ +#define DMASWDB (2*0x0040u) /* DMA transfer: source word to destination byte */ +#define DMASBDB (3*0x0040u) /* DMA transfer: source byte to destination byte */ + +#define DMASRCINCR_0 (0*0x0100u) /* DMA source increment 0: source address unchanged */ +#define DMASRCINCR_1 (1*0x0100u) /* DMA source increment 1: source address unchanged */ +#define DMASRCINCR_2 (2*0x0100u) /* DMA source increment 2: source address decremented */ +#define DMASRCINCR_3 (3*0x0100u) /* DMA source increment 3: source address incremented */ + +#define DMADSTINCR_0 (0*0x0400u) /* DMA destination increment 0: destination address unchanged */ +#define DMADSTINCR_1 (1*0x0400u) /* DMA destination increment 1: destination address unchanged */ +#define DMADSTINCR_2 (2*0x0400u) /* DMA destination increment 2: destination address decremented */ +#define DMADSTINCR_3 (3*0x0400u) /* DMA destination increment 3: destination address incremented */ + +#define DMADT_0 (0*0x1000u) /* DMA transfer mode 0: Single transfer */ +#define DMADT_1 (1*0x1000u) /* DMA transfer mode 1: Block transfer */ +#define DMADT_2 (2*0x1000u) /* DMA transfer mode 2: Burst-Block transfer */ +#define DMADT_3 (3*0x1000u) /* DMA transfer mode 3: Burst-Block transfer */ +#define DMADT_4 (4*0x1000u) /* DMA transfer mode 4: Repeated Single transfer */ +#define DMADT_5 (5*0x1000u) /* DMA transfer mode 5: Repeated Block transfer */ +#define DMADT_6 (6*0x1000u) /* DMA transfer mode 6: Repeated Burst-Block transfer */ +#define DMADT_7 (7*0x1000u) /* DMA transfer mode 7: Repeated Burst-Block transfer */ + +/* DMAIV Definitions */ +#define DMAIV_NONE (0x0000) /* No Interrupt pending */ +#define DMAIV_DMA0IFG (0x0002) /* DMA0IFG*/ +#define DMAIV_DMA1IFG (0x0004) /* DMA1IFG*/ +#define DMAIV_DMA2IFG (0x0006) /* DMA2IFG*/ + +#endif +/************************************************************ +* EXTENDED SCAN INTERFACE +************************************************************/ +#ifdef __MSP430_HAS_ESI__ /* Definition to show that Module is available */ + +#define OFS_ESIDEBUG1 (0x0000) /* ESI debug register 1 */ +#define OFS_ESIDEBUG1_L OFS_ESIDEBUG1 +#define OFS_ESIDEBUG1_H OFS_ESIDEBUG1+1 +#define OFS_ESIDEBUG2 (0x0002) /* ESI debug register 2 */ +#define OFS_ESIDEBUG2_L OFS_ESIDEBUG2 +#define OFS_ESIDEBUG2_H OFS_ESIDEBUG2+1 +#define OFS_ESIDEBUG3 (0x0004) /* ESI debug register 3 */ +#define OFS_ESIDEBUG3_L OFS_ESIDEBUG3 +#define OFS_ESIDEBUG3_H OFS_ESIDEBUG3+1 +#define OFS_ESIDEBUG4 (0x0006) /* ESI debug register 4 */ +#define OFS_ESIDEBUG4_L OFS_ESIDEBUG4 +#define OFS_ESIDEBUG4_H OFS_ESIDEBUG4+1 +#define OFS_ESIDEBUG5 (0x0008) /* ESI debug register 5 */ +#define OFS_ESIDEBUG5_L OFS_ESIDEBUG5 +#define OFS_ESIDEBUG5_H OFS_ESIDEBUG5+1 +#define OFS_ESICNT0 (0x0010) /* ESI PSM counter 0 */ +#define OFS_ESICNT0_L OFS_ESICNT0 +#define OFS_ESICNT0_H OFS_ESICNT0+1 +#define OFS_ESICNT1 (0x0012) /* ESI PSM counter 1 */ +#define OFS_ESICNT1_L OFS_ESICNT1 +#define OFS_ESICNT1_H OFS_ESICNT1+1 +#define OFS_ESICNT2 (0x0014) /* ESI PSM counter 2 */ +#define OFS_ESICNT2_L OFS_ESICNT2 +#define OFS_ESICNT2_H OFS_ESICNT2+1 +#define OFS_ESICNT3 (0x0016) /* ESI oscillator counter register */ +#define OFS_ESICNT3_L OFS_ESICNT3 +#define OFS_ESICNT3_H OFS_ESICNT3+1 +#define OFS_ESIIV (0x001A) /* ESI interrupt vector */ +#define OFS_ESIIV_L OFS_ESIIV +#define OFS_ESIIV_H OFS_ESIIV+1 +#define OFS_ESIINT1 (0x001C) /* ESI interrupt register 1 */ +#define OFS_ESIINT1_L OFS_ESIINT1 +#define OFS_ESIINT1_H OFS_ESIINT1+1 +#define OFS_ESIINT2 (0x001E) /* ESI interrupt register 2 */ +#define OFS_ESIINT2_L OFS_ESIINT2 +#define OFS_ESIINT2_H OFS_ESIINT2+1 +#define OFS_ESIAFE (0x0020) /* ESI AFE control register */ +#define OFS_ESIAFE_L OFS_ESIAFE +#define OFS_ESIAFE_H OFS_ESIAFE+1 +#define OFS_ESIPPU (0x0022) /* ESI PPU control register */ +#define OFS_ESIPPU_L OFS_ESIPPU +#define OFS_ESIPPU_H OFS_ESIPPU+1 +#define OFS_ESITSM (0x0024) /* ESI TSM control register */ +#define OFS_ESITSM_L OFS_ESITSM +#define OFS_ESITSM_H OFS_ESITSM+1 +#define OFS_ESIPSM (0x0026) /* ESI PSM control register */ +#define OFS_ESIPSM_L OFS_ESIPSM +#define OFS_ESIPSM_H OFS_ESIPSM+1 +#define OFS_ESIOSC (0x0028) /* ESI oscillator control register*/ +#define OFS_ESIOSC_L OFS_ESIOSC +#define OFS_ESIOSC_H OFS_ESIOSC+1 +#define OFS_ESICTL (0x002A) /* ESI control register */ +#define OFS_ESICTL_L OFS_ESICTL +#define OFS_ESICTL_H OFS_ESICTL+1 +#define OFS_ESITHR1 (0x002C) /* ESI PSM Counter Threshold 1 register */ +#define OFS_ESITHR1_L OFS_ESITHR1 +#define OFS_ESITHR1_H OFS_ESITHR1+1 +#define OFS_ESITHR2 (0x002E) /* ESI PSM Counter Threshold 2 register */ +#define OFS_ESITHR2_L OFS_ESITHR2 +#define OFS_ESITHR2_H OFS_ESITHR2+1 +#define OFS_ESIDAC1R0 (0x0040) /* ESI DAC1 register 0 */ +#define OFS_ESIDAC1R0_L OFS_ESIDAC1R0 +#define OFS_ESIDAC1R0_H OFS_ESIDAC1R0+1 +#define OFS_ESIDAC1R1 (0x0042) /* ESI DAC1 register 1 */ +#define OFS_ESIDAC1R1_L OFS_ESIDAC1R1 +#define OFS_ESIDAC1R1_H OFS_ESIDAC1R1+1 +#define OFS_ESIDAC1R2 (0x0044) /* ESI DAC1 register 2 */ +#define OFS_ESIDAC1R2_L OFS_ESIDAC1R2 +#define OFS_ESIDAC1R2_H OFS_ESIDAC1R2+1 +#define OFS_ESIDAC1R3 (0x0046) /* ESI DAC1 register 3 */ +#define OFS_ESIDAC1R3_L OFS_ESIDAC1R3 +#define OFS_ESIDAC1R3_H OFS_ESIDAC1R3+1 +#define OFS_ESIDAC1R4 (0x0048) /* ESI DAC1 register 4 */ +#define OFS_ESIDAC1R4_L OFS_ESIDAC1R4 +#define OFS_ESIDAC1R4_H OFS_ESIDAC1R4+1 +#define OFS_ESIDAC1R5 (0x004A) /* ESI DAC1 register 5 */ +#define OFS_ESIDAC1R5_L OFS_ESIDAC1R5 +#define OFS_ESIDAC1R5_H OFS_ESIDAC1R5+1 +#define OFS_ESIDAC1R6 (0x004C) /* ESI DAC1 register 6 */ +#define OFS_ESIDAC1R6_L OFS_ESIDAC1R6 +#define OFS_ESIDAC1R6_H OFS_ESIDAC1R6+1 +#define OFS_ESIDAC1R7 (0x004E) /* ESI DAC1 register 7 */ +#define OFS_ESIDAC1R7_L OFS_ESIDAC1R7 +#define OFS_ESIDAC1R7_H OFS_ESIDAC1R7+1 +#define OFS_ESIDAC2R0 (0x0050) /* ESI DAC2 register 0 */ +#define OFS_ESIDAC2R0_L OFS_ESIDAC2R0 +#define OFS_ESIDAC2R0_H OFS_ESIDAC2R0+1 +#define OFS_ESIDAC2R1 (0x0052) /* ESI DAC2 register 1 */ +#define OFS_ESIDAC2R1_L OFS_ESIDAC2R1 +#define OFS_ESIDAC2R1_H OFS_ESIDAC2R1+1 +#define OFS_ESIDAC2R2 (0x0054) /* ESI DAC2 register 2 */ +#define OFS_ESIDAC2R2_L OFS_ESIDAC2R2 +#define OFS_ESIDAC2R2_H OFS_ESIDAC2R2+1 +#define OFS_ESIDAC2R3 (0x0056) /* ESI DAC2 register 3 */ +#define OFS_ESIDAC2R3_L OFS_ESIDAC2R3 +#define OFS_ESIDAC2R3_H OFS_ESIDAC2R3+1 +#define OFS_ESIDAC2R4 (0x0058) /* ESI DAC2 register 4 */ +#define OFS_ESIDAC2R4_L OFS_ESIDAC2R4 +#define OFS_ESIDAC2R4_H OFS_ESIDAC2R4+1 +#define OFS_ESIDAC2R5 (0x005A) /* ESI DAC2 register 5 */ +#define OFS_ESIDAC2R5_L OFS_ESIDAC2R5 +#define OFS_ESIDAC2R5_H OFS_ESIDAC2R5+1 +#define OFS_ESIDAC2R6 (0x005C) /* ESI DAC2 register 6 */ +#define OFS_ESIDAC2R6_L OFS_ESIDAC2R6 +#define OFS_ESIDAC2R6_H OFS_ESIDAC2R6+1 +#define OFS_ESIDAC2R7 (0x005E) /* ESI DAC2 register 7 */ +#define OFS_ESIDAC2R7_L OFS_ESIDAC2R7 +#define OFS_ESIDAC2R7_H OFS_ESIDAC2R7+1 +#define OFS_ESITSM0 (0x0060) /* ESI TSM 0 */ +#define OFS_ESITSM0_L OFS_ESITSM0 +#define OFS_ESITSM0_H OFS_ESITSM0+1 +#define OFS_ESITSM1 (0x0062) /* ESI TSM 1 */ +#define OFS_ESITSM1_L OFS_ESITSM1 +#define OFS_ESITSM1_H OFS_ESITSM1+1 +#define OFS_ESITSM2 (0x0064) /* ESI TSM 2 */ +#define OFS_ESITSM2_L OFS_ESITSM2 +#define OFS_ESITSM2_H OFS_ESITSM2+1 +#define OFS_ESITSM3 (0x0066) /* ESI TSM 3 */ +#define OFS_ESITSM3_L OFS_ESITSM3 +#define OFS_ESITSM3_H OFS_ESITSM3+1 +#define OFS_ESITSM4 (0x0068) /* ESI TSM 4 */ +#define OFS_ESITSM4_L OFS_ESITSM4 +#define OFS_ESITSM4_H OFS_ESITSM4+1 +#define OFS_ESITSM5 (0x006A) /* ESI TSM 5 */ +#define OFS_ESITSM5_L OFS_ESITSM5 +#define OFS_ESITSM5_H OFS_ESITSM5+1 +#define OFS_ESITSM6 (0x006C) /* ESI TSM 6 */ +#define OFS_ESITSM6_L OFS_ESITSM6 +#define OFS_ESITSM6_H OFS_ESITSM6+1 +#define OFS_ESITSM7 (0x006E) /* ESI TSM 7 */ +#define OFS_ESITSM7_L OFS_ESITSM7 +#define OFS_ESITSM7_H OFS_ESITSM7+1 +#define OFS_ESITSM8 (0x0070) /* ESI TSM 8 */ +#define OFS_ESITSM8_L OFS_ESITSM8 +#define OFS_ESITSM8_H OFS_ESITSM8+1 +#define OFS_ESITSM9 (0x0072) /* ESI TSM 9 */ +#define OFS_ESITSM9_L OFS_ESITSM9 +#define OFS_ESITSM9_H OFS_ESITSM9+1 +#define OFS_ESITSM10 (0x0074) /* ESI TSM 10 */ +#define OFS_ESITSM10_L OFS_ESITSM10 +#define OFS_ESITSM10_H OFS_ESITSM10+1 +#define OFS_ESITSM11 (0x0076) /* ESI TSM 11 */ +#define OFS_ESITSM11_L OFS_ESITSM11 +#define OFS_ESITSM11_H OFS_ESITSM11+1 +#define OFS_ESITSM12 (0x0078) /* ESI TSM 12 */ +#define OFS_ESITSM12_L OFS_ESITSM12 +#define OFS_ESITSM12_H OFS_ESITSM12+1 +#define OFS_ESITSM13 (0x007A) /* ESI TSM 13 */ +#define OFS_ESITSM13_L OFS_ESITSM13 +#define OFS_ESITSM13_H OFS_ESITSM13+1 +#define OFS_ESITSM14 (0x007C) /* ESI TSM 14 */ +#define OFS_ESITSM14_L OFS_ESITSM14 +#define OFS_ESITSM14_H OFS_ESITSM14+1 +#define OFS_ESITSM15 (0x007E) /* ESI TSM 15 */ +#define OFS_ESITSM15_L OFS_ESITSM15 +#define OFS_ESITSM15_H OFS_ESITSM15+1 +#define OFS_ESITSM16 (0x0080) /* ESI TSM 16 */ +#define OFS_ESITSM16_L OFS_ESITSM16 +#define OFS_ESITSM16_H OFS_ESITSM16+1 +#define OFS_ESITSM17 (0x0082) /* ESI TSM 17 */ +#define OFS_ESITSM17_L OFS_ESITSM17 +#define OFS_ESITSM17_H OFS_ESITSM17+1 +#define OFS_ESITSM18 (0x0084) /* ESI TSM 18 */ +#define OFS_ESITSM18_L OFS_ESITSM18 +#define OFS_ESITSM18_H OFS_ESITSM18+1 +#define OFS_ESITSM19 (0x0086) /* ESI TSM 19 */ +#define OFS_ESITSM19_L OFS_ESITSM19 +#define OFS_ESITSM19_H OFS_ESITSM19+1 +#define OFS_ESITSM20 (0x0088) /* ESI TSM 20 */ +#define OFS_ESITSM20_L OFS_ESITSM20 +#define OFS_ESITSM20_H OFS_ESITSM20+1 +#define OFS_ESITSM21 (0x008A) /* ESI TSM 21 */ +#define OFS_ESITSM21_L OFS_ESITSM21 +#define OFS_ESITSM21_H OFS_ESITSM21+1 +#define OFS_ESITSM22 (0x008C) /* ESI TSM 22 */ +#define OFS_ESITSM22_L OFS_ESITSM22 +#define OFS_ESITSM22_H OFS_ESITSM22+1 +#define OFS_ESITSM23 (0x008E) /* ESI TSM 23 */ +#define OFS_ESITSM23_L OFS_ESITSM23 +#define OFS_ESITSM23_H OFS_ESITSM23+1 +#define OFS_ESITSM24 (0x0090) /* ESI TSM 24 */ +#define OFS_ESITSM24_L OFS_ESITSM24 +#define OFS_ESITSM24_H OFS_ESITSM24+1 +#define OFS_ESITSM25 (0x0092) /* ESI TSM 25 */ +#define OFS_ESITSM25_L OFS_ESITSM25 +#define OFS_ESITSM25_H OFS_ESITSM25+1 +#define OFS_ESITSM26 (0x0094) /* ESI TSM 26 */ +#define OFS_ESITSM26_L OFS_ESITSM26 +#define OFS_ESITSM26_H OFS_ESITSM26+1 +#define OFS_ESITSM27 (0x0096) /* ESI TSM 27 */ +#define OFS_ESITSM27_L OFS_ESITSM27 +#define OFS_ESITSM27_H OFS_ESITSM27+1 +#define OFS_ESITSM28 (0x0098) /* ESI TSM 28 */ +#define OFS_ESITSM28_L OFS_ESITSM28 +#define OFS_ESITSM28_H OFS_ESITSM28+1 +#define OFS_ESITSM29 (0x009A) /* ESI TSM 29 */ +#define OFS_ESITSM29_L OFS_ESITSM29 +#define OFS_ESITSM29_H OFS_ESITSM29+1 +#define OFS_ESITSM30 (0x009C) /* ESI TSM 30 */ +#define OFS_ESITSM30_L OFS_ESITSM30 +#define OFS_ESITSM30_H OFS_ESITSM30+1 +#define OFS_ESITSM31 (0x009E) /* ESI TSM 31 */ +#define OFS_ESITSM31_L OFS_ESITSM31 +#define OFS_ESITSM31_H OFS_ESITSM31+1 + +/* ESIIV Control Bits */ + +#define ESIIV_NONE (0x0000) /* No ESI Interrupt Pending */ +#define ESIIV_ESIIFG1 (0x0002) /* rising edge of the ESISTOP(tsm) */ +#define ESIIV_ESIIFG0 (0x0004) /* ESIOUT0 to ESIOUT3 conditions selected by ESIIFGSETx bits */ +#define ESIIV_ESIIFG8 (0x0006) /* ESIOUT4 to ESIOUT7 conditions selected by ESIIFGSET2x bits */ +#define ESIIV_ESIIFG3 (0x0008) /* ESICNT1 counter conditions selected with the ESITHR1 and ESITHR2 registers */ +#define ESIIV_ESIIFG6 (0x000A) /* PSM transitions to a state with a Q7 bit */ +#define ESIIV_ESIIFG5 (0x000C) /* PSM transitions to a state with a Q6 bit */ +#define ESIIV_ESIIFG4 (0x000E) /* ESICNT2 counter conditions selected with the ESIIS2x bits */ +#define ESIIV_ESIIFG7 (0x0010) /* ESICNT0 counter conditions selected with the ESIIS0x bits */ +#define ESIIV_ESIIFG2 (0x0012) /* start of a TSM sequence */ + +/* ESIINT1 Control Bits */ +#define ESIIFGSET22 (0x8000) /* ESIIFG8 interrupt flag source */ +#define ESIIFGSET21 (0x4000) /* ESIIFG8 interrupt flag source */ +#define ESIIFGSET20 (0x2000) /* ESIIFG8 interrupt flag source */ +#define ESIIFGSET12 (0x1000) /* ESIIFG0 interrupt flag source */ +#define ESIIFGSET11 (0x0800) /* ESIIFG0 interrupt flag source */ +#define ESIIFGSET10 (0x0400) /* ESIIFG0 interrupt flag source */ +#define ESIIE8 (0x0100) /* Interrupt enable */ +#define ESIIE7 (0x0080) /* Interrupt enable */ +#define ESIIE6 (0x0040) /* Interrupt enable */ +#define ESIIE5 (0x0020) /* Interrupt enable */ +#define ESIIE4 (0x0010) /* Interrupt enable */ +#define ESIIE3 (0x0008) /* Interrupt enable */ +#define ESIIE2 (0x0004) /* Interrupt enable */ +#define ESIIE1 (0x0002) /* Interrupt enable */ +#define ESIIE0 (0x0001) /* Interrupt enable */ + +/* ESIINT1 Control Bits */ +#define ESIIE7_L (0x0080) /* Interrupt enable */ +#define ESIIE6_L (0x0040) /* Interrupt enable */ +#define ESIIE5_L (0x0020) /* Interrupt enable */ +#define ESIIE4_L (0x0010) /* Interrupt enable */ +#define ESIIE3_L (0x0008) /* Interrupt enable */ +#define ESIIE2_L (0x0004) /* Interrupt enable */ +#define ESIIE1_L (0x0002) /* Interrupt enable */ +#define ESIIE0_L (0x0001) /* Interrupt enable */ + +/* ESIINT1 Control Bits */ +#define ESIIFGSET22_H (0x0080) /* ESIIFG8 interrupt flag source */ +#define ESIIFGSET21_H (0x0040) /* ESIIFG8 interrupt flag source */ +#define ESIIFGSET20_H (0x0020) /* ESIIFG8 interrupt flag source */ +#define ESIIFGSET12_H (0x0010) /* ESIIFG0 interrupt flag source */ +#define ESIIFGSET11_H (0x0008) /* ESIIFG0 interrupt flag source */ +#define ESIIFGSET10_H (0x0004) /* ESIIFG0 interrupt flag source */ +#define ESIIE8_H (0x0001) /* Interrupt enable */ + +#define ESIIFGSET2_0 (0x0000) /* ESIIFG8 is set when ESIOUT4 is set */ +#define ESIIFGSET2_1 (0x2000) /* ESIIFG8 is set when ESIOUT4 is reset */ +#define ESIIFGSET2_2 (0x4000) /* ESIIFG8 is set when ESIOUT5 is set */ +#define ESIIFGSET2_3 (0x6000) /* ESIIFG8 is set when ESIOUT5 is reset */ +#define ESIIFGSET2_4 (0x8000) /* ESIIFG8 is set when ESIOUT6 is set */ +#define ESIIFGSET2_5 (0xA000) /* ESIIFG8 is set when ESIOUT6 is reset */ +#define ESIIFGSET2_6 (0xC000) /* ESIIFG8 is set when ESIOUT7 is set */ +#define ESIIFGSET2_7 (0xE000) /* ESIIFG8 is set when ESIOUT7 is reset */ +#define ESIIFGSET1_0 (0x0000) /* ESIIFG0 is set when ESIOUT0 is set */ +#define ESIIFGSET1_1 (0x0400) /* ESIIFG0 is set when ESIOUT0 is reset */ +#define ESIIFGSET1_2 (0x0800) /* ESIIFG0 is set when ESIOUT1 is set */ +#define ESIIFGSET1_3 (0x0C00) /* ESIIFG0 is set when ESIOUT1 is reset */ +#define ESIIFGSET1_4 (0x1000) /* ESIIFG0 is set when ESIOUT2 is set */ +#define ESIIFGSET1_5 (0x1400) /* ESIIFG0 is set when ESIOUT2 is reset */ +#define ESIIFGSET1_6 (0x1800) /* ESIIFG0 is set when ESIOUT3 is set */ +#define ESIIFGSET1_7 (0x1C00) /* ESIIFG0 is set when ESIOUT3 is reset */ + +/* ESIINT2 Control Bits */ +#define ESIIS21 (0x4000) /* SIFIFG4 interrupt flag source */ +#define ESIIS20 (0x2000) /* SIFIFG4 interrupt flag source */ +#define ESIIS01 (0x0800) /* SIFIFG7 interrupt flag source */ +#define ESIIS00 (0x0400) /* SIFIFG7 interrupt flag source */ +#define ESIIFG8 (0x0100) /* ESIIFG8 interrupt pending */ +#define ESIIFG7 (0x0080) /* ESIIFG7 interrupt pending */ +#define ESIIFG6 (0x0040) /* ESIIFG6 interrupt pending */ +#define ESIIFG5 (0x0020) /* ESIIFG5 interrupt pending */ +#define ESIIFG4 (0x0010) /* ESIIFG4 interrupt pending */ +#define ESIIFG3 (0x0008) /* ESIIFG3 interrupt pending */ +#define ESIIFG2 (0x0004) /* ESIIFG2 interrupt pending */ +#define ESIIFG1 (0x0002) /* ESIIFG1 interrupt pending */ +#define ESIIFG0 (0x0001) /* ESIIFG0 interrupt pending */ + +/* ESIINT2 Control Bits */ +#define ESIIFG7_L (0x0080) /* ESIIFG7 interrupt pending */ +#define ESIIFG6_L (0x0040) /* ESIIFG6 interrupt pending */ +#define ESIIFG5_L (0x0020) /* ESIIFG5 interrupt pending */ +#define ESIIFG4_L (0x0010) /* ESIIFG4 interrupt pending */ +#define ESIIFG3_L (0x0008) /* ESIIFG3 interrupt pending */ +#define ESIIFG2_L (0x0004) /* ESIIFG2 interrupt pending */ +#define ESIIFG1_L (0x0002) /* ESIIFG1 interrupt pending */ +#define ESIIFG0_L (0x0001) /* ESIIFG0 interrupt pending */ + +/* ESIINT2 Control Bits */ +#define ESIIS21_H (0x0040) /* SIFIFG4 interrupt flag source */ +#define ESIIS20_H (0x0020) /* SIFIFG4 interrupt flag source */ +#define ESIIS01_H (0x0008) /* SIFIFG7 interrupt flag source */ +#define ESIIS00_H (0x0004) /* SIFIFG7 interrupt flag source */ +#define ESIIFG8_H (0x0001) /* ESIIFG8 interrupt pending */ + +#define ESIIS2_0 (0x0000) /* SIFIFG4 interrupt flag source: SIFCNT2 */ +#define ESIIS2_1 (0x2000) /* SIFIFG4 interrupt flag source: SIFCNT2 MOD 4 */ +#define ESIIS2_2 (0x4000) /* SIFIFG4 interrupt flag source: SIFCNT2 MOD 256 */ +#define ESIIS2_3 (0x6000) /* SIFIFG4 interrupt flag source: SIFCNT2 decrements from 01h to 00h */ +#define ESIIS0_0 (0x0000) /* SIFIFG7 interrupt flag source: SIFCNT0 */ +#define ESIIS0_1 (0x0400) /* SIFIFG7 interrupt flag source: SIFCNT0 MOD 4 */ +#define ESIIS0_2 (0x0800) /* SIFIFG7 interrupt flag source: SIFCNT0 MOD 256 */ +#define ESIIS0_3 (0x0C00) /* SIFIFG7 interrupt flag source: SIFCNT0 increments from FFFFh to 00h */ + +/* ESIAFE Control Bits */ +#define ESIDAC2EN (0x0800) /* Enable ESIDAC(tsm) control for DAC in AFE2 */ +#define ESICA2EN (0x0400) /* Enable ESICA(tsm) control for comparator in AFE2 */ +#define ESICA2INV (0x0200) /* Invert AFE2's comparator output */ +#define ESICA1INV (0x0100) /* Invert AFE1's comparator output */ +#define ESICA2X (0x0080) /* AFE2's comparator input select */ +#define ESICA1X (0x0040) /* AFE1's comparator input select */ +#define ESICISEL (0x0020) /* Comparator input select for AFE1 only */ +#define ESICACI3 (0x0010) /* Comparator input select for AFE1 only */ +#define ESIVSS (0x0008) /* Sample-and-hold ESIVSS select */ +#define ESIVCC2 (0x0004) /* Mid-voltage generator */ +#define ESISH (0x0002) /* Sample-and-hold enable */ +#define ESITEN (0x0001) /* Excitation enable */ + +/* ESIAFE Control Bits */ +#define ESICA2X_L (0x0080) /* AFE2's comparator input select */ +#define ESICA1X_L (0x0040) /* AFE1's comparator input select */ +#define ESICISEL_L (0x0020) /* Comparator input select for AFE1 only */ +#define ESICACI3_L (0x0010) /* Comparator input select for AFE1 only */ +#define ESIVSS_L (0x0008) /* Sample-and-hold ESIVSS select */ +#define ESIVCC2_L (0x0004) /* Mid-voltage generator */ +#define ESISH_L (0x0002) /* Sample-and-hold enable */ +#define ESITEN_L (0x0001) /* Excitation enable */ + +/* ESIAFE Control Bits */ +#define ESIDAC2EN_H (0x0008) /* Enable ESIDAC(tsm) control for DAC in AFE2 */ +#define ESICA2EN_H (0x0004) /* Enable ESICA(tsm) control for comparator in AFE2 */ +#define ESICA2INV_H (0x0002) /* Invert AFE2's comparator output */ +#define ESICA1INV_H (0x0001) /* Invert AFE1's comparator output */ + +/* ESIPPU Control Bits */ +#define ESITCHOUT1 (0x0200) /* Latched AFE1 comparator output for test channel 1 */ +#define ESITCHOUT0 (0x0100) /* Lachted AFE1 comparator output for test channel 0 */ +#define ESIOUT7 (0x0080) /* Latched AFE2 comparator output when ESICH3 input is selected */ +#define ESIOUT6 (0x0040) /* Latched AFE2 comparator output when ESICH2 input is selected */ +#define ESIOUT5 (0x0020) /* Latched AFE2 comparator output when ESICH1 input is selected */ +#define ESIOUT4 (0x0010) /* Latched AFE2 comparator output when ESICH0 input is selected */ +#define ESIOUT3 (0x0008) /* Latched AFE1 comparator output when ESICH3 input is selected */ +#define ESIOUT2 (0x0004) /* Latched AFE1 comparator output when ESICH2 input is selected */ +#define ESIOUT1 (0x0002) /* Latched AFE1 comparator output when ESICH1 input is selected */ +#define ESIOUT0 (0x0001) /* Latched AFE1 comparator output when ESICH0 input is selected */ + +/* ESIPPU Control Bits */ +#define ESIOUT7_L (0x0080) /* Latched AFE2 comparator output when ESICH3 input is selected */ +#define ESIOUT6_L (0x0040) /* Latched AFE2 comparator output when ESICH2 input is selected */ +#define ESIOUT5_L (0x0020) /* Latched AFE2 comparator output when ESICH1 input is selected */ +#define ESIOUT4_L (0x0010) /* Latched AFE2 comparator output when ESICH0 input is selected */ +#define ESIOUT3_L (0x0008) /* Latched AFE1 comparator output when ESICH3 input is selected */ +#define ESIOUT2_L (0x0004) /* Latched AFE1 comparator output when ESICH2 input is selected */ +#define ESIOUT1_L (0x0002) /* Latched AFE1 comparator output when ESICH1 input is selected */ +#define ESIOUT0_L (0x0001) /* Latched AFE1 comparator output when ESICH0 input is selected */ + +/* ESIPPU Control Bits */ +#define ESITCHOUT1_H (0x0002) /* Latched AFE1 comparator output for test channel 1 */ +#define ESITCHOUT0_H (0x0001) /* Lachted AFE1 comparator output for test channel 0 */ + +/* ESITSM Control Bits */ +#define ESICLKAZSEL (0x4000) /* Functionality selection of ESITSMx bit5 */ +#define ESITSMTRG1 (0x2000) /* TSM start trigger selection */ +#define ESITSMTRG0 (0x1000) /* TSM start trigger selection */ +#define ESISTART (0x0800) /* TSM software start trigger */ +#define ESITSMRP (0x0400) /* TSM repeat modee */ +#define ESIDIV3B2 (0x0200) /* TSM start trigger ACLK divider */ +#define ESIDIV3B1 (0x0100) /* TSM start trigger ACLK divider */ +#define ESIDIV3B0 (0x0080) /* TSM start trigger ACLK divider */ +#define ESIDIV3A2 (0x0040) /* TSM start trigger ACLK divider */ +#define ESIDIV3A1 (0x0020) /* TSM start trigger ACLK divider */ +#define ESIDIV3A0 (0x0010) /* TSM start trigger ACLK divider */ +#define ESIDIV21 (0x0008) /* ACLK divider */ +#define ESIDIV20 (0x0004) /* ACLK divider */ +#define ESIDIV11 (0x0002) /* TSM SMCLK divider */ +#define ESIDIV10 (0x0001) /* TSM SMCLK divider */ + +/* ESITSM Control Bits */ +#define ESIDIV3B0_L (0x0080) /* TSM start trigger ACLK divider */ +#define ESIDIV3A2_L (0x0040) /* TSM start trigger ACLK divider */ +#define ESIDIV3A1_L (0x0020) /* TSM start trigger ACLK divider */ +#define ESIDIV3A0_L (0x0010) /* TSM start trigger ACLK divider */ +#define ESIDIV21_L (0x0008) /* ACLK divider */ +#define ESIDIV20_L (0x0004) /* ACLK divider */ +#define ESIDIV11_L (0x0002) /* TSM SMCLK divider */ +#define ESIDIV10_L (0x0001) /* TSM SMCLK divider */ + +/* ESITSM Control Bits */ +#define ESICLKAZSEL_H (0x0040) /* Functionality selection of ESITSMx bit5 */ +#define ESITSMTRG1_H (0x0020) /* TSM start trigger selection */ +#define ESITSMTRG0_H (0x0010) /* TSM start trigger selection */ +#define ESISTART_H (0x0008) /* TSM software start trigger */ +#define ESITSMRP_H (0x0004) /* TSM repeat modee */ +#define ESIDIV3B2_H (0x0002) /* TSM start trigger ACLK divider */ +#define ESIDIV3B1_H (0x0001) /* TSM start trigger ACLK divider */ + +#define ESITSMTRG_0 (0x0000) /* Halt mode */ +#define ESITSMTRG_1 (0x1000) /* TSM start trigger ACLK divider */ +#define ESITSMTRG_2 (0x2000) /* Software trigger for TSM */ +#define ESITSMTRG_3 (0x3000) /* Either the ACLK divider or the ESISTART biT */ +#define ESIDIV3B_0 (0x0000) /* TSM start trigger ACLK divider */ +#define ESIDIV3B_1 (0x0080) /* TSM start trigger ACLK divider */ +#define ESIDIV3B_2 (0x0100) /* TSM start trigger ACLK divider */ +#define ESIDIV3B_3 (0x0180) /* TSM start trigger ACLK divider */ +#define ESIDIV3B_4 (0x0200) /* TSM start trigger ACLK divider */ +#define ESIDIV3B_5 (0x0280) /* TSM start trigger ACLK divider */ +#define ESIDIV3B_6 (0x0300) /* TSM start trigger ACLK divider */ +#define ESIDIV3B_7 (0x0380) /* TSM start trigger ACLK divider */ +#define ESIDIV3A_0 (0x0000) /* TSM start trigger ACLK divider */ +#define ESIDIV3A_1 (0x0010) /* TSM start trigger ACLK divider */ +#define ESIDIV3A_2 (0x0020) /* TSM start trigger ACLK divider */ +#define ESIDIV3A_3 (0x0030) /* TSM start trigger ACLK divider */ +#define ESIDIV3A_4 (0x0040) /* TSM start trigger ACLK divider */ +#define ESIDIV3A_5 (0x0050) /* TSM start trigger ACLK divider */ +#define ESIDIV3A_6 (0x0060) /* TSM start trigger ACLK divider */ +#define ESIDIV3A_7 (0x0070) /* TSM start trigger ACLK divider */ +#define ESIDIV2_0 (0x0000) /* ACLK divider mode: 0 */ +#define ESIDIV2_1 (0x0004) /* ACLK divider mode: 1 */ +#define ESIDIV2_2 (0x0008) /* ACLK divider mode: 2 */ +#define ESIDIV2_3 (0x000C) /* ACLK divider mode: 3 */ +#define ESIDIV2__1 (0x0000) /* ACLK divider = /1 */ +#define ESIDIV2__2 (0x0004) /* ACLK divider = /2 */ +#define ESIDIV2__4 (0x0008) /* ACLK divider = /4 */ +#define ESIDIV2__8 (0x000C) /* ACLK divider = /8 */ +#define ESIDIV1_0 (0x0000) /* TSM SMCLK/ESIOSC divider mode: 0 */ +#define ESIDIV1_1 (0x0001) /* TSM SMCLK/ESIOSC divider mode: 1 */ +#define ESIDIV1_2 (0x0002) /* TSM SMCLK/ESIOSC divider mode: 2 */ +#define ESIDIV1_3 (0x0003) /* TSM SMCLK/ESIOSC divider mode: 3 */ +#define ESIDIV1__1 (0x0000) /* TSM SMCLK/ESIOSC divider = /1 */ +#define ESIDIV1__2 (0x0001) /* TSM SMCLK/ESIOSC divider = /2 */ +#define ESIDIV1__4 (0x0002) /* TSM SMCLK/ESIOSC divider = /4 */ +#define ESIDIV1__8 (0x0003) /* TSM SMCLK/ESIOSC divider = /8 */ + +/* ESIPSM Control Bits */ +#define ESICNT2RST (0x8000) /* ESI Counter 2 reset */ +#define ESICNT1RST (0x4000) /* ESI Counter 1 reset */ +#define ESICNT0RST (0x2000) /* ESI Counter 0 reset */ +#define ESITEST4SEL1 (0x0200) /* Output signal selection for SIFTEST4 pin */ +#define ESITEST4SEL0 (0x0100) /* Output signal selection for SIFTEST4 pin */ +#define ESIV2SEL (0x0080) /* Source Selection for V2 bit*/ +#define ESICNT2EN (0x0020) /* ESICNT2 enable (down counter) */ +#define ESICNT1EN (0x0010) /* ESICNT1 enable (up/down counter) */ +#define ESICNT0EN (0x0008) /* ESICNT0 enable (up counter) */ +#define ESIQ7TRG (0x0004) /* Enabling to use Q7 as trigger for a TSM sequence */ +#define ESIQ6EN (0x0001) /* Q6 enable */ + +/* ESIPSM Control Bits */ +#define ESIV2SEL_L (0x0080) /* Source Selection for V2 bit*/ +#define ESICNT2EN_L (0x0020) /* ESICNT2 enable (down counter) */ +#define ESICNT1EN_L (0x0010) /* ESICNT1 enable (up/down counter) */ +#define ESICNT0EN_L (0x0008) /* ESICNT0 enable (up counter) */ +#define ESIQ7TRG_L (0x0004) /* Enabling to use Q7 as trigger for a TSM sequence */ +#define ESIQ6EN_L (0x0001) /* Q6 enable */ + +/* ESIPSM Control Bits */ +#define ESICNT2RST_H (0x0080) /* ESI Counter 2 reset */ +#define ESICNT1RST_H (0x0040) /* ESI Counter 1 reset */ +#define ESICNT0RST_H (0x0020) /* ESI Counter 0 reset */ +#define ESITEST4SEL1_H (0x0002) /* Output signal selection for SIFTEST4 pin */ +#define ESITEST4SEL0_H (0x0001) /* Output signal selection for SIFTEST4 pin */ + +#define ESITEST4SEL_0 (0x0000) /* Q1 signal from PSM table */ +#define ESITEST4SEL_1 (0x0100) /* Q2 signal from PSM table */ +#define ESITEST4SEL_2 (0x0200) /* TSM clock signal from Timing State Machine */ +#define ESITEST4SEL_3 (0x0300) /* AFE1's comparator output signal Comp1Out */ + +/* ESIOSC Control Bits */ +#define ESICLKFQ5 (0x2000) /* Internal oscillator frequency adjust */ +#define ESICLKFQ4 (0x1000) /* Internal oscillator frequency adjust */ +#define ESICLKFQ3 (0x0800) /* Internal oscillator frequency adjust */ +#define ESICLKFQ2 (0x0400) /* Internal oscillator frequency adjust */ +#define ESICLKFQ1 (0x0200) /* Internal oscillator frequency adjust */ +#define ESICLKFQ0 (0x0100) /* Internal oscillator frequency adjust */ +#define ESICLKGON (0x0002) /* Internal oscillator control */ +#define ESIHFSEL (0x0001) /* Internal oscillator enable */ + +/* ESIOSC Control Bits */ +#define ESICLKGON_L (0x0002) /* Internal oscillator control */ +#define ESIHFSEL_L (0x0001) /* Internal oscillator enable */ + +/* ESIOSC Control Bits */ +#define ESICLKFQ5_H (0x0020) /* Internal oscillator frequency adjust */ +#define ESICLKFQ4_H (0x0010) /* Internal oscillator frequency adjust */ +#define ESICLKFQ3_H (0x0008) /* Internal oscillator frequency adjust */ +#define ESICLKFQ2_H (0x0004) /* Internal oscillator frequency adjust */ +#define ESICLKFQ1_H (0x0002) /* Internal oscillator frequency adjust */ +#define ESICLKFQ0_H (0x0001) /* Internal oscillator frequency adjust */ + +/* ESICTL Control Bits */ +#define ESIS3SEL2 (0x8000) /* PPUS3 source select */ +#define ESIS3SEL1 (0x4000) /* PPUS3 source select */ +#define ESIS3SEL0 (0x2000) /* PPUS3 source select */ +#define ESIS2SEL2 (0x1000) /* PPUS2 source select */ +#define ESIS2SEL1 (0x0800) /* PPUS2 source select */ +#define ESIS2SEL0 (0x0400) /* PPUS2 source select */ +#define ESIS1SEL2 (0x0200) /* PPUS1 source select */ +#define ESIS1SEL1 (0x0100) /* PPUS1 source select */ +#define ESIS1SEL0 (0x0080) /* PPUS1 source select */ +#define ESITCH11 (0x0040) /* select the comparator input for test channel 1 */ +#define ESITCH10 (0x0020) /* select the comparator input for test channel 1 */ +#define ESITCH01 (0x0010) /* select the comparator input for test channel 0 */ +#define ESITCH00 (0x0008) /* select the comparator input for test channel 0 */ +#define ESICS (0x0004) /* Comparator output/Timer_A input selection */ +#define ESITESTD (0x0002) /* Test cycle insertion */ +#define ESIEN (0x0001) /* Extended Scan interface enable */ + +/* ESICTL Control Bits */ +#define ESIS1SEL0_L (0x0080) /* PPUS1 source select */ +#define ESITCH11_L (0x0040) /* select the comparator input for test channel 1 */ +#define ESITCH10_L (0x0020) /* select the comparator input for test channel 1 */ +#define ESITCH01_L (0x0010) /* select the comparator input for test channel 0 */ +#define ESITCH00_L (0x0008) /* select the comparator input for test channel 0 */ +#define ESICS_L (0x0004) /* Comparator output/Timer_A input selection */ +#define ESITESTD_L (0x0002) /* Test cycle insertion */ +#define ESIEN_L (0x0001) /* Extended Scan interface enable */ + +/* ESICTL Control Bits */ +#define ESIS3SEL2_H (0x0080) /* PPUS3 source select */ +#define ESIS3SEL1_H (0x0040) /* PPUS3 source select */ +#define ESIS3SEL0_H (0x0020) /* PPUS3 source select */ +#define ESIS2SEL2_H (0x0010) /* PPUS2 source select */ +#define ESIS2SEL1_H (0x0008) /* PPUS2 source select */ +#define ESIS2SEL0_H (0x0004) /* PPUS2 source select */ +#define ESIS1SEL2_H (0x0002) /* PPUS1 source select */ +#define ESIS1SEL1_H (0x0001) /* PPUS1 source select */ + +#define ESIS3SEL_0 (0x0000) /* ESIOUT0 is the PPUS3 source */ +#define ESIS3SEL_1 (0x2000) /* ESIOUT1 is the PPUS3 source */ +#define ESIS3SEL_2 (0x4000) /* ESIOUT2 is the PPUS3 source */ +#define ESIS3SEL_3 (0x6000) /* ESIOUT3 is the PPUS3 source */ +#define ESIS3SEL_4 (0x8000) /* ESIOUT4 is the PPUS3 source */ +#define ESIS3SEL_5 (0xA000) /* ESIOUT5 is the PPUS3 source */ +#define ESIS3SEL_6 (0xC000) /* ESIOUT6 is the PPUS3 source */ +#define ESIS3SEL_7 (0xE000) /* ESIOUT7 is the PPUS3 source */ +#define ESIS2SEL_0 (0x0000) /* ESIOUT0 is the PPUS2 source */ +#define ESIS2SEL_1 (0x0400) /* ESIOUT1 is the PPUS2 source */ +#define ESIS2SEL_2 (0x0800) /* ESIOUT2 is the PPUS2 source */ +#define ESIS2SEL_3 (0x0C00) /* ESIOUT3 is the PPUS2 source */ +#define ESIS2SEL_4 (0x1000) /* ESIOUT4 is the PPUS2 source */ +#define ESIS2SEL_5 (0x1400) /* ESIOUT5 is the PPUS2 source */ +#define ESIS2SEL_6 (0x1800) /* ESIOUT6 is the PPUS2 source */ +#define ESIS2SEL_7 (0x1C00) /* ESIOUT7 is the PPUS2 source */ +#define ESIS1SEL_0 (0x0000) /* ESIOUT0 is the PPUS1 source */ +#define ESIS1SEL_1 (0x0080) /* ESIOUT1 is the PPUS1 source */ +#define ESIS1SEL_2 (0x0100) /* ESIOUT2 is the PPUS1 source */ +#define ESIS1SEL_3 (0x0180) /* ESIOUT3 is the PPUS1 source */ +#define ESIS1SEL_4 (0x0200) /* ESIOUT4 is the PPUS1 source */ +#define ESIS1SEL_5 (0x0280) /* ESIOUT5 is the PPUS1 source */ +#define ESIS1SEL_6 (0x0300) /* ESIOUT6 is the PPUS1 source */ +#define ESIS1SEL_7 (0x0380) /* ESIOUT7 is the PPUS1 source */ +#define ESITCH1_0 (0x0000) /* Comparator input is ESICH0 when ESICAX = 0; Comparator input is ESICI0 when ESICAX = 1 */ +#define ESITCH1_1 (0x0400) /* Comparator input is ESICH1 when ESICAX = 0; Comparator input is ESICI1 when ESICAX = 1 */ +#define ESITCH1_2 (0x0800) /* Comparator input is ESICH2 when ESICAX = 0; Comparator input is ESICI2 when ESICAX = 1 */ +#define ESITCH1_3 (0x0C00) /* Comparator input is ESICH3 when ESICAX = 0; Comparator input is ESICI3 when ESICAX = 1 */ +#define ESITCH0_0 (0x0000) /* Comparator input is ESICH0 when ESICAX = 0; Comparator input is ESICI0 when ESICAX = 1 */ +#define ESITCH0_1 (0x0008) /* Comparator input is ESICH1 when ESICAX = 0; Comparator input is ESICI1 when ESICAX = 1 */ +#define ESITCH0_2 (0x0010) /* Comparator input is ESICH2 when ESICAX = 0; Comparator input is ESICI2 when ESICAX = 1 */ +#define ESITCH0_3 (0x0018) /* Comparator input is ESICH3 when ESICAX = 0; Comparator input is ESICI3 when ESICAX = 1 */ + +/* Timing State Machine Control Bits */ +#define ESIREPEAT4 (0x8000) /* These bits together with the ESICLK bit configure the duration of this state */ +#define ESIREPEAT3 (0x4000) /* ESIREPEATx selects the number of clock cycles for this state. The number of clock cycles = ESIREPEATx + 1 */ +#define ESIREPEAT2 (0x2000) /* */ +#define ESIREPEAT1 (0x1000) /* */ +#define ESIREPEAT0 (0x0800) /* */ +#define ESICLK (0x0400) /* This bit selects the clock source for the TSM */ +#define ESISTOP (0x0200) /* This bit indicates the end of the TSM sequence */ +#define ESIDAC (0x0100) /* TSM DAC on */ +#define ESITESTS1 (0x0080) /* TSM test cycle control */ +#define ESIRSON (0x0040) /* Internal output latches enabled */ +#define ESICLKON (0x0020) /* High-frequency clock on */ +#define ESICA (0x0010) /* TSM comparator on */ +#define ESIEX (0x0008) /* Excitation and sample-and-hold */ +#define ESILCEN (0x0004) /* LC enable */ +#define ESICH1 (0x0002) /* Input channel select */ +#define ESICH0 (0x0001) /* Input channel select */ + +/* Timing State Machine Control Bits */ +#define ESITESTS1_L (0x0080) /* TSM test cycle control */ +#define ESIRSON_L (0x0040) /* Internal output latches enabled */ +#define ESICLKON_L (0x0020) /* High-frequency clock on */ +#define ESICA_L (0x0010) /* TSM comparator on */ +#define ESIEX_L (0x0008) /* Excitation and sample-and-hold */ +#define ESILCEN_L (0x0004) /* LC enable */ +#define ESICH1_L (0x0002) /* Input channel select */ +#define ESICH0_L (0x0001) /* Input channel select */ + +/* Timing State Machine Control Bits */ +#define ESIREPEAT4_H (0x0080) /* These bits together with the ESICLK bit configure the duration of this state */ +#define ESIREPEAT3_H (0x0040) /* ESIREPEATx selects the number of clock cycles for this state. The number of clock cycles = ESIREPEATx + 1 */ +#define ESIREPEAT2_H (0x0020) /* */ +#define ESIREPEAT1_H (0x0010) /* */ +#define ESIREPEAT0_H (0x0008) /* */ +#define ESICLK_H (0x0004) /* This bit selects the clock source for the TSM */ +#define ESISTOP_H (0x0002) /* This bit indicates the end of the TSM sequence */ +#define ESIDAC_H (0x0001) /* TSM DAC on */ + +#define ESICAAZ (0x0020) /* Comparator Offset calibration annulation */ + +#define ESIREPEAT_0 (0x0000) /* These bits configure the duration of this state */ +#define ESIREPEAT_1 (0x0800) /* ESIREPEATx selects the number of clock cycles for this state. The number of clock cycles = ESIREPEATx + 1 */ +#define ESIREPEAT_2 (0x1000) +#define ESIREPEAT_3 (0x1800) +#define ESIREPEAT_4 (0x2000) +#define ESIREPEAT_5 (0x2800) +#define ESIREPEAT_6 (0x3000) +#define ESIREPEAT_7 (0x3800) +#define ESIREPEAT_8 (0x4000) +#define ESIREPEAT_9 (0x4800) +#define ESIREPEAT_10 (0x5000) +#define ESIREPEAT_11 (0x5800) +#define ESIREPEAT_12 (0x6000) +#define ESIREPEAT_13 (0x6800) +#define ESIREPEAT_14 (0x7000) +#define ESIREPEAT_15 (0x7800) +#define ESIREPEAT_16 (0x8000) +#define ESIREPEAT_17 (0x8800) +#define ESIREPEAT_18 (0x9000) +#define ESIREPEAT_19 (0x9800) +#define ESIREPEAT_20 (0xA000) +#define ESIREPEAT_21 (0xA800) +#define ESIREPEAT_22 (0xB000) +#define ESIREPEAT_23 (0xB800) +#define ESIREPEAT_24 (0xC000) +#define ESIREPEAT_25 (0xC800) +#define ESIREPEAT_26 (0xD000) +#define ESIREPEAT_27 (0xD800) +#define ESIREPEAT_28 (0xE000) +#define ESIREPEAT_29 (0xE800) +#define ESIREPEAT_30 (0xF000) +#define ESIREPEAT_31 (0xF800) +#define ESICH_0 (0x0000) /* Input channel select: ESICH0 */ +#define ESICH_1 (0x0001) /* Input channel select: ESICH1 */ +#define ESICH_2 (0x0002) /* Input channel select: ESICH2 */ +#define ESICH_3 (0x0003) /* Input channel select: ESICH3 */ +#endif +/************************************************************ +* EXTENDED SCAN INTERFACE RAM +************************************************************/ +#ifdef __MSP430_HAS_ESI_RAM__ /* Definition to show that Module is available */ + +#define OFS_ESIRAM0 (0x0000) /* ESI RAM 0 */ +#define OFS_ESIRAM1 (0x0001) /* ESI RAM 1 */ +#define OFS_ESIRAM2 (0x0002) /* ESI RAM 2 */ +#define OFS_ESIRAM3 (0x0003) /* ESI RAM 3 */ +#define OFS_ESIRAM4 (0x0004) /* ESI RAM 4 */ +#define OFS_ESIRAM5 (0x0005) /* ESI RAM 5 */ +#define OFS_ESIRAM6 (0x0006) /* ESI RAM 6 */ +#define OFS_ESIRAM7 (0x0007) /* ESI RAM 7 */ +#define OFS_ESIRAM8 (0x0008) /* ESI RAM 8 */ +#define OFS_ESIRAM9 (0x0009) /* ESI RAM 9 */ +#define OFS_ESIRAM10 (0x000A) /* ESI RAM 10 */ +#define OFS_ESIRAM11 (0x000B) /* ESI RAM 11 */ +#define OFS_ESIRAM12 (0x000C) /* ESI RAM 12 */ +#define OFS_ESIRAM13 (0x000D) /* ESI RAM 13 */ +#define OFS_ESIRAM14 (0x000E) /* ESI RAM 14 */ +#define OFS_ESIRAM15 (0x000F) /* ESI RAM 15 */ +#define OFS_ESIRAM16 (0x0010) /* ESI RAM 16 */ +#define OFS_ESIRAM17 (0x0011) /* ESI RAM 17 */ +#define OFS_ESIRAM18 (0x0012) /* ESI RAM 18 */ +#define OFS_ESIRAM19 (0x0013) /* ESI RAM 19 */ +#define OFS_ESIRAM20 (0x0014) /* ESI RAM 20 */ +#define OFS_ESIRAM21 (0x0015) /* ESI RAM 21 */ +#define OFS_ESIRAM22 (0x0016) /* ESI RAM 22 */ +#define OFS_ESIRAM23 (0x0017) /* ESI RAM 23 */ +#define OFS_ESIRAM24 (0x0018) /* ESI RAM 24 */ +#define OFS_ESIRAM25 (0x0019) /* ESI RAM 25 */ +#define OFS_ESIRAM26 (0x001A) /* ESI RAM 26 */ +#define OFS_ESIRAM27 (0x001B) /* ESI RAM 27 */ +#define OFS_ESIRAM28 (0x001C) /* ESI RAM 28 */ +#define OFS_ESIRAM29 (0x001D) /* ESI RAM 29 */ +#define OFS_ESIRAM30 (0x001E) /* ESI RAM 30 */ +#define OFS_ESIRAM31 (0x001F) /* ESI RAM 31 */ +#define OFS_ESIRAM32 (0x0020) /* ESI RAM 32 */ +#define OFS_ESIRAM33 (0x0021) /* ESI RAM 33 */ +#define OFS_ESIRAM34 (0x0022) /* ESI RAM 34 */ +#define OFS_ESIRAM35 (0x0023) /* ESI RAM 35 */ +#define OFS_ESIRAM36 (0x0024) /* ESI RAM 36 */ +#define OFS_ESIRAM37 (0x0025) /* ESI RAM 37 */ +#define OFS_ESIRAM38 (0x0026) /* ESI RAM 38 */ +#define OFS_ESIRAM39 (0x0027) /* ESI RAM 39 */ +#define OFS_ESIRAM40 (0x0028) /* ESI RAM 40 */ +#define OFS_ESIRAM41 (0x0029) /* ESI RAM 41 */ +#define OFS_ESIRAM42 (0x002A) /* ESI RAM 42 */ +#define OFS_ESIRAM43 (0x002B) /* ESI RAM 43 */ +#define OFS_ESIRAM44 (0x002C) /* ESI RAM 44 */ +#define OFS_ESIRAM45 (0x002D) /* ESI RAM 45 */ +#define OFS_ESIRAM46 (0x002E) /* ESI RAM 46 */ +#define OFS_ESIRAM47 (0x002F) /* ESI RAM 47 */ +#define OFS_ESIRAM48 (0x0030) /* ESI RAM 48 */ +#define OFS_ESIRAM49 (0x0031) /* ESI RAM 49 */ +#define OFS_ESIRAM50 (0x0032) /* ESI RAM 50 */ +#define OFS_ESIRAM51 (0x0033) /* ESI RAM 51 */ +#define OFS_ESIRAM52 (0x0034) /* ESI RAM 52 */ +#define OFS_ESIRAM53 (0x0035) /* ESI RAM 53 */ +#define OFS_ESIRAM54 (0x0036) /* ESI RAM 54 */ +#define OFS_ESIRAM55 (0x0037) /* ESI RAM 55 */ +#define OFS_ESIRAM56 (0x0038) /* ESI RAM 56 */ +#define OFS_ESIRAM57 (0x0039) /* ESI RAM 57 */ +#define OFS_ESIRAM58 (0x003A) /* ESI RAM 58 */ +#define OFS_ESIRAM59 (0x003B) /* ESI RAM 59 */ +#define OFS_ESIRAM60 (0x003C) /* ESI RAM 60 */ +#define OFS_ESIRAM61 (0x003D) /* ESI RAM 61 */ +#define OFS_ESIRAM62 (0x003E) /* ESI RAM 62 */ +#define OFS_ESIRAM63 (0x003F) /* ESI RAM 63 */ +#define OFS_ESIRAM64 (0x0040) /* ESI RAM 64 */ +#define OFS_ESIRAM65 (0x0041) /* ESI RAM 65 */ +#define OFS_ESIRAM66 (0x0042) /* ESI RAM 66 */ +#define OFS_ESIRAM67 (0x0043) /* ESI RAM 67 */ +#define OFS_ESIRAM68 (0x0044) /* ESI RAM 68 */ +#define OFS_ESIRAM69 (0x0045) /* ESI RAM 69 */ +#define OFS_ESIRAM70 (0x0046) /* ESI RAM 70 */ +#define OFS_ESIRAM71 (0x0047) /* ESI RAM 71 */ +#define OFS_ESIRAM72 (0x0048) /* ESI RAM 72 */ +#define OFS_ESIRAM73 (0x0049) /* ESI RAM 73 */ +#define OFS_ESIRAM74 (0x004A) /* ESI RAM 74 */ +#define OFS_ESIRAM75 (0x004B) /* ESI RAM 75 */ +#define OFS_ESIRAM76 (0x004C) /* ESI RAM 76 */ +#define OFS_ESIRAM77 (0x004D) /* ESI RAM 77 */ +#define OFS_ESIRAM78 (0x004E) /* ESI RAM 78 */ +#define OFS_ESIRAM79 (0x004F) /* ESI RAM 79 */ +#define OFS_ESIRAM80 (0x0050) /* ESI RAM 80 */ +#define OFS_ESIRAM81 (0x0051) /* ESI RAM 81 */ +#define OFS_ESIRAM82 (0x0052) /* ESI RAM 82 */ +#define OFS_ESIRAM83 (0x0053) /* ESI RAM 83 */ +#define OFS_ESIRAM84 (0x0054) /* ESI RAM 84 */ +#define OFS_ESIRAM85 (0x0055) /* ESI RAM 85 */ +#define OFS_ESIRAM86 (0x0056) /* ESI RAM 86 */ +#define OFS_ESIRAM87 (0x0057) /* ESI RAM 87 */ +#define OFS_ESIRAM88 (0x0058) /* ESI RAM 88 */ +#define OFS_ESIRAM89 (0x0059) /* ESI RAM 89 */ +#define OFS_ESIRAM90 (0x005A) /* ESI RAM 90 */ +#define OFS_ESIRAM91 (0x005B) /* ESI RAM 91 */ +#define OFS_ESIRAM92 (0x005C) /* ESI RAM 92 */ +#define OFS_ESIRAM93 (0x005D) /* ESI RAM 93 */ +#define OFS_ESIRAM94 (0x005E) /* ESI RAM 94 */ +#define OFS_ESIRAM95 (0x005F) /* ESI RAM 95 */ +#define OFS_ESIRAM96 (0x0060) /* ESI RAM 96 */ +#define OFS_ESIRAM97 (0x0061) /* ESI RAM 97 */ +#define OFS_ESIRAM98 (0x0062) /* ESI RAM 98 */ +#define OFS_ESIRAM99 (0x0063) /* ESI RAM 99 */ +#define OFS_ESIRAM100 (0x0064) /* ESI RAM 100 */ +#define OFS_ESIRAM101 (0x0065) /* ESI RAM 101 */ +#define OFS_ESIRAM102 (0x0066) /* ESI RAM 102 */ +#define OFS_ESIRAM103 (0x0067) /* ESI RAM 103 */ +#define OFS_ESIRAM104 (0x0068) /* ESI RAM 104 */ +#define OFS_ESIRAM105 (0x0069) /* ESI RAM 105 */ +#define OFS_ESIRAM106 (0x006A) /* ESI RAM 106 */ +#define OFS_ESIRAM107 (0x006B) /* ESI RAM 107 */ +#define OFS_ESIRAM108 (0x006C) /* ESI RAM 108 */ +#define OFS_ESIRAM109 (0x006D) /* ESI RAM 109 */ +#define OFS_ESIRAM110 (0x006E) /* ESI RAM 110 */ +#define OFS_ESIRAM111 (0x006F) /* ESI RAM 111 */ +#define OFS_ESIRAM112 (0x0070) /* ESI RAM 112 */ +#define OFS_ESIRAM113 (0x0071) /* ESI RAM 113 */ +#define OFS_ESIRAM114 (0x0072) /* ESI RAM 114 */ +#define OFS_ESIRAM115 (0x0073) /* ESI RAM 115 */ +#define OFS_ESIRAM116 (0x0074) /* ESI RAM 116 */ +#define OFS_ESIRAM117 (0x0075) /* ESI RAM 117 */ +#define OFS_ESIRAM118 (0x0076) /* ESI RAM 118 */ +#define OFS_ESIRAM119 (0x0077) /* ESI RAM 119 */ +#define OFS_ESIRAM120 (0x0078) /* ESI RAM 120 */ +#define OFS_ESIRAM121 (0x0079) /* ESI RAM 121 */ +#define OFS_ESIRAM122 (0x007A) /* ESI RAM 122 */ +#define OFS_ESIRAM123 (0x007B) /* ESI RAM 123 */ +#define OFS_ESIRAM124 (0x007C) /* ESI RAM 124 */ +#define OFS_ESIRAM125 (0x007D) /* ESI RAM 125 */ +#define OFS_ESIRAM126 (0x007E) /* ESI RAM 126 */ +#define OFS_ESIRAM127 (0x007F) /* ESI RAM 127 */ +#endif +/************************************************************* +* FRAM Memory +*************************************************************/ +#ifdef __MSP430_HAS_FRAM__ /* Definition to show that Module is available */ + +#define OFS_FRCTL0 (0x0000) /* FRAM Controller Control 0 */ +#define OFS_FRCTL0_L OFS_FRCTL0 +#define OFS_FRCTL0_H OFS_FRCTL0+1 +#define OFS_GCCTL0 (0x0004) /* General Control 0 */ +#define OFS_GCCTL0_L OFS_GCCTL0 +#define OFS_GCCTL0_H OFS_GCCTL0+1 +#define OFS_GCCTL1 (0x0006) /* General Control 1 */ +#define OFS_GCCTL1_L OFS_GCCTL1 +#define OFS_GCCTL1_H OFS_GCCTL1+1 + +#define FRCTLPW (0xA500) /* FRAM password for write */ +#define FRPW (0x9600) /* FRAM password returned by read */ +#define FWPW (0xA500) /* FRAM password for write */ +#define FXPW (0x3300) /* for use with XOR instruction */ + +/* FRCTL0 Control Bits */ +//#define RESERVED (0x0001) /* RESERVED */ +//#define RESERVED (0x0002) /* RESERVED */ +//#define RESERVED (0x0004) /* RESERVED */ +#define NWAITS0 (0x0010) /* FRAM Wait state control Bit: 0 */ +#define NWAITS1 (0x0020) /* FRAM Wait state control Bit: 1 */ +#define NWAITS2 (0x0040) /* FRAM Wait state control Bit: 2 */ +//#define RESERVED (0x0080) /* RESERVED */ + +/* FRCTL0 Control Bits */ +//#define RESERVED (0x0001) /* RESERVED */ +//#define RESERVED (0x0002) /* RESERVED */ +//#define RESERVED (0x0004) /* RESERVED */ +#define NWAITS0_L (0x0010) /* FRAM Wait state control Bit: 0 */ +#define NWAITS1_L (0x0020) /* FRAM Wait state control Bit: 1 */ +#define NWAITS2_L (0x0040) /* FRAM Wait state control Bit: 2 */ +//#define RESERVED (0x0080) /* RESERVED */ + +#define NWAITS_0 (0x0000) /* FRAM Wait state control: 0 */ +#define NWAITS_1 (0x0010) /* FRAM Wait state control: 1 */ +#define NWAITS_2 (0x0020) /* FRAM Wait state control: 2 */ +#define NWAITS_3 (0x0030) /* FRAM Wait state control: 3 */ +#define NWAITS_4 (0x0040) /* FRAM Wait state control: 4 */ +#define NWAITS_5 (0x0050) /* FRAM Wait state control: 5 */ +#define NWAITS_6 (0x0060) /* FRAM Wait state control: 6 */ +#define NWAITS_7 (0x0070) /* FRAM Wait state control: 7 */ + +/* Legacy Defines */ +#define NAUTO (0x0008) /* FRAM Disables the wait state generator (obsolete on Rev.E and later)*/ +#define NACCESS0 (0x0010) /* FRAM Wait state Generator Access Time control Bit: 0 */ +#define NACCESS1 (0x0020) /* FRAM Wait state Generator Access Time control Bit: 1 */ +#define NACCESS2 (0x0040) /* FRAM Wait state Generator Access Time control Bit: 2 */ +#define NACCESS_0 (0x0000) /* FRAM Wait state Generator Access Time control: 0 */ +#define NACCESS_1 (0x0010) /* FRAM Wait state Generator Access Time control: 1 */ +#define NACCESS_2 (0x0020) /* FRAM Wait state Generator Access Time control: 2 */ +#define NACCESS_3 (0x0030) /* FRAM Wait state Generator Access Time control: 3 */ +#define NACCESS_4 (0x0040) /* FRAM Wait state Generator Access Time control: 4 */ +#define NACCESS_5 (0x0050) /* FRAM Wait state Generator Access Time control: 5 */ +#define NACCESS_6 (0x0060) /* FRAM Wait state Generator Access Time control: 6 */ +#define NACCESS_7 (0x0070) /* FRAM Wait state Generator Access Time control: 7 */ + +/* GCCTL0 Control Bits */ +//#define RESERVED (0x0001) /* RESERVED */ +#define FRLPMPWR (0x0002) /* FRAM Enable FRAM auto power up after LPM */ +#define FRPWR (0x0004) /* FRAM Power Control */ +#define ACCTEIE (0x0008) /* Enable NMI event if Access time error occurs */ +//#define RESERVED (0x0010) /* RESERVED */ +#define CBDIE (0x0020) /* Enable NMI event if correctable bit error detected */ +#define UBDIE (0x0040) /* Enable NMI event if uncorrectable bit error detected */ +#define UBDRSTEN (0x0080) /* Enable Power Up Clear (PUC) reset if FRAM uncorrectable bit error detected */ + +/* GCCTL0 Control Bits */ +//#define RESERVED (0x0001) /* RESERVED */ +#define FRLPMPWR_L (0x0002) /* FRAM Enable FRAM auto power up after LPM */ +#define FRPWR_L (0x0004) /* FRAM Power Control */ +#define ACCTEIE_L (0x0008) /* Enable NMI event if Access time error occurs */ +//#define RESERVED (0x0010) /* RESERVED */ +#define CBDIE_L (0x0020) /* Enable NMI event if correctable bit error detected */ +#define UBDIE_L (0x0040) /* Enable NMI event if uncorrectable bit error detected */ +#define UBDRSTEN_L (0x0080) /* Enable Power Up Clear (PUC) reset if FRAM uncorrectable bit error detected */ + +/* GCCTL1 Control Bits */ +//#define RESERVED (0x0001) /* RESERVED */ +#define CBDIFG (0x0002) /* FRAM correctable bit error flag */ +#define UBDIFG (0x0004) /* FRAM uncorrectable bit error flag */ +#define ACCTEIFG (0x0008) /* Access time error flag */ + +/* GCCTL1 Control Bits */ +//#define RESERVED (0x0001) /* RESERVED */ +#define CBDIFG_L (0x0002) /* FRAM correctable bit error flag */ +#define UBDIFG_L (0x0004) /* FRAM uncorrectable bit error flag */ +#define ACCTEIFG_L (0x0008) /* Access time error flag */ + +#endif +/************************************************************ +* LCD_C +************************************************************/ +#ifdef __MSP430_HAS_LCD_C__ /* Definition to show that Module is available */ + +#define OFS_LCDCCTL0 (0x0000) /* LCD_C Control Register 0 */ +#define OFS_LCDCCTL0_L OFS_LCDCCTL0 +#define OFS_LCDCCTL0_H OFS_LCDCCTL0+1 +#define OFS_LCDCCTL1 (0x0002) /* LCD_C Control Register 1 */ +#define OFS_LCDCCTL1_L OFS_LCDCCTL1 +#define OFS_LCDCCTL1_H OFS_LCDCCTL1+1 +#define OFS_LCDCBLKCTL (0x0004) /* LCD_C blinking control register */ +#define OFS_LCDCBLKCTL_L OFS_LCDCBLKCTL +#define OFS_LCDCBLKCTL_H OFS_LCDCBLKCTL+1 +#define OFS_LCDCMEMCTL (0x0006) /* LCD_C memory control register */ +#define OFS_LCDCMEMCTL_L OFS_LCDCMEMCTL +#define OFS_LCDCMEMCTL_H OFS_LCDCMEMCTL+1 +#define OFS_LCDCVCTL (0x0008) /* LCD_C Voltage Control Register */ +#define OFS_LCDCVCTL_L OFS_LCDCVCTL +#define OFS_LCDCVCTL_H OFS_LCDCVCTL+1 +#define OFS_LCDCPCTL0 (0x000A) /* LCD_C Port Control Register 0 */ +#define OFS_LCDCPCTL0_L OFS_LCDCPCTL0 +#define OFS_LCDCPCTL0_H OFS_LCDCPCTL0+1 +#define OFS_LCDCPCTL1 (0x000C) /* LCD_C Port Control Register 1 */ +#define OFS_LCDCPCTL1_L OFS_LCDCPCTL1 +#define OFS_LCDCPCTL1_H OFS_LCDCPCTL1+1 +#define OFS_LCDCPCTL2 (0x000E) /* LCD_C Port Control Register 2 */ +#define OFS_LCDCPCTL2_L OFS_LCDCPCTL2 +#define OFS_LCDCPCTL2_H OFS_LCDCPCTL2+1 +#define OFS_LCDCPCTL3 (0x0010) /* LCD_C Port Control Register 3 */ +#define OFS_LCDCPCTL3_L OFS_LCDCPCTL3 +#define OFS_LCDCPCTL3_H OFS_LCDCPCTL3+1 +#define OFS_LCDCCPCTL (0x0012) /* LCD_C Charge Pump Control Register 3 */ +#define OFS_LCDCCPCTL_L OFS_LCDCCPCTL +#define OFS_LCDCCPCTL_H OFS_LCDCCPCTL+1 +#define OFS_LCDCIV (0x001E) /* LCD_C Interrupt Vector Register */ + +// LCDCCTL0 +#define LCDON (0x0001) /* LCD_C LCD On */ +#define LCDLP (0x0002) /* LCD_C Low Power Waveform */ +#define LCDSON (0x0004) /* LCD_C LCD Segments On */ +#define LCDMX0 (0x0008) /* LCD_C Mux Rate Bit: 0 */ +#define LCDMX1 (0x0010) /* LCD_C Mux Rate Bit: 1 */ +#define LCDMX2 (0x0020) /* LCD_C Mux Rate Bit: 2 */ +//#define RESERVED (0x0040) /* LCD_C RESERVED */ +#define LCDSSEL (0x0080) /* LCD_C Clock Select */ +#define LCDPRE0 (0x0100) /* LCD_C LCD frequency pre-scaler Bit: 0 */ +#define LCDPRE1 (0x0200) /* LCD_C LCD frequency pre-scaler Bit: 1 */ +#define LCDPRE2 (0x0400) /* LCD_C LCD frequency pre-scaler Bit: 2 */ +#define LCDDIV0 (0x0800) /* LCD_C LCD frequency divider Bit: 0 */ +#define LCDDIV1 (0x1000) /* LCD_C LCD frequency divider Bit: 1 */ +#define LCDDIV2 (0x2000) /* LCD_C LCD frequency divider Bit: 2 */ +#define LCDDIV3 (0x4000) /* LCD_C LCD frequency divider Bit: 3 */ +#define LCDDIV4 (0x8000) /* LCD_C LCD frequency divider Bit: 4 */ + +// LCDCCTL0 +#define LCDON_L (0x0001) /* LCD_C LCD On */ +#define LCDLP_L (0x0002) /* LCD_C Low Power Waveform */ +#define LCDSON_L (0x0004) /* LCD_C LCD Segments On */ +#define LCDMX0_L (0x0008) /* LCD_C Mux Rate Bit: 0 */ +#define LCDMX1_L (0x0010) /* LCD_C Mux Rate Bit: 1 */ +#define LCDMX2_L (0x0020) /* LCD_C Mux Rate Bit: 2 */ +//#define RESERVED (0x0040) /* LCD_C RESERVED */ +#define LCDSSEL_L (0x0080) /* LCD_C Clock Select */ + +// LCDCCTL0 +//#define RESERVED (0x0040) /* LCD_C RESERVED */ +#define LCDPRE0_H (0x0001) /* LCD_C LCD frequency pre-scaler Bit: 0 */ +#define LCDPRE1_H (0x0002) /* LCD_C LCD frequency pre-scaler Bit: 1 */ +#define LCDPRE2_H (0x0004) /* LCD_C LCD frequency pre-scaler Bit: 2 */ +#define LCDDIV0_H (0x0008) /* LCD_C LCD frequency divider Bit: 0 */ +#define LCDDIV1_H (0x0010) /* LCD_C LCD frequency divider Bit: 1 */ +#define LCDDIV2_H (0x0020) /* LCD_C LCD frequency divider Bit: 2 */ +#define LCDDIV3_H (0x0040) /* LCD_C LCD frequency divider Bit: 3 */ +#define LCDDIV4_H (0x0080) /* LCD_C LCD frequency divider Bit: 4 */ + +#define LCDPRE_0 (0x0000) /* LCD_C LCD frequency pre-scaler: /1 */ +#define LCDPRE_1 (0x0100) /* LCD_C LCD frequency pre-scaler: /2 */ +#define LCDPRE_2 (0x0200) /* LCD_C LCD frequency pre-scaler: /4 */ +#define LCDPRE_3 (0x0300) /* LCD_C LCD frequency pre-scaler: /8 */ +#define LCDPRE_4 (0x0400) /* LCD_C LCD frequency pre-scaler: /16 */ +#define LCDPRE_5 (0x0500) /* LCD_C LCD frequency pre-scaler: /32 */ +#define LCDPRE__1 (0x0000) /* LCD_C LCD frequency pre-scaler: /1 */ +#define LCDPRE__2 (0x0100) /* LCD_C LCD frequency pre-scaler: /2 */ +#define LCDPRE__4 (0x0200) /* LCD_C LCD frequency pre-scaler: /4 */ +#define LCDPRE__8 (0x0300) /* LCD_C LCD frequency pre-scaler: /8 */ +#define LCDPRE__16 (0x0400) /* LCD_C LCD frequency pre-scaler: /16 */ +#define LCDPRE__32 (0x0500) /* LCD_C LCD frequency pre-scaler: /32 */ + +#define LCDDIV_0 (0x0000) /* LCD_C LCD frequency divider: /1 */ +#define LCDDIV_1 (0x0800) /* LCD_C LCD frequency divider: /2 */ +#define LCDDIV_2 (0x1000) /* LCD_C LCD frequency divider: /3 */ +#define LCDDIV_3 (0x1800) /* LCD_C LCD frequency divider: /4 */ +#define LCDDIV_4 (0x2000) /* LCD_C LCD frequency divider: /5 */ +#define LCDDIV_5 (0x2800) /* LCD_C LCD frequency divider: /6 */ +#define LCDDIV_6 (0x3000) /* LCD_C LCD frequency divider: /7 */ +#define LCDDIV_7 (0x3800) /* LCD_C LCD frequency divider: /8 */ +#define LCDDIV_8 (0x4000) /* LCD_C LCD frequency divider: /9 */ +#define LCDDIV_9 (0x4800) /* LCD_C LCD frequency divider: /10 */ +#define LCDDIV_10 (0x5000) /* LCD_C LCD frequency divider: /11 */ +#define LCDDIV_11 (0x5800) /* LCD_C LCD frequency divider: /12 */ +#define LCDDIV_12 (0x6000) /* LCD_C LCD frequency divider: /13 */ +#define LCDDIV_13 (0x6800) /* LCD_C LCD frequency divider: /14 */ +#define LCDDIV_14 (0x7000) /* LCD_C LCD frequency divider: /15 */ +#define LCDDIV_15 (0x7800) /* LCD_C LCD frequency divider: /16 */ +#define LCDDIV_16 (0x8000) /* LCD_C LCD frequency divider: /17 */ +#define LCDDIV_17 (0x8800) /* LCD_C LCD frequency divider: /18 */ +#define LCDDIV_18 (0x9000) /* LCD_C LCD frequency divider: /19 */ +#define LCDDIV_19 (0x9800) /* LCD_C LCD frequency divider: /20 */ +#define LCDDIV_20 (0xA000) /* LCD_C LCD frequency divider: /21 */ +#define LCDDIV_21 (0xA800) /* LCD_C LCD frequency divider: /22 */ +#define LCDDIV_22 (0xB000) /* LCD_C LCD frequency divider: /23 */ +#define LCDDIV_23 (0xB800) /* LCD_C LCD frequency divider: /24 */ +#define LCDDIV_24 (0xC000) /* LCD_C LCD frequency divider: /25 */ +#define LCDDIV_25 (0xC800) /* LCD_C LCD frequency divider: /26 */ +#define LCDDIV_26 (0xD000) /* LCD_C LCD frequency divider: /27 */ +#define LCDDIV_27 (0xD800) /* LCD_C LCD frequency divider: /28 */ +#define LCDDIV_28 (0xE000) /* LCD_C LCD frequency divider: /29 */ +#define LCDDIV_29 (0xE800) /* LCD_C LCD frequency divider: /30 */ +#define LCDDIV_30 (0xF000) /* LCD_C LCD frequency divider: /31 */ +#define LCDDIV_31 (0xF800) /* LCD_C LCD frequency divider: /32 */ +#define LCDDIV__1 (0x0000) /* LCD_C LCD frequency divider: /1 */ +#define LCDDIV__2 (0x0800) /* LCD_C LCD frequency divider: /2 */ +#define LCDDIV__3 (0x1000) /* LCD_C LCD frequency divider: /3 */ +#define LCDDIV__4 (0x1800) /* LCD_C LCD frequency divider: /4 */ +#define LCDDIV__5 (0x2000) /* LCD_C LCD frequency divider: /5 */ +#define LCDDIV__6 (0x2800) /* LCD_C LCD frequency divider: /6 */ +#define LCDDIV__7 (0x3000) /* LCD_C LCD frequency divider: /7 */ +#define LCDDIV__8 (0x3800) /* LCD_C LCD frequency divider: /8 */ +#define LCDDIV__9 (0x4000) /* LCD_C LCD frequency divider: /9 */ +#define LCDDIV__10 (0x4800) /* LCD_C LCD frequency divider: /10 */ +#define LCDDIV__11 (0x5000) /* LCD_C LCD frequency divider: /11 */ +#define LCDDIV__12 (0x5800) /* LCD_C LCD frequency divider: /12 */ +#define LCDDIV__13 (0x6000) /* LCD_C LCD frequency divider: /13 */ +#define LCDDIV__14 (0x6800) /* LCD_C LCD frequency divider: /14 */ +#define LCDDIV__15 (0x7000) /* LCD_C LCD frequency divider: /15 */ +#define LCDDIV__16 (0x7800) /* LCD_C LCD frequency divider: /16 */ +#define LCDDIV__17 (0x8000) /* LCD_C LCD frequency divider: /17 */ +#define LCDDIV__18 (0x8800) /* LCD_C LCD frequency divider: /18 */ +#define LCDDIV__19 (0x9000) /* LCD_C LCD frequency divider: /19 */ +#define LCDDIV__20 (0x9800) /* LCD_C LCD frequency divider: /20 */ +#define LCDDIV__21 (0xA000) /* LCD_C LCD frequency divider: /21 */ +#define LCDDIV__22 (0xA800) /* LCD_C LCD frequency divider: /22 */ +#define LCDDIV__23 (0xB000) /* LCD_C LCD frequency divider: /23 */ +#define LCDDIV__24 (0xB800) /* LCD_C LCD frequency divider: /24 */ +#define LCDDIV__25 (0xC000) /* LCD_C LCD frequency divider: /25 */ +#define LCDDIV__26 (0xC800) /* LCD_C LCD frequency divider: /26 */ +#define LCDDIV__27 (0xD000) /* LCD_C LCD frequency divider: /27 */ +#define LCDDIV__28 (0xD800) /* LCD_C LCD frequency divider: /28 */ +#define LCDDIV__29 (0xE000) /* LCD_C LCD frequency divider: /29 */ +#define LCDDIV__30 (0xE800) /* LCD_C LCD frequency divider: /30 */ +#define LCDDIV__31 (0xF000) /* LCD_C LCD frequency divider: /31 */ +#define LCDDIV__32 (0xF800) /* LCD_C LCD frequency divider: /32 */ + +/* Display modes coded with Bits 2-4 */ +#define LCDSTATIC (LCDSON) +#define LCD2MUX (LCDMX0+LCDSON) +#define LCD3MUX (LCDMX1+LCDSON) +#define LCD4MUX (LCDMX1+LCDMX0+LCDSON) +#define LCD5MUX (LCDMX2+LCDSON) +#define LCD6MUX (LCDMX2+LCDMX0+LCDSON) +#define LCD7MUX (LCDMX2+LCDMX1+LCDSON) +#define LCD8MUX (LCDMX2+LCDMX1+LCDMX0+LCDSON) + +// LCDCCTL1 +#define LCDFRMIFG (0x0001) /* LCD_C LCD frame interrupt flag */ +#define LCDBLKOFFIFG (0x0002) /* LCD_C LCD blinking off interrupt flag, */ +#define LCDBLKONIFG (0x0004) /* LCD_C LCD blinking on interrupt flag, */ +#define LCDNOCAPIFG (0x0008) /* LCD_C No cpacitance connected interrupt flag */ +#define LCDFRMIE (0x0100) /* LCD_C LCD frame interrupt enable */ +#define LCDBLKOFFIE (0x0200) /* LCD_C LCD blinking off interrupt flag, */ +#define LCDBLKONIE (0x0400) /* LCD_C LCD blinking on interrupt flag, */ +#define LCDNOCAPIE (0x0800) /* LCD_C No cpacitance connected interrupt enable */ + +// LCDCCTL1 +#define LCDFRMIFG_L (0x0001) /* LCD_C LCD frame interrupt flag */ +#define LCDBLKOFFIFG_L (0x0002) /* LCD_C LCD blinking off interrupt flag, */ +#define LCDBLKONIFG_L (0x0004) /* LCD_C LCD blinking on interrupt flag, */ +#define LCDNOCAPIFG_L (0x0008) /* LCD_C No cpacitance connected interrupt flag */ + +// LCDCCTL1 +#define LCDFRMIE_H (0x0001) /* LCD_C LCD frame interrupt enable */ +#define LCDBLKOFFIE_H (0x0002) /* LCD_C LCD blinking off interrupt flag, */ +#define LCDBLKONIE_H (0x0004) /* LCD_C LCD blinking on interrupt flag, */ +#define LCDNOCAPIE_H (0x0008) /* LCD_C No cpacitance connected interrupt enable */ + +// LCDCBLKCTL +#define LCDBLKMOD0 (0x0001) /* LCD_C Blinking mode Bit: 0 */ +#define LCDBLKMOD1 (0x0002) /* LCD_C Blinking mode Bit: 1 */ +#define LCDBLKPRE0 (0x0004) /* LCD_C Clock pre-scaler for blinking frequency Bit: 0 */ +#define LCDBLKPRE1 (0x0008) /* LCD_C Clock pre-scaler for blinking frequency Bit: 1 */ +#define LCDBLKPRE2 (0x0010) /* LCD_C Clock pre-scaler for blinking frequency Bit: 2 */ +#define LCDBLKDIV0 (0x0020) /* LCD_C Clock divider for blinking frequency Bit: 0 */ +#define LCDBLKDIV1 (0x0040) /* LCD_C Clock divider for blinking frequency Bit: 1 */ +#define LCDBLKDIV2 (0x0080) /* LCD_C Clock divider for blinking frequency Bit: 2 */ + +// LCDCBLKCTL +#define LCDBLKMOD0_L (0x0001) /* LCD_C Blinking mode Bit: 0 */ +#define LCDBLKMOD1_L (0x0002) /* LCD_C Blinking mode Bit: 1 */ +#define LCDBLKPRE0_L (0x0004) /* LCD_C Clock pre-scaler for blinking frequency Bit: 0 */ +#define LCDBLKPRE1_L (0x0008) /* LCD_C Clock pre-scaler for blinking frequency Bit: 1 */ +#define LCDBLKPRE2_L (0x0010) /* LCD_C Clock pre-scaler for blinking frequency Bit: 2 */ +#define LCDBLKDIV0_L (0x0020) /* LCD_C Clock divider for blinking frequency Bit: 0 */ +#define LCDBLKDIV1_L (0x0040) /* LCD_C Clock divider for blinking frequency Bit: 1 */ +#define LCDBLKDIV2_L (0x0080) /* LCD_C Clock divider for blinking frequency Bit: 2 */ + +#define LCDBLKMOD_0 (0x0000) /* LCD_C Blinking mode: Off */ +#define LCDBLKMOD_1 (0x0001) /* LCD_C Blinking mode: Individual */ +#define LCDBLKMOD_2 (0x0002) /* LCD_C Blinking mode: All */ +#define LCDBLKMOD_3 (0x0003) /* LCD_C Blinking mode: Switching */ + +// LCDCMEMCTL +#define LCDDISP (0x0001) /* LCD_C LCD memory registers for display */ +#define LCDCLRM (0x0002) /* LCD_C Clear LCD memory */ +#define LCDCLRBM (0x0004) /* LCD_C Clear LCD blinking memory */ + +// LCDCMEMCTL +#define LCDDISP_L (0x0001) /* LCD_C LCD memory registers for display */ +#define LCDCLRM_L (0x0002) /* LCD_C Clear LCD memory */ +#define LCDCLRBM_L (0x0004) /* LCD_C Clear LCD blinking memory */ + +// LCDCVCTL +#define LCD2B (0x0001) /* Selects 1/2 bias. */ +#define VLCDREF0 (0x0002) /* Selects reference voltage for regulated charge pump: 0 */ +#define VLCDREF1 (0x0004) /* Selects reference voltage for regulated charge pump: 1 */ +#define LCDCPEN (0x0008) /* LCD Voltage Charge Pump Enable. */ +#define VLCDEXT (0x0010) /* Select external source for VLCD. */ +#define LCDEXTBIAS (0x0020) /* V2 - V4 voltage select. */ +#define R03EXT (0x0040) /* Selects external connections for LCD mid voltages. */ +#define LCDREXT (0x0080) /* Selects external connection for lowest LCD voltage. */ +#define VLCD0 (0x0200) /* VLCD select: 0 */ +#define VLCD1 (0x0400) /* VLCD select: 1 */ +#define VLCD2 (0x0800) /* VLCD select: 2 */ +#define VLCD3 (0x1000) /* VLCD select: 3 */ +#define VLCD4 (0x2000) /* VLCD select: 4 */ +#define VLCD5 (0x4000) /* VLCD select: 5 */ + +// LCDCVCTL +#define LCD2B_L (0x0001) /* Selects 1/2 bias. */ +#define VLCDREF0_L (0x0002) /* Selects reference voltage for regulated charge pump: 0 */ +#define VLCDREF1_L (0x0004) /* Selects reference voltage for regulated charge pump: 1 */ +#define LCDCPEN_L (0x0008) /* LCD Voltage Charge Pump Enable. */ +#define VLCDEXT_L (0x0010) /* Select external source for VLCD. */ +#define LCDEXTBIAS_L (0x0020) /* V2 - V4 voltage select. */ +#define R03EXT_L (0x0040) /* Selects external connections for LCD mid voltages. */ +#define LCDREXT_L (0x0080) /* Selects external connection for lowest LCD voltage. */ + +// LCDCVCTL +#define VLCD0_H (0x0002) /* VLCD select: 0 */ +#define VLCD1_H (0x0004) /* VLCD select: 1 */ +#define VLCD2_H (0x0008) /* VLCD select: 2 */ +#define VLCD3_H (0x0010) /* VLCD select: 3 */ +#define VLCD4_H (0x0020) /* VLCD select: 4 */ +#define VLCD5_H (0x0040) /* VLCD select: 5 */ + +/* Reference voltage source select for the regulated charge pump */ +#define VLCDREF_0 (0x0000) /* Internal */ +#define VLCDREF_1 (0x0002) /* External */ +#define VLCDREF_2 (0x0004) /* Reserved */ +#define VLCDREF_3 (0x0006) /* Reserved */ + +/* Charge pump voltage selections */ +#define VLCD_0 (0x0000) /* Charge pump disabled */ +#define VLCD_1 (0x0200) /* VLCD = 2.60V */ +#define VLCD_2 (0x0400) /* VLCD = 2.66V */ +#define VLCD_3 (0x0600) /* VLCD = 2.72V */ +#define VLCD_4 (0x0800) /* VLCD = 2.78V */ +#define VLCD_5 (0x0A00) /* VLCD = 2.84V */ +#define VLCD_6 (0x0C00) /* VLCD = 2.90V */ +#define VLCD_7 (0x0E00) /* VLCD = 2.96V */ +#define VLCD_8 (0x1000) /* VLCD = 3.02V */ +#define VLCD_9 (0x1200) /* VLCD = 3.08V */ +#define VLCD_10 (0x1400) /* VLCD = 3.14V */ +#define VLCD_11 (0x1600) /* VLCD = 3.20V */ +#define VLCD_12 (0x1800) /* VLCD = 3.26V */ +#define VLCD_13 (0x1A00) /* VLCD = 3.32V */ +#define VLCD_14 (0x1C00) /* VLCD = 3.38V */ +#define VLCD_15 (0x1E00) /* VLCD = 3.44V */ + +#define VLCD_DISABLED (0x0000) /* Charge pump disabled */ +#define VLCD_2_60 (0x0200) /* VLCD = 2.60V */ +#define VLCD_2_66 (0x0400) /* VLCD = 2.66V */ +#define VLCD_2_72 (0x0600) /* VLCD = 2.72V */ +#define VLCD_2_78 (0x0800) /* VLCD = 2.78V */ +#define VLCD_2_84 (0x0A00) /* VLCD = 2.84V */ +#define VLCD_2_90 (0x0C00) /* VLCD = 2.90V */ +#define VLCD_2_96 (0x0E00) /* VLCD = 2.96V */ +#define VLCD_3_02 (0x1000) /* VLCD = 3.02V */ +#define VLCD_3_08 (0x1200) /* VLCD = 3.08V */ +#define VLCD_3_14 (0x1400) /* VLCD = 3.14V */ +#define VLCD_3_20 (0x1600) /* VLCD = 3.20V */ +#define VLCD_3_26 (0x1800) /* VLCD = 3.26V */ +#define VLCD_3_32 (0x1A00) /* VLCD = 3.32V */ +#define VLCD_3_38 (0x1C00) /* VLCD = 3.38V */ +#define VLCD_3_44 (0x1E00) /* VLCD = 3.44V */ + +// LCDCPCTL0 +#define LCDS0 (0x0001) /* LCD Segment 0 enable. */ +#define LCDS1 (0x0002) /* LCD Segment 1 enable. */ +#define LCDS2 (0x0004) /* LCD Segment 2 enable. */ +#define LCDS3 (0x0008) /* LCD Segment 3 enable. */ +#define LCDS4 (0x0010) /* LCD Segment 4 enable. */ +#define LCDS5 (0x0020) /* LCD Segment 5 enable. */ +#define LCDS6 (0x0040) /* LCD Segment 6 enable. */ +#define LCDS7 (0x0080) /* LCD Segment 7 enable. */ +#define LCDS8 (0x0100) /* LCD Segment 8 enable. */ +#define LCDS9 (0x0200) /* LCD Segment 9 enable. */ +#define LCDS10 (0x0400) /* LCD Segment 10 enable. */ +#define LCDS11 (0x0800) /* LCD Segment 11 enable. */ +#define LCDS12 (0x1000) /* LCD Segment 12 enable. */ +#define LCDS13 (0x2000) /* LCD Segment 13 enable. */ +#define LCDS14 (0x4000) /* LCD Segment 14 enable. */ +#define LCDS15 (0x8000) /* LCD Segment 15 enable. */ + +// LCDCPCTL0 +#define LCDS0_L (0x0001) /* LCD Segment 0 enable. */ +#define LCDS1_L (0x0002) /* LCD Segment 1 enable. */ +#define LCDS2_L (0x0004) /* LCD Segment 2 enable. */ +#define LCDS3_L (0x0008) /* LCD Segment 3 enable. */ +#define LCDS4_L (0x0010) /* LCD Segment 4 enable. */ +#define LCDS5_L (0x0020) /* LCD Segment 5 enable. */ +#define LCDS6_L (0x0040) /* LCD Segment 6 enable. */ +#define LCDS7_L (0x0080) /* LCD Segment 7 enable. */ + +// LCDCPCTL0 +#define LCDS8_H (0x0001) /* LCD Segment 8 enable. */ +#define LCDS9_H (0x0002) /* LCD Segment 9 enable. */ +#define LCDS10_H (0x0004) /* LCD Segment 10 enable. */ +#define LCDS11_H (0x0008) /* LCD Segment 11 enable. */ +#define LCDS12_H (0x0010) /* LCD Segment 12 enable. */ +#define LCDS13_H (0x0020) /* LCD Segment 13 enable. */ +#define LCDS14_H (0x0040) /* LCD Segment 14 enable. */ +#define LCDS15_H (0x0080) /* LCD Segment 15 enable. */ + +// LCDCPCTL1 +#define LCDS16 (0x0001) /* LCD Segment 16 enable. */ +#define LCDS17 (0x0002) /* LCD Segment 17 enable. */ +#define LCDS18 (0x0004) /* LCD Segment 18 enable. */ +#define LCDS19 (0x0008) /* LCD Segment 19 enable. */ +#define LCDS20 (0x0010) /* LCD Segment 20 enable. */ +#define LCDS21 (0x0020) /* LCD Segment 21 enable. */ +#define LCDS22 (0x0040) /* LCD Segment 22 enable. */ +#define LCDS23 (0x0080) /* LCD Segment 23 enable. */ +#define LCDS24 (0x0100) /* LCD Segment 24 enable. */ +#define LCDS25 (0x0200) /* LCD Segment 25 enable. */ +#define LCDS26 (0x0400) /* LCD Segment 26 enable. */ +#define LCDS27 (0x0800) /* LCD Segment 27 enable. */ +#define LCDS28 (0x1000) /* LCD Segment 28 enable. */ +#define LCDS29 (0x2000) /* LCD Segment 29 enable. */ +#define LCDS30 (0x4000) /* LCD Segment 30 enable. */ +#define LCDS31 (0x8000) /* LCD Segment 31 enable. */ + +// LCDCPCTL1 +#define LCDS16_L (0x0001) /* LCD Segment 16 enable. */ +#define LCDS17_L (0x0002) /* LCD Segment 17 enable. */ +#define LCDS18_L (0x0004) /* LCD Segment 18 enable. */ +#define LCDS19_L (0x0008) /* LCD Segment 19 enable. */ +#define LCDS20_L (0x0010) /* LCD Segment 20 enable. */ +#define LCDS21_L (0x0020) /* LCD Segment 21 enable. */ +#define LCDS22_L (0x0040) /* LCD Segment 22 enable. */ +#define LCDS23_L (0x0080) /* LCD Segment 23 enable. */ + +// LCDCPCTL1 +#define LCDS24_H (0x0001) /* LCD Segment 24 enable. */ +#define LCDS25_H (0x0002) /* LCD Segment 25 enable. */ +#define LCDS26_H (0x0004) /* LCD Segment 26 enable. */ +#define LCDS27_H (0x0008) /* LCD Segment 27 enable. */ +#define LCDS28_H (0x0010) /* LCD Segment 28 enable. */ +#define LCDS29_H (0x0020) /* LCD Segment 29 enable. */ +#define LCDS30_H (0x0040) /* LCD Segment 30 enable. */ +#define LCDS31_H (0x0080) /* LCD Segment 31 enable. */ + +// LCDCPCTL2 +#define LCDS32 (0x0001) /* LCD Segment 32 enable. */ +#define LCDS33 (0x0002) /* LCD Segment 33 enable. */ +#define LCDS34 (0x0004) /* LCD Segment 34 enable. */ +#define LCDS35 (0x0008) /* LCD Segment 35 enable. */ +#define LCDS36 (0x0010) /* LCD Segment 36 enable. */ +#define LCDS37 (0x0020) /* LCD Segment 37 enable. */ +#define LCDS38 (0x0040) /* LCD Segment 38 enable. */ +#define LCDS39 (0x0080) /* LCD Segment 39 enable. */ +#define LCDS40 (0x0100) /* LCD Segment 40 enable. */ +#define LCDS41 (0x0200) /* LCD Segment 41 enable. */ +#define LCDS42 (0x0400) /* LCD Segment 42 enable. */ +#define LCDS43 (0x0800) /* LCD Segment 43 enable. */ +#define LCDS44 (0x1000) /* LCD Segment 44 enable. */ +#define LCDS45 (0x2000) /* LCD Segment 45 enable. */ +#define LCDS46 (0x4000) /* LCD Segment 46 enable. */ +#define LCDS47 (0x8000) /* LCD Segment 47 enable. */ + +// LCDCPCTL2 +#define LCDS32_L (0x0001) /* LCD Segment 32 enable. */ +#define LCDS33_L (0x0002) /* LCD Segment 33 enable. */ +#define LCDS34_L (0x0004) /* LCD Segment 34 enable. */ +#define LCDS35_L (0x0008) /* LCD Segment 35 enable. */ +#define LCDS36_L (0x0010) /* LCD Segment 36 enable. */ +#define LCDS37_L (0x0020) /* LCD Segment 37 enable. */ +#define LCDS38_L (0x0040) /* LCD Segment 38 enable. */ +#define LCDS39_L (0x0080) /* LCD Segment 39 enable. */ + +// LCDCPCTL2 +#define LCDS40_H (0x0001) /* LCD Segment 40 enable. */ +#define LCDS41_H (0x0002) /* LCD Segment 41 enable. */ +#define LCDS42_H (0x0004) /* LCD Segment 42 enable. */ +#define LCDS43_H (0x0008) /* LCD Segment 43 enable. */ +#define LCDS44_H (0x0010) /* LCD Segment 44 enable. */ +#define LCDS45_H (0x0020) /* LCD Segment 45 enable. */ +#define LCDS46_H (0x0040) /* LCD Segment 46 enable. */ +#define LCDS47_H (0x0080) /* LCD Segment 47 enable. */ + +// LCDCPCTL3 +#define LCDS48 (0x0001) /* LCD Segment 48 enable. */ +#define LCDS49 (0x0002) /* LCD Segment 49 enable. */ +#define LCDS50 (0x0004) /* LCD Segment 50 enable. */ +#define LCDS51 (0x0008) /* LCD Segment 51 enable. */ +#define LCDS52 (0x0010) /* LCD Segment 52 enable. */ +#define LCDS53 (0x0020) /* LCD Segment 53 enable. */ + +// LCDCPCTL3 +#define LCDS48_L (0x0001) /* LCD Segment 48 enable. */ +#define LCDS49_L (0x0002) /* LCD Segment 49 enable. */ +#define LCDS50_L (0x0004) /* LCD Segment 50 enable. */ +#define LCDS51_L (0x0008) /* LCD Segment 51 enable. */ +#define LCDS52_L (0x0010) /* LCD Segment 52 enable. */ +#define LCDS53_L (0x0020) /* LCD Segment 53 enable. */ + +// LCDCCPCTL +#define LCDCPDIS0 (0x0001) /* LCD charge pump disable */ +#define LCDCPDIS1 (0x0002) /* LCD charge pump disable */ +#define LCDCPDIS2 (0x0004) /* LCD charge pump disable */ +#define LCDCPDIS3 (0x0008) /* LCD charge pump disable */ +#define LCDCPDIS4 (0x0010) /* LCD charge pump disable */ +#define LCDCPDIS5 (0x0020) /* LCD charge pump disable */ +#define LCDCPDIS6 (0x0040) /* LCD charge pump disable */ +#define LCDCPDIS7 (0x0080) /* LCD charge pump disable */ +#define LCDCPCLKSYNC (0x8000) /* LCD charge pump clock synchronization */ + +// LCDCCPCTL +#define LCDCPDIS0_L (0x0001) /* LCD charge pump disable */ +#define LCDCPDIS1_L (0x0002) /* LCD charge pump disable */ +#define LCDCPDIS2_L (0x0004) /* LCD charge pump disable */ +#define LCDCPDIS3_L (0x0008) /* LCD charge pump disable */ +#define LCDCPDIS4_L (0x0010) /* LCD charge pump disable */ +#define LCDCPDIS5_L (0x0020) /* LCD charge pump disable */ +#define LCDCPDIS6_L (0x0040) /* LCD charge pump disable */ +#define LCDCPDIS7_L (0x0080) /* LCD charge pump disable */ + +// LCDCCPCTL +#define LCDCPCLKSYNC_H (0x0080) /* LCD charge pump clock synchronization */ + +#define OFS_LCDM1 (0x0020) /* LCD Memory 1 */ +#define LCDMEM_ LCDM1 /* LCD Memory */ +#ifdef __ASM_HEADER__ +#define LCDMEM LCDM1 /* LCD Memory (for assembler) */ +#else +#define LCDMEM ((char*) &LCDM1) /* LCD Memory (for C) */ +#endif +#define OFS_LCDM2 (0x0021) /* LCD Memory 2 */ +#define OFS_LCDM3 (0x0022) /* LCD Memory 3 */ +#define OFS_LCDM4 (0x0023) /* LCD Memory 4 */ +#define OFS_LCDM5 (0x0024) /* LCD Memory 5 */ +#define OFS_LCDM6 (0x0025) /* LCD Memory 6 */ +#define OFS_LCDM7 (0x0026) /* LCD Memory 7 */ +#define OFS_LCDM8 (0x0027) /* LCD Memory 8 */ +#define OFS_LCDM9 (0x0028) /* LCD Memory 9 */ +#define OFS_LCDM10 (0x0029) /* LCD Memory 10 */ +#define OFS_LCDM11 (0x002A) /* LCD Memory 11 */ +#define OFS_LCDM12 (0x002B) /* LCD Memory 12 */ +#define OFS_LCDM13 (0x002C) /* LCD Memory 13 */ +#define OFS_LCDM14 (0x002D) /* LCD Memory 14 */ +#define OFS_LCDM15 (0x002E) /* LCD Memory 15 */ +#define OFS_LCDM16 (0x002F) /* LCD Memory 16 */ +#define OFS_LCDM17 (0x0030) /* LCD Memory 17 */ +#define OFS_LCDM18 (0x0031) /* LCD Memory 18 */ +#define OFS_LCDM19 (0x0032) /* LCD Memory 19 */ +#define OFS_LCDM20 (0x0033) /* LCD Memory 20 */ +#define OFS_LCDM21 (0x0034) /* LCD Memory 21 */ +#define OFS_LCDM22 (0x0035) /* LCD Memory 22 */ +#define OFS_LCDM23 (0x0036) /* LCD Memory 23 */ +#define OFS_LCDM24 (0x0037) /* LCD Memory 24 */ +#define OFS_LCDM25 (0x0038) /* LCD Memory 25 */ +#define OFS_LCDM26 (0x0039) /* LCD Memory 26 */ +#define OFS_LCDM27 (0x003A) /* LCD Memory 27 */ +#define OFS_LCDM28 (0x003B) /* LCD Memory 28 */ +#define OFS_LCDM29 (0x003C) /* LCD Memory 29 */ +#define OFS_LCDM30 (0x003D) /* LCD Memory 30 */ +#define OFS_LCDM31 (0x003E) /* LCD Memory 31 */ +#define OFS_LCDM32 (0x003F) /* LCD Memory 32 */ +#define OFS_LCDM33 (0x0040) /* LCD Memory 33 */ +#define OFS_LCDM34 (0x0041) /* LCD Memory 34 */ +#define OFS_LCDM35 (0x0042) /* LCD Memory 35 */ +#define OFS_LCDM36 (0x0043) /* LCD Memory 36 */ +#define OFS_LCDM37 (0x0044) /* LCD Memory 37 */ +#define OFS_LCDM38 (0x0045) /* LCD Memory 38 */ +#define OFS_LCDM39 (0x0046) /* LCD Memory 39 */ +#define OFS_LCDM40 (0x0047) /* LCD Memory 40 */ + +#define OFS_LCDBM1 (0x0040) /* LCD Blinking Memory 1 */ +#define LCDBMEM_ LCDBM1 /* LCD Blinking Memory */ +#ifdef __ASM_HEADER__ +#define LCDBMEM (LCDBM1) /* LCD Blinking Memory (for assembler) */ +#else +#define LCDBMEM ((char*) &LCDBM1) /* LCD Blinking Memory (for C) */ +#endif +#define OFS_LCDBM2 (0x0041) /* LCD Blinking Memory 2 */ +#define OFS_LCDBM3 (0x0042) /* LCD Blinking Memory 3 */ +#define OFS_LCDBM4 (0x0043) /* LCD Blinking Memory 4 */ +#define OFS_LCDBM5 (0x0044) /* LCD Blinking Memory 5 */ +#define OFS_LCDBM6 (0x0045) /* LCD Blinking Memory 6 */ +#define OFS_LCDBM7 (0x0046) /* LCD Blinking Memory 7 */ +#define OFS_LCDBM8 (0x0047) /* LCD Blinking Memory 8 */ +#define OFS_LCDBM9 (0x0048) /* LCD Blinking Memory 9 */ +#define OFS_LCDBM10 (0x0049) /* LCD Blinking Memory 10 */ +#define OFS_LCDBM11 (0x004A) /* LCD Blinking Memory 11 */ +#define OFS_LCDBM12 (0x004B) /* LCD Blinking Memory 12 */ +#define OFS_LCDBM13 (0x004C) /* LCD Blinking Memory 13 */ +#define OFS_LCDBM14 (0x004D) /* LCD Blinking Memory 14 */ +#define OFS_LCDBM15 (0x004E) /* LCD Blinking Memory 15 */ +#define OFS_LCDBM16 (0x004F) /* LCD Blinking Memory 16 */ +#define OFS_LCDBM17 (0x0050) /* LCD Blinking Memory 17 */ +#define OFS_LCDBM18 (0x0051) /* LCD Blinking Memory 18 */ +#define OFS_LCDBM19 (0x0052) /* LCD Blinking Memory 19 */ +#define OFS_LCDBM20 (0x0053) /* LCD Blinking Memory 20 */ + +/* LCDCIV Definitions */ +#define LCDCIV_NONE (0x0000) /* No Interrupt pending */ +#define LCDCIV_LCDNOCAPIFG (0x0002) /* No capacitor connected */ +#define LCDCIV_LCDCLKOFFIFG (0x0004) /* Blink, segments off */ +#define LCDCIV_LCDCLKONIFG (0x0006) /* Blink, segments on */ +#define LCDCIV_LCDFRMIFG (0x0008) /* Frame interrupt */ + +#endif +/************************************************************ +* Memory Protection Unit +************************************************************/ +#ifdef __MSP430_HAS_MPU__ /* Definition to show that Module is available */ + +#define OFS_MPUCTL0 (0x0000) /* MPU Control Register 0 */ +#define OFS_MPUCTL0_L OFS_MPUCTL0 +#define OFS_MPUCTL0_H OFS_MPUCTL0+1 +#define OFS_MPUCTL1 (0x0002) /* MPU Control Register 1 */ +#define OFS_MPUCTL1_L OFS_MPUCTL1 +#define OFS_MPUCTL1_H OFS_MPUCTL1+1 +#define OFS_MPUSEGB2 (0x0004) /* MPU Segmentation Border 2 Register */ +#define OFS_MPUSEGB2_L OFS_MPUSEGB2 +#define OFS_MPUSEGB2_H OFS_MPUSEGB2+1 +#define OFS_MPUSEGB1 (0x0006) /* MPU Segmentation Border 1 Register */ +#define OFS_MPUSEGB1_L OFS_MPUSEGB1 +#define OFS_MPUSEGB1_H OFS_MPUSEGB1+1 +#define OFS_MPUSAM (0x0008) /* MPU Access Management Register */ +#define OFS_MPUSAM_L OFS_MPUSAM +#define OFS_MPUSAM_H OFS_MPUSAM+1 +#define OFS_MPUIPC0 (0x000A) /* MPU IP Control 0 Register */ +#define OFS_MPUIPC0_L OFS_MPUIPC0 +#define OFS_MPUIPC0_H OFS_MPUIPC0+1 +#define OFS_MPUIPSEGB2 (0x000C) /* MPU IP Segment Border 2 Register */ +#define OFS_MPUIPSEGB2_L OFS_MPUIPSEGB2 +#define OFS_MPUIPSEGB2_H OFS_MPUIPSEGB2+1 +#define OFS_MPUIPSEGB1 (0x000E) /* MPU IP Segment Border 1 Register */ +#define OFS_MPUIPSEGB1_L OFS_MPUIPSEGB1 +#define OFS_MPUIPSEGB1_H OFS_MPUIPSEGB1+1 + +/* MPUCTL0 Control Bits */ +#define MPUENA (0x0001) /* MPU Enable */ +#define MPULOCK (0x0002) /* MPU Lock */ +#define MPUSEGIE (0x0010) /* MPU Enable NMI on Segment violation */ + +/* MPUCTL0 Control Bits */ +#define MPUENA_L (0x0001) /* MPU Enable */ +#define MPULOCK_L (0x0002) /* MPU Lock */ +#define MPUSEGIE_L (0x0010) /* MPU Enable NMI on Segment violation */ + +#define MPUPW (0xA500) /* MPU Access Password */ +#define MPUPW_H (0xA5) /* MPU Access Password */ + +/* MPUCTL1 Control Bits */ +#define MPUSEG1IFG (0x0001) /* MPU Main Memory Segment 1 violation interupt flag */ +#define MPUSEG2IFG (0x0002) /* MPU Main Memory Segment 2 violation interupt flag */ +#define MPUSEG3IFG (0x0004) /* MPU Main Memory Segment 3 violation interupt flag */ +#define MPUSEGIIFG (0x0008) /* MPU Info Memory Segment violation interupt flag */ +#define MPUSEGIPIFG (0x0010) /* MPU IP Memory Segment violation interupt flag */ + +/* MPUCTL1 Control Bits */ +#define MPUSEG1IFG_L (0x0001) /* MPU Main Memory Segment 1 violation interupt flag */ +#define MPUSEG2IFG_L (0x0002) /* MPU Main Memory Segment 2 violation interupt flag */ +#define MPUSEG3IFG_L (0x0004) /* MPU Main Memory Segment 3 violation interupt flag */ +#define MPUSEGIIFG_L (0x0008) /* MPU Info Memory Segment violation interupt flag */ +#define MPUSEGIPIFG_L (0x0010) /* MPU IP Memory Segment violation interupt flag */ + +/* MPUSEGB2 Control Bits */ + +/* MPUSEGB2 Control Bits */ + +/* MPUSEGB2 Control Bits */ + +/* MPUSEGB1 Control Bits */ + +/* MPUSEGB1 Control Bits */ + +/* MPUSEGB1 Control Bits */ + +/* MPUSAM Control Bits */ +#define MPUSEG1RE (0x0001) /* MPU Main memory Segment 1 Read enable */ +#define MPUSEG1WE (0x0002) /* MPU Main memory Segment 1 Write enable */ +#define MPUSEG1XE (0x0004) /* MPU Main memory Segment 1 Execute enable */ +#define MPUSEG1VS (0x0008) /* MPU Main memory Segment 1 Violation select */ +#define MPUSEG2RE (0x0010) /* MPU Main memory Segment 2 Read enable */ +#define MPUSEG2WE (0x0020) /* MPU Main memory Segment 2 Write enable */ +#define MPUSEG2XE (0x0040) /* MPU Main memory Segment 2 Execute enable */ +#define MPUSEG2VS (0x0080) /* MPU Main memory Segment 2 Violation select */ +#define MPUSEG3RE (0x0100) /* MPU Main memory Segment 3 Read enable */ +#define MPUSEG3WE (0x0200) /* MPU Main memory Segment 3 Write enable */ +#define MPUSEG3XE (0x0400) /* MPU Main memory Segment 3 Execute enable */ +#define MPUSEG3VS (0x0800) /* MPU Main memory Segment 3 Violation select */ +#define MPUSEGIRE (0x1000) /* MPU Info memory Segment Read enable */ +#define MPUSEGIWE (0x2000) /* MPU Info memory Segment Write enable */ +#define MPUSEGIXE (0x4000) /* MPU Info memory Segment Execute enable */ +#define MPUSEGIVS (0x8000) /* MPU Info memory Segment Violation select */ + +/* MPUSAM Control Bits */ +#define MPUSEG1RE_L (0x0001) /* MPU Main memory Segment 1 Read enable */ +#define MPUSEG1WE_L (0x0002) /* MPU Main memory Segment 1 Write enable */ +#define MPUSEG1XE_L (0x0004) /* MPU Main memory Segment 1 Execute enable */ +#define MPUSEG1VS_L (0x0008) /* MPU Main memory Segment 1 Violation select */ +#define MPUSEG2RE_L (0x0010) /* MPU Main memory Segment 2 Read enable */ +#define MPUSEG2WE_L (0x0020) /* MPU Main memory Segment 2 Write enable */ +#define MPUSEG2XE_L (0x0040) /* MPU Main memory Segment 2 Execute enable */ +#define MPUSEG2VS_L (0x0080) /* MPU Main memory Segment 2 Violation select */ + +/* MPUSAM Control Bits */ +#define MPUSEG3RE_H (0x0001) /* MPU Main memory Segment 3 Read enable */ +#define MPUSEG3WE_H (0x0002) /* MPU Main memory Segment 3 Write enable */ +#define MPUSEG3XE_H (0x0004) /* MPU Main memory Segment 3 Execute enable */ +#define MPUSEG3VS_H (0x0008) /* MPU Main memory Segment 3 Violation select */ +#define MPUSEGIRE_H (0x0010) /* MPU Info memory Segment Read enable */ +#define MPUSEGIWE_H (0x0020) /* MPU Info memory Segment Write enable */ +#define MPUSEGIXE_H (0x0040) /* MPU Info memory Segment Execute enable */ +#define MPUSEGIVS_H (0x0080) /* MPU Info memory Segment Violation select */ + +/* MPUIPC0 Control Bits */ +#define MPUIPVS (0x0020) /* MPU MPU IP protection segment Violation Select */ +#define MPUIPENA (0x0040) /* MPU MPU IP Protection Enable */ +#define MPUIPLOCK (0x0080) /* MPU IP Protection Lock */ + +/* MPUIPC0 Control Bits */ +#define MPUIPVS_L (0x0020) /* MPU MPU IP protection segment Violation Select */ +#define MPUIPENA_L (0x0040) /* MPU MPU IP Protection Enable */ +#define MPUIPLOCK_L (0x0080) /* MPU IP Protection Lock */ + +/* MPUIPSEGB2 Control Bits */ + +/* MPUIPSEGB2 Control Bits */ + +/* MPUIPSEGB2 Control Bits */ + +/* MPUIPSEGB1 Control Bits */ + +/* MPUIPSEGB1 Control Bits */ + +/* MPUIPSEGB1 Control Bits */ + +#endif +/************************************************************ +* HARDWARE MULTIPLIER 32Bit +************************************************************/ +#ifdef __MSP430_HAS_MPY32__ /* Definition to show that Module is available */ + +#define OFS_MPY (0x0000) /* Multiply Unsigned/Operand 1 */ +#define OFS_MPY_L OFS_MPY +#define OFS_MPY_H OFS_MPY+1 +#define OFS_MPYS (0x0002) /* Multiply Signed/Operand 1 */ +#define OFS_MPYS_L OFS_MPYS +#define OFS_MPYS_H OFS_MPYS+1 +#define OFS_MAC (0x0004) /* Multiply Unsigned and Accumulate/Operand 1 */ +#define OFS_MAC_L OFS_MAC +#define OFS_MAC_H OFS_MAC+1 +#define OFS_MACS (0x0006) /* Multiply Signed and Accumulate/Operand 1 */ +#define OFS_MACS_L OFS_MACS +#define OFS_MACS_H OFS_MACS+1 +#define OFS_OP2 (0x0008) /* Operand 2 */ +#define OFS_OP2_L OFS_OP2 +#define OFS_OP2_H OFS_OP2+1 +#define OFS_RESLO (0x000A) /* Result Low Word */ +#define OFS_RESLO_L OFS_RESLO +#define OFS_RESLO_H OFS_RESLO+1 +#define OFS_RESHI (0x000C) /* Result High Word */ +#define OFS_RESHI_L OFS_RESHI +#define OFS_RESHI_H OFS_RESHI+1 +#define OFS_SUMEXT (0x000E) /* Sum Extend */ +#define OFS_SUMEXT_L OFS_SUMEXT +#define OFS_SUMEXT_H OFS_SUMEXT+1 +#define OFS_MPY32CTL0 (0x002C) +#define OFS_MPY32CTL0_L OFS_MPY32CTL0 +#define OFS_MPY32CTL0_H OFS_MPY32CTL0+1 + +#define OFS_MPY32L (0x0010) /* 32-bit operand 1 - multiply - low word */ +#define OFS_MPY32L_L OFS_MPY32L +#define OFS_MPY32L_H OFS_MPY32L+1 +#define OFS_MPY32H (0x0012) /* 32-bit operand 1 - multiply - high word */ +#define OFS_MPY32H_L OFS_MPY32H +#define OFS_MPY32H_H OFS_MPY32H+1 +#define OFS_MPYS32L (0x0014) /* 32-bit operand 1 - signed multiply - low word */ +#define OFS_MPYS32L_L OFS_MPYS32L +#define OFS_MPYS32L_H OFS_MPYS32L+1 +#define OFS_MPYS32H (0x0016) /* 32-bit operand 1 - signed multiply - high word */ +#define OFS_MPYS32H_L OFS_MPYS32H +#define OFS_MPYS32H_H OFS_MPYS32H+1 +#define OFS_MAC32L (0x0018) /* 32-bit operand 1 - multiply accumulate - low word */ +#define OFS_MAC32L_L OFS_MAC32L +#define OFS_MAC32L_H OFS_MAC32L+1 +#define OFS_MAC32H (0x001A) /* 32-bit operand 1 - multiply accumulate - high word */ +#define OFS_MAC32H_L OFS_MAC32H +#define OFS_MAC32H_H OFS_MAC32H+1 +#define OFS_MACS32L (0x001C) /* 32-bit operand 1 - signed multiply accumulate - low word */ +#define OFS_MACS32L_L OFS_MACS32L +#define OFS_MACS32L_H OFS_MACS32L+1 +#define OFS_MACS32H (0x001E) /* 32-bit operand 1 - signed multiply accumulate - high word */ +#define OFS_MACS32H_L OFS_MACS32H +#define OFS_MACS32H_H OFS_MACS32H+1 +#define OFS_OP2L (0x0020) /* 32-bit operand 2 - low word */ +#define OFS_OP2L_L OFS_OP2L +#define OFS_OP2L_H OFS_OP2L+1 +#define OFS_OP2H (0x0022) /* 32-bit operand 2 - high word */ +#define OFS_OP2H_L OFS_OP2H +#define OFS_OP2H_H OFS_OP2H+1 +#define OFS_RES0 (0x0024) /* 32x32-bit result 0 - least significant word */ +#define OFS_RES0_L OFS_RES0 +#define OFS_RES0_H OFS_RES0+1 +#define OFS_RES1 (0x0026) /* 32x32-bit result 1 */ +#define OFS_RES1_L OFS_RES1 +#define OFS_RES1_H OFS_RES1+1 +#define OFS_RES2 (0x0028) /* 32x32-bit result 2 */ +#define OFS_RES2_L OFS_RES2 +#define OFS_RES2_H OFS_RES2+1 +#define OFS_RES3 (0x002A) /* 32x32-bit result 3 - most significant word */ +#define OFS_RES3_L OFS_RES3 +#define OFS_RES3_H OFS_RES3+1 +#define OFS_SUMEXT (0x000E) +#define OFS_SUMEXT_L OFS_SUMEXT +#define OFS_SUMEXT_H OFS_SUMEXT+1 +#define OFS_MPY32CTL0 (0x002C) /* MPY32 Control Register 0 */ +#define OFS_MPY32CTL0_L OFS_MPY32CTL0 +#define OFS_MPY32CTL0_H OFS_MPY32CTL0+1 + +#define MPY_B MPY_L /* Multiply Unsigned/Operand 1 (Byte Access) */ +#define MPYS_B MPYS_L /* Multiply Signed/Operand 1 (Byte Access) */ +#define MAC_B MAC_L /* Multiply Unsigned and Accumulate/Operand 1 (Byte Access) */ +#define MACS_B MACS_L /* Multiply Signed and Accumulate/Operand 1 (Byte Access) */ +#define OP2_B OP2_L /* Operand 2 (Byte Access) */ +#define MPY32L_B MPY32L_L /* 32-bit operand 1 - multiply - low word (Byte Access) */ +#define MPY32H_B MPY32H_L /* 32-bit operand 1 - multiply - high word (Byte Access) */ +#define MPYS32L_B MPYS32L_L /* 32-bit operand 1 - signed multiply - low word (Byte Access) */ +#define MPYS32H_B MPYS32H_L /* 32-bit operand 1 - signed multiply - high word (Byte Access) */ +#define MAC32L_B MAC32L_L /* 32-bit operand 1 - multiply accumulate - low word (Byte Access) */ +#define MAC32H_B MAC32H_L /* 32-bit operand 1 - multiply accumulate - high word (Byte Access) */ +#define MACS32L_B MACS32L_L /* 32-bit operand 1 - signed multiply accumulate - low word (Byte Access) */ +#define MACS32H_B MACS32H_L /* 32-bit operand 1 - signed multiply accumulate - high word (Byte Access) */ +#define OP2L_B OP2L_L /* 32-bit operand 2 - low word (Byte Access) */ +#define OP2H_B OP2H_L /* 32-bit operand 2 - high word (Byte Access) */ + +/* MPY32CTL0 Control Bits */ +#define MPYC (0x0001) /* Carry of the multiplier */ +//#define RESERVED (0x0002) /* Reserved */ +#define MPYFRAC (0x0004) /* Fractional mode */ +#define MPYSAT (0x0008) /* Saturation mode */ +#define MPYM0 (0x0010) /* Multiplier mode Bit:0 */ +#define MPYM1 (0x0020) /* Multiplier mode Bit:1 */ +#define OP1_32 (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */ +#define OP2_32 (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */ +#define MPYDLYWRTEN (0x0100) /* Delayed write enable */ +#define MPYDLY32 (0x0200) /* Delayed write mode */ + +/* MPY32CTL0 Control Bits */ +#define MPYC_L (0x0001) /* Carry of the multiplier */ +//#define RESERVED (0x0002) /* Reserved */ +#define MPYFRAC_L (0x0004) /* Fractional mode */ +#define MPYSAT_L (0x0008) /* Saturation mode */ +#define MPYM0_L (0x0010) /* Multiplier mode Bit:0 */ +#define MPYM1_L (0x0020) /* Multiplier mode Bit:1 */ +#define OP1_32_L (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */ +#define OP2_32_L (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */ + +/* MPY32CTL0 Control Bits */ +//#define RESERVED (0x0002) /* Reserved */ +#define MPYDLYWRTEN_H (0x0001) /* Delayed write enable */ +#define MPYDLY32_H (0x0002) /* Delayed write mode */ + +#define MPYM_0 (0x0000) /* Multiplier mode: MPY */ +#define MPYM_1 (0x0010) /* Multiplier mode: MPYS */ +#define MPYM_2 (0x0020) /* Multiplier mode: MAC */ +#define MPYM_3 (0x0030) /* Multiplier mode: MACS */ +#define MPYM__MPY (0x0000) /* Multiplier mode: MPY */ +#define MPYM__MPYS (0x0010) /* Multiplier mode: MPYS */ +#define MPYM__MAC (0x0020) /* Multiplier mode: MAC */ +#define MPYM__MACS (0x0030) /* Multiplier mode: MACS */ + +#endif +/************************************************************ +* PMM - Power Management System for FRAM +************************************************************/ +#ifdef __MSP430_HAS_PMM_FRAM__ /* Definition to show that Module is available */ + +#define OFS_PMMCTL0 (0x0000) /* PMM Control 0 */ +#define OFS_PMMCTL0_L OFS_PMMCTL0 +#define OFS_PMMCTL0_H OFS_PMMCTL0+1 +#define OFS_PMMCTL1 (0x0002) /* PMM Control 1 */ +#define OFS_PMMIFG (0x000A) /* PMM Interrupt Flag */ +#define OFS_PMMIFG_L OFS_PMMIFG +#define OFS_PMMIFG_H OFS_PMMIFG+1 +#define OFS_PM5CTL0 (0x0010) /* PMM Power Mode 5 Control Register 0 */ +#define OFS_PM5CTL0_L OFS_PM5CTL0 +#define OFS_PM5CTL0_H OFS_PM5CTL0+1 + +#define PMMPW (0xA500) /* PMM Register Write Password */ +#define PMMPW_H (0xA5) /* PMM Register Write Password for high word access */ + +/* PMMCTL0 Control Bits */ +#define PMMSWBOR (0x0004) /* PMM Software BOR */ +#define PMMSWPOR (0x0008) /* PMM Software POR */ +#define PMMREGOFF (0x0010) /* PMM Turn Regulator off */ +#define SVSHE (0x0040) /* SVS high side enable */ +#define PMMLPRST (0x0080) /* PMM Low-Power Reset Enable */ + +/* PMMCTL0 Control Bits */ +#define PMMSWBOR_L (0x0004) /* PMM Software BOR */ +#define PMMSWPOR_L (0x0008) /* PMM Software POR */ +#define PMMREGOFF_L (0x0010) /* PMM Turn Regulator off */ +#define SVSHE_L (0x0040) /* SVS high side enable */ +#define PMMLPRST_L (0x0080) /* PMM Low-Power Reset Enable */ + +/* PMMCTL1 Control Bits */ +#define PMMLPSVEN (0x0002) /* PMM Low-Power Supervision Enable */ +#define PMMLPRNG0 (0x0004) /* PMM Load Range Control overwrite for LPM2, LPM3 and LPM4 Bit: 0 */ +#define PMMLPRNG1 (0x0008) /* PMM Load Range Control overwrite for LPM2, LPM3 and LPM4 Bit: 1 */ +#define PMMAMRNG0 (0x0010) /* Load Range Control overwrite for AM, LPM0 and LPM1 Bit: 0 */ +#define PMMAMRNG1 (0x0020) /* Load Range Control overwrite for AM, LPM0 and LPM1 Bit: 1 */ +#define PMMAMRNG2 (0x0040) /* Load Range Control overwrite for AM, LPM0 and LPM1 Bit: 2 */ +#define PMMAMRNG3 (0x0080) /* Load Range Control overwrite for AM, LPM0 and LPM1 Bit: 3 */ +#define PMMCTL1KEY (0xCC00) /* PMM PMMCTL1 Register Write Password */ + +/* PMMIFG Control Bits */ +#define PMMBORIFG (0x0100) /* PMM Software BOR interrupt flag */ +#define PMMRSTIFG (0x0200) /* PMM RESET pin interrupt flag */ +#define PMMPORIFG (0x0400) /* PMM Software POR interrupt flag */ +#define SVSHIFG (0x2000) /* SVS low side interrupt flag */ +#define PMMLPM5IFG (0x8000) /* LPM5 indication Flag */ + +/* PMMIFG Control Bits */ +#define PMMBORIFG_H (0x0001) /* PMM Software BOR interrupt flag */ +#define PMMRSTIFG_H (0x0002) /* PMM RESET pin interrupt flag */ +#define PMMPORIFG_H (0x0004) /* PMM Software POR interrupt flag */ +#define SVSHIFG_H (0x0020) /* SVS low side interrupt flag */ +#define PMMLPM5IFG_H (0x0080) /* LPM5 indication Flag */ + +/* PM5CTL0 Power Mode 5 Control Bits */ +#define LOCKLPM5 (0x0001) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */ + +/* PM5CTL0 Power Mode 5 Control Bits */ +#define LOCKLPM5_L (0x0001) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */ + + +#endif +/************************************************************ +* DIGITAL I/O Port1/2 Pull up / Pull down Resistors +************************************************************/ +#ifdef __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORTA_R__ /* Definition to show that Module is available */ + +#define OFS_PAIN (0x0000) /* Port A Input */ +#define OFS_PAIN_L OFS_PAIN +#define OFS_PAIN_H OFS_PAIN+1 +#define OFS_PAOUT (0x0002) /* Port A Output */ +#define OFS_PAOUT_L OFS_PAOUT +#define OFS_PAOUT_H OFS_PAOUT+1 +#define OFS_PADIR (0x0004) /* Port A Direction */ +#define OFS_PADIR_L OFS_PADIR +#define OFS_PADIR_H OFS_PADIR+1 +#define OFS_PAREN (0x0006) /* Port A Resistor Enable */ +#define OFS_PAREN_L OFS_PAREN +#define OFS_PAREN_H OFS_PAREN+1 +#define OFS_PASEL0 (0x000A) /* Port A Selection 0 */ +#define OFS_PASEL0_L OFS_PASEL0 +#define OFS_PASEL0_H OFS_PASEL0+1 +#define OFS_PASEL1 (0x000C) /* Port A Selection 1 */ +#define OFS_PASEL1_L OFS_PASEL1 +#define OFS_PASEL1_H OFS_PASEL1+1 +#define OFS_PASELC (0x0016) /* Port A Complement Selection */ +#define OFS_PASELC_L OFS_PASELC +#define OFS_PASELC_H OFS_PASELC+1 +#define OFS_PAIES (0x0018) /* Port A Interrupt Edge Select */ +#define OFS_PAIES_L OFS_PAIES +#define OFS_PAIES_H OFS_PAIES+1 +#define OFS_PAIE (0x001A) /* Port A Interrupt Enable */ +#define OFS_PAIE_L OFS_PAIE +#define OFS_PAIE_H OFS_PAIE+1 +#define OFS_PAIFG (0x001C) /* Port A Interrupt Flag */ +#define OFS_PAIFG_L OFS_PAIFG +#define OFS_PAIFG_H OFS_PAIFG+1 + + +#define OFS_P1IN (0x0000) +#define OFS_P1OUT (0x0002) +#define OFS_P1DIR (0x0004) +#define OFS_P1REN (0x0006) +#define OFS_P1SEL0 (0x000A) +#define OFS_P1SEL1 (0x000C) +#define OFS_P1SELC (0x0016) +#define OFS_P1IV (0x000E) /* Port 1 Interrupt Vector Word */ +#define OFS_P1IES (0x0018) +#define OFS_P1IE (0x001A) +#define OFS_P1IFG (0x001C) +#define OFS_P2IN (0x0001) +#define OFS_P2OUT (0x0003) +#define OFS_P2DIR (0x0005) +#define OFS_P2REN (0x0007) +#define OFS_P2SEL0 (0x000B) +#define OFS_P2SEL1 (0x000D) +#define OFS_P2SELC (0x0017) +#define OFS_P2IV (0x001E) /* Port 2 Interrupt Vector Word */ +#define OFS_P2IES (0x0019) +#define OFS_P2IE (0x001B) +#define OFS_P2IFG (0x001d) +#define P1IN (PAIN_L) /* Port 1 Input */ +#define P1OUT (PAOUT_L) /* Port 1 Output */ +#define P1DIR (PADIR_L) /* Port 1 Direction */ +#define P1REN (PAREN_L) /* Port 1 Resistor Enable */ +#define P1SEL0 (PASEL0_L) /* Port 1 Selection 0 */ +#define P1SEL1 (PASEL1_L) /* Port 1 Selection 1 */ +#define P1SELC (PASELC_L) /* Port 1 Complement Selection */ +#define P1IES (PAIES_L) /* Port 1 Interrupt Edge Select */ +#define P1IE (PAIE_L) /* Port 1 Interrupt Enable */ +#define P1IFG (PAIFG_L) /* Port 1 Interrupt Flag */ + +//Definitions for P1IV +#define P1IV_NONE (0x0000) /* No Interrupt pending */ +#define P1IV_P1IFG0 (0x0002) /* P1IV P1IFG.0 */ +#define P1IV_P1IFG1 (0x0004) /* P1IV P1IFG.1 */ +#define P1IV_P1IFG2 (0x0006) /* P1IV P1IFG.2 */ +#define P1IV_P1IFG3 (0x0008) /* P1IV P1IFG.3 */ +#define P1IV_P1IFG4 (0x000A) /* P1IV P1IFG.4 */ +#define P1IV_P1IFG5 (0x000C) /* P1IV P1IFG.5 */ +#define P1IV_P1IFG6 (0x000E) /* P1IV P1IFG.6 */ +#define P1IV_P1IFG7 (0x0010) /* P1IV P1IFG.7 */ + +#define P2IN (PAIN_H) /* Port 2 Input */ +#define P2OUT (PAOUT_H) /* Port 2 Output */ +#define P2DIR (PADIR_H) /* Port 2 Direction */ +#define P2REN (PAREN_H) /* Port 2 Resistor Enable */ +#define P2SEL0 (PASEL0_H) /* Port 2 Selection 0 */ +#define P2SEL1 (PASEL1_H) /* Port 2 Selection 1 */ +#define P2SELC (PASELC_H) /* Port 2 Complement Selection */ +#define P2IES (PAIES_H) /* Port 2 Interrupt Edge Select */ +#define P2IE (PAIE_H) /* Port 2 Interrupt Enable */ +#define P2IFG (PAIFG_H) /* Port 2 Interrupt Flag */ + +//Definitions for P2IV +#define P2IV_NONE (0x0000) /* No Interrupt pending */ +#define P2IV_P2IFG0 (0x0002) /* P2IV P2IFG.0 */ +#define P2IV_P2IFG1 (0x0004) /* P2IV P2IFG.1 */ +#define P2IV_P2IFG2 (0x0006) /* P2IV P2IFG.2 */ +#define P2IV_P2IFG3 (0x0008) /* P2IV P2IFG.3 */ +#define P2IV_P2IFG4 (0x000A) /* P2IV P2IFG.4 */ +#define P2IV_P2IFG5 (0x000C) /* P2IV P2IFG.5 */ +#define P2IV_P2IFG6 (0x000E) /* P2IV P2IFG.6 */ +#define P2IV_P2IFG7 (0x0010) /* P2IV P2IFG.7 */ + + +#endif +#endif +#endif +/************************************************************ +* DIGITAL I/O Port3/4 Pull up / Pull down Resistors +************************************************************/ +#ifdef __MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORT4_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORTB_R__ /* Definition to show that Module is available */ + +#define OFS_PBIN (0x0000) /* Port B Input */ +#define OFS_PBIN_L OFS_PBIN +#define OFS_PBIN_H OFS_PBIN+1 +#define OFS_PBOUT (0x0002) /* Port B Output */ +#define OFS_PBOUT_L OFS_PBOUT +#define OFS_PBOUT_H OFS_PBOUT+1 +#define OFS_PBDIR (0x0004) /* Port B Direction */ +#define OFS_PBDIR_L OFS_PBDIR +#define OFS_PBDIR_H OFS_PBDIR+1 +#define OFS_PBREN (0x0006) /* Port B Resistor Enable */ +#define OFS_PBREN_L OFS_PBREN +#define OFS_PBREN_H OFS_PBREN+1 +#define OFS_PBSEL0 (0x000A) /* Port B Selection 0 */ +#define OFS_PBSEL0_L OFS_PBSEL0 +#define OFS_PBSEL0_H OFS_PBSEL0+1 +#define OFS_PBSEL1 (0x000C) /* Port B Selection 1 */ +#define OFS_PBSEL1_L OFS_PBSEL1 +#define OFS_PBSEL1_H OFS_PBSEL1+1 +#define OFS_PBSELC (0x0016) /* Port B Complement Selection */ +#define OFS_PBSELC_L OFS_PBSELC +#define OFS_PBSELC_H OFS_PBSELC+1 +#define OFS_PBIES (0x0018) /* Port B Interrupt Edge Select */ +#define OFS_PBIES_L OFS_PBIES +#define OFS_PBIES_H OFS_PBIES+1 +#define OFS_PBIE (0x001A) /* Port B Interrupt Enable */ +#define OFS_PBIE_L OFS_PBIE +#define OFS_PBIE_H OFS_PBIE+1 +#define OFS_PBIFG (0x001C) /* Port B Interrupt Flag */ +#define OFS_PBIFG_L OFS_PBIFG +#define OFS_PBIFG_H OFS_PBIFG+1 + + +#define OFS_P3IN (0x0000) +#define OFS_P3OUT (0x0002) +#define OFS_P3DIR (0x0004) +#define OFS_P3REN (0x0006) +#define OFS_P3SEL0 (0x000A) +#define OFS_P3SEL1 (0x000C) +#define OFS_P3SELC (0x0016) +#define OFS_P3IV (0x000E) /* Port 3 Interrupt Vector Word */ +#define OFS_P3IES (0x0018) +#define OFS_P3IE (0x001A) +#define OFS_P3IFG (0x001C) +#define OFS_P4IN (0x0001) +#define OFS_P4OUT (0x0003) +#define OFS_P4DIR (0x0005) +#define OFS_P4REN (0x0007) +#define OFS_P4SEL0 (0x000B) +#define OFS_P4SEL1 (0x000D) +#define OFS_P4SELC (0x0017) +#define OFS_P4IV (0x001E) /* Port 4 Interrupt Vector Word */ +#define OFS_P4IES (0x0019) +#define OFS_P4IE (0x001B) +#define OFS_P4IFG (0x001d) +#define P3IN (PBIN_L) /* Port 3 Input */ +#define P3OUT (PBOUT_L) /* Port 3 Output */ +#define P3DIR (PBDIR_L) /* Port 3 Direction */ +#define P3REN (PBREN_L) /* Port 3 Resistor Enable */ +#define P3SEL0 (PBSEL0_L) /* Port 3 Selection 0 */ +#define P3SEL1 (PBSEL1_L) /* Port 3 Selection 1 */ +#define P3SELC (PBSELC_L) /* Port 3 Complement Selection */ +#define P3IES (PBIES_L) /* Port 3 Interrupt Edge Select */ +#define P3IE (PBIE_L) /* Port 3 Interrupt Enable */ +#define P3IFG (PBIFG_L) /* Port 3 Interrupt Flag */ + +//Definitions for P3IV +#define P3IV_NONE (0x0000) /* No Interrupt pending */ +#define P3IV_P3IFG0 (0x0002) /* P3IV P3IFG.0 */ +#define P3IV_P3IFG1 (0x0004) /* P3IV P3IFG.1 */ +#define P3IV_P3IFG2 (0x0006) /* P3IV P3IFG.2 */ +#define P3IV_P3IFG3 (0x0008) /* P3IV P3IFG.3 */ +#define P3IV_P3IFG4 (0x000A) /* P3IV P3IFG.4 */ +#define P3IV_P3IFG5 (0x000C) /* P3IV P3IFG.5 */ +#define P3IV_P3IFG6 (0x000E) /* P3IV P3IFG.6 */ +#define P3IV_P3IFG7 (0x0010) /* P3IV P3IFG.7 */ + +#define P4IN (PBIN_H) /* Port 4 Input */ +#define P4OUT (PBOUT_H) /* Port 4 Output */ +#define P4DIR (PBDIR_H) /* Port 4 Direction */ +#define P4REN (PBREN_H) /* Port 4 Resistor Enable */ +#define P4SEL0 (PBSEL0_H) /* Port 4 Selection 0 */ +#define P4SEL1 (PBSEL1_H) /* Port 4 Selection 1 */ +#define P4SELC (PBSELC_H) /* Port 4 Complement Selection */ +#define P4IES (PBIES_H) /* Port 4 Interrupt Edge Select */ +#define P4IE (PBIE_H) /* Port 4 Interrupt Enable */ +#define P4IFG (PBIFG_H) /* Port 4 Interrupt Flag */ + +//Definitions for P4IV +#define P4IV_NONE (0x0000) /* No Interrupt pending */ +#define P4IV_P4IFG0 (0x0002) /* P4IV P4IFG.0 */ +#define P4IV_P4IFG1 (0x0004) /* P4IV P4IFG.1 */ +#define P4IV_P4IFG2 (0x0006) /* P4IV P4IFG.2 */ +#define P4IV_P4IFG3 (0x0008) /* P4IV P4IFG.3 */ +#define P4IV_P4IFG4 (0x000A) /* P4IV P4IFG.4 */ +#define P4IV_P4IFG5 (0x000C) /* P4IV P4IFG.5 */ +#define P4IV_P4IFG6 (0x000E) /* P4IV P4IFG.6 */ +#define P4IV_P4IFG7 (0x0010) /* P4IV P4IFG.7 */ + + +#endif +#endif +#endif +/************************************************************ +* DIGITAL I/O Port5/6 Pull up / Pull down Resistors +************************************************************/ +#ifdef __MSP430_HAS_PORT5_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORT6_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORTC_R__ /* Definition to show that Module is available */ + +#define OFS_PCIN (0x0000) /* Port C Input */ +#define OFS_PCIN_L OFS_PCIN +#define OFS_PCIN_H OFS_PCIN+1 +#define OFS_PCOUT (0x0002) /* Port C Output */ +#define OFS_PCOUT_L OFS_PCOUT +#define OFS_PCOUT_H OFS_PCOUT+1 +#define OFS_PCDIR (0x0004) /* Port C Direction */ +#define OFS_PCDIR_L OFS_PCDIR +#define OFS_PCDIR_H OFS_PCDIR+1 +#define OFS_PCREN (0x0006) /* Port C Resistor Enable */ +#define OFS_PCREN_L OFS_PCREN +#define OFS_PCREN_H OFS_PCREN+1 +#define OFS_PCSEL0 (0x000A) /* Port C Selection 0 */ +#define OFS_PCSEL0_L OFS_PCSEL0 +#define OFS_PCSEL0_H OFS_PCSEL0+1 +#define OFS_PCSEL1 (0x000C) /* Port C Selection 1 */ +#define OFS_PCSEL1_L OFS_PCSEL1 +#define OFS_PCSEL1_H OFS_PCSEL1+1 +#define OFS_PCSELC (0x0016) /* Port C Complement Selection */ +#define OFS_PCSELC_L OFS_PCSELC +#define OFS_PCSELC_H OFS_PCSELC+1 +#define OFS_PCIES (0x0018) /* Port C Interrupt Edge Select */ +#define OFS_PCIES_L OFS_PCIES +#define OFS_PCIES_H OFS_PCIES+1 +#define OFS_PCIE (0x001A) /* Port C Interrupt Enable */ +#define OFS_PCIE_L OFS_PCIE +#define OFS_PCIE_H OFS_PCIE+1 +#define OFS_PCIFG (0x001C) /* Port C Interrupt Flag */ +#define OFS_PCIFG_L OFS_PCIFG +#define OFS_PCIFG_H OFS_PCIFG+1 + + +#define OFS_P5IN (0x0000) +#define OFS_P5OUT (0x0002) +#define OFS_P5DIR (0x0004) +#define OFS_P5REN (0x0006) +#define OFS_P5SEL0 (0x000A) +#define OFS_P5SEL1 (0x000C) +#define OFS_P5SELC (0x0016) +#define OFS_P5IV (0x000E) /* Port 5 Interrupt Vector Word */ +#define OFS_P5IES (0x0018) +#define OFS_P5IE (0x001A) +#define OFS_P5IFG (0x001C) +#define OFS_P6IN (0x0001) +#define OFS_P6OUT (0x0003) +#define OFS_P6DIR (0x0005) +#define OFS_P6REN (0x0007) +#define OFS_P6SEL0 (0x000B) +#define OFS_P6SEL1 (0x000D) +#define OFS_P6SELC (0x0017) +#define OFS_P6IV (0x001E) /* Port 6 Interrupt Vector Word */ +#define OFS_P6IES (0x0019) +#define OFS_P6IE (0x001B) +#define OFS_P6IFG (0x001d) +#define P5IN (PCIN_L) /* Port 5 Input */ +#define P5OUT (PCOUT_L) /* Port 5 Output */ +#define P5DIR (PCDIR_L) /* Port 5 Direction */ +#define P5REN (PCREN_L) /* Port 5 Resistor Enable */ +#define P5SEL0 (PCSEL0_L) /* Port 5 Selection 0 */ +#define P5SEL1 (PCSEL1_L) /* Port 5 Selection 1 */ +#define P5SELC (PCSELC_L) /* Port 5 Complement Selection */ +#define P5IES (PCIES_L) /* Port 5 Interrupt Edge Select */ +#define P5IE (PCIE_L) /* Port 5 Interrupt Enable */ +#define P5IFG (PCIFG_L) /* Port 5 Interrupt Flag */ + +//Definitions for P5IV +#define P5IV_NONE (0x0000) /* No Interrupt pending */ +#define P5IV_P5IFG0 (0x0002) /* P5IV P5IFG.0 */ +#define P5IV_P5IFG1 (0x0004) /* P5IV P5IFG.1 */ +#define P5IV_P5IFG2 (0x0006) /* P5IV P5IFG.2 */ +#define P5IV_P5IFG3 (0x0008) /* P5IV P5IFG.3 */ +#define P5IV_P5IFG4 (0x000A) /* P5IV P5IFG.4 */ +#define P5IV_P5IFG5 (0x000C) /* P5IV P5IFG.5 */ +#define P5IV_P5IFG6 (0x000E) /* P5IV P5IFG.6 */ +#define P5IV_P5IFG7 (0x0010) /* P5IV P5IFG.7 */ + +#define P6IN (PCIN_H) /* Port 6 Input */ +#define P6OUT (PCOUT_H) /* Port 6 Output */ +#define P6DIR (PCDIR_H) /* Port 6 Direction */ +#define P6REN (PCREN_H) /* Port 6 Resistor Enable */ +#define P6SEL0 (PCSEL0_H) /* Port 6 Selection 0 */ +#define P6SEL1 (PCSEL1_H) /* Port 6 Selection 1 */ +#define P6SELC (PCSELC_H) /* Port 6 Complement Selection */ +#define P6IES (PCIES_H) /* Port 6 Interrupt Edge Select */ +#define P6IE (PCIE_H) /* Port 6 Interrupt Enable */ +#define P6IFG (PCIFG_H) /* Port 6 Interrupt Flag */ + +//Definitions for P6IV +#define P6IV_NONE (0x0000) /* No Interrupt pending */ +#define P6IV_P6IFG0 (0x0002) /* P6IV P6IFG.0 */ +#define P6IV_P6IFG1 (0x0004) /* P6IV P6IFG.1 */ +#define P6IV_P6IFG2 (0x0006) /* P6IV P6IFG.2 */ +#define P6IV_P6IFG3 (0x0008) /* P6IV P6IFG.3 */ +#define P6IV_P6IFG4 (0x000A) /* P6IV P6IFG.4 */ +#define P6IV_P6IFG5 (0x000C) /* P6IV P6IFG.5 */ +#define P6IV_P6IFG6 (0x000E) /* P6IV P6IFG.6 */ +#define P6IV_P6IFG7 (0x0010) /* P6IV P6IFG.7 */ + + +#endif +#endif +#endif +/************************************************************ +* DIGITAL I/O Port7/8 Pull up / Pull down Resistors +************************************************************/ +#ifdef __MSP430_HAS_PORT7_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORT8_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORTD_R__ /* Definition to show that Module is available */ + +#define OFS_PDIN (0x0000) /* Port D Input */ +#define OFS_PDIN_L OFS_PDIN +#define OFS_PDIN_H OFS_PDIN+1 +#define OFS_PDOUT (0x0002) /* Port D Output */ +#define OFS_PDOUT_L OFS_PDOUT +#define OFS_PDOUT_H OFS_PDOUT+1 +#define OFS_PDDIR (0x0004) /* Port D Direction */ +#define OFS_PDDIR_L OFS_PDDIR +#define OFS_PDDIR_H OFS_PDDIR+1 +#define OFS_PDREN (0x0006) /* Port D Resistor Enable */ +#define OFS_PDREN_L OFS_PDREN +#define OFS_PDREN_H OFS_PDREN+1 +#define OFS_PDSEL0 (0x000A) /* Port D Selection 0 */ +#define OFS_PDSEL0_L OFS_PDSEL0 +#define OFS_PDSEL0_H OFS_PDSEL0+1 +#define OFS_PDSEL1 (0x000C) /* Port D Selection 1 */ +#define OFS_PDSEL1_L OFS_PDSEL1 +#define OFS_PDSEL1_H OFS_PDSEL1+1 +#define OFS_PDSELC (0x0016) /* Port D Complement Selection */ +#define OFS_PDSELC_L OFS_PDSELC +#define OFS_PDSELC_H OFS_PDSELC+1 +#define OFS_PDIES (0x0018) /* Port D Interrupt Edge Select */ +#define OFS_PDIES_L OFS_PDIES +#define OFS_PDIES_H OFS_PDIES+1 +#define OFS_PDIE (0x001A) /* Port D Interrupt Enable */ +#define OFS_PDIE_L OFS_PDIE +#define OFS_PDIE_H OFS_PDIE+1 +#define OFS_PDIFG (0x001C) /* Port D Interrupt Flag */ +#define OFS_PDIFG_L OFS_PDIFG +#define OFS_PDIFG_H OFS_PDIFG+1 + + +#define OFS_P7IN (0x0000) +#define OFS_P7OUT (0x0002) +#define OFS_P7DIR (0x0004) +#define OFS_P7REN (0x0006) +#define OFS_P7SEL0 (0x000A) +#define OFS_P7SEL1 (0x000C) +#define OFS_P7SELC (0x0016) +#define OFS_P7IV (0x000E) /* Port 7 Interrupt Vector Word */ +#define OFS_P7IES (0x0018) +#define OFS_P7IE (0x001A) +#define OFS_P7IFG (0x001C) +#define OFS_P8IN (0x0001) +#define OFS_P8OUT (0x0003) +#define OFS_P8DIR (0x0005) +#define OFS_P8REN (0x0007) +#define OFS_P8SEL0 (0x000B) +#define OFS_P8SEL1 (0x000D) +#define OFS_P8SELC (0x0017) +#define OFS_P8IV (0x001E) /* Port 8 Interrupt Vector Word */ +#define OFS_P8IES (0x0019) +#define OFS_P8IE (0x001B) +#define OFS_P8IFG (0x001d) +#define P7IN (PDIN_L) /* Port 7 Input */ +#define P7OUT (PDOUT_L) /* Port 7 Output */ +#define P7DIR (PDDIR_L) /* Port 7 Direction */ +#define P7REN (PDREN_L) /* Port 7 Resistor Enable */ +#define P7SEL0 (PDSEL0_L) /* Port 7 Selection 0 */ +#define P7SEL1 (PDSEL1_L) /* Port 7 Selection 1 */ +#define P7SELC (PDSELC_L) /* Port 7 Complement Selection */ +#define P7IES (PDIES_L) /* Port 7 Interrupt Edge Select */ +#define P7IE (PDIE_L) /* Port 7 Interrupt Enable */ +#define P7IFG (PDIFG_L) /* Port 7 Interrupt Flag */ + +//Definitions for P7IV +#define P7IV_NONE (0x0000) /* No Interrupt pending */ +#define P7IV_P7IFG0 (0x0002) /* P7IV P7IFG.0 */ +#define P7IV_P7IFG1 (0x0004) /* P7IV P7IFG.1 */ +#define P7IV_P7IFG2 (0x0006) /* P7IV P7IFG.2 */ +#define P7IV_P7IFG3 (0x0008) /* P7IV P7IFG.3 */ +#define P7IV_P7IFG4 (0x000A) /* P7IV P7IFG.4 */ +#define P7IV_P7IFG5 (0x000C) /* P7IV P7IFG.5 */ +#define P7IV_P7IFG6 (0x000E) /* P7IV P7IFG.6 */ +#define P7IV_P7IFG7 (0x0010) /* P7IV P7IFG.7 */ + +#define P8IN (PDIN_H) /* Port 8 Input */ +#define P8OUT (PDOUT_H) /* Port 8 Output */ +#define P8DIR (PDDIR_H) /* Port 8 Direction */ +#define P8REN (PDREN_H) /* Port 8 Resistor Enable */ +#define P8SEL0 (PDSEL0_H) /* Port 8 Selection 0 */ +#define P8SEL1 (PDSEL1_H) /* Port 8 Selection 1 */ +#define P8SELC (PDSELC_H) /* Port 8 Complement Selection */ +#define P8IES (PDIES_H) /* Port 8 Interrupt Edge Select */ +#define P8IE (PDIE_H) /* Port 8 Interrupt Enable */ +#define P8IFG (PDIFG_H) /* Port 8 Interrupt Flag */ + +//Definitions for P8IV +#define P8IV_NONE (0x0000) /* No Interrupt pending */ +#define P8IV_P8IFG0 (0x0002) /* P8IV P8IFG.0 */ +#define P8IV_P8IFG1 (0x0004) /* P8IV P8IFG.1 */ +#define P8IV_P8IFG2 (0x0006) /* P8IV P8IFG.2 */ +#define P8IV_P8IFG3 (0x0008) /* P8IV P8IFG.3 */ +#define P8IV_P8IFG4 (0x000A) /* P8IV P8IFG.4 */ +#define P8IV_P8IFG5 (0x000C) /* P8IV P8IFG.5 */ +#define P8IV_P8IFG6 (0x000E) /* P8IV P8IFG.6 */ +#define P8IV_P8IFG7 (0x0010) /* P8IV P8IFG.7 */ + + +#endif +#endif +#endif +/************************************************************ +* DIGITAL I/O Port9/10 Pull up / Pull down Resistors +************************************************************/ +#ifdef __MSP430_HAS_PORT9_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORT10_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORTE_R__ /* Definition to show that Module is available */ + +#define OFS_PEIN (0x0000) /* Port E Input */ +#define OFS_PEIN_L OFS_PEIN +#define OFS_PEIN_H OFS_PEIN+1 +#define OFS_PEOUT (0x0002) /* Port E Output */ +#define OFS_PEOUT_L OFS_PEOUT +#define OFS_PEOUT_H OFS_PEOUT+1 +#define OFS_PEDIR (0x0004) /* Port E Direction */ +#define OFS_PEDIR_L OFS_PEDIR +#define OFS_PEDIR_H OFS_PEDIR+1 +#define OFS_PEREN (0x0006) /* Port E Resistor Enable */ +#define OFS_PEREN_L OFS_PEREN +#define OFS_PEREN_H OFS_PEREN+1 +#define OFS_PESEL0 (0x000A) /* Port E Selection 0 */ +#define OFS_PESEL0_L OFS_PESEL0 +#define OFS_PESEL0_H OFS_PESEL0+1 +#define OFS_PESEL1 (0x000C) /* Port E Selection 1 */ +#define OFS_PESEL1_L OFS_PESEL1 +#define OFS_PESEL1_H OFS_PESEL1+1 +#define OFS_PESELC (0x0016) /* Port E Complement Selection */ +#define OFS_PESELC_L OFS_PESELC +#define OFS_PESELC_H OFS_PESELC+1 +#define OFS_PEIES (0x0018) /* Port E Interrupt Edge Select */ +#define OFS_PEIES_L OFS_PEIES +#define OFS_PEIES_H OFS_PEIES+1 +#define OFS_PEIE (0x001A) /* Port E Interrupt Enable */ +#define OFS_PEIE_L OFS_PEIE +#define OFS_PEIE_H OFS_PEIE+1 +#define OFS_PEIFG (0x001C) /* Port E Interrupt Flag */ +#define OFS_PEIFG_L OFS_PEIFG +#define OFS_PEIFG_H OFS_PEIFG+1 + + +#define OFS_P9IN (0x0000) +#define OFS_P9OUT (0x0002) +#define OFS_P9DIR (0x0004) +#define OFS_P9REN (0x0006) +#define OFS_P9SEL0 (0x000A) +#define OFS_P9SEL1 (0x000C) +#define OFS_P9SELC (0x0016) +#define OFS_P9IV (0x000E) /* Port 9 Interrupt Vector Word */ +#define OFS_P9IES (0x0018) +#define OFS_P9IE (0x001A) +#define OFS_P9IFG (0x001C) +#define OFS_P10IN (0x0001) +#define OFS_P10OUT (0x0003) +#define OFS_P10DIR (0x0005) +#define OFS_P10REN (0x0007) +#define OFS_P10SEL0 (0x000B) +#define OFS_P10SEL1 (0x000D) +#define OFS_P10SELC (0x0017) +#define OFS_P10IV (0x001E) /* Port 10 Interrupt Vector Word */ +#define OFS_P10IES (0x0019) +#define OFS_P10IE (0x001B) +#define OFS_P10IFG (0x001d) +#define P9IN (PEIN_L) /* Port 9 Input */ +#define P9OUT (PEOUT_L) /* Port 9 Output */ +#define P9DIR (PEDIR_L) /* Port 9 Direction */ +#define P9REN (PEREN_L) /* Port 9 Resistor Enable */ +#define P9SEL0 (PESEL0_L) /* Port 9 Selection 0 */ +#define P9SEL1 (PESEL1_L) /* Port 9 Selection 1 */ +#define P9SELC (PESELC_L) /* Port 9 Complement Selection */ +#define P9IES (PEIES_L) /* Port 9 Interrupt Edge Select */ +#define P9IE (PEIE_L) /* Port 9 Interrupt Enable */ +#define P9IFG (PEIFG_L) /* Port 9 Interrupt Flag */ + +//Definitions for P9IV +#define P9IV_NONE (0x0000) /* No Interrupt pending */ +#define P9IV_P9IFG0 (0x0002) /* P9IV P9IFG.0 */ +#define P9IV_P9IFG1 (0x0004) /* P9IV P9IFG.1 */ +#define P9IV_P9IFG2 (0x0006) /* P9IV P9IFG.2 */ +#define P9IV_P9IFG3 (0x0008) /* P9IV P9IFG.3 */ +#define P9IV_P9IFG4 (0x000A) /* P9IV P9IFG.4 */ +#define P9IV_P9IFG5 (0x000C) /* P9IV P9IFG.5 */ +#define P9IV_P9IFG6 (0x000E) /* P9IV P9IFG.6 */ +#define P9IV_P9IFG7 (0x0010) /* P9IV P9IFG.7 */ + +#define P10IN (PEIN_H) /* Port 10 Input */ +#define P10OUT (PEOUT_H) /* Port 10 Output */ +#define P10DIR (PEDIR_H) /* Port 10 Direction */ +#define P10REN (PEREN_H) /* Port 10 Resistor Enable */ +#define P10SEL0 (PESEL0_H) /* Port 10 Selection 0 */ +#define P10SEL1 (PESEL1_H) /* Port 10 Selection 1 */ +#define P10SELC (PESELC_H) /* Port 10 Complement Selection */ +#define P10IES (PEIES_H) /* Port 10 Interrupt Edge Select */ +#define P10IE (PEIE_H) /* Port 10 Interrupt Enable */ +#define P10IFG (PEIFG_H) /* Port 10 Interrupt Flag */ + +//Definitions for P10IV +#define P10IV_NONE (0x0000) /* No Interrupt pending */ +#define P10IV_P10IFG0 (0x0002) /* P10IV P10IFG.0 */ +#define P10IV_P10IFG1 (0x0004) /* P10IV P10IFG.1 */ +#define P10IV_P10IFG2 (0x0006) /* P10IV P10IFG.2 */ +#define P10IV_P10IFG3 (0x0008) /* P10IV P10IFG.3 */ +#define P10IV_P10IFG4 (0x000A) /* P10IV P10IFG.4 */ +#define P10IV_P10IFG5 (0x000C) /* P10IV P10IFG.5 */ +#define P10IV_P10IFG6 (0x000E) /* P10IV P10IFG.6 */ +#define P10IV_P10IFG7 (0x0010) /* P10IV P10IFG.7 */ + + +#endif +#endif +#endif +/************************************************************ +* DIGITAL I/O Port11 Pull up / Pull down Resistors +************************************************************/ +#ifdef __MSP430_HAS_PORT11_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORTF_R__ /* Definition to show that Module is available */ + +#define OFS_PFIN (0x0000) /* Port F Input */ +#define OFS_PFIN_L OFS_PFIN +#define OFS_PFIN_H OFS_PFIN+1 +#define OFS_PFOUT (0x0002) /* Port F Output */ +#define OFS_PFOUT_L OFS_PFOUT +#define OFS_PFOUT_H OFS_PFOUT+1 +#define OFS_PFDIR (0x0004) /* Port F Direction */ +#define OFS_PFDIR_L OFS_PFDIR +#define OFS_PFDIR_H OFS_PFDIR+1 +#define OFS_PFREN (0x0006) /* Port F Resistor Enable */ +#define OFS_PFREN_L OFS_PFREN +#define OFS_PFREN_H OFS_PFREN+1 +#define OFS_PFSEL0 (0x000A) /* Port F Selection 0 */ +#define OFS_PFSEL0_L OFS_PFSEL0 +#define OFS_PFSEL0_H OFS_PFSEL0+1 +#define OFS_PFSEL1 (0x000C) /* Port F Selection 1 */ +#define OFS_PFSEL1_L OFS_PFSEL1 +#define OFS_PFSEL1_H OFS_PFSEL1+1 +#define OFS_PFSELC (0x0016) /* Port F Complement Selection */ +#define OFS_PFSELC_L OFS_PFSELC +#define OFS_PFSELC_H OFS_PFSELC+1 +#define OFS_PFIES (0x0018) /* Port F Interrupt Edge Select */ +#define OFS_PFIES_L OFS_PFIES +#define OFS_PFIES_H OFS_PFIES+1 +#define OFS_PFIE (0x001A) /* Port F Interrupt Enable */ +#define OFS_PFIE_L OFS_PFIE +#define OFS_PFIE_H OFS_PFIE+1 +#define OFS_PFIFG (0x001C) /* Port F Interrupt Flag */ +#define OFS_PFIFG_L OFS_PFIFG +#define OFS_PFIFG_H OFS_PFIFG+1 + + +#define OFS_P11IN (0x0000) +#define OFS_P11OUT (0x0002) +#define OFS_P11DIR (0x0004) +#define OFS_P11REN (0x0006) +#define OFS_P11SEL0 (0x000A) +#define OFS_P11SEL1 (0x000C) +#define OFS_P11SELC (0x0016) +#define OFS_P11IV (0x000E) /* Port 11 Interrupt Vector Word */ +#define OFS_P11IES (0x0018) +#define OFS_P11IE (0x001A) +#define OFS_P11IFG (0x001C) +#define P11IN (PFIN_L) /* Port 11 Input */ +#define P11OUT (PFOUT_L) /* Port 11 Output */ +#define P11DIR (PFDIR_L) /* Port 11 Direction */ +#define P11REN (PFREN_L) /* Port 11 Resistor Enable */ +#define P11SEL0 (PFSEL0_L) /* Port 11 Selection0 */ +#define P11SEL1 (PFSEL1_L) /* Port 11 Selection1 */ +#define OFS_P11SELC (0x0017) + +#define P11IES (PFIES_L) /* Port 11 Interrupt Edge Select */ +#define P11IE (PFIE_L) /* Port 11 Interrupt Enable */ +#define P11IFG (PFIFG_L) /* Port 11 Interrupt Flag */ + +//Definitions for P11IV +#define P11IV_NONE (0x0000) /* No Interrupt pending */ +#define P11IV_P11IFG0 (0x0002) /* P11IV P11IFG.0 */ +#define P11IV_P11IFG1 (0x0004) /* P11IV P11IFG.1 */ +#define P11IV_P11IFG2 (0x0006) /* P11IV P11IFG.2 */ +#define P11IV_P11IFG3 (0x0008) /* P11IV P11IFG.3 */ +#define P11IV_P11IFG4 (0x000A) /* P11IV P11IFG.4 */ +#define P11IV_P11IFG5 (0x000C) /* P11IV P11IFG.5 */ +#define P11IV_P11IFG6 (0x000E) /* P11IV P11IFG.6 */ +#define P11IV_P11IFG7 (0x0010) /* P11IV P11IFG.7 */ + + +#endif +#endif +/************************************************************ +* DIGITAL I/O PortJ Pull up / Pull down Resistors +************************************************************/ +#ifdef __MSP430_HAS_PORTJ_R__ /* Definition to show that Module is available */ + +#define OFS_PJIN (0x0000) /* Port J Input */ +#define OFS_PJIN_L OFS_PJIN +#define OFS_PJIN_H OFS_PJIN+1 +#define OFS_PJOUT (0x0002) /* Port J Output */ +#define OFS_PJOUT_L OFS_PJOUT +#define OFS_PJOUT_H OFS_PJOUT+1 +#define OFS_PJDIR (0x0004) /* Port J Direction */ +#define OFS_PJDIR_L OFS_PJDIR +#define OFS_PJDIR_H OFS_PJDIR+1 +#define OFS_PJREN (0x0006) /* Port J Resistor Enable */ +#define OFS_PJREN_L OFS_PJREN +#define OFS_PJREN_H OFS_PJREN+1 +#define OFS_PJSEL0 (0x000A) /* Port J Selection 0 */ +#define OFS_PJSEL0_L OFS_PJSEL0 +#define OFS_PJSEL0_H OFS_PJSEL0+1 +#define OFS_PJSEL1 (0x000C) /* Port J Selection 1 */ +#define OFS_PJSEL1_L OFS_PJSEL1 +#define OFS_PJSEL1_H OFS_PJSEL1+1 +#define OFS_PJSELC (0x0016) /* Port J Complement Selection */ +#define OFS_PJSELC_L OFS_PJSELC +#define OFS_PJSELC_H OFS_PJSELC+1 + +#endif +/************************************************************* +* RAM Control Module for FRAM +*************************************************************/ +#ifdef __MSP430_HAS_RC_FRAM__ /* Definition to show that Module is available */ + +#define OFS_RCCTL0 (0x0000) /* Ram Controller Control Register */ +#define OFS_RCCTL0_L OFS_RCCTL0 +#define OFS_RCCTL0_H OFS_RCCTL0+1 + +/* RCCTL0 Control Bits */ +#define RCRS0OFF0 (0x0001) /* RAM Controller RAM Sector 0 Off Bit: 0 */ +#define RCRS0OFF1 (0x0002) /* RAM Controller RAM Sector 0 Off Bit: 1 */ +#define RCRS4OFF0 (0x0100) /* RAM Controller RAM Sector 4 Off Bit: 0 */ +#define RCRS4OFF1 (0x0200) /* RAM Controller RAM Sector 4 Off Bit: 1 */ +#define RCRS5OFF0 (0x0400) /* RAM Controller RAM Sector 5 Off Bit: 0 */ +#define RCRS5OFF1 (0x0800) /* RAM Controller RAM Sector 5 Off Bit: 1 */ +#define RCRS6OFF0 (0x1000) /* RAM Controller RAM Sector 6 Off Bit: 0 */ +#define RCRS6OFF1 (0x2000) /* RAM Controller RAM Sector 6 Off Bit: 1 */ +#define RCRS7OFF0 (0x4000) /* RAM Controller RAM Sector 7 (USB) Off Bit: 0 */ +#define RCRS7OFF1 (0x8000) /* RAM Controller RAM Sector 7 (USB) Off Bit: 1 */ + +/* RCCTL0 Control Bits */ +#define RCRS0OFF0_L (0x0001) /* RAM Controller RAM Sector 0 Off Bit: 0 */ +#define RCRS0OFF1_L (0x0002) /* RAM Controller RAM Sector 0 Off Bit: 1 */ + +/* RCCTL0 Control Bits */ +#define RCRS4OFF0_H (0x0001) /* RAM Controller RAM Sector 4 Off Bit: 0 */ +#define RCRS4OFF1_H (0x0002) /* RAM Controller RAM Sector 4 Off Bit: 1 */ +#define RCRS5OFF0_H (0x0004) /* RAM Controller RAM Sector 5 Off Bit: 0 */ +#define RCRS5OFF1_H (0x0008) /* RAM Controller RAM Sector 5 Off Bit: 1 */ +#define RCRS6OFF0_H (0x0010) /* RAM Controller RAM Sector 6 Off Bit: 0 */ +#define RCRS6OFF1_H (0x0020) /* RAM Controller RAM Sector 6 Off Bit: 1 */ +#define RCRS7OFF0_H (0x0040) /* RAM Controller RAM Sector 7 (USB) Off Bit: 0 */ +#define RCRS7OFF1_H (0x0080) /* RAM Controller RAM Sector 7 (USB) Off Bit: 1 */ + +#define RCKEY (0x5A00) + +#define RCRS0OFF_0 (0x0000) /* RAM Controller RAM Sector 0 Off : 0 */ +#define RCRS0OFF_1 (0x0001) /* RAM Controller RAM Sector 0 Off : 1 */ +#define RCRS0OFF_2 (0x0002) /* RAM Controller RAM Sector 0 Off : 2 */ +#define RCRS0OFF_3 (0x0003) /* RAM Controller RAM Sector 0 Off : 3 */ +#define RCRS4OFF_0 (0x0000) /* RAM Controller RAM Sector 4 Off : 0 */ +#define RCRS4OFF_2 (0x0100) /* RAM Controller RAM Sector 4 Off : 1 */ +#define RCRS4OFF_3 (0x0200) /* RAM Controller RAM Sector 4 Off : 2 */ +#define RCRS4OFF_4 (0x0300) /* RAM Controller RAM Sector 4 Off : 3 */ +#define RCRS5OFF_0 (0x0000) /* RAM Controller RAM Sector 5 Off : 0 */ +#define RCRS5OFF_1 (0x0400) /* RAM Controller RAM Sector 5 Off : 1 */ +#define RCRS5OFF_2 (0x0800) /* RAM Controller RAM Sector 5 Off : 2 */ +#define RCRS5OFF_3 (0x0C00) /* RAM Controller RAM Sector 5 Off : 3 */ +#define RCRS6OFF_0 (0x0000) /* RAM Controller RAM Sector 6 Off : 0 */ +#define RCRS6OFF_1 (0x0100) /* RAM Controller RAM Sector 6 Off : 1 */ +#define RCRS6OFF_2 (0x0200) /* RAM Controller RAM Sector 6 Off : 2 */ +#define RCRS6OFF_3 (0x0300) /* RAM Controller RAM Sector 6 Off : 3 */ +#define RCRS7OFF_0 (0x0000) /* RAM Controller RAM Sector 7 Off : 0 */ +#define RCRS7OFF_1 (0x4000) /* RAM Controller RAM Sector 7 Off : 1 */ +#define RCRS7OFF_2 (0x8000) /* RAM Controller RAM Sector 7 Off : 2*/ +#define RCRS7OFF_3 (0xC000) /* RAM Controller RAM Sector 7 Off : 3*/ + +#endif +/************************************************************ +* Shared Reference +************************************************************/ +#ifdef __MSP430_HAS_REF_A__ /* Definition to show that Module is available */ + +#define OFS_REFCTL0 (0x0000) /* REF Shared Reference control register 0 */ +#define OFS_REFCTL0_L OFS_REFCTL0 +#define OFS_REFCTL0_H OFS_REFCTL0+1 + +/* REFCTL0 Control Bits */ +#define REFON (0x0001) /* REF Reference On */ +#define REFOUT (0x0002) /* REF Reference output Buffer On */ +//#define RESERVED (0x0004) /* Reserved */ +#define REFTCOFF (0x0008) /* REF Temp.Sensor off */ +#define REFVSEL0 (0x0010) /* REF Reference Voltage Level Select Bit:0 */ +#define REFVSEL1 (0x0020) /* REF Reference Voltage Level Select Bit:1 */ +#define REFGENOT (0x0040) /* REF Reference generator one-time trigger */ +#define REFBGOT (0x0080) /* REF Bandgap and bandgap buffer one-time trigger */ +#define REFGENACT (0x0100) /* REF Reference generator active */ +#define REFBGACT (0x0200) /* REF Reference bandgap active */ +#define REFGENBUSY (0x0400) /* REF Reference generator busy */ +#define BGMODE (0x0800) /* REF Bandgap mode */ +#define REFGENRDY (0x1000) /* REF Reference generator ready */ +#define REFBGRDY (0x2000) /* REF Reference bandgap ready */ +//#define RESERVED (0x4000) /* Reserved */ +//#define RESERVED (0x8000) /* Reserved */ + +/* REFCTL0 Control Bits */ +#define REFON_L (0x0001) /* REF Reference On */ +#define REFOUT_L (0x0002) /* REF Reference output Buffer On */ +//#define RESERVED (0x0004) /* Reserved */ +#define REFTCOFF_L (0x0008) /* REF Temp.Sensor off */ +#define REFVSEL0_L (0x0010) /* REF Reference Voltage Level Select Bit:0 */ +#define REFVSEL1_L (0x0020) /* REF Reference Voltage Level Select Bit:1 */ +#define REFGENOT_L (0x0040) /* REF Reference generator one-time trigger */ +#define REFBGOT_L (0x0080) /* REF Bandgap and bandgap buffer one-time trigger */ +//#define RESERVED (0x4000) /* Reserved */ +//#define RESERVED (0x8000) /* Reserved */ + +/* REFCTL0 Control Bits */ +//#define RESERVED (0x0004) /* Reserved */ +#define REFGENACT_H (0x0001) /* REF Reference generator active */ +#define REFBGACT_H (0x0002) /* REF Reference bandgap active */ +#define REFGENBUSY_H (0x0004) /* REF Reference generator busy */ +#define BGMODE_H (0x0008) /* REF Bandgap mode */ +#define REFGENRDY_H (0x0010) /* REF Reference generator ready */ +#define REFBGRDY_H (0x0020) /* REF Reference bandgap ready */ +//#define RESERVED (0x4000) /* Reserved */ +//#define RESERVED (0x8000) /* Reserved */ + +#define REFVSEL_0 (0x0000) /* REF Reference Voltage Level Select 1.2V */ +#define REFVSEL_1 (0x0010) /* REF Reference Voltage Level Select 2.0V */ +#define REFVSEL_2 (0x0020) /* REF Reference Voltage Level Select 2.5V */ +#define REFVSEL_3 (0x0030) /* REF Reference Voltage Level Select 2.5V */ + +#endif +/************************************************************ +* Real Time Clock +************************************************************/ +#ifdef __MSP430_HAS_RTC_B__ /* Definition to show that Module is available */ + +#define OFS_RTCCTL01 (0x0000) /* Real Timer Control 0/1 */ +#define OFS_RTCCTL01_L OFS_RTCCTL01 +#define OFS_RTCCTL01_H OFS_RTCCTL01+1 +#define OFS_RTCCTL23 (0x0002) /* Real Timer Control 2/3 */ +#define OFS_RTCCTL23_L OFS_RTCCTL23 +#define OFS_RTCCTL23_H OFS_RTCCTL23+1 +#define OFS_RTCPS0CTL (0x0008) /* Real Timer Prescale Timer 0 Control */ +#define OFS_RTCPS0CTL_L OFS_RTCPS0CTL +#define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1 +#define OFS_RTCPS1CTL (0x000A) /* Real Timer Prescale Timer 1 Control */ +#define OFS_RTCPS1CTL_L OFS_RTCPS1CTL +#define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1 +#define OFS_RTCPS (0x000C) /* Real Timer Prescale Timer Control */ +#define OFS_RTCPS_L OFS_RTCPS +#define OFS_RTCPS_H OFS_RTCPS+1 +#define OFS_RTCIV (0x000E) /* Real Time Clock Interrupt Vector */ +#define OFS_RTCTIM0 (0x0010) /* Real Time Clock Time 0 */ +#define OFS_RTCTIM0_L OFS_RTCTIM0 +#define OFS_RTCTIM0_H OFS_RTCTIM0+1 +#define OFS_RTCTIM1 (0x0012) /* Real Time Clock Time 1 */ +#define OFS_RTCTIM1_L OFS_RTCTIM1 +#define OFS_RTCTIM1_H OFS_RTCTIM1+1 +#define OFS_RTCDATE (0x0014) /* Real Time Clock Date */ +#define OFS_RTCDATE_L OFS_RTCDATE +#define OFS_RTCDATE_H OFS_RTCDATE+1 +#define OFS_RTCYEAR (0x0016) /* Real Time Clock Year */ +#define OFS_RTCYEAR_L OFS_RTCYEAR +#define OFS_RTCYEAR_H OFS_RTCYEAR+1 +#define OFS_RTCAMINHR (0x0018) /* Real Time Clock Alarm Min/Hour */ +#define OFS_RTCAMINHR_L OFS_RTCAMINHR +#define OFS_RTCAMINHR_H OFS_RTCAMINHR+1 +#define OFS_RTCADOWDAY (0x001A) /* Real Time Clock Alarm day of week/day */ +#define OFS_RTCADOWDAY_L OFS_RTCADOWDAY +#define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1 +#define OFS_BIN2BCD (0x001C) /* Real Time Binary-to-BCD conversion register */ +#define OFS_BCD2BIN (0x001E) /* Real Time BCD-to-binary conversion register */ +#define OFS_RTCSEC (0x0010) +#define OFS_RTCMIN (0x0011) +#define OFS_RTCHOUR (0x0012) +#define OFS_RTCDOW (0x0013) +#define OFS_RTCDAY (0x0014) +#define OFS_RTCMON (0x0015) +#define OFS_RTCAMIN (0x0018) +#define OFS_RTCAHOUR (0x0019) +#define OFS_RTCADOW (0x001A) +#define OFS_RTCADAY (0x001B) + +#define RTCCTL0 RTCCTL01_L /* Real Time Clock Control 0 */ +#define RTCCTL1 RTCCTL01_H /* Real Time Clock Control 1 */ +#define RTCCTL2 RTCCTL23_L /* Real Time Clock Control 2 */ +#define RTCCTL3 RTCCTL23_H /* Real Time Clock Control 3 */ +#define RTCNT12 RTCTIM0 +#define RTCNT34 RTCTIM1 +#define RTCNT1 RTCTIM0_L +#define RTCNT2 RTCTIM0_H +#define RTCNT3 RTCTIM1_L +#define RTCNT4 RTCTIM1_H +#define RTCSEC RTCTIM0_L +#define RTCMIN RTCTIM0_H +#define RTCHOUR RTCTIM1_L +#define RTCDOW RTCTIM1_H +#define RTCDAY RTCDATE_L +#define RTCMON RTCDATE_H +#define RTCYEARL RTCYEAR_L +#define RTCYEARH RTCYEAR_H +#define RT0PS RTCPS_L +#define RT1PS RTCPS_H +#define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */ +#define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */ +#define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */ +#define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */ + +/* RTCCTL01 Control Bits */ +#define RTCBCD (0x8000) /* RTC BCD 0:Binary / 1:BCD */ +#define RTCHOLD (0x4000) /* RTC Hold */ +//#define RESERVED (0x2000) /* RESERVED */ +#define RTCRDY (0x1000) /* RTC Ready */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +#define RTCTEV1 (0x0200) /* RTC Time Event 1 */ +#define RTCTEV0 (0x0100) /* RTC Time Event 0 */ +#define RTCOFIE (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */ +#define RTCTEVIE (0x0040) /* RTC Time Event Interrupt Enable Flag */ +#define RTCAIE (0x0020) /* RTC Alarm Interrupt Enable Flag */ +#define RTCRDYIE (0x0010) /* RTC Ready Interrupt Enable Flag */ +#define RTCOFIFG (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */ +#define RTCTEVIFG (0x0004) /* RTC Time Event Interrupt Flag */ +#define RTCAIFG (0x0002) /* RTC Alarm Interrupt Flag */ +#define RTCRDYIFG (0x0001) /* RTC Ready Interrupt Flag */ + +/* RTCCTL01 Control Bits */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +#define RTCOFIE_L (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */ +#define RTCTEVIE_L (0x0040) /* RTC Time Event Interrupt Enable Flag */ +#define RTCAIE_L (0x0020) /* RTC Alarm Interrupt Enable Flag */ +#define RTCRDYIE_L (0x0010) /* RTC Ready Interrupt Enable Flag */ +#define RTCOFIFG_L (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */ +#define RTCTEVIFG_L (0x0004) /* RTC Time Event Interrupt Flag */ +#define RTCAIFG_L (0x0002) /* RTC Alarm Interrupt Flag */ +#define RTCRDYIFG_L (0x0001) /* RTC Ready Interrupt Flag */ + +/* RTCCTL01 Control Bits */ +#define RTCBCD_H (0x0080) /* RTC BCD 0:Binary / 1:BCD */ +#define RTCHOLD_H (0x0040) /* RTC Hold */ +//#define RESERVED (0x2000) /* RESERVED */ +#define RTCRDY_H (0x0010) /* RTC Ready */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +#define RTCTEV1_H (0x0002) /* RTC Time Event 1 */ +#define RTCTEV0_H (0x0001) /* RTC Time Event 0 */ + +#define RTCTEV_0 (0x0000) /* RTC Time Event: 0 (Min. changed) */ +#define RTCTEV_1 (0x0100) /* RTC Time Event: 1 (Hour changed) */ +#define RTCTEV_2 (0x0200) /* RTC Time Event: 2 (12:00 changed) */ +#define RTCTEV_3 (0x0300) /* RTC Time Event: 3 (00:00 changed) */ +#define RTCTEV__MIN (0x0000) /* RTC Time Event: 0 (Min. changed) */ +#define RTCTEV__HOUR (0x0100) /* RTC Time Event: 1 (Hour changed) */ +#define RTCTEV__0000 (0x0200) /* RTC Time Event: 2 (00:00 changed) */ +#define RTCTEV__1200 (0x0300) /* RTC Time Event: 3 (12:00 changed) */ + +/* RTCCTL23 Control Bits */ +#define RTCCALF1 (0x0200) /* RTC Calibration Frequency Bit 1 */ +#define RTCCALF0 (0x0100) /* RTC Calibration Frequency Bit 0 */ +#define RTCCALS (0x0080) /* RTC Calibration Sign */ +//#define Reserved (0x0040) +#define RTCCAL5 (0x0020) /* RTC Calibration Bit 5 */ +#define RTCCAL4 (0x0010) /* RTC Calibration Bit 4 */ +#define RTCCAL3 (0x0008) /* RTC Calibration Bit 3 */ +#define RTCCAL2 (0x0004) /* RTC Calibration Bit 2 */ +#define RTCCAL1 (0x0002) /* RTC Calibration Bit 1 */ +#define RTCCAL0 (0x0001) /* RTC Calibration Bit 0 */ + +/* RTCCTL23 Control Bits */ +#define RTCCALS_L (0x0080) /* RTC Calibration Sign */ +//#define Reserved (0x0040) +#define RTCCAL5_L (0x0020) /* RTC Calibration Bit 5 */ +#define RTCCAL4_L (0x0010) /* RTC Calibration Bit 4 */ +#define RTCCAL3_L (0x0008) /* RTC Calibration Bit 3 */ +#define RTCCAL2_L (0x0004) /* RTC Calibration Bit 2 */ +#define RTCCAL1_L (0x0002) /* RTC Calibration Bit 1 */ +#define RTCCAL0_L (0x0001) /* RTC Calibration Bit 0 */ + +/* RTCCTL23 Control Bits */ +#define RTCCALF1_H (0x0002) /* RTC Calibration Frequency Bit 1 */ +#define RTCCALF0_H (0x0001) /* RTC Calibration Frequency Bit 0 */ +//#define Reserved (0x0040) + +#define RTCCALF_0 (0x0000) /* RTC Calibration Frequency: No Output */ +#define RTCCALF_1 (0x0100) /* RTC Calibration Frequency: 512 Hz */ +#define RTCCALF_2 (0x0200) /* RTC Calibration Frequency: 256 Hz */ +#define RTCCALF_3 (0x0300) /* RTC Calibration Frequency: 1 Hz */ + +#define RTCAE (0x80) /* Real Time Clock Alarm enable */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT0IP2 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ +#define RT0IP1 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ +#define RT0IP0 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ +#define RT0PSIE (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */ +#define RT0PSIFG (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT0IP2_L (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ +#define RT0IP1_L (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ +#define RT0IP0_L (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ +#define RT0PSIE_L (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */ +#define RT0PSIFG_L (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */ + +#define RT0IP_0 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */ +#define RT0IP_1 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */ +#define RT0IP_2 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */ +#define RT0IP_3 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */ +#define RT0IP_4 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */ +#define RT0IP_5 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */ +#define RT0IP_6 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */ +#define RT0IP_7 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */ + +#define RT0IP__2 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */ +#define RT0IP__4 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */ +#define RT0IP__8 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */ +#define RT0IP__16 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */ +#define RT0IP__32 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */ +#define RT0IP__64 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */ +#define RT0IP__128 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */ +#define RT0IP__256 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */ + +/* RTCPS1CTL Control Bits */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT1IP2 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ +#define RT1IP1 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ +#define RT1IP0 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ +#define RT1PSIE (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */ +#define RT1PSIFG (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */ + +/* RTCPS1CTL Control Bits */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT1IP2_L (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ +#define RT1IP1_L (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ +#define RT1IP0_L (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ +#define RT1PSIE_L (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */ +#define RT1PSIFG_L (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */ + +#define RT1IP_0 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */ +#define RT1IP_1 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */ +#define RT1IP_2 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */ +#define RT1IP_3 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */ +#define RT1IP_4 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */ +#define RT1IP_5 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */ +#define RT1IP_6 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */ +#define RT1IP_7 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */ + +#define RT1IP__2 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */ +#define RT1IP__4 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */ +#define RT1IP__8 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */ +#define RT1IP__16 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */ +#define RT1IP__32 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */ +#define RT1IP__64 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */ +#define RT1IP__128 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */ +#define RT1IP__256 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */ + +/* RTC Definitions */ +#define RTCIV_NONE (0x0000) /* No Interrupt pending */ +#define RTCIV_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */ +#define RTCIV_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */ +#define RTCIV_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */ +#define RTCIV_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */ +#define RTCIV_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */ +#define RTCIV_RTCOFIFG (0x000C) /* RTC Oscillator fault */ + +/* Legacy Definitions */ +#define RTC_NONE (0x0000) /* No Interrupt pending */ +#define RTC_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */ +#define RTC_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */ +#define RTC_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */ +#define RTC_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */ +#define RTC_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */ +#define RTC_RTCOFIFG (0x000C) /* RTC Oscillator fault */ + +#endif +/************************************************************ +* Real Time Clock +************************************************************/ +#ifdef __MSP430_HAS_RTC_C__ /* Definition to show that Module is available */ + +#define OFS_RTCCTL0 (0x0000) /* Real Timer Clock Control 0/Key */ +#define OFS_RTCCTL0_L OFS_RTCCTL0 +#define OFS_RTCCTL0_H OFS_RTCCTL0+1 +#define OFS_RTCCTL13 (0x0002) /* Real Timer Clock Control 1/3 */ +#define OFS_RTCCTL13_L OFS_RTCCTL13 +#define OFS_RTCCTL13_H OFS_RTCCTL13+1 +#define RTCCTL1 RTCCTL13_L +#define RTCCTL3 RTCCTL13_H +#define OFS_RTCOCAL (0x0004) /* Real Timer Clock Offset Calibartion */ +#define OFS_RTCOCAL_L OFS_RTCOCAL +#define OFS_RTCOCAL_H OFS_RTCOCAL+1 +#define OFS_RTCTCMP (0x0006) /* Real Timer Temperature Compensation */ +#define OFS_RTCTCMP_L OFS_RTCTCMP +#define OFS_RTCTCMP_H OFS_RTCTCMP+1 +#define OFS_RTCPS0CTL (0x0008) /* Real Timer Prescale Timer 0 Control */ +#define OFS_RTCPS0CTL_L OFS_RTCPS0CTL +#define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1 +#define OFS_RTCPS1CTL (0x000A) /* Real Timer Prescale Timer 1 Control */ +#define OFS_RTCPS1CTL_L OFS_RTCPS1CTL +#define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1 +#define OFS_RTCPS (0x000C) /* Real Timer Prescale Timer Control */ +#define OFS_RTCPS_L OFS_RTCPS +#define OFS_RTCPS_H OFS_RTCPS+1 +#define OFS_RTCIV (0x000E) /* Real Time Clock Interrupt Vector */ +#define OFS_RTCTIM0 (0x0010) /* Real Time Clock Time 0 */ +#define OFS_RTCTIM0_L OFS_RTCTIM0 +#define OFS_RTCTIM0_H OFS_RTCTIM0+1 +#define OFS_RTCTIM1 (0x0012) /* Real Time Clock Time 1 */ +#define OFS_RTCTIM1_L OFS_RTCTIM1 +#define OFS_RTCTIM1_H OFS_RTCTIM1+1 +#define OFS_RTCDATE (0x0014) /* Real Time Clock Date */ +#define OFS_RTCDATE_L OFS_RTCDATE +#define OFS_RTCDATE_H OFS_RTCDATE+1 +#define OFS_RTCYEAR (0x0016) /* Real Time Clock Year */ +#define OFS_RTCYEAR_L OFS_RTCYEAR +#define OFS_RTCYEAR_H OFS_RTCYEAR+1 +#define OFS_RTCAMINHR (0x0018) /* Real Time Clock Alarm Min/Hour */ +#define OFS_RTCAMINHR_L OFS_RTCAMINHR +#define OFS_RTCAMINHR_H OFS_RTCAMINHR+1 +#define OFS_RTCADOWDAY (0x001A) /* Real Time Clock Alarm day of week/day */ +#define OFS_RTCADOWDAY_L OFS_RTCADOWDAY +#define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1 +#define OFS_BIN2BCD (0x001C) /* Real Time Binary-to-BCD conversion register */ +#define OFS_BCD2BIN (0x001E) /* Real Time BCD-to-binary conversion register */ +#define OFS_RTCSEC (0x0010) +#define OFS_RTCMIN (0x0011) +#define OFS_RTCHOUR (0x0012) +#define OFS_RTCDOW (0x0013) +#define OFS_RTCDAY (0x0014) +#define OFS_RTCMON (0x0015) +#define OFS_RTCAMIN (0x0018) +#define OFS_RTCAHOUR (0x0019) +#define OFS_RTCADOW (0x001A) +#define OFS_RTCADAY (0x001B) + +#define RTCSEC RTCTIM0_L +#define RTCMIN RTCTIM0_H +#define RTCHOUR RTCTIM1_L +#define RTCDOW RTCTIM1_H +#define RTCDAY RTCDATE_L +#define RTCMON RTCDATE_H +#define RTCYEARL RTCYEAR_L +#define RT0PS RTCPS_L +#define RT1PS RTCPS_H +#define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */ +#define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */ +#define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */ +#define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */ + +/* RTCCTL0 Control Bits */ +#define RTCOFIE (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */ +#define RTCTEVIE (0x0040) /* RTC Time Event Interrupt Enable Flag */ +#define RTCAIE (0x0020) /* RTC Alarm Interrupt Enable Flag */ +#define RTCRDYIE (0x0010) /* RTC Ready Interrupt Enable Flag */ +#define RTCOFIFG (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */ +#define RTCTEVIFG (0x0004) /* RTC Time Event Interrupt Flag */ +#define RTCAIFG (0x0002) /* RTC Alarm Interrupt Flag */ +#define RTCRDYIFG (0x0001) /* RTC Ready Interrupt Flag */ + +/* RTCCTL0 Control Bits */ +#define RTCOFIE_L (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */ +#define RTCTEVIE_L (0x0040) /* RTC Time Event Interrupt Enable Flag */ +#define RTCAIE_L (0x0020) /* RTC Alarm Interrupt Enable Flag */ +#define RTCRDYIE_L (0x0010) /* RTC Ready Interrupt Enable Flag */ +#define RTCOFIFG_L (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */ +#define RTCTEVIFG_L (0x0004) /* RTC Time Event Interrupt Flag */ +#define RTCAIFG_L (0x0002) /* RTC Alarm Interrupt Flag */ +#define RTCRDYIFG_L (0x0001) /* RTC Ready Interrupt Flag */ + +#define RTCKEY (0xA500) /* RTC Key for RTC write access */ +#define RTCKEY_H (0xA5) /* RTC Key for RTC write access (high word) */ + +/* RTCCTL13 Control Bits */ +#define RTCCALF1 (0x0200) /* RTC Calibration Frequency Bit 1 */ +#define RTCCALF0 (0x0100) /* RTC Calibration Frequency Bit 0 */ +#define RTCBCD (0x0080) /* RTC BCD 0:Binary / 1:BCD */ +#define RTCHOLD (0x0040) /* RTC Hold */ +#define RTCMODE (0x0020) /* RTC Mode 0:Counter / 1: Calendar */ +#define RTCRDY (0x0010) /* RTC Ready */ +#define RTCSSEL1 (0x0008) /* RTC Source Select 1 */ +#define RTCSSEL0 (0x0004) /* RTC Source Select 0 */ +#define RTCTEV1 (0x0002) /* RTC Time Event 1 */ +#define RTCTEV0 (0x0001) /* RTC Time Event 0 */ + +/* RTCCTL13 Control Bits */ +#define RTCBCD_L (0x0080) /* RTC BCD 0:Binary / 1:BCD */ +#define RTCHOLD_L (0x0040) /* RTC Hold */ +#define RTCMODE_L (0x0020) /* RTC Mode 0:Counter / 1: Calendar */ +#define RTCRDY_L (0x0010) /* RTC Ready */ +#define RTCSSEL1_L (0x0008) /* RTC Source Select 1 */ +#define RTCSSEL0_L (0x0004) /* RTC Source Select 0 */ +#define RTCTEV1_L (0x0002) /* RTC Time Event 1 */ +#define RTCTEV0_L (0x0001) /* RTC Time Event 0 */ + +/* RTCCTL13 Control Bits */ +#define RTCCALF1_H (0x0002) /* RTC Calibration Frequency Bit 1 */ +#define RTCCALF0_H (0x0001) /* RTC Calibration Frequency Bit 0 */ + +#define RTCSSEL_0 (0x0000) /* RTC Source Select ACLK */ +#define RTCSSEL_1 (0x0004) /* RTC Source Select SMCLK */ +#define RTCSSEL_2 (0x0008) /* RTC Source Select RT1PS */ +#define RTCSSEL_3 (0x000C) /* RTC Source Select RT1PS */ +#define RTCSSEL__ACLK (0x0000) /* RTC Source Select ACLK */ +#define RTCSSEL__SMCLK (0x0004) /* RTC Source Select SMCLK */ +#define RTCSSEL__RT1PS (0x0008) /* RTC Source Select RT1PS */ + +#define RTCTEV_0 (0x0000) /* RTC Time Event: 0 (Min. changed) */ +#define RTCTEV_1 (0x0001) /* RTC Time Event: 1 (Hour changed) */ +#define RTCTEV_2 (0x0002) /* RTC Time Event: 2 (12:00 changed) */ +#define RTCTEV_3 (0x0003) /* RTC Time Event: 3 (00:00 changed) */ +#define RTCTEV__MIN (0x0000) /* RTC Time Event: 0 (Min. changed) */ +#define RTCTEV__HOUR (0x0001) /* RTC Time Event: 1 (Hour changed) */ +#define RTCTEV__0000 (0x0002) /* RTC Time Event: 2 (00:00 changed) */ +#define RTCTEV__1200 (0x0003) /* RTC Time Event: 3 (12:00 changed) */ + +#define RTCCALF_0 (0x0000) /* RTC Calibration Frequency: No Output */ +#define RTCCALF_1 (0x0100) /* RTC Calibration Frequency: 512 Hz */ +#define RTCCALF_2 (0x0200) /* RTC Calibration Frequency: 256 Hz */ +#define RTCCALF_3 (0x0300) /* RTC Calibration Frequency: 1 Hz */ + +/* RTCOCAL Control Bits */ +#define RTCOCALS (0x8000) /* RTC Offset Calibration Sign */ +#define RTCOCAL7 (0x0080) /* RTC Offset Calibration Bit 7 */ +#define RTCOCAL6 (0x0040) /* RTC Offset Calibration Bit 6 */ +#define RTCOCAL5 (0x0020) /* RTC Offset Calibration Bit 5 */ +#define RTCOCAL4 (0x0010) /* RTC Offset Calibration Bit 4 */ +#define RTCOCAL3 (0x0008) /* RTC Offset Calibration Bit 3 */ +#define RTCOCAL2 (0x0004) /* RTC Offset Calibration Bit 2 */ +#define RTCOCAL1 (0x0002) /* RTC Offset Calibration Bit 1 */ +#define RTCOCAL0 (0x0001) /* RTC Offset Calibration Bit 0 */ + +/* RTCOCAL Control Bits */ +#define RTCOCAL7_L (0x0080) /* RTC Offset Calibration Bit 7 */ +#define RTCOCAL6_L (0x0040) /* RTC Offset Calibration Bit 6 */ +#define RTCOCAL5_L (0x0020) /* RTC Offset Calibration Bit 5 */ +#define RTCOCAL4_L (0x0010) /* RTC Offset Calibration Bit 4 */ +#define RTCOCAL3_L (0x0008) /* RTC Offset Calibration Bit 3 */ +#define RTCOCAL2_L (0x0004) /* RTC Offset Calibration Bit 2 */ +#define RTCOCAL1_L (0x0002) /* RTC Offset Calibration Bit 1 */ +#define RTCOCAL0_L (0x0001) /* RTC Offset Calibration Bit 0 */ + +/* RTCOCAL Control Bits */ +#define RTCOCALS_H (0x0080) /* RTC Offset Calibration Sign */ + +/* RTCTCMP Control Bits */ +#define RTCTCMPS (0x8000) /* RTC Temperature Compensation Sign */ +#define RTCTCRDY (0x4000) /* RTC Temperature compensation ready */ +#define RTCTCOK (0x2000) /* RTC Temperature compensation write OK */ +#define RTCTCMP7 (0x0080) /* RTC Temperature Compensation Bit 7 */ +#define RTCTCMP6 (0x0040) /* RTC Temperature Compensation Bit 6 */ +#define RTCTCMP5 (0x0020) /* RTC Temperature Compensation Bit 5 */ +#define RTCTCMP4 (0x0010) /* RTC Temperature Compensation Bit 4 */ +#define RTCTCMP3 (0x0008) /* RTC Temperature Compensation Bit 3 */ +#define RTCTCMP2 (0x0004) /* RTC Temperature Compensation Bit 2 */ +#define RTCTCMP1 (0x0002) /* RTC Temperature Compensation Bit 1 */ +#define RTCTCMP0 (0x0001) /* RTC Temperature Compensation Bit 0 */ + +/* RTCTCMP Control Bits */ +#define RTCTCMP7_L (0x0080) /* RTC Temperature Compensation Bit 7 */ +#define RTCTCMP6_L (0x0040) /* RTC Temperature Compensation Bit 6 */ +#define RTCTCMP5_L (0x0020) /* RTC Temperature Compensation Bit 5 */ +#define RTCTCMP4_L (0x0010) /* RTC Temperature Compensation Bit 4 */ +#define RTCTCMP3_L (0x0008) /* RTC Temperature Compensation Bit 3 */ +#define RTCTCMP2_L (0x0004) /* RTC Temperature Compensation Bit 2 */ +#define RTCTCMP1_L (0x0002) /* RTC Temperature Compensation Bit 1 */ +#define RTCTCMP0_L (0x0001) /* RTC Temperature Compensation Bit 0 */ + +/* RTCTCMP Control Bits */ +#define RTCTCMPS_H (0x0080) /* RTC Temperature Compensation Sign */ +#define RTCTCRDY_H (0x0040) /* RTC Temperature compensation ready */ +#define RTCTCOK_H (0x0020) /* RTC Temperature compensation write OK */ + +#define RTCAE (0x80) /* Real Time Clock Alarm enable */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x8000) +//#define Reserved (0x4000) +#define RT0PSDIV2 (0x2000) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */ +#define RT0PSDIV1 (0x1000) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */ +#define RT0PSDIV0 (0x0800) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +#define RT0PSHOLD (0x0100) /* RTC Prescale Timer 0 Hold */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT0IP2 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ +#define RT0IP1 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ +#define RT0IP0 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ +#define RT0PSIE (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */ +#define RT0PSIFG (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x8000) +//#define Reserved (0x4000) +//#define Reserved (0x0400) +//#define Reserved (0x0200) +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT0IP2_L (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ +#define RT0IP1_L (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ +#define RT0IP0_L (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ +#define RT0PSIE_L (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */ +#define RT0PSIFG_L (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x8000) +//#define Reserved (0x4000) +#define RT0PSDIV2_H (0x0020) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */ +#define RT0PSDIV1_H (0x0010) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */ +#define RT0PSDIV0_H (0x0008) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +#define RT0PSHOLD_H (0x0001) /* RTC Prescale Timer 0 Hold */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) + +#define RT0IP_0 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */ +#define RT0IP_1 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */ +#define RT0IP_2 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */ +#define RT0IP_3 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */ +#define RT0IP_4 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */ +#define RT0IP_5 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */ +#define RT0IP_6 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */ +#define RT0IP_7 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */ + +/* RTCPS1CTL Control Bits */ +#define RT1SSEL1 (0x8000) /* RTC Prescale Timer 1 Source Select Bit 1 */ +#define RT1SSEL0 (0x4000) /* RTC Prescale Timer 1 Source Select Bit 0 */ +#define RT1PSDIV2 (0x2000) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */ +#define RT1PSDIV1 (0x1000) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */ +#define RT1PSDIV0 (0x0800) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +#define RT1PSHOLD (0x0100) /* RTC Prescale Timer 1 Hold */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT1IP2 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ +#define RT1IP1 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ +#define RT1IP0 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ +#define RT1PSIE (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */ +#define RT1PSIFG (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */ + +/* RTCPS1CTL Control Bits */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT1IP2_L (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ +#define RT1IP1_L (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ +#define RT1IP0_L (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ +#define RT1PSIE_L (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */ +#define RT1PSIFG_L (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */ + +/* RTCPS1CTL Control Bits */ +#define RT1SSEL1_H (0x0080) /* RTC Prescale Timer 1 Source Select Bit 1 */ +#define RT1SSEL0_H (0x0040) /* RTC Prescale Timer 1 Source Select Bit 0 */ +#define RT1PSDIV2_H (0x0020) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */ +#define RT1PSDIV1_H (0x0010) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */ +#define RT1PSDIV0_H (0x0008) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +#define RT1PSHOLD_H (0x0001) /* RTC Prescale Timer 1 Hold */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) + +#define RT1IP_0 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */ +#define RT1IP_1 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */ +#define RT1IP_2 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */ +#define RT1IP_3 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */ +#define RT1IP_4 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */ +#define RT1IP_5 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */ +#define RT1IP_6 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */ +#define RT1IP_7 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */ + +/* RTC Definitions */ +#define RTCIV_NONE (0x0000) /* No Interrupt pending */ +#define RTCIV_RTCOFIFG (0x0002) /* RTC Osc fault: RTCOFIFG */ +#define RTCIV_RTCRDYIFG (0x0004) /* RTC ready: RTCRDYIFG */ +#define RTCIV_RTCTEVIFG (0x0006) /* RTC interval timer: RTCTEVIFG */ +#define RTCIV_RTCAIFG (0x0008) /* RTC user alarm: RTCAIFG */ +#define RTCIV_RT0PSIFG (0x000A) /* RTC prescaler 0: RT0PSIFG */ +#define RTCIV_RT1PSIFG (0x000C) /* RTC prescaler 1: RT1PSIFG */ + +/* Legacy Definitions */ +#define RTC_NONE (0x0000) /* No Interrupt pending */ +#define RTC_RTCOFIFG (0x0002) /* RTC Osc fault: RTCOFIFG */ +#define RTC_RTCRDYIFG (0x0004) /* RTC ready: RTCRDYIFG */ +#define RTC_RTCTEVIFG (0x0006) /* RTC interval timer: RTCTEVIFG */ +#define RTC_RTCAIFG (0x0008) /* RTC user alarm: RTCAIFG */ +#define RTC_RT0PSIFG (0x000A) /* RTC prescaler 0: RT0PSIFG */ +#define RTC_RT1PSIFG (0x000C) /* RTC prescaler 1: RT1PSIFG */ + +#endif +/************************************************************ +* SFR - Special Function Register Module +************************************************************/ +#ifdef __MSP430_HAS_SFR__ /* Definition to show that Module is available */ + +#define OFS_SFRIE1 (0x0000) /* Interrupt Enable 1 */ +#define OFS_SFRIE1_L OFS_SFRIE1 +#define OFS_SFRIE1_H OFS_SFRIE1+1 + +/* SFRIE1 Control Bits */ +#define WDTIE (0x0001) /* WDT Interrupt Enable */ +#define OFIE (0x0002) /* Osc Fault Enable */ +//#define Reserved (0x0004) +#define VMAIE (0x0008) /* Vacant Memory Interrupt Enable */ +#define NMIIE (0x0010) /* NMI Interrupt Enable */ +#define JMBINIE (0x0040) /* JTAG Mail Box input Interrupt Enable */ +#define JMBOUTIE (0x0080) /* JTAG Mail Box output Interrupt Enable */ + +#define WDTIE_L (0x0001) /* WDT Interrupt Enable */ +#define OFIE_L (0x0002) /* Osc Fault Enable */ +//#define Reserved (0x0004) +#define VMAIE_L (0x0008) /* Vacant Memory Interrupt Enable */ +#define NMIIE_L (0x0010) /* NMI Interrupt Enable */ +#define JMBINIE_L (0x0040) /* JTAG Mail Box input Interrupt Enable */ +#define JMBOUTIE_L (0x0080) /* JTAG Mail Box output Interrupt Enable */ + +#define OFS_SFRIFG1 (0x0002) /* Interrupt Flag 1 */ +#define OFS_SFRIFG1_L OFS_SFRIFG1 +#define OFS_SFRIFG1_H OFS_SFRIFG1+1 +/* SFRIFG1 Control Bits */ +#define WDTIFG (0x0001) /* WDT Interrupt Flag */ +#define OFIFG (0x0002) /* Osc Fault Flag */ +//#define Reserved (0x0004) +#define VMAIFG (0x0008) /* Vacant Memory Interrupt Flag */ +#define NMIIFG (0x0010) /* NMI Interrupt Flag */ +//#define Reserved (0x0020) +#define JMBINIFG (0x0040) /* JTAG Mail Box input Interrupt Flag */ +#define JMBOUTIFG (0x0080) /* JTAG Mail Box output Interrupt Flag */ + +#define WDTIFG_L (0x0001) /* WDT Interrupt Flag */ +#define OFIFG_L (0x0002) /* Osc Fault Flag */ +//#define Reserved (0x0004) +#define VMAIFG_L (0x0008) /* Vacant Memory Interrupt Flag */ +#define NMIIFG_L (0x0010) /* NMI Interrupt Flag */ +//#define Reserved (0x0020) +#define JMBINIFG_L (0x0040) /* JTAG Mail Box input Interrupt Flag */ +#define JMBOUTIFG_L (0x0080) /* JTAG Mail Box output Interrupt Flag */ + +#define OFS_SFRRPCR (0x0004) /* RESET Pin Control Register */ +#define OFS_SFRRPCR_L OFS_SFRRPCR +#define OFS_SFRRPCR_H OFS_SFRRPCR+1 +/* SFRRPCR Control Bits */ +#define SYSNMI (0x0001) /* NMI select */ +#define SYSNMIIES (0x0002) /* NMI edge select */ +#define SYSRSTUP (0x0004) /* RESET Pin pull down/up select */ +#define SYSRSTRE (0x0008) /* RESET Pin Resistor enable */ + +#define SYSNMI_L (0x0001) /* NMI select */ +#define SYSNMIIES_L (0x0002) /* NMI edge select */ +#define SYSRSTUP_L (0x0004) /* RESET Pin pull down/up select */ +#define SYSRSTRE_L (0x0008) /* RESET Pin Resistor enable */ + +#endif +/************************************************************ +* SYS - System Module +************************************************************/ +#ifdef __MSP430_HAS_SYS__ /* Definition to show that Module is available */ + +#define OFS_SYSCTL (0x0000) /* System control */ +#define OFS_SYSCTL_L OFS_SYSCTL +#define OFS_SYSCTL_H OFS_SYSCTL+1 +#define OFS_SYSBSLC (0x0002) /* Boot strap configuration area */ +#define OFS_SYSBSLC_L OFS_SYSBSLC +#define OFS_SYSBSLC_H OFS_SYSBSLC+1 +#define OFS_SYSJMBC (0x0006) /* JTAG mailbox control */ +#define OFS_SYSJMBC_L OFS_SYSJMBC +#define OFS_SYSJMBC_H OFS_SYSJMBC+1 +#define OFS_SYSJMBI0 (0x0008) /* JTAG mailbox input 0 */ +#define OFS_SYSJMBI0_L OFS_SYSJMBI0 +#define OFS_SYSJMBI0_H OFS_SYSJMBI0+1 +#define OFS_SYSJMBI1 (0x000A) /* JTAG mailbox input 1 */ +#define OFS_SYSJMBI1_L OFS_SYSJMBI1 +#define OFS_SYSJMBI1_H OFS_SYSJMBI1+1 +#define OFS_SYSJMBO0 (0x000C) /* JTAG mailbox output 0 */ +#define OFS_SYSJMBO0_L OFS_SYSJMBO0 +#define OFS_SYSJMBO0_H OFS_SYSJMBO0+1 +#define OFS_SYSJMBO1 (0x000E) /* JTAG mailbox output 1 */ +#define OFS_SYSJMBO1_L OFS_SYSJMBO1 +#define OFS_SYSJMBO1_H OFS_SYSJMBO1+1 + +#define OFS_SYSBERRIV (0x0018) /* Bus Error vector generator */ +#define OFS_SYSBERRIV_L OFS_SYSBERRIV +#define OFS_SYSBERRIV_H OFS_SYSBERRIV+1 +#define OFS_SYSUNIV (0x001A) /* User NMI vector generator */ +#define OFS_SYSUNIV_L OFS_SYSUNIV +#define OFS_SYSUNIV_H OFS_SYSUNIV+1 +#define OFS_SYSSNIV (0x001C) /* System NMI vector generator */ +#define OFS_SYSSNIV_L OFS_SYSSNIV +#define OFS_SYSSNIV_H OFS_SYSSNIV+1 +#define OFS_SYSRSTIV (0x001E) /* Reset vector generator */ +#define OFS_SYSRSTIV_L OFS_SYSRSTIV +#define OFS_SYSRSTIV_H OFS_SYSRSTIV+1 + +/* SYSCTL Control Bits */ +#define SYSRIVECT (0x0001) /* SYS - RAM based interrupt vectors */ +//#define RESERVED (0x0002) /* SYS - Reserved */ +#define SYSPMMPE (0x0004) /* SYS - PMM access protect */ +//#define RESERVED (0x0008) /* SYS - Reserved */ +#define SYSBSLIND (0x0010) /* SYS - TCK/RST indication detected */ +#define SYSJTAGPIN (0x0020) /* SYS - Dedicated JTAG pins enabled */ +//#define RESERVED (0x0040) /* SYS - Reserved */ +//#define RESERVED (0x0080) /* SYS - Reserved */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ +//#define RESERVED (0x4000) /* SYS - Reserved */ +//#define RESERVED (0x8000) /* SYS - Reserved */ + +/* SYSCTL Control Bits */ +#define SYSRIVECT_L (0x0001) /* SYS - RAM based interrupt vectors */ +//#define RESERVED (0x0002) /* SYS - Reserved */ +#define SYSPMMPE_L (0x0004) /* SYS - PMM access protect */ +//#define RESERVED (0x0008) /* SYS - Reserved */ +#define SYSBSLIND_L (0x0010) /* SYS - TCK/RST indication detected */ +#define SYSJTAGPIN_L (0x0020) /* SYS - Dedicated JTAG pins enabled */ +//#define RESERVED (0x0040) /* SYS - Reserved */ +//#define RESERVED (0x0080) /* SYS - Reserved */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ +//#define RESERVED (0x4000) /* SYS - Reserved */ +//#define RESERVED (0x8000) /* SYS - Reserved */ + +/* SYSBSLC Control Bits */ +#define SYSBSLSIZE0 (0x0001) /* SYS - BSL Protection Size 0 */ +#define SYSBSLSIZE1 (0x0002) /* SYS - BSL Protection Size 1 */ +#define SYSBSLR (0x0004) /* SYS - RAM assigned to BSL */ +//#define RESERVED (0x0008) /* SYS - Reserved */ +//#define RESERVED (0x0010) /* SYS - Reserved */ +//#define RESERVED (0x0020) /* SYS - Reserved */ +//#define RESERVED (0x0040) /* SYS - Reserved */ +//#define RESERVED (0x0080) /* SYS - Reserved */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ +#define SYSBSLOFF (0x4000) /* SYS - BSL Memory disabled */ +#define SYSBSLPE (0x8000) /* SYS - BSL Memory protection enabled */ + +/* SYSBSLC Control Bits */ +#define SYSBSLSIZE0_L (0x0001) /* SYS - BSL Protection Size 0 */ +#define SYSBSLSIZE1_L (0x0002) /* SYS - BSL Protection Size 1 */ +#define SYSBSLR_L (0x0004) /* SYS - RAM assigned to BSL */ +//#define RESERVED (0x0008) /* SYS - Reserved */ +//#define RESERVED (0x0010) /* SYS - Reserved */ +//#define RESERVED (0x0020) /* SYS - Reserved */ +//#define RESERVED (0x0040) /* SYS - Reserved */ +//#define RESERVED (0x0080) /* SYS - Reserved */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ + +/* SYSBSLC Control Bits */ +//#define RESERVED (0x0008) /* SYS - Reserved */ +//#define RESERVED (0x0010) /* SYS - Reserved */ +//#define RESERVED (0x0020) /* SYS - Reserved */ +//#define RESERVED (0x0040) /* SYS - Reserved */ +//#define RESERVED (0x0080) /* SYS - Reserved */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ +#define SYSBSLOFF_H (0x0040) /* SYS - BSL Memory disabled */ +#define SYSBSLPE_H (0x0080) /* SYS - BSL Memory protection enabled */ + +/* SYSJMBC Control Bits */ +#define JMBIN0FG (0x0001) /* SYS - Incoming JTAG Mailbox 0 Flag */ +#define JMBIN1FG (0x0002) /* SYS - Incoming JTAG Mailbox 1 Flag */ +#define JMBOUT0FG (0x0004) /* SYS - Outgoing JTAG Mailbox 0 Flag */ +#define JMBOUT1FG (0x0008) /* SYS - Outgoing JTAG Mailbox 1 Flag */ +#define JMBMODE (0x0010) /* SYS - JMB 16/32 Bit Mode */ +//#define RESERVED (0x0020) /* SYS - Reserved */ +#define JMBCLR0OFF (0x0040) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */ +#define JMBCLR1OFF (0x0080) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ +//#define RESERVED (0x4000) /* SYS - Reserved */ +//#define RESERVED (0x8000) /* SYS - Reserved */ + +/* SYSJMBC Control Bits */ +#define JMBIN0FG_L (0x0001) /* SYS - Incoming JTAG Mailbox 0 Flag */ +#define JMBIN1FG_L (0x0002) /* SYS - Incoming JTAG Mailbox 1 Flag */ +#define JMBOUT0FG_L (0x0004) /* SYS - Outgoing JTAG Mailbox 0 Flag */ +#define JMBOUT1FG_L (0x0008) /* SYS - Outgoing JTAG Mailbox 1 Flag */ +#define JMBMODE_L (0x0010) /* SYS - JMB 16/32 Bit Mode */ +//#define RESERVED (0x0020) /* SYS - Reserved */ +#define JMBCLR0OFF_L (0x0040) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */ +#define JMBCLR1OFF_L (0x0080) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ +//#define RESERVED (0x4000) /* SYS - Reserved */ +//#define RESERVED (0x8000) /* SYS - Reserved */ + + +#endif +/************************************************************ +* Timerx_A7 +************************************************************/ +#ifdef __MSP430_HAS_TxA7__ /* Definition to show that Module is available */ + +#define OFS_TAxCTL (0x0000) /* Timerx_A7 Control */ +#define OFS_TAxCCTL0 (0x0002) /* Timerx_A7 Capture/Compare Control 0 */ +#define OFS_TAxCCTL1 (0x0004) /* Timerx_A7 Capture/Compare Control 1 */ +#define OFS_TAxCCTL2 (0x0006) /* Timerx_A7 Capture/Compare Control 2 */ +#define OFS_TAxCCTL3 (0x0008) /* Timerx_A7 Capture/Compare Control 3 */ +#define OFS_TAxCCTL4 (0x000A) /* Timerx_A7 Capture/Compare Control 4 */ +#define OFS_TAxCCTL5 (0x000C) /* Timerx_A7 Capture/Compare Control 5 */ +#define OFS_TAxCCTL6 (0x000E) /* Timerx_A7 Capture/Compare Control 6 */ +#define OFS_TAxR (0x0010) /* Timerx_A7 */ +#define OFS_TAxCCR0 (0x0012) /* Timerx_A7 Capture/Compare 0 */ +#define OFS_TAxCCR1 (0x0014) /* Timerx_A7 Capture/Compare 1 */ +#define OFS_TAxCCR2 (0x0016) /* Timerx_A7 Capture/Compare 2 */ +#define OFS_TAxCCR3 (0x0018) /* Timerx_A7 Capture/Compare 3 */ +#define OFS_TAxCCR4 (0x001A) /* Timerx_A7 Capture/Compare 4 */ +#define OFS_TAxCCR5 (0x001C) /* Timerx_A7 Capture/Compare 5 */ +#define OFS_TAxCCR6 (0x001E) /* Timerx_A7 Capture/Compare 6 */ +#define OFS_TAxIV (0x002E) /* Timerx_A7 Interrupt Vector Word */ +#define OFS_TAxEX0 (0x0020) /* Timerx_A7 Expansion Register 0 */ + +/* Bits are already defined within the Timer0_Ax */ + +/* TAxIV Definitions */ +#define TAxIV_NONE (0x0000) /* No Interrupt pending */ +#define TAxIV_TACCR1 (0x0002) /* TAxCCR1_CCIFG */ +#define TAxIV_TACCR2 (0x0004) /* TAxCCR2_CCIFG */ +#define TAxIV_TACCR3 (0x0006) /* TAxCCR3_CCIFG */ +#define TAxIV_TACCR4 (0x0008) /* TAxCCR4_CCIFG */ +#define TAxIV_TACCR5 (0x000A) /* TAxCCR5_CCIFG */ +#define TAxIV_TACCR6 (0x000C) /* TAxCCR6_CCIFG */ +#define TAxIV_TAIFG (0x000E) /* TAxIFG */ + +/* Legacy Defines */ +#define TAxIV_TAxCCR1 (0x0002) /* TAxCCR1_CCIFG */ +#define TAxIV_TAxCCR2 (0x0004) /* TAxCCR2_CCIFG */ +#define TAxIV_TAxCCR3 (0x0006) /* TAxCCR3_CCIFG */ +#define TAxIV_TAxCCR4 (0x0008) /* TAxCCR4_CCIFG */ +#define TAxIV_TAxCCR5 (0x000A) /* TAxCCR5_CCIFG */ +#define TAxIV_TAxCCR6 (0x000C) /* TAxCCR6_CCIFG */ +#define TAxIV_TAxIFG (0x000E) /* TAxIFG */ + +/* TAxCTL Control Bits */ +#define TASSEL1 (0x0200) /* Timer A clock source select 1 */ +#define TASSEL0 (0x0100) /* Timer A clock source select 0 */ +#define ID1 (0x0080) /* Timer A clock input divider 1 */ +#define ID0 (0x0040) /* Timer A clock input divider 0 */ +#define MC1 (0x0020) /* Timer A mode control 1 */ +#define MC0 (0x0010) /* Timer A mode control 0 */ +#define TACLR (0x0004) /* Timer A counter clear */ +#define TAIE (0x0002) /* Timer A counter interrupt enable */ +#define TAIFG (0x0001) /* Timer A counter interrupt flag */ + +#define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */ +#define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */ +#define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continuous up */ +#define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */ +#define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */ +#define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */ +#define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */ +#define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */ +#define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */ +#define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */ +#define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */ +#define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */ +#define MC__STOP (0*0x10u) /* Timer A mode control: 0 - Stop */ +#define MC__UP (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */ +#define MC__CONTINUOUS (2*0x10u) /* Timer A mode control: 2 - Continuous up */ +#define MC__CONTINOUS (2*0x10u) /* Legacy define */ +#define MC__UPDOWN (3*0x10u) /* Timer A mode control: 3 - Up/Down */ +#define ID__1 (0*0x40u) /* Timer A input divider: 0 - /1 */ +#define ID__2 (1*0x40u) /* Timer A input divider: 1 - /2 */ +#define ID__4 (2*0x40u) /* Timer A input divider: 2 - /4 */ +#define ID__8 (3*0x40u) /* Timer A input divider: 3 - /8 */ +#define TASSEL__TACLK (0*0x100u) /* Timer A clock source select: 0 - TACLK */ +#define TASSEL__ACLK (1*0x100u) /* Timer A clock source select: 1 - ACLK */ +#define TASSEL__SMCLK (2*0x100u) /* Timer A clock source select: 2 - SMCLK */ +#define TASSEL__INCLK (3*0x100u) /* Timer A clock source select: 3 - INCLK */ + +/* TAxCCTLx Control Bits */ +#define CM1 (0x8000) /* Capture mode 1 */ +#define CM0 (0x4000) /* Capture mode 0 */ +#define CCIS1 (0x2000) /* Capture input select 1 */ +#define CCIS0 (0x1000) /* Capture input select 0 */ +#define SCS (0x0800) /* Capture sychronize */ +#define SCCI (0x0400) /* Latched capture signal (read) */ +#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */ +#define OUTMOD2 (0x0080) /* Output mode 2 */ +#define OUTMOD1 (0x0040) /* Output mode 1 */ +#define OUTMOD0 (0x0020) /* Output mode 0 */ +#define CCIE (0x0010) /* Capture/compare interrupt enable */ +#define CCI (0x0008) /* Capture input signal (read) */ +#define OUT (0x0004) /* PWM Output signal if output mode 0 */ +#define COV (0x0002) /* Capture/compare overflow flag */ +#define CCIFG (0x0001) /* Capture/compare interrupt flag */ + +#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */ +#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */ +#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */ +#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */ +#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */ +#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */ +#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */ +#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */ +#define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */ +#define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */ +#define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */ +#define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */ +#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */ +#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */ +#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */ +#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */ + +/* TAxEX0 Control Bits */ +#define TAIDEX0 (0x0001) /* Timer A Input divider expansion Bit: 0 */ +#define TAIDEX1 (0x0002) /* Timer A Input divider expansion Bit: 1 */ +#define TAIDEX2 (0x0004) /* Timer A Input divider expansion Bit: 2 */ + +#define TAIDEX_0 (0*0x0001u) /* Timer A Input divider expansion : /1 */ +#define TAIDEX_1 (1*0x0001u) /* Timer A Input divider expansion : /2 */ +#define TAIDEX_2 (2*0x0001u) /* Timer A Input divider expansion : /3 */ +#define TAIDEX_3 (3*0x0001u) /* Timer A Input divider expansion : /4 */ +#define TAIDEX_4 (4*0x0001u) /* Timer A Input divider expansion : /5 */ +#define TAIDEX_5 (5*0x0001u) /* Timer A Input divider expansion : /6 */ +#define TAIDEX_6 (6*0x0001u) /* Timer A Input divider expansion : /7 */ +#define TAIDEX_7 (7*0x0001u) /* Timer A Input divider expansion : /8 */ + +#endif +/************************************************************ +* Timerx_B7 +************************************************************/ +#ifdef __MSP430_HAS_TxB7__ /* Definition to show that Module is available */ + +#define OFS_TBxCTL (0x0000) /* Timerx_B7 Control */ +#define OFS_TBxCCTL0 (0x0002) /* Timerx_B7 Capture/Compare Control 0 */ +#define OFS_TBxCCTL1 (0x0004) /* Timerx_B7 Capture/Compare Control 1 */ +#define OFS_TBxCCTL2 (0x0006) /* Timerx_B7 Capture/Compare Control 2 */ +#define OFS_TBxCCTL3 (0x0008) /* Timerx_B7 Capture/Compare Control 3 */ +#define OFS_TBxCCTL4 (0x000A) /* Timerx_B7 Capture/Compare Control 4 */ +#define OFS_TBxCCTL5 (0x000C) /* Timerx_B7 Capture/Compare Control 5 */ +#define OFS_TBxCCTL6 (0x000E) /* Timerx_B7 Capture/Compare Control 6 */ +#define OFS_TBxR (0x0010) /* Timerx_B7 */ +#define OFS_TBxCCR0 (0x0012) /* Timerx_B7 Capture/Compare 0 */ +#define OFS_TBxCCR1 (0x0014) /* Timerx_B7 Capture/Compare 1 */ +#define OFS_TBxCCR2 (0x0016) /* Timerx_B7 Capture/Compare 2 */ +#define OFS_TBxCCR3 (0x0018) /* Timerx_B7 Capture/Compare 3 */ +#define OFS_TBxCCR4 (0x001A) /* Timerx_B7 Capture/Compare 4 */ +#define OFS_TBxCCR5 (0x001C) /* Timerx_B7 Capture/Compare 5 */ +#define OFS_TBxCCR6 (0x001E) /* Timerx_B7 Capture/Compare 6 */ +#define OFS_TBxIV (0x002E) /* Timerx_B7 Interrupt Vector Word */ +#define OFS_TBxEX0 (0x0020) /* Timerx_B7 Expansion Register 0 */ + +/* Bits are already defined within the Timer0_Ax */ + +/* TBxIV Definitions */ +#define TBxIV_NONE (0x0000) /* No Interrupt pending */ +#define TBxIV_TBCCR1 (0x0002) /* TBxCCR1_CCIFG */ +#define TBxIV_TBCCR2 (0x0004) /* TBxCCR2_CCIFG */ +#define TBxIV_TBCCR3 (0x0006) /* TBxCCR3_CCIFG */ +#define TBxIV_TBCCR4 (0x0008) /* TBxCCR4_CCIFG */ +#define TBxIV_TBCCR5 (0x000A) /* TBxCCR5_CCIFG */ +#define TBxIV_TBCCR6 (0x000C) /* TBxCCR6_CCIFG */ +#define TBxIV_TBIFG (0x000E) /* TBxIFG */ + +/* Legacy Defines */ +#define TBxIV_TBxCCR1 (0x0002) /* TBxCCR1_CCIFG */ +#define TBxIV_TBxCCR2 (0x0004) /* TBxCCR2_CCIFG */ +#define TBxIV_TBxCCR3 (0x0006) /* TBxCCR3_CCIFG */ +#define TBxIV_TBxCCR4 (0x0008) /* TBxCCR4_CCIFG */ +#define TBxIV_TBxCCR5 (0x000A) /* TBxCCR5_CCIFG */ +#define TBxIV_TBxCCR6 (0x000C) /* TBxCCR6_CCIFG */ +#define TBxIV_TBxIFG (0x000E) /* TBxIFG */ + +/* TBxCTL Control Bits */ +#define TBCLGRP1 (0x4000) /* Timer_B7 Compare latch load group 1 */ +#define TBCLGRP0 (0x2000) /* Timer_B7 Compare latch load group 0 */ +#define CNTL1 (0x1000) /* Counter lenght 1 */ +#define CNTL0 (0x0800) /* Counter lenght 0 */ +#define TBSSEL1 (0x0200) /* Clock source 1 */ +#define TBSSEL0 (0x0100) /* Clock source 0 */ +#define TBCLR (0x0004) /* Timer_B7 counter clear */ +#define TBIE (0x0002) /* Timer_B7 interrupt enable */ +#define TBIFG (0x0001) /* Timer_B7 interrupt flag */ + +#define SHR1 (0x4000) /* Timer_B7 Compare latch load group 1 */ +#define SHR0 (0x2000) /* Timer_B7 Compare latch load group 0 */ + +#define TBSSEL_0 (0*0x0100u) /* Clock Source: TBCLK */ +#define TBSSEL_1 (1*0x0100u) /* Clock Source: ACLK */ +#define TBSSEL_2 (2*0x0100u) /* Clock Source: SMCLK */ +#define TBSSEL_3 (3*0x0100u) /* Clock Source: INCLK */ +#define CNTL_0 (0*0x0800u) /* Counter lenght: 16 bit */ +#define CNTL_1 (1*0x0800u) /* Counter lenght: 12 bit */ +#define CNTL_2 (2*0x0800u) /* Counter lenght: 10 bit */ +#define CNTL_3 (3*0x0800u) /* Counter lenght: 8 bit */ +#define SHR_0 (0*0x2000u) /* Timer_B7 Group: 0 - individually */ +#define SHR_1 (1*0x2000u) /* Timer_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */ +#define SHR_2 (2*0x2000u) /* Timer_B7 Group: 2 - 2 groups (1-3, 4-6)*/ +#define SHR_3 (3*0x2000u) /* Timer_B7 Group: 3 - 1 group (all) */ +#define TBCLGRP_0 (0*0x2000u) /* Timer_B7 Group: 0 - individually */ +#define TBCLGRP_1 (1*0x2000u) /* Timer_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */ +#define TBCLGRP_2 (2*0x2000u) /* Timer_B7 Group: 2 - 2 groups (1-3, 4-6)*/ +#define TBCLGRP_3 (3*0x2000u) /* Timer_B7 Group: 3 - 1 group (all) */ +#define TBSSEL__TBCLK (0*0x100u) /* Timer0_B7 clock source select: 0 - TBCLK */ +#define TBSSEL__TACLK (0*0x100u) /* Timer0_B7 clock source select: 0 - TBCLK (legacy) */ +#define TBSSEL__ACLK (1*0x100u) /* Timer_B7 clock source select: 1 - ACLK */ +#define TBSSEL__SMCLK (2*0x100u) /* Timer_B7 clock source select: 2 - SMCLK */ +#define TBSSEL__INCLK (3*0x100u) /* Timer_B7 clock source select: 3 - INCLK */ +#define CNTL__16 (0*0x0800u) /* Counter lenght: 16 bit */ +#define CNTL__12 (1*0x0800u) /* Counter lenght: 12 bit */ +#define CNTL__10 (2*0x0800u) /* Counter lenght: 10 bit */ +#define CNTL__8 (3*0x0800u) /* Counter lenght: 8 bit */ + +/* Additional Timer B Control Register bits are defined in Timer A */ +/* TBxCCTLx Control Bits */ +#define CLLD1 (0x0400) /* Compare latch load source 1 */ +#define CLLD0 (0x0200) /* Compare latch load source 0 */ + +#define SLSHR1 (0x0400) /* Compare latch load source 1 */ +#define SLSHR0 (0x0200) /* Compare latch load source 0 */ + +#define SLSHR_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */ +#define SLSHR_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */ +#define SLSHR_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */ +#define SLSHR_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */ + +#define CLLD_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */ +#define CLLD_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */ +#define CLLD_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */ +#define CLLD_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */ + +/* TBxEX0 Control Bits */ +#define TBIDEX0 (0x0001) /* Timer_B7 Input divider expansion Bit: 0 */ +#define TBIDEX1 (0x0002) /* Timer_B7 Input divider expansion Bit: 1 */ +#define TBIDEX2 (0x0004) /* Timer_B7 Input divider expansion Bit: 2 */ + +#define TBIDEX_0 (0*0x0001u) /* Timer_B7 Input divider expansion : /1 */ +#define TBIDEX_1 (1*0x0001u) /* Timer_B7 Input divider expansion : /2 */ +#define TBIDEX_2 (2*0x0001u) /* Timer_B7 Input divider expansion : /3 */ +#define TBIDEX_3 (3*0x0001u) /* Timer_B7 Input divider expansion : /4 */ +#define TBIDEX_4 (4*0x0001u) /* Timer_B7 Input divider expansion : /5 */ +#define TBIDEX_5 (5*0x0001u) /* Timer_B7 Input divider expansion : /6 */ +#define TBIDEX_6 (6*0x0001u) /* Timer_B7 Input divider expansion : /7 */ +#define TBIDEX_7 (7*0x0001u) /* Timer_B7 Input divider expansion : /8 */ +#define TBIDEX__1 (0*0x0001u) /* Timer_B7 Input divider expansion : /1 */ +#define TBIDEX__2 (1*0x0001u) /* Timer_B7 Input divider expansion : /2 */ +#define TBIDEX__3 (2*0x0001u) /* Timer_B7 Input divider expansion : /3 */ +#define TBIDEX__4 (3*0x0001u) /* Timer_B7 Input divider expansion : /4 */ +#define TBIDEX__5 (4*0x0001u) /* Timer_B7 Input divider expansion : /5 */ +#define TBIDEX__6 (5*0x0001u) /* Timer_B7 Input divider expansion : /6 */ +#define TBIDEX__7 (6*0x0001u) /* Timer_B7 Input divider expansion : /7 */ +#define TBIDEX__8 (7*0x0001u) /* Timer_B7 Input divider expansion : /8 */ + + +#define ID1 (0x0080) /* Timer B clock input divider 1 */ +#define ID0 (0x0040) /* Timer B clock input divider 0 */ +#define MC1 (0x0020) /* Timer B mode control 1 */ +#define MC0 (0x0010) /* Timer B mode control 0 */ +#define MC__STOP (0*0x10u) /* Timer B mode control: 0 - Stop */ +#define MC__UP (1*0x10u) /* Timer B mode control: 1 - Up to CCR0 */ +#define MC__CONTINUOUS (2*0x10u) /* Timer B mode control: 2 - Continuous up */ +#define MC__CONTINOUS (2*0x10u) /* Legacy define */ +#define MC__UPDOWN (3*0x10u) /* Timer B mode control: 3 - Up/Down */ +#define CM1 (0x8000) /* Capture mode 1 */ +#define CM0 (0x4000) /* Capture mode 0 */ +#define MC_0 (0*0x10u) /* Timer B mode control: 0 - Stop */ +#define MC_1 (1*0x10u) /* Timer B mode control: 1 - Up to CCR0 */ +#define MC_2 (2*0x10u) /* Timer B mode control: 2 - Continuous up */ +#define MC_3 (3*0x10u) /* Timer B mode control: 3 - Up/Down */ +#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */ +#define CCIE (0x0010) /* Capture/compare interrupt enable */ +#define CCIFG (0x0001) /* Capture/compare interrupt flag */ +#define CCIS_0 (0*0x1000u) +#define CCIS_1 (1*0x1000u) +#define CCIS_2 (2*0x1000u) +#define CCIS_3 (3*0x1000u) +#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */ +#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */ +#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */ +#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */ +#define OUT (0x0004) /* PWM Output signal if output mode 0 */ +#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */ +#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */ +#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */ +#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */ +#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */ +#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */ +#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */ +#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */ +#define SCCI (0x0400) /* Latched capture signal (read) */ +#define SCS (0x0800) /* Capture sychronize */ +#define CCI (0x0008) /* Capture input signal (read) */ +#define ID__1 (0*0x40u) /* Timer B input divider: 0 - /1 */ +#define ID__2 (1*0x40u) /* Timer B input divider: 1 - /2 */ +#define ID__4 (2*0x40u) /* Timer B input divider: 2 - /4 */ +#define ID__8 (3*0x40u) /* Timer B input divider: 3 - /8 */ +#define ID_0 (0*0x40u) /* Timer B input divider: 0 - /1 */ +#define ID_1 (1*0x40u) /* Timer B input divider: 1 - /2 */ +#define ID_2 (2*0x40u) /* Timer B input divider: 2 - /4 */ +#define ID_3 (3*0x40u) /* Timer B input divider: 3 - /8 */ + +#endif +/************************************************************ +* USCI Ax +************************************************************/ +#ifdef __MSP430_HAS_EUSCI_Ax__ /* Definition to show that Module is available */ + +#define OFS_UCAxCTLW0 (0x0000) /* USCI Ax Control Word Register 0 */ +#define OFS_UCAxCTLW0_L OFS_UCAxCTLW0 +#define OFS_UCAxCTLW0_H OFS_UCAxCTLW0+1 +#define OFS_UCAxCTL0 (0x0001) +#define OFS_UCAxCTL1 (0x0000) +#define UCAxCTL1 UCAxCTLW0_L /* USCI Ax Control Register 1 */ +#define UCAxCTL0 UCAxCTLW0_H /* USCI Ax Control Register 0 */ +#define OFS_UCAxCTLW1 (0x0002) /* USCI Ax Control Word Register 1 */ +#define OFS_UCAxCTLW1_L OFS_UCAxCTLW1 +#define OFS_UCAxCTLW1_H OFS_UCAxCTLW1+1 +#define OFS_UCAxBRW (0x0006) /* USCI Ax Baud Word Rate 0 */ +#define OFS_UCAxBRW_L OFS_UCAxBRW +#define OFS_UCAxBRW_H OFS_UCAxBRW+1 +#define OFS_UCAxBR0 (0x0006) +#define OFS_UCAxBR1 (0x0007) +#define UCAxBR0 UCAxBRW_L /* USCI Ax Baud Rate 0 */ +#define UCAxBR1 UCAxBRW_H /* USCI Ax Baud Rate 1 */ +#define OFS_UCAxMCTLW (0x0008) /* USCI Ax Modulation Control */ +#define OFS_UCAxMCTLW_L OFS_UCAxMCTLW +#define OFS_UCAxMCTLW_H OFS_UCAxMCTLW+1 +#define OFS_UCAxSTATW (0x000A) /* USCI Ax Status Register */ +#define OFS_UCAxRXBUF (0x000C) /* USCI Ax Receive Buffer */ +#define OFS_UCAxRXBUF_L OFS_UCAxRXBUF +#define OFS_UCAxRXBUF_H OFS_UCAxRXBUF+1 +#define OFS_UCAxTXBUF (0x000E) /* USCI Ax Transmit Buffer */ +#define OFS_UCAxTXBUF_L OFS_UCAxTXBUF +#define OFS_UCAxTXBUF_H OFS_UCAxTXBUF+1 +#define OFS_UCAxABCTL (0x0010) /* USCI Ax LIN Control */ +#define OFS_UCAxIRCTL (0x0012) /* USCI Ax IrDA Transmit Control */ +#define OFS_UCAxIRCTL_L OFS_UCAxIRCTL +#define OFS_UCAxIRCTL_H OFS_UCAxIRCTL+1 +#define OFS_UCAxIRTCTL (0x0012) +#define OFS_UCAxIRRCTL (0x0013) +#define UCAxIRTCTL UCAxIRCTL_L /* USCI Ax IrDA Transmit Control */ +#define UCAxIRRCTL UCAxIRCTL_H /* USCI Ax IrDA Receive Control */ +#define OFS_UCAxIE (0x001A) /* USCI Ax Interrupt Enable Register */ +#define OFS_UCAxIE_L OFS_UCAxIE +#define OFS_UCAxIE_H OFS_UCAxIE+1 +#define OFS_UCAxIFG (0x001C) /* USCI Ax Interrupt Flags Register */ +#define OFS_UCAxIFG_L OFS_UCAxIFG +#define OFS_UCAxIFG_H OFS_UCAxIFG+1 +#define OFS_UCAxIE__UART (0x001A) +#define OFS_UCAxIE__UART_L OFS_UCAxIE__UART +#define OFS_UCAxIE__UART_H OFS_UCAxIE__UART+1 +#define OFS_UCAxIFG__UART (0x001C) +#define OFS_UCAxIFG__UART_L OFS_UCAxIFG__UART +#define OFS_UCAxIFG__UART_H OFS_UCAxIFG__UART+1 +#define OFS_UCAxIV (0x001E) /* USCI Ax Interrupt Vector Register */ + +#define OFS_UCAxCTLW0__SPI (0x0000) +#define OFS_UCAxCTLW0__SPI_L OFS_UCAxCTLW0__SPI +#define OFS_UCAxCTLW0__SPI_H OFS_UCAxCTLW0__SPI+1 +#define OFS_UCAxCTL0__SPI (0x0001) +#define OFS_UCAxCTL1__SPI (0x0000) +#define OFS_UCAxBRW__SPI (0x0006) +#define OFS_UCAxBRW__SPI_L OFS_UCAxBRW__SPI +#define OFS_UCAxBRW__SPI_H OFS_UCAxBRW__SPI+1 +#define OFS_UCAxBR0__SPI (0x0006) +#define OFS_UCAxBR1__SPI (0x0007) +#define OFS_UCAxSTATW__SPI (0x000A) +#define OFS_UCAxRXBUF__SPI (0x000C) +#define OFS_UCAxRXBUF__SPI_L OFS_UCAxRXBUF__SPI +#define OFS_UCAxRXBUF__SPI_H OFS_UCAxRXBUF__SPI+1 +#define OFS_UCAxTXBUF__SPI (0x000E) +#define OFS_UCAxTXBUF__SPI_L OFS_UCAxTXBUF__SPI +#define OFS_UCAxTXBUF__SPI_H OFS_UCAxTXBUF__SPI+1 +#define OFS_UCAxIE__SPI (0x001A) +#define OFS_UCAxIFG__SPI (0x001C) +#define OFS_UCAxIV__SPI (0x001E) + +#endif +/************************************************************ +* USCI Bx +************************************************************/ +#ifdef __MSP430_HAS_EUSCI_Bx__ /* Definition to show that Module is available */ + +#define OFS_UCBxCTLW0__SPI (0x0000) +#define OFS_UCBxCTLW0__SPI_L OFS_UCBxCTLW0__SPI +#define OFS_UCBxCTLW0__SPI_H OFS_UCBxCTLW0__SPI+1 +#define OFS_UCBxCTL0__SPI (0x0001) +#define OFS_UCBxCTL1__SPI (0x0000) +#define OFS_UCBxBRW__SPI (0x0006) +#define OFS_UCBxBRW__SPI_L OFS_UCBxBRW__SPI +#define OFS_UCBxBRW__SPI_H OFS_UCBxBRW__SPI+1 +#define OFS_UCBxBR0__SPI (0x0006) +#define OFS_UCBxBR1__SPI (0x0007) +#define OFS_UCBxSTATW__SPI (0x0008) +#define OFS_UCBxSTATW__SPI_L OFS_UCBxSTATW__SPI +#define OFS_UCBxSTATW__SPI_H OFS_UCBxSTATW__SPI+1 +#define OFS_UCBxRXBUF__SPI (0x000C) +#define OFS_UCBxRXBUF__SPI_L OFS_UCBxRXBUF__SPI +#define OFS_UCBxRXBUF__SPI_H OFS_UCBxRXBUF__SPI+1 +#define OFS_UCBxTXBUF__SPI (0x000E) +#define OFS_UCBxTXBUF__SPI_L OFS_UCBxTXBUF__SPI +#define OFS_UCBxTXBUF__SPI_H OFS_UCBxTXBUF__SPI+1 +#define OFS_UCBxIE__SPI (0x002A) +#define OFS_UCBxIE__SPI_L OFS_UCBxIE__SPI +#define OFS_UCBxIE__SPI_H OFS_UCBxIE__SPI+1 +#define OFS_UCBxIFG__SPI (0x002C) +#define OFS_UCBxIFG__SPI_L OFS_UCBxIFG__SPI +#define OFS_UCBxIFG__SPI_H OFS_UCBxIFG__SPI+1 +#define OFS_UCBxIV__SPI (0x002E) + +#define OFS_UCBxCTLW0 (0x0000) /* USCI Bx Control Word Register 0 */ +#define OFS_UCBxCTLW0_L OFS_UCBxCTLW0 +#define OFS_UCBxCTLW0_H OFS_UCBxCTLW0+1 +#define OFS_UCBxCTL0 (0x0001) +#define OFS_UCBxCTL1 (0x0000) +#define UCBxCTL1 UCBxCTLW0_L /* USCI Bx Control Register 1 */ +#define UCBxCTL0 UCBxCTLW0_H /* USCI Bx Control Register 0 */ +#define OFS_UCBxCTLW1 (0x0002) /* USCI Bx Control Word Register 1 */ +#define OFS_UCBxCTLW1_L OFS_UCBxCTLW1 +#define OFS_UCBxCTLW1_H OFS_UCBxCTLW1+1 +#define OFS_UCBxBRW (0x0006) /* USCI Bx Baud Word Rate 0 */ +#define OFS_UCBxBRW_L OFS_UCBxBRW +#define OFS_UCBxBRW_H OFS_UCBxBRW+1 +#define OFS_UCBxBR0 (0x0006) +#define OFS_UCBxBR1 (0x0007) +#define UCBxBR0 UCBxBRW_L /* USCI Bx Baud Rate 0 */ +#define UCBxBR1 UCBxBRW_H /* USCI Bx Baud Rate 1 */ +#define OFS_UCBxSTATW (0x0008) /* USCI Bx Status Word Register */ +#define OFS_UCBxSTATW_L OFS_UCBxSTATW +#define OFS_UCBxSTATW_H OFS_UCBxSTATW+1 +#define OFS_UCBxSTATW__I2C (0x0008) +#define OFS_UCBxSTAT__I2C (0x0008) +#define OFS_UCBxBCNT__I2C (0x0009) +#define UCBxSTAT UCBxSTATW_L /* USCI Bx Status Register */ +#define UCBxBCNT UCBxSTATW_H /* USCI Bx Byte Counter Register */ +#define OFS_UCBxTBCNT (0x000A) /* USCI Bx Byte Counter Threshold Register */ +#define OFS_UCBxTBCNT_L OFS_UCBxTBCNT +#define OFS_UCBxTBCNT_H OFS_UCBxTBCNT+1 +#define OFS_UCBxRXBUF (0x000C) /* USCI Bx Receive Buffer */ +#define OFS_UCBxRXBUF_L OFS_UCBxRXBUF +#define OFS_UCBxRXBUF_H OFS_UCBxRXBUF+1 +#define OFS_UCBxTXBUF (0x000E) /* USCI Bx Transmit Buffer */ +#define OFS_UCBxTXBUF_L OFS_UCBxTXBUF +#define OFS_UCBxTXBUF_H OFS_UCBxTXBUF+1 +#define OFS_UCBxI2COA0 (0x0014) /* USCI Bx I2C Own Address 0 */ +#define OFS_UCBxI2COA0_L OFS_UCBxI2COA0 +#define OFS_UCBxI2COA0_H OFS_UCBxI2COA0+1 +#define OFS_UCBxI2COA1 (0x0016) /* USCI Bx I2C Own Address 1 */ +#define OFS_UCBxI2COA1_L OFS_UCBxI2COA1 +#define OFS_UCBxI2COA1_H OFS_UCBxI2COA1+1 +#define OFS_UCBxI2COA2 (0x0018) /* USCI Bx I2C Own Address 2 */ +#define OFS_UCBxI2COA2_L OFS_UCBxI2COA2 +#define OFS_UCBxI2COA2_H OFS_UCBxI2COA2+1 +#define OFS_UCBxI2COA3 (0x001A) /* USCI Bx I2C Own Address 3 */ +#define OFS_UCBxI2COA3_L OFS_UCBxI2COA3 +#define OFS_UCBxI2COA3_H OFS_UCBxI2COA3+1 +#define OFS_UCBxADDRX (0x001C) /* USCI Bx Received Address Register */ +#define OFS_UCBxADDRX_L OFS_UCBxADDRX +#define OFS_UCBxADDRX_H OFS_UCBxADDRX+1 +#define OFS_UCBxADDMASK (0x001E) /* USCI Bx Address Mask Register */ +#define OFS_UCBxADDMASK_L OFS_UCBxADDMASK +#define OFS_UCBxADDMASK_H OFS_UCBxADDMASK+1 +#define OFS_UCBxI2CSA (0x0020) /* USCI Bx I2C Slave Address */ +#define OFS_UCBxI2CSA_L OFS_UCBxI2CSA +#define OFS_UCBxI2CSA_H OFS_UCBxI2CSA+1 +#define OFS_UCBxIE (0x002A) /* USCI Bx Interrupt Enable Register */ +#define OFS_UCBxIE_L OFS_UCBxIE +#define OFS_UCBxIE_H OFS_UCBxIE+1 +#define OFS_UCBxIFG (0x002C) /* USCI Bx Interrupt Flags Register */ +#define OFS_UCBxIFG_L OFS_UCBxIFG +#define OFS_UCBxIFG_H OFS_UCBxIFG+1 +#define OFS_UCBxIE__I2C (0x002A) +#define OFS_UCBxIE__I2C_L OFS_UCBxIE__I2C +#define OFS_UCBxIE__I2C_H OFS_UCBxIE__I2C+1 +#define OFS_UCBxIFG__I2C (0x002C) +#define OFS_UCBxIFG__I2C_L OFS_UCBxIFG__I2C +#define OFS_UCBxIFG__I2C_H OFS_UCBxIFG__I2C+1 +#define OFS_UCBxIV (0x002E) /* USCI Bx Interrupt Vector Register */ + +#endif +#if (defined(__MSP430_HAS_EUSCI_Ax__) || defined(__MSP430_HAS_EUSCI_Bx__)) + +// UCAxCTLW0 UART-Mode Control Bits +#define UCPEN (0x8000) /* Async. Mode: Parity enable */ +#define UCPAR (0x4000) /* Async. Mode: Parity 0:odd / 1:even */ +#define UCMSB (0x2000) /* Async. Mode: MSB first 0:LSB / 1:MSB */ +#define UC7BIT (0x1000) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */ +#define UCSPB (0x0800) /* Async. Mode: Stop Bits 0:one / 1: two */ +#define UCMODE1 (0x0400) /* Async. Mode: USCI Mode 1 */ +#define UCMODE0 (0x0200) /* Async. Mode: USCI Mode 0 */ +#define UCSYNC (0x0100) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */ +#define UCSSEL1 (0x0080) /* USCI 0 Clock Source Select 1 */ +#define UCSSEL0 (0x0040) /* USCI 0 Clock Source Select 0 */ +#define UCRXEIE (0x0020) /* RX Error interrupt enable */ +#define UCBRKIE (0x0010) /* Break interrupt enable */ +#define UCDORM (0x0008) /* Dormant (Sleep) Mode */ +#define UCTXADDR (0x0004) /* Send next Data as Address */ +#define UCTXBRK (0x0002) /* Send next Data as Break */ +#define UCSWRST (0x0001) /* USCI Software Reset */ + +// UCAxCTLW0 UART-Mode Control Bits +#define UCSSEL1_L (0x0080) /* USCI 0 Clock Source Select 1 */ +#define UCSSEL0_L (0x0040) /* USCI 0 Clock Source Select 0 */ +#define UCRXEIE_L (0x0020) /* RX Error interrupt enable */ +#define UCBRKIE_L (0x0010) /* Break interrupt enable */ +#define UCDORM_L (0x0008) /* Dormant (Sleep) Mode */ +#define UCTXADDR_L (0x0004) /* Send next Data as Address */ +#define UCTXBRK_L (0x0002) /* Send next Data as Break */ +#define UCSWRST_L (0x0001) /* USCI Software Reset */ + +// UCAxCTLW0 UART-Mode Control Bits +#define UCPEN_H (0x0080) /* Async. Mode: Parity enable */ +#define UCPAR_H (0x0040) /* Async. Mode: Parity 0:odd / 1:even */ +#define UCMSB_H (0x0020) /* Async. Mode: MSB first 0:LSB / 1:MSB */ +#define UC7BIT_H (0x0010) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */ +#define UCSPB_H (0x0008) /* Async. Mode: Stop Bits 0:one / 1: two */ +#define UCMODE1_H (0x0004) /* Async. Mode: USCI Mode 1 */ +#define UCMODE0_H (0x0002) /* Async. Mode: USCI Mode 0 */ +#define UCSYNC_H (0x0001) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */ + +// UCxxCTLW0 SPI-Mode Control Bits +#define UCCKPH (0x8000) /* Sync. Mode: Clock Phase */ +#define UCCKPL (0x4000) /* Sync. Mode: Clock Polarity */ +#define UCMST (0x0800) /* Sync. Mode: Master Select */ +//#define res (0x0020) /* reserved */ +//#define res (0x0010) /* reserved */ +//#define res (0x0008) /* reserved */ +//#define res (0x0004) /* reserved */ +#define UCSTEM (0x0002) /* USCI STE Mode */ + +// UCBxCTLW0 I2C-Mode Control Bits +#define UCA10 (0x8000) /* 10-bit Address Mode */ +#define UCSLA10 (0x4000) /* 10-bit Slave Address Mode */ +#define UCMM (0x2000) /* Multi-Master Environment */ +//#define res (0x1000) /* reserved */ +//#define res (0x0100) /* reserved */ +#define UCTXACK (0x0020) /* Transmit ACK */ +#define UCTR (0x0010) /* Transmit/Receive Select/Flag */ +#define UCTXNACK (0x0008) /* Transmit NACK */ +#define UCTXSTP (0x0004) /* Transmit STOP */ +#define UCTXSTT (0x0002) /* Transmit START */ + +// UCBxCTLW0 I2C-Mode Control Bits +//#define res (0x1000) /* reserved */ +//#define res (0x0100) /* reserved */ +#define UCTXACK_L (0x0020) /* Transmit ACK */ +#define UCTR_L (0x0010) /* Transmit/Receive Select/Flag */ +#define UCTXNACK_L (0x0008) /* Transmit NACK */ +#define UCTXSTP_L (0x0004) /* Transmit STOP */ +#define UCTXSTT_L (0x0002) /* Transmit START */ + +// UCBxCTLW0 I2C-Mode Control Bits +#define UCA10_H (0x0080) /* 10-bit Address Mode */ +#define UCSLA10_H (0x0040) /* 10-bit Slave Address Mode */ +#define UCMM_H (0x0020) /* Multi-Master Environment */ +//#define res (0x1000) /* reserved */ +//#define res (0x0100) /* reserved */ + +#define UCMODE_0 (0x0000) /* Sync. Mode: USCI Mode: 0 */ +#define UCMODE_1 (0x0200) /* Sync. Mode: USCI Mode: 1 */ +#define UCMODE_2 (0x0400) /* Sync. Mode: USCI Mode: 2 */ +#define UCMODE_3 (0x0600) /* Sync. Mode: USCI Mode: 3 */ + +#define UCSSEL_0 (0x0000) /* USCI 0 Clock Source: 0 */ +#define UCSSEL_1 (0x0040) /* USCI 0 Clock Source: 1 */ +#define UCSSEL_2 (0x0080) /* USCI 0 Clock Source: 2 */ +#define UCSSEL_3 (0x00C0) /* USCI 0 Clock Source: 3 */ +#define UCSSEL__UCLK (0x0000) /* USCI 0 Clock Source: UCLK */ +#define UCSSEL__ACLK (0x0040) /* USCI 0 Clock Source: ACLK */ +#define UCSSEL__SMCLK (0x0080) /* USCI 0 Clock Source: SMCLK */ + +// UCAxCTLW1 UART-Mode Control Bits +#define UCGLIT1 (0x0002) /* USCI Deglitch Time Bit 1 */ +#define UCGLIT0 (0x0001) /* USCI Deglitch Time Bit 0 */ + +// UCAxCTLW1 UART-Mode Control Bits +#define UCGLIT1_L (0x0002) /* USCI Deglitch Time Bit 1 */ +#define UCGLIT0_L (0x0001) /* USCI Deglitch Time Bit 0 */ + +// UCBxCTLW1 I2C-Mode Control Bits +#define UCETXINT (0x0100) /* USCI Early UCTXIFG0 */ +#define UCCLTO1 (0x0080) /* USCI Clock low timeout Bit: 1 */ +#define UCCLTO0 (0x0040) /* USCI Clock low timeout Bit: 0 */ +#define UCSTPNACK (0x0020) /* USCI Acknowledge Stop last byte */ +#define UCSWACK (0x0010) /* USCI Software controlled ACK */ +#define UCASTP1 (0x0008) /* USCI Automatic Stop condition generation Bit: 1 */ +#define UCASTP0 (0x0004) /* USCI Automatic Stop condition generation Bit: 0 */ +#define UCGLIT1 (0x0002) /* USCI Deglitch time Bit: 1 */ +#define UCGLIT0 (0x0001) /* USCI Deglitch time Bit: 0 */ + +// UCBxCTLW1 I2C-Mode Control Bits +#define UCCLTO1_L (0x0080) /* USCI Clock low timeout Bit: 1 */ +#define UCCLTO0_L (0x0040) /* USCI Clock low timeout Bit: 0 */ +#define UCSTPNACK_L (0x0020) /* USCI Acknowledge Stop last byte */ +#define UCSWACK_L (0x0010) /* USCI Software controlled ACK */ +#define UCASTP1_L (0x0008) /* USCI Automatic Stop condition generation Bit: 1 */ +#define UCASTP0_L (0x0004) /* USCI Automatic Stop condition generation Bit: 0 */ +#define UCGLIT1_L (0x0002) /* USCI Deglitch time Bit: 1 */ +#define UCGLIT0_L (0x0001) /* USCI Deglitch time Bit: 0 */ + +// UCBxCTLW1 I2C-Mode Control Bits +#define UCETXINT_H (0x0001) /* USCI Early UCTXIFG0 */ + +#define UCGLIT_0 (0x0000) /* USCI Deglitch time: 0 */ +#define UCGLIT_1 (0x0001) /* USCI Deglitch time: 1 */ +#define UCGLIT_2 (0x0002) /* USCI Deglitch time: 2 */ +#define UCGLIT_3 (0x0003) /* USCI Deglitch time: 3 */ + +#define UCASTP_0 (0x0000) /* USCI Automatic Stop condition generation: 0 */ +#define UCASTP_1 (0x0004) /* USCI Automatic Stop condition generation: 1 */ +#define UCASTP_2 (0x0008) /* USCI Automatic Stop condition generation: 2 */ +#define UCASTP_3 (0x000C) /* USCI Automatic Stop condition generation: 3 */ + +#define UCCLTO_0 (0x0000) /* USCI Clock low timeout: 0 */ +#define UCCLTO_1 (0x0040) /* USCI Clock low timeout: 1 */ +#define UCCLTO_2 (0x0080) /* USCI Clock low timeout: 2 */ +#define UCCLTO_3 (0x00C0) /* USCI Clock low timeout: 3 */ + +/* UCAxMCTLW Control Bits */ +#define UCBRS7 (0x8000) /* USCI Second Stage Modulation Select 7 */ +#define UCBRS6 (0x4000) /* USCI Second Stage Modulation Select 6 */ +#define UCBRS5 (0x2000) /* USCI Second Stage Modulation Select 5 */ +#define UCBRS4 (0x1000) /* USCI Second Stage Modulation Select 4 */ +#define UCBRS3 (0x0800) /* USCI Second Stage Modulation Select 3 */ +#define UCBRS2 (0x0400) /* USCI Second Stage Modulation Select 2 */ +#define UCBRS1 (0x0200) /* USCI Second Stage Modulation Select 1 */ +#define UCBRS0 (0x0100) /* USCI Second Stage Modulation Select 0 */ +#define UCBRF3 (0x0080) /* USCI First Stage Modulation Select 3 */ +#define UCBRF2 (0x0040) /* USCI First Stage Modulation Select 2 */ +#define UCBRF1 (0x0020) /* USCI First Stage Modulation Select 1 */ +#define UCBRF0 (0x0010) /* USCI First Stage Modulation Select 0 */ +#define UCOS16 (0x0001) /* USCI 16-times Oversampling enable */ + +/* UCAxMCTLW Control Bits */ +#define UCBRF3_L (0x0080) /* USCI First Stage Modulation Select 3 */ +#define UCBRF2_L (0x0040) /* USCI First Stage Modulation Select 2 */ +#define UCBRF1_L (0x0020) /* USCI First Stage Modulation Select 1 */ +#define UCBRF0_L (0x0010) /* USCI First Stage Modulation Select 0 */ +#define UCOS16_L (0x0001) /* USCI 16-times Oversampling enable */ + +/* UCAxMCTLW Control Bits */ +#define UCBRS7_H (0x0080) /* USCI Second Stage Modulation Select 7 */ +#define UCBRS6_H (0x0040) /* USCI Second Stage Modulation Select 6 */ +#define UCBRS5_H (0x0020) /* USCI Second Stage Modulation Select 5 */ +#define UCBRS4_H (0x0010) /* USCI Second Stage Modulation Select 4 */ +#define UCBRS3_H (0x0008) /* USCI Second Stage Modulation Select 3 */ +#define UCBRS2_H (0x0004) /* USCI Second Stage Modulation Select 2 */ +#define UCBRS1_H (0x0002) /* USCI Second Stage Modulation Select 1 */ +#define UCBRS0_H (0x0001) /* USCI Second Stage Modulation Select 0 */ + +#define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */ +#define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */ +#define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */ +#define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */ +#define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */ +#define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */ +#define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */ +#define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */ +#define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */ +#define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */ +#define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */ +#define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */ +#define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */ +#define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */ +#define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */ +#define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */ + +/* UCAxSTATW Control Bits */ +#define UCLISTEN (0x0080) /* USCI Listen mode */ +#define UCFE (0x0040) /* USCI Frame Error Flag */ +#define UCOE (0x0020) /* USCI Overrun Error Flag */ +#define UCPE (0x0010) /* USCI Parity Error Flag */ +#define UCBRK (0x0008) /* USCI Break received */ +#define UCRXERR (0x0004) /* USCI RX Error Flag */ +#define UCADDR (0x0002) /* USCI Address received Flag */ +#define UCBUSY (0x0001) /* USCI Busy Flag */ +#define UCIDLE (0x0002) /* USCI Idle line detected Flag */ + +/* UCBxSTATW I2C Control Bits */ +#define UCBCNT7 (0x8000) /* USCI Byte Counter Bit 7 */ +#define UCBCNT6 (0x4000) /* USCI Byte Counter Bit 6 */ +#define UCBCNT5 (0x2000) /* USCI Byte Counter Bit 5 */ +#define UCBCNT4 (0x1000) /* USCI Byte Counter Bit 4 */ +#define UCBCNT3 (0x0800) /* USCI Byte Counter Bit 3 */ +#define UCBCNT2 (0x0400) /* USCI Byte Counter Bit 2 */ +#define UCBCNT1 (0x0200) /* USCI Byte Counter Bit 1 */ +#define UCBCNT0 (0x0100) /* USCI Byte Counter Bit 0 */ +#define UCSCLLOW (0x0040) /* SCL low */ +#define UCGC (0x0020) /* General Call address received Flag */ +#define UCBBUSY (0x0010) /* Bus Busy Flag */ + +/* UCBxTBCNT I2C Control Bits */ +#define UCTBCNT7 (0x0080) /* USCI Byte Counter Bit 7 */ +#define UCTBCNT6 (0x0040) /* USCI Byte Counter Bit 6 */ +#define UCTBCNT5 (0x0020) /* USCI Byte Counter Bit 5 */ +#define UCTBCNT4 (0x0010) /* USCI Byte Counter Bit 4 */ +#define UCTBCNT3 (0x0008) /* USCI Byte Counter Bit 3 */ +#define UCTBCNT2 (0x0004) /* USCI Byte Counter Bit 2 */ +#define UCTBCNT1 (0x0002) /* USCI Byte Counter Bit 1 */ +#define UCTBCNT0 (0x0001) /* USCI Byte Counter Bit 0 */ + +/* UCAxIRCTL Control Bits */ +#define UCIRRXFL5 (0x8000) /* IRDA Receive Filter Length 5 */ +#define UCIRRXFL4 (0x4000) /* IRDA Receive Filter Length 4 */ +#define UCIRRXFL3 (0x2000) /* IRDA Receive Filter Length 3 */ +#define UCIRRXFL2 (0x1000) /* IRDA Receive Filter Length 2 */ +#define UCIRRXFL1 (0x0800) /* IRDA Receive Filter Length 1 */ +#define UCIRRXFL0 (0x0400) /* IRDA Receive Filter Length 0 */ +#define UCIRRXPL (0x0200) /* IRDA Receive Input Polarity */ +#define UCIRRXFE (0x0100) /* IRDA Receive Filter enable */ +#define UCIRTXPL5 (0x0080) /* IRDA Transmit Pulse Length 5 */ +#define UCIRTXPL4 (0x0040) /* IRDA Transmit Pulse Length 4 */ +#define UCIRTXPL3 (0x0020) /* IRDA Transmit Pulse Length 3 */ +#define UCIRTXPL2 (0x0010) /* IRDA Transmit Pulse Length 2 */ +#define UCIRTXPL1 (0x0008) /* IRDA Transmit Pulse Length 1 */ +#define UCIRTXPL0 (0x0004) /* IRDA Transmit Pulse Length 0 */ +#define UCIRTXCLK (0x0002) /* IRDA Transmit Pulse Clock Select */ +#define UCIREN (0x0001) /* IRDA Encoder/Decoder enable */ + +/* UCAxIRCTL Control Bits */ +#define UCIRTXPL5_L (0x0080) /* IRDA Transmit Pulse Length 5 */ +#define UCIRTXPL4_L (0x0040) /* IRDA Transmit Pulse Length 4 */ +#define UCIRTXPL3_L (0x0020) /* IRDA Transmit Pulse Length 3 */ +#define UCIRTXPL2_L (0x0010) /* IRDA Transmit Pulse Length 2 */ +#define UCIRTXPL1_L (0x0008) /* IRDA Transmit Pulse Length 1 */ +#define UCIRTXPL0_L (0x0004) /* IRDA Transmit Pulse Length 0 */ +#define UCIRTXCLK_L (0x0002) /* IRDA Transmit Pulse Clock Select */ +#define UCIREN_L (0x0001) /* IRDA Encoder/Decoder enable */ + +/* UCAxIRCTL Control Bits */ +#define UCIRRXFL5_H (0x0080) /* IRDA Receive Filter Length 5 */ +#define UCIRRXFL4_H (0x0040) /* IRDA Receive Filter Length 4 */ +#define UCIRRXFL3_H (0x0020) /* IRDA Receive Filter Length 3 */ +#define UCIRRXFL2_H (0x0010) /* IRDA Receive Filter Length 2 */ +#define UCIRRXFL1_H (0x0008) /* IRDA Receive Filter Length 1 */ +#define UCIRRXFL0_H (0x0004) /* IRDA Receive Filter Length 0 */ +#define UCIRRXPL_H (0x0002) /* IRDA Receive Input Polarity */ +#define UCIRRXFE_H (0x0001) /* IRDA Receive Filter enable */ + +/* UCAxABCTL Control Bits */ +//#define res (0x80) /* reserved */ +//#define res (0x40) /* reserved */ +#define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */ +#define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */ +#define UCSTOE (0x08) /* Sync-Field Timeout error */ +#define UCBTOE (0x04) /* Break Timeout error */ +//#define res (0x02) /* reserved */ +#define UCABDEN (0x01) /* Auto Baud Rate detect enable */ + +/* UCBxI2COA0 Control Bits */ +#define UCGCEN (0x8000) /* I2C General Call enable */ +#define UCOAEN (0x0400) /* I2C Own Address enable */ +#define UCOA9 (0x0200) /* I2C Own Address Bit 9 */ +#define UCOA8 (0x0100) /* I2C Own Address Bit 8 */ +#define UCOA7 (0x0080) /* I2C Own Address Bit 7 */ +#define UCOA6 (0x0040) /* I2C Own Address Bit 6 */ +#define UCOA5 (0x0020) /* I2C Own Address Bit 5 */ +#define UCOA4 (0x0010) /* I2C Own Address Bit 4 */ +#define UCOA3 (0x0008) /* I2C Own Address Bit 3 */ +#define UCOA2 (0x0004) /* I2C Own Address Bit 2 */ +#define UCOA1 (0x0002) /* I2C Own Address Bit 1 */ +#define UCOA0 (0x0001) /* I2C Own Address Bit 0 */ + +/* UCBxI2COA0 Control Bits */ +#define UCOA7_L (0x0080) /* I2C Own Address Bit 7 */ +#define UCOA6_L (0x0040) /* I2C Own Address Bit 6 */ +#define UCOA5_L (0x0020) /* I2C Own Address Bit 5 */ +#define UCOA4_L (0x0010) /* I2C Own Address Bit 4 */ +#define UCOA3_L (0x0008) /* I2C Own Address Bit 3 */ +#define UCOA2_L (0x0004) /* I2C Own Address Bit 2 */ +#define UCOA1_L (0x0002) /* I2C Own Address Bit 1 */ +#define UCOA0_L (0x0001) /* I2C Own Address Bit 0 */ + +/* UCBxI2COA0 Control Bits */ +#define UCGCEN_H (0x0080) /* I2C General Call enable */ +#define UCOAEN_H (0x0004) /* I2C Own Address enable */ +#define UCOA9_H (0x0002) /* I2C Own Address Bit 9 */ +#define UCOA8_H (0x0001) /* I2C Own Address Bit 8 */ + +/* UCBxI2COAx Control Bits */ +#define UCOAEN (0x0400) /* I2C Own Address enable */ +#define UCOA9 (0x0200) /* I2C Own Address Bit 9 */ +#define UCOA8 (0x0100) /* I2C Own Address Bit 8 */ +#define UCOA7 (0x0080) /* I2C Own Address Bit 7 */ +#define UCOA6 (0x0040) /* I2C Own Address Bit 6 */ +#define UCOA5 (0x0020) /* I2C Own Address Bit 5 */ +#define UCOA4 (0x0010) /* I2C Own Address Bit 4 */ +#define UCOA3 (0x0008) /* I2C Own Address Bit 3 */ +#define UCOA2 (0x0004) /* I2C Own Address Bit 2 */ +#define UCOA1 (0x0002) /* I2C Own Address Bit 1 */ +#define UCOA0 (0x0001) /* I2C Own Address Bit 0 */ + +/* UCBxI2COAx Control Bits */ +#define UCOA7_L (0x0080) /* I2C Own Address Bit 7 */ +#define UCOA6_L (0x0040) /* I2C Own Address Bit 6 */ +#define UCOA5_L (0x0020) /* I2C Own Address Bit 5 */ +#define UCOA4_L (0x0010) /* I2C Own Address Bit 4 */ +#define UCOA3_L (0x0008) /* I2C Own Address Bit 3 */ +#define UCOA2_L (0x0004) /* I2C Own Address Bit 2 */ +#define UCOA1_L (0x0002) /* I2C Own Address Bit 1 */ +#define UCOA0_L (0x0001) /* I2C Own Address Bit 0 */ + +/* UCBxI2COAx Control Bits */ +#define UCOAEN_H (0x0004) /* I2C Own Address enable */ +#define UCOA9_H (0x0002) /* I2C Own Address Bit 9 */ +#define UCOA8_H (0x0001) /* I2C Own Address Bit 8 */ + +/* UCBxADDRX Control Bits */ +#define UCADDRX9 (0x0200) /* I2C Receive Address Bit 9 */ +#define UCADDRX8 (0x0100) /* I2C Receive Address Bit 8 */ +#define UCADDRX7 (0x0080) /* I2C Receive Address Bit 7 */ +#define UCADDRX6 (0x0040) /* I2C Receive Address Bit 6 */ +#define UCADDRX5 (0x0020) /* I2C Receive Address Bit 5 */ +#define UCADDRX4 (0x0010) /* I2C Receive Address Bit 4 */ +#define UCADDRX3 (0x0008) /* I2C Receive Address Bit 3 */ +#define UCADDRX2 (0x0004) /* I2C Receive Address Bit 2 */ +#define UCADDRX1 (0x0002) /* I2C Receive Address Bit 1 */ +#define UCADDRX0 (0x0001) /* I2C Receive Address Bit 0 */ + +/* UCBxADDRX Control Bits */ +#define UCADDRX7_L (0x0080) /* I2C Receive Address Bit 7 */ +#define UCADDRX6_L (0x0040) /* I2C Receive Address Bit 6 */ +#define UCADDRX5_L (0x0020) /* I2C Receive Address Bit 5 */ +#define UCADDRX4_L (0x0010) /* I2C Receive Address Bit 4 */ +#define UCADDRX3_L (0x0008) /* I2C Receive Address Bit 3 */ +#define UCADDRX2_L (0x0004) /* I2C Receive Address Bit 2 */ +#define UCADDRX1_L (0x0002) /* I2C Receive Address Bit 1 */ +#define UCADDRX0_L (0x0001) /* I2C Receive Address Bit 0 */ + +/* UCBxADDRX Control Bits */ +#define UCADDRX9_H (0x0002) /* I2C Receive Address Bit 9 */ +#define UCADDRX8_H (0x0001) /* I2C Receive Address Bit 8 */ + +/* UCBxADDMASK Control Bits */ +#define UCADDMASK9 (0x0200) /* I2C Address Mask Bit 9 */ +#define UCADDMASK8 (0x0100) /* I2C Address Mask Bit 8 */ +#define UCADDMASK7 (0x0080) /* I2C Address Mask Bit 7 */ +#define UCADDMASK6 (0x0040) /* I2C Address Mask Bit 6 */ +#define UCADDMASK5 (0x0020) /* I2C Address Mask Bit 5 */ +#define UCADDMASK4 (0x0010) /* I2C Address Mask Bit 4 */ +#define UCADDMASK3 (0x0008) /* I2C Address Mask Bit 3 */ +#define UCADDMASK2 (0x0004) /* I2C Address Mask Bit 2 */ +#define UCADDMASK1 (0x0002) /* I2C Address Mask Bit 1 */ +#define UCADDMASK0 (0x0001) /* I2C Address Mask Bit 0 */ + +/* UCBxADDMASK Control Bits */ +#define UCADDMASK7_L (0x0080) /* I2C Address Mask Bit 7 */ +#define UCADDMASK6_L (0x0040) /* I2C Address Mask Bit 6 */ +#define UCADDMASK5_L (0x0020) /* I2C Address Mask Bit 5 */ +#define UCADDMASK4_L (0x0010) /* I2C Address Mask Bit 4 */ +#define UCADDMASK3_L (0x0008) /* I2C Address Mask Bit 3 */ +#define UCADDMASK2_L (0x0004) /* I2C Address Mask Bit 2 */ +#define UCADDMASK1_L (0x0002) /* I2C Address Mask Bit 1 */ +#define UCADDMASK0_L (0x0001) /* I2C Address Mask Bit 0 */ + +/* UCBxADDMASK Control Bits */ +#define UCADDMASK9_H (0x0002) /* I2C Address Mask Bit 9 */ +#define UCADDMASK8_H (0x0001) /* I2C Address Mask Bit 8 */ + +/* UCBxI2CSA Control Bits */ +#define UCSA9 (0x0200) /* I2C Slave Address Bit 9 */ +#define UCSA8 (0x0100) /* I2C Slave Address Bit 8 */ +#define UCSA7 (0x0080) /* I2C Slave Address Bit 7 */ +#define UCSA6 (0x0040) /* I2C Slave Address Bit 6 */ +#define UCSA5 (0x0020) /* I2C Slave Address Bit 5 */ +#define UCSA4 (0x0010) /* I2C Slave Address Bit 4 */ +#define UCSA3 (0x0008) /* I2C Slave Address Bit 3 */ +#define UCSA2 (0x0004) /* I2C Slave Address Bit 2 */ +#define UCSA1 (0x0002) /* I2C Slave Address Bit 1 */ +#define UCSA0 (0x0001) /* I2C Slave Address Bit 0 */ + +/* UCBxI2CSA Control Bits */ +#define UCSA7_L (0x0080) /* I2C Slave Address Bit 7 */ +#define UCSA6_L (0x0040) /* I2C Slave Address Bit 6 */ +#define UCSA5_L (0x0020) /* I2C Slave Address Bit 5 */ +#define UCSA4_L (0x0010) /* I2C Slave Address Bit 4 */ +#define UCSA3_L (0x0008) /* I2C Slave Address Bit 3 */ +#define UCSA2_L (0x0004) /* I2C Slave Address Bit 2 */ +#define UCSA1_L (0x0002) /* I2C Slave Address Bit 1 */ +#define UCSA0_L (0x0001) /* I2C Slave Address Bit 0 */ + +/* UCBxI2CSA Control Bits */ +#define UCSA9_H (0x0002) /* I2C Slave Address Bit 9 */ +#define UCSA8_H (0x0001) /* I2C Slave Address Bit 8 */ + +/* UCAxIE UART Control Bits */ +#define UCTXCPTIE (0x0008) /* UART Transmit Complete Interrupt Enable */ +#define UCSTTIE (0x0004) /* UART Start Bit Interrupt Enalble */ +#define UCTXIE (0x0002) /* UART Transmit Interrupt Enable */ +#define UCRXIE (0x0001) /* UART Receive Interrupt Enable */ + +/* UCAxIE/UCBxIE SPI Control Bits */ + +/* UCBxIE I2C Control Bits */ +#define UCBIT9IE (0x4000) /* I2C Bit 9 Position Interrupt Enable 3 */ +#define UCTXIE3 (0x2000) /* I2C Transmit Interrupt Enable 3 */ +#define UCRXIE3 (0x1000) /* I2C Receive Interrupt Enable 3 */ +#define UCTXIE2 (0x0800) /* I2C Transmit Interrupt Enable 2 */ +#define UCRXIE2 (0x0400) /* I2C Receive Interrupt Enable 2 */ +#define UCTXIE1 (0x0200) /* I2C Transmit Interrupt Enable 1 */ +#define UCRXIE1 (0x0100) /* I2C Receive Interrupt Enable 1 */ +#define UCCLTOIE (0x0080) /* I2C Clock Low Timeout interrupt enable */ +#define UCBCNTIE (0x0040) /* I2C Automatic stop assertion interrupt enable */ +#define UCNACKIE (0x0020) /* I2C NACK Condition interrupt enable */ +#define UCALIE (0x0010) /* I2C Arbitration Lost interrupt enable */ +#define UCSTPIE (0x0008) /* I2C STOP Condition interrupt enable */ +#define UCSTTIE (0x0004) /* I2C START Condition interrupt enable */ +#define UCTXIE0 (0x0002) /* I2C Transmit Interrupt Enable 0 */ +#define UCRXIE0 (0x0001) /* I2C Receive Interrupt Enable 0 */ + +/* UCAxIFG UART Control Bits */ +#define UCTXCPTIFG (0x0008) /* UART Transmit Complete Interrupt Flag */ +#define UCSTTIFG (0x0004) /* UART Start Bit Interrupt Flag */ +#define UCTXIFG (0x0002) /* UART Transmit Interrupt Flag */ +#define UCRXIFG (0x0001) /* UART Receive Interrupt Flag */ + +/* UCAxIFG/UCBxIFG SPI Control Bits */ +#define UCTXIFG (0x0002) /* SPI Transmit Interrupt Flag */ +#define UCRXIFG (0x0001) /* SPI Receive Interrupt Flag */ + +/* UCBxIFG Control Bits */ +#define UCBIT9IFG (0x4000) /* I2C Bit 9 Possition Interrupt Flag 3 */ +#define UCTXIFG3 (0x2000) /* I2C Transmit Interrupt Flag 3 */ +#define UCRXIFG3 (0x1000) /* I2C Receive Interrupt Flag 3 */ +#define UCTXIFG2 (0x0800) /* I2C Transmit Interrupt Flag 2 */ +#define UCRXIFG2 (0x0400) /* I2C Receive Interrupt Flag 2 */ +#define UCTXIFG1 (0x0200) /* I2C Transmit Interrupt Flag 1 */ +#define UCRXIFG1 (0x0100) /* I2C Receive Interrupt Flag 1 */ +#define UCCLTOIFG (0x0080) /* I2C Clock low Timeout interrupt Flag */ +#define UCBCNTIFG (0x0040) /* I2C Byte counter interrupt flag */ +#define UCNACKIFG (0x0020) /* I2C NACK Condition interrupt Flag */ +#define UCALIFG (0x0010) /* I2C Arbitration Lost interrupt Flag */ +#define UCSTPIFG (0x0008) /* I2C STOP Condition interrupt Flag */ +#define UCSTTIFG (0x0004) /* I2C START Condition interrupt Flag */ +#define UCTXIFG0 (0x0002) /* I2C Transmit Interrupt Flag 0 */ +#define UCRXIFG0 (0x0001) /* I2C Receive Interrupt Flag 0 */ + +/* USCI UART Definitions */ +#define USCI_NONE (0x0000) /* No Interrupt pending */ +#define USCI_UART_UCRXIFG (0x0002) /* USCI UCRXIFG */ +#define USCI_UART_UCTXIFG (0x0004) /* USCI UCTXIFG */ +#define USCI_UART_UCSTTIFG (0x0006) /* USCI UCSTTIFG */ +#define USCI_UART_UCTXCPTIFG (0x0008) /* USCI UCTXCPTIFG */ + +/* USCI SPI Definitions */ +#define USCI_SPI_UCRXIFG (0x0002) /* USCI UCRXIFG */ +#define USCI_SPI_UCTXIFG (0x0004) /* USCI UCTXIFG */ + +/* USCI I2C Definitions */ +#define USCI_I2C_UCALIFG (0x0002) /* USCI I2C Mode: UCALIFG */ +#define USCI_I2C_UCNACKIFG (0x0004) /* USCI I2C Mode: UCNACKIFG */ +#define USCI_I2C_UCSTTIFG (0x0006) /* USCI I2C Mode: UCSTTIFG*/ +#define USCI_I2C_UCSTPIFG (0x0008) /* USCI I2C Mode: UCSTPIFG*/ +#define USCI_I2C_UCRXIFG3 (0x000A) /* USCI I2C Mode: UCRXIFG3 */ +#define USCI_I2C_UCTXIFG3 (0x000C) /* USCI I2C Mode: UCTXIFG3 */ +#define USCI_I2C_UCRXIFG2 (0x000E) /* USCI I2C Mode: UCRXIFG2 */ +#define USCI_I2C_UCTXIFG2 (0x0010) /* USCI I2C Mode: UCTXIFG2 */ +#define USCI_I2C_UCRXIFG1 (0x0012) /* USCI I2C Mode: UCRXIFG1 */ +#define USCI_I2C_UCTXIFG1 (0x0014) /* USCI I2C Mode: UCTXIFG1 */ +#define USCI_I2C_UCRXIFG0 (0x0016) /* USCI I2C Mode: UCRXIFG0 */ +#define USCI_I2C_UCTXIFG0 (0x0018) /* USCI I2C Mode: UCTXIFG0 */ +#define USCI_I2C_UCBCNTIFG (0x001A) /* USCI I2C Mode: UCBCNTIFG */ +#define USCI_I2C_UCCLTOIFG (0x001C) /* USCI I2C Mode: UCCLTOIFG */ +#define USCI_I2C_UCBIT9IFG (0x001E) /* USCI I2C Mode: UCBIT9IFG */ + +#endif +/************************************************************ +* WATCHDOG TIMER A +************************************************************/ +#ifdef __MSP430_HAS_WDT_A__ /* Definition to show that Module is available */ + +#define OFS_WDTCTL (0x000C) /* Watchdog Timer Control */ +#define OFS_WDTCTL_L OFS_WDTCTL +#define OFS_WDTCTL_H OFS_WDTCTL+1 +/* The bit names have been prefixed with "WDT" */ +/* WDTCTL Control Bits */ +#define WDTIS0 (0x0001) /* WDT - Timer Interval Select 0 */ +#define WDTIS1 (0x0002) /* WDT - Timer Interval Select 1 */ +#define WDTIS2 (0x0004) /* WDT - Timer Interval Select 2 */ +#define WDTCNTCL (0x0008) /* WDT - Timer Clear */ +#define WDTTMSEL (0x0010) /* WDT - Timer Mode Select */ +#define WDTSSEL0 (0x0020) /* WDT - Timer Clock Source Select 0 */ +#define WDTSSEL1 (0x0040) /* WDT - Timer Clock Source Select 1 */ +#define WDTHOLD (0x0080) /* WDT - Timer hold */ + +/* WDTCTL Control Bits */ +#define WDTIS0_L (0x0001) /* WDT - Timer Interval Select 0 */ +#define WDTIS1_L (0x0002) /* WDT - Timer Interval Select 1 */ +#define WDTIS2_L (0x0004) /* WDT - Timer Interval Select 2 */ +#define WDTCNTCL_L (0x0008) /* WDT - Timer Clear */ +#define WDTTMSEL_L (0x0010) /* WDT - Timer Mode Select */ +#define WDTSSEL0_L (0x0020) /* WDT - Timer Clock Source Select 0 */ +#define WDTSSEL1_L (0x0040) /* WDT - Timer Clock Source Select 1 */ +#define WDTHOLD_L (0x0080) /* WDT - Timer hold */ + +#define WDTPW (0x5A00) + +#define WDTIS_0 (0*0x0001u) /* WDT - Timer Interval Select: /2G */ +#define WDTIS_1 (1*0x0001u) /* WDT - Timer Interval Select: /128M */ +#define WDTIS_2 (2*0x0001u) /* WDT - Timer Interval Select: /8192k */ +#define WDTIS_3 (3*0x0001u) /* WDT - Timer Interval Select: /512k */ +#define WDTIS_4 (4*0x0001u) /* WDT - Timer Interval Select: /32k */ +#define WDTIS_5 (5*0x0001u) /* WDT - Timer Interval Select: /8192 */ +#define WDTIS_6 (6*0x0001u) /* WDT - Timer Interval Select: /512 */ +#define WDTIS_7 (7*0x0001u) /* WDT - Timer Interval Select: /64 */ +#define WDTIS__2G (0*0x0001u) /* WDT - Timer Interval Select: /2G */ +#define WDTIS__128M (1*0x0001u) /* WDT - Timer Interval Select: /128M */ +#define WDTIS__8192K (2*0x0001u) /* WDT - Timer Interval Select: /8192k */ +#define WDTIS__512K (3*0x0001u) /* WDT - Timer Interval Select: /512k */ +#define WDTIS__32K (4*0x0001u) /* WDT - Timer Interval Select: /32k */ +#define WDTIS__8192 (5*0x0001u) /* WDT - Timer Interval Select: /8192 */ +#define WDTIS__512 (6*0x0001u) /* WDT - Timer Interval Select: /512 */ +#define WDTIS__64 (7*0x0001u) /* WDT - Timer Interval Select: /64 */ + +#define WDTSSEL_0 (0*0x0020u) /* WDT - Timer Clock Source Select: SMCLK */ +#define WDTSSEL_1 (1*0x0020u) /* WDT - Timer Clock Source Select: ACLK */ +#define WDTSSEL_2 (2*0x0020u) /* WDT - Timer Clock Source Select: VLO_CLK */ +#define WDTSSEL_3 (3*0x0020u) /* WDT - Timer Clock Source Select: reserved */ +#define WDTSSEL__SMCLK (0*0x0020u) /* WDT - Timer Clock Source Select: SMCLK */ +#define WDTSSEL__ACLK (1*0x0020u) /* WDT - Timer Clock Source Select: ACLK */ +#define WDTSSEL__VLO (2*0x0020u) /* WDT - Timer Clock Source Select: VLO_CLK */ + +/* WDT-interval times [1ms] coded with Bits 0-2 */ +/* WDT is clocked by fSMCLK (assumed 1MHz) */ +#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2) /* 32ms interval (default) */ +#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */ +#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */ +#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */ +/* WDT is clocked by fACLK (assumed 32KHz) */ +#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0) /* 1000ms " */ +#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0) /* 250ms " */ +#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1) /* 16ms " */ +#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0) /* 1.9ms " */ +/* Watchdog mode -> reset after expired time */ +/* WDT is clocked by fSMCLK (assumed 1MHz) */ +#define WDT_MRST_32 (WDTPW+WDTCNTCL+WDTIS2) /* 32ms interval (default) */ +#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */ +#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */ +#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */ +/* WDT is clocked by fACLK (assumed 32KHz) */ +#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2) /* 1000ms " */ +#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0) /* 250ms " */ +#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1) /* 16ms " */ +#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0) /* 1.9ms " */ + +#endif + +/************************************************************ +* TLV Descriptors +************************************************************/ +#define __MSP430_HAS_TLV__ /* Definition to show that Module is available */ +#define TLV_BASE __MSP430_BASEADDRESS_TLV__ + +#define TLV_START (0x1A08) /* Start Address of the TLV structure */ +#define TLV_END (0x1AFF) /* End Address of the TLV structure */ + +#define TLV_LDTAG (0x01) /* Legacy descriptor (1xx, 2xx, 4xx families) */ +#define TLV_PDTAG (0x02) /* Peripheral discovery descriptor */ +#define TLV_Reserved3 (0x03) /* Future usage */ +#define TLV_Reserved4 (0x04) /* Future usage */ +#define TLV_BLANK (0x05) /* Blank descriptor */ +#define TLV_Reserved6 (0x06) /* Future usage */ +#define TLV_Reserved7 (0x07) /* Serial Number */ +#define TLV_DIERECORD (0x08) /* Die Record */ +#define TLV_ADCCAL (0x11) /* ADC12 calibration */ +#define TLV_ADC12CAL (0x11) /* ADC12 calibration */ +#define TLV_REFCAL (0x12) /* REF calibration */ +#define TLV_ADC10CAL (0x13) /* ADC10 calibration */ +#define TLV_TIMERDCAL (0x15) /* TIMER_D calibration */ +#define TLV_TAGEXT (0xFE) /* Tag extender */ +#define TLV_TAGEND (0xFF) /* Tag End of Table */ + +/************************************************************ +* Interrupt Vectors (offset from 0xFF80) +************************************************************/ + +#pragma diag_suppress 1107 +#define VECTOR_NAME(name) name##_ptr +#define EMIT_PRAGMA(x) _Pragma(#x) +#define CREATE_VECTOR(name) void * const VECTOR_NAME(name) = (void *)(long)&name +#define PLACE_VECTOR(vector,section) EMIT_PRAGMA(DATA_SECTION(vector,section)) +#define PLACE_INTERRUPT(func) EMIT_PRAGMA(CODE_SECTION(func,".text:_isr")) +#define ISR_VECTOR(func,offset) CREATE_VECTOR(func); \ + PLACE_VECTOR(VECTOR_NAME(func), offset) \ + PLACE_INTERRUPT(func) + + +/************************************************************ +* End of Modules +************************************************************/ + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif /* #ifndef __msp430FR5XX_FR6XXGENERIC */ + diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/deprecated/IAR/msp430fr5xx_6xxgeneric.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/deprecated/IAR/msp430fr5xx_6xxgeneric.h new file mode 100644 index 000000000..35d39cf5f --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/deprecated/IAR/msp430fr5xx_6xxgeneric.h @@ -0,0 +1,6573 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +/******************************************************************** +* +* Standard register and bit definitions for the Texas Instruments +* MSP430 microcontroller. +* +* This file supports assembler and C development for +* MSP430FR5XX_FR6XXGENERIC device. +* +* Texas Instruments, Version 1.0 +* +* Rev. 1.0, Setup +* +* +********************************************************************/ + +#ifndef __msp430FR5XX_FR6XXGENERIC +#define __msp430FR5XX_FR6XXGENERIC + +//#define __MSP430_HEADER_VERSION__ 1125 + +#ifdef __IAR_SYSTEMS_ICC__ +#ifndef _SYSTEM_BUILD +#pragma system_include +#endif +#endif + +#if (((__TID__ >> 8) & 0x7F) != 0x2b) /* 0x2b = 43 dec */ +#error msp430fr5xx_6xxgeneric.h file for use with ICC430/A430 only +#endif + + +#ifdef __IAR_SYSTEMS_ICC__ +#include "in430.h" +#pragma language=extended + +#define DEFC(name, address) __no_init volatile unsigned char name @ address; +#define DEFW(name, address) __no_init volatile unsigned short name @ address; + +#define DEFCW(name, address) __no_init union \ +{ \ + struct \ + { \ + volatile unsigned char name##_L; \ + volatile unsigned char name##_H; \ + }; \ + volatile unsigned short name; \ +} @ address; + +#define READ_ONLY_DEFCW(name, address) __no_init union \ +{ \ + struct \ + { \ + volatile READ_ONLY unsigned char name##_L; \ + volatile READ_ONLY unsigned char name##_H; \ + }; \ + volatile READ_ONLY unsigned short name; \ +} @ address; + + +#if __REGISTER_MODEL__ == __REGISTER_MODEL_REG20__ +#define __ACCESS_20BIT_REG__ void __data20 * volatile +#else +#define __ACCESS_20BIT_REG__ volatile unsigned short /* only short access from C is allowed in small memory model */ +#endif + +#define DEFA(name, address) __no_init union \ +{ \ + struct \ + { \ + volatile unsigned char name##_L; \ + volatile unsigned char name##_H; \ + }; \ + struct \ + { \ + volatile unsigned short name##L; \ + volatile unsigned short name##H; \ + }; \ + __ACCESS_20BIT_REG__ name; \ +} @ address; + +#endif /* __IAR_SYSTEMS_ICC__ */ + + +#ifdef __IAR_SYSTEMS_ASM__ +#define DEFC(name, address) sfrb name = address; +#define DEFW(name, address) sfrw name = address; + +#define DEFCW(name, address) sfrbw name, name##_L, name##_H, address; +sfrbw macro name, name_L, name_H, address; +sfrb name_L = address; +sfrb name_H = address+1; +sfrw name = address; + endm + +#define READ_ONLY_DEFCW(name, address) const_sfrbw name, name##_L, name##_H, address; +const_sfrbw macro name, name_L, name_H, address; +const sfrb name_L = address; +const sfrb name_H = address+1; +const sfrw name = address; + endm + +#define DEFA(name, address) sfrba name, name##L, name##H, name##_L, name##_H, address; +sfrba macro name, nameL, nameH, name_L, name_H, address; +sfrb name_L = address; +sfrb name_H = address+1; +sfrw nameL = address; +sfrw nameH = address+2; +sfrl name = address; + endm + +#endif /* __IAR_SYSTEMS_ASM__*/ + +#ifdef __cplusplus +#define READ_ONLY +#else +#define READ_ONLY const +#endif + +/************************************************************ +* STANDARD BITS +************************************************************/ + +#define BIT0 (0x0001u) +#define BIT1 (0x0002u) +#define BIT2 (0x0004u) +#define BIT3 (0x0008u) +#define BIT4 (0x0010u) +#define BIT5 (0x0020u) +#define BIT6 (0x0040u) +#define BIT7 (0x0080u) +#define BIT8 (0x0100u) +#define BIT9 (0x0200u) +#define BITA (0x0400u) +#define BITB (0x0800u) +#define BITC (0x1000u) +#define BITD (0x2000u) +#define BITE (0x4000u) +#define BITF (0x8000u) + +/************************************************************ +* STATUS REGISTER BITS +************************************************************/ + +#define C (0x0001u) +#define Z (0x0002u) +#define N (0x0004u) +#define V (0x0100u) +#define GIE (0x0008u) +#define CPUOFF (0x0010u) +#define OSCOFF (0x0020u) +#define SCG0 (0x0040u) +#define SCG1 (0x0080u) + +/* Low Power Modes coded with Bits 4-7 in SR */ + +#ifndef __IAR_SYSTEMS_ICC__ /* Begin #defines for assembler */ +#define LPM0 (CPUOFF) +#define LPM1 (SCG0+CPUOFF) +#define LPM2 (SCG1+CPUOFF) +#define LPM3 (SCG1+SCG0+CPUOFF) +#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF) +/* End #defines for assembler */ + +#else /* Begin #defines for C */ +#define LPM0_bits (CPUOFF) +#define LPM1_bits (SCG0+CPUOFF) +#define LPM2_bits (SCG1+CPUOFF) +#define LPM3_bits (SCG1+SCG0+CPUOFF) +#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF) + +#include "in430.h" + +#if __MSP430_HEADER_VERSION__ < 1107 +#define LPM0 _BIS_SR(LPM0_bits) /* Enter Low Power Mode 0 */ +#define LPM0_EXIT _BIC_SR_IRQ(LPM0_bits) /* Exit Low Power Mode 0 */ +#define LPM1 _BIS_SR(LPM1_bits) /* Enter Low Power Mode 1 */ +#define LPM1_EXIT _BIC_SR_IRQ(LPM1_bits) /* Exit Low Power Mode 1 */ +#define LPM2 _BIS_SR(LPM2_bits) /* Enter Low Power Mode 2 */ +#define LPM2_EXIT _BIC_SR_IRQ(LPM2_bits) /* Exit Low Power Mode 2 */ +#define LPM3 _BIS_SR(LPM3_bits) /* Enter Low Power Mode 3 */ +#define LPM3_EXIT _BIC_SR_IRQ(LPM3_bits) /* Exit Low Power Mode 3 */ +#define LPM4 _BIS_SR(LPM4_bits) /* Enter Low Power Mode 4 */ +#define LPM4_EXIT _BIC_SR_IRQ(LPM4_bits) /* Exit Low Power Mode 4 */ +#else +#define LPM0 __bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */ +#define LPM0_EXIT __bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */ +#define LPM1 __bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */ +#define LPM1_EXIT __bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */ +#define LPM2 __bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */ +#define LPM2_EXIT __bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */ +#define LPM3 __bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */ +#define LPM3_EXIT __bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */ +#define LPM4 __bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */ +#define LPM4_EXIT __bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */ +#endif +#endif /* End #defines for C */ + +/************************************************************ +* CPU +************************************************************/ +#define __MSP430_HAS_MSP430XV2_CPU__ /* Definition to show that it has MSP430XV2 CPU */ + +#if defined(__MSP430_HAS_T0A2__) || defined(__MSP430_HAS_T1A2__) || defined(__MSP430_HAS_T2A2__) || defined(__MSP430_HAS_T3A2__) \ + || defined(__MSP430_HAS_T0A3__) || defined(__MSP430_HAS_T1A3__) || defined(__MSP430_HAS_T2A3__) || defined(__MSP430_HAS_T3A3__) \ + || defined(__MSP430_HAS_T0A5__) || defined(__MSP430_HAS_T1A5__) || defined(__MSP430_HAS_T2A5__) || defined(__MSP430_HAS_T3A5__) \ + || defined(__MSP430_HAS_T0A7__) || defined(__MSP430_HAS_T1A7__) || defined(__MSP430_HAS_T2A7__) || defined(__MSP430_HAS_T3A7__) + #define __MSP430_HAS_TxA7__ +#endif +#if defined(__MSP430_HAS_T0B3__) || defined(__MSP430_HAS_T0B5__) || defined(__MSP430_HAS_T0B7__) \ + || defined(__MSP430_HAS_T1B3__) || defined(__MSP430_HAS_T1B5__) || defined(__MSP430_HAS_T1B7__) + #define __MSP430_HAS_TxB7__ +#endif +#if defined(__MSP430_HAS_T0D3__) || defined(__MSP430_HAS_T0D5__) || defined(__MSP430_HAS_T0D7__) \ + || defined(__MSP430_HAS_T1D3__) || defined(__MSP430_HAS_T1D5__) || defined(__MSP430_HAS_T1D7__) + #define __MSP430_HAS_TxD7__ +#endif +#if defined(__MSP430_HAS_USCI_A0__) || defined(__MSP430_HAS_USCI_A1__) || defined(__MSP430_HAS_USCI_A2__) || defined(__MSP430_HAS_USCI_A3__) + #define __MSP430_HAS_USCI_Ax__ +#endif +#if defined(__MSP430_HAS_USCI_B0__) || defined(__MSP430_HAS_USCI_B1__) || defined(__MSP430_HAS_USCI_B2__) || defined(__MSP430_HAS_USCI_B3__) + #define __MSP430_HAS_USCI_Bx__ +#endif +#if defined(__MSP430_HAS_EUSCI_A0__) || defined(__MSP430_HAS_EUSCI_A1__) || defined(__MSP430_HAS_EUSCI_A2__) || defined(__MSP430_HAS_EUSCI_A3__) + #define __MSP430_HAS_EUSCI_Ax__ +#endif +#if defined(__MSP430_HAS_EUSCI_B0__) || defined(__MSP430_HAS_EUSCI_B1__) || defined(__MSP430_HAS_EUSCI_B2__) || defined(__MSP430_HAS_EUSCI_B3__) + #define __MSP430_HAS_EUSCI_Bx__ +#endif +#ifdef __MSP430_HAS_EUSCI_B0__ + #define __MSP430_HAS_EUSCI_Bx__ +#endif + +/************************************************************ +* ADC12_B +************************************************************/ +#ifdef __MSP430_HAS_ADC12_B__ /* Definition to show that Module is available */ + +#define OFS_ADC12CTL0 (0x0000u) /* ADC12 B Control 0 */ +#define OFS_ADC12CTL0_L OFS_ADC12CTL0 +#define OFS_ADC12CTL0_H OFS_ADC12CTL0+1 +#define OFS_ADC12CTL1 (0x0002u) /* ADC12 B Control 1 */ +#define OFS_ADC12CTL1_L OFS_ADC12CTL1 +#define OFS_ADC12CTL1_H OFS_ADC12CTL1+1 +#define OFS_ADC12CTL2 (0x0004u) /* ADC12 B Control 2 */ +#define OFS_ADC12CTL2_L OFS_ADC12CTL2 +#define OFS_ADC12CTL2_H OFS_ADC12CTL2+1 +#define OFS_ADC12CTL3 (0x0006u) /* ADC12 B Control 3 */ +#define OFS_ADC12CTL3_L OFS_ADC12CTL3 +#define OFS_ADC12CTL3_H OFS_ADC12CTL3+1 +#define OFS_ADC12LO (0x0008u) /* ADC12 B Window Comparator High Threshold */ +#define OFS_ADC12LO_L OFS_ADC12LO +#define OFS_ADC12LO_H OFS_ADC12LO+1 +#define OFS_ADC12HI (0x000Au) /* ADC12 B Window Comparator High Threshold */ +#define OFS_ADC12HI_L OFS_ADC12HI +#define OFS_ADC12HI_H OFS_ADC12HI+1 +#define OFS_ADC12IFGR0 (0x000Cu) /* ADC12 B Interrupt Flag 0 */ +#define OFS_ADC12IFGR0_L OFS_ADC12IFGR0 +#define OFS_ADC12IFGR0_H OFS_ADC12IFGR0+1 +#define OFS_ADC12IFGR1 (0x000Eu) /* ADC12 B Interrupt Flag 1 */ +#define OFS_ADC12IFGR1_L OFS_ADC12IFGR1 +#define OFS_ADC12IFGR1_H OFS_ADC12IFGR1+1 +#define OFS_ADC12IFGR2 (0x0010u) /* ADC12 B Interrupt Flag 2 */ +#define OFS_ADC12IFGR2_L OFS_ADC12IFGR2 +#define OFS_ADC12IFGR2_H OFS_ADC12IFGR2+1 +#define OFS_ADC12IER0 (0x0012u) /* ADC12 B Interrupt Enable 0 */ +#define OFS_ADC12IER0_L OFS_ADC12IER0 +#define OFS_ADC12IER0_H OFS_ADC12IER0+1 +#define OFS_ADC12IER1 (0x0014u) /* ADC12 B Interrupt Enable 1 */ +#define OFS_ADC12IER1_L OFS_ADC12IER1 +#define OFS_ADC12IER1_H OFS_ADC12IER1+1 +#define OFS_ADC12IER2 (0x0016u) /* ADC12 B Interrupt Enable 2 */ +#define OFS_ADC12IER2_L OFS_ADC12IER2 +#define OFS_ADC12IER2_H OFS_ADC12IER2+1 +#define OFS_ADC12IV (0x0018u) /* ADC12 B Interrupt Vector Word */ +#define OFS_ADC12IV_L OFS_ADC12IV +#define OFS_ADC12IV_H OFS_ADC12IV+1 + +#define OFS_ADC12MCTL0 (0x0020u) /* ADC12 Memory Control 0 */ +#define OFS_ADC12MCTL0_L OFS_ADC12MCTL0 +#define OFS_ADC12MCTL0_H OFS_ADC12MCTL0+1 +#define OFS_ADC12MCTL1 (0x0022u) /* ADC12 Memory Control 1 */ +#define OFS_ADC12MCTL1_L OFS_ADC12MCTL1 +#define OFS_ADC12MCTL1_H OFS_ADC12MCTL1+1 +#define OFS_ADC12MCTL2 (0x0024u) /* ADC12 Memory Control 2 */ +#define OFS_ADC12MCTL2_L OFS_ADC12MCTL2 +#define OFS_ADC12MCTL2_H OFS_ADC12MCTL2+1 +#define OFS_ADC12MCTL3 (0x0026u) /* ADC12 Memory Control 3 */ +#define OFS_ADC12MCTL3_L OFS_ADC12MCTL3 +#define OFS_ADC12MCTL3_H OFS_ADC12MCTL3+1 +#define OFS_ADC12MCTL4 (0x0028u) /* ADC12 Memory Control 4 */ +#define OFS_ADC12MCTL4_L OFS_ADC12MCTL4 +#define OFS_ADC12MCTL4_H OFS_ADC12MCTL4+1 +#define OFS_ADC12MCTL5 (0x002Au) /* ADC12 Memory Control 5 */ +#define OFS_ADC12MCTL5_L OFS_ADC12MCTL5 +#define OFS_ADC12MCTL5_H OFS_ADC12MCTL5+1 +#define OFS_ADC12MCTL6 (0x002Cu) /* ADC12 Memory Control 6 */ +#define OFS_ADC12MCTL6_L OFS_ADC12MCTL6 +#define OFS_ADC12MCTL6_H OFS_ADC12MCTL6+1 +#define OFS_ADC12MCTL7 (0x002Eu) /* ADC12 Memory Control 7 */ +#define OFS_ADC12MCTL7_L OFS_ADC12MCTL7 +#define OFS_ADC12MCTL7_H OFS_ADC12MCTL7+1 +#define OFS_ADC12MCTL8 (0x0030u) /* ADC12 Memory Control 8 */ +#define OFS_ADC12MCTL8_L OFS_ADC12MCTL8 +#define OFS_ADC12MCTL8_H OFS_ADC12MCTL8+1 +#define OFS_ADC12MCTL9 (0x0032u) /* ADC12 Memory Control 9 */ +#define OFS_ADC12MCTL9_L OFS_ADC12MCTL9 +#define OFS_ADC12MCTL9_H OFS_ADC12MCTL9+1 +#define OFS_ADC12MCTL10 (0x0034u) /* ADC12 Memory Control 10 */ +#define OFS_ADC12MCTL10_L OFS_ADC12MCTL10 +#define OFS_ADC12MCTL10_H OFS_ADC12MCTL10+1 +#define OFS_ADC12MCTL11 (0x0036u) /* ADC12 Memory Control 11 */ +#define OFS_ADC12MCTL11_L OFS_ADC12MCTL11 +#define OFS_ADC12MCTL11_H OFS_ADC12MCTL11+1 +#define OFS_ADC12MCTL12 (0x0038u) /* ADC12 Memory Control 12 */ +#define OFS_ADC12MCTL12_L OFS_ADC12MCTL12 +#define OFS_ADC12MCTL12_H OFS_ADC12MCTL12+1 +#define OFS_ADC12MCTL13 (0x003Au) /* ADC12 Memory Control 13 */ +#define OFS_ADC12MCTL13_L OFS_ADC12MCTL13 +#define OFS_ADC12MCTL13_H OFS_ADC12MCTL13+1 +#define OFS_ADC12MCTL14 (0x003Cu) /* ADC12 Memory Control 14 */ +#define OFS_ADC12MCTL14_L OFS_ADC12MCTL14 +#define OFS_ADC12MCTL14_H OFS_ADC12MCTL14+1 +#define OFS_ADC12MCTL15 (0x003Eu) /* ADC12 Memory Control 15 */ +#define OFS_ADC12MCTL15_L OFS_ADC12MCTL15 +#define OFS_ADC12MCTL15_H OFS_ADC12MCTL15+1 +#define OFS_ADC12MCTL16 (0x0040u) /* ADC12 Memory Control 16 */ +#define OFS_ADC12MCTL16_L OFS_ADC12MCTL16 +#define OFS_ADC12MCTL16_H OFS_ADC12MCTL16+1 +#define OFS_ADC12MCTL17 (0x0042u) /* ADC12 Memory Control 17 */ +#define OFS_ADC12MCTL17_L OFS_ADC12MCTL17 +#define OFS_ADC12MCTL17_H OFS_ADC12MCTL17+1 +#define OFS_ADC12MCTL18 (0x0044u) /* ADC12 Memory Control 18 */ +#define OFS_ADC12MCTL18_L OFS_ADC12MCTL18 +#define OFS_ADC12MCTL18_H OFS_ADC12MCTL18+1 +#define OFS_ADC12MCTL19 (0x0046u) /* ADC12 Memory Control 19 */ +#define OFS_ADC12MCTL19_L OFS_ADC12MCTL19 +#define OFS_ADC12MCTL19_H OFS_ADC12MCTL19+1 +#define OFS_ADC12MCTL20 (0x0048u) /* ADC12 Memory Control 20 */ +#define OFS_ADC12MCTL20_L OFS_ADC12MCTL20 +#define OFS_ADC12MCTL20_H OFS_ADC12MCTL20+1 +#define OFS_ADC12MCTL21 (0x004Au) /* ADC12 Memory Control 21 */ +#define OFS_ADC12MCTL21_L OFS_ADC12MCTL21 +#define OFS_ADC12MCTL21_H OFS_ADC12MCTL21+1 +#define OFS_ADC12MCTL22 (0x004Cu) /* ADC12 Memory Control 22 */ +#define OFS_ADC12MCTL22_L OFS_ADC12MCTL22 +#define OFS_ADC12MCTL22_H OFS_ADC12MCTL22+1 +#define OFS_ADC12MCTL23 (0x004Eu) /* ADC12 Memory Control 23 */ +#define OFS_ADC12MCTL23_L OFS_ADC12MCTL23 +#define OFS_ADC12MCTL23_H OFS_ADC12MCTL23+1 +#define OFS_ADC12MCTL24 (0x0050u) /* ADC12 Memory Control 24 */ +#define OFS_ADC12MCTL24_L OFS_ADC12MCTL24 +#define OFS_ADC12MCTL24_H OFS_ADC12MCTL24+1 +#define OFS_ADC12MCTL25 (0x0052u) /* ADC12 Memory Control 25 */ +#define OFS_ADC12MCTL25_L OFS_ADC12MCTL25 +#define OFS_ADC12MCTL25_H OFS_ADC12MCTL25+1 +#define OFS_ADC12MCTL26 (0x0054u) /* ADC12 Memory Control 26 */ +#define OFS_ADC12MCTL26_L OFS_ADC12MCTL26 +#define OFS_ADC12MCTL26_H OFS_ADC12MCTL26+1 +#define OFS_ADC12MCTL27 (0x0056u) /* ADC12 Memory Control 27 */ +#define OFS_ADC12MCTL27_L OFS_ADC12MCTL27 +#define OFS_ADC12MCTL27_H OFS_ADC12MCTL27+1 +#define OFS_ADC12MCTL28 (0x0058u) /* ADC12 Memory Control 28 */ +#define OFS_ADC12MCTL28_L OFS_ADC12MCTL28 +#define OFS_ADC12MCTL28_H OFS_ADC12MCTL28+1 +#define OFS_ADC12MCTL29 (0x005Au) /* ADC12 Memory Control 29 */ +#define OFS_ADC12MCTL29_L OFS_ADC12MCTL29 +#define OFS_ADC12MCTL29_H OFS_ADC12MCTL29+1 +#define OFS_ADC12MCTL30 (0x005Cu) /* ADC12 Memory Control 30 */ +#define OFS_ADC12MCTL30_L OFS_ADC12MCTL30 +#define OFS_ADC12MCTL30_H OFS_ADC12MCTL30+1 +#define OFS_ADC12MCTL31 (0x005Eu) /* ADC12 Memory Control 31 */ +#define OFS_ADC12MCTL31_L OFS_ADC12MCTL31 +#define OFS_ADC12MCTL31_H OFS_ADC12MCTL31+1 +#define ADC12MCTL_ ADC12MCTL /* ADC12 Memory Control */ +#ifndef __IAR_SYSTEMS_ICC__ +#define ADC12MCTL ADC12MCTL0 /* ADC12 Memory Control (for assembler) */ +#else +#define ADC12MCTL ((char*) &ADC12MCTL0) /* ADC12 Memory Control (for C) */ +#endif + +#define OFS_ADC12MEM0 (0x0060u) /* ADC12 Conversion Memory 0 */ +#define OFS_ADC12MEM0_L OFS_ADC12MEM0 +#define OFS_ADC12MEM0_H OFS_ADC12MEM0+1 +#define OFS_ADC12MEM1 (0x0062u) /* ADC12 Conversion Memory 1 */ +#define OFS_ADC12MEM1_L OFS_ADC12MEM1 +#define OFS_ADC12MEM1_H OFS_ADC12MEM1+1 +#define OFS_ADC12MEM2 (0x0064u) /* ADC12 Conversion Memory 2 */ +#define OFS_ADC12MEM2_L OFS_ADC12MEM2 +#define OFS_ADC12MEM2_H OFS_ADC12MEM2+1 +#define OFS_ADC12MEM3 (0x0066u) /* ADC12 Conversion Memory 3 */ +#define OFS_ADC12MEM3_L OFS_ADC12MEM3 +#define OFS_ADC12MEM3_H OFS_ADC12MEM3+1 +#define OFS_ADC12MEM4 (0x0068u) /* ADC12 Conversion Memory 4 */ +#define OFS_ADC12MEM4_L OFS_ADC12MEM4 +#define OFS_ADC12MEM4_H OFS_ADC12MEM4+1 +#define OFS_ADC12MEM5 (0x006Au) /* ADC12 Conversion Memory 5 */ +#define OFS_ADC12MEM5_L OFS_ADC12MEM5 +#define OFS_ADC12MEM5_H OFS_ADC12MEM5+1 +#define OFS_ADC12MEM6 (0x006Cu) /* ADC12 Conversion Memory 6 */ +#define OFS_ADC12MEM6_L OFS_ADC12MEM6 +#define OFS_ADC12MEM6_H OFS_ADC12MEM6+1 +#define OFS_ADC12MEM7 (0x006Eu) /* ADC12 Conversion Memory 7 */ +#define OFS_ADC12MEM7_L OFS_ADC12MEM7 +#define OFS_ADC12MEM7_H OFS_ADC12MEM7+1 +#define OFS_ADC12MEM8 (0x0070u) /* ADC12 Conversion Memory 8 */ +#define OFS_ADC12MEM8_L OFS_ADC12MEM8 +#define OFS_ADC12MEM8_H OFS_ADC12MEM8+1 +#define OFS_ADC12MEM9 (0x0072u) /* ADC12 Conversion Memory 9 */ +#define OFS_ADC12MEM9_L OFS_ADC12MEM9 +#define OFS_ADC12MEM9_H OFS_ADC12MEM9+1 +#define OFS_ADC12MEM10 (0x0074u) /* ADC12 Conversion Memory 10 */ +#define OFS_ADC12MEM10_L OFS_ADC12MEM10 +#define OFS_ADC12MEM10_H OFS_ADC12MEM10+1 +#define OFS_ADC12MEM11 (0x0076u) /* ADC12 Conversion Memory 11 */ +#define OFS_ADC12MEM11_L OFS_ADC12MEM11 +#define OFS_ADC12MEM11_H OFS_ADC12MEM11+1 +#define OFS_ADC12MEM12 (0x0078u) /* ADC12 Conversion Memory 12 */ +#define OFS_ADC12MEM12_L OFS_ADC12MEM12 +#define OFS_ADC12MEM12_H OFS_ADC12MEM12+1 +#define OFS_ADC12MEM13 (0x007Au) /* ADC12 Conversion Memory 13 */ +#define OFS_ADC12MEM13_L OFS_ADC12MEM13 +#define OFS_ADC12MEM13_H OFS_ADC12MEM13+1 +#define OFS_ADC12MEM14 (0x007Cu) /* ADC12 Conversion Memory 14 */ +#define OFS_ADC12MEM14_L OFS_ADC12MEM14 +#define OFS_ADC12MEM14_H OFS_ADC12MEM14+1 +#define OFS_ADC12MEM15 (0x007Eu) /* ADC12 Conversion Memory 15 */ +#define OFS_ADC12MEM15_L OFS_ADC12MEM15 +#define OFS_ADC12MEM15_H OFS_ADC12MEM15+1 +#define OFS_ADC12MEM16 (0x0080u) /* ADC12 Conversion Memory 16 */ +#define OFS_ADC12MEM16_L OFS_ADC12MEM16 +#define OFS_ADC12MEM16_H OFS_ADC12MEM16+1 +#define OFS_ADC12MEM17 (0x0082u) /* ADC12 Conversion Memory 17 */ +#define OFS_ADC12MEM17_L OFS_ADC12MEM17 +#define OFS_ADC12MEM17_H OFS_ADC12MEM17+1 +#define OFS_ADC12MEM18 (0x0084u) /* ADC12 Conversion Memory 18 */ +#define OFS_ADC12MEM18_L OFS_ADC12MEM18 +#define OFS_ADC12MEM18_H OFS_ADC12MEM18+1 +#define OFS_ADC12MEM19 (0x0086u) /* ADC12 Conversion Memory 19 */ +#define OFS_ADC12MEM19_L OFS_ADC12MEM19 +#define OFS_ADC12MEM19_H OFS_ADC12MEM19+1 +#define OFS_ADC12MEM20 (0x0088u) /* ADC12 Conversion Memory 20 */ +#define OFS_ADC12MEM20_L OFS_ADC12MEM20 +#define OFS_ADC12MEM20_H OFS_ADC12MEM20+1 +#define OFS_ADC12MEM21 (0x008Au) /* ADC12 Conversion Memory 21 */ +#define OFS_ADC12MEM21_L OFS_ADC12MEM21 +#define OFS_ADC12MEM21_H OFS_ADC12MEM21+1 +#define OFS_ADC12MEM22 (0x008Cu) /* ADC12 Conversion Memory 22 */ +#define OFS_ADC12MEM22_L OFS_ADC12MEM22 +#define OFS_ADC12MEM22_H OFS_ADC12MEM22+1 +#define OFS_ADC12MEM23 (0x008Eu) /* ADC12 Conversion Memory 23 */ +#define OFS_ADC12MEM23_L OFS_ADC12MEM23 +#define OFS_ADC12MEM23_H OFS_ADC12MEM23+1 +#define OFS_ADC12MEM24 (0x0090u) /* ADC12 Conversion Memory 24 */ +#define OFS_ADC12MEM24_L OFS_ADC12MEM24 +#define OFS_ADC12MEM24_H OFS_ADC12MEM24+1 +#define OFS_ADC12MEM25 (0x0092u) /* ADC12 Conversion Memory 25 */ +#define OFS_ADC12MEM25_L OFS_ADC12MEM25 +#define OFS_ADC12MEM25_H OFS_ADC12MEM25+1 +#define OFS_ADC12MEM26 (0x0094u) /* ADC12 Conversion Memory 26 */ +#define OFS_ADC12MEM26_L OFS_ADC12MEM26 +#define OFS_ADC12MEM26_H OFS_ADC12MEM26+1 +#define OFS_ADC12MEM27 (0x0096u) /* ADC12 Conversion Memory 27 */ +#define OFS_ADC12MEM27_L OFS_ADC12MEM27 +#define OFS_ADC12MEM27_H OFS_ADC12MEM27+1 +#define OFS_ADC12MEM28 (0x0098u) /* ADC12 Conversion Memory 28 */ +#define OFS_ADC12MEM28_L OFS_ADC12MEM28 +#define OFS_ADC12MEM28_H OFS_ADC12MEM28+1 +#define OFS_ADC12MEM29 (0x009Au) /* ADC12 Conversion Memory 29 */ +#define OFS_ADC12MEM29_L OFS_ADC12MEM29 +#define OFS_ADC12MEM29_H OFS_ADC12MEM29+1 +#define OFS_ADC12MEM30 (0x009Cu) /* ADC12 Conversion Memory 30 */ +#define OFS_ADC12MEM30_L OFS_ADC12MEM30 +#define OFS_ADC12MEM30_H OFS_ADC12MEM30+1 +#define OFS_ADC12MEM31 (0x009Eu) /* ADC12 Conversion Memory 31 */ +#define OFS_ADC12MEM31_L OFS_ADC12MEM31 +#define OFS_ADC12MEM31_H OFS_ADC12MEM31+1 +#define ADC12MEM_ ADC12MEM /* ADC12 Conversion Memory */ +#ifndef __IAR_SYSTEMS_ICC__ +#define ADC12MEM ADC12MEM0 /* ADC12 Conversion Memory (for assembler) */ +#else +#define ADC12MEM ((int*) &ADC12MEM0) /* ADC12 Conversion Memory (for C) */ +#endif + +/* ADC12CTL0 Control Bits */ +#define ADC12SC (0x0001u) /* ADC12 Start Conversion */ +#define ADC12ENC (0x0002u) /* ADC12 Enable Conversion */ +#define ADC12ON (0x0010u) /* ADC12 On/enable */ +#define ADC12MSC (0x0080u) /* ADC12 Multiple SampleConversion */ +#define ADC12SHT00 (0x0100u) /* ADC12 Sample Hold 0 Select Bit: 0 */ +#define ADC12SHT01 (0x0200u) /* ADC12 Sample Hold 0 Select Bit: 1 */ +#define ADC12SHT02 (0x0400u) /* ADC12 Sample Hold 0 Select Bit: 2 */ +#define ADC12SHT03 (0x0800u) /* ADC12 Sample Hold 0 Select Bit: 3 */ +#define ADC12SHT10 (0x1000u) /* ADC12 Sample Hold 1 Select Bit: 0 */ +#define ADC12SHT11 (0x2000u) /* ADC12 Sample Hold 1 Select Bit: 1 */ +#define ADC12SHT12 (0x4000u) /* ADC12 Sample Hold 1 Select Bit: 2 */ +#define ADC12SHT13 (0x8000u) /* ADC12 Sample Hold 1 Select Bit: 3 */ + +/* ADC12CTL0 Control Bits */ +#define ADC12SC_L (0x0001u) /* ADC12 Start Conversion */ +#define ADC12ENC_L (0x0002u) /* ADC12 Enable Conversion */ +#define ADC12ON_L (0x0010u) /* ADC12 On/enable */ +#define ADC12MSC_L (0x0080u) /* ADC12 Multiple SampleConversion */ + +/* ADC12CTL0 Control Bits */ +#define ADC12SHT00_H (0x0001u) /* ADC12 Sample Hold 0 Select Bit: 0 */ +#define ADC12SHT01_H (0x0002u) /* ADC12 Sample Hold 0 Select Bit: 1 */ +#define ADC12SHT02_H (0x0004u) /* ADC12 Sample Hold 0 Select Bit: 2 */ +#define ADC12SHT03_H (0x0008u) /* ADC12 Sample Hold 0 Select Bit: 3 */ +#define ADC12SHT10_H (0x0010u) /* ADC12 Sample Hold 1 Select Bit: 0 */ +#define ADC12SHT11_H (0x0020u) /* ADC12 Sample Hold 1 Select Bit: 1 */ +#define ADC12SHT12_H (0x0040u) /* ADC12 Sample Hold 1 Select Bit: 2 */ +#define ADC12SHT13_H (0x0080u) /* ADC12 Sample Hold 1 Select Bit: 3 */ + +#define ADC12SHT0_0 (0*0x100u) /* ADC12 Sample Hold 0 Select Bit: 0 */ +#define ADC12SHT0_1 (1*0x100u) /* ADC12 Sample Hold 0 Select Bit: 1 */ +#define ADC12SHT0_2 (2*0x100u) /* ADC12 Sample Hold 0 Select Bit: 2 */ +#define ADC12SHT0_3 (3*0x100u) /* ADC12 Sample Hold 0 Select Bit: 3 */ +#define ADC12SHT0_4 (4*0x100u) /* ADC12 Sample Hold 0 Select Bit: 4 */ +#define ADC12SHT0_5 (5*0x100u) /* ADC12 Sample Hold 0 Select Bit: 5 */ +#define ADC12SHT0_6 (6*0x100u) /* ADC12 Sample Hold 0 Select Bit: 6 */ +#define ADC12SHT0_7 (7*0x100u) /* ADC12 Sample Hold 0 Select Bit: 7 */ +#define ADC12SHT0_8 (8*0x100u) /* ADC12 Sample Hold 0 Select Bit: 8 */ +#define ADC12SHT0_9 (9*0x100u) /* ADC12 Sample Hold 0 Select Bit: 9 */ +#define ADC12SHT0_10 (10*0x100u) /* ADC12 Sample Hold 0 Select Bit: 10 */ +#define ADC12SHT0_11 (11*0x100u) /* ADC12 Sample Hold 0 Select Bit: 11 */ +#define ADC12SHT0_12 (12*0x100u) /* ADC12 Sample Hold 0 Select Bit: 12 */ +#define ADC12SHT0_13 (13*0x100u) /* ADC12 Sample Hold 0 Select Bit: 13 */ +#define ADC12SHT0_14 (14*0x100u) /* ADC12 Sample Hold 0 Select Bit: 14 */ +#define ADC12SHT0_15 (15*0x100u) /* ADC12 Sample Hold 0 Select Bit: 15 */ + +#define ADC12SHT1_0 (0*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 0 */ +#define ADC12SHT1_1 (1*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 1 */ +#define ADC12SHT1_2 (2*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 2 */ +#define ADC12SHT1_3 (3*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 3 */ +#define ADC12SHT1_4 (4*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 4 */ +#define ADC12SHT1_5 (5*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 5 */ +#define ADC12SHT1_6 (6*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 6 */ +#define ADC12SHT1_7 (7*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 7 */ +#define ADC12SHT1_8 (8*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 8 */ +#define ADC12SHT1_9 (9*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 9 */ +#define ADC12SHT1_10 (10*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 10 */ +#define ADC12SHT1_11 (11*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 11 */ +#define ADC12SHT1_12 (12*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 12 */ +#define ADC12SHT1_13 (13*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 13 */ +#define ADC12SHT1_14 (14*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 14 */ +#define ADC12SHT1_15 (15*0x1000u) /* ADC12 Sample Hold 1 Select Bit: 15 */ + +/* ADC12CTL1 Control Bits */ +#define ADC12BUSY (0x0001u) /* ADC12 Busy */ +#define ADC12CONSEQ0 (0x0002u) /* ADC12 Conversion Sequence Select Bit: 0 */ +#define ADC12CONSEQ1 (0x0004u) /* ADC12 Conversion Sequence Select Bit: 1 */ +#define ADC12SSEL0 (0x0008u) /* ADC12 Clock Source Select Bit: 0 */ +#define ADC12SSEL1 (0x0010u) /* ADC12 Clock Source Select Bit: 1 */ +#define ADC12DIV0 (0x0020u) /* ADC12 Clock Divider Select Bit: 0 */ +#define ADC12DIV1 (0x0040u) /* ADC12 Clock Divider Select Bit: 1 */ +#define ADC12DIV2 (0x0080u) /* ADC12 Clock Divider Select Bit: 2 */ +#define ADC12ISSH (0x0100u) /* ADC12 Invert Sample Hold Signal */ +#define ADC12SHP (0x0200u) /* ADC12 Sample/Hold Pulse Mode */ +#define ADC12SHS0 (0x0400u) /* ADC12 Sample/Hold Source Bit: 0 */ +#define ADC12SHS1 (0x0800u) /* ADC12 Sample/Hold Source Bit: 1 */ +#define ADC12SHS2 (0x1000u) /* ADC12 Sample/Hold Source Bit: 2 */ +#define ADC12PDIV0 (0x2000u) /* ADC12 Predivider Bit: 0 */ +#define ADC12PDIV1 (0x4000u) /* ADC12 Predivider Bit: 1 */ + +/* ADC12CTL1 Control Bits */ +#define ADC12BUSY_L (0x0001u) /* ADC12 Busy */ +#define ADC12CONSEQ0_L (0x0002u) /* ADC12 Conversion Sequence Select Bit: 0 */ +#define ADC12CONSEQ1_L (0x0004u) /* ADC12 Conversion Sequence Select Bit: 1 */ +#define ADC12SSEL0_L (0x0008u) /* ADC12 Clock Source Select Bit: 0 */ +#define ADC12SSEL1_L (0x0010u) /* ADC12 Clock Source Select Bit: 1 */ +#define ADC12DIV0_L (0x0020u) /* ADC12 Clock Divider Select Bit: 0 */ +#define ADC12DIV1_L (0x0040u) /* ADC12 Clock Divider Select Bit: 1 */ +#define ADC12DIV2_L (0x0080u) /* ADC12 Clock Divider Select Bit: 2 */ + +/* ADC12CTL1 Control Bits */ +#define ADC12ISSH_H (0x0001u) /* ADC12 Invert Sample Hold Signal */ +#define ADC12SHP_H (0x0002u) /* ADC12 Sample/Hold Pulse Mode */ +#define ADC12SHS0_H (0x0004u) /* ADC12 Sample/Hold Source Bit: 0 */ +#define ADC12SHS1_H (0x0008u) /* ADC12 Sample/Hold Source Bit: 1 */ +#define ADC12SHS2_H (0x0010u) /* ADC12 Sample/Hold Source Bit: 2 */ +#define ADC12PDIV0_H (0x0020u) /* ADC12 Predivider Bit: 0 */ +#define ADC12PDIV1_H (0x0040u) /* ADC12 Predivider Bit: 1 */ + +#define ADC12CONSEQ_0 (0*0x0002u) /* ADC12 Conversion Sequence Select: 0 */ +#define ADC12CONSEQ_1 (1*0x0002u) /* ADC12 Conversion Sequence Select: 1 */ +#define ADC12CONSEQ_2 (2*0x0002u) /* ADC12 Conversion Sequence Select: 2 */ +#define ADC12CONSEQ_3 (3*0x0002u) /* ADC12 Conversion Sequence Select: 3 */ + +#define ADC12SSEL_0 (0*0x0008u) /* ADC12 Clock Source Select: 0 */ +#define ADC12SSEL_1 (1*0x0008u) /* ADC12 Clock Source Select: 1 */ +#define ADC12SSEL_2 (2*0x0008u) /* ADC12 Clock Source Select: 2 */ +#define ADC12SSEL_3 (3*0x0008u) /* ADC12 Clock Source Select: 3 */ + +#define ADC12DIV_0 (0*0x0020u) /* ADC12 Clock Divider Select: 0 */ +#define ADC12DIV_1 (1*0x0020u) /* ADC12 Clock Divider Select: 1 */ +#define ADC12DIV_2 (2*0x0020u) /* ADC12 Clock Divider Select: 2 */ +#define ADC12DIV_3 (3*0x0020u) /* ADC12 Clock Divider Select: 3 */ +#define ADC12DIV_4 (4*0x0020u) /* ADC12 Clock Divider Select: 4 */ +#define ADC12DIV_5 (5*0x0020u) /* ADC12 Clock Divider Select: 5 */ +#define ADC12DIV_6 (6*0x0020u) /* ADC12 Clock Divider Select: 6 */ +#define ADC12DIV_7 (7*0x0020u) /* ADC12 Clock Divider Select: 7 */ + +#define ADC12SHS_0 (0*0x0400u) /* ADC12 Sample/Hold Source: 0 */ +#define ADC12SHS_1 (1*0x0400u) /* ADC12 Sample/Hold Source: 1 */ +#define ADC12SHS_2 (2*0x0400u) /* ADC12 Sample/Hold Source: 2 */ +#define ADC12SHS_3 (3*0x0400u) /* ADC12 Sample/Hold Source: 3 */ +#define ADC12SHS_4 (4*0x0400u) /* ADC12 Sample/Hold Source: 4 */ +#define ADC12SHS_5 (5*0x0400u) /* ADC12 Sample/Hold Source: 5 */ +#define ADC12SHS_6 (6*0x0400u) /* ADC12 Sample/Hold Source: 6 */ +#define ADC12SHS_7 (7*0x0400u) /* ADC12 Sample/Hold Source: 7 */ + +#define ADC12PDIV_0 (0*0x2000u) /* ADC12 Clock predivider Select 0 */ +#define ADC12PDIV_1 (1*0x2000u) /* ADC12 Clock predivider Select 1 */ +#define ADC12PDIV_2 (2*0x2000u) /* ADC12 Clock predivider Select 2 */ +#define ADC12PDIV_3 (3*0x2000u) /* ADC12 Clock predivider Select 3 */ +#define ADC12PDIV__1 (0*0x2000u) /* ADC12 Clock predivider Select: /1 */ +#define ADC12PDIV__4 (1*0x2000u) /* ADC12 Clock predivider Select: /4 */ +#define ADC12PDIV__32 (2*0x2000u) /* ADC12 Clock predivider Select: /32 */ +#define ADC12PDIV__64 (3*0x2000u) /* ADC12 Clock predivider Select: /64 */ + +/* ADC12CTL2 Control Bits */ +#define ADC12PWRMD (0x0001u) /* ADC12 Power Mode */ +#define ADC12DF (0x0008u) /* ADC12 Data Format */ +#define ADC12RES0 (0x0010u) /* ADC12 Resolution Bit: 0 */ +#define ADC12RES1 (0x0020u) /* ADC12 Resolution Bit: 1 */ + +/* ADC12CTL2 Control Bits */ +#define ADC12PWRMD_L (0x0001u) /* ADC12 Power Mode */ +#define ADC12DF_L (0x0008u) /* ADC12 Data Format */ +#define ADC12RES0_L (0x0010u) /* ADC12 Resolution Bit: 0 */ +#define ADC12RES1_L (0x0020u) /* ADC12 Resolution Bit: 1 */ + +#define ADC12RES_0 (0x0000u) /* ADC12+ Resolution : 8 Bit */ +#define ADC12RES_1 (0x0010u) /* ADC12+ Resolution : 10 Bit */ +#define ADC12RES_2 (0x0020u) /* ADC12+ Resolution : 12 Bit */ +#define ADC12RES_3 (0x0030u) /* ADC12+ Resolution : reserved */ + +#define ADC12RES__8BIT (0x0000u) /* ADC12+ Resolution : 8 Bit */ +#define ADC12RES__10BIT (0x0010u) /* ADC12+ Resolution : 10 Bit */ +#define ADC12RES__12BIT (0x0020u) /* ADC12+ Resolution : 12 Bit */ + +/* ADC12CTL3 Control Bits */ +#define ADC12CSTARTADD0 (0x0001u) /* ADC12 Conversion Start Address Bit: 0 */ +#define ADC12CSTARTADD1 (0x0002u) /* ADC12 Conversion Start Address Bit: 1 */ +#define ADC12CSTARTADD2 (0x0004u) /* ADC12 Conversion Start Address Bit: 2 */ +#define ADC12CSTARTADD3 (0x0008u) /* ADC12 Conversion Start Address Bit: 3 */ +#define ADC12CSTARTADD4 (0x0010u) /* ADC12 Conversion Start Address Bit: 4 */ +#define ADC12BATMAP (0x0040u) /* ADC12 Internal AVCC/2 select */ +#define ADC12TCMAP (0x0080u) /* ADC12 Internal TempSensor select */ +#define ADC12ICH0MAP (0x0100u) /* ADC12 Internal Channel 0 select */ +#define ADC12ICH1MAP (0x0200u) /* ADC12 Internal Channel 1 select */ +#define ADC12ICH2MAP (0x0400u) /* ADC12 Internal Channel 2 select */ +#define ADC12ICH3MAP (0x0800u) /* ADC12 Internal Channel 3 select */ + +/* ADC12CTL3 Control Bits */ +#define ADC12CSTARTADD0_L (0x0001u) /* ADC12 Conversion Start Address Bit: 0 */ +#define ADC12CSTARTADD1_L (0x0002u) /* ADC12 Conversion Start Address Bit: 1 */ +#define ADC12CSTARTADD2_L (0x0004u) /* ADC12 Conversion Start Address Bit: 2 */ +#define ADC12CSTARTADD3_L (0x0008u) /* ADC12 Conversion Start Address Bit: 3 */ +#define ADC12CSTARTADD4_L (0x0010u) /* ADC12 Conversion Start Address Bit: 4 */ +#define ADC12BATMAP_L (0x0040u) /* ADC12 Internal AVCC/2 select */ +#define ADC12TCMAP_L (0x0080u) /* ADC12 Internal TempSensor select */ + +/* ADC12CTL3 Control Bits */ +#define ADC12ICH0MAP_H (0x0001u) /* ADC12 Internal Channel 0 select */ +#define ADC12ICH1MAP_H (0x0002u) /* ADC12 Internal Channel 1 select */ +#define ADC12ICH2MAP_H (0x0004u) /* ADC12 Internal Channel 2 select */ +#define ADC12ICH3MAP_H (0x0008u) /* ADC12 Internal Channel 3 select */ + +#define ADC12CSTARTADD_0 ( 0*0x0001u) /* ADC12 Conversion Start Address: 0 */ +#define ADC12CSTARTADD_1 ( 1*0x0001u) /* ADC12 Conversion Start Address: 1 */ +#define ADC12CSTARTADD_2 ( 2*0x0001u) /* ADC12 Conversion Start Address: 2 */ +#define ADC12CSTARTADD_3 ( 3*0x0001u) /* ADC12 Conversion Start Address: 3 */ +#define ADC12CSTARTADD_4 ( 4*0x0001u) /* ADC12 Conversion Start Address: 4 */ +#define ADC12CSTARTADD_5 ( 5*0x0001u) /* ADC12 Conversion Start Address: 5 */ +#define ADC12CSTARTADD_6 ( 6*0x0001u) /* ADC12 Conversion Start Address: 6 */ +#define ADC12CSTARTADD_7 ( 7*0x0001u) /* ADC12 Conversion Start Address: 7 */ +#define ADC12CSTARTADD_8 ( 8*0x0001u) /* ADC12 Conversion Start Address: 8 */ +#define ADC12CSTARTADD_9 ( 9*0x0001u) /* ADC12 Conversion Start Address: 9 */ +#define ADC12CSTARTADD_10 (10*0x0001u) /* ADC12 Conversion Start Address: 10 */ +#define ADC12CSTARTADD_11 (11*0x0001u) /* ADC12 Conversion Start Address: 11 */ +#define ADC12CSTARTADD_12 (12*0x0001u) /* ADC12 Conversion Start Address: 12 */ +#define ADC12CSTARTADD_13 (13*0x0001u) /* ADC12 Conversion Start Address: 13 */ +#define ADC12CSTARTADD_14 (14*0x0001u) /* ADC12 Conversion Start Address: 14 */ +#define ADC12CSTARTADD_15 (15*0x0001u) /* ADC12 Conversion Start Address: 15 */ +#define ADC12CSTARTADD_16 (16*0x0001u) /* ADC12 Conversion Start Address: 16 */ +#define ADC12CSTARTADD_17 (17*0x0001u) /* ADC12 Conversion Start Address: 17 */ +#define ADC12CSTARTADD_18 (18*0x0001u) /* ADC12 Conversion Start Address: 18 */ +#define ADC12CSTARTADD_19 (19*0x0001u) /* ADC12 Conversion Start Address: 19 */ +#define ADC12CSTARTADD_20 (20*0x0001u) /* ADC12 Conversion Start Address: 20 */ +#define ADC12CSTARTADD_21 (21*0x0001u) /* ADC12 Conversion Start Address: 21 */ +#define ADC12CSTARTADD_22 (22*0x0001u) /* ADC12 Conversion Start Address: 22 */ +#define ADC12CSTARTADD_23 (23*0x0001u) /* ADC12 Conversion Start Address: 23 */ +#define ADC12CSTARTADD_24 (24*0x0001u) /* ADC12 Conversion Start Address: 24 */ +#define ADC12CSTARTADD_25 (25*0x0001u) /* ADC12 Conversion Start Address: 25 */ +#define ADC12CSTARTADD_26 (26*0x0001u) /* ADC12 Conversion Start Address: 26 */ +#define ADC12CSTARTADD_27 (27*0x0001u) /* ADC12 Conversion Start Address: 27 */ +#define ADC12CSTARTADD_28 (28*0x0001u) /* ADC12 Conversion Start Address: 28 */ +#define ADC12CSTARTADD_29 (29*0x0001u) /* ADC12 Conversion Start Address: 29 */ +#define ADC12CSTARTADD_30 (30*0x0001u) /* ADC12 Conversion Start Address: 30 */ +#define ADC12CSTARTADD_31 (31*0x0001u) /* ADC12 Conversion Start Address: 31 */ + +/* ADC12MCTLx Control Bits */ +#define ADC12INCH0 (0x0001u) /* ADC12 Input Channel Select Bit 0 */ +#define ADC12INCH1 (0x0002u) /* ADC12 Input Channel Select Bit 1 */ +#define ADC12INCH2 (0x0004u) /* ADC12 Input Channel Select Bit 2 */ +#define ADC12INCH3 (0x0008u) /* ADC12 Input Channel Select Bit 3 */ +#define ADC12INCH4 (0x0010u) /* ADC12 Input Channel Select Bit 4 */ +#define ADC12EOS (0x0080u) /* ADC12 End of Sequence */ +#define ADC12VRSEL0 (0x0100u) /* ADC12 VR Select Bit 0 */ +#define ADC12VRSEL1 (0x0200u) /* ADC12 VR Select Bit 1 */ +#define ADC12VRSEL2 (0x0400u) /* ADC12 VR Select Bit 2 */ +#define ADC12VRSEL3 (0x0800u) /* ADC12 VR Select Bit 3 */ +#define ADC12DIF (0x2000u) /* ADC12 Differential mode (only for even Registers) */ +#define ADC12WINC (0x4000u) /* ADC12 Comparator window enable */ + +/* ADC12MCTLx Control Bits */ +#define ADC12INCH0_L (0x0001u) /* ADC12 Input Channel Select Bit 0 */ +#define ADC12INCH1_L (0x0002u) /* ADC12 Input Channel Select Bit 1 */ +#define ADC12INCH2_L (0x0004u) /* ADC12 Input Channel Select Bit 2 */ +#define ADC12INCH3_L (0x0008u) /* ADC12 Input Channel Select Bit 3 */ +#define ADC12INCH4_L (0x0010u) /* ADC12 Input Channel Select Bit 4 */ +#define ADC12EOS_L (0x0080u) /* ADC12 End of Sequence */ + +/* ADC12MCTLx Control Bits */ +#define ADC12VRSEL0_H (0x0001u) /* ADC12 VR Select Bit 0 */ +#define ADC12VRSEL1_H (0x0002u) /* ADC12 VR Select Bit 1 */ +#define ADC12VRSEL2_H (0x0004u) /* ADC12 VR Select Bit 2 */ +#define ADC12VRSEL3_H (0x0008u) /* ADC12 VR Select Bit 3 */ +#define ADC12DIF_H (0x0020u) /* ADC12 Differential mode (only for even Registers) */ +#define ADC12WINC_H (0x0040u) /* ADC12 Comparator window enable */ + +#define ADC12INCH_0 (0x0000u) /* ADC12 Input Channel 0 */ +#define ADC12INCH_1 (0x0001u) /* ADC12 Input Channel 1 */ +#define ADC12INCH_2 (0x0002u) /* ADC12 Input Channel 2 */ +#define ADC12INCH_3 (0x0003u) /* ADC12 Input Channel 3 */ +#define ADC12INCH_4 (0x0004u) /* ADC12 Input Channel 4 */ +#define ADC12INCH_5 (0x0005u) /* ADC12 Input Channel 5 */ +#define ADC12INCH_6 (0x0006u) /* ADC12 Input Channel 6 */ +#define ADC12INCH_7 (0x0007u) /* ADC12 Input Channel 7 */ +#define ADC12INCH_8 (0x0008u) /* ADC12 Input Channel 8 */ +#define ADC12INCH_9 (0x0009u) /* ADC12 Input Channel 9 */ +#define ADC12INCH_10 (0x000Au) /* ADC12 Input Channel 10 */ +#define ADC12INCH_11 (0x000Bu) /* ADC12 Input Channel 11 */ +#define ADC12INCH_12 (0x000Cu) /* ADC12 Input Channel 12 */ +#define ADC12INCH_13 (0x000Du) /* ADC12 Input Channel 13 */ +#define ADC12INCH_14 (0x000Eu) /* ADC12 Input Channel 14 */ +#define ADC12INCH_15 (0x000Fu) /* ADC12 Input Channel 15 */ +#define ADC12INCH_16 (0x0010u) /* ADC12 Input Channel 16 */ +#define ADC12INCH_17 (0x0011u) /* ADC12 Input Channel 17 */ +#define ADC12INCH_18 (0x0012u) /* ADC12 Input Channel 18 */ +#define ADC12INCH_19 (0x0013u) /* ADC12 Input Channel 19 */ +#define ADC12INCH_20 (0x0014u) /* ADC12 Input Channel 20 */ +#define ADC12INCH_21 (0x0015u) /* ADC12 Input Channel 21 */ +#define ADC12INCH_22 (0x0016u) /* ADC12 Input Channel 22 */ +#define ADC12INCH_23 (0x0017u) /* ADC12 Input Channel 23 */ +#define ADC12INCH_24 (0x0018u) /* ADC12 Input Channel 24 */ +#define ADC12INCH_25 (0x0019u) /* ADC12 Input Channel 25 */ +#define ADC12INCH_26 (0x001Au) /* ADC12 Input Channel 26 */ +#define ADC12INCH_27 (0x001Bu) /* ADC12 Input Channel 27 */ +#define ADC12INCH_28 (0x001Cu) /* ADC12 Input Channel 28 */ +#define ADC12INCH_29 (0x001Du) /* ADC12 Input Channel 29 */ +#define ADC12INCH_30 (0x001Eu) /* ADC12 Input Channel 30 */ +#define ADC12INCH_31 (0x001Fu) /* ADC12 Input Channel 31 */ + +#define ADC12VRSEL_0 (0*0x100u) /* ADC12 Select Reference 0 */ +#define ADC12VRSEL_1 (1*0x100u) /* ADC12 Select Reference 1 */ +#define ADC12VRSEL_2 (2*0x100u) /* ADC12 Select Reference 2 */ +#define ADC12VRSEL_3 (3*0x100u) /* ADC12 Select Reference 3 */ +#define ADC12VRSEL_4 (4*0x100u) /* ADC12 Select Reference 4 */ +#define ADC12VRSEL_5 (5*0x100u) /* ADC12 Select Reference 5 */ +#define ADC12VRSEL_6 (6*0x100u) /* ADC12 Select Reference 6 */ +#define ADC12VRSEL_7 (7*0x100u) /* ADC12 Select Reference 7 */ +#define ADC12VRSEL_8 (8*0x100u) /* ADC12 Select Reference 8 */ +#define ADC12VRSEL_9 (9*0x100u) /* ADC12 Select Reference 9 */ +#define ADC12VRSEL_10 (10*0x100u) /* ADC12 Select Reference 10 */ +#define ADC12VRSEL_11 (11*0x100u) /* ADC12 Select Reference 11 */ +#define ADC12VRSEL_12 (12*0x100u) /* ADC12 Select Reference 12 */ +#define ADC12VRSEL_13 (13*0x100u) /* ADC12 Select Reference 13 */ +#define ADC12VRSEL_14 (14*0x100u) /* ADC12 Select Reference 14 */ +#define ADC12VRSEL_15 (15*0x100u) /* ADC12 Select Reference 15 */ + +/* ADC12HI Control Bits */ + +/* ADC12LO Control Bits */ + +/* ADC12IER0 Control Bits */ +#define ADC12IE0 (0x0001u) /* ADC12 Memory 0 Interrupt Enable */ +#define ADC12IE1 (0x0002u) /* ADC12 Memory 1 Interrupt Enable */ +#define ADC12IE2 (0x0004u) /* ADC12 Memory 2 Interrupt Enable */ +#define ADC12IE3 (0x0008u) /* ADC12 Memory 3 Interrupt Enable */ +#define ADC12IE4 (0x0010u) /* ADC12 Memory 4 Interrupt Enable */ +#define ADC12IE5 (0x0020u) /* ADC12 Memory 5 Interrupt Enable */ +#define ADC12IE6 (0x0040u) /* ADC12 Memory 6 Interrupt Enable */ +#define ADC12IE7 (0x0080u) /* ADC12 Memory 7 Interrupt Enable */ +#define ADC12IE8 (0x0100u) /* ADC12 Memory 8 Interrupt Enable */ +#define ADC12IE9 (0x0200u) /* ADC12 Memory 9 Interrupt Enable */ +#define ADC12IE10 (0x0400u) /* ADC12 Memory 10 Interrupt Enable */ +#define ADC12IE11 (0x0800u) /* ADC12 Memory 11 Interrupt Enable */ +#define ADC12IE12 (0x1000u) /* ADC12 Memory 12 Interrupt Enable */ +#define ADC12IE13 (0x2000u) /* ADC12 Memory 13 Interrupt Enable */ +#define ADC12IE14 (0x4000u) /* ADC12 Memory 14 Interrupt Enable */ +#define ADC12IE15 (0x8000u) /* ADC12 Memory 15 Interrupt Enable */ + +/* ADC12IER0 Control Bits */ +#define ADC12IE0_L (0x0001u) /* ADC12 Memory 0 Interrupt Enable */ +#define ADC12IE1_L (0x0002u) /* ADC12 Memory 1 Interrupt Enable */ +#define ADC12IE2_L (0x0004u) /* ADC12 Memory 2 Interrupt Enable */ +#define ADC12IE3_L (0x0008u) /* ADC12 Memory 3 Interrupt Enable */ +#define ADC12IE4_L (0x0010u) /* ADC12 Memory 4 Interrupt Enable */ +#define ADC12IE5_L (0x0020u) /* ADC12 Memory 5 Interrupt Enable */ +#define ADC12IE6_L (0x0040u) /* ADC12 Memory 6 Interrupt Enable */ +#define ADC12IE7_L (0x0080u) /* ADC12 Memory 7 Interrupt Enable */ + +/* ADC12IER0 Control Bits */ +#define ADC12IE8_H (0x0001u) /* ADC12 Memory 8 Interrupt Enable */ +#define ADC12IE9_H (0x0002u) /* ADC12 Memory 9 Interrupt Enable */ +#define ADC12IE10_H (0x0004u) /* ADC12 Memory 10 Interrupt Enable */ +#define ADC12IE11_H (0x0008u) /* ADC12 Memory 11 Interrupt Enable */ +#define ADC12IE12_H (0x0010u) /* ADC12 Memory 12 Interrupt Enable */ +#define ADC12IE13_H (0x0020u) /* ADC12 Memory 13 Interrupt Enable */ +#define ADC12IE14_H (0x0040u) /* ADC12 Memory 14 Interrupt Enable */ +#define ADC12IE15_H (0x0080u) /* ADC12 Memory 15 Interrupt Enable */ + +/* ADC12IER1 Control Bits */ +#define ADC12IE16 (0x0001u) /* ADC12 Memory 16 Interrupt Enable */ +#define ADC12IE17 (0x0002u) /* ADC12 Memory 17 Interrupt Enable */ +#define ADC12IE18 (0x0004u) /* ADC12 Memory 18 Interrupt Enable */ +#define ADC12IE19 (0x0008u) /* ADC12 Memory 19 Interrupt Enable */ +#define ADC12IE20 (0x0010u) /* ADC12 Memory 20 Interrupt Enable */ +#define ADC12IE21 (0x0020u) /* ADC12 Memory 21 Interrupt Enable */ +#define ADC12IE22 (0x0040u) /* ADC12 Memory 22 Interrupt Enable */ +#define ADC12IE23 (0x0080u) /* ADC12 Memory 23 Interrupt Enable */ +#define ADC12IE24 (0x0100u) /* ADC12 Memory 24 Interrupt Enable */ +#define ADC12IE25 (0x0200u) /* ADC12 Memory 25 Interrupt Enable */ +#define ADC12IE26 (0x0400u) /* ADC12 Memory 26 Interrupt Enable */ +#define ADC12IE27 (0x0800u) /* ADC12 Memory 27 Interrupt Enable */ +#define ADC12IE28 (0x1000u) /* ADC12 Memory 28 Interrupt Enable */ +#define ADC12IE29 (0x2000u) /* ADC12 Memory 29 Interrupt Enable */ +#define ADC12IE30 (0x4000u) /* ADC12 Memory 30 Interrupt Enable */ +#define ADC12IE31 (0x8000u) /* ADC12 Memory 31 Interrupt Enable */ + +/* ADC12IER1 Control Bits */ +#define ADC12IE16_L (0x0001u) /* ADC12 Memory 16 Interrupt Enable */ +#define ADC12IE17_L (0x0002u) /* ADC12 Memory 17 Interrupt Enable */ +#define ADC12IE18_L (0x0004u) /* ADC12 Memory 18 Interrupt Enable */ +#define ADC12IE19_L (0x0008u) /* ADC12 Memory 19 Interrupt Enable */ +#define ADC12IE20_L (0x0010u) /* ADC12 Memory 20 Interrupt Enable */ +#define ADC12IE21_L (0x0020u) /* ADC12 Memory 21 Interrupt Enable */ +#define ADC12IE22_L (0x0040u) /* ADC12 Memory 22 Interrupt Enable */ +#define ADC12IE23_L (0x0080u) /* ADC12 Memory 23 Interrupt Enable */ + +/* ADC12IER1 Control Bits */ +#define ADC12IE24_H (0x0001u) /* ADC12 Memory 24 Interrupt Enable */ +#define ADC12IE25_H (0x0002u) /* ADC12 Memory 25 Interrupt Enable */ +#define ADC12IE26_H (0x0004u) /* ADC12 Memory 26 Interrupt Enable */ +#define ADC12IE27_H (0x0008u) /* ADC12 Memory 27 Interrupt Enable */ +#define ADC12IE28_H (0x0010u) /* ADC12 Memory 28 Interrupt Enable */ +#define ADC12IE29_H (0x0020u) /* ADC12 Memory 29 Interrupt Enable */ +#define ADC12IE30_H (0x0040u) /* ADC12 Memory 30 Interrupt Enable */ +#define ADC12IE31_H (0x0080u) /* ADC12 Memory 31 Interrupt Enable */ + +/* ADC12IER2 Control Bits */ +#define ADC12INIE (0x0002u) /* ADC12 Interrupt enable for the inside of window of the Window comparator */ +#define ADC12LOIE (0x0004u) /* ADC12 Interrupt enable for lower threshold of the Window comparator */ +#define ADC12HIIE (0x0008u) /* ADC12 Interrupt enable for upper threshold of the Window comparator */ +#define ADC12OVIE (0x0010u) /* ADC12 ADC12MEMx Overflow interrupt enable */ +#define ADC12TOVIE (0x0020u) /* ADC12 Timer Overflow interrupt enable */ +#define ADC12RDYIE (0x0040u) /* ADC12 local buffered reference ready interrupt enable */ + +/* ADC12IER2 Control Bits */ +#define ADC12INIE_L (0x0002u) /* ADC12 Interrupt enable for the inside of window of the Window comparator */ +#define ADC12LOIE_L (0x0004u) /* ADC12 Interrupt enable for lower threshold of the Window comparator */ +#define ADC12HIIE_L (0x0008u) /* ADC12 Interrupt enable for upper threshold of the Window comparator */ +#define ADC12OVIE_L (0x0010u) /* ADC12 ADC12MEMx Overflow interrupt enable */ +#define ADC12TOVIE_L (0x0020u) /* ADC12 Timer Overflow interrupt enable */ +#define ADC12RDYIE_L (0x0040u) /* ADC12 local buffered reference ready interrupt enable */ + +/* ADC12IFGR0 Control Bits */ +#define ADC12IFG0 (0x0001u) /* ADC12 Memory 0 Interrupt Flag */ +#define ADC12IFG1 (0x0002u) /* ADC12 Memory 1 Interrupt Flag */ +#define ADC12IFG2 (0x0004u) /* ADC12 Memory 2 Interrupt Flag */ +#define ADC12IFG3 (0x0008u) /* ADC12 Memory 3 Interrupt Flag */ +#define ADC12IFG4 (0x0010u) /* ADC12 Memory 4 Interrupt Flag */ +#define ADC12IFG5 (0x0020u) /* ADC12 Memory 5 Interrupt Flag */ +#define ADC12IFG6 (0x0040u) /* ADC12 Memory 6 Interrupt Flag */ +#define ADC12IFG7 (0x0080u) /* ADC12 Memory 7 Interrupt Flag */ +#define ADC12IFG8 (0x0100u) /* ADC12 Memory 8 Interrupt Flag */ +#define ADC12IFG9 (0x0200u) /* ADC12 Memory 9 Interrupt Flag */ +#define ADC12IFG10 (0x0400u) /* ADC12 Memory 10 Interrupt Flag */ +#define ADC12IFG11 (0x0800u) /* ADC12 Memory 11 Interrupt Flag */ +#define ADC12IFG12 (0x1000u) /* ADC12 Memory 12 Interrupt Flag */ +#define ADC12IFG13 (0x2000u) /* ADC12 Memory 13 Interrupt Flag */ +#define ADC12IFG14 (0x4000u) /* ADC12 Memory 14 Interrupt Flag */ +#define ADC12IFG15 (0x8000u) /* ADC12 Memory 15 Interrupt Flag */ + +/* ADC12IFGR0 Control Bits */ +#define ADC12IFG0_L (0x0001u) /* ADC12 Memory 0 Interrupt Flag */ +#define ADC12IFG1_L (0x0002u) /* ADC12 Memory 1 Interrupt Flag */ +#define ADC12IFG2_L (0x0004u) /* ADC12 Memory 2 Interrupt Flag */ +#define ADC12IFG3_L (0x0008u) /* ADC12 Memory 3 Interrupt Flag */ +#define ADC12IFG4_L (0x0010u) /* ADC12 Memory 4 Interrupt Flag */ +#define ADC12IFG5_L (0x0020u) /* ADC12 Memory 5 Interrupt Flag */ +#define ADC12IFG6_L (0x0040u) /* ADC12 Memory 6 Interrupt Flag */ +#define ADC12IFG7_L (0x0080u) /* ADC12 Memory 7 Interrupt Flag */ + +/* ADC12IFGR0 Control Bits */ +#define ADC12IFG8_H (0x0001u) /* ADC12 Memory 8 Interrupt Flag */ +#define ADC12IFG9_H (0x0002u) /* ADC12 Memory 9 Interrupt Flag */ +#define ADC12IFG10_H (0x0004u) /* ADC12 Memory 10 Interrupt Flag */ +#define ADC12IFG11_H (0x0008u) /* ADC12 Memory 11 Interrupt Flag */ +#define ADC12IFG12_H (0x0010u) /* ADC12 Memory 12 Interrupt Flag */ +#define ADC12IFG13_H (0x0020u) /* ADC12 Memory 13 Interrupt Flag */ +#define ADC12IFG14_H (0x0040u) /* ADC12 Memory 14 Interrupt Flag */ +#define ADC12IFG15_H (0x0080u) /* ADC12 Memory 15 Interrupt Flag */ + +/* ADC12IFGR1 Control Bits */ +#define ADC12IFG16 (0x0001u) /* ADC12 Memory 16 Interrupt Flag */ +#define ADC12IFG17 (0x0002u) /* ADC12 Memory 17 Interrupt Flag */ +#define ADC12IFG18 (0x0004u) /* ADC12 Memory 18 Interrupt Flag */ +#define ADC12IFG19 (0x0008u) /* ADC12 Memory 19 Interrupt Flag */ +#define ADC12IFG20 (0x0010u) /* ADC12 Memory 20 Interrupt Flag */ +#define ADC12IFG21 (0x0020u) /* ADC12 Memory 21 Interrupt Flag */ +#define ADC12IFG22 (0x0040u) /* ADC12 Memory 22 Interrupt Flag */ +#define ADC12IFG23 (0x0080u) /* ADC12 Memory 23 Interrupt Flag */ +#define ADC12IFG24 (0x0100u) /* ADC12 Memory 24 Interrupt Flag */ +#define ADC12IFG25 (0x0200u) /* ADC12 Memory 25 Interrupt Flag */ +#define ADC12IFG26 (0x0400u) /* ADC12 Memory 26 Interrupt Flag */ +#define ADC12IFG27 (0x0800u) /* ADC12 Memory 27 Interrupt Flag */ +#define ADC12IFG28 (0x1000u) /* ADC12 Memory 28 Interrupt Flag */ +#define ADC12IFG29 (0x2000u) /* ADC12 Memory 29 Interrupt Flag */ +#define ADC12IFG30 (0x4000u) /* ADC12 Memory 30 Interrupt Flag */ +#define ADC12IFG31 (0x8000u) /* ADC12 Memory 31 Interrupt Flag */ + +/* ADC12IFGR1 Control Bits */ +#define ADC12IFG16_L (0x0001u) /* ADC12 Memory 16 Interrupt Flag */ +#define ADC12IFG17_L (0x0002u) /* ADC12 Memory 17 Interrupt Flag */ +#define ADC12IFG18_L (0x0004u) /* ADC12 Memory 18 Interrupt Flag */ +#define ADC12IFG19_L (0x0008u) /* ADC12 Memory 19 Interrupt Flag */ +#define ADC12IFG20_L (0x0010u) /* ADC12 Memory 20 Interrupt Flag */ +#define ADC12IFG21_L (0x0020u) /* ADC12 Memory 21 Interrupt Flag */ +#define ADC12IFG22_L (0x0040u) /* ADC12 Memory 22 Interrupt Flag */ +#define ADC12IFG23_L (0x0080u) /* ADC12 Memory 23 Interrupt Flag */ + +/* ADC12IFGR1 Control Bits */ +#define ADC12IFG24_H (0x0001u) /* ADC12 Memory 24 Interrupt Flag */ +#define ADC12IFG25_H (0x0002u) /* ADC12 Memory 25 Interrupt Flag */ +#define ADC12IFG26_H (0x0004u) /* ADC12 Memory 26 Interrupt Flag */ +#define ADC12IFG27_H (0x0008u) /* ADC12 Memory 27 Interrupt Flag */ +#define ADC12IFG28_H (0x0010u) /* ADC12 Memory 28 Interrupt Flag */ +#define ADC12IFG29_H (0x0020u) /* ADC12 Memory 29 Interrupt Flag */ +#define ADC12IFG30_H (0x0040u) /* ADC12 Memory 30 Interrupt Flag */ +#define ADC12IFG31_H (0x0080u) /* ADC12 Memory 31 Interrupt Flag */ + +/* ADC12IFGR2 Control Bits */ +#define ADC12INIFG (0x0002u) /* ADC12 Interrupt Flag for the inside of window of the Window comparator */ +#define ADC12LOIFG (0x0004u) /* ADC12 Interrupt Flag for lower threshold of the Window comparator */ +#define ADC12HIIFG (0x0008u) /* ADC12 Interrupt Flag for upper threshold of the Window comparator */ +#define ADC12OVIFG (0x0010u) /* ADC12 ADC12MEMx Overflow interrupt Flag */ +#define ADC12TOVIFG (0x0020u) /* ADC12 Timer Overflow interrupt Flag */ +#define ADC12RDYIFG (0x0040u) /* ADC12 local buffered reference ready interrupt Flag */ + +/* ADC12IFGR2 Control Bits */ +#define ADC12INIFG_L (0x0002u) /* ADC12 Interrupt Flag for the inside of window of the Window comparator */ +#define ADC12LOIFG_L (0x0004u) /* ADC12 Interrupt Flag for lower threshold of the Window comparator */ +#define ADC12HIIFG_L (0x0008u) /* ADC12 Interrupt Flag for upper threshold of the Window comparator */ +#define ADC12OVIFG_L (0x0010u) /* ADC12 ADC12MEMx Overflow interrupt Flag */ +#define ADC12TOVIFG_L (0x0020u) /* ADC12 Timer Overflow interrupt Flag */ +#define ADC12RDYIFG_L (0x0040u) /* ADC12 local buffered reference ready interrupt Flag */ + +/* ADC12IV Definitions */ +#define ADC12IV_NONE (0x0000u) /* No Interrupt pending */ +#define ADC12IV_ADC12OVIFG (0x0002u) /* ADC12OVIFG */ +#define ADC12IV_ADC12TOVIFG (0x0004u) /* ADC12TOVIFG */ +#define ADC12IV_ADC12HIIFG (0x0006u) /* ADC12HIIFG */ +#define ADC12IV_ADC12LOIFG (0x0008u) /* ADC12LOIFG */ +#define ADC12IV_ADC12INIFG (0x000Au) /* ADC12INIFG */ +#define ADC12IV_ADC12IFG0 (0x000Cu) /* ADC12IFG0 */ +#define ADC12IV_ADC12IFG1 (0x000Eu) /* ADC12IFG1 */ +#define ADC12IV_ADC12IFG2 (0x0010u) /* ADC12IFG2 */ +#define ADC12IV_ADC12IFG3 (0x0012u) /* ADC12IFG3 */ +#define ADC12IV_ADC12IFG4 (0x0014u) /* ADC12IFG4 */ +#define ADC12IV_ADC12IFG5 (0x0016u) /* ADC12IFG5 */ +#define ADC12IV_ADC12IFG6 (0x0018u) /* ADC12IFG6 */ +#define ADC12IV_ADC12IFG7 (0x001Au) /* ADC12IFG7 */ +#define ADC12IV_ADC12IFG8 (0x001Cu) /* ADC12IFG8 */ +#define ADC12IV_ADC12IFG9 (0x001Eu) /* ADC12IFG9 */ +#define ADC12IV_ADC12IFG10 (0x0020u) /* ADC12IFG10 */ +#define ADC12IV_ADC12IFG11 (0x0022u) /* ADC12IFG11 */ +#define ADC12IV_ADC12IFG12 (0x0024u) /* ADC12IFG12 */ +#define ADC12IV_ADC12IFG13 (0x0026u) /* ADC12IFG13 */ +#define ADC12IV_ADC12IFG14 (0x0028u) /* ADC12IFG14 */ +#define ADC12IV_ADC12IFG15 (0x002Au) /* ADC12IFG15 */ +#define ADC12IV_ADC12IFG16 (0x002Cu) /* ADC12IFG16 */ +#define ADC12IV_ADC12IFG17 (0x002Eu) /* ADC12IFG17 */ +#define ADC12IV_ADC12IFG18 (0x0030u) /* ADC12IFG18 */ +#define ADC12IV_ADC12IFG19 (0x0032u) /* ADC12IFG19 */ +#define ADC12IV_ADC12IFG20 (0x0034u) /* ADC12IFG20 */ +#define ADC12IV_ADC12IFG21 (0x0036u) /* ADC12IFG21 */ +#define ADC12IV_ADC12IFG22 (0x0038u) /* ADC12IFG22 */ +#define ADC12IV_ADC12IFG23 (0x003Au) /* ADC12IFG23 */ +#define ADC12IV_ADC12IFG24 (0x003Cu) /* ADC12IFG24 */ +#define ADC12IV_ADC12IFG25 (0x003Eu) /* ADC12IFG25 */ +#define ADC12IV_ADC12IFG26 (0x0040u) /* ADC12IFG26 */ +#define ADC12IV_ADC12IFG27 (0x0042u) /* ADC12IFG27 */ +#define ADC12IV_ADC12IFG28 (0x0044u) /* ADC12IFG28 */ +#define ADC12IV_ADC12IFG29 (0x0046u) /* ADC12IFG29 */ +#define ADC12IV_ADC12IFG30 (0x0048u) /* ADC12IFG30 */ +#define ADC12IV_ADC12IFG31 (0x004Au) /* ADC12IFG31 */ +#define ADC12IV_ADC12RDYIFG (0x004Cu) /* ADC12RDYIFG */ + + +#endif +/************************************************************ +* AES256 Accelerator +************************************************************/ +#ifdef __MSP430_HAS_AES256__ /* Definition to show that Module is available */ + +#define OFS_AESACTL0 (0x0000u) /* AES accelerator control register 0 */ +#define OFS_AESACTL0_L OFS_AESACTL0 +#define OFS_AESACTL0_H OFS_AESACTL0+1 +#define OFS_AESACTL1 (0x0002u) /* AES accelerator control register 1 */ +#define OFS_AESACTL1_L OFS_AESACTL1 +#define OFS_AESACTL1_H OFS_AESACTL1+1 +#define OFS_AESASTAT (0x0004u) /* AES accelerator status register */ +#define OFS_AESASTAT_L OFS_AESASTAT +#define OFS_AESASTAT_H OFS_AESASTAT+1 +#define OFS_AESAKEY (0x0006u) /* AES accelerator key register */ +#define OFS_AESAKEY_L OFS_AESAKEY +#define OFS_AESAKEY_H OFS_AESAKEY+1 +#define OFS_AESADIN (0x0008u) /* AES accelerator data in register */ +#define OFS_AESADIN_L OFS_AESADIN +#define OFS_AESADIN_H OFS_AESADIN+1 +#define OFS_AESADOUT (0x000Au) /* AES accelerator data out register */ +#define OFS_AESADOUT_L OFS_AESADOUT +#define OFS_AESADOUT_H OFS_AESADOUT+1 +#define OFS_AESAXDIN (0x000Cu) /* AES accelerator XORed data in register */ +#define OFS_AESAXDIN_L OFS_AESAXDIN +#define OFS_AESAXDIN_H OFS_AESAXDIN+1 +#define OFS_AESAXIN (0x000Eu) /* AES accelerator XORed data in register (no trigger) */ +#define OFS_AESAXIN_L OFS_AESAXIN +#define OFS_AESAXIN_H OFS_AESAXIN+1 + +/* AESACTL0 Control Bits */ +#define AESOP0 (0x0001u) /* AES Operation Bit: 0 */ +#define AESOP1 (0x0002u) /* AES Operation Bit: 1 */ +#define AESKL0 (0x0004u) /* AES Key length Bit: 0 */ +#define AESKL1 (0x0008u) /* AES Key length Bit: 1 */ +#define AESTRIG (0x0010u) /* AES Trigger Select */ +#define AESCM0 (0x0020u) /* AES Cipher mode select Bit: 0 */ +#define AESCM1 (0x0040u) /* AES Cipher mode select Bit: 1 */ +#define AESSWRST (0x0080u) /* AES Software Reset */ +#define AESRDYIFG (0x0100u) /* AES ready interrupt flag */ +#define AESERRFG (0x0800u) /* AES Error Flag */ +#define AESRDYIE (0x1000u) /* AES ready interrupt enable*/ +#define AESCMEN (0x8000u) /* AES DMA cipher mode enable*/ + +/* AESACTL0 Control Bits */ +#define AESOP0_L (0x0001u) /* AES Operation Bit: 0 */ +#define AESOP1_L (0x0002u) /* AES Operation Bit: 1 */ +#define AESKL0_L (0x0004u) /* AES Key length Bit: 0 */ +#define AESKL1_L (0x0008u) /* AES Key length Bit: 1 */ +#define AESTRIG_L (0x0010u) /* AES Trigger Select */ +#define AESCM0_L (0x0020u) /* AES Cipher mode select Bit: 0 */ +#define AESCM1_L (0x0040u) /* AES Cipher mode select Bit: 1 */ +#define AESSWRST_L (0x0080u) /* AES Software Reset */ + +/* AESACTL0 Control Bits */ +#define AESRDYIFG_H (0x0001u) /* AES ready interrupt flag */ +#define AESERRFG_H (0x0008u) /* AES Error Flag */ +#define AESRDYIE_H (0x0010u) /* AES ready interrupt enable*/ +#define AESCMEN_H (0x0080u) /* AES DMA cipher mode enable*/ + +#define AESOP_0 (0x0000u) /* AES Operation: Encrypt */ +#define AESOP_1 (0x0001u) /* AES Operation: Decrypt (same Key) */ +#define AESOP_2 (0x0002u) /* AES Operation: Decrypt (frist round Key) */ +#define AESOP_3 (0x0003u) /* AES Operation: Generate first round Key */ + +#define AESKL_0 (0x0000u) /* AES Key length: AES128 */ +#define AESKL_1 (0x0004u) /* AES Key length: AES192 */ +#define AESKL_2 (0x0008u) /* AES Key length: AES256 */ +#define AESKL__128 (0x0000u) /* AES Key length: AES128 */ +#define AESKL__192 (0x0004u) /* AES Key length: AES192 */ +#define AESKL__256 (0x0008u) /* AES Key length: AES256 */ + +#define AESCM_0 (0x0000u) /* AES Cipher mode select: ECB */ +#define AESCM_1 (0x0020u) /* AES Cipher mode select: CBC */ +#define AESCM_2 (0x0040u) /* AES Cipher mode select: OFB */ +#define AESCM_3 (0x0060u) /* AES Cipher mode select: CFB */ +#define AESCM__ECB (0x0000u) /* AES Cipher mode select: ECB */ +#define AESCM__CBC (0x0020u) /* AES Cipher mode select: CBC */ +#define AESCM__OFB (0x0040u) /* AES Cipher mode select: OFB */ +#define AESCM__CFB (0x0060u) /* AES Cipher mode select: CFB */ + +/* AESACTL1 Control Bits */ +#define AESBLKCNT0 (0x0001u) /* AES Cipher Block Counter Bit: 0 */ +#define AESBLKCNT1 (0x0002u) /* AES Cipher Block Counter Bit: 1 */ +#define AESBLKCNT2 (0x0004u) /* AES Cipher Block Counter Bit: 2 */ +#define AESBLKCNT3 (0x0008u) /* AES Cipher Block Counter Bit: 3 */ +#define AESBLKCNT4 (0x0010u) /* AES Cipher Block Counter Bit: 4 */ +#define AESBLKCNT5 (0x0020u) /* AES Cipher Block Counter Bit: 5 */ +#define AESBLKCNT6 (0x0040u) /* AES Cipher Block Counter Bit: 6 */ +#define AESBLKCNT7 (0x0080u) /* AES Cipher Block Counter Bit: 7 */ + +/* AESACTL1 Control Bits */ +#define AESBLKCNT0_L (0x0001u) /* AES Cipher Block Counter Bit: 0 */ +#define AESBLKCNT1_L (0x0002u) /* AES Cipher Block Counter Bit: 1 */ +#define AESBLKCNT2_L (0x0004u) /* AES Cipher Block Counter Bit: 2 */ +#define AESBLKCNT3_L (0x0008u) /* AES Cipher Block Counter Bit: 3 */ +#define AESBLKCNT4_L (0x0010u) /* AES Cipher Block Counter Bit: 4 */ +#define AESBLKCNT5_L (0x0020u) /* AES Cipher Block Counter Bit: 5 */ +#define AESBLKCNT6_L (0x0040u) /* AES Cipher Block Counter Bit: 6 */ +#define AESBLKCNT7_L (0x0080u) /* AES Cipher Block Counter Bit: 7 */ + +/* AESASTAT Control Bits */ +#define AESBUSY (0x0001u) /* AES Busy */ +#define AESKEYWR (0x0002u) /* AES All 16 bytes written to AESAKEY */ +#define AESDINWR (0x0004u) /* AES All 16 bytes written to AESADIN */ +#define AESDOUTRD (0x0008u) /* AES All 16 bytes read from AESADOUT */ +#define AESKEYCNT0 (0x0010u) /* AES Bytes written via AESAKEY Bit: 0 */ +#define AESKEYCNT1 (0x0020u) /* AES Bytes written via AESAKEY Bit: 1 */ +#define AESKEYCNT2 (0x0040u) /* AES Bytes written via AESAKEY Bit: 2 */ +#define AESKEYCNT3 (0x0080u) /* AES Bytes written via AESAKEY Bit: 3 */ +#define AESDINCNT0 (0x0100u) /* AES Bytes written via AESADIN Bit: 0 */ +#define AESDINCNT1 (0x0200u) /* AES Bytes written via AESADIN Bit: 1 */ +#define AESDINCNT2 (0x0400u) /* AES Bytes written via AESADIN Bit: 2 */ +#define AESDINCNT3 (0x0800u) /* AES Bytes written via AESADIN Bit: 3 */ +#define AESDOUTCNT0 (0x1000u) /* AES Bytes read via AESADOUT Bit: 0 */ +#define AESDOUTCNT1 (0x2000u) /* AES Bytes read via AESADOUT Bit: 1 */ +#define AESDOUTCNT2 (0x4000u) /* AES Bytes read via AESADOUT Bit: 2 */ +#define AESDOUTCNT3 (0x8000u) /* AES Bytes read via AESADOUT Bit: 3 */ + +/* AESASTAT Control Bits */ +#define AESBUSY_L (0x0001u) /* AES Busy */ +#define AESKEYWR_L (0x0002u) /* AES All 16 bytes written to AESAKEY */ +#define AESDINWR_L (0x0004u) /* AES All 16 bytes written to AESADIN */ +#define AESDOUTRD_L (0x0008u) /* AES All 16 bytes read from AESADOUT */ +#define AESKEYCNT0_L (0x0010u) /* AES Bytes written via AESAKEY Bit: 0 */ +#define AESKEYCNT1_L (0x0020u) /* AES Bytes written via AESAKEY Bit: 1 */ +#define AESKEYCNT2_L (0x0040u) /* AES Bytes written via AESAKEY Bit: 2 */ +#define AESKEYCNT3_L (0x0080u) /* AES Bytes written via AESAKEY Bit: 3 */ + +/* AESASTAT Control Bits */ +#define AESDINCNT0_H (0x0001u) /* AES Bytes written via AESADIN Bit: 0 */ +#define AESDINCNT1_H (0x0002u) /* AES Bytes written via AESADIN Bit: 1 */ +#define AESDINCNT2_H (0x0004u) /* AES Bytes written via AESADIN Bit: 2 */ +#define AESDINCNT3_H (0x0008u) /* AES Bytes written via AESADIN Bit: 3 */ +#define AESDOUTCNT0_H (0x0010u) /* AES Bytes read via AESADOUT Bit: 0 */ +#define AESDOUTCNT1_H (0x0020u) /* AES Bytes read via AESADOUT Bit: 1 */ +#define AESDOUTCNT2_H (0x0040u) /* AES Bytes read via AESADOUT Bit: 2 */ +#define AESDOUTCNT3_H (0x0080u) /* AES Bytes read via AESADOUT Bit: 3 */ + +#endif +/************************************************************ +* Capacitive_Touch_IO 0 +************************************************************/ +#ifdef __MSP430_HAS_CAP_TOUCH_IO_0__ /* Definition to show that Module is available */ + +#define OFS_CAPTIO0CTL (0x000Eu) /* Capacitive_Touch_IO 0 control register */ +#define OFS_CAPTIO0CTL_L OFS_CAPTIO0CTL +#define OFS_CAPTIO0CTL_H OFS_CAPTIO0CTL+1 + +#define CAPSIO0CTL CAPTIO0CTL /* legacy define */ + +/* CAPTIOxCTL Control Bits */ +#define CAPTIOPISEL0 (0x0002u) /* CapTouchIO Pin Select Bit: 0 */ +#define CAPTIOPISEL1 (0x0004u) /* CapTouchIO Pin Select Bit: 1 */ +#define CAPTIOPISEL2 (0x0008u) /* CapTouchIO Pin Select Bit: 2 */ +#define CAPTIOPOSEL0 (0x0010u) /* CapTouchIO Port Select Bit: 0 */ +#define CAPTIOPOSEL1 (0x0020u) /* CapTouchIO Port Select Bit: 1 */ +#define CAPTIOPOSEL2 (0x0040u) /* CapTouchIO Port Select Bit: 2 */ +#define CAPTIOPOSEL3 (0x0080u) /* CapTouchIO Port Select Bit: 3 */ +#define CAPTIOEN (0x0100u) /* CapTouchIO Enable */ +#define CAPTIO (0x0200u) /* CapTouchIO state */ + +/* CAPTIOxCTL Control Bits */ +#define CAPTIOPISEL0_L (0x0002u) /* CapTouchIO Pin Select Bit: 0 */ +#define CAPTIOPISEL1_L (0x0004u) /* CapTouchIO Pin Select Bit: 1 */ +#define CAPTIOPISEL2_L (0x0008u) /* CapTouchIO Pin Select Bit: 2 */ +#define CAPTIOPOSEL0_L (0x0010u) /* CapTouchIO Port Select Bit: 0 */ +#define CAPTIOPOSEL1_L (0x0020u) /* CapTouchIO Port Select Bit: 1 */ +#define CAPTIOPOSEL2_L (0x0040u) /* CapTouchIO Port Select Bit: 2 */ +#define CAPTIOPOSEL3_L (0x0080u) /* CapTouchIO Port Select Bit: 3 */ + +/* CAPTIOxCTL Control Bits */ +#define CAPTIOEN_H (0x0001u) /* CapTouchIO Enable */ +#define CAPTIO_H (0x0002u) /* CapTouchIO state */ + +/* Legacy defines */ +#define CAPSIOPISEL0 (0x0002u) /* CapTouchIO Pin Select Bit: 0 */ +#define CAPSIOPISEL1 (0x0004u) /* CapTouchIO Pin Select Bit: 1 */ +#define CAPSIOPISEL2 (0x0008u) /* CapTouchIO Pin Select Bit: 2 */ +#define CAPSIOPOSEL0 (0x0010u) /* CapTouchIO Port Select Bit: 0 */ +#define CAPSIOPOSEL1 (0x0020u) /* CapTouchIO Port Select Bit: 1 */ +#define CAPSIOPOSEL2 (0x0040u) /* CapTouchIO Port Select Bit: 2 */ +#define CAPSIOPOSEL3 (0x0080u) /* CapTouchIO Port Select Bit: 3 */ +#define CAPSIOEN (0x0100u) /* CapTouchIO Enable */ +#define CAPSIO (0x0200u) /* CapTouchIO state */ + +#endif +/************************************************************ +* Capacitive_Touch_IO 1 +************************************************************/ +#ifdef __MSP430_HAS_CAP_TOUCH_IO_1__ /* Definition to show that Module is available */ + +#define OFS_CAPTIO1CTL (0x000Eu) /* Capacitive_Touch_IO 1 control register */ +#define OFS_CAPTIO1CTL_L OFS_CAPTIO1CTL +#define OFS_CAPTIO1CTL_H OFS_CAPTIO1CTL+1 + +#define CAPSIO1CTL CAPTIO1CTL /* legacy define */ + +#endif +/************************************************************ +* Comparator E +************************************************************/ +#ifdef __MSP430_HAS_COMP_E__ /* Definition to show that Module is available */ + +#define OFS_CECTL0 (0x0000u) /* Comparator E Control Register 0 */ +#define OFS_CECTL0_L OFS_CECTL0 +#define OFS_CECTL0_H OFS_CECTL0+1 +#define OFS_CECTL1 (0x0002u) /* Comparator E Control Register 1 */ +#define OFS_CECTL1_L OFS_CECTL1 +#define OFS_CECTL1_H OFS_CECTL1+1 +#define OFS_CECTL2 (0x0004u) /* Comparator E Control Register 2 */ +#define OFS_CECTL2_L OFS_CECTL2 +#define OFS_CECTL2_H OFS_CECTL2+1 +#define OFS_CECTL3 (0x0006u) /* Comparator E Control Register 3 */ +#define OFS_CECTL3_L OFS_CECTL3 +#define OFS_CECTL3_H OFS_CECTL3+1 +#define OFS_CEINT (0x000Cu) /* Comparator E Interrupt Register */ +#define OFS_CEINT_L OFS_CEINT +#define OFS_CEINT_H OFS_CEINT+1 +#define OFS_CEIV (0x000Eu) /* Comparator E Interrupt Vector Word */ +#define OFS_CEIV_L OFS_CEIV +#define OFS_CEIV_H OFS_CEIV+1 + +/* CECTL0 Control Bits */ +#define CEIPSEL0 (0x0001u) /* Comp. E Pos. Channel Input Select 0 */ +#define CEIPSEL1 (0x0002u) /* Comp. E Pos. Channel Input Select 1 */ +#define CEIPSEL2 (0x0004u) /* Comp. E Pos. Channel Input Select 2 */ +#define CEIPSEL3 (0x0008u) /* Comp. E Pos. Channel Input Select 3 */ +//#define RESERVED (0x0010u) /* Comp. E */ +//#define RESERVED (0x0020u) /* Comp. E */ +//#define RESERVED (0x0040u) /* Comp. E */ +#define CEIPEN (0x0080u) /* Comp. E Pos. Channel Input Enable */ +#define CEIMSEL0 (0x0100u) /* Comp. E Neg. Channel Input Select 0 */ +#define CEIMSEL1 (0x0200u) /* Comp. E Neg. Channel Input Select 1 */ +#define CEIMSEL2 (0x0400u) /* Comp. E Neg. Channel Input Select 2 */ +#define CEIMSEL3 (0x0800u) /* Comp. E Neg. Channel Input Select 3 */ +//#define RESERVED (0x1000u) /* Comp. E */ +//#define RESERVED (0x2000u) /* Comp. E */ +//#define RESERVED (0x4000u) /* Comp. E */ +#define CEIMEN (0x8000u) /* Comp. E Neg. Channel Input Enable */ + +/* CECTL0 Control Bits */ +#define CEIPSEL0_L (0x0001u) /* Comp. E Pos. Channel Input Select 0 */ +#define CEIPSEL1_L (0x0002u) /* Comp. E Pos. Channel Input Select 1 */ +#define CEIPSEL2_L (0x0004u) /* Comp. E Pos. Channel Input Select 2 */ +#define CEIPSEL3_L (0x0008u) /* Comp. E Pos. Channel Input Select 3 */ +//#define RESERVED (0x0010u) /* Comp. E */ +//#define RESERVED (0x0020u) /* Comp. E */ +//#define RESERVED (0x0040u) /* Comp. E */ +#define CEIPEN_L (0x0080u) /* Comp. E Pos. Channel Input Enable */ +//#define RESERVED (0x1000u) /* Comp. E */ +//#define RESERVED (0x2000u) /* Comp. E */ +//#define RESERVED (0x4000u) /* Comp. E */ + +/* CECTL0 Control Bits */ +//#define RESERVED (0x0010u) /* Comp. E */ +//#define RESERVED (0x0020u) /* Comp. E */ +//#define RESERVED (0x0040u) /* Comp. E */ +#define CEIMSEL0_H (0x0001u) /* Comp. E Neg. Channel Input Select 0 */ +#define CEIMSEL1_H (0x0002u) /* Comp. E Neg. Channel Input Select 1 */ +#define CEIMSEL2_H (0x0004u) /* Comp. E Neg. Channel Input Select 2 */ +#define CEIMSEL3_H (0x0008u) /* Comp. E Neg. Channel Input Select 3 */ +//#define RESERVED (0x1000u) /* Comp. E */ +//#define RESERVED (0x2000u) /* Comp. E */ +//#define RESERVED (0x4000u) /* Comp. E */ +#define CEIMEN_H (0x0080u) /* Comp. E Neg. Channel Input Enable */ + +#define CEIPSEL_0 (0x0000u) /* Comp. E V+ terminal Input Select: Channel 0 */ +#define CEIPSEL_1 (0x0001u) /* Comp. E V+ terminal Input Select: Channel 1 */ +#define CEIPSEL_2 (0x0002u) /* Comp. E V+ terminal Input Select: Channel 2 */ +#define CEIPSEL_3 (0x0003u) /* Comp. E V+ terminal Input Select: Channel 3 */ +#define CEIPSEL_4 (0x0004u) /* Comp. E V+ terminal Input Select: Channel 4 */ +#define CEIPSEL_5 (0x0005u) /* Comp. E V+ terminal Input Select: Channel 5 */ +#define CEIPSEL_6 (0x0006u) /* Comp. E V+ terminal Input Select: Channel 6 */ +#define CEIPSEL_7 (0x0007u) /* Comp. E V+ terminal Input Select: Channel 7 */ +#define CEIPSEL_8 (0x0008u) /* Comp. E V+ terminal Input Select: Channel 8 */ +#define CEIPSEL_9 (0x0009u) /* Comp. E V+ terminal Input Select: Channel 9 */ +#define CEIPSEL_10 (0x000Au) /* Comp. E V+ terminal Input Select: Channel 10 */ +#define CEIPSEL_11 (0x000Bu) /* Comp. E V+ terminal Input Select: Channel 11 */ +#define CEIPSEL_12 (0x000Cu) /* Comp. E V+ terminal Input Select: Channel 12 */ +#define CEIPSEL_13 (0x000Du) /* Comp. E V+ terminal Input Select: Channel 13 */ +#define CEIPSEL_14 (0x000Eu) /* Comp. E V+ terminal Input Select: Channel 14 */ +#define CEIPSEL_15 (0x000Fu) /* Comp. E V+ terminal Input Select: Channel 15 */ + +#define CEIMSEL_0 (0x0000u) /* Comp. E V- Terminal Input Select: Channel 0 */ +#define CEIMSEL_1 (0x0100u) /* Comp. E V- Terminal Input Select: Channel 1 */ +#define CEIMSEL_2 (0x0200u) /* Comp. E V- Terminal Input Select: Channel 2 */ +#define CEIMSEL_3 (0x0300u) /* Comp. E V- Terminal Input Select: Channel 3 */ +#define CEIMSEL_4 (0x0400u) /* Comp. E V- Terminal Input Select: Channel 4 */ +#define CEIMSEL_5 (0x0500u) /* Comp. E V- Terminal Input Select: Channel 5 */ +#define CEIMSEL_6 (0x0600u) /* Comp. E V- Terminal Input Select: Channel 6 */ +#define CEIMSEL_7 (0x0700u) /* Comp. E V- Terminal Input Select: Channel 7 */ +#define CEIMSEL_8 (0x0800u) /* Comp. E V- terminal Input Select: Channel 8 */ +#define CEIMSEL_9 (0x0900u) /* Comp. E V- terminal Input Select: Channel 9 */ +#define CEIMSEL_10 (0x0A00u) /* Comp. E V- terminal Input Select: Channel 10 */ +#define CEIMSEL_11 (0x0B00u) /* Comp. E V- terminal Input Select: Channel 11 */ +#define CEIMSEL_12 (0x0C00u) /* Comp. E V- terminal Input Select: Channel 12 */ +#define CEIMSEL_13 (0x0D00u) /* Comp. E V- terminal Input Select: Channel 13 */ +#define CEIMSEL_14 (0x0E00u) /* Comp. E V- terminal Input Select: Channel 14 */ +#define CEIMSEL_15 (0x0F00u) /* Comp. E V- terminal Input Select: Channel 15 */ + +/* CECTL1 Control Bits */ +#define CEOUT (0x0001u) /* Comp. E Output */ +#define CEOUTPOL (0x0002u) /* Comp. E Output Polarity */ +#define CEF (0x0004u) /* Comp. E Enable Output Filter */ +#define CEIES (0x0008u) /* Comp. E Interrupt Edge Select */ +#define CESHORT (0x0010u) /* Comp. E Input Short */ +#define CEEX (0x0020u) /* Comp. E Exchange Inputs */ +#define CEFDLY0 (0x0040u) /* Comp. E Filter delay Bit 0 */ +#define CEFDLY1 (0x0080u) /* Comp. E Filter delay Bit 1 */ +#define CEPWRMD0 (0x0100u) /* Comp. E Power mode Bit 0 */ +#define CEPWRMD1 (0x0200u) /* Comp. E Power mode Bit 1 */ +#define CEON (0x0400u) /* Comp. E enable */ +#define CEMRVL (0x0800u) /* Comp. E CEMRV Level */ +#define CEMRVS (0x1000u) /* Comp. E Output selects between VREF0 or VREF1*/ +//#define RESERVED (0x2000u) /* Comp. E */ +//#define RESERVED (0x4000u) /* Comp. E */ +//#define RESERVED (0x8000u) /* Comp. E */ + +/* CECTL1 Control Bits */ +#define CEOUT_L (0x0001u) /* Comp. E Output */ +#define CEOUTPOL_L (0x0002u) /* Comp. E Output Polarity */ +#define CEF_L (0x0004u) /* Comp. E Enable Output Filter */ +#define CEIES_L (0x0008u) /* Comp. E Interrupt Edge Select */ +#define CESHORT_L (0x0010u) /* Comp. E Input Short */ +#define CEEX_L (0x0020u) /* Comp. E Exchange Inputs */ +#define CEFDLY0_L (0x0040u) /* Comp. E Filter delay Bit 0 */ +#define CEFDLY1_L (0x0080u) /* Comp. E Filter delay Bit 1 */ +//#define RESERVED (0x2000u) /* Comp. E */ +//#define RESERVED (0x4000u) /* Comp. E */ +//#define RESERVED (0x8000u) /* Comp. E */ + +/* CECTL1 Control Bits */ +#define CEPWRMD0_H (0x0001u) /* Comp. E Power mode Bit 0 */ +#define CEPWRMD1_H (0x0002u) /* Comp. E Power mode Bit 1 */ +#define CEON_H (0x0004u) /* Comp. E enable */ +#define CEMRVL_H (0x0008u) /* Comp. E CEMRV Level */ +#define CEMRVS_H (0x0010u) /* Comp. E Output selects between VREF0 or VREF1*/ +//#define RESERVED (0x2000u) /* Comp. E */ +//#define RESERVED (0x4000u) /* Comp. E */ +//#define RESERVED (0x8000u) /* Comp. E */ + +#define CEPWRMD_0 (0x0000u) /* Comp. E Power mode 0 */ +#define CEPWRMD_1 (0x0100u) /* Comp. E Power mode 1 */ +#define CEPWRMD_2 (0x0200u) /* Comp. E Power mode 2 */ +#define CEPWRMD_3 (0x0300u) /* Comp. E Power mode 3*/ + +#define CEFDLY_0 (0x0000u) /* Comp. E Filter delay 0 : 450ns */ +#define CEFDLY_1 (0x0040u) /* Comp. E Filter delay 1 : 900ns */ +#define CEFDLY_2 (0x0080u) /* Comp. E Filter delay 2 : 1800ns */ +#define CEFDLY_3 (0x00C0u) /* Comp. E Filter delay 3 : 3600ns */ + +/* CECTL2 Control Bits */ +#define CEREF00 (0x0001u) /* Comp. E Reference 0 Resistor Select Bit : 0 */ +#define CEREF01 (0x0002u) /* Comp. E Reference 0 Resistor Select Bit : 1 */ +#define CEREF02 (0x0004u) /* Comp. E Reference 0 Resistor Select Bit : 2 */ +#define CEREF03 (0x0008u) /* Comp. E Reference 0 Resistor Select Bit : 3 */ +#define CEREF04 (0x0010u) /* Comp. E Reference 0 Resistor Select Bit : 4 */ +#define CERSEL (0x0020u) /* Comp. E Reference select */ +#define CERS0 (0x0040u) /* Comp. E Reference Source Bit : 0 */ +#define CERS1 (0x0080u) /* Comp. E Reference Source Bit : 1 */ +#define CEREF10 (0x0100u) /* Comp. E Reference 1 Resistor Select Bit : 0 */ +#define CEREF11 (0x0200u) /* Comp. E Reference 1 Resistor Select Bit : 1 */ +#define CEREF12 (0x0400u) /* Comp. E Reference 1 Resistor Select Bit : 2 */ +#define CEREF13 (0x0800u) /* Comp. E Reference 1 Resistor Select Bit : 3 */ +#define CEREF14 (0x1000u) /* Comp. E Reference 1 Resistor Select Bit : 4 */ +#define CEREFL0 (0x2000u) /* Comp. E Reference voltage level Bit : 0 */ +#define CEREFL1 (0x4000u) /* Comp. E Reference voltage level Bit : 1 */ +#define CEREFACC (0x8000u) /* Comp. E Reference Accuracy */ + +/* CECTL2 Control Bits */ +#define CEREF00_L (0x0001u) /* Comp. E Reference 0 Resistor Select Bit : 0 */ +#define CEREF01_L (0x0002u) /* Comp. E Reference 0 Resistor Select Bit : 1 */ +#define CEREF02_L (0x0004u) /* Comp. E Reference 0 Resistor Select Bit : 2 */ +#define CEREF03_L (0x0008u) /* Comp. E Reference 0 Resistor Select Bit : 3 */ +#define CEREF04_L (0x0010u) /* Comp. E Reference 0 Resistor Select Bit : 4 */ +#define CERSEL_L (0x0020u) /* Comp. E Reference select */ +#define CERS0_L (0x0040u) /* Comp. E Reference Source Bit : 0 */ +#define CERS1_L (0x0080u) /* Comp. E Reference Source Bit : 1 */ + +/* CECTL2 Control Bits */ +#define CEREF10_H (0x0001u) /* Comp. E Reference 1 Resistor Select Bit : 0 */ +#define CEREF11_H (0x0002u) /* Comp. E Reference 1 Resistor Select Bit : 1 */ +#define CEREF12_H (0x0004u) /* Comp. E Reference 1 Resistor Select Bit : 2 */ +#define CEREF13_H (0x0008u) /* Comp. E Reference 1 Resistor Select Bit : 3 */ +#define CEREF14_H (0x0010u) /* Comp. E Reference 1 Resistor Select Bit : 4 */ +#define CEREFL0_H (0x0020u) /* Comp. E Reference voltage level Bit : 0 */ +#define CEREFL1_H (0x0040u) /* Comp. E Reference voltage level Bit : 1 */ +#define CEREFACC_H (0x0080u) /* Comp. E Reference Accuracy */ + +#define CEREF0_0 (0x0000u) /* Comp. E Int. Ref.0 Select 0 : 1/32 */ +#define CEREF0_1 (0x0001u) /* Comp. E Int. Ref.0 Select 1 : 2/32 */ +#define CEREF0_2 (0x0002u) /* Comp. E Int. Ref.0 Select 2 : 3/32 */ +#define CEREF0_3 (0x0003u) /* Comp. E Int. Ref.0 Select 3 : 4/32 */ +#define CEREF0_4 (0x0004u) /* Comp. E Int. Ref.0 Select 4 : 5/32 */ +#define CEREF0_5 (0x0005u) /* Comp. E Int. Ref.0 Select 5 : 6/32 */ +#define CEREF0_6 (0x0006u) /* Comp. E Int. Ref.0 Select 6 : 7/32 */ +#define CEREF0_7 (0x0007u) /* Comp. E Int. Ref.0 Select 7 : 8/32 */ +#define CEREF0_8 (0x0008u) /* Comp. E Int. Ref.0 Select 0 : 9/32 */ +#define CEREF0_9 (0x0009u) /* Comp. E Int. Ref.0 Select 1 : 10/32 */ +#define CEREF0_10 (0x000Au) /* Comp. E Int. Ref.0 Select 2 : 11/32 */ +#define CEREF0_11 (0x000Bu) /* Comp. E Int. Ref.0 Select 3 : 12/32 */ +#define CEREF0_12 (0x000Cu) /* Comp. E Int. Ref.0 Select 4 : 13/32 */ +#define CEREF0_13 (0x000Du) /* Comp. E Int. Ref.0 Select 5 : 14/32 */ +#define CEREF0_14 (0x000Eu) /* Comp. E Int. Ref.0 Select 6 : 15/32 */ +#define CEREF0_15 (0x000Fu) /* Comp. E Int. Ref.0 Select 7 : 16/32 */ +#define CEREF0_16 (0x0010u) /* Comp. E Int. Ref.0 Select 0 : 17/32 */ +#define CEREF0_17 (0x0011u) /* Comp. E Int. Ref.0 Select 1 : 18/32 */ +#define CEREF0_18 (0x0012u) /* Comp. E Int. Ref.0 Select 2 : 19/32 */ +#define CEREF0_19 (0x0013u) /* Comp. E Int. Ref.0 Select 3 : 20/32 */ +#define CEREF0_20 (0x0014u) /* Comp. E Int. Ref.0 Select 4 : 21/32 */ +#define CEREF0_21 (0x0015u) /* Comp. E Int. Ref.0 Select 5 : 22/32 */ +#define CEREF0_22 (0x0016u) /* Comp. E Int. Ref.0 Select 6 : 23/32 */ +#define CEREF0_23 (0x0017u) /* Comp. E Int. Ref.0 Select 7 : 24/32 */ +#define CEREF0_24 (0x0018u) /* Comp. E Int. Ref.0 Select 0 : 25/32 */ +#define CEREF0_25 (0x0019u) /* Comp. E Int. Ref.0 Select 1 : 26/32 */ +#define CEREF0_26 (0x001Au) /* Comp. E Int. Ref.0 Select 2 : 27/32 */ +#define CEREF0_27 (0x001Bu) /* Comp. E Int. Ref.0 Select 3 : 28/32 */ +#define CEREF0_28 (0x001Cu) /* Comp. E Int. Ref.0 Select 4 : 29/32 */ +#define CEREF0_29 (0x001Du) /* Comp. E Int. Ref.0 Select 5 : 30/32 */ +#define CEREF0_30 (0x001Eu) /* Comp. E Int. Ref.0 Select 6 : 31/32 */ +#define CEREF0_31 (0x001Fu) /* Comp. E Int. Ref.0 Select 7 : 32/32 */ + +#define CERS_0 (0x0000u) /* Comp. E Reference Source 0 : Off */ +#define CERS_1 (0x0040u) /* Comp. E Reference Source 1 : Vcc */ +#define CERS_2 (0x0080u) /* Comp. E Reference Source 2 : Shared Ref. */ +#define CERS_3 (0x00C0u) /* Comp. E Reference Source 3 : Shared Ref. / Off */ + +#define CEREF1_0 (0x0000u) /* Comp. E Int. Ref.1 Select 0 : 1/32 */ +#define CEREF1_1 (0x0100u) /* Comp. E Int. Ref.1 Select 1 : 2/32 */ +#define CEREF1_2 (0x0200u) /* Comp. E Int. Ref.1 Select 2 : 3/32 */ +#define CEREF1_3 (0x0300u) /* Comp. E Int. Ref.1 Select 3 : 4/32 */ +#define CEREF1_4 (0x0400u) /* Comp. E Int. Ref.1 Select 4 : 5/32 */ +#define CEREF1_5 (0x0500u) /* Comp. E Int. Ref.1 Select 5 : 6/32 */ +#define CEREF1_6 (0x0600u) /* Comp. E Int. Ref.1 Select 6 : 7/32 */ +#define CEREF1_7 (0x0700u) /* Comp. E Int. Ref.1 Select 7 : 8/32 */ +#define CEREF1_8 (0x0800u) /* Comp. E Int. Ref.1 Select 0 : 9/32 */ +#define CEREF1_9 (0x0900u) /* Comp. E Int. Ref.1 Select 1 : 10/32 */ +#define CEREF1_10 (0x0A00u) /* Comp. E Int. Ref.1 Select 2 : 11/32 */ +#define CEREF1_11 (0x0B00u) /* Comp. E Int. Ref.1 Select 3 : 12/32 */ +#define CEREF1_12 (0x0C00u) /* Comp. E Int. Ref.1 Select 4 : 13/32 */ +#define CEREF1_13 (0x0D00u) /* Comp. E Int. Ref.1 Select 5 : 14/32 */ +#define CEREF1_14 (0x0E00u) /* Comp. E Int. Ref.1 Select 6 : 15/32 */ +#define CEREF1_15 (0x0F00u) /* Comp. E Int. Ref.1 Select 7 : 16/32 */ +#define CEREF1_16 (0x1000u) /* Comp. E Int. Ref.1 Select 0 : 17/32 */ +#define CEREF1_17 (0x1100u) /* Comp. E Int. Ref.1 Select 1 : 18/32 */ +#define CEREF1_18 (0x1200u) /* Comp. E Int. Ref.1 Select 2 : 19/32 */ +#define CEREF1_19 (0x1300u) /* Comp. E Int. Ref.1 Select 3 : 20/32 */ +#define CEREF1_20 (0x1400u) /* Comp. E Int. Ref.1 Select 4 : 21/32 */ +#define CEREF1_21 (0x1500u) /* Comp. E Int. Ref.1 Select 5 : 22/32 */ +#define CEREF1_22 (0x1600u) /* Comp. E Int. Ref.1 Select 6 : 23/32 */ +#define CEREF1_23 (0x1700u) /* Comp. E Int. Ref.1 Select 7 : 24/32 */ +#define CEREF1_24 (0x1800u) /* Comp. E Int. Ref.1 Select 0 : 25/32 */ +#define CEREF1_25 (0x1900u) /* Comp. E Int. Ref.1 Select 1 : 26/32 */ +#define CEREF1_26 (0x1A00u) /* Comp. E Int. Ref.1 Select 2 : 27/32 */ +#define CEREF1_27 (0x1B00u) /* Comp. E Int. Ref.1 Select 3 : 28/32 */ +#define CEREF1_28 (0x1C00u) /* Comp. E Int. Ref.1 Select 4 : 29/32 */ +#define CEREF1_29 (0x1D00u) /* Comp. E Int. Ref.1 Select 5 : 30/32 */ +#define CEREF1_30 (0x1E00u) /* Comp. E Int. Ref.1 Select 6 : 31/32 */ +#define CEREF1_31 (0x1F00u) /* Comp. E Int. Ref.1 Select 7 : 32/32 */ + +#define CEREFL_0 (0x0000u) /* Comp. E Reference voltage level 0 : None */ +#define CEREFL_1 (0x2000u) /* Comp. E Reference voltage level 1 : 1.2V */ +#define CEREFL_2 (0x4000u) /* Comp. E Reference voltage level 2 : 2.0V */ +#define CEREFL_3 (0x6000u) /* Comp. E Reference voltage level 3 : 2.5V */ + +#define CEPD0 (0x0001u) /* Comp. E Disable Input Buffer of Port Register .0 */ +#define CEPD1 (0x0002u) /* Comp. E Disable Input Buffer of Port Register .1 */ +#define CEPD2 (0x0004u) /* Comp. E Disable Input Buffer of Port Register .2 */ +#define CEPD3 (0x0008u) /* Comp. E Disable Input Buffer of Port Register .3 */ +#define CEPD4 (0x0010u) /* Comp. E Disable Input Buffer of Port Register .4 */ +#define CEPD5 (0x0020u) /* Comp. E Disable Input Buffer of Port Register .5 */ +#define CEPD6 (0x0040u) /* Comp. E Disable Input Buffer of Port Register .6 */ +#define CEPD7 (0x0080u) /* Comp. E Disable Input Buffer of Port Register .7 */ +#define CEPD8 (0x0100u) /* Comp. E Disable Input Buffer of Port Register .8 */ +#define CEPD9 (0x0200u) /* Comp. E Disable Input Buffer of Port Register .9 */ +#define CEPD10 (0x0400u) /* Comp. E Disable Input Buffer of Port Register .10 */ +#define CEPD11 (0x0800u) /* Comp. E Disable Input Buffer of Port Register .11 */ +#define CEPD12 (0x1000u) /* Comp. E Disable Input Buffer of Port Register .12 */ +#define CEPD13 (0x2000u) /* Comp. E Disable Input Buffer of Port Register .13 */ +#define CEPD14 (0x4000u) /* Comp. E Disable Input Buffer of Port Register .14 */ +#define CEPD15 (0x8000u) /* Comp. E Disable Input Buffer of Port Register .15 */ + +#define CEPD0_L (0x0001u) /* Comp. E Disable Input Buffer of Port Register .0 */ +#define CEPD1_L (0x0002u) /* Comp. E Disable Input Buffer of Port Register .1 */ +#define CEPD2_L (0x0004u) /* Comp. E Disable Input Buffer of Port Register .2 */ +#define CEPD3_L (0x0008u) /* Comp. E Disable Input Buffer of Port Register .3 */ +#define CEPD4_L (0x0010u) /* Comp. E Disable Input Buffer of Port Register .4 */ +#define CEPD5_L (0x0020u) /* Comp. E Disable Input Buffer of Port Register .5 */ +#define CEPD6_L (0x0040u) /* Comp. E Disable Input Buffer of Port Register .6 */ +#define CEPD7_L (0x0080u) /* Comp. E Disable Input Buffer of Port Register .7 */ + +#define CEPD8_H (0x0001u) /* Comp. E Disable Input Buffer of Port Register .8 */ +#define CEPD9_H (0x0002u) /* Comp. E Disable Input Buffer of Port Register .9 */ +#define CEPD10_H (0x0004u) /* Comp. E Disable Input Buffer of Port Register .10 */ +#define CEPD11_H (0x0008u) /* Comp. E Disable Input Buffer of Port Register .11 */ +#define CEPD12_H (0x0010u) /* Comp. E Disable Input Buffer of Port Register .12 */ +#define CEPD13_H (0x0020u) /* Comp. E Disable Input Buffer of Port Register .13 */ +#define CEPD14_H (0x0040u) /* Comp. E Disable Input Buffer of Port Register .14 */ +#define CEPD15_H (0x0080u) /* Comp. E Disable Input Buffer of Port Register .15 */ + +/* CEINT Control Bits */ +#define CEIFG (0x0001u) /* Comp. E Interrupt Flag */ +#define CEIIFG (0x0002u) /* Comp. E Interrupt Flag Inverted Polarity */ +//#define RESERVED (0x0004u) /* Comp. E */ +//#define RESERVED (0x0008u) /* Comp. E */ +#define CERDYIFG (0x0010u) /* Comp. E Comparator_E ready interrupt flag */ +//#define RESERVED (0x0020u) /* Comp. E */ +//#define RESERVED (0x0040u) /* Comp. E */ +//#define RESERVED (0x0080u) /* Comp. E */ +#define CEIE (0x0100u) /* Comp. E Interrupt Enable */ +#define CEIIE (0x0200u) /* Comp. E Interrupt Enable Inverted Polarity */ +//#define RESERVED (0x0400u) /* Comp. E */ +//#define RESERVED (0x0800u) /* Comp. E */ +#define CERDYIE (0x1000u) /* Comp. E Comparator_E ready interrupt enable */ +//#define RESERVED (0x2000u) /* Comp. E */ +//#define RESERVED (0x4000u) /* Comp. E */ +//#define RESERVED (0x8000u) /* Comp. E */ + +/* CEINT Control Bits */ +#define CEIFG_L (0x0001u) /* Comp. E Interrupt Flag */ +#define CEIIFG_L (0x0002u) /* Comp. E Interrupt Flag Inverted Polarity */ +//#define RESERVED (0x0004u) /* Comp. E */ +//#define RESERVED (0x0008u) /* Comp. E */ +#define CERDYIFG_L (0x0010u) /* Comp. E Comparator_E ready interrupt flag */ +//#define RESERVED (0x0020u) /* Comp. E */ +//#define RESERVED (0x0040u) /* Comp. E */ +//#define RESERVED (0x0080u) /* Comp. E */ +//#define RESERVED (0x0400u) /* Comp. E */ +//#define RESERVED (0x0800u) /* Comp. E */ +//#define RESERVED (0x2000u) /* Comp. E */ +//#define RESERVED (0x4000u) /* Comp. E */ +//#define RESERVED (0x8000u) /* Comp. E */ + +/* CEINT Control Bits */ +//#define RESERVED (0x0004u) /* Comp. E */ +//#define RESERVED (0x0008u) /* Comp. E */ +//#define RESERVED (0x0020u) /* Comp. E */ +//#define RESERVED (0x0040u) /* Comp. E */ +//#define RESERVED (0x0080u) /* Comp. E */ +#define CEIE_H (0x0001u) /* Comp. E Interrupt Enable */ +#define CEIIE_H (0x0002u) /* Comp. E Interrupt Enable Inverted Polarity */ +//#define RESERVED (0x0400u) /* Comp. E */ +//#define RESERVED (0x0800u) /* Comp. E */ +#define CERDYIE_H (0x0010u) /* Comp. E Comparator_E ready interrupt enable */ +//#define RESERVED (0x2000u) /* Comp. E */ +//#define RESERVED (0x4000u) /* Comp. E */ +//#define RESERVED (0x8000u) /* Comp. E */ + +/* CEIV Definitions */ +#define CEIV_NONE (0x0000u) /* No Interrupt pending */ +#define CEIV_CEIFG (0x0002u) /* CEIFG */ +#define CEIV_CEIIFG (0x0004u) /* CEIIFG */ +#define CEIV_CERDYIFG (0x000Au) /* CERDYIFG */ + +#endif +/************************************************************* +* CRC Module +*************************************************************/ +#ifdef __MSP430_HAS_CRC__ /* Definition to show that Module is available */ + +#define OFS_CRCDI (0x0000u) /* CRC Data In Register */ +#define OFS_CRCDI_L OFS_CRCDI +#define OFS_CRCDI_H OFS_CRCDI+1 +#define OFS_CRCDIRB (0x0002u) /* CRC data in reverse byte Register */ +#define OFS_CRCDIRB_L OFS_CRCDIRB +#define OFS_CRCDIRB_H OFS_CRCDIRB+1 +#define OFS_CRCINIRES (0x0004u) /* CRC Initialisation Register and Result Register */ +#define OFS_CRCINIRES_L OFS_CRCINIRES +#define OFS_CRCINIRES_H OFS_CRCINIRES+1 +#define OFS_CRCRESR (0x0006u) /* CRC reverse result Register */ +#define OFS_CRCRESR_L OFS_CRCRESR +#define OFS_CRCRESR_H OFS_CRCRESR+1 + +#endif +/************************************************************* +* CRC Module +*************************************************************/ +#ifdef __MSP430_HAS_CRC32__ /* Definition to show that Module is available */ + + +//#define CRC32DIL0_O (0x0000u) /* CRC32 Data In */ +#define OFS_CRC32DIW0 (0x0000u) /* CRC32 Data In */ +#define OFS_CRC32DIW0_L OFS_CRC32DIW0 +#define OFS_CRC32DIW0_H OFS_CRC32DIW0+1 +#define OFS_CRC32DIW1 (0x0002u) /* CRC32 Data In */ +#define OFS_CRC32DIW1_L OFS_CRC32DIW1 +#define OFS_CRC32DIW1_H OFS_CRC32DIW1+1 +#define CRC32DIB0 CRC32DIW0_L + +//#define CRC32DIRBL0_O (0x0004u) /* CRC32 Data In Reversed Bit */ +#define OFS_CRC32DIRBW1 (0x0004u) /* CRC32 Data In Reversed Bit */ +#define OFS_CRC32DIRBW1_L OFS_CRC32DIRBW1 +#define OFS_CRC32DIRBW1_H OFS_CRC32DIRBW1+1 +#define OFS_CRC32DIRBW0 (0x0006u) /* CRC32 Data In Reversed Bit */ +#define OFS_CRC32DIRBW0_L OFS_CRC32DIRBW0 +#define OFS_CRC32DIRBW0_H OFS_CRC32DIRBW0+1 +#define CRC32DIRBB0 CRC32DIRBW0_H + +//#define CRC32INIRESL0_O (0x0008u) /* CRC32 Initialization and Result */ +#define OFS_CRC32INIRESW0 (0x0008u) /* CRC32 Initialization and Result */ +#define OFS_CRC32INIRESW0_L OFS_CRC32INIRESW0 +#define OFS_CRC32INIRESW0_H OFS_CRC32INIRESW0+1 +#define OFS_CRC32INIRESW1 (0x000Au) /* CRC32 Initialization and Result */ +#define OFS_CRC32INIRESW1_L OFS_CRC32INIRESW1 +#define OFS_CRC32INIRESW1_H OFS_CRC32INIRESW1+1 +#define CRC32RESB0 CRC32INIRESW0_L +#define CRC32RESB1 CRC32INIRESW0_H +#define CRC32RESB2 CRC32INIRESW1_L +#define CRC32RESB3 CRC32INIRESW1_H + +//#define CRC32RESRL0_O (0x000Cu) /* CRC32 Result Reverse */ +#define OFS_CRC32RESRW1 (0x000Cu) /* CRC32 Result Reverse */ +#define OFS_CRC32RESRW1_L OFS_CRC32RESRW1 +#define OFS_CRC32RESRW1_H OFS_CRC32RESRW1+1 +#define OFS_CRC32RESRW0 (0x000Eu) /* CRC32 Result Reverse */ +#define OFS_CRC32RESRW0_L OFS_CRC32RESRW0 +#define OFS_CRC32RESRW0_H OFS_CRC32RESRW0+1 +#define CRC32RESRB3 CRC32RESRW1_L +#define CRC32RESRB2 CRC32RESRW1_H +#define CRC32RESRB1 CRC32RESRW0_L +#define CRC32RESRB0 CRC32RESRW0_H + +//#define CRC16DIL0_O (0x0010u) /* CRC16 Data Input */ +#define OFS_CRC16DIW0 (0x0010u) /* CRC16 Data Input */ +#define OFS_CRC16DIW0_L OFS_CRC16DIW0 +#define OFS_CRC16DIW0_H OFS_CRC16DIW0+1 +#define OFS_CRC16DIW1 (0x0012u) /* CRC16 Data Input */ +#define OFS_CRC16DIW1_L OFS_CRC16DIW1 +#define OFS_CRC16DIW1_H OFS_CRC16DIW1+1 +#define CRC16DIB0 CRC16DIW0_L +//#define CRC16DIRBL0_O (0x0014u) /* CRC16 Data In Reverse */ +#define OFS_CRC16DIRBW1 (0x0014u) /* CRC16 Data In Reverse */ +#define OFS_CRC16DIRBW1_L OFS_CRC16DIRBW1 +#define OFS_CRC16DIRBW1_H OFS_CRC16DIRBW1+1 +#define OFS_CRC16DIRBW0 (0x0016u) /* CRC16 Data In Reverse */ +#define OFS_CRC16DIRBW0_L OFS_CRC16DIRBW0 +#define OFS_CRC16DIRBW0_H OFS_CRC16DIRBW0+1 +#define CRC16DIRBB0 CRC16DIRBW0_L + +//#define CRC16INIRESL0_O (0x0018u) /* CRC16 Init and Result */ +#define OFS_CRC16INIRESW0 (0x0018u) /* CRC16 Init and Result */ +#define OFS_CRC16INIRESW0_L OFS_CRC16INIRESW0 +#define OFS_CRC16INIRESW0_H OFS_CRC16INIRESW0+1 +#define CRC16INIRESB1 CRC16INIRESW0_H +#define CRC16INIRESB0 CRC16INIRESW0_L + +//#define CRC16RESRL0_O (0x001Eu) /* CRC16 Result Reverse */ +#define OFS_CRC16RESRW0 (0x001Eu) /* CRC16 Result Reverse */ +#define OFS_CRC16RESRW0_L OFS_CRC16RESRW0 +#define OFS_CRC16RESRW0_H OFS_CRC16RESRW0+1 +#define OFS_CRC16RESRW1 (0x001Cu) /* CRC16 Result Reverse */ +#define OFS_CRC16RESRW1_L OFS_CRC16RESRW1 +#define OFS_CRC16RESRW1_H OFS_CRC16RESRW1+1 +#define CRC16RESRB1 CRC16RESRW0_L +#define CRC16RESRB0 CRC16RESRW0_H + +#endif +/************************************************************ +* CLOCK SYSTEM +************************************************************/ +#ifdef __MSP430_HAS_CS__ /* Definition to show that Module is available */ + +#define OFS_CSCTL0 (0x0000u) /* CS Control Register 0 */ +#define OFS_CSCTL0_L OFS_CSCTL0 +#define OFS_CSCTL0_H OFS_CSCTL0+1 +#define OFS_CSCTL1 (0x0002u) /* CS Control Register 1 */ +#define OFS_CSCTL1_L OFS_CSCTL1 +#define OFS_CSCTL1_H OFS_CSCTL1+1 +#define OFS_CSCTL2 (0x0004u) /* CS Control Register 2 */ +#define OFS_CSCTL2_L OFS_CSCTL2 +#define OFS_CSCTL2_H OFS_CSCTL2+1 +#define OFS_CSCTL3 (0x0006u) /* CS Control Register 3 */ +#define OFS_CSCTL3_L OFS_CSCTL3 +#define OFS_CSCTL3_H OFS_CSCTL3+1 +#define OFS_CSCTL4 (0x0008u) /* CS Control Register 4 */ +#define OFS_CSCTL4_L OFS_CSCTL4 +#define OFS_CSCTL4_H OFS_CSCTL4+1 +#define OFS_CSCTL5 (0x000Au) /* CS Control Register 5 */ +#define OFS_CSCTL5_L OFS_CSCTL5 +#define OFS_CSCTL5_H OFS_CSCTL5+1 +#define OFS_CSCTL6 (0x000Cu) /* CS Control Register 6 */ +#define OFS_CSCTL6_L OFS_CSCTL6 +#define OFS_CSCTL6_H OFS_CSCTL6+1 + +/* CSCTL0 Control Bits */ + +#define CSKEY (0xA500u) /* CS Password */ +#define CSKEY_H (0xA5) /* CS Password for high byte access */ + +/* CSCTL1 Control Bits */ +#define DCOFSEL0 (0x0002u) /* DCO frequency select Bit: 0 */ +#define DCOFSEL1 (0x0004u) /* DCO frequency select Bit: 1 */ +#define DCOFSEL2 (0x0008u) /* DCO frequency select Bit: 2 */ +#define DCORSEL (0x0040u) /* DCO range select. */ + +/* CSCTL1 Control Bits */ +#define DCOFSEL0_L (0x0002u) /* DCO frequency select Bit: 0 */ +#define DCOFSEL1_L (0x0004u) /* DCO frequency select Bit: 1 */ +#define DCOFSEL2_L (0x0008u) /* DCO frequency select Bit: 2 */ +#define DCORSEL_L (0x0040u) /* DCO range select. */ + +#define DCOFSEL_0 (0x0000u) /* DCO frequency select: 0 */ +#define DCOFSEL_1 (0x0002u) /* DCO frequency select: 1 */ +#define DCOFSEL_2 (0x0004u) /* DCO frequency select: 2 */ +#define DCOFSEL_3 (0x0006u) /* DCO frequency select: 3 */ +#define DCOFSEL_4 (0x0008u) /* DCO frequency select: 4 */ +#define DCOFSEL_5 (0x000Au) /* DCO frequency select: 5 */ +#define DCOFSEL_6 (0x000Cu) /* DCO frequency select: 6 */ +#define DCOFSEL_7 (0x000Eu) /* DCO frequency select: 7 */ + +/* CSCTL2 Control Bits */ +#define SELM0 (0x0001u) /* MCLK Source Select Bit: 0 */ +#define SELM1 (0x0002u) /* MCLK Source Select Bit: 1 */ +#define SELM2 (0x0004u) /* MCLK Source Select Bit: 2 */ +//#define RESERVED (0x0004u) /* RESERVED */ +//#define RESERVED (0x0008u) /* RESERVED */ +#define SELS0 (0x0010u) /* SMCLK Source Select Bit: 0 */ +#define SELS1 (0x0020u) /* SMCLK Source Select Bit: 1 */ +#define SELS2 (0x0040u) /* SMCLK Source Select Bit: 2 */ +//#define RESERVED (0x0040u) /* RESERVED */ +//#define RESERVED (0x0080u) /* RESERVED */ +#define SELA0 (0x0100u) /* ACLK Source Select Bit: 0 */ +#define SELA1 (0x0200u) /* ACLK Source Select Bit: 1 */ +#define SELA2 (0x0400u) /* ACLK Source Select Bit: 2 */ +//#define RESERVED (0x0400u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x1000u) /* RESERVED */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +/* CSCTL2 Control Bits */ +#define SELM0_L (0x0001u) /* MCLK Source Select Bit: 0 */ +#define SELM1_L (0x0002u) /* MCLK Source Select Bit: 1 */ +#define SELM2_L (0x0004u) /* MCLK Source Select Bit: 2 */ +//#define RESERVED (0x0004u) /* RESERVED */ +//#define RESERVED (0x0008u) /* RESERVED */ +#define SELS0_L (0x0010u) /* SMCLK Source Select Bit: 0 */ +#define SELS1_L (0x0020u) /* SMCLK Source Select Bit: 1 */ +#define SELS2_L (0x0040u) /* SMCLK Source Select Bit: 2 */ +//#define RESERVED (0x0040u) /* RESERVED */ +//#define RESERVED (0x0080u) /* RESERVED */ +//#define RESERVED (0x0400u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x1000u) /* RESERVED */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +/* CSCTL2 Control Bits */ +//#define RESERVED (0x0004u) /* RESERVED */ +//#define RESERVED (0x0008u) /* RESERVED */ +//#define RESERVED (0x0040u) /* RESERVED */ +//#define RESERVED (0x0080u) /* RESERVED */ +#define SELA0_H (0x0001u) /* ACLK Source Select Bit: 0 */ +#define SELA1_H (0x0002u) /* ACLK Source Select Bit: 1 */ +#define SELA2_H (0x0004u) /* ACLK Source Select Bit: 2 */ +//#define RESERVED (0x0400u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x1000u) /* RESERVED */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +#define SELM_0 (0x0000u) /* MCLK Source Select 0 */ +#define SELM_1 (0x0001u) /* MCLK Source Select 1 */ +#define SELM_2 (0x0002u) /* MCLK Source Select 2 */ +#define SELM_3 (0x0003u) /* MCLK Source Select 3 */ +#define SELM_4 (0x0004u) /* MCLK Source Select 4 */ +#define SELM_5 (0x0005u) /* MCLK Source Select 5 */ +#define SELM_6 (0x0006u) /* MCLK Source Select 6 */ +#define SELM_7 (0x0007u) /* MCLK Source Select 7 */ +#define SELM__LFXTCLK (0x0000u) /* MCLK Source Select LFXTCLK */ +#define SELM__VLOCLK (0x0001u) /* MCLK Source Select VLOCLK */ +#define SELM__LFMODOSC (0x0002u) /* MCLK Source Select LFMODOSC */ +#define SELM__DCOCLK (0x0003u) /* MCLK Source Select DCOCLK */ +#define SELM__MODOSC (0x0004u) /* MCLK Source Select MODOSC */ +#define SELM__HFXTCLK (0x0005u) /* MCLK Source Select HFXTCLK */ + +#define SELS_0 (0x0000u) /* SMCLK Source Select 0 */ +#define SELS_1 (0x0010u) /* SMCLK Source Select 1 */ +#define SELS_2 (0x0020u) /* SMCLK Source Select 2 */ +#define SELS_3 (0x0030u) /* SMCLK Source Select 3 */ +#define SELS_4 (0x0040u) /* SMCLK Source Select 4 */ +#define SELS_5 (0x0050u) /* SMCLK Source Select 5 */ +#define SELS_6 (0x0060u) /* SMCLK Source Select 6 */ +#define SELS_7 (0x0070u) /* SMCLK Source Select 7 */ +#define SELS__LFXTCLK (0x0000u) /* SMCLK Source Select LFXTCLK */ +#define SELS__VLOCLK (0x0010u) /* SMCLK Source Select VLOCLK */ +#define SELS__LFMODOSC (0x0020u) /* SMCLK Source Select LFMODOSC */ +#define SELS__DCOCLK (0x0030u) /* SMCLK Source Select DCOCLK */ +#define SELS__MODOSC (0x0040u) /* SMCLK Source Select MODOSC */ +#define SELS__HFXTCLK (0x0050u) /* SMCLK Source Select HFXTCLK */ + +#define SELA_0 (0x0000u) /* ACLK Source Select 0 */ +#define SELA_1 (0x0100u) /* ACLK Source Select 1 */ +#define SELA_2 (0x0200u) /* ACLK Source Select 2 */ +#define SELA_3 (0x0300u) /* ACLK Source Select 3 */ +#define SELA_4 (0x0400u) /* ACLK Source Select 4 */ +#define SELA_5 (0x0500u) /* ACLK Source Select 5 */ +#define SELA_6 (0x0600u) /* ACLK Source Select 6 */ +#define SELA_7 (0x0700u) /* ACLK Source Select 7 */ +#define SELA__LFXTCLK (0x0000u) /* ACLK Source Select LFXTCLK */ +#define SELA__VLOCLK (0x0100u) /* ACLK Source Select VLOCLK */ +#define SELA__LFMODOSC (0x0200u) /* ACLK Source Select LFMODOSC */ + +/* CSCTL3 Control Bits */ +#define DIVM0 (0x0001u) /* MCLK Divider Bit: 0 */ +#define DIVM1 (0x0002u) /* MCLK Divider Bit: 1 */ +#define DIVM2 (0x0004u) /* MCLK Divider Bit: 2 */ +//#define RESERVED (0x0004u) /* RESERVED */ +//#define RESERVED (0x0008u) /* RESERVED */ +#define DIVS0 (0x0010u) /* SMCLK Divider Bit: 0 */ +#define DIVS1 (0x0020u) /* SMCLK Divider Bit: 1 */ +#define DIVS2 (0x0040u) /* SMCLK Divider Bit: 2 */ +//#define RESERVED (0x0040u) /* RESERVED */ +//#define RESERVED (0x0080u) /* RESERVED */ +#define DIVA0 (0x0100u) /* ACLK Divider Bit: 0 */ +#define DIVA1 (0x0200u) /* ACLK Divider Bit: 1 */ +#define DIVA2 (0x0400u) /* ACLK Divider Bit: 2 */ +//#define RESERVED (0x0400u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x1000u) /* RESERVED */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +/* CSCTL3 Control Bits */ +#define DIVM0_L (0x0001u) /* MCLK Divider Bit: 0 */ +#define DIVM1_L (0x0002u) /* MCLK Divider Bit: 1 */ +#define DIVM2_L (0x0004u) /* MCLK Divider Bit: 2 */ +//#define RESERVED (0x0004u) /* RESERVED */ +//#define RESERVED (0x0008u) /* RESERVED */ +#define DIVS0_L (0x0010u) /* SMCLK Divider Bit: 0 */ +#define DIVS1_L (0x0020u) /* SMCLK Divider Bit: 1 */ +#define DIVS2_L (0x0040u) /* SMCLK Divider Bit: 2 */ +//#define RESERVED (0x0040u) /* RESERVED */ +//#define RESERVED (0x0080u) /* RESERVED */ +//#define RESERVED (0x0400u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x1000u) /* RESERVED */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +/* CSCTL3 Control Bits */ +//#define RESERVED (0x0004u) /* RESERVED */ +//#define RESERVED (0x0008u) /* RESERVED */ +//#define RESERVED (0x0040u) /* RESERVED */ +//#define RESERVED (0x0080u) /* RESERVED */ +#define DIVA0_H (0x0001u) /* ACLK Divider Bit: 0 */ +#define DIVA1_H (0x0002u) /* ACLK Divider Bit: 1 */ +#define DIVA2_H (0x0004u) /* ACLK Divider Bit: 2 */ +//#define RESERVED (0x0400u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x1000u) /* RESERVED */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x4000u) /* RESERVED */ +//#define RESERVED (0x8000u) /* RESERVED */ + +#define DIVM_0 (0x0000u) /* MCLK Source Divider 0 */ +#define DIVM_1 (0x0001u) /* MCLK Source Divider 1 */ +#define DIVM_2 (0x0002u) /* MCLK Source Divider 2 */ +#define DIVM_3 (0x0003u) /* MCLK Source Divider 3 */ +#define DIVM_4 (0x0004u) /* MCLK Source Divider 4 */ +#define DIVM_5 (0x0005u) /* MCLK Source Divider 5 */ +#define DIVM__1 (0x0000u) /* MCLK Source Divider f(MCLK)/1 */ +#define DIVM__2 (0x0001u) /* MCLK Source Divider f(MCLK)/2 */ +#define DIVM__4 (0x0002u) /* MCLK Source Divider f(MCLK)/4 */ +#define DIVM__8 (0x0003u) /* MCLK Source Divider f(MCLK)/8 */ +#define DIVM__16 (0x0004u) /* MCLK Source Divider f(MCLK)/16 */ +#define DIVM__32 (0x0005u) /* MCLK Source Divider f(MCLK)/32 */ + +#define DIVS_0 (0x0000u) /* SMCLK Source Divider 0 */ +#define DIVS_1 (0x0010u) /* SMCLK Source Divider 1 */ +#define DIVS_2 (0x0020u) /* SMCLK Source Divider 2 */ +#define DIVS_3 (0x0030u) /* SMCLK Source Divider 3 */ +#define DIVS_4 (0x0040u) /* SMCLK Source Divider 4 */ +#define DIVS_5 (0x0050u) /* SMCLK Source Divider 5 */ +#define DIVS__1 (0x0000u) /* SMCLK Source Divider f(SMCLK)/1 */ +#define DIVS__2 (0x0010u) /* SMCLK Source Divider f(SMCLK)/2 */ +#define DIVS__4 (0x0020u) /* SMCLK Source Divider f(SMCLK)/4 */ +#define DIVS__8 (0x0030u) /* SMCLK Source Divider f(SMCLK)/8 */ +#define DIVS__16 (0x0040u) /* SMCLK Source Divider f(SMCLK)/16 */ +#define DIVS__32 (0x0050u) /* SMCLK Source Divider f(SMCLK)/32 */ + +#define DIVA_0 (0x0000u) /* ACLK Source Divider 0 */ +#define DIVA_1 (0x0100u) /* ACLK Source Divider 1 */ +#define DIVA_2 (0x0200u) /* ACLK Source Divider 2 */ +#define DIVA_3 (0x0300u) /* ACLK Source Divider 3 */ +#define DIVA_4 (0x0400u) /* ACLK Source Divider 4 */ +#define DIVA_5 (0x0500u) /* ACLK Source Divider 5 */ +#define DIVA__1 (0x0000u) /* ACLK Source Divider f(ACLK)/1 */ +#define DIVA__2 (0x0100u) /* ACLK Source Divider f(ACLK)/2 */ +#define DIVA__4 (0x0200u) /* ACLK Source Divider f(ACLK)/4 */ +#define DIVA__8 (0x0300u) /* ACLK Source Divider f(ACLK)/8 */ +#define DIVA__16 (0x0400u) /* ACLK Source Divider f(ACLK)/16 */ +#define DIVA__32 (0x0500u) /* ACLK Source Divider f(ACLK)/32 */ + +/* CSCTL4 Control Bits */ +#define LFXTOFF (0x0001u) /* High Frequency Oscillator 1 (XT1) disable */ +#define SMCLKOFF (0x0002u) /* SMCLK Off */ +#define VLOOFF (0x0008u) /* VLO Off */ +#define LFXTBYPASS (0x0010u) /* LFXT bypass mode : 0: internal 1:sourced from external pin */ +#define LFXTAGCOFF (0x0020u) /* LFXT automatic gain control off */ +#define LFXTDRIVE0 (0x0040u) /* LFXT Drive Level mode Bit 0 */ +#define LFXTDRIVE1 (0x0080u) /* LFXT Drive Level mode Bit 1 */ +#define HFXTOFF (0x0100u) /* High Frequency Oscillator disable */ +#define HFFREQ0 (0x0400u) /* HFXT frequency selection Bit 1 */ +#define HFFREQ1 (0x0800u) /* HFXT frequency selection Bit 0 */ +#define HFXTBYPASS (0x1000u) /* HFXT bypass mode : 0: internal 1:sourced from external pin */ +#define HFXTDRIVE0 (0x4000u) /* HFXT Drive Level mode Bit 0 */ +#define HFXTDRIVE1 (0x8000u) /* HFXT Drive Level mode Bit 1 */ + +/* CSCTL4 Control Bits */ +#define LFXTOFF_L (0x0001u) /* High Frequency Oscillator 1 (XT1) disable */ +#define SMCLKOFF_L (0x0002u) /* SMCLK Off */ +#define VLOOFF_L (0x0008u) /* VLO Off */ +#define LFXTBYPASS_L (0x0010u) /* LFXT bypass mode : 0: internal 1:sourced from external pin */ +#define LFXTAGCOFF_L (0x0020u) /* LFXT automatic gain control off */ +#define LFXTDRIVE0_L (0x0040u) /* LFXT Drive Level mode Bit 0 */ +#define LFXTDRIVE1_L (0x0080u) /* LFXT Drive Level mode Bit 1 */ + +/* CSCTL4 Control Bits */ +#define HFXTOFF_H (0x0001u) /* High Frequency Oscillator disable */ +#define HFFREQ0_H (0x0004u) /* HFXT frequency selection Bit 1 */ +#define HFFREQ1_H (0x0008u) /* HFXT frequency selection Bit 0 */ +#define HFXTBYPASS_H (0x0010u) /* HFXT bypass mode : 0: internal 1:sourced from external pin */ +#define HFXTDRIVE0_H (0x0040u) /* HFXT Drive Level mode Bit 0 */ +#define HFXTDRIVE1_H (0x0080u) /* HFXT Drive Level mode Bit 1 */ + +#define LFXTDRIVE_0 (0x0000u) /* LFXT Drive Level mode: 0 */ +#define LFXTDRIVE_1 (0x0040u) /* LFXT Drive Level mode: 1 */ +#define LFXTDRIVE_2 (0x0080u) /* LFXT Drive Level mode: 2 */ +#define LFXTDRIVE_3 (0x00C0u) /* LFXT Drive Level mode: 3 */ + +#define HFFREQ_0 (0x0000u) /* HFXT frequency selection: 0 */ +#define HFFREQ_1 (0x0400u) /* HFXT frequency selection: 1 */ +#define HFFREQ_2 (0x0800u) /* HFXT frequency selection: 2 */ +#define HFFREQ_3 (0x0C00u) /* HFXT frequency selection: 3 */ + +#define HFXTDRIVE_0 (0x0000u) /* HFXT Drive Level mode: 0 */ +#define HFXTDRIVE_1 (0x4000u) /* HFXT Drive Level mode: 1 */ +#define HFXTDRIVE_2 (0x8000u) /* HFXT Drive Level mode: 2 */ +#define HFXTDRIVE_3 (0xC000u) /* HFXT Drive Level mode: 3 */ + +/* CSCTL5 Control Bits */ +#define LFXTOFFG (0x0001u) /* LFXT Low Frequency Oscillator Fault Flag */ +#define HFXTOFFG (0x0002u) /* HFXT High Frequency Oscillator Fault Flag */ +#define ENSTFCNT1 (0x0040u) /* Enable start counter for XT1 */ +#define ENSTFCNT2 (0x0080u) /* Enable start counter for XT2 */ + +/* CSCTL5 Control Bits */ +#define LFXTOFFG_L (0x0001u) /* LFXT Low Frequency Oscillator Fault Flag */ +#define HFXTOFFG_L (0x0002u) /* HFXT High Frequency Oscillator Fault Flag */ +#define ENSTFCNT1_L (0x0040u) /* Enable start counter for XT1 */ +#define ENSTFCNT2_L (0x0080u) /* Enable start counter for XT2 */ + +/* CSCTL6 Control Bits */ +#define ACLKREQEN (0x0001u) /* ACLK Clock Request Enable */ +#define MCLKREQEN (0x0002u) /* MCLK Clock Request Enable */ +#define SMCLKREQEN (0x0004u) /* SMCLK Clock Request Enable */ +#define MODCLKREQEN (0x0008u) /* MODOSC Clock Request Enable */ + +/* CSCTL6 Control Bits */ +#define ACLKREQEN_L (0x0001u) /* ACLK Clock Request Enable */ +#define MCLKREQEN_L (0x0002u) /* MCLK Clock Request Enable */ +#define SMCLKREQEN_L (0x0004u) /* SMCLK Clock Request Enable */ +#define MODCLKREQEN_L (0x0008u) /* MODOSC Clock Request Enable */ + +#endif +/************************************************************ +* DMA_X +************************************************************/ +#ifdef __MSP430_HAS_DMAX_3__ /* Definition to show that Module is available */ + +#define OFS_DMACTL0 (0x0000u) /* DMA Module Control 0 */ +#define OFS_DMACTL0_L OFS_DMACTL0 +#define OFS_DMACTL0_H OFS_DMACTL0+1 +#define OFS_DMACTL1 (0x0002u) /* DMA Module Control 1 */ +#define OFS_DMACTL1_L OFS_DMACTL1 +#define OFS_DMACTL1_H OFS_DMACTL1+1 +#define OFS_DMACTL2 (0x0004u) /* DMA Module Control 2 */ +#define OFS_DMACTL2_L OFS_DMACTL2 +#define OFS_DMACTL2_H OFS_DMACTL2+1 +#define OFS_DMACTL3 (0x0006u) /* DMA Module Control 3 */ +#define OFS_DMACTL3_L OFS_DMACTL3 +#define OFS_DMACTL3_H OFS_DMACTL3+1 +#define OFS_DMACTL4 (0x0008u) /* DMA Module Control 4 */ +#define OFS_DMACTL4_L OFS_DMACTL4 +#define OFS_DMACTL4_H OFS_DMACTL4+1 +#define OFS_DMAIV (0x000Eu) /* DMA Interrupt Vector Word */ +#define OFS_DMAIV_L OFS_DMAIV +#define OFS_DMAIV_H OFS_DMAIV+1 + +#define OFS_DMA0CTL (0x0010u) /* DMA Channel 0 Control */ +#define OFS_DMA0CTL_L OFS_DMA0CTL +#define OFS_DMA0CTL_H OFS_DMA0CTL+1 +#define OFS_DMA0SA (0x0012u) /* DMA Channel 0 Source Address */ +#define OFS_DMA0DA (0x0016u) /* DMA Channel 0 Destination Address */ +#define OFS_DMA0SZ (0x001Au) /* DMA Channel 0 Transfer Size */ + +#define OFS_DMA1CTL (0x0020u) /* DMA Channel 1 Control */ +#define OFS_DMA1CTL_L OFS_DMA1CTL +#define OFS_DMA1CTL_H OFS_DMA1CTL+1 +#define OFS_DMA1SA (0x0022u) /* DMA Channel 1 Source Address */ +#define OFS_DMA1DA (0x0026u) /* DMA Channel 1 Destination Address */ +#define OFS_DMA1SZ (0x002Au) /* DMA Channel 1 Transfer Size */ + +#define OFS_DMA2CTL (0x0030u) /* DMA Channel 2 Control */ +#define OFS_DMA2CTL_L OFS_DMA2CTL +#define OFS_DMA2CTL_H OFS_DMA2CTL+1 +#define OFS_DMA2SA (0x0032u) /* DMA Channel 2 Source Address */ +#define OFS_DMA2DA (0x0036u) /* DMA Channel 2 Destination Address */ +#define OFS_DMA2SZ (0x003Au) /* DMA Channel 2 Transfer Size */ + +/* DMACTL0 Control Bits */ +#define DMA0TSEL0 (0x0001u) /* DMA channel 0 transfer select bit 0 */ +#define DMA0TSEL1 (0x0002u) /* DMA channel 0 transfer select bit 1 */ +#define DMA0TSEL2 (0x0004u) /* DMA channel 0 transfer select bit 2 */ +#define DMA0TSEL3 (0x0008u) /* DMA channel 0 transfer select bit 3 */ +#define DMA0TSEL4 (0x0010u) /* DMA channel 0 transfer select bit 4 */ +#define DMA1TSEL0 (0x0100u) /* DMA channel 1 transfer select bit 0 */ +#define DMA1TSEL1 (0x0200u) /* DMA channel 1 transfer select bit 1 */ +#define DMA1TSEL2 (0x0400u) /* DMA channel 1 transfer select bit 2 */ +#define DMA1TSEL3 (0x0800u) /* DMA channel 1 transfer select bit 3 */ +#define DMA1TSEL4 (0x1000u) /* DMA channel 1 transfer select bit 4 */ + +/* DMACTL0 Control Bits */ +#define DMA0TSEL0_L (0x0001u) /* DMA channel 0 transfer select bit 0 */ +#define DMA0TSEL1_L (0x0002u) /* DMA channel 0 transfer select bit 1 */ +#define DMA0TSEL2_L (0x0004u) /* DMA channel 0 transfer select bit 2 */ +#define DMA0TSEL3_L (0x0008u) /* DMA channel 0 transfer select bit 3 */ +#define DMA0TSEL4_L (0x0010u) /* DMA channel 0 transfer select bit 4 */ + +/* DMACTL0 Control Bits */ +#define DMA1TSEL0_H (0x0001u) /* DMA channel 1 transfer select bit 0 */ +#define DMA1TSEL1_H (0x0002u) /* DMA channel 1 transfer select bit 1 */ +#define DMA1TSEL2_H (0x0004u) /* DMA channel 1 transfer select bit 2 */ +#define DMA1TSEL3_H (0x0008u) /* DMA channel 1 transfer select bit 3 */ +#define DMA1TSEL4_H (0x0010u) /* DMA channel 1 transfer select bit 4 */ + +/* DMACTL01 Control Bits */ +#define DMA2TSEL0 (0x0001u) /* DMA channel 2 transfer select bit 0 */ +#define DMA2TSEL1 (0x0002u) /* DMA channel 2 transfer select bit 1 */ +#define DMA2TSEL2 (0x0004u) /* DMA channel 2 transfer select bit 2 */ +#define DMA2TSEL3 (0x0008u) /* DMA channel 2 transfer select bit 3 */ +#define DMA2TSEL4 (0x0010u) /* DMA channel 2 transfer select bit 4 */ + +/* DMACTL01 Control Bits */ +#define DMA2TSEL0_L (0x0001u) /* DMA channel 2 transfer select bit 0 */ +#define DMA2TSEL1_L (0x0002u) /* DMA channel 2 transfer select bit 1 */ +#define DMA2TSEL2_L (0x0004u) /* DMA channel 2 transfer select bit 2 */ +#define DMA2TSEL3_L (0x0008u) /* DMA channel 2 transfer select bit 3 */ +#define DMA2TSEL4_L (0x0010u) /* DMA channel 2 transfer select bit 4 */ + +/* DMACTL4 Control Bits */ +#define ENNMI (0x0001u) /* Enable NMI interruption of DMA */ +#define ROUNDROBIN (0x0002u) /* Round-Robin DMA channel priorities */ +#define DMARMWDIS (0x0004u) /* Inhibited DMA transfers during read-modify-write CPU operations */ + +/* DMACTL4 Control Bits */ +#define ENNMI_L (0x0001u) /* Enable NMI interruption of DMA */ +#define ROUNDROBIN_L (0x0002u) /* Round-Robin DMA channel priorities */ +#define DMARMWDIS_L (0x0004u) /* Inhibited DMA transfers during read-modify-write CPU operations */ + +/* DMAxCTL Control Bits */ +#define DMAREQ (0x0001u) /* Initiate DMA transfer with DMATSEL */ +#define DMAABORT (0x0002u) /* DMA transfer aborted by NMI */ +#define DMAIE (0x0004u) /* DMA interrupt enable */ +#define DMAIFG (0x0008u) /* DMA interrupt flag */ +#define DMAEN (0x0010u) /* DMA enable */ +#define DMALEVEL (0x0020u) /* DMA level sensitive trigger select */ +#define DMASRCBYTE (0x0040u) /* DMA source byte */ +#define DMADSTBYTE (0x0080u) /* DMA destination byte */ +#define DMASRCINCR0 (0x0100u) /* DMA source increment bit 0 */ +#define DMASRCINCR1 (0x0200u) /* DMA source increment bit 1 */ +#define DMADSTINCR0 (0x0400u) /* DMA destination increment bit 0 */ +#define DMADSTINCR1 (0x0800u) /* DMA destination increment bit 1 */ +#define DMADT0 (0x1000u) /* DMA transfer mode bit 0 */ +#define DMADT1 (0x2000u) /* DMA transfer mode bit 1 */ +#define DMADT2 (0x4000u) /* DMA transfer mode bit 2 */ + +/* DMAxCTL Control Bits */ +#define DMAREQ_L (0x0001u) /* Initiate DMA transfer with DMATSEL */ +#define DMAABORT_L (0x0002u) /* DMA transfer aborted by NMI */ +#define DMAIE_L (0x0004u) /* DMA interrupt enable */ +#define DMAIFG_L (0x0008u) /* DMA interrupt flag */ +#define DMAEN_L (0x0010u) /* DMA enable */ +#define DMALEVEL_L (0x0020u) /* DMA level sensitive trigger select */ +#define DMASRCBYTE_L (0x0040u) /* DMA source byte */ +#define DMADSTBYTE_L (0x0080u) /* DMA destination byte */ + +/* DMAxCTL Control Bits */ +#define DMASRCINCR0_H (0x0001u) /* DMA source increment bit 0 */ +#define DMASRCINCR1_H (0x0002u) /* DMA source increment bit 1 */ +#define DMADSTINCR0_H (0x0004u) /* DMA destination increment bit 0 */ +#define DMADSTINCR1_H (0x0008u) /* DMA destination increment bit 1 */ +#define DMADT0_H (0x0010u) /* DMA transfer mode bit 0 */ +#define DMADT1_H (0x0020u) /* DMA transfer mode bit 1 */ +#define DMADT2_H (0x0040u) /* DMA transfer mode bit 2 */ + +#define DMASWDW (0*0x0040u) /* DMA transfer: source word to destination word */ +#define DMASBDW (1*0x0040u) /* DMA transfer: source byte to destination word */ +#define DMASWDB (2*0x0040u) /* DMA transfer: source word to destination byte */ +#define DMASBDB (3*0x0040u) /* DMA transfer: source byte to destination byte */ + +#define DMASRCINCR_0 (0*0x0100u) /* DMA source increment 0: source address unchanged */ +#define DMASRCINCR_1 (1*0x0100u) /* DMA source increment 1: source address unchanged */ +#define DMASRCINCR_2 (2*0x0100u) /* DMA source increment 2: source address decremented */ +#define DMASRCINCR_3 (3*0x0100u) /* DMA source increment 3: source address incremented */ + +#define DMADSTINCR_0 (0*0x0400u) /* DMA destination increment 0: destination address unchanged */ +#define DMADSTINCR_1 (1*0x0400u) /* DMA destination increment 1: destination address unchanged */ +#define DMADSTINCR_2 (2*0x0400u) /* DMA destination increment 2: destination address decremented */ +#define DMADSTINCR_3 (3*0x0400u) /* DMA destination increment 3: destination address incremented */ + +#define DMADT_0 (0*0x1000u) /* DMA transfer mode 0: Single transfer */ +#define DMADT_1 (1*0x1000u) /* DMA transfer mode 1: Block transfer */ +#define DMADT_2 (2*0x1000u) /* DMA transfer mode 2: Burst-Block transfer */ +#define DMADT_3 (3*0x1000u) /* DMA transfer mode 3: Burst-Block transfer */ +#define DMADT_4 (4*0x1000u) /* DMA transfer mode 4: Repeated Single transfer */ +#define DMADT_5 (5*0x1000u) /* DMA transfer mode 5: Repeated Block transfer */ +#define DMADT_6 (6*0x1000u) /* DMA transfer mode 6: Repeated Burst-Block transfer */ +#define DMADT_7 (7*0x1000u) /* DMA transfer mode 7: Repeated Burst-Block transfer */ + +/* DMAIV Definitions */ +#define DMAIV_NONE (0x0000u) /* No Interrupt pending */ +#define DMAIV_DMA0IFG (0x0002u) /* DMA0IFG*/ +#define DMAIV_DMA1IFG (0x0004u) /* DMA1IFG*/ +#define DMAIV_DMA2IFG (0x0006u) /* DMA2IFG*/ + +#endif +/************************************************************ +* EXTENDED SCAN INTERFACE +************************************************************/ +#ifdef __MSP430_HAS_ESI__ /* Definition to show that Module is available */ + +#define OFS_ESIDEBUG1 (0x0000u) /* ESI debug register 1 */ +#define OFS_ESIDEBUG1_L OFS_ESIDEBUG1 +#define OFS_ESIDEBUG1_H OFS_ESIDEBUG1+1 +#define OFS_ESIDEBUG2 (0x0002u) /* ESI debug register 2 */ +#define OFS_ESIDEBUG2_L OFS_ESIDEBUG2 +#define OFS_ESIDEBUG2_H OFS_ESIDEBUG2+1 +#define OFS_ESIDEBUG3 (0x0004u) /* ESI debug register 3 */ +#define OFS_ESIDEBUG3_L OFS_ESIDEBUG3 +#define OFS_ESIDEBUG3_H OFS_ESIDEBUG3+1 +#define OFS_ESIDEBUG4 (0x0006u) /* ESI debug register 4 */ +#define OFS_ESIDEBUG4_L OFS_ESIDEBUG4 +#define OFS_ESIDEBUG4_H OFS_ESIDEBUG4+1 +#define OFS_ESIDEBUG5 (0x0008u) /* ESI debug register 5 */ +#define OFS_ESIDEBUG5_L OFS_ESIDEBUG5 +#define OFS_ESIDEBUG5_H OFS_ESIDEBUG5+1 +#define OFS_ESICNT0 (0x0010u) /* ESI PSM counter 0 */ +#define OFS_ESICNT0_L OFS_ESICNT0 +#define OFS_ESICNT0_H OFS_ESICNT0+1 +#define OFS_ESICNT1 (0x0012u) /* ESI PSM counter 1 */ +#define OFS_ESICNT1_L OFS_ESICNT1 +#define OFS_ESICNT1_H OFS_ESICNT1+1 +#define OFS_ESICNT2 (0x0014u) /* ESI PSM counter 2 */ +#define OFS_ESICNT2_L OFS_ESICNT2 +#define OFS_ESICNT2_H OFS_ESICNT2+1 +#define OFS_ESICNT3 (0x0016u) /* ESI oscillator counter register */ +#define OFS_ESICNT3_L OFS_ESICNT3 +#define OFS_ESICNT3_H OFS_ESICNT3+1 +#define OFS_ESIIV (0x001Au) /* ESI interrupt vector */ +#define OFS_ESIIV_L OFS_ESIIV +#define OFS_ESIIV_H OFS_ESIIV+1 +#define OFS_ESIINT1 (0x001Cu) /* ESI interrupt register 1 */ +#define OFS_ESIINT1_L OFS_ESIINT1 +#define OFS_ESIINT1_H OFS_ESIINT1+1 +#define OFS_ESIINT2 (0x001Eu) /* ESI interrupt register 2 */ +#define OFS_ESIINT2_L OFS_ESIINT2 +#define OFS_ESIINT2_H OFS_ESIINT2+1 +#define OFS_ESIAFE (0x0020u) /* ESI AFE control register */ +#define OFS_ESIAFE_L OFS_ESIAFE +#define OFS_ESIAFE_H OFS_ESIAFE+1 +#define OFS_ESIPPU (0x0022u) /* ESI PPU control register */ +#define OFS_ESIPPU_L OFS_ESIPPU +#define OFS_ESIPPU_H OFS_ESIPPU+1 +#define OFS_ESITSM (0x0024u) /* ESI TSM control register */ +#define OFS_ESITSM_L OFS_ESITSM +#define OFS_ESITSM_H OFS_ESITSM+1 +#define OFS_ESIPSM (0x0026u) /* ESI PSM control register */ +#define OFS_ESIPSM_L OFS_ESIPSM +#define OFS_ESIPSM_H OFS_ESIPSM+1 +#define OFS_ESIOSC (0x0028u) /* ESI oscillator control register*/ +#define OFS_ESIOSC_L OFS_ESIOSC +#define OFS_ESIOSC_H OFS_ESIOSC+1 +#define OFS_ESICTL (0x002Au) /* ESI control register */ +#define OFS_ESICTL_L OFS_ESICTL +#define OFS_ESICTL_H OFS_ESICTL+1 +#define OFS_ESITHR1 (0x002Cu) /* ESI PSM Counter Threshold 1 register */ +#define OFS_ESITHR1_L OFS_ESITHR1 +#define OFS_ESITHR1_H OFS_ESITHR1+1 +#define OFS_ESITHR2 (0x002Eu) /* ESI PSM Counter Threshold 2 register */ +#define OFS_ESITHR2_L OFS_ESITHR2 +#define OFS_ESITHR2_H OFS_ESITHR2+1 +#define OFS_ESIDAC1R0 (0x0040u) /* ESI DAC1 register 0 */ +#define OFS_ESIDAC1R0_L OFS_ESIDAC1R0 +#define OFS_ESIDAC1R0_H OFS_ESIDAC1R0+1 +#define OFS_ESIDAC1R1 (0x0042u) /* ESI DAC1 register 1 */ +#define OFS_ESIDAC1R1_L OFS_ESIDAC1R1 +#define OFS_ESIDAC1R1_H OFS_ESIDAC1R1+1 +#define OFS_ESIDAC1R2 (0x0044u) /* ESI DAC1 register 2 */ +#define OFS_ESIDAC1R2_L OFS_ESIDAC1R2 +#define OFS_ESIDAC1R2_H OFS_ESIDAC1R2+1 +#define OFS_ESIDAC1R3 (0x0046u) /* ESI DAC1 register 3 */ +#define OFS_ESIDAC1R3_L OFS_ESIDAC1R3 +#define OFS_ESIDAC1R3_H OFS_ESIDAC1R3+1 +#define OFS_ESIDAC1R4 (0x0048u) /* ESI DAC1 register 4 */ +#define OFS_ESIDAC1R4_L OFS_ESIDAC1R4 +#define OFS_ESIDAC1R4_H OFS_ESIDAC1R4+1 +#define OFS_ESIDAC1R5 (0x004Au) /* ESI DAC1 register 5 */ +#define OFS_ESIDAC1R5_L OFS_ESIDAC1R5 +#define OFS_ESIDAC1R5_H OFS_ESIDAC1R5+1 +#define OFS_ESIDAC1R6 (0x004Cu) /* ESI DAC1 register 6 */ +#define OFS_ESIDAC1R6_L OFS_ESIDAC1R6 +#define OFS_ESIDAC1R6_H OFS_ESIDAC1R6+1 +#define OFS_ESIDAC1R7 (0x004Eu) /* ESI DAC1 register 7 */ +#define OFS_ESIDAC1R7_L OFS_ESIDAC1R7 +#define OFS_ESIDAC1R7_H OFS_ESIDAC1R7+1 +#define OFS_ESIDAC2R0 (0x0050u) /* ESI DAC2 register 0 */ +#define OFS_ESIDAC2R0_L OFS_ESIDAC2R0 +#define OFS_ESIDAC2R0_H OFS_ESIDAC2R0+1 +#define OFS_ESIDAC2R1 (0x0052u) /* ESI DAC2 register 1 */ +#define OFS_ESIDAC2R1_L OFS_ESIDAC2R1 +#define OFS_ESIDAC2R1_H OFS_ESIDAC2R1+1 +#define OFS_ESIDAC2R2 (0x0054u) /* ESI DAC2 register 2 */ +#define OFS_ESIDAC2R2_L OFS_ESIDAC2R2 +#define OFS_ESIDAC2R2_H OFS_ESIDAC2R2+1 +#define OFS_ESIDAC2R3 (0x0056u) /* ESI DAC2 register 3 */ +#define OFS_ESIDAC2R3_L OFS_ESIDAC2R3 +#define OFS_ESIDAC2R3_H OFS_ESIDAC2R3+1 +#define OFS_ESIDAC2R4 (0x0058u) /* ESI DAC2 register 4 */ +#define OFS_ESIDAC2R4_L OFS_ESIDAC2R4 +#define OFS_ESIDAC2R4_H OFS_ESIDAC2R4+1 +#define OFS_ESIDAC2R5 (0x005Au) /* ESI DAC2 register 5 */ +#define OFS_ESIDAC2R5_L OFS_ESIDAC2R5 +#define OFS_ESIDAC2R5_H OFS_ESIDAC2R5+1 +#define OFS_ESIDAC2R6 (0x005Cu) /* ESI DAC2 register 6 */ +#define OFS_ESIDAC2R6_L OFS_ESIDAC2R6 +#define OFS_ESIDAC2R6_H OFS_ESIDAC2R6+1 +#define OFS_ESIDAC2R7 (0x005Eu) /* ESI DAC2 register 7 */ +#define OFS_ESIDAC2R7_L OFS_ESIDAC2R7 +#define OFS_ESIDAC2R7_H OFS_ESIDAC2R7+1 +#define OFS_ESITSM0 (0x0060u) /* ESI TSM 0 */ +#define OFS_ESITSM0_L OFS_ESITSM0 +#define OFS_ESITSM0_H OFS_ESITSM0+1 +#define OFS_ESITSM1 (0x0062u) /* ESI TSM 1 */ +#define OFS_ESITSM1_L OFS_ESITSM1 +#define OFS_ESITSM1_H OFS_ESITSM1+1 +#define OFS_ESITSM2 (0x0064u) /* ESI TSM 2 */ +#define OFS_ESITSM2_L OFS_ESITSM2 +#define OFS_ESITSM2_H OFS_ESITSM2+1 +#define OFS_ESITSM3 (0x0066u) /* ESI TSM 3 */ +#define OFS_ESITSM3_L OFS_ESITSM3 +#define OFS_ESITSM3_H OFS_ESITSM3+1 +#define OFS_ESITSM4 (0x0068u) /* ESI TSM 4 */ +#define OFS_ESITSM4_L OFS_ESITSM4 +#define OFS_ESITSM4_H OFS_ESITSM4+1 +#define OFS_ESITSM5 (0x006Au) /* ESI TSM 5 */ +#define OFS_ESITSM5_L OFS_ESITSM5 +#define OFS_ESITSM5_H OFS_ESITSM5+1 +#define OFS_ESITSM6 (0x006Cu) /* ESI TSM 6 */ +#define OFS_ESITSM6_L OFS_ESITSM6 +#define OFS_ESITSM6_H OFS_ESITSM6+1 +#define OFS_ESITSM7 (0x006Eu) /* ESI TSM 7 */ +#define OFS_ESITSM7_L OFS_ESITSM7 +#define OFS_ESITSM7_H OFS_ESITSM7+1 +#define OFS_ESITSM8 (0x0070u) /* ESI TSM 8 */ +#define OFS_ESITSM8_L OFS_ESITSM8 +#define OFS_ESITSM8_H OFS_ESITSM8+1 +#define OFS_ESITSM9 (0x0072u) /* ESI TSM 9 */ +#define OFS_ESITSM9_L OFS_ESITSM9 +#define OFS_ESITSM9_H OFS_ESITSM9+1 +#define OFS_ESITSM10 (0x0074u) /* ESI TSM 10 */ +#define OFS_ESITSM10_L OFS_ESITSM10 +#define OFS_ESITSM10_H OFS_ESITSM10+1 +#define OFS_ESITSM11 (0x0076u) /* ESI TSM 11 */ +#define OFS_ESITSM11_L OFS_ESITSM11 +#define OFS_ESITSM11_H OFS_ESITSM11+1 +#define OFS_ESITSM12 (0x0078u) /* ESI TSM 12 */ +#define OFS_ESITSM12_L OFS_ESITSM12 +#define OFS_ESITSM12_H OFS_ESITSM12+1 +#define OFS_ESITSM13 (0x007Au) /* ESI TSM 13 */ +#define OFS_ESITSM13_L OFS_ESITSM13 +#define OFS_ESITSM13_H OFS_ESITSM13+1 +#define OFS_ESITSM14 (0x007Cu) /* ESI TSM 14 */ +#define OFS_ESITSM14_L OFS_ESITSM14 +#define OFS_ESITSM14_H OFS_ESITSM14+1 +#define OFS_ESITSM15 (0x007Eu) /* ESI TSM 15 */ +#define OFS_ESITSM15_L OFS_ESITSM15 +#define OFS_ESITSM15_H OFS_ESITSM15+1 +#define OFS_ESITSM16 (0x0080u) /* ESI TSM 16 */ +#define OFS_ESITSM16_L OFS_ESITSM16 +#define OFS_ESITSM16_H OFS_ESITSM16+1 +#define OFS_ESITSM17 (0x0082u) /* ESI TSM 17 */ +#define OFS_ESITSM17_L OFS_ESITSM17 +#define OFS_ESITSM17_H OFS_ESITSM17+1 +#define OFS_ESITSM18 (0x0084u) /* ESI TSM 18 */ +#define OFS_ESITSM18_L OFS_ESITSM18 +#define OFS_ESITSM18_H OFS_ESITSM18+1 +#define OFS_ESITSM19 (0x0086u) /* ESI TSM 19 */ +#define OFS_ESITSM19_L OFS_ESITSM19 +#define OFS_ESITSM19_H OFS_ESITSM19+1 +#define OFS_ESITSM20 (0x0088u) /* ESI TSM 20 */ +#define OFS_ESITSM20_L OFS_ESITSM20 +#define OFS_ESITSM20_H OFS_ESITSM20+1 +#define OFS_ESITSM21 (0x008Au) /* ESI TSM 21 */ +#define OFS_ESITSM21_L OFS_ESITSM21 +#define OFS_ESITSM21_H OFS_ESITSM21+1 +#define OFS_ESITSM22 (0x008Cu) /* ESI TSM 22 */ +#define OFS_ESITSM22_L OFS_ESITSM22 +#define OFS_ESITSM22_H OFS_ESITSM22+1 +#define OFS_ESITSM23 (0x008Eu) /* ESI TSM 23 */ +#define OFS_ESITSM23_L OFS_ESITSM23 +#define OFS_ESITSM23_H OFS_ESITSM23+1 +#define OFS_ESITSM24 (0x0090u) /* ESI TSM 24 */ +#define OFS_ESITSM24_L OFS_ESITSM24 +#define OFS_ESITSM24_H OFS_ESITSM24+1 +#define OFS_ESITSM25 (0x0092u) /* ESI TSM 25 */ +#define OFS_ESITSM25_L OFS_ESITSM25 +#define OFS_ESITSM25_H OFS_ESITSM25+1 +#define OFS_ESITSM26 (0x0094u) /* ESI TSM 26 */ +#define OFS_ESITSM26_L OFS_ESITSM26 +#define OFS_ESITSM26_H OFS_ESITSM26+1 +#define OFS_ESITSM27 (0x0096u) /* ESI TSM 27 */ +#define OFS_ESITSM27_L OFS_ESITSM27 +#define OFS_ESITSM27_H OFS_ESITSM27+1 +#define OFS_ESITSM28 (0x0098u) /* ESI TSM 28 */ +#define OFS_ESITSM28_L OFS_ESITSM28 +#define OFS_ESITSM28_H OFS_ESITSM28+1 +#define OFS_ESITSM29 (0x009Au) /* ESI TSM 29 */ +#define OFS_ESITSM29_L OFS_ESITSM29 +#define OFS_ESITSM29_H OFS_ESITSM29+1 +#define OFS_ESITSM30 (0x009Cu) /* ESI TSM 30 */ +#define OFS_ESITSM30_L OFS_ESITSM30 +#define OFS_ESITSM30_H OFS_ESITSM30+1 +#define OFS_ESITSM31 (0x009Eu) /* ESI TSM 31 */ +#define OFS_ESITSM31_L OFS_ESITSM31 +#define OFS_ESITSM31_H OFS_ESITSM31+1 + +/* ESIIV Control Bits */ + +#define ESIIV_NONE (0x0000u) /* No ESI Interrupt Pending */ +#define ESIIV_ESIIFG1 (0x0002u) /* rising edge of the ESISTOP(tsm) */ +#define ESIIV_ESIIFG0 (0x0004u) /* ESIOUT0 to ESIOUT3 conditions selected by ESIIFGSETx bits */ +#define ESIIV_ESIIFG8 (0x0006u) /* ESIOUT4 to ESIOUT7 conditions selected by ESIIFGSET2x bits */ +#define ESIIV_ESIIFG3 (0x0008u) /* ESICNT1 counter conditions selected with the ESITHR1 and ESITHR2 registers */ +#define ESIIV_ESIIFG6 (0x000Au) /* PSM transitions to a state with a Q7 bit */ +#define ESIIV_ESIIFG5 (0x000Cu) /* PSM transitions to a state with a Q6 bit */ +#define ESIIV_ESIIFG4 (0x000Eu) /* ESICNT2 counter conditions selected with the ESIIS2x bits */ +#define ESIIV_ESIIFG7 (0x0010u) /* ESICNT0 counter conditions selected with the ESIIS0x bits */ +#define ESIIV_ESIIFG2 (0x0012u) /* start of a TSM sequence */ + +/* ESIINT1 Control Bits */ +#define ESIIFGSET22 (0x8000u) /* ESIIFG8 interrupt flag source */ +#define ESIIFGSET21 (0x4000u) /* ESIIFG8 interrupt flag source */ +#define ESIIFGSET20 (0x2000u) /* ESIIFG8 interrupt flag source */ +#define ESIIFGSET12 (0x1000u) /* ESIIFG0 interrupt flag source */ +#define ESIIFGSET11 (0x0800u) /* ESIIFG0 interrupt flag source */ +#define ESIIFGSET10 (0x0400u) /* ESIIFG0 interrupt flag source */ +#define ESIIE8 (0x0100u) /* Interrupt enable */ +#define ESIIE7 (0x0080u) /* Interrupt enable */ +#define ESIIE6 (0x0040u) /* Interrupt enable */ +#define ESIIE5 (0x0020u) /* Interrupt enable */ +#define ESIIE4 (0x0010u) /* Interrupt enable */ +#define ESIIE3 (0x0008u) /* Interrupt enable */ +#define ESIIE2 (0x0004u) /* Interrupt enable */ +#define ESIIE1 (0x0002u) /* Interrupt enable */ +#define ESIIE0 (0x0001u) /* Interrupt enable */ + +/* ESIINT1 Control Bits */ +#define ESIIE7_L (0x0080u) /* Interrupt enable */ +#define ESIIE6_L (0x0040u) /* Interrupt enable */ +#define ESIIE5_L (0x0020u) /* Interrupt enable */ +#define ESIIE4_L (0x0010u) /* Interrupt enable */ +#define ESIIE3_L (0x0008u) /* Interrupt enable */ +#define ESIIE2_L (0x0004u) /* Interrupt enable */ +#define ESIIE1_L (0x0002u) /* Interrupt enable */ +#define ESIIE0_L (0x0001u) /* Interrupt enable */ + +/* ESIINT1 Control Bits */ +#define ESIIFGSET22_H (0x0080u) /* ESIIFG8 interrupt flag source */ +#define ESIIFGSET21_H (0x0040u) /* ESIIFG8 interrupt flag source */ +#define ESIIFGSET20_H (0x0020u) /* ESIIFG8 interrupt flag source */ +#define ESIIFGSET12_H (0x0010u) /* ESIIFG0 interrupt flag source */ +#define ESIIFGSET11_H (0x0008u) /* ESIIFG0 interrupt flag source */ +#define ESIIFGSET10_H (0x0004u) /* ESIIFG0 interrupt flag source */ +#define ESIIE8_H (0x0001u) /* Interrupt enable */ + +#define ESIIFGSET2_0 (0x0000u) /* ESIIFG8 is set when ESIOUT4 is set */ +#define ESIIFGSET2_1 (0x2000u) /* ESIIFG8 is set when ESIOUT4 is reset */ +#define ESIIFGSET2_2 (0x4000u) /* ESIIFG8 is set when ESIOUT5 is set */ +#define ESIIFGSET2_3 (0x6000u) /* ESIIFG8 is set when ESIOUT5 is reset */ +#define ESIIFGSET2_4 (0x8000u) /* ESIIFG8 is set when ESIOUT6 is set */ +#define ESIIFGSET2_5 (0xA000u) /* ESIIFG8 is set when ESIOUT6 is reset */ +#define ESIIFGSET2_6 (0xC000u) /* ESIIFG8 is set when ESIOUT7 is set */ +#define ESIIFGSET2_7 (0xE000u) /* ESIIFG8 is set when ESIOUT7 is reset */ +#define ESIIFGSET1_0 (0x0000u) /* ESIIFG0 is set when ESIOUT0 is set */ +#define ESIIFGSET1_1 (0x0400u) /* ESIIFG0 is set when ESIOUT0 is reset */ +#define ESIIFGSET1_2 (0x0800u) /* ESIIFG0 is set when ESIOUT1 is set */ +#define ESIIFGSET1_3 (0x0C00u) /* ESIIFG0 is set when ESIOUT1 is reset */ +#define ESIIFGSET1_4 (0x1000u) /* ESIIFG0 is set when ESIOUT2 is set */ +#define ESIIFGSET1_5 (0x1400u) /* ESIIFG0 is set when ESIOUT2 is reset */ +#define ESIIFGSET1_6 (0x1800u) /* ESIIFG0 is set when ESIOUT3 is set */ +#define ESIIFGSET1_7 (0x1C00u) /* ESIIFG0 is set when ESIOUT3 is reset */ + +/* ESIINT2 Control Bits */ +#define ESIIS21 (0x4000u) /* SIFIFG4 interrupt flag source */ +#define ESIIS20 (0x2000u) /* SIFIFG4 interrupt flag source */ +#define ESIIS01 (0x0800u) /* SIFIFG7 interrupt flag source */ +#define ESIIS00 (0x0400u) /* SIFIFG7 interrupt flag source */ +#define ESIIFG8 (0x0100u) /* ESIIFG8 interrupt pending */ +#define ESIIFG7 (0x0080u) /* ESIIFG7 interrupt pending */ +#define ESIIFG6 (0x0040u) /* ESIIFG6 interrupt pending */ +#define ESIIFG5 (0x0020u) /* ESIIFG5 interrupt pending */ +#define ESIIFG4 (0x0010u) /* ESIIFG4 interrupt pending */ +#define ESIIFG3 (0x0008u) /* ESIIFG3 interrupt pending */ +#define ESIIFG2 (0x0004u) /* ESIIFG2 interrupt pending */ +#define ESIIFG1 (0x0002u) /* ESIIFG1 interrupt pending */ +#define ESIIFG0 (0x0001u) /* ESIIFG0 interrupt pending */ + +/* ESIINT2 Control Bits */ +#define ESIIFG7_L (0x0080u) /* ESIIFG7 interrupt pending */ +#define ESIIFG6_L (0x0040u) /* ESIIFG6 interrupt pending */ +#define ESIIFG5_L (0x0020u) /* ESIIFG5 interrupt pending */ +#define ESIIFG4_L (0x0010u) /* ESIIFG4 interrupt pending */ +#define ESIIFG3_L (0x0008u) /* ESIIFG3 interrupt pending */ +#define ESIIFG2_L (0x0004u) /* ESIIFG2 interrupt pending */ +#define ESIIFG1_L (0x0002u) /* ESIIFG1 interrupt pending */ +#define ESIIFG0_L (0x0001u) /* ESIIFG0 interrupt pending */ + +/* ESIINT2 Control Bits */ +#define ESIIS21_H (0x0040u) /* SIFIFG4 interrupt flag source */ +#define ESIIS20_H (0x0020u) /* SIFIFG4 interrupt flag source */ +#define ESIIS01_H (0x0008u) /* SIFIFG7 interrupt flag source */ +#define ESIIS00_H (0x0004u) /* SIFIFG7 interrupt flag source */ +#define ESIIFG8_H (0x0001u) /* ESIIFG8 interrupt pending */ + +#define ESIIS2_0 (0x0000u) /* SIFIFG4 interrupt flag source: SIFCNT2 */ +#define ESIIS2_1 (0x2000u) /* SIFIFG4 interrupt flag source: SIFCNT2 MOD 4 */ +#define ESIIS2_2 (0x4000u) /* SIFIFG4 interrupt flag source: SIFCNT2 MOD 256 */ +#define ESIIS2_3 (0x6000u) /* SIFIFG4 interrupt flag source: SIFCNT2 decrements from 01h to 00h */ +#define ESIIS0_0 (0x0000u) /* SIFIFG7 interrupt flag source: SIFCNT0 */ +#define ESIIS0_1 (0x0400u) /* SIFIFG7 interrupt flag source: SIFCNT0 MOD 4 */ +#define ESIIS0_2 (0x0800u) /* SIFIFG7 interrupt flag source: SIFCNT0 MOD 256 */ +#define ESIIS0_3 (0x0C00u) /* SIFIFG7 interrupt flag source: SIFCNT0 increments from FFFFh to 00h */ + +/* ESIAFE Control Bits */ +#define ESIDAC2EN (0x0800u) /* Enable ESIDAC(tsm) control for DAC in AFE2 */ +#define ESICA2EN (0x0400u) /* Enable ESICA(tsm) control for comparator in AFE2 */ +#define ESICA2INV (0x0200u) /* Invert AFE2's comparator output */ +#define ESICA1INV (0x0100u) /* Invert AFE1's comparator output */ +#define ESICA2X (0x0080u) /* AFE2's comparator input select */ +#define ESICA1X (0x0040u) /* AFE1's comparator input select */ +#define ESICISEL (0x0020u) /* Comparator input select for AFE1 only */ +#define ESICACI3 (0x0010u) /* Comparator input select for AFE1 only */ +#define ESIVSS (0x0008u) /* Sample-and-hold ESIVSS select */ +#define ESIVCC2 (0x0004u) /* Mid-voltage generator */ +#define ESISH (0x0002u) /* Sample-and-hold enable */ +#define ESITEN (0x0001u) /* Excitation enable */ + +/* ESIAFE Control Bits */ +#define ESICA2X_L (0x0080u) /* AFE2's comparator input select */ +#define ESICA1X_L (0x0040u) /* AFE1's comparator input select */ +#define ESICISEL_L (0x0020u) /* Comparator input select for AFE1 only */ +#define ESICACI3_L (0x0010u) /* Comparator input select for AFE1 only */ +#define ESIVSS_L (0x0008u) /* Sample-and-hold ESIVSS select */ +#define ESIVCC2_L (0x0004u) /* Mid-voltage generator */ +#define ESISH_L (0x0002u) /* Sample-and-hold enable */ +#define ESITEN_L (0x0001u) /* Excitation enable */ + +/* ESIAFE Control Bits */ +#define ESIDAC2EN_H (0x0008u) /* Enable ESIDAC(tsm) control for DAC in AFE2 */ +#define ESICA2EN_H (0x0004u) /* Enable ESICA(tsm) control for comparator in AFE2 */ +#define ESICA2INV_H (0x0002u) /* Invert AFE2's comparator output */ +#define ESICA1INV_H (0x0001u) /* Invert AFE1's comparator output */ + +/* ESIPPU Control Bits */ +#define ESITCHOUT1 (0x0200u) /* Latched AFE1 comparator output for test channel 1 */ +#define ESITCHOUT0 (0x0100u) /* Lachted AFE1 comparator output for test channel 0 */ +#define ESIOUT7 (0x0080u) /* Latched AFE2 comparator output when ESICH3 input is selected */ +#define ESIOUT6 (0x0040u) /* Latched AFE2 comparator output when ESICH2 input is selected */ +#define ESIOUT5 (0x0020u) /* Latched AFE2 comparator output when ESICH1 input is selected */ +#define ESIOUT4 (0x0010u) /* Latched AFE2 comparator output when ESICH0 input is selected */ +#define ESIOUT3 (0x0008u) /* Latched AFE1 comparator output when ESICH3 input is selected */ +#define ESIOUT2 (0x0004u) /* Latched AFE1 comparator output when ESICH2 input is selected */ +#define ESIOUT1 (0x0002u) /* Latched AFE1 comparator output when ESICH1 input is selected */ +#define ESIOUT0 (0x0001u) /* Latched AFE1 comparator output when ESICH0 input is selected */ + +/* ESIPPU Control Bits */ +#define ESIOUT7_L (0x0080u) /* Latched AFE2 comparator output when ESICH3 input is selected */ +#define ESIOUT6_L (0x0040u) /* Latched AFE2 comparator output when ESICH2 input is selected */ +#define ESIOUT5_L (0x0020u) /* Latched AFE2 comparator output when ESICH1 input is selected */ +#define ESIOUT4_L (0x0010u) /* Latched AFE2 comparator output when ESICH0 input is selected */ +#define ESIOUT3_L (0x0008u) /* Latched AFE1 comparator output when ESICH3 input is selected */ +#define ESIOUT2_L (0x0004u) /* Latched AFE1 comparator output when ESICH2 input is selected */ +#define ESIOUT1_L (0x0002u) /* Latched AFE1 comparator output when ESICH1 input is selected */ +#define ESIOUT0_L (0x0001u) /* Latched AFE1 comparator output when ESICH0 input is selected */ + +/* ESIPPU Control Bits */ +#define ESITCHOUT1_H (0x0002u) /* Latched AFE1 comparator output for test channel 1 */ +#define ESITCHOUT0_H (0x0001u) /* Lachted AFE1 comparator output for test channel 0 */ + +/* ESITSM Control Bits */ +#define ESICLKAZSEL (0x4000u) /* Functionality selection of ESITSMx bit5 */ +#define ESITSMTRG1 (0x2000u) /* TSM start trigger selection */ +#define ESITSMTRG0 (0x1000u) /* TSM start trigger selection */ +#define ESISTART (0x0800u) /* TSM software start trigger */ +#define ESITSMRP (0x0400u) /* TSM repeat modee */ +#define ESIDIV3B2 (0x0200u) /* TSM start trigger ACLK divider */ +#define ESIDIV3B1 (0x0100u) /* TSM start trigger ACLK divider */ +#define ESIDIV3B0 (0x0080u) /* TSM start trigger ACLK divider */ +#define ESIDIV3A2 (0x0040u) /* TSM start trigger ACLK divider */ +#define ESIDIV3A1 (0x0020u) /* TSM start trigger ACLK divider */ +#define ESIDIV3A0 (0x0010u) /* TSM start trigger ACLK divider */ +#define ESIDIV21 (0x0008u) /* ACLK divider */ +#define ESIDIV20 (0x0004u) /* ACLK divider */ +#define ESIDIV11 (0x0002u) /* TSM SMCLK divider */ +#define ESIDIV10 (0x0001u) /* TSM SMCLK divider */ + +/* ESITSM Control Bits */ +#define ESIDIV3B0_L (0x0080u) /* TSM start trigger ACLK divider */ +#define ESIDIV3A2_L (0x0040u) /* TSM start trigger ACLK divider */ +#define ESIDIV3A1_L (0x0020u) /* TSM start trigger ACLK divider */ +#define ESIDIV3A0_L (0x0010u) /* TSM start trigger ACLK divider */ +#define ESIDIV21_L (0x0008u) /* ACLK divider */ +#define ESIDIV20_L (0x0004u) /* ACLK divider */ +#define ESIDIV11_L (0x0002u) /* TSM SMCLK divider */ +#define ESIDIV10_L (0x0001u) /* TSM SMCLK divider */ + +/* ESITSM Control Bits */ +#define ESICLKAZSEL_H (0x0040u) /* Functionality selection of ESITSMx bit5 */ +#define ESITSMTRG1_H (0x0020u) /* TSM start trigger selection */ +#define ESITSMTRG0_H (0x0010u) /* TSM start trigger selection */ +#define ESISTART_H (0x0008u) /* TSM software start trigger */ +#define ESITSMRP_H (0x0004u) /* TSM repeat modee */ +#define ESIDIV3B2_H (0x0002u) /* TSM start trigger ACLK divider */ +#define ESIDIV3B1_H (0x0001u) /* TSM start trigger ACLK divider */ + +#define ESITSMTRG_0 (0x0000u) /* Halt mode */ +#define ESITSMTRG_1 (0x1000u) /* TSM start trigger ACLK divider */ +#define ESITSMTRG_2 (0x2000u) /* Software trigger for TSM */ +#define ESITSMTRG_3 (0x3000u) /* Either the ACLK divider or the ESISTART biT */ +#define ESIDIV3B_0 (0x0000u) /* TSM start trigger ACLK divider */ +#define ESIDIV3B_1 (0x0080u) /* TSM start trigger ACLK divider */ +#define ESIDIV3B_2 (0x0100u) /* TSM start trigger ACLK divider */ +#define ESIDIV3B_3 (0x0180u) /* TSM start trigger ACLK divider */ +#define ESIDIV3B_4 (0x0200u) /* TSM start trigger ACLK divider */ +#define ESIDIV3B_5 (0x0280u) /* TSM start trigger ACLK divider */ +#define ESIDIV3B_6 (0x0300u) /* TSM start trigger ACLK divider */ +#define ESIDIV3B_7 (0x0380u) /* TSM start trigger ACLK divider */ +#define ESIDIV3A_0 (0x0000u) /* TSM start trigger ACLK divider */ +#define ESIDIV3A_1 (0x0010u) /* TSM start trigger ACLK divider */ +#define ESIDIV3A_2 (0x0020u) /* TSM start trigger ACLK divider */ +#define ESIDIV3A_3 (0x0030u) /* TSM start trigger ACLK divider */ +#define ESIDIV3A_4 (0x0040u) /* TSM start trigger ACLK divider */ +#define ESIDIV3A_5 (0x0050u) /* TSM start trigger ACLK divider */ +#define ESIDIV3A_6 (0x0060u) /* TSM start trigger ACLK divider */ +#define ESIDIV3A_7 (0x0070u) /* TSM start trigger ACLK divider */ +#define ESIDIV2_0 (0x0000u) /* ACLK divider mode: 0 */ +#define ESIDIV2_1 (0x0004u) /* ACLK divider mode: 1 */ +#define ESIDIV2_2 (0x0008u) /* ACLK divider mode: 2 */ +#define ESIDIV2_3 (0x000Cu) /* ACLK divider mode: 3 */ +#define ESIDIV2__1 (0x0000u) /* ACLK divider = /1 */ +#define ESIDIV2__2 (0x0004u) /* ACLK divider = /2 */ +#define ESIDIV2__4 (0x0008u) /* ACLK divider = /4 */ +#define ESIDIV2__8 (0x000Cu) /* ACLK divider = /8 */ +#define ESIDIV1_0 (0x0000u) /* TSM SMCLK/ESIOSC divider mode: 0 */ +#define ESIDIV1_1 (0x0001u) /* TSM SMCLK/ESIOSC divider mode: 1 */ +#define ESIDIV1_2 (0x0002u) /* TSM SMCLK/ESIOSC divider mode: 2 */ +#define ESIDIV1_3 (0x0003u) /* TSM SMCLK/ESIOSC divider mode: 3 */ +#define ESIDIV1__1 (0x0000u) /* TSM SMCLK/ESIOSC divider = /1 */ +#define ESIDIV1__2 (0x0001u) /* TSM SMCLK/ESIOSC divider = /2 */ +#define ESIDIV1__4 (0x0002u) /* TSM SMCLK/ESIOSC divider = /4 */ +#define ESIDIV1__8 (0x0003u) /* TSM SMCLK/ESIOSC divider = /8 */ + +/* ESIPSM Control Bits */ +#define ESICNT2RST (0x8000u) /* ESI Counter 2 reset */ +#define ESICNT1RST (0x4000u) /* ESI Counter 1 reset */ +#define ESICNT0RST (0x2000u) /* ESI Counter 0 reset */ +#define ESITEST4SEL1 (0x0200u) /* Output signal selection for SIFTEST4 pin */ +#define ESITEST4SEL0 (0x0100u) /* Output signal selection for SIFTEST4 pin */ +#define ESIV2SEL (0x0080u) /* Source Selection for V2 bit*/ +#define ESICNT2EN (0x0020u) /* ESICNT2 enable (down counter) */ +#define ESICNT1EN (0x0010u) /* ESICNT1 enable (up/down counter) */ +#define ESICNT0EN (0x0008u) /* ESICNT0 enable (up counter) */ +#define ESIQ7TRG (0x0004u) /* Enabling to use Q7 as trigger for a TSM sequence */ +#define ESIQ6EN (0x0001u) /* Q6 enable */ + +/* ESIPSM Control Bits */ +#define ESIV2SEL_L (0x0080u) /* Source Selection for V2 bit*/ +#define ESICNT2EN_L (0x0020u) /* ESICNT2 enable (down counter) */ +#define ESICNT1EN_L (0x0010u) /* ESICNT1 enable (up/down counter) */ +#define ESICNT0EN_L (0x0008u) /* ESICNT0 enable (up counter) */ +#define ESIQ7TRG_L (0x0004u) /* Enabling to use Q7 as trigger for a TSM sequence */ +#define ESIQ6EN_L (0x0001u) /* Q6 enable */ + +/* ESIPSM Control Bits */ +#define ESICNT2RST_H (0x0080u) /* ESI Counter 2 reset */ +#define ESICNT1RST_H (0x0040u) /* ESI Counter 1 reset */ +#define ESICNT0RST_H (0x0020u) /* ESI Counter 0 reset */ +#define ESITEST4SEL1_H (0x0002u) /* Output signal selection for SIFTEST4 pin */ +#define ESITEST4SEL0_H (0x0001u) /* Output signal selection for SIFTEST4 pin */ + +#define ESITEST4SEL_0 (0x0000u) /* Q1 signal from PSM table */ +#define ESITEST4SEL_1 (0x0100u) /* Q2 signal from PSM table */ +#define ESITEST4SEL_2 (0x0200u) /* TSM clock signal from Timing State Machine */ +#define ESITEST4SEL_3 (0x0300u) /* AFE1's comparator output signal Comp1Out */ + +/* ESIOSC Control Bits */ +#define ESICLKFQ5 (0x2000u) /* Internal oscillator frequency adjust */ +#define ESICLKFQ4 (0x1000u) /* Internal oscillator frequency adjust */ +#define ESICLKFQ3 (0x0800u) /* Internal oscillator frequency adjust */ +#define ESICLKFQ2 (0x0400u) /* Internal oscillator frequency adjust */ +#define ESICLKFQ1 (0x0200u) /* Internal oscillator frequency adjust */ +#define ESICLKFQ0 (0x0100u) /* Internal oscillator frequency adjust */ +#define ESICLKGON (0x0002u) /* Internal oscillator control */ +#define ESIHFSEL (0x0001u) /* Internal oscillator enable */ + +/* ESIOSC Control Bits */ +#define ESICLKGON_L (0x0002u) /* Internal oscillator control */ +#define ESIHFSEL_L (0x0001u) /* Internal oscillator enable */ + +/* ESIOSC Control Bits */ +#define ESICLKFQ5_H (0x0020u) /* Internal oscillator frequency adjust */ +#define ESICLKFQ4_H (0x0010u) /* Internal oscillator frequency adjust */ +#define ESICLKFQ3_H (0x0008u) /* Internal oscillator frequency adjust */ +#define ESICLKFQ2_H (0x0004u) /* Internal oscillator frequency adjust */ +#define ESICLKFQ1_H (0x0002u) /* Internal oscillator frequency adjust */ +#define ESICLKFQ0_H (0x0001u) /* Internal oscillator frequency adjust */ + +/* ESICTL Control Bits */ +#define ESIS3SEL2 (0x8000u) /* PPUS3 source select */ +#define ESIS3SEL1 (0x4000u) /* PPUS3 source select */ +#define ESIS3SEL0 (0x2000u) /* PPUS3 source select */ +#define ESIS2SEL2 (0x1000u) /* PPUS2 source select */ +#define ESIS2SEL1 (0x0800u) /* PPUS2 source select */ +#define ESIS2SEL0 (0x0400u) /* PPUS2 source select */ +#define ESIS1SEL2 (0x0200u) /* PPUS1 source select */ +#define ESIS1SEL1 (0x0100u) /* PPUS1 source select */ +#define ESIS1SEL0 (0x0080u) /* PPUS1 source select */ +#define ESITCH11 (0x0040u) /* select the comparator input for test channel 1 */ +#define ESITCH10 (0x0020u) /* select the comparator input for test channel 1 */ +#define ESITCH01 (0x0010u) /* select the comparator input for test channel 0 */ +#define ESITCH00 (0x0008u) /* select the comparator input for test channel 0 */ +#define ESICS (0x0004u) /* Comparator output/Timer_A input selection */ +#define ESITESTD (0x0002u) /* Test cycle insertion */ +#define ESIEN (0x0001u) /* Extended Scan interface enable */ + +/* ESICTL Control Bits */ +#define ESIS1SEL0_L (0x0080u) /* PPUS1 source select */ +#define ESITCH11_L (0x0040u) /* select the comparator input for test channel 1 */ +#define ESITCH10_L (0x0020u) /* select the comparator input for test channel 1 */ +#define ESITCH01_L (0x0010u) /* select the comparator input for test channel 0 */ +#define ESITCH00_L (0x0008u) /* select the comparator input for test channel 0 */ +#define ESICS_L (0x0004u) /* Comparator output/Timer_A input selection */ +#define ESITESTD_L (0x0002u) /* Test cycle insertion */ +#define ESIEN_L (0x0001u) /* Extended Scan interface enable */ + +/* ESICTL Control Bits */ +#define ESIS3SEL2_H (0x0080u) /* PPUS3 source select */ +#define ESIS3SEL1_H (0x0040u) /* PPUS3 source select */ +#define ESIS3SEL0_H (0x0020u) /* PPUS3 source select */ +#define ESIS2SEL2_H (0x0010u) /* PPUS2 source select */ +#define ESIS2SEL1_H (0x0008u) /* PPUS2 source select */ +#define ESIS2SEL0_H (0x0004u) /* PPUS2 source select */ +#define ESIS1SEL2_H (0x0002u) /* PPUS1 source select */ +#define ESIS1SEL1_H (0x0001u) /* PPUS1 source select */ + +#define ESIS3SEL_0 (0x0000u) /* ESIOUT0 is the PPUS3 source */ +#define ESIS3SEL_1 (0x2000u) /* ESIOUT1 is the PPUS3 source */ +#define ESIS3SEL_2 (0x4000u) /* ESIOUT2 is the PPUS3 source */ +#define ESIS3SEL_3 (0x6000u) /* ESIOUT3 is the PPUS3 source */ +#define ESIS3SEL_4 (0x8000u) /* ESIOUT4 is the PPUS3 source */ +#define ESIS3SEL_5 (0xA000u) /* ESIOUT5 is the PPUS3 source */ +#define ESIS3SEL_6 (0xC000u) /* ESIOUT6 is the PPUS3 source */ +#define ESIS3SEL_7 (0xE000u) /* ESIOUT7 is the PPUS3 source */ +#define ESIS2SEL_0 (0x0000u) /* ESIOUT0 is the PPUS2 source */ +#define ESIS2SEL_1 (0x0400u) /* ESIOUT1 is the PPUS2 source */ +#define ESIS2SEL_2 (0x0800u) /* ESIOUT2 is the PPUS2 source */ +#define ESIS2SEL_3 (0x0C00u) /* ESIOUT3 is the PPUS2 source */ +#define ESIS2SEL_4 (0x1000u) /* ESIOUT4 is the PPUS2 source */ +#define ESIS2SEL_5 (0x1400u) /* ESIOUT5 is the PPUS2 source */ +#define ESIS2SEL_6 (0x1800u) /* ESIOUT6 is the PPUS2 source */ +#define ESIS2SEL_7 (0x1C00u) /* ESIOUT7 is the PPUS2 source */ +#define ESIS1SEL_0 (0x0000u) /* ESIOUT0 is the PPUS1 source */ +#define ESIS1SEL_1 (0x0080u) /* ESIOUT1 is the PPUS1 source */ +#define ESIS1SEL_2 (0x0100u) /* ESIOUT2 is the PPUS1 source */ +#define ESIS1SEL_3 (0x0180u) /* ESIOUT3 is the PPUS1 source */ +#define ESIS1SEL_4 (0x0200u) /* ESIOUT4 is the PPUS1 source */ +#define ESIS1SEL_5 (0x0280u) /* ESIOUT5 is the PPUS1 source */ +#define ESIS1SEL_6 (0x0300u) /* ESIOUT6 is the PPUS1 source */ +#define ESIS1SEL_7 (0x0380u) /* ESIOUT7 is the PPUS1 source */ +#define ESITCH1_0 (0x0000u) /* Comparator input is ESICH0 when ESICAX = 0; Comparator input is ESICI0 when ESICAX = 1 */ +#define ESITCH1_1 (0x0400u) /* Comparator input is ESICH1 when ESICAX = 0; Comparator input is ESICI1 when ESICAX = 1 */ +#define ESITCH1_2 (0x0800u) /* Comparator input is ESICH2 when ESICAX = 0; Comparator input is ESICI2 when ESICAX = 1 */ +#define ESITCH1_3 (0x0C00u) /* Comparator input is ESICH3 when ESICAX = 0; Comparator input is ESICI3 when ESICAX = 1 */ +#define ESITCH0_0 (0x0000u) /* Comparator input is ESICH0 when ESICAX = 0; Comparator input is ESICI0 when ESICAX = 1 */ +#define ESITCH0_1 (0x0008u) /* Comparator input is ESICH1 when ESICAX = 0; Comparator input is ESICI1 when ESICAX = 1 */ +#define ESITCH0_2 (0x0010u) /* Comparator input is ESICH2 when ESICAX = 0; Comparator input is ESICI2 when ESICAX = 1 */ +#define ESITCH0_3 (0x0018u) /* Comparator input is ESICH3 when ESICAX = 0; Comparator input is ESICI3 when ESICAX = 1 */ + +/* Timing State Machine Control Bits */ +#define ESIREPEAT4 (0x8000u) /* These bits together with the ESICLK bit configure the duration of this state */ +#define ESIREPEAT3 (0x4000u) /* ESIREPEATx selects the number of clock cycles for this state. The number of clock cycles = ESIREPEATx + 1 */ +#define ESIREPEAT2 (0x2000u) /* */ +#define ESIREPEAT1 (0x1000u) /* */ +#define ESIREPEAT0 (0x0800u) /* */ +#define ESICLK (0x0400u) /* This bit selects the clock source for the TSM */ +#define ESISTOP (0x0200u) /* This bit indicates the end of the TSM sequence */ +#define ESIDAC (0x0100u) /* TSM DAC on */ +#define ESITESTS1 (0x0080u) /* TSM test cycle control */ +#define ESIRSON (0x0040u) /* Internal output latches enabled */ +#define ESICLKON (0x0020u) /* High-frequency clock on */ +#define ESICA (0x0010u) /* TSM comparator on */ +#define ESIEX (0x0008u) /* Excitation and sample-and-hold */ +#define ESILCEN (0x0004u) /* LC enable */ +#define ESICH1 (0x0002u) /* Input channel select */ +#define ESICH0 (0x0001u) /* Input channel select */ + +/* Timing State Machine Control Bits */ +#define ESITESTS1_L (0x0080u) /* TSM test cycle control */ +#define ESIRSON_L (0x0040u) /* Internal output latches enabled */ +#define ESICLKON_L (0x0020u) /* High-frequency clock on */ +#define ESICA_L (0x0010u) /* TSM comparator on */ +#define ESIEX_L (0x0008u) /* Excitation and sample-and-hold */ +#define ESILCEN_L (0x0004u) /* LC enable */ +#define ESICH1_L (0x0002u) /* Input channel select */ +#define ESICH0_L (0x0001u) /* Input channel select */ + +/* Timing State Machine Control Bits */ +#define ESIREPEAT4_H (0x0080u) /* These bits together with the ESICLK bit configure the duration of this state */ +#define ESIREPEAT3_H (0x0040u) /* ESIREPEATx selects the number of clock cycles for this state. The number of clock cycles = ESIREPEATx + 1 */ +#define ESIREPEAT2_H (0x0020u) /* */ +#define ESIREPEAT1_H (0x0010u) /* */ +#define ESIREPEAT0_H (0x0008u) /* */ +#define ESICLK_H (0x0004u) /* This bit selects the clock source for the TSM */ +#define ESISTOP_H (0x0002u) /* This bit indicates the end of the TSM sequence */ +#define ESIDAC_H (0x0001u) /* TSM DAC on */ + +#define ESICAAZ (0x0020u) /* Comparator Offset calibration annulation */ + +#define ESIREPEAT_0 (0x0000u) /* These bits configure the duration of this state */ +#define ESIREPEAT_1 (0x0800u) /* ESIREPEATx selects the number of clock cycles for this state. The number of clock cycles = ESIREPEATx + 1 */ +#define ESIREPEAT_2 (0x1000u) +#define ESIREPEAT_3 (0x1800u) +#define ESIREPEAT_4 (0x2000u) +#define ESIREPEAT_5 (0x2800u) +#define ESIREPEAT_6 (0x3000u) +#define ESIREPEAT_7 (0x3800u) +#define ESIREPEAT_8 (0x4000u) +#define ESIREPEAT_9 (0x4800u) +#define ESIREPEAT_10 (0x5000u) +#define ESIREPEAT_11 (0x5800u) +#define ESIREPEAT_12 (0x6000u) +#define ESIREPEAT_13 (0x6800u) +#define ESIREPEAT_14 (0x7000u) +#define ESIREPEAT_15 (0x7800u) +#define ESIREPEAT_16 (0x8000u) +#define ESIREPEAT_17 (0x8800u) +#define ESIREPEAT_18 (0x9000u) +#define ESIREPEAT_19 (0x9800u) +#define ESIREPEAT_20 (0xA000u) +#define ESIREPEAT_21 (0xA800u) +#define ESIREPEAT_22 (0xB000u) +#define ESIREPEAT_23 (0xB800u) +#define ESIREPEAT_24 (0xC000u) +#define ESIREPEAT_25 (0xC800u) +#define ESIREPEAT_26 (0xD000u) +#define ESIREPEAT_27 (0xD800u) +#define ESIREPEAT_28 (0xE000u) +#define ESIREPEAT_29 (0xE800u) +#define ESIREPEAT_30 (0xF000u) +#define ESIREPEAT_31 (0xF800u) +#define ESICH_0 (0x0000u) /* Input channel select: ESICH0 */ +#define ESICH_1 (0x0001u) /* Input channel select: ESICH1 */ +#define ESICH_2 (0x0002u) /* Input channel select: ESICH2 */ +#define ESICH_3 (0x0003u) /* Input channel select: ESICH3 */ +#endif +/************************************************************ +* EXTENDED SCAN INTERFACE RAM +************************************************************/ +#ifdef __MSP430_HAS_ESI_RAM__ /* Definition to show that Module is available */ + +#define OFS_ESIRAM0 (0x0000u) /* ESI RAM 0 */ +#define OFS_ESIRAM1 (0x0001u) /* ESI RAM 1 */ +#define OFS_ESIRAM2 (0x0002u) /* ESI RAM 2 */ +#define OFS_ESIRAM3 (0x0003u) /* ESI RAM 3 */ +#define OFS_ESIRAM4 (0x0004u) /* ESI RAM 4 */ +#define OFS_ESIRAM5 (0x0005u) /* ESI RAM 5 */ +#define OFS_ESIRAM6 (0x0006u) /* ESI RAM 6 */ +#define OFS_ESIRAM7 (0x0007u) /* ESI RAM 7 */ +#define OFS_ESIRAM8 (0x0008u) /* ESI RAM 8 */ +#define OFS_ESIRAM9 (0x0009u) /* ESI RAM 9 */ +#define OFS_ESIRAM10 (0x000Au) /* ESI RAM 10 */ +#define OFS_ESIRAM11 (0x000Bu) /* ESI RAM 11 */ +#define OFS_ESIRAM12 (0x000Cu) /* ESI RAM 12 */ +#define OFS_ESIRAM13 (0x000Du) /* ESI RAM 13 */ +#define OFS_ESIRAM14 (0x000Eu) /* ESI RAM 14 */ +#define OFS_ESIRAM15 (0x000Fu) /* ESI RAM 15 */ +#define OFS_ESIRAM16 (0x0010u) /* ESI RAM 16 */ +#define OFS_ESIRAM17 (0x0011u) /* ESI RAM 17 */ +#define OFS_ESIRAM18 (0x0012u) /* ESI RAM 18 */ +#define OFS_ESIRAM19 (0x0013u) /* ESI RAM 19 */ +#define OFS_ESIRAM20 (0x0014u) /* ESI RAM 20 */ +#define OFS_ESIRAM21 (0x0015u) /* ESI RAM 21 */ +#define OFS_ESIRAM22 (0x0016u) /* ESI RAM 22 */ +#define OFS_ESIRAM23 (0x0017u) /* ESI RAM 23 */ +#define OFS_ESIRAM24 (0x0018u) /* ESI RAM 24 */ +#define OFS_ESIRAM25 (0x0019u) /* ESI RAM 25 */ +#define OFS_ESIRAM26 (0x001Au) /* ESI RAM 26 */ +#define OFS_ESIRAM27 (0x001Bu) /* ESI RAM 27 */ +#define OFS_ESIRAM28 (0x001Cu) /* ESI RAM 28 */ +#define OFS_ESIRAM29 (0x001Du) /* ESI RAM 29 */ +#define OFS_ESIRAM30 (0x001Eu) /* ESI RAM 30 */ +#define OFS_ESIRAM31 (0x001Fu) /* ESI RAM 31 */ +#define OFS_ESIRAM32 (0x0020u) /* ESI RAM 32 */ +#define OFS_ESIRAM33 (0x0021u) /* ESI RAM 33 */ +#define OFS_ESIRAM34 (0x0022u) /* ESI RAM 34 */ +#define OFS_ESIRAM35 (0x0023u) /* ESI RAM 35 */ +#define OFS_ESIRAM36 (0x0024u) /* ESI RAM 36 */ +#define OFS_ESIRAM37 (0x0025u) /* ESI RAM 37 */ +#define OFS_ESIRAM38 (0x0026u) /* ESI RAM 38 */ +#define OFS_ESIRAM39 (0x0027u) /* ESI RAM 39 */ +#define OFS_ESIRAM40 (0x0028u) /* ESI RAM 40 */ +#define OFS_ESIRAM41 (0x0029u) /* ESI RAM 41 */ +#define OFS_ESIRAM42 (0x002Au) /* ESI RAM 42 */ +#define OFS_ESIRAM43 (0x002Bu) /* ESI RAM 43 */ +#define OFS_ESIRAM44 (0x002Cu) /* ESI RAM 44 */ +#define OFS_ESIRAM45 (0x002Du) /* ESI RAM 45 */ +#define OFS_ESIRAM46 (0x002Eu) /* ESI RAM 46 */ +#define OFS_ESIRAM47 (0x002Fu) /* ESI RAM 47 */ +#define OFS_ESIRAM48 (0x0030u) /* ESI RAM 48 */ +#define OFS_ESIRAM49 (0x0031u) /* ESI RAM 49 */ +#define OFS_ESIRAM50 (0x0032u) /* ESI RAM 50 */ +#define OFS_ESIRAM51 (0x0033u) /* ESI RAM 51 */ +#define OFS_ESIRAM52 (0x0034u) /* ESI RAM 52 */ +#define OFS_ESIRAM53 (0x0035u) /* ESI RAM 53 */ +#define OFS_ESIRAM54 (0x0036u) /* ESI RAM 54 */ +#define OFS_ESIRAM55 (0x0037u) /* ESI RAM 55 */ +#define OFS_ESIRAM56 (0x0038u) /* ESI RAM 56 */ +#define OFS_ESIRAM57 (0x0039u) /* ESI RAM 57 */ +#define OFS_ESIRAM58 (0x003Au) /* ESI RAM 58 */ +#define OFS_ESIRAM59 (0x003Bu) /* ESI RAM 59 */ +#define OFS_ESIRAM60 (0x003Cu) /* ESI RAM 60 */ +#define OFS_ESIRAM61 (0x003Du) /* ESI RAM 61 */ +#define OFS_ESIRAM62 (0x003Eu) /* ESI RAM 62 */ +#define OFS_ESIRAM63 (0x003Fu) /* ESI RAM 63 */ +#define OFS_ESIRAM64 (0x0040u) /* ESI RAM 64 */ +#define OFS_ESIRAM65 (0x0041u) /* ESI RAM 65 */ +#define OFS_ESIRAM66 (0x0042u) /* ESI RAM 66 */ +#define OFS_ESIRAM67 (0x0043u) /* ESI RAM 67 */ +#define OFS_ESIRAM68 (0x0044u) /* ESI RAM 68 */ +#define OFS_ESIRAM69 (0x0045u) /* ESI RAM 69 */ +#define OFS_ESIRAM70 (0x0046u) /* ESI RAM 70 */ +#define OFS_ESIRAM71 (0x0047u) /* ESI RAM 71 */ +#define OFS_ESIRAM72 (0x0048u) /* ESI RAM 72 */ +#define OFS_ESIRAM73 (0x0049u) /* ESI RAM 73 */ +#define OFS_ESIRAM74 (0x004Au) /* ESI RAM 74 */ +#define OFS_ESIRAM75 (0x004Bu) /* ESI RAM 75 */ +#define OFS_ESIRAM76 (0x004Cu) /* ESI RAM 76 */ +#define OFS_ESIRAM77 (0x004Du) /* ESI RAM 77 */ +#define OFS_ESIRAM78 (0x004Eu) /* ESI RAM 78 */ +#define OFS_ESIRAM79 (0x004Fu) /* ESI RAM 79 */ +#define OFS_ESIRAM80 (0x0050u) /* ESI RAM 80 */ +#define OFS_ESIRAM81 (0x0051u) /* ESI RAM 81 */ +#define OFS_ESIRAM82 (0x0052u) /* ESI RAM 82 */ +#define OFS_ESIRAM83 (0x0053u) /* ESI RAM 83 */ +#define OFS_ESIRAM84 (0x0054u) /* ESI RAM 84 */ +#define OFS_ESIRAM85 (0x0055u) /* ESI RAM 85 */ +#define OFS_ESIRAM86 (0x0056u) /* ESI RAM 86 */ +#define OFS_ESIRAM87 (0x0057u) /* ESI RAM 87 */ +#define OFS_ESIRAM88 (0x0058u) /* ESI RAM 88 */ +#define OFS_ESIRAM89 (0x0059u) /* ESI RAM 89 */ +#define OFS_ESIRAM90 (0x005Au) /* ESI RAM 90 */ +#define OFS_ESIRAM91 (0x005Bu) /* ESI RAM 91 */ +#define OFS_ESIRAM92 (0x005Cu) /* ESI RAM 92 */ +#define OFS_ESIRAM93 (0x005Du) /* ESI RAM 93 */ +#define OFS_ESIRAM94 (0x005Eu) /* ESI RAM 94 */ +#define OFS_ESIRAM95 (0x005Fu) /* ESI RAM 95 */ +#define OFS_ESIRAM96 (0x0060u) /* ESI RAM 96 */ +#define OFS_ESIRAM97 (0x0061u) /* ESI RAM 97 */ +#define OFS_ESIRAM98 (0x0062u) /* ESI RAM 98 */ +#define OFS_ESIRAM99 (0x0063u) /* ESI RAM 99 */ +#define OFS_ESIRAM100 (0x0064u) /* ESI RAM 100 */ +#define OFS_ESIRAM101 (0x0065u) /* ESI RAM 101 */ +#define OFS_ESIRAM102 (0x0066u) /* ESI RAM 102 */ +#define OFS_ESIRAM103 (0x0067u) /* ESI RAM 103 */ +#define OFS_ESIRAM104 (0x0068u) /* ESI RAM 104 */ +#define OFS_ESIRAM105 (0x0069u) /* ESI RAM 105 */ +#define OFS_ESIRAM106 (0x006Au) /* ESI RAM 106 */ +#define OFS_ESIRAM107 (0x006Bu) /* ESI RAM 107 */ +#define OFS_ESIRAM108 (0x006Cu) /* ESI RAM 108 */ +#define OFS_ESIRAM109 (0x006Du) /* ESI RAM 109 */ +#define OFS_ESIRAM110 (0x006Eu) /* ESI RAM 110 */ +#define OFS_ESIRAM111 (0x006Fu) /* ESI RAM 111 */ +#define OFS_ESIRAM112 (0x0070u) /* ESI RAM 112 */ +#define OFS_ESIRAM113 (0x0071u) /* ESI RAM 113 */ +#define OFS_ESIRAM114 (0x0072u) /* ESI RAM 114 */ +#define OFS_ESIRAM115 (0x0073u) /* ESI RAM 115 */ +#define OFS_ESIRAM116 (0x0074u) /* ESI RAM 116 */ +#define OFS_ESIRAM117 (0x0075u) /* ESI RAM 117 */ +#define OFS_ESIRAM118 (0x0076u) /* ESI RAM 118 */ +#define OFS_ESIRAM119 (0x0077u) /* ESI RAM 119 */ +#define OFS_ESIRAM120 (0x0078u) /* ESI RAM 120 */ +#define OFS_ESIRAM121 (0x0079u) /* ESI RAM 121 */ +#define OFS_ESIRAM122 (0x007Au) /* ESI RAM 122 */ +#define OFS_ESIRAM123 (0x007Bu) /* ESI RAM 123 */ +#define OFS_ESIRAM124 (0x007Cu) /* ESI RAM 124 */ +#define OFS_ESIRAM125 (0x007Du) /* ESI RAM 125 */ +#define OFS_ESIRAM126 (0x007Eu) /* ESI RAM 126 */ +#define OFS_ESIRAM127 (0x007Fu) /* ESI RAM 127 */ +#endif +/************************************************************* +* FRAM Memory +*************************************************************/ +#ifdef __MSP430_HAS_FRAM__ /* Definition to show that Module is available */ + +#define OFS_FRCTL0 (0x0000u) /* FRAM Controller Control 0 */ +#define OFS_FRCTL0_L OFS_FRCTL0 +#define OFS_FRCTL0_H OFS_FRCTL0+1 +#define OFS_GCCTL0 (0x0004u) /* General Control 0 */ +#define OFS_GCCTL0_L OFS_GCCTL0 +#define OFS_GCCTL0_H OFS_GCCTL0+1 +#define OFS_GCCTL1 (0x0006u) /* General Control 1 */ +#define OFS_GCCTL1_L OFS_GCCTL1 +#define OFS_GCCTL1_H OFS_GCCTL1+1 + +#define FRCTLPW (0xA500u) /* FRAM password for write */ +#define FRPW (0x9600u) /* FRAM password returned by read */ +#define FWPW (0xA500u) /* FRAM password for write */ +#define FXPW (0x3300u) /* for use with XOR instruction */ + +/* FRCTL0 Control Bits */ +//#define RESERVED (0x0001u) /* RESERVED */ +//#define RESERVED (0x0002u) /* RESERVED */ +//#define RESERVED (0x0004u) /* RESERVED */ +#define NWAITS0 (0x0010u) /* FRAM Wait state control Bit: 0 */ +#define NWAITS1 (0x0020u) /* FRAM Wait state control Bit: 1 */ +#define NWAITS2 (0x0040u) /* FRAM Wait state control Bit: 2 */ +//#define RESERVED (0x0080u) /* RESERVED */ + +/* FRCTL0 Control Bits */ +//#define RESERVED (0x0001u) /* RESERVED */ +//#define RESERVED (0x0002u) /* RESERVED */ +//#define RESERVED (0x0004u) /* RESERVED */ +#define NWAITS0_L (0x0010u) /* FRAM Wait state control Bit: 0 */ +#define NWAITS1_L (0x0020u) /* FRAM Wait state control Bit: 1 */ +#define NWAITS2_L (0x0040u) /* FRAM Wait state control Bit: 2 */ +//#define RESERVED (0x0080u) /* RESERVED */ + +#define NWAITS_0 (0x0000u) /* FRAM Wait state control: 0 */ +#define NWAITS_1 (0x0010u) /* FRAM Wait state control: 1 */ +#define NWAITS_2 (0x0020u) /* FRAM Wait state control: 2 */ +#define NWAITS_3 (0x0030u) /* FRAM Wait state control: 3 */ +#define NWAITS_4 (0x0040u) /* FRAM Wait state control: 4 */ +#define NWAITS_5 (0x0050u) /* FRAM Wait state control: 5 */ +#define NWAITS_6 (0x0060u) /* FRAM Wait state control: 6 */ +#define NWAITS_7 (0x0070u) /* FRAM Wait state control: 7 */ + +/* Legacy Defines */ +#define NAUTO (0x0008u) /* FRAM Disables the wait state generator (obsolete on Rev.E and later)*/ +#define NACCESS0 (0x0010u) /* FRAM Wait state Generator Access Time control Bit: 0 */ +#define NACCESS1 (0x0020u) /* FRAM Wait state Generator Access Time control Bit: 1 */ +#define NACCESS2 (0x0040u) /* FRAM Wait state Generator Access Time control Bit: 2 */ +#define NACCESS_0 (0x0000u) /* FRAM Wait state Generator Access Time control: 0 */ +#define NACCESS_1 (0x0010u) /* FRAM Wait state Generator Access Time control: 1 */ +#define NACCESS_2 (0x0020u) /* FRAM Wait state Generator Access Time control: 2 */ +#define NACCESS_3 (0x0030u) /* FRAM Wait state Generator Access Time control: 3 */ +#define NACCESS_4 (0x0040u) /* FRAM Wait state Generator Access Time control: 4 */ +#define NACCESS_5 (0x0050u) /* FRAM Wait state Generator Access Time control: 5 */ +#define NACCESS_6 (0x0060u) /* FRAM Wait state Generator Access Time control: 6 */ +#define NACCESS_7 (0x0070u) /* FRAM Wait state Generator Access Time control: 7 */ + +/* GCCTL0 Control Bits */ +//#define RESERVED (0x0001u) /* RESERVED */ +#define FRLPMPWR (0x0002u) /* FRAM Enable FRAM auto power up after LPM */ +#define FRPWR (0x0004u) /* FRAM Power Control */ +#define ACCTEIE (0x0008u) /* Enable NMI event if Access time error occurs */ +//#define RESERVED (0x0010u) /* RESERVED */ +#define CBDIE (0x0020u) /* Enable NMI event if correctable bit error detected */ +#define UBDIE (0x0040u) /* Enable NMI event if uncorrectable bit error detected */ +#define UBDRSTEN (0x0080u) /* Enable Power Up Clear (PUC) reset if FRAM uncorrectable bit error detected */ + +/* GCCTL0 Control Bits */ +//#define RESERVED (0x0001u) /* RESERVED */ +#define FRLPMPWR_L (0x0002u) /* FRAM Enable FRAM auto power up after LPM */ +#define FRPWR_L (0x0004u) /* FRAM Power Control */ +#define ACCTEIE_L (0x0008u) /* Enable NMI event if Access time error occurs */ +//#define RESERVED (0x0010u) /* RESERVED */ +#define CBDIE_L (0x0020u) /* Enable NMI event if correctable bit error detected */ +#define UBDIE_L (0x0040u) /* Enable NMI event if uncorrectable bit error detected */ +#define UBDRSTEN_L (0x0080u) /* Enable Power Up Clear (PUC) reset if FRAM uncorrectable bit error detected */ + +/* GCCTL1 Control Bits */ +//#define RESERVED (0x0001u) /* RESERVED */ +#define CBDIFG (0x0002u) /* FRAM correctable bit error flag */ +#define UBDIFG (0x0004u) /* FRAM uncorrectable bit error flag */ +#define ACCTEIFG (0x0008u) /* Access time error flag */ + +/* GCCTL1 Control Bits */ +//#define RESERVED (0x0001u) /* RESERVED */ +#define CBDIFG_L (0x0002u) /* FRAM correctable bit error flag */ +#define UBDIFG_L (0x0004u) /* FRAM uncorrectable bit error flag */ +#define ACCTEIFG_L (0x0008u) /* Access time error flag */ + +#endif +/************************************************************ +* LCD_C +************************************************************/ +#ifdef __MSP430_HAS_LCD_C__ /* Definition to show that Module is available */ + +#define OFS_LCDCCTL0 (0x0000u) /* LCD_C Control Register 0 */ +#define OFS_LCDCCTL0_L OFS_LCDCCTL0 +#define OFS_LCDCCTL0_H OFS_LCDCCTL0+1 +#define OFS_LCDCCTL1 (0x0002u) /* LCD_C Control Register 1 */ +#define OFS_LCDCCTL1_L OFS_LCDCCTL1 +#define OFS_LCDCCTL1_H OFS_LCDCCTL1+1 +#define OFS_LCDCBLKCTL (0x0004u) /* LCD_C blinking control register */ +#define OFS_LCDCBLKCTL_L OFS_LCDCBLKCTL +#define OFS_LCDCBLKCTL_H OFS_LCDCBLKCTL+1 +#define OFS_LCDCMEMCTL (0x0006u) /* LCD_C memory control register */ +#define OFS_LCDCMEMCTL_L OFS_LCDCMEMCTL +#define OFS_LCDCMEMCTL_H OFS_LCDCMEMCTL+1 +#define OFS_LCDCVCTL (0x0008u) /* LCD_C Voltage Control Register */ +#define OFS_LCDCVCTL_L OFS_LCDCVCTL +#define OFS_LCDCVCTL_H OFS_LCDCVCTL+1 +#define OFS_LCDCPCTL0 (0x000Au) /* LCD_C Port Control Register 0 */ +#define OFS_LCDCPCTL0_L OFS_LCDCPCTL0 +#define OFS_LCDCPCTL0_H OFS_LCDCPCTL0+1 +#define OFS_LCDCPCTL1 (0x000Cu) /* LCD_C Port Control Register 1 */ +#define OFS_LCDCPCTL1_L OFS_LCDCPCTL1 +#define OFS_LCDCPCTL1_H OFS_LCDCPCTL1+1 +#define OFS_LCDCPCTL2 (0x000Eu) /* LCD_C Port Control Register 2 */ +#define OFS_LCDCPCTL2_L OFS_LCDCPCTL2 +#define OFS_LCDCPCTL2_H OFS_LCDCPCTL2+1 +#define OFS_LCDCPCTL3 (0x0010u) /* LCD_C Port Control Register 3 */ +#define OFS_LCDCPCTL3_L OFS_LCDCPCTL3 +#define OFS_LCDCPCTL3_H OFS_LCDCPCTL3+1 +#define OFS_LCDCCPCTL (0x0012u) /* LCD_C Charge Pump Control Register 3 */ +#define OFS_LCDCCPCTL_L OFS_LCDCCPCTL +#define OFS_LCDCCPCTL_H OFS_LCDCCPCTL+1 +#define OFS_LCDCIV (0x001Eu) /* LCD_C Interrupt Vector Register */ + +// LCDCCTL0 +#define LCDON (0x0001u) /* LCD_C LCD On */ +#define LCDLP (0x0002u) /* LCD_C Low Power Waveform */ +#define LCDSON (0x0004u) /* LCD_C LCD Segments On */ +#define LCDMX0 (0x0008u) /* LCD_C Mux Rate Bit: 0 */ +#define LCDMX1 (0x0010u) /* LCD_C Mux Rate Bit: 1 */ +#define LCDMX2 (0x0020u) /* LCD_C Mux Rate Bit: 2 */ +//#define RESERVED (0x0040u) /* LCD_C RESERVED */ +#define LCDSSEL (0x0080u) /* LCD_C Clock Select */ +#define LCDPRE0 (0x0100u) /* LCD_C LCD frequency pre-scaler Bit: 0 */ +#define LCDPRE1 (0x0200u) /* LCD_C LCD frequency pre-scaler Bit: 1 */ +#define LCDPRE2 (0x0400u) /* LCD_C LCD frequency pre-scaler Bit: 2 */ +#define LCDDIV0 (0x0800u) /* LCD_C LCD frequency divider Bit: 0 */ +#define LCDDIV1 (0x1000u) /* LCD_C LCD frequency divider Bit: 1 */ +#define LCDDIV2 (0x2000u) /* LCD_C LCD frequency divider Bit: 2 */ +#define LCDDIV3 (0x4000u) /* LCD_C LCD frequency divider Bit: 3 */ +#define LCDDIV4 (0x8000u) /* LCD_C LCD frequency divider Bit: 4 */ + +// LCDCCTL0 +#define LCDON_L (0x0001u) /* LCD_C LCD On */ +#define LCDLP_L (0x0002u) /* LCD_C Low Power Waveform */ +#define LCDSON_L (0x0004u) /* LCD_C LCD Segments On */ +#define LCDMX0_L (0x0008u) /* LCD_C Mux Rate Bit: 0 */ +#define LCDMX1_L (0x0010u) /* LCD_C Mux Rate Bit: 1 */ +#define LCDMX2_L (0x0020u) /* LCD_C Mux Rate Bit: 2 */ +//#define RESERVED (0x0040u) /* LCD_C RESERVED */ +#define LCDSSEL_L (0x0080u) /* LCD_C Clock Select */ + +// LCDCCTL0 +//#define RESERVED (0x0040u) /* LCD_C RESERVED */ +#define LCDPRE0_H (0x0001u) /* LCD_C LCD frequency pre-scaler Bit: 0 */ +#define LCDPRE1_H (0x0002u) /* LCD_C LCD frequency pre-scaler Bit: 1 */ +#define LCDPRE2_H (0x0004u) /* LCD_C LCD frequency pre-scaler Bit: 2 */ +#define LCDDIV0_H (0x0008u) /* LCD_C LCD frequency divider Bit: 0 */ +#define LCDDIV1_H (0x0010u) /* LCD_C LCD frequency divider Bit: 1 */ +#define LCDDIV2_H (0x0020u) /* LCD_C LCD frequency divider Bit: 2 */ +#define LCDDIV3_H (0x0040u) /* LCD_C LCD frequency divider Bit: 3 */ +#define LCDDIV4_H (0x0080u) /* LCD_C LCD frequency divider Bit: 4 */ + +#define LCDPRE_0 (0x0000u) /* LCD_C LCD frequency pre-scaler: /1 */ +#define LCDPRE_1 (0x0100u) /* LCD_C LCD frequency pre-scaler: /2 */ +#define LCDPRE_2 (0x0200u) /* LCD_C LCD frequency pre-scaler: /4 */ +#define LCDPRE_3 (0x0300u) /* LCD_C LCD frequency pre-scaler: /8 */ +#define LCDPRE_4 (0x0400u) /* LCD_C LCD frequency pre-scaler: /16 */ +#define LCDPRE_5 (0x0500u) /* LCD_C LCD frequency pre-scaler: /32 */ +#define LCDPRE__1 (0x0000u) /* LCD_C LCD frequency pre-scaler: /1 */ +#define LCDPRE__2 (0x0100u) /* LCD_C LCD frequency pre-scaler: /2 */ +#define LCDPRE__4 (0x0200u) /* LCD_C LCD frequency pre-scaler: /4 */ +#define LCDPRE__8 (0x0300u) /* LCD_C LCD frequency pre-scaler: /8 */ +#define LCDPRE__16 (0x0400u) /* LCD_C LCD frequency pre-scaler: /16 */ +#define LCDPRE__32 (0x0500u) /* LCD_C LCD frequency pre-scaler: /32 */ + +#define LCDDIV_0 (0x0000u) /* LCD_C LCD frequency divider: /1 */ +#define LCDDIV_1 (0x0800u) /* LCD_C LCD frequency divider: /2 */ +#define LCDDIV_2 (0x1000u) /* LCD_C LCD frequency divider: /3 */ +#define LCDDIV_3 (0x1800u) /* LCD_C LCD frequency divider: /4 */ +#define LCDDIV_4 (0x2000u) /* LCD_C LCD frequency divider: /5 */ +#define LCDDIV_5 (0x2800u) /* LCD_C LCD frequency divider: /6 */ +#define LCDDIV_6 (0x3000u) /* LCD_C LCD frequency divider: /7 */ +#define LCDDIV_7 (0x3800u) /* LCD_C LCD frequency divider: /8 */ +#define LCDDIV_8 (0x4000u) /* LCD_C LCD frequency divider: /9 */ +#define LCDDIV_9 (0x4800u) /* LCD_C LCD frequency divider: /10 */ +#define LCDDIV_10 (0x5000u) /* LCD_C LCD frequency divider: /11 */ +#define LCDDIV_11 (0x5800u) /* LCD_C LCD frequency divider: /12 */ +#define LCDDIV_12 (0x6000u) /* LCD_C LCD frequency divider: /13 */ +#define LCDDIV_13 (0x6800u) /* LCD_C LCD frequency divider: /14 */ +#define LCDDIV_14 (0x7000u) /* LCD_C LCD frequency divider: /15 */ +#define LCDDIV_15 (0x7800u) /* LCD_C LCD frequency divider: /16 */ +#define LCDDIV_16 (0x8000u) /* LCD_C LCD frequency divider: /17 */ +#define LCDDIV_17 (0x8800u) /* LCD_C LCD frequency divider: /18 */ +#define LCDDIV_18 (0x9000u) /* LCD_C LCD frequency divider: /19 */ +#define LCDDIV_19 (0x9800u) /* LCD_C LCD frequency divider: /20 */ +#define LCDDIV_20 (0xA000u) /* LCD_C LCD frequency divider: /21 */ +#define LCDDIV_21 (0xA800u) /* LCD_C LCD frequency divider: /22 */ +#define LCDDIV_22 (0xB000u) /* LCD_C LCD frequency divider: /23 */ +#define LCDDIV_23 (0xB800u) /* LCD_C LCD frequency divider: /24 */ +#define LCDDIV_24 (0xC000u) /* LCD_C LCD frequency divider: /25 */ +#define LCDDIV_25 (0xC800u) /* LCD_C LCD frequency divider: /26 */ +#define LCDDIV_26 (0xD000u) /* LCD_C LCD frequency divider: /27 */ +#define LCDDIV_27 (0xD800u) /* LCD_C LCD frequency divider: /28 */ +#define LCDDIV_28 (0xE000u) /* LCD_C LCD frequency divider: /29 */ +#define LCDDIV_29 (0xE800u) /* LCD_C LCD frequency divider: /30 */ +#define LCDDIV_30 (0xF000u) /* LCD_C LCD frequency divider: /31 */ +#define LCDDIV_31 (0xF800u) /* LCD_C LCD frequency divider: /32 */ +#define LCDDIV__1 (0x0000u) /* LCD_C LCD frequency divider: /1 */ +#define LCDDIV__2 (0x0800u) /* LCD_C LCD frequency divider: /2 */ +#define LCDDIV__3 (0x1000u) /* LCD_C LCD frequency divider: /3 */ +#define LCDDIV__4 (0x1800u) /* LCD_C LCD frequency divider: /4 */ +#define LCDDIV__5 (0x2000u) /* LCD_C LCD frequency divider: /5 */ +#define LCDDIV__6 (0x2800u) /* LCD_C LCD frequency divider: /6 */ +#define LCDDIV__7 (0x3000u) /* LCD_C LCD frequency divider: /7 */ +#define LCDDIV__8 (0x3800u) /* LCD_C LCD frequency divider: /8 */ +#define LCDDIV__9 (0x4000u) /* LCD_C LCD frequency divider: /9 */ +#define LCDDIV__10 (0x4800u) /* LCD_C LCD frequency divider: /10 */ +#define LCDDIV__11 (0x5000u) /* LCD_C LCD frequency divider: /11 */ +#define LCDDIV__12 (0x5800u) /* LCD_C LCD frequency divider: /12 */ +#define LCDDIV__13 (0x6000u) /* LCD_C LCD frequency divider: /13 */ +#define LCDDIV__14 (0x6800u) /* LCD_C LCD frequency divider: /14 */ +#define LCDDIV__15 (0x7000u) /* LCD_C LCD frequency divider: /15 */ +#define LCDDIV__16 (0x7800u) /* LCD_C LCD frequency divider: /16 */ +#define LCDDIV__17 (0x8000u) /* LCD_C LCD frequency divider: /17 */ +#define LCDDIV__18 (0x8800u) /* LCD_C LCD frequency divider: /18 */ +#define LCDDIV__19 (0x9000u) /* LCD_C LCD frequency divider: /19 */ +#define LCDDIV__20 (0x9800u) /* LCD_C LCD frequency divider: /20 */ +#define LCDDIV__21 (0xA000u) /* LCD_C LCD frequency divider: /21 */ +#define LCDDIV__22 (0xA800u) /* LCD_C LCD frequency divider: /22 */ +#define LCDDIV__23 (0xB000u) /* LCD_C LCD frequency divider: /23 */ +#define LCDDIV__24 (0xB800u) /* LCD_C LCD frequency divider: /24 */ +#define LCDDIV__25 (0xC000u) /* LCD_C LCD frequency divider: /25 */ +#define LCDDIV__26 (0xC800u) /* LCD_C LCD frequency divider: /26 */ +#define LCDDIV__27 (0xD000u) /* LCD_C LCD frequency divider: /27 */ +#define LCDDIV__28 (0xD800u) /* LCD_C LCD frequency divider: /28 */ +#define LCDDIV__29 (0xE000u) /* LCD_C LCD frequency divider: /29 */ +#define LCDDIV__30 (0xE800u) /* LCD_C LCD frequency divider: /30 */ +#define LCDDIV__31 (0xF000u) /* LCD_C LCD frequency divider: /31 */ +#define LCDDIV__32 (0xF800u) /* LCD_C LCD frequency divider: /32 */ + +/* Display modes coded with Bits 2-4 */ +#define LCDSTATIC (LCDSON) +#define LCD2MUX (LCDMX0+LCDSON) +#define LCD3MUX (LCDMX1+LCDSON) +#define LCD4MUX (LCDMX1+LCDMX0+LCDSON) +#define LCD5MUX (LCDMX2+LCDSON) +#define LCD6MUX (LCDMX2+LCDMX0+LCDSON) +#define LCD7MUX (LCDMX2+LCDMX1+LCDSON) +#define LCD8MUX (LCDMX2+LCDMX1+LCDMX0+LCDSON) + +// LCDCCTL1 +#define LCDFRMIFG (0x0001u) /* LCD_C LCD frame interrupt flag */ +#define LCDBLKOFFIFG (0x0002u) /* LCD_C LCD blinking off interrupt flag, */ +#define LCDBLKONIFG (0x0004u) /* LCD_C LCD blinking on interrupt flag, */ +#define LCDNOCAPIFG (0x0008u) /* LCD_C No cpacitance connected interrupt flag */ +#define LCDFRMIE (0x0100u) /* LCD_C LCD frame interrupt enable */ +#define LCDBLKOFFIE (0x0200u) /* LCD_C LCD blinking off interrupt flag, */ +#define LCDBLKONIE (0x0400u) /* LCD_C LCD blinking on interrupt flag, */ +#define LCDNOCAPIE (0x0800u) /* LCD_C No cpacitance connected interrupt enable */ + +// LCDCCTL1 +#define LCDFRMIFG_L (0x0001u) /* LCD_C LCD frame interrupt flag */ +#define LCDBLKOFFIFG_L (0x0002u) /* LCD_C LCD blinking off interrupt flag, */ +#define LCDBLKONIFG_L (0x0004u) /* LCD_C LCD blinking on interrupt flag, */ +#define LCDNOCAPIFG_L (0x0008u) /* LCD_C No cpacitance connected interrupt flag */ + +// LCDCCTL1 +#define LCDFRMIE_H (0x0001u) /* LCD_C LCD frame interrupt enable */ +#define LCDBLKOFFIE_H (0x0002u) /* LCD_C LCD blinking off interrupt flag, */ +#define LCDBLKONIE_H (0x0004u) /* LCD_C LCD blinking on interrupt flag, */ +#define LCDNOCAPIE_H (0x0008u) /* LCD_C No cpacitance connected interrupt enable */ + +// LCDCBLKCTL +#define LCDBLKMOD0 (0x0001u) /* LCD_C Blinking mode Bit: 0 */ +#define LCDBLKMOD1 (0x0002u) /* LCD_C Blinking mode Bit: 1 */ +#define LCDBLKPRE0 (0x0004u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 0 */ +#define LCDBLKPRE1 (0x0008u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 1 */ +#define LCDBLKPRE2 (0x0010u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 2 */ +#define LCDBLKDIV0 (0x0020u) /* LCD_C Clock divider for blinking frequency Bit: 0 */ +#define LCDBLKDIV1 (0x0040u) /* LCD_C Clock divider for blinking frequency Bit: 1 */ +#define LCDBLKDIV2 (0x0080u) /* LCD_C Clock divider for blinking frequency Bit: 2 */ + +// LCDCBLKCTL +#define LCDBLKMOD0_L (0x0001u) /* LCD_C Blinking mode Bit: 0 */ +#define LCDBLKMOD1_L (0x0002u) /* LCD_C Blinking mode Bit: 1 */ +#define LCDBLKPRE0_L (0x0004u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 0 */ +#define LCDBLKPRE1_L (0x0008u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 1 */ +#define LCDBLKPRE2_L (0x0010u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 2 */ +#define LCDBLKDIV0_L (0x0020u) /* LCD_C Clock divider for blinking frequency Bit: 0 */ +#define LCDBLKDIV1_L (0x0040u) /* LCD_C Clock divider for blinking frequency Bit: 1 */ +#define LCDBLKDIV2_L (0x0080u) /* LCD_C Clock divider for blinking frequency Bit: 2 */ + +#define LCDBLKMOD_0 (0x0000u) /* LCD_C Blinking mode: Off */ +#define LCDBLKMOD_1 (0x0001u) /* LCD_C Blinking mode: Individual */ +#define LCDBLKMOD_2 (0x0002u) /* LCD_C Blinking mode: All */ +#define LCDBLKMOD_3 (0x0003u) /* LCD_C Blinking mode: Switching */ + +// LCDCMEMCTL +#define LCDDISP (0x0001u) /* LCD_C LCD memory registers for display */ +#define LCDCLRM (0x0002u) /* LCD_C Clear LCD memory */ +#define LCDCLRBM (0x0004u) /* LCD_C Clear LCD blinking memory */ + +// LCDCMEMCTL +#define LCDDISP_L (0x0001u) /* LCD_C LCD memory registers for display */ +#define LCDCLRM_L (0x0002u) /* LCD_C Clear LCD memory */ +#define LCDCLRBM_L (0x0004u) /* LCD_C Clear LCD blinking memory */ + +// LCDCVCTL +#define LCD2B (0x0001u) /* Selects 1/2 bias. */ +#define VLCDREF0 (0x0002u) /* Selects reference voltage for regulated charge pump: 0 */ +#define VLCDREF1 (0x0004u) /* Selects reference voltage for regulated charge pump: 1 */ +#define LCDCPEN (0x0008u) /* LCD Voltage Charge Pump Enable. */ +#define VLCDEXT (0x0010u) /* Select external source for VLCD. */ +#define LCDEXTBIAS (0x0020u) /* V2 - V4 voltage select. */ +#define R03EXT (0x0040u) /* Selects external connections for LCD mid voltages. */ +#define LCDREXT (0x0080u) /* Selects external connection for lowest LCD voltage. */ +#define VLCD0 (0x0200u) /* VLCD select: 0 */ +#define VLCD1 (0x0400u) /* VLCD select: 1 */ +#define VLCD2 (0x0800u) /* VLCD select: 2 */ +#define VLCD3 (0x1000u) /* VLCD select: 3 */ +#define VLCD4 (0x2000u) /* VLCD select: 4 */ +#define VLCD5 (0x4000u) /* VLCD select: 5 */ + +// LCDCVCTL +#define LCD2B_L (0x0001u) /* Selects 1/2 bias. */ +#define VLCDREF0_L (0x0002u) /* Selects reference voltage for regulated charge pump: 0 */ +#define VLCDREF1_L (0x0004u) /* Selects reference voltage for regulated charge pump: 1 */ +#define LCDCPEN_L (0x0008u) /* LCD Voltage Charge Pump Enable. */ +#define VLCDEXT_L (0x0010u) /* Select external source for VLCD. */ +#define LCDEXTBIAS_L (0x0020u) /* V2 - V4 voltage select. */ +#define R03EXT_L (0x0040u) /* Selects external connections for LCD mid voltages. */ +#define LCDREXT_L (0x0080u) /* Selects external connection for lowest LCD voltage. */ + +// LCDCVCTL +#define VLCD0_H (0x0002u) /* VLCD select: 0 */ +#define VLCD1_H (0x0004u) /* VLCD select: 1 */ +#define VLCD2_H (0x0008u) /* VLCD select: 2 */ +#define VLCD3_H (0x0010u) /* VLCD select: 3 */ +#define VLCD4_H (0x0020u) /* VLCD select: 4 */ +#define VLCD5_H (0x0040u) /* VLCD select: 5 */ + +/* Reference voltage source select for the regulated charge pump */ +#define VLCDREF_0 (0x0000u) /* Internal */ +#define VLCDREF_1 (0x0002u) /* External */ +#define VLCDREF_2 (0x0004u) /* Reserved */ +#define VLCDREF_3 (0x0006u) /* Reserved */ + +/* Charge pump voltage selections */ +#define VLCD_0 (0x0000u) /* Charge pump disabled */ +#define VLCD_1 (0x0200u) /* VLCD = 2.60V */ +#define VLCD_2 (0x0400u) /* VLCD = 2.66V */ +#define VLCD_3 (0x0600u) /* VLCD = 2.72V */ +#define VLCD_4 (0x0800u) /* VLCD = 2.78V */ +#define VLCD_5 (0x0A00u) /* VLCD = 2.84V */ +#define VLCD_6 (0x0C00u) /* VLCD = 2.90V */ +#define VLCD_7 (0x0E00u) /* VLCD = 2.96V */ +#define VLCD_8 (0x1000u) /* VLCD = 3.02V */ +#define VLCD_9 (0x1200u) /* VLCD = 3.08V */ +#define VLCD_10 (0x1400u) /* VLCD = 3.14V */ +#define VLCD_11 (0x1600u) /* VLCD = 3.20V */ +#define VLCD_12 (0x1800u) /* VLCD = 3.26V */ +#define VLCD_13 (0x1A00u) /* VLCD = 3.32V */ +#define VLCD_14 (0x1C00u) /* VLCD = 3.38V */ +#define VLCD_15 (0x1E00u) /* VLCD = 3.44V */ + +#define VLCD_DISABLED (0x0000u) /* Charge pump disabled */ +#define VLCD_2_60 (0x0200u) /* VLCD = 2.60V */ +#define VLCD_2_66 (0x0400u) /* VLCD = 2.66V */ +#define VLCD_2_72 (0x0600u) /* VLCD = 2.72V */ +#define VLCD_2_78 (0x0800u) /* VLCD = 2.78V */ +#define VLCD_2_84 (0x0A00u) /* VLCD = 2.84V */ +#define VLCD_2_90 (0x0C00u) /* VLCD = 2.90V */ +#define VLCD_2_96 (0x0E00u) /* VLCD = 2.96V */ +#define VLCD_3_02 (0x1000u) /* VLCD = 3.02V */ +#define VLCD_3_08 (0x1200u) /* VLCD = 3.08V */ +#define VLCD_3_14 (0x1400u) /* VLCD = 3.14V */ +#define VLCD_3_20 (0x1600u) /* VLCD = 3.20V */ +#define VLCD_3_26 (0x1800u) /* VLCD = 3.26V */ +#define VLCD_3_32 (0x1A00u) /* VLCD = 3.32V */ +#define VLCD_3_38 (0x1C00u) /* VLCD = 3.38V */ +#define VLCD_3_44 (0x1E00u) /* VLCD = 3.44V */ + +// LCDCPCTL0 +#define LCDS0 (0x0001u) /* LCD Segment 0 enable. */ +#define LCDS1 (0x0002u) /* LCD Segment 1 enable. */ +#define LCDS2 (0x0004u) /* LCD Segment 2 enable. */ +#define LCDS3 (0x0008u) /* LCD Segment 3 enable. */ +#define LCDS4 (0x0010u) /* LCD Segment 4 enable. */ +#define LCDS5 (0x0020u) /* LCD Segment 5 enable. */ +#define LCDS6 (0x0040u) /* LCD Segment 6 enable. */ +#define LCDS7 (0x0080u) /* LCD Segment 7 enable. */ +#define LCDS8 (0x0100u) /* LCD Segment 8 enable. */ +#define LCDS9 (0x0200u) /* LCD Segment 9 enable. */ +#define LCDS10 (0x0400u) /* LCD Segment 10 enable. */ +#define LCDS11 (0x0800u) /* LCD Segment 11 enable. */ +#define LCDS12 (0x1000u) /* LCD Segment 12 enable. */ +#define LCDS13 (0x2000u) /* LCD Segment 13 enable. */ +#define LCDS14 (0x4000u) /* LCD Segment 14 enable. */ +#define LCDS15 (0x8000u) /* LCD Segment 15 enable. */ + +// LCDCPCTL0 +#define LCDS0_L (0x0001u) /* LCD Segment 0 enable. */ +#define LCDS1_L (0x0002u) /* LCD Segment 1 enable. */ +#define LCDS2_L (0x0004u) /* LCD Segment 2 enable. */ +#define LCDS3_L (0x0008u) /* LCD Segment 3 enable. */ +#define LCDS4_L (0x0010u) /* LCD Segment 4 enable. */ +#define LCDS5_L (0x0020u) /* LCD Segment 5 enable. */ +#define LCDS6_L (0x0040u) /* LCD Segment 6 enable. */ +#define LCDS7_L (0x0080u) /* LCD Segment 7 enable. */ + +// LCDCPCTL0 +#define LCDS8_H (0x0001u) /* LCD Segment 8 enable. */ +#define LCDS9_H (0x0002u) /* LCD Segment 9 enable. */ +#define LCDS10_H (0x0004u) /* LCD Segment 10 enable. */ +#define LCDS11_H (0x0008u) /* LCD Segment 11 enable. */ +#define LCDS12_H (0x0010u) /* LCD Segment 12 enable. */ +#define LCDS13_H (0x0020u) /* LCD Segment 13 enable. */ +#define LCDS14_H (0x0040u) /* LCD Segment 14 enable. */ +#define LCDS15_H (0x0080u) /* LCD Segment 15 enable. */ + +// LCDCPCTL1 +#define LCDS16 (0x0001u) /* LCD Segment 16 enable. */ +#define LCDS17 (0x0002u) /* LCD Segment 17 enable. */ +#define LCDS18 (0x0004u) /* LCD Segment 18 enable. */ +#define LCDS19 (0x0008u) /* LCD Segment 19 enable. */ +#define LCDS20 (0x0010u) /* LCD Segment 20 enable. */ +#define LCDS21 (0x0020u) /* LCD Segment 21 enable. */ +#define LCDS22 (0x0040u) /* LCD Segment 22 enable. */ +#define LCDS23 (0x0080u) /* LCD Segment 23 enable. */ +#define LCDS24 (0x0100u) /* LCD Segment 24 enable. */ +#define LCDS25 (0x0200u) /* LCD Segment 25 enable. */ +#define LCDS26 (0x0400u) /* LCD Segment 26 enable. */ +#define LCDS27 (0x0800u) /* LCD Segment 27 enable. */ +#define LCDS28 (0x1000u) /* LCD Segment 28 enable. */ +#define LCDS29 (0x2000u) /* LCD Segment 29 enable. */ +#define LCDS30 (0x4000u) /* LCD Segment 30 enable. */ +#define LCDS31 (0x8000u) /* LCD Segment 31 enable. */ + +// LCDCPCTL1 +#define LCDS16_L (0x0001u) /* LCD Segment 16 enable. */ +#define LCDS17_L (0x0002u) /* LCD Segment 17 enable. */ +#define LCDS18_L (0x0004u) /* LCD Segment 18 enable. */ +#define LCDS19_L (0x0008u) /* LCD Segment 19 enable. */ +#define LCDS20_L (0x0010u) /* LCD Segment 20 enable. */ +#define LCDS21_L (0x0020u) /* LCD Segment 21 enable. */ +#define LCDS22_L (0x0040u) /* LCD Segment 22 enable. */ +#define LCDS23_L (0x0080u) /* LCD Segment 23 enable. */ + +// LCDCPCTL1 +#define LCDS24_H (0x0001u) /* LCD Segment 24 enable. */ +#define LCDS25_H (0x0002u) /* LCD Segment 25 enable. */ +#define LCDS26_H (0x0004u) /* LCD Segment 26 enable. */ +#define LCDS27_H (0x0008u) /* LCD Segment 27 enable. */ +#define LCDS28_H (0x0010u) /* LCD Segment 28 enable. */ +#define LCDS29_H (0x0020u) /* LCD Segment 29 enable. */ +#define LCDS30_H (0x0040u) /* LCD Segment 30 enable. */ +#define LCDS31_H (0x0080u) /* LCD Segment 31 enable. */ + +// LCDCPCTL2 +#define LCDS32 (0x0001u) /* LCD Segment 32 enable. */ +#define LCDS33 (0x0002u) /* LCD Segment 33 enable. */ +#define LCDS34 (0x0004u) /* LCD Segment 34 enable. */ +#define LCDS35 (0x0008u) /* LCD Segment 35 enable. */ +#define LCDS36 (0x0010u) /* LCD Segment 36 enable. */ +#define LCDS37 (0x0020u) /* LCD Segment 37 enable. */ +#define LCDS38 (0x0040u) /* LCD Segment 38 enable. */ +#define LCDS39 (0x0080u) /* LCD Segment 39 enable. */ +#define LCDS40 (0x0100u) /* LCD Segment 40 enable. */ +#define LCDS41 (0x0200u) /* LCD Segment 41 enable. */ +#define LCDS42 (0x0400u) /* LCD Segment 42 enable. */ +#define LCDS43 (0x0800u) /* LCD Segment 43 enable. */ +#define LCDS44 (0x1000u) /* LCD Segment 44 enable. */ +#define LCDS45 (0x2000u) /* LCD Segment 45 enable. */ +#define LCDS46 (0x4000u) /* LCD Segment 46 enable. */ +#define LCDS47 (0x8000u) /* LCD Segment 47 enable. */ + +// LCDCPCTL2 +#define LCDS32_L (0x0001u) /* LCD Segment 32 enable. */ +#define LCDS33_L (0x0002u) /* LCD Segment 33 enable. */ +#define LCDS34_L (0x0004u) /* LCD Segment 34 enable. */ +#define LCDS35_L (0x0008u) /* LCD Segment 35 enable. */ +#define LCDS36_L (0x0010u) /* LCD Segment 36 enable. */ +#define LCDS37_L (0x0020u) /* LCD Segment 37 enable. */ +#define LCDS38_L (0x0040u) /* LCD Segment 38 enable. */ +#define LCDS39_L (0x0080u) /* LCD Segment 39 enable. */ + +// LCDCPCTL2 +#define LCDS40_H (0x0001u) /* LCD Segment 40 enable. */ +#define LCDS41_H (0x0002u) /* LCD Segment 41 enable. */ +#define LCDS42_H (0x0004u) /* LCD Segment 42 enable. */ +#define LCDS43_H (0x0008u) /* LCD Segment 43 enable. */ +#define LCDS44_H (0x0010u) /* LCD Segment 44 enable. */ +#define LCDS45_H (0x0020u) /* LCD Segment 45 enable. */ +#define LCDS46_H (0x0040u) /* LCD Segment 46 enable. */ +#define LCDS47_H (0x0080u) /* LCD Segment 47 enable. */ + +// LCDCPCTL3 +#define LCDS48 (0x0001u) /* LCD Segment 48 enable. */ +#define LCDS49 (0x0002u) /* LCD Segment 49 enable. */ +#define LCDS50 (0x0004u) /* LCD Segment 50 enable. */ +#define LCDS51 (0x0008u) /* LCD Segment 51 enable. */ +#define LCDS52 (0x0010u) /* LCD Segment 52 enable. */ +#define LCDS53 (0x0020u) /* LCD Segment 53 enable. */ + +// LCDCPCTL3 +#define LCDS48_L (0x0001u) /* LCD Segment 48 enable. */ +#define LCDS49_L (0x0002u) /* LCD Segment 49 enable. */ +#define LCDS50_L (0x0004u) /* LCD Segment 50 enable. */ +#define LCDS51_L (0x0008u) /* LCD Segment 51 enable. */ +#define LCDS52_L (0x0010u) /* LCD Segment 52 enable. */ +#define LCDS53_L (0x0020u) /* LCD Segment 53 enable. */ + +// LCDCCPCTL +#define LCDCPDIS0 (0x0001u) /* LCD charge pump disable */ +#define LCDCPDIS1 (0x0002u) /* LCD charge pump disable */ +#define LCDCPDIS2 (0x0004u) /* LCD charge pump disable */ +#define LCDCPDIS3 (0x0008u) /* LCD charge pump disable */ +#define LCDCPDIS4 (0x0010u) /* LCD charge pump disable */ +#define LCDCPDIS5 (0x0020u) /* LCD charge pump disable */ +#define LCDCPDIS6 (0x0040u) /* LCD charge pump disable */ +#define LCDCPDIS7 (0x0080u) /* LCD charge pump disable */ +#define LCDCPCLKSYNC (0x8000u) /* LCD charge pump clock synchronization */ + +// LCDCCPCTL +#define LCDCPDIS0_L (0x0001u) /* LCD charge pump disable */ +#define LCDCPDIS1_L (0x0002u) /* LCD charge pump disable */ +#define LCDCPDIS2_L (0x0004u) /* LCD charge pump disable */ +#define LCDCPDIS3_L (0x0008u) /* LCD charge pump disable */ +#define LCDCPDIS4_L (0x0010u) /* LCD charge pump disable */ +#define LCDCPDIS5_L (0x0020u) /* LCD charge pump disable */ +#define LCDCPDIS6_L (0x0040u) /* LCD charge pump disable */ +#define LCDCPDIS7_L (0x0080u) /* LCD charge pump disable */ + +// LCDCCPCTL +#define LCDCPCLKSYNC_H (0x0080u) /* LCD charge pump clock synchronization */ + +#define OFS_LCDM1 (0x0020u) /* LCD Memory 1 */ +#define LCDMEM_ LCDM1 /* LCD Memory */ +#ifndef __IAR_SYSTEMS_ICC__ +#define LCDMEM LCDM1 /* LCD Memory (for assembler) */ +#else +#define LCDMEM ((char*) &LCDM1) /* LCD Memory (for C) */ +#endif +#define OFS_LCDM2 (0x0021u) /* LCD Memory 2 */ +#define OFS_LCDM3 (0x0022u) /* LCD Memory 3 */ +#define OFS_LCDM4 (0x0023u) /* LCD Memory 4 */ +#define OFS_LCDM5 (0x0024u) /* LCD Memory 5 */ +#define OFS_LCDM6 (0x0025u) /* LCD Memory 6 */ +#define OFS_LCDM7 (0x0026u) /* LCD Memory 7 */ +#define OFS_LCDM8 (0x0027u) /* LCD Memory 8 */ +#define OFS_LCDM9 (0x0028u) /* LCD Memory 9 */ +#define OFS_LCDM10 (0x0029u) /* LCD Memory 10 */ +#define OFS_LCDM11 (0x002Au) /* LCD Memory 11 */ +#define OFS_LCDM12 (0x002Bu) /* LCD Memory 12 */ +#define OFS_LCDM13 (0x002Cu) /* LCD Memory 13 */ +#define OFS_LCDM14 (0x002Du) /* LCD Memory 14 */ +#define OFS_LCDM15 (0x002Eu) /* LCD Memory 15 */ +#define OFS_LCDM16 (0x002Fu) /* LCD Memory 16 */ +#define OFS_LCDM17 (0x0030u) /* LCD Memory 17 */ +#define OFS_LCDM18 (0x0031u) /* LCD Memory 18 */ +#define OFS_LCDM19 (0x0032u) /* LCD Memory 19 */ +#define OFS_LCDM20 (0x0033u) /* LCD Memory 20 */ +#define OFS_LCDM21 (0x0034u) /* LCD Memory 21 */ +#define OFS_LCDM22 (0x0035u) /* LCD Memory 22 */ +#define OFS_LCDM23 (0x0036u) /* LCD Memory 23 */ +#define OFS_LCDM24 (0x0037u) /* LCD Memory 24 */ +#define OFS_LCDM25 (0x0038u) /* LCD Memory 25 */ +#define OFS_LCDM26 (0x0039u) /* LCD Memory 26 */ +#define OFS_LCDM27 (0x003Au) /* LCD Memory 27 */ +#define OFS_LCDM28 (0x003Bu) /* LCD Memory 28 */ +#define OFS_LCDM29 (0x003Cu) /* LCD Memory 29 */ +#define OFS_LCDM30 (0x003Du) /* LCD Memory 30 */ +#define OFS_LCDM31 (0x003Eu) /* LCD Memory 31 */ +#define OFS_LCDM32 (0x003Fu) /* LCD Memory 32 */ +#define OFS_LCDM33 (0x0040u) /* LCD Memory 33 */ +#define OFS_LCDM34 (0x0041u) /* LCD Memory 34 */ +#define OFS_LCDM35 (0x0042u) /* LCD Memory 35 */ +#define OFS_LCDM36 (0x0043u) /* LCD Memory 36 */ +#define OFS_LCDM37 (0x0044u) /* LCD Memory 37 */ +#define OFS_LCDM38 (0x0045u) /* LCD Memory 38 */ +#define OFS_LCDM39 (0x0046u) /* LCD Memory 39 */ +#define OFS_LCDM40 (0x0047u) /* LCD Memory 40 */ + +#define OFS_LCDBM1 (0x0040u) /* LCD Blinking Memory 1 */ +#define LCDBMEM_ LCDBM1 /* LCD Blinking Memory */ +#ifndef __IAR_SYSTEMS_ICC__ +#define LCDBMEM (LCDBM1) /* LCD Blinking Memory (for assembler) */ +#else +#define LCDBMEM ((char*) &LCDBM1) /* LCD Blinking Memory (for C) */ +#endif +#define OFS_LCDBM2 (0x0041u) /* LCD Blinking Memory 2 */ +#define OFS_LCDBM3 (0x0042u) /* LCD Blinking Memory 3 */ +#define OFS_LCDBM4 (0x0043u) /* LCD Blinking Memory 4 */ +#define OFS_LCDBM5 (0x0044u) /* LCD Blinking Memory 5 */ +#define OFS_LCDBM6 (0x0045u) /* LCD Blinking Memory 6 */ +#define OFS_LCDBM7 (0x0046u) /* LCD Blinking Memory 7 */ +#define OFS_LCDBM8 (0x0047u) /* LCD Blinking Memory 8 */ +#define OFS_LCDBM9 (0x0048u) /* LCD Blinking Memory 9 */ +#define OFS_LCDBM10 (0x0049u) /* LCD Blinking Memory 10 */ +#define OFS_LCDBM11 (0x004Au) /* LCD Blinking Memory 11 */ +#define OFS_LCDBM12 (0x004Bu) /* LCD Blinking Memory 12 */ +#define OFS_LCDBM13 (0x004Cu) /* LCD Blinking Memory 13 */ +#define OFS_LCDBM14 (0x004Du) /* LCD Blinking Memory 14 */ +#define OFS_LCDBM15 (0x004Eu) /* LCD Blinking Memory 15 */ +#define OFS_LCDBM16 (0x004Fu) /* LCD Blinking Memory 16 */ +#define OFS_LCDBM17 (0x0050u) /* LCD Blinking Memory 17 */ +#define OFS_LCDBM18 (0x0051u) /* LCD Blinking Memory 18 */ +#define OFS_LCDBM19 (0x0052u) /* LCD Blinking Memory 19 */ +#define OFS_LCDBM20 (0x0053u) /* LCD Blinking Memory 20 */ + +/* LCDCIV Definitions */ +#define LCDCIV_NONE (0x0000u) /* No Interrupt pending */ +#define LCDCIV_LCDNOCAPIFG (0x0002u) /* No capacitor connected */ +#define LCDCIV_LCDCLKOFFIFG (0x0004u) /* Blink, segments off */ +#define LCDCIV_LCDCLKONIFG (0x0006u) /* Blink, segments on */ +#define LCDCIV_LCDFRMIFG (0x0008u) /* Frame interrupt */ + +#endif +/************************************************************ +* Memory Protection Unit +************************************************************/ +#ifdef __MSP430_HAS_MPU__ /* Definition to show that Module is available */ + +#define OFS_MPUCTL0 (0x0000u) /* MPU Control Register 0 */ +#define OFS_MPUCTL0_L OFS_MPUCTL0 +#define OFS_MPUCTL0_H OFS_MPUCTL0+1 +#define OFS_MPUCTL1 (0x0002u) /* MPU Control Register 1 */ +#define OFS_MPUCTL1_L OFS_MPUCTL1 +#define OFS_MPUCTL1_H OFS_MPUCTL1+1 +#define OFS_MPUSEGB2 (0x0004u) /* MPU Segmentation Border 2 Register */ +#define OFS_MPUSEGB2_L OFS_MPUSEGB2 +#define OFS_MPUSEGB2_H OFS_MPUSEGB2+1 +#define OFS_MPUSEGB1 (0x0006u) /* MPU Segmentation Border 1 Register */ +#define OFS_MPUSEGB1_L OFS_MPUSEGB1 +#define OFS_MPUSEGB1_H OFS_MPUSEGB1+1 +#define OFS_MPUSAM (0x0008u) /* MPU Access Management Register */ +#define OFS_MPUSAM_L OFS_MPUSAM +#define OFS_MPUSAM_H OFS_MPUSAM+1 +#define OFS_MPUIPC0 (0x000Au) /* MPU IP Control 0 Register */ +#define OFS_MPUIPC0_L OFS_MPUIPC0 +#define OFS_MPUIPC0_H OFS_MPUIPC0+1 +#define OFS_MPUIPSEGB2 (0x000Cu) /* MPU IP Segment Border 2 Register */ +#define OFS_MPUIPSEGB2_L OFS_MPUIPSEGB2 +#define OFS_MPUIPSEGB2_H OFS_MPUIPSEGB2+1 +#define OFS_MPUIPSEGB1 (0x000Eu) /* MPU IP Segment Border 1 Register */ +#define OFS_MPUIPSEGB1_L OFS_MPUIPSEGB1 +#define OFS_MPUIPSEGB1_H OFS_MPUIPSEGB1+1 + +/* MPUCTL0 Control Bits */ +#define MPUENA (0x0001u) /* MPU Enable */ +#define MPULOCK (0x0002u) /* MPU Lock */ +#define MPUSEGIE (0x0010u) /* MPU Enable NMI on Segment violation */ + +/* MPUCTL0 Control Bits */ +#define MPUENA_L (0x0001u) /* MPU Enable */ +#define MPULOCK_L (0x0002u) /* MPU Lock */ +#define MPUSEGIE_L (0x0010u) /* MPU Enable NMI on Segment violation */ + +#define MPUPW (0xA500u) /* MPU Access Password */ +#define MPUPW_H (0xA5) /* MPU Access Password */ + +/* MPUCTL1 Control Bits */ +#define MPUSEG1IFG (0x0001u) /* MPU Main Memory Segment 1 violation interupt flag */ +#define MPUSEG2IFG (0x0002u) /* MPU Main Memory Segment 2 violation interupt flag */ +#define MPUSEG3IFG (0x0004u) /* MPU Main Memory Segment 3 violation interupt flag */ +#define MPUSEGIIFG (0x0008u) /* MPU Info Memory Segment violation interupt flag */ +#define MPUSEGIPIFG (0x0010u) /* MPU IP Memory Segment violation interupt flag */ + +/* MPUCTL1 Control Bits */ +#define MPUSEG1IFG_L (0x0001u) /* MPU Main Memory Segment 1 violation interupt flag */ +#define MPUSEG2IFG_L (0x0002u) /* MPU Main Memory Segment 2 violation interupt flag */ +#define MPUSEG3IFG_L (0x0004u) /* MPU Main Memory Segment 3 violation interupt flag */ +#define MPUSEGIIFG_L (0x0008u) /* MPU Info Memory Segment violation interupt flag */ +#define MPUSEGIPIFG_L (0x0010u) /* MPU IP Memory Segment violation interupt flag */ + +/* MPUSEGB2 Control Bits */ + +/* MPUSEGB2 Control Bits */ + +/* MPUSEGB2 Control Bits */ + +/* MPUSEGB1 Control Bits */ + +/* MPUSEGB1 Control Bits */ + +/* MPUSEGB1 Control Bits */ + +/* MPUSAM Control Bits */ +#define MPUSEG1RE (0x0001u) /* MPU Main memory Segment 1 Read enable */ +#define MPUSEG1WE (0x0002u) /* MPU Main memory Segment 1 Write enable */ +#define MPUSEG1XE (0x0004u) /* MPU Main memory Segment 1 Execute enable */ +#define MPUSEG1VS (0x0008u) /* MPU Main memory Segment 1 Violation select */ +#define MPUSEG2RE (0x0010u) /* MPU Main memory Segment 2 Read enable */ +#define MPUSEG2WE (0x0020u) /* MPU Main memory Segment 2 Write enable */ +#define MPUSEG2XE (0x0040u) /* MPU Main memory Segment 2 Execute enable */ +#define MPUSEG2VS (0x0080u) /* MPU Main memory Segment 2 Violation select */ +#define MPUSEG3RE (0x0100u) /* MPU Main memory Segment 3 Read enable */ +#define MPUSEG3WE (0x0200u) /* MPU Main memory Segment 3 Write enable */ +#define MPUSEG3XE (0x0400u) /* MPU Main memory Segment 3 Execute enable */ +#define MPUSEG3VS (0x0800u) /* MPU Main memory Segment 3 Violation select */ +#define MPUSEGIRE (0x1000u) /* MPU Info memory Segment Read enable */ +#define MPUSEGIWE (0x2000u) /* MPU Info memory Segment Write enable */ +#define MPUSEGIXE (0x4000u) /* MPU Info memory Segment Execute enable */ +#define MPUSEGIVS (0x8000u) /* MPU Info memory Segment Violation select */ + +/* MPUSAM Control Bits */ +#define MPUSEG1RE_L (0x0001u) /* MPU Main memory Segment 1 Read enable */ +#define MPUSEG1WE_L (0x0002u) /* MPU Main memory Segment 1 Write enable */ +#define MPUSEG1XE_L (0x0004u) /* MPU Main memory Segment 1 Execute enable */ +#define MPUSEG1VS_L (0x0008u) /* MPU Main memory Segment 1 Violation select */ +#define MPUSEG2RE_L (0x0010u) /* MPU Main memory Segment 2 Read enable */ +#define MPUSEG2WE_L (0x0020u) /* MPU Main memory Segment 2 Write enable */ +#define MPUSEG2XE_L (0x0040u) /* MPU Main memory Segment 2 Execute enable */ +#define MPUSEG2VS_L (0x0080u) /* MPU Main memory Segment 2 Violation select */ + +/* MPUSAM Control Bits */ +#define MPUSEG3RE_H (0x0001u) /* MPU Main memory Segment 3 Read enable */ +#define MPUSEG3WE_H (0x0002u) /* MPU Main memory Segment 3 Write enable */ +#define MPUSEG3XE_H (0x0004u) /* MPU Main memory Segment 3 Execute enable */ +#define MPUSEG3VS_H (0x0008u) /* MPU Main memory Segment 3 Violation select */ +#define MPUSEGIRE_H (0x0010u) /* MPU Info memory Segment Read enable */ +#define MPUSEGIWE_H (0x0020u) /* MPU Info memory Segment Write enable */ +#define MPUSEGIXE_H (0x0040u) /* MPU Info memory Segment Execute enable */ +#define MPUSEGIVS_H (0x0080u) /* MPU Info memory Segment Violation select */ + +/* MPUIPC0 Control Bits */ +#define MPUIPVS (0x0020u) /* MPU MPU IP protection segment Violation Select */ +#define MPUIPENA (0x0040u) /* MPU MPU IP Protection Enable */ +#define MPUIPLOCK (0x0080u) /* MPU IP Protection Lock */ + +/* MPUIPC0 Control Bits */ +#define MPUIPVS_L (0x0020u) /* MPU MPU IP protection segment Violation Select */ +#define MPUIPENA_L (0x0040u) /* MPU MPU IP Protection Enable */ +#define MPUIPLOCK_L (0x0080u) /* MPU IP Protection Lock */ + +/* MPUIPSEGB2 Control Bits */ + +/* MPUIPSEGB2 Control Bits */ + +/* MPUIPSEGB2 Control Bits */ + +/* MPUIPSEGB1 Control Bits */ + +/* MPUIPSEGB1 Control Bits */ + +/* MPUIPSEGB1 Control Bits */ + +#endif +/************************************************************ +* HARDWARE MULTIPLIER 32Bit +************************************************************/ +#ifdef __MSP430_HAS_MPY32__ /* Definition to show that Module is available */ + +#define OFS_MPY (0x0000u) /* Multiply Unsigned/Operand 1 */ +#define OFS_MPY_L OFS_MPY +#define OFS_MPY_H OFS_MPY+1 +#define OFS_MPYS (0x0002u) /* Multiply Signed/Operand 1 */ +#define OFS_MPYS_L OFS_MPYS +#define OFS_MPYS_H OFS_MPYS+1 +#define OFS_MAC (0x0004u) /* Multiply Unsigned and Accumulate/Operand 1 */ +#define OFS_MAC_L OFS_MAC +#define OFS_MAC_H OFS_MAC+1 +#define OFS_MACS (0x0006u) /* Multiply Signed and Accumulate/Operand 1 */ +#define OFS_MACS_L OFS_MACS +#define OFS_MACS_H OFS_MACS+1 +#define OFS_OP2 (0x0008u) /* Operand 2 */ +#define OFS_OP2_L OFS_OP2 +#define OFS_OP2_H OFS_OP2+1 +#define OFS_RESLO (0x000Au) /* Result Low Word */ +#define OFS_RESLO_L OFS_RESLO +#define OFS_RESLO_H OFS_RESLO+1 +#define OFS_RESHI (0x000Cu) /* Result High Word */ +#define OFS_RESHI_L OFS_RESHI +#define OFS_RESHI_H OFS_RESHI+1 +#define OFS_SUMEXT (0x000Eu) /* Sum Extend */ +#define OFS_SUMEXT_L OFS_SUMEXT +#define OFS_SUMEXT_H OFS_SUMEXT+1 +#define OFS_MPY32CTL0 (0x002Cu) +#define OFS_MPY32CTL0_L OFS_MPY32CTL0 +#define OFS_MPY32CTL0_H OFS_MPY32CTL0+1 + +#define OFS_MPY32L (0x0010u) /* 32-bit operand 1 - multiply - low word */ +#define OFS_MPY32L_L OFS_MPY32L +#define OFS_MPY32L_H OFS_MPY32L+1 +#define OFS_MPY32H (0x0012u) /* 32-bit operand 1 - multiply - high word */ +#define OFS_MPY32H_L OFS_MPY32H +#define OFS_MPY32H_H OFS_MPY32H+1 +#define OFS_MPYS32L (0x0014u) /* 32-bit operand 1 - signed multiply - low word */ +#define OFS_MPYS32L_L OFS_MPYS32L +#define OFS_MPYS32L_H OFS_MPYS32L+1 +#define OFS_MPYS32H (0x0016u) /* 32-bit operand 1 - signed multiply - high word */ +#define OFS_MPYS32H_L OFS_MPYS32H +#define OFS_MPYS32H_H OFS_MPYS32H+1 +#define OFS_MAC32L (0x0018u) /* 32-bit operand 1 - multiply accumulate - low word */ +#define OFS_MAC32L_L OFS_MAC32L +#define OFS_MAC32L_H OFS_MAC32L+1 +#define OFS_MAC32H (0x001Au) /* 32-bit operand 1 - multiply accumulate - high word */ +#define OFS_MAC32H_L OFS_MAC32H +#define OFS_MAC32H_H OFS_MAC32H+1 +#define OFS_MACS32L (0x001Cu) /* 32-bit operand 1 - signed multiply accumulate - low word */ +#define OFS_MACS32L_L OFS_MACS32L +#define OFS_MACS32L_H OFS_MACS32L+1 +#define OFS_MACS32H (0x001Eu) /* 32-bit operand 1 - signed multiply accumulate - high word */ +#define OFS_MACS32H_L OFS_MACS32H +#define OFS_MACS32H_H OFS_MACS32H+1 +#define OFS_OP2L (0x0020u) /* 32-bit operand 2 - low word */ +#define OFS_OP2L_L OFS_OP2L +#define OFS_OP2L_H OFS_OP2L+1 +#define OFS_OP2H (0x0022u) /* 32-bit operand 2 - high word */ +#define OFS_OP2H_L OFS_OP2H +#define OFS_OP2H_H OFS_OP2H+1 +#define OFS_RES0 (0x0024u) /* 32x32-bit result 0 - least significant word */ +#define OFS_RES0_L OFS_RES0 +#define OFS_RES0_H OFS_RES0+1 +#define OFS_RES1 (0x0026u) /* 32x32-bit result 1 */ +#define OFS_RES1_L OFS_RES1 +#define OFS_RES1_H OFS_RES1+1 +#define OFS_RES2 (0x0028u) /* 32x32-bit result 2 */ +#define OFS_RES2_L OFS_RES2 +#define OFS_RES2_H OFS_RES2+1 +#define OFS_RES3 (0x002Au) /* 32x32-bit result 3 - most significant word */ +#define OFS_RES3_L OFS_RES3 +#define OFS_RES3_H OFS_RES3+1 +#define OFS_SUMEXT (0x000Eu) +#define OFS_SUMEXT_L OFS_SUMEXT +#define OFS_SUMEXT_H OFS_SUMEXT+1 +#define OFS_MPY32CTL0 (0x002Cu) /* MPY32 Control Register 0 */ +#define OFS_MPY32CTL0_L OFS_MPY32CTL0 +#define OFS_MPY32CTL0_H OFS_MPY32CTL0+1 + +#define MPY_B MPY_L /* Multiply Unsigned/Operand 1 (Byte Access) */ +#define MPYS_B MPYS_L /* Multiply Signed/Operand 1 (Byte Access) */ +#define MAC_B MAC_L /* Multiply Unsigned and Accumulate/Operand 1 (Byte Access) */ +#define MACS_B MACS_L /* Multiply Signed and Accumulate/Operand 1 (Byte Access) */ +#define OP2_B OP2_L /* Operand 2 (Byte Access) */ +#define MPY32L_B MPY32L_L /* 32-bit operand 1 - multiply - low word (Byte Access) */ +#define MPY32H_B MPY32H_L /* 32-bit operand 1 - multiply - high word (Byte Access) */ +#define MPYS32L_B MPYS32L_L /* 32-bit operand 1 - signed multiply - low word (Byte Access) */ +#define MPYS32H_B MPYS32H_L /* 32-bit operand 1 - signed multiply - high word (Byte Access) */ +#define MAC32L_B MAC32L_L /* 32-bit operand 1 - multiply accumulate - low word (Byte Access) */ +#define MAC32H_B MAC32H_L /* 32-bit operand 1 - multiply accumulate - high word (Byte Access) */ +#define MACS32L_B MACS32L_L /* 32-bit operand 1 - signed multiply accumulate - low word (Byte Access) */ +#define MACS32H_B MACS32H_L /* 32-bit operand 1 - signed multiply accumulate - high word (Byte Access) */ +#define OP2L_B OP2L_L /* 32-bit operand 2 - low word (Byte Access) */ +#define OP2H_B OP2H_L /* 32-bit operand 2 - high word (Byte Access) */ + +/* MPY32CTL0 Control Bits */ +#define MPYC (0x0001u) /* Carry of the multiplier */ +//#define RESERVED (0x0002u) /* Reserved */ +#define MPYFRAC (0x0004u) /* Fractional mode */ +#define MPYSAT (0x0008u) /* Saturation mode */ +#define MPYM0 (0x0010u) /* Multiplier mode Bit:0 */ +#define MPYM1 (0x0020u) /* Multiplier mode Bit:1 */ +#define OP1_32 (0x0040u) /* Bit-width of operand 1 0:16Bit / 1:32Bit */ +#define OP2_32 (0x0080u) /* Bit-width of operand 2 0:16Bit / 1:32Bit */ +#define MPYDLYWRTEN (0x0100u) /* Delayed write enable */ +#define MPYDLY32 (0x0200u) /* Delayed write mode */ + +/* MPY32CTL0 Control Bits */ +#define MPYC_L (0x0001u) /* Carry of the multiplier */ +//#define RESERVED (0x0002u) /* Reserved */ +#define MPYFRAC_L (0x0004u) /* Fractional mode */ +#define MPYSAT_L (0x0008u) /* Saturation mode */ +#define MPYM0_L (0x0010u) /* Multiplier mode Bit:0 */ +#define MPYM1_L (0x0020u) /* Multiplier mode Bit:1 */ +#define OP1_32_L (0x0040u) /* Bit-width of operand 1 0:16Bit / 1:32Bit */ +#define OP2_32_L (0x0080u) /* Bit-width of operand 2 0:16Bit / 1:32Bit */ + +/* MPY32CTL0 Control Bits */ +//#define RESERVED (0x0002u) /* Reserved */ +#define MPYDLYWRTEN_H (0x0001u) /* Delayed write enable */ +#define MPYDLY32_H (0x0002u) /* Delayed write mode */ + +#define MPYM_0 (0x0000u) /* Multiplier mode: MPY */ +#define MPYM_1 (0x0010u) /* Multiplier mode: MPYS */ +#define MPYM_2 (0x0020u) /* Multiplier mode: MAC */ +#define MPYM_3 (0x0030u) /* Multiplier mode: MACS */ +#define MPYM__MPY (0x0000u) /* Multiplier mode: MPY */ +#define MPYM__MPYS (0x0010u) /* Multiplier mode: MPYS */ +#define MPYM__MAC (0x0020u) /* Multiplier mode: MAC */ +#define MPYM__MACS (0x0030u) /* Multiplier mode: MACS */ + +#endif +/************************************************************ +* PMM - Power Management System for FRAM +************************************************************/ +#ifdef __MSP430_HAS_PMM_FRAM__ /* Definition to show that Module is available */ + +#define OFS_PMMCTL0 (0x0000u) /* PMM Control 0 */ +#define OFS_PMMCTL0_L OFS_PMMCTL0 +#define OFS_PMMCTL0_H OFS_PMMCTL0+1 +#define OFS_PMMCTL1 (0x0002u) /* PMM Control 1 */ +#define OFS_PMMIFG (0x000Au) /* PMM Interrupt Flag */ +#define OFS_PMMIFG_L OFS_PMMIFG +#define OFS_PMMIFG_H OFS_PMMIFG+1 +#define OFS_PM5CTL0 (0x0010u) /* PMM Power Mode 5 Control Register 0 */ +#define OFS_PM5CTL0_L OFS_PM5CTL0 +#define OFS_PM5CTL0_H OFS_PM5CTL0+1 + +#define PMMPW (0xA500u) /* PMM Register Write Password */ +#define PMMPW_H (0xA5) /* PMM Register Write Password for high word access */ + +/* PMMCTL0 Control Bits */ +#define PMMSWBOR (0x0004u) /* PMM Software BOR */ +#define PMMSWPOR (0x0008u) /* PMM Software POR */ +#define PMMREGOFF (0x0010u) /* PMM Turn Regulator off */ +#define SVSHE (0x0040u) /* SVS high side enable */ +#define PMMLPRST (0x0080u) /* PMM Low-Power Reset Enable */ + +/* PMMCTL0 Control Bits */ +#define PMMSWBOR_L (0x0004u) /* PMM Software BOR */ +#define PMMSWPOR_L (0x0008u) /* PMM Software POR */ +#define PMMREGOFF_L (0x0010u) /* PMM Turn Regulator off */ +#define SVSHE_L (0x0040u) /* SVS high side enable */ +#define PMMLPRST_L (0x0080u) /* PMM Low-Power Reset Enable */ + +/* PMMCTL1 Control Bits */ +#define PMMLPSVEN (0x0002u) /* PMM Low-Power Supervision Enable */ +#define PMMLPRNG0 (0x0004u) /* PMM Load Range Control overwrite for LPM2, LPM3 and LPM4 Bit: 0 */ +#define PMMLPRNG1 (0x0008u) /* PMM Load Range Control overwrite for LPM2, LPM3 and LPM4 Bit: 1 */ +#define PMMAMRNG0 (0x0010u) /* Load Range Control overwrite for AM, LPM0 and LPM1 Bit: 0 */ +#define PMMAMRNG1 (0x0020u) /* Load Range Control overwrite for AM, LPM0 and LPM1 Bit: 1 */ +#define PMMAMRNG2 (0x0040u) /* Load Range Control overwrite for AM, LPM0 and LPM1 Bit: 2 */ +#define PMMAMRNG3 (0x0080u) /* Load Range Control overwrite for AM, LPM0 and LPM1 Bit: 3 */ +#define PMMCTL1KEY (0xCC00u) /* PMM PMMCTL1 Register Write Password */ + +/* PMMIFG Control Bits */ +#define PMMBORIFG (0x0100u) /* PMM Software BOR interrupt flag */ +#define PMMRSTIFG (0x0200u) /* PMM RESET pin interrupt flag */ +#define PMMPORIFG (0x0400u) /* PMM Software POR interrupt flag */ +#define SVSHIFG (0x2000u) /* SVS low side interrupt flag */ +#define PMMLPM5IFG (0x8000u) /* LPM5 indication Flag */ + +/* PMMIFG Control Bits */ +#define PMMBORIFG_H (0x0001u) /* PMM Software BOR interrupt flag */ +#define PMMRSTIFG_H (0x0002u) /* PMM RESET pin interrupt flag */ +#define PMMPORIFG_H (0x0004u) /* PMM Software POR interrupt flag */ +#define SVSHIFG_H (0x0020u) /* SVS low side interrupt flag */ +#define PMMLPM5IFG_H (0x0080u) /* LPM5 indication Flag */ + +/* PM5CTL0 Power Mode 5 Control Bits */ +#define LOCKLPM5 (0x0001u) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */ + +/* PM5CTL0 Power Mode 5 Control Bits */ +#define LOCKLPM5_L (0x0001u) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */ + + +#endif +/************************************************************ +* DIGITAL I/O Port1/2 Pull up / Pull down Resistors +************************************************************/ +#ifdef __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORTA_R__ /* Definition to show that Module is available */ + +#define OFS_PAIN (0x0000u) /* Port A Input */ +#define OFS_PAIN_L OFS_PAIN +#define OFS_PAIN_H OFS_PAIN+1 +#define OFS_PAOUT (0x0002u) /* Port A Output */ +#define OFS_PAOUT_L OFS_PAOUT +#define OFS_PAOUT_H OFS_PAOUT+1 +#define OFS_PADIR (0x0004u) /* Port A Direction */ +#define OFS_PADIR_L OFS_PADIR +#define OFS_PADIR_H OFS_PADIR+1 +#define OFS_PAREN (0x0006u) /* Port A Resistor Enable */ +#define OFS_PAREN_L OFS_PAREN +#define OFS_PAREN_H OFS_PAREN+1 +#define OFS_PASEL0 (0x000Au) /* Port A Selection 0 */ +#define OFS_PASEL0_L OFS_PASEL0 +#define OFS_PASEL0_H OFS_PASEL0+1 +#define OFS_PASEL1 (0x000Cu) /* Port A Selection 1 */ +#define OFS_PASEL1_L OFS_PASEL1 +#define OFS_PASEL1_H OFS_PASEL1+1 +#define OFS_PASELC (0x0016u) /* Port A Complement Selection */ +#define OFS_PASELC_L OFS_PASELC +#define OFS_PASELC_H OFS_PASELC+1 +#define OFS_PAIES (0x0018u) /* Port A Interrupt Edge Select */ +#define OFS_PAIES_L OFS_PAIES +#define OFS_PAIES_H OFS_PAIES+1 +#define OFS_PAIE (0x001Au) /* Port A Interrupt Enable */ +#define OFS_PAIE_L OFS_PAIE +#define OFS_PAIE_H OFS_PAIE+1 +#define OFS_PAIFG (0x001Cu) /* Port A Interrupt Flag */ +#define OFS_PAIFG_L OFS_PAIFG +#define OFS_PAIFG_H OFS_PAIFG+1 + + +#define OFS_P1IN (0x0000u) +#define OFS_P1OUT (0x0002u) +#define OFS_P1DIR (0x0004u) +#define OFS_P1REN (0x0006u) +#define OFS_P1SEL0 (0x000Au) +#define OFS_P1SEL1 (0x000Cu) +#define OFS_P1SELC (0x0016u) +#define OFS_P1IV (0x000Eu) /* Port 1 Interrupt Vector Word */ +#define OFS_P1IES (0x0018u) +#define OFS_P1IE (0x001Au) +#define OFS_P1IFG (0x001Cu) +#define OFS_P2IN (0x0001u) +#define OFS_P2OUT (0x0003u) +#define OFS_P2DIR (0x0005u) +#define OFS_P2REN (0x0007u) +#define OFS_P2SEL0 (0x000Bu) +#define OFS_P2SEL1 (0x000Du) +#define OFS_P2SELC (0x0017u) +#define OFS_P2IV (0x001Eu) /* Port 2 Interrupt Vector Word */ +#define OFS_P2IES (0x0019u) +#define OFS_P2IE (0x001Bu) +#define OFS_P2IFG (0x001du) +#define P1IN (PAIN_L) /* Port 1 Input */ +#define P1OUT (PAOUT_L) /* Port 1 Output */ +#define P1DIR (PADIR_L) /* Port 1 Direction */ +#define P1REN (PAREN_L) /* Port 1 Resistor Enable */ +#define P1SEL0 (PASEL0_L) /* Port 1 Selection 0 */ +#define P1SEL1 (PASEL1_L) /* Port 1 Selection 1 */ +#define P1SELC (PASELC_L) /* Port 1 Complement Selection */ +#define P1IES (PAIES_L) /* Port 1 Interrupt Edge Select */ +#define P1IE (PAIE_L) /* Port 1 Interrupt Enable */ +#define P1IFG (PAIFG_L) /* Port 1 Interrupt Flag */ + +//Definitions for P1IV +#define P1IV_NONE (0x0000u) /* No Interrupt pending */ +#define P1IV_P1IFG0 (0x0002u) /* P1IV P1IFG.0 */ +#define P1IV_P1IFG1 (0x0004u) /* P1IV P1IFG.1 */ +#define P1IV_P1IFG2 (0x0006u) /* P1IV P1IFG.2 */ +#define P1IV_P1IFG3 (0x0008u) /* P1IV P1IFG.3 */ +#define P1IV_P1IFG4 (0x000Au) /* P1IV P1IFG.4 */ +#define P1IV_P1IFG5 (0x000Cu) /* P1IV P1IFG.5 */ +#define P1IV_P1IFG6 (0x000Eu) /* P1IV P1IFG.6 */ +#define P1IV_P1IFG7 (0x0010u) /* P1IV P1IFG.7 */ + +#define P2IN (PAIN_H) /* Port 2 Input */ +#define P2OUT (PAOUT_H) /* Port 2 Output */ +#define P2DIR (PADIR_H) /* Port 2 Direction */ +#define P2REN (PAREN_H) /* Port 2 Resistor Enable */ +#define P2SEL0 (PASEL0_H) /* Port 2 Selection 0 */ +#define P2SEL1 (PASEL1_H) /* Port 2 Selection 1 */ +#define P2SELC (PASELC_H) /* Port 2 Complement Selection */ +#define P2IES (PAIES_H) /* Port 2 Interrupt Edge Select */ +#define P2IE (PAIE_H) /* Port 2 Interrupt Enable */ +#define P2IFG (PAIFG_H) /* Port 2 Interrupt Flag */ + +//Definitions for P2IV +#define P2IV_NONE (0x0000u) /* No Interrupt pending */ +#define P2IV_P2IFG0 (0x0002u) /* P2IV P2IFG.0 */ +#define P2IV_P2IFG1 (0x0004u) /* P2IV P2IFG.1 */ +#define P2IV_P2IFG2 (0x0006u) /* P2IV P2IFG.2 */ +#define P2IV_P2IFG3 (0x0008u) /* P2IV P2IFG.3 */ +#define P2IV_P2IFG4 (0x000Au) /* P2IV P2IFG.4 */ +#define P2IV_P2IFG5 (0x000Cu) /* P2IV P2IFG.5 */ +#define P2IV_P2IFG6 (0x000Eu) /* P2IV P2IFG.6 */ +#define P2IV_P2IFG7 (0x0010u) /* P2IV P2IFG.7 */ + + +#endif +#endif +#endif +/************************************************************ +* DIGITAL I/O Port3/4 Pull up / Pull down Resistors +************************************************************/ +#ifdef __MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORT4_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORTB_R__ /* Definition to show that Module is available */ + +#define OFS_PBIN (0x0000u) /* Port B Input */ +#define OFS_PBIN_L OFS_PBIN +#define OFS_PBIN_H OFS_PBIN+1 +#define OFS_PBOUT (0x0002u) /* Port B Output */ +#define OFS_PBOUT_L OFS_PBOUT +#define OFS_PBOUT_H OFS_PBOUT+1 +#define OFS_PBDIR (0x0004u) /* Port B Direction */ +#define OFS_PBDIR_L OFS_PBDIR +#define OFS_PBDIR_H OFS_PBDIR+1 +#define OFS_PBREN (0x0006u) /* Port B Resistor Enable */ +#define OFS_PBREN_L OFS_PBREN +#define OFS_PBREN_H OFS_PBREN+1 +#define OFS_PBSEL0 (0x000Au) /* Port B Selection 0 */ +#define OFS_PBSEL0_L OFS_PBSEL0 +#define OFS_PBSEL0_H OFS_PBSEL0+1 +#define OFS_PBSEL1 (0x000Cu) /* Port B Selection 1 */ +#define OFS_PBSEL1_L OFS_PBSEL1 +#define OFS_PBSEL1_H OFS_PBSEL1+1 +#define OFS_PBSELC (0x0016u) /* Port B Complement Selection */ +#define OFS_PBSELC_L OFS_PBSELC +#define OFS_PBSELC_H OFS_PBSELC+1 +#define OFS_PBIES (0x0018u) /* Port B Interrupt Edge Select */ +#define OFS_PBIES_L OFS_PBIES +#define OFS_PBIES_H OFS_PBIES+1 +#define OFS_PBIE (0x001Au) /* Port B Interrupt Enable */ +#define OFS_PBIE_L OFS_PBIE +#define OFS_PBIE_H OFS_PBIE+1 +#define OFS_PBIFG (0x001Cu) /* Port B Interrupt Flag */ +#define OFS_PBIFG_L OFS_PBIFG +#define OFS_PBIFG_H OFS_PBIFG+1 + + +#define OFS_P3IN (0x0000u) +#define OFS_P3OUT (0x0002u) +#define OFS_P3DIR (0x0004u) +#define OFS_P3REN (0x0006u) +#define OFS_P3SEL0 (0x000Au) +#define OFS_P3SEL1 (0x000Cu) +#define OFS_P3SELC (0x0016u) +#define OFS_P3IV (0x000Eu) /* Port 3 Interrupt Vector Word */ +#define OFS_P3IES (0x0018u) +#define OFS_P3IE (0x001Au) +#define OFS_P3IFG (0x001Cu) +#define OFS_P4IN (0x0001u) +#define OFS_P4OUT (0x0003u) +#define OFS_P4DIR (0x0005u) +#define OFS_P4REN (0x0007u) +#define OFS_P4SEL0 (0x000Bu) +#define OFS_P4SEL1 (0x000Du) +#define OFS_P4SELC (0x0017u) +#define OFS_P4IV (0x001Eu) /* Port 4 Interrupt Vector Word */ +#define OFS_P4IES (0x0019u) +#define OFS_P4IE (0x001Bu) +#define OFS_P4IFG (0x001du) +#define P3IN (PBIN_L) /* Port 3 Input */ +#define P3OUT (PBOUT_L) /* Port 3 Output */ +#define P3DIR (PBDIR_L) /* Port 3 Direction */ +#define P3REN (PBREN_L) /* Port 3 Resistor Enable */ +#define P3SEL0 (PBSEL0_L) /* Port 3 Selection 0 */ +#define P3SEL1 (PBSEL1_L) /* Port 3 Selection 1 */ +#define P3SELC (PBSELC_L) /* Port 3 Complement Selection */ +#define P3IES (PBIES_L) /* Port 3 Interrupt Edge Select */ +#define P3IE (PBIE_L) /* Port 3 Interrupt Enable */ +#define P3IFG (PBIFG_L) /* Port 3 Interrupt Flag */ + +//Definitions for P3IV +#define P3IV_NONE (0x0000u) /* No Interrupt pending */ +#define P3IV_P3IFG0 (0x0002u) /* P3IV P3IFG.0 */ +#define P3IV_P3IFG1 (0x0004u) /* P3IV P3IFG.1 */ +#define P3IV_P3IFG2 (0x0006u) /* P3IV P3IFG.2 */ +#define P3IV_P3IFG3 (0x0008u) /* P3IV P3IFG.3 */ +#define P3IV_P3IFG4 (0x000Au) /* P3IV P3IFG.4 */ +#define P3IV_P3IFG5 (0x000Cu) /* P3IV P3IFG.5 */ +#define P3IV_P3IFG6 (0x000Eu) /* P3IV P3IFG.6 */ +#define P3IV_P3IFG7 (0x0010u) /* P3IV P3IFG.7 */ + +#define P4IN (PBIN_H) /* Port 4 Input */ +#define P4OUT (PBOUT_H) /* Port 4 Output */ +#define P4DIR (PBDIR_H) /* Port 4 Direction */ +#define P4REN (PBREN_H) /* Port 4 Resistor Enable */ +#define P4SEL0 (PBSEL0_H) /* Port 4 Selection 0 */ +#define P4SEL1 (PBSEL1_H) /* Port 4 Selection 1 */ +#define P4SELC (PBSELC_H) /* Port 4 Complement Selection */ +#define P4IES (PBIES_H) /* Port 4 Interrupt Edge Select */ +#define P4IE (PBIE_H) /* Port 4 Interrupt Enable */ +#define P4IFG (PBIFG_H) /* Port 4 Interrupt Flag */ + +//Definitions for P4IV +#define P4IV_NONE (0x0000u) /* No Interrupt pending */ +#define P4IV_P4IFG0 (0x0002u) /* P4IV P4IFG.0 */ +#define P4IV_P4IFG1 (0x0004u) /* P4IV P4IFG.1 */ +#define P4IV_P4IFG2 (0x0006u) /* P4IV P4IFG.2 */ +#define P4IV_P4IFG3 (0x0008u) /* P4IV P4IFG.3 */ +#define P4IV_P4IFG4 (0x000Au) /* P4IV P4IFG.4 */ +#define P4IV_P4IFG5 (0x000Cu) /* P4IV P4IFG.5 */ +#define P4IV_P4IFG6 (0x000Eu) /* P4IV P4IFG.6 */ +#define P4IV_P4IFG7 (0x0010u) /* P4IV P4IFG.7 */ + + +#endif +#endif +#endif +/************************************************************ +* DIGITAL I/O Port5/6 Pull up / Pull down Resistors +************************************************************/ +#ifdef __MSP430_HAS_PORT5_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORT6_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORTC_R__ /* Definition to show that Module is available */ + +#define OFS_PCIN (0x0000u) /* Port C Input */ +#define OFS_PCIN_L OFS_PCIN +#define OFS_PCIN_H OFS_PCIN+1 +#define OFS_PCOUT (0x0002u) /* Port C Output */ +#define OFS_PCOUT_L OFS_PCOUT +#define OFS_PCOUT_H OFS_PCOUT+1 +#define OFS_PCDIR (0x0004u) /* Port C Direction */ +#define OFS_PCDIR_L OFS_PCDIR +#define OFS_PCDIR_H OFS_PCDIR+1 +#define OFS_PCREN (0x0006u) /* Port C Resistor Enable */ +#define OFS_PCREN_L OFS_PCREN +#define OFS_PCREN_H OFS_PCREN+1 +#define OFS_PCSEL0 (0x000Au) /* Port C Selection 0 */ +#define OFS_PCSEL0_L OFS_PCSEL0 +#define OFS_PCSEL0_H OFS_PCSEL0+1 +#define OFS_PCSEL1 (0x000Cu) /* Port C Selection 1 */ +#define OFS_PCSEL1_L OFS_PCSEL1 +#define OFS_PCSEL1_H OFS_PCSEL1+1 +#define OFS_PCSELC (0x0016u) /* Port C Complement Selection */ +#define OFS_PCSELC_L OFS_PCSELC +#define OFS_PCSELC_H OFS_PCSELC+1 +#define OFS_PCIES (0x0018u) /* Port C Interrupt Edge Select */ +#define OFS_PCIES_L OFS_PCIES +#define OFS_PCIES_H OFS_PCIES+1 +#define OFS_PCIE (0x001Au) /* Port C Interrupt Enable */ +#define OFS_PCIE_L OFS_PCIE +#define OFS_PCIE_H OFS_PCIE+1 +#define OFS_PCIFG (0x001Cu) /* Port C Interrupt Flag */ +#define OFS_PCIFG_L OFS_PCIFG +#define OFS_PCIFG_H OFS_PCIFG+1 + + +#define OFS_P5IN (0x0000u) +#define OFS_P5OUT (0x0002u) +#define OFS_P5DIR (0x0004u) +#define OFS_P5REN (0x0006u) +#define OFS_P5SEL0 (0x000Au) +#define OFS_P5SEL1 (0x000Cu) +#define OFS_P5SELC (0x0016u) +#define OFS_P5IV (0x000Eu) /* Port 5 Interrupt Vector Word */ +#define OFS_P5IES (0x0018u) +#define OFS_P5IE (0x001Au) +#define OFS_P5IFG (0x001Cu) +#define OFS_P6IN (0x0001u) +#define OFS_P6OUT (0x0003u) +#define OFS_P6DIR (0x0005u) +#define OFS_P6REN (0x0007u) +#define OFS_P6SEL0 (0x000Bu) +#define OFS_P6SEL1 (0x000Du) +#define OFS_P6SELC (0x0017u) +#define OFS_P6IV (0x001Eu) /* Port 6 Interrupt Vector Word */ +#define OFS_P6IES (0x0019u) +#define OFS_P6IE (0x001Bu) +#define OFS_P6IFG (0x001du) +#define P5IN (PCIN_L) /* Port 5 Input */ +#define P5OUT (PCOUT_L) /* Port 5 Output */ +#define P5DIR (PCDIR_L) /* Port 5 Direction */ +#define P5REN (PCREN_L) /* Port 5 Resistor Enable */ +#define P5SEL0 (PCSEL0_L) /* Port 5 Selection 0 */ +#define P5SEL1 (PCSEL1_L) /* Port 5 Selection 1 */ +#define P5SELC (PCSELC_L) /* Port 5 Complement Selection */ +#define P5IES (PCIES_L) /* Port 5 Interrupt Edge Select */ +#define P5IE (PCIE_L) /* Port 5 Interrupt Enable */ +#define P5IFG (PCIFG_L) /* Port 5 Interrupt Flag */ + +//Definitions for P5IV +#define P5IV_NONE (0x0000u) /* No Interrupt pending */ +#define P5IV_P5IFG0 (0x0002u) /* P5IV P5IFG.0 */ +#define P5IV_P5IFG1 (0x0004u) /* P5IV P5IFG.1 */ +#define P5IV_P5IFG2 (0x0006u) /* P5IV P5IFG.2 */ +#define P5IV_P5IFG3 (0x0008u) /* P5IV P5IFG.3 */ +#define P5IV_P5IFG4 (0x000Au) /* P5IV P5IFG.4 */ +#define P5IV_P5IFG5 (0x000Cu) /* P5IV P5IFG.5 */ +#define P5IV_P5IFG6 (0x000Eu) /* P5IV P5IFG.6 */ +#define P5IV_P5IFG7 (0x0010u) /* P5IV P5IFG.7 */ + +#define P6IN (PCIN_H) /* Port 6 Input */ +#define P6OUT (PCOUT_H) /* Port 6 Output */ +#define P6DIR (PCDIR_H) /* Port 6 Direction */ +#define P6REN (PCREN_H) /* Port 6 Resistor Enable */ +#define P6SEL0 (PCSEL0_H) /* Port 6 Selection 0 */ +#define P6SEL1 (PCSEL1_H) /* Port 6 Selection 1 */ +#define P6SELC (PCSELC_H) /* Port 6 Complement Selection */ +#define P6IES (PCIES_H) /* Port 6 Interrupt Edge Select */ +#define P6IE (PCIE_H) /* Port 6 Interrupt Enable */ +#define P6IFG (PCIFG_H) /* Port 6 Interrupt Flag */ + +//Definitions for P6IV +#define P6IV_NONE (0x0000u) /* No Interrupt pending */ +#define P6IV_P6IFG0 (0x0002u) /* P6IV P6IFG.0 */ +#define P6IV_P6IFG1 (0x0004u) /* P6IV P6IFG.1 */ +#define P6IV_P6IFG2 (0x0006u) /* P6IV P6IFG.2 */ +#define P6IV_P6IFG3 (0x0008u) /* P6IV P6IFG.3 */ +#define P6IV_P6IFG4 (0x000Au) /* P6IV P6IFG.4 */ +#define P6IV_P6IFG5 (0x000Cu) /* P6IV P6IFG.5 */ +#define P6IV_P6IFG6 (0x000Eu) /* P6IV P6IFG.6 */ +#define P6IV_P6IFG7 (0x0010u) /* P6IV P6IFG.7 */ + + +#endif +#endif +#endif +/************************************************************ +* DIGITAL I/O Port7/8 Pull up / Pull down Resistors +************************************************************/ +#ifdef __MSP430_HAS_PORT7_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORT8_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORTD_R__ /* Definition to show that Module is available */ + +#define OFS_PDIN (0x0000u) /* Port D Input */ +#define OFS_PDIN_L OFS_PDIN +#define OFS_PDIN_H OFS_PDIN+1 +#define OFS_PDOUT (0x0002u) /* Port D Output */ +#define OFS_PDOUT_L OFS_PDOUT +#define OFS_PDOUT_H OFS_PDOUT+1 +#define OFS_PDDIR (0x0004u) /* Port D Direction */ +#define OFS_PDDIR_L OFS_PDDIR +#define OFS_PDDIR_H OFS_PDDIR+1 +#define OFS_PDREN (0x0006u) /* Port D Resistor Enable */ +#define OFS_PDREN_L OFS_PDREN +#define OFS_PDREN_H OFS_PDREN+1 +#define OFS_PDSEL0 (0x000Au) /* Port D Selection 0 */ +#define OFS_PDSEL0_L OFS_PDSEL0 +#define OFS_PDSEL0_H OFS_PDSEL0+1 +#define OFS_PDSEL1 (0x000Cu) /* Port D Selection 1 */ +#define OFS_PDSEL1_L OFS_PDSEL1 +#define OFS_PDSEL1_H OFS_PDSEL1+1 +#define OFS_PDSELC (0x0016u) /* Port D Complement Selection */ +#define OFS_PDSELC_L OFS_PDSELC +#define OFS_PDSELC_H OFS_PDSELC+1 +#define OFS_PDIES (0x0018u) /* Port D Interrupt Edge Select */ +#define OFS_PDIES_L OFS_PDIES +#define OFS_PDIES_H OFS_PDIES+1 +#define OFS_PDIE (0x001Au) /* Port D Interrupt Enable */ +#define OFS_PDIE_L OFS_PDIE +#define OFS_PDIE_H OFS_PDIE+1 +#define OFS_PDIFG (0x001Cu) /* Port D Interrupt Flag */ +#define OFS_PDIFG_L OFS_PDIFG +#define OFS_PDIFG_H OFS_PDIFG+1 + + +#define OFS_P7IN (0x0000u) +#define OFS_P7OUT (0x0002u) +#define OFS_P7DIR (0x0004u) +#define OFS_P7REN (0x0006u) +#define OFS_P7SEL0 (0x000Au) +#define OFS_P7SEL1 (0x000Cu) +#define OFS_P7SELC (0x0016u) +#define OFS_P7IV (0x000Eu) /* Port 7 Interrupt Vector Word */ +#define OFS_P7IES (0x0018u) +#define OFS_P7IE (0x001Au) +#define OFS_P7IFG (0x001Cu) +#define OFS_P8IN (0x0001u) +#define OFS_P8OUT (0x0003u) +#define OFS_P8DIR (0x0005u) +#define OFS_P8REN (0x0007u) +#define OFS_P8SEL0 (0x000Bu) +#define OFS_P8SEL1 (0x000Du) +#define OFS_P8SELC (0x0017u) +#define OFS_P8IV (0x001Eu) /* Port 8 Interrupt Vector Word */ +#define OFS_P8IES (0x0019u) +#define OFS_P8IE (0x001Bu) +#define OFS_P8IFG (0x001du) +#define P7IN (PDIN_L) /* Port 7 Input */ +#define P7OUT (PDOUT_L) /* Port 7 Output */ +#define P7DIR (PDDIR_L) /* Port 7 Direction */ +#define P7REN (PDREN_L) /* Port 7 Resistor Enable */ +#define P7SEL0 (PDSEL0_L) /* Port 7 Selection 0 */ +#define P7SEL1 (PDSEL1_L) /* Port 7 Selection 1 */ +#define P7SELC (PDSELC_L) /* Port 7 Complement Selection */ +#define P7IES (PDIES_L) /* Port 7 Interrupt Edge Select */ +#define P7IE (PDIE_L) /* Port 7 Interrupt Enable */ +#define P7IFG (PDIFG_L) /* Port 7 Interrupt Flag */ + +//Definitions for P7IV +#define P7IV_NONE (0x0000u) /* No Interrupt pending */ +#define P7IV_P7IFG0 (0x0002u) /* P7IV P7IFG.0 */ +#define P7IV_P7IFG1 (0x0004u) /* P7IV P7IFG.1 */ +#define P7IV_P7IFG2 (0x0006u) /* P7IV P7IFG.2 */ +#define P7IV_P7IFG3 (0x0008u) /* P7IV P7IFG.3 */ +#define P7IV_P7IFG4 (0x000Au) /* P7IV P7IFG.4 */ +#define P7IV_P7IFG5 (0x000Cu) /* P7IV P7IFG.5 */ +#define P7IV_P7IFG6 (0x000Eu) /* P7IV P7IFG.6 */ +#define P7IV_P7IFG7 (0x0010u) /* P7IV P7IFG.7 */ + +#define P8IN (PDIN_H) /* Port 8 Input */ +#define P8OUT (PDOUT_H) /* Port 8 Output */ +#define P8DIR (PDDIR_H) /* Port 8 Direction */ +#define P8REN (PDREN_H) /* Port 8 Resistor Enable */ +#define P8SEL0 (PDSEL0_H) /* Port 8 Selection 0 */ +#define P8SEL1 (PDSEL1_H) /* Port 8 Selection 1 */ +#define P8SELC (PDSELC_H) /* Port 8 Complement Selection */ +#define P8IES (PDIES_H) /* Port 8 Interrupt Edge Select */ +#define P8IE (PDIE_H) /* Port 8 Interrupt Enable */ +#define P8IFG (PDIFG_H) /* Port 8 Interrupt Flag */ + +//Definitions for P8IV +#define P8IV_NONE (0x0000u) /* No Interrupt pending */ +#define P8IV_P8IFG0 (0x0002u) /* P8IV P8IFG.0 */ +#define P8IV_P8IFG1 (0x0004u) /* P8IV P8IFG.1 */ +#define P8IV_P8IFG2 (0x0006u) /* P8IV P8IFG.2 */ +#define P8IV_P8IFG3 (0x0008u) /* P8IV P8IFG.3 */ +#define P8IV_P8IFG4 (0x000Au) /* P8IV P8IFG.4 */ +#define P8IV_P8IFG5 (0x000Cu) /* P8IV P8IFG.5 */ +#define P8IV_P8IFG6 (0x000Eu) /* P8IV P8IFG.6 */ +#define P8IV_P8IFG7 (0x0010u) /* P8IV P8IFG.7 */ + + +#endif +#endif +#endif +/************************************************************ +* DIGITAL I/O Port9/10 Pull up / Pull down Resistors +************************************************************/ +#ifdef __MSP430_HAS_PORT9_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORT10_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORTE_R__ /* Definition to show that Module is available */ + +#define OFS_PEIN (0x0000u) /* Port E Input */ +#define OFS_PEIN_L OFS_PEIN +#define OFS_PEIN_H OFS_PEIN+1 +#define OFS_PEOUT (0x0002u) /* Port E Output */ +#define OFS_PEOUT_L OFS_PEOUT +#define OFS_PEOUT_H OFS_PEOUT+1 +#define OFS_PEDIR (0x0004u) /* Port E Direction */ +#define OFS_PEDIR_L OFS_PEDIR +#define OFS_PEDIR_H OFS_PEDIR+1 +#define OFS_PEREN (0x0006u) /* Port E Resistor Enable */ +#define OFS_PEREN_L OFS_PEREN +#define OFS_PEREN_H OFS_PEREN+1 +#define OFS_PESEL0 (0x000Au) /* Port E Selection 0 */ +#define OFS_PESEL0_L OFS_PESEL0 +#define OFS_PESEL0_H OFS_PESEL0+1 +#define OFS_PESEL1 (0x000Cu) /* Port E Selection 1 */ +#define OFS_PESEL1_L OFS_PESEL1 +#define OFS_PESEL1_H OFS_PESEL1+1 +#define OFS_PESELC (0x0016u) /* Port E Complement Selection */ +#define OFS_PESELC_L OFS_PESELC +#define OFS_PESELC_H OFS_PESELC+1 +#define OFS_PEIES (0x0018u) /* Port E Interrupt Edge Select */ +#define OFS_PEIES_L OFS_PEIES +#define OFS_PEIES_H OFS_PEIES+1 +#define OFS_PEIE (0x001Au) /* Port E Interrupt Enable */ +#define OFS_PEIE_L OFS_PEIE +#define OFS_PEIE_H OFS_PEIE+1 +#define OFS_PEIFG (0x001Cu) /* Port E Interrupt Flag */ +#define OFS_PEIFG_L OFS_PEIFG +#define OFS_PEIFG_H OFS_PEIFG+1 + + +#define OFS_P9IN (0x0000u) +#define OFS_P9OUT (0x0002u) +#define OFS_P9DIR (0x0004u) +#define OFS_P9REN (0x0006u) +#define OFS_P9SEL0 (0x000Au) +#define OFS_P9SEL1 (0x000Cu) +#define OFS_P9SELC (0x0016u) +#define OFS_P9IV (0x000Eu) /* Port 9 Interrupt Vector Word */ +#define OFS_P9IES (0x0018u) +#define OFS_P9IE (0x001Au) +#define OFS_P9IFG (0x001Cu) +#define OFS_P10IN (0x0001u) +#define OFS_P10OUT (0x0003u) +#define OFS_P10DIR (0x0005u) +#define OFS_P10REN (0x0007u) +#define OFS_P10SEL0 (0x000Bu) +#define OFS_P10SEL1 (0x000Du) +#define OFS_P10SELC (0x0017u) +#define OFS_P10IV (0x001Eu) /* Port 10 Interrupt Vector Word */ +#define OFS_P10IES (0x0019u) +#define OFS_P10IE (0x001Bu) +#define OFS_P10IFG (0x001du) +#define P9IN (PEIN_L) /* Port 9 Input */ +#define P9OUT (PEOUT_L) /* Port 9 Output */ +#define P9DIR (PEDIR_L) /* Port 9 Direction */ +#define P9REN (PEREN_L) /* Port 9 Resistor Enable */ +#define P9SEL0 (PESEL0_L) /* Port 9 Selection 0 */ +#define P9SEL1 (PESEL1_L) /* Port 9 Selection 1 */ +#define P9SELC (PESELC_L) /* Port 9 Complement Selection */ +#define P9IES (PEIES_L) /* Port 9 Interrupt Edge Select */ +#define P9IE (PEIE_L) /* Port 9 Interrupt Enable */ +#define P9IFG (PEIFG_L) /* Port 9 Interrupt Flag */ + +//Definitions for P9IV +#define P9IV_NONE (0x0000u) /* No Interrupt pending */ +#define P9IV_P9IFG0 (0x0002u) /* P9IV P9IFG.0 */ +#define P9IV_P9IFG1 (0x0004u) /* P9IV P9IFG.1 */ +#define P9IV_P9IFG2 (0x0006u) /* P9IV P9IFG.2 */ +#define P9IV_P9IFG3 (0x0008u) /* P9IV P9IFG.3 */ +#define P9IV_P9IFG4 (0x000Au) /* P9IV P9IFG.4 */ +#define P9IV_P9IFG5 (0x000Cu) /* P9IV P9IFG.5 */ +#define P9IV_P9IFG6 (0x000Eu) /* P9IV P9IFG.6 */ +#define P9IV_P9IFG7 (0x0010u) /* P9IV P9IFG.7 */ + +#define P10IN (PEIN_H) /* Port 10 Input */ +#define P10OUT (PEOUT_H) /* Port 10 Output */ +#define P10DIR (PEDIR_H) /* Port 10 Direction */ +#define P10REN (PEREN_H) /* Port 10 Resistor Enable */ +#define P10SEL0 (PESEL0_H) /* Port 10 Selection 0 */ +#define P10SEL1 (PESEL1_H) /* Port 10 Selection 1 */ +#define P10SELC (PESELC_H) /* Port 10 Complement Selection */ +#define P10IES (PEIES_H) /* Port 10 Interrupt Edge Select */ +#define P10IE (PEIE_H) /* Port 10 Interrupt Enable */ +#define P10IFG (PEIFG_H) /* Port 10 Interrupt Flag */ + +//Definitions for P10IV +#define P10IV_NONE (0x0000u) /* No Interrupt pending */ +#define P10IV_P10IFG0 (0x0002u) /* P10IV P10IFG.0 */ +#define P10IV_P10IFG1 (0x0004u) /* P10IV P10IFG.1 */ +#define P10IV_P10IFG2 (0x0006u) /* P10IV P10IFG.2 */ +#define P10IV_P10IFG3 (0x0008u) /* P10IV P10IFG.3 */ +#define P10IV_P10IFG4 (0x000Au) /* P10IV P10IFG.4 */ +#define P10IV_P10IFG5 (0x000Cu) /* P10IV P10IFG.5 */ +#define P10IV_P10IFG6 (0x000Eu) /* P10IV P10IFG.6 */ +#define P10IV_P10IFG7 (0x0010u) /* P10IV P10IFG.7 */ + + +#endif +#endif +#endif +/************************************************************ +* DIGITAL I/O Port11 Pull up / Pull down Resistors +************************************************************/ +#ifdef __MSP430_HAS_PORT11_R__ /* Definition to show that Module is available */ +#ifdef __MSP430_HAS_PORTF_R__ /* Definition to show that Module is available */ + +#define OFS_PFIN (0x0000u) /* Port F Input */ +#define OFS_PFIN_L OFS_PFIN +#define OFS_PFIN_H OFS_PFIN+1 +#define OFS_PFOUT (0x0002u) /* Port F Output */ +#define OFS_PFOUT_L OFS_PFOUT +#define OFS_PFOUT_H OFS_PFOUT+1 +#define OFS_PFDIR (0x0004u) /* Port F Direction */ +#define OFS_PFDIR_L OFS_PFDIR +#define OFS_PFDIR_H OFS_PFDIR+1 +#define OFS_PFREN (0x0006u) /* Port F Resistor Enable */ +#define OFS_PFREN_L OFS_PFREN +#define OFS_PFREN_H OFS_PFREN+1 +#define OFS_PFSEL0 (0x000Au) /* Port F Selection 0 */ +#define OFS_PFSEL0_L OFS_PFSEL0 +#define OFS_PFSEL0_H OFS_PFSEL0+1 +#define OFS_PFSEL1 (0x000Cu) /* Port F Selection 1 */ +#define OFS_PFSEL1_L OFS_PFSEL1 +#define OFS_PFSEL1_H OFS_PFSEL1+1 +#define OFS_PFSELC (0x0016u) /* Port F Complement Selection */ +#define OFS_PFSELC_L OFS_PFSELC +#define OFS_PFSELC_H OFS_PFSELC+1 +#define OFS_PFIES (0x0018u) /* Port F Interrupt Edge Select */ +#define OFS_PFIES_L OFS_PFIES +#define OFS_PFIES_H OFS_PFIES+1 +#define OFS_PFIE (0x001Au) /* Port F Interrupt Enable */ +#define OFS_PFIE_L OFS_PFIE +#define OFS_PFIE_H OFS_PFIE+1 +#define OFS_PFIFG (0x001Cu) /* Port F Interrupt Flag */ +#define OFS_PFIFG_L OFS_PFIFG +#define OFS_PFIFG_H OFS_PFIFG+1 + + +#define OFS_P11IN (0x0000u) +#define OFS_P11OUT (0x0002u) +#define OFS_P11DIR (0x0004u) +#define OFS_P11REN (0x0006u) +#define OFS_P11SEL0 (0x000Au) +#define OFS_P11SEL1 (0x000Cu) +#define OFS_P11SELC (0x0016u) +#define OFS_P11IV (0x000Eu) /* Port 11 Interrupt Vector Word */ +#define OFS_P11IES (0x0018u) +#define OFS_P11IE (0x001Au) +#define OFS_P11IFG (0x001Cu) +#define P11IN (PFIN_L) /* Port 11 Input */ +#define P11OUT (PFOUT_L) /* Port 11 Output */ +#define P11DIR (PFDIR_L) /* Port 11 Direction */ +#define P11REN (PFREN_L) /* Port 11 Resistor Enable */ +#define P11SEL0 (PFSEL0_L) /* Port 11 Selection0 */ +#define P11SEL1 (PFSEL1_L) /* Port 11 Selection1 */ +#define OFS_P11SELC (0x0017u) + +#define P11IES (PFIES_L) /* Port 11 Interrupt Edge Select */ +#define P11IE (PFIE_L) /* Port 11 Interrupt Enable */ +#define P11IFG (PFIFG_L) /* Port 11 Interrupt Flag */ + +//Definitions for P11IV +#define P11IV_NONE (0x0000u) /* No Interrupt pending */ +#define P11IV_P11IFG0 (0x0002u) /* P11IV P11IFG.0 */ +#define P11IV_P11IFG1 (0x0004u) /* P11IV P11IFG.1 */ +#define P11IV_P11IFG2 (0x0006u) /* P11IV P11IFG.2 */ +#define P11IV_P11IFG3 (0x0008u) /* P11IV P11IFG.3 */ +#define P11IV_P11IFG4 (0x000Au) /* P11IV P11IFG.4 */ +#define P11IV_P11IFG5 (0x000Cu) /* P11IV P11IFG.5 */ +#define P11IV_P11IFG6 (0x000Eu) /* P11IV P11IFG.6 */ +#define P11IV_P11IFG7 (0x0010u) /* P11IV P11IFG.7 */ + + +#endif +#endif +/************************************************************ +* DIGITAL I/O PortJ Pull up / Pull down Resistors +************************************************************/ +#ifdef __MSP430_HAS_PORTJ_R__ /* Definition to show that Module is available */ + +#define OFS_PJIN (0x0000u) /* Port J Input */ +#define OFS_PJIN_L OFS_PJIN +#define OFS_PJIN_H OFS_PJIN+1 +#define OFS_PJOUT (0x0002u) /* Port J Output */ +#define OFS_PJOUT_L OFS_PJOUT +#define OFS_PJOUT_H OFS_PJOUT+1 +#define OFS_PJDIR (0x0004u) /* Port J Direction */ +#define OFS_PJDIR_L OFS_PJDIR +#define OFS_PJDIR_H OFS_PJDIR+1 +#define OFS_PJREN (0x0006u) /* Port J Resistor Enable */ +#define OFS_PJREN_L OFS_PJREN +#define OFS_PJREN_H OFS_PJREN+1 +#define OFS_PJSEL0 (0x000Au) /* Port J Selection 0 */ +#define OFS_PJSEL0_L OFS_PJSEL0 +#define OFS_PJSEL0_H OFS_PJSEL0+1 +#define OFS_PJSEL1 (0x000Cu) /* Port J Selection 1 */ +#define OFS_PJSEL1_L OFS_PJSEL1 +#define OFS_PJSEL1_H OFS_PJSEL1+1 +#define OFS_PJSELC (0x0016u) /* Port J Complement Selection */ +#define OFS_PJSELC_L OFS_PJSELC +#define OFS_PJSELC_H OFS_PJSELC+1 + +#endif +/************************************************************* +* RAM Control Module for FRAM +*************************************************************/ +#ifdef __MSP430_HAS_RC_FRAM__ /* Definition to show that Module is available */ + +#define OFS_RCCTL0 (0x0000u) /* Ram Controller Control Register */ +#define OFS_RCCTL0_L OFS_RCCTL0 +#define OFS_RCCTL0_H OFS_RCCTL0+1 + +/* RCCTL0 Control Bits */ +#define RCRS0OFF0 (0x0001u) /* RAM Controller RAM Sector 0 Off Bit: 0 */ +#define RCRS0OFF1 (0x0002u) /* RAM Controller RAM Sector 0 Off Bit: 1 */ +#define RCRS4OFF0 (0x0100u) /* RAM Controller RAM Sector 4 Off Bit: 0 */ +#define RCRS4OFF1 (0x0200u) /* RAM Controller RAM Sector 4 Off Bit: 1 */ +#define RCRS5OFF0 (0x0400u) /* RAM Controller RAM Sector 5 Off Bit: 0 */ +#define RCRS5OFF1 (0x0800u) /* RAM Controller RAM Sector 5 Off Bit: 1 */ +#define RCRS6OFF0 (0x1000u) /* RAM Controller RAM Sector 6 Off Bit: 0 */ +#define RCRS6OFF1 (0x2000u) /* RAM Controller RAM Sector 6 Off Bit: 1 */ +#define RCRS7OFF0 (0x4000u) /* RAM Controller RAM Sector 7 (USB) Off Bit: 0 */ +#define RCRS7OFF1 (0x8000u) /* RAM Controller RAM Sector 7 (USB) Off Bit: 1 */ + +/* RCCTL0 Control Bits */ +#define RCRS0OFF0_L (0x0001u) /* RAM Controller RAM Sector 0 Off Bit: 0 */ +#define RCRS0OFF1_L (0x0002u) /* RAM Controller RAM Sector 0 Off Bit: 1 */ + +/* RCCTL0 Control Bits */ +#define RCRS4OFF0_H (0x0001u) /* RAM Controller RAM Sector 4 Off Bit: 0 */ +#define RCRS4OFF1_H (0x0002u) /* RAM Controller RAM Sector 4 Off Bit: 1 */ +#define RCRS5OFF0_H (0x0004u) /* RAM Controller RAM Sector 5 Off Bit: 0 */ +#define RCRS5OFF1_H (0x0008u) /* RAM Controller RAM Sector 5 Off Bit: 1 */ +#define RCRS6OFF0_H (0x0010u) /* RAM Controller RAM Sector 6 Off Bit: 0 */ +#define RCRS6OFF1_H (0x0020u) /* RAM Controller RAM Sector 6 Off Bit: 1 */ +#define RCRS7OFF0_H (0x0040u) /* RAM Controller RAM Sector 7 (USB) Off Bit: 0 */ +#define RCRS7OFF1_H (0x0080u) /* RAM Controller RAM Sector 7 (USB) Off Bit: 1 */ + +#define RCKEY (0x5A00u) + +#define RCRS0OFF_0 (0x0000u) /* RAM Controller RAM Sector 0 Off : 0 */ +#define RCRS0OFF_1 (0x0001u) /* RAM Controller RAM Sector 0 Off : 1 */ +#define RCRS0OFF_2 (0x0002u) /* RAM Controller RAM Sector 0 Off : 2 */ +#define RCRS0OFF_3 (0x0003u) /* RAM Controller RAM Sector 0 Off : 3 */ +#define RCRS4OFF_0 (0x0000u) /* RAM Controller RAM Sector 4 Off : 0 */ +#define RCRS4OFF_2 (0x0100u) /* RAM Controller RAM Sector 4 Off : 1 */ +#define RCRS4OFF_3 (0x0200u) /* RAM Controller RAM Sector 4 Off : 2 */ +#define RCRS4OFF_4 (0x0300u) /* RAM Controller RAM Sector 4 Off : 3 */ +#define RCRS5OFF_0 (0x0000u) /* RAM Controller RAM Sector 5 Off : 0 */ +#define RCRS5OFF_1 (0x0400u) /* RAM Controller RAM Sector 5 Off : 1 */ +#define RCRS5OFF_2 (0x0800u) /* RAM Controller RAM Sector 5 Off : 2 */ +#define RCRS5OFF_3 (0x0C00u) /* RAM Controller RAM Sector 5 Off : 3 */ +#define RCRS6OFF_0 (0x0000u) /* RAM Controller RAM Sector 6 Off : 0 */ +#define RCRS6OFF_1 (0x0100u) /* RAM Controller RAM Sector 6 Off : 1 */ +#define RCRS6OFF_2 (0x0200u) /* RAM Controller RAM Sector 6 Off : 2 */ +#define RCRS6OFF_3 (0x0300u) /* RAM Controller RAM Sector 6 Off : 3 */ +#define RCRS7OFF_0 (0x0000u) /* RAM Controller RAM Sector 7 Off : 0 */ +#define RCRS7OFF_1 (0x4000u) /* RAM Controller RAM Sector 7 Off : 1 */ +#define RCRS7OFF_2 (0x8000u) /* RAM Controller RAM Sector 7 Off : 2*/ +#define RCRS7OFF_3 (0xC000u) /* RAM Controller RAM Sector 7 Off : 3*/ + +#endif +/************************************************************ +* Shared Reference +************************************************************/ +#ifdef __MSP430_HAS_REF_A__ /* Definition to show that Module is available */ + +#define OFS_REFCTL0 (0x0000u) /* REF Shared Reference control register 0 */ +#define OFS_REFCTL0_L OFS_REFCTL0 +#define OFS_REFCTL0_H OFS_REFCTL0+1 + +/* REFCTL0 Control Bits */ +#define REFON (0x0001u) /* REF Reference On */ +#define REFOUT (0x0002u) /* REF Reference output Buffer On */ +//#define RESERVED (0x0004u) /* Reserved */ +#define REFTCOFF (0x0008u) /* REF Temp.Sensor off */ +#define REFVSEL0 (0x0010u) /* REF Reference Voltage Level Select Bit:0 */ +#define REFVSEL1 (0x0020u) /* REF Reference Voltage Level Select Bit:1 */ +#define REFGENOT (0x0040u) /* REF Reference generator one-time trigger */ +#define REFBGOT (0x0080u) /* REF Bandgap and bandgap buffer one-time trigger */ +#define REFGENACT (0x0100u) /* REF Reference generator active */ +#define REFBGACT (0x0200u) /* REF Reference bandgap active */ +#define REFGENBUSY (0x0400u) /* REF Reference generator busy */ +#define BGMODE (0x0800u) /* REF Bandgap mode */ +#define REFGENRDY (0x1000u) /* REF Reference generator ready */ +#define REFBGRDY (0x2000u) /* REF Reference bandgap ready */ +//#define RESERVED (0x4000u) /* Reserved */ +//#define RESERVED (0x8000u) /* Reserved */ + +/* REFCTL0 Control Bits */ +#define REFON_L (0x0001u) /* REF Reference On */ +#define REFOUT_L (0x0002u) /* REF Reference output Buffer On */ +//#define RESERVED (0x0004u) /* Reserved */ +#define REFTCOFF_L (0x0008u) /* REF Temp.Sensor off */ +#define REFVSEL0_L (0x0010u) /* REF Reference Voltage Level Select Bit:0 */ +#define REFVSEL1_L (0x0020u) /* REF Reference Voltage Level Select Bit:1 */ +#define REFGENOT_L (0x0040u) /* REF Reference generator one-time trigger */ +#define REFBGOT_L (0x0080u) /* REF Bandgap and bandgap buffer one-time trigger */ +//#define RESERVED (0x4000u) /* Reserved */ +//#define RESERVED (0x8000u) /* Reserved */ + +/* REFCTL0 Control Bits */ +//#define RESERVED (0x0004u) /* Reserved */ +#define REFGENACT_H (0x0001u) /* REF Reference generator active */ +#define REFBGACT_H (0x0002u) /* REF Reference bandgap active */ +#define REFGENBUSY_H (0x0004u) /* REF Reference generator busy */ +#define BGMODE_H (0x0008u) /* REF Bandgap mode */ +#define REFGENRDY_H (0x0010u) /* REF Reference generator ready */ +#define REFBGRDY_H (0x0020u) /* REF Reference bandgap ready */ +//#define RESERVED (0x4000u) /* Reserved */ +//#define RESERVED (0x8000u) /* Reserved */ + +#define REFVSEL_0 (0x0000u) /* REF Reference Voltage Level Select 1.2V */ +#define REFVSEL_1 (0x0010u) /* REF Reference Voltage Level Select 2.0V */ +#define REFVSEL_2 (0x0020u) /* REF Reference Voltage Level Select 2.5V */ +#define REFVSEL_3 (0x0030u) /* REF Reference Voltage Level Select 2.5V */ + +#endif +/************************************************************ +* Real Time Clock +************************************************************/ +#ifdef __MSP430_HAS_RTC_B__ /* Definition to show that Module is available */ + +#define OFS_RTCCTL01 (0x0000u) /* Real Timer Control 0/1 */ +#define OFS_RTCCTL01_L OFS_RTCCTL01 +#define OFS_RTCCTL01_H OFS_RTCCTL01+1 +#define OFS_RTCCTL23 (0x0002u) /* Real Timer Control 2/3 */ +#define OFS_RTCCTL23_L OFS_RTCCTL23 +#define OFS_RTCCTL23_H OFS_RTCCTL23+1 +#define OFS_RTCPS0CTL (0x0008u) /* Real Timer Prescale Timer 0 Control */ +#define OFS_RTCPS0CTL_L OFS_RTCPS0CTL +#define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1 +#define OFS_RTCPS1CTL (0x000Au) /* Real Timer Prescale Timer 1 Control */ +#define OFS_RTCPS1CTL_L OFS_RTCPS1CTL +#define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1 +#define OFS_RTCPS (0x000Cu) /* Real Timer Prescale Timer Control */ +#define OFS_RTCPS_L OFS_RTCPS +#define OFS_RTCPS_H OFS_RTCPS+1 +#define OFS_RTCIV (0x000Eu) /* Real Time Clock Interrupt Vector */ +#define OFS_RTCTIM0 (0x0010u) /* Real Time Clock Time 0 */ +#define OFS_RTCTIM0_L OFS_RTCTIM0 +#define OFS_RTCTIM0_H OFS_RTCTIM0+1 +#define OFS_RTCTIM1 (0x0012u) /* Real Time Clock Time 1 */ +#define OFS_RTCTIM1_L OFS_RTCTIM1 +#define OFS_RTCTIM1_H OFS_RTCTIM1+1 +#define OFS_RTCDATE (0x0014u) /* Real Time Clock Date */ +#define OFS_RTCDATE_L OFS_RTCDATE +#define OFS_RTCDATE_H OFS_RTCDATE+1 +#define OFS_RTCYEAR (0x0016u) /* Real Time Clock Year */ +#define OFS_RTCYEAR_L OFS_RTCYEAR +#define OFS_RTCYEAR_H OFS_RTCYEAR+1 +#define OFS_RTCAMINHR (0x0018u) /* Real Time Clock Alarm Min/Hour */ +#define OFS_RTCAMINHR_L OFS_RTCAMINHR +#define OFS_RTCAMINHR_H OFS_RTCAMINHR+1 +#define OFS_RTCADOWDAY (0x001Au) /* Real Time Clock Alarm day of week/day */ +#define OFS_RTCADOWDAY_L OFS_RTCADOWDAY +#define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1 +#define OFS_BIN2BCD (0x001Cu) /* Real Time Binary-to-BCD conversion register */ +#define OFS_BCD2BIN (0x001Eu) /* Real Time BCD-to-binary conversion register */ +#define OFS_RTCSEC (0x0010u) +#define OFS_RTCMIN (0x0011u) +#define OFS_RTCHOUR (0x0012u) +#define OFS_RTCDOW (0x0013u) +#define OFS_RTCDAY (0x0014u) +#define OFS_RTCMON (0x0015u) +#define OFS_RTCAMIN (0x0018u) +#define OFS_RTCAHOUR (0x0019u) +#define OFS_RTCADOW (0x001Au) +#define OFS_RTCADAY (0x001Bu) + +#define RTCCTL0 RTCCTL01_L /* Real Time Clock Control 0 */ +#define RTCCTL1 RTCCTL01_H /* Real Time Clock Control 1 */ +#define RTCCTL2 RTCCTL23_L /* Real Time Clock Control 2 */ +#define RTCCTL3 RTCCTL23_H /* Real Time Clock Control 3 */ +#define RTCNT12 RTCTIM0 +#define RTCNT34 RTCTIM1 +#define RTCNT1 RTCTIM0_L +#define RTCNT2 RTCTIM0_H +#define RTCNT3 RTCTIM1_L +#define RTCNT4 RTCTIM1_H +#define RTCSEC RTCTIM0_L +#define RTCMIN RTCTIM0_H +#define RTCHOUR RTCTIM1_L +#define RTCDOW RTCTIM1_H +#define RTCDAY RTCDATE_L +#define RTCMON RTCDATE_H +#define RTCYEARL RTCYEAR_L +#define RTCYEARH RTCYEAR_H +#define RT0PS RTCPS_L +#define RT1PS RTCPS_H +#define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */ +#define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */ +#define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */ +#define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */ + +/* RTCCTL01 Control Bits */ +#define RTCBCD (0x8000u) /* RTC BCD 0:Binary / 1:BCD */ +#define RTCHOLD (0x4000u) /* RTC Hold */ +//#define RESERVED (0x2000u) /* RESERVED */ +#define RTCRDY (0x1000u) /* RTC Ready */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x0400u) /* RESERVED */ +#define RTCTEV1 (0x0200u) /* RTC Time Event 1 */ +#define RTCTEV0 (0x0100u) /* RTC Time Event 0 */ +#define RTCOFIE (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */ +#define RTCTEVIE (0x0040u) /* RTC Time Event Interrupt Enable Flag */ +#define RTCAIE (0x0020u) /* RTC Alarm Interrupt Enable Flag */ +#define RTCRDYIE (0x0010u) /* RTC Ready Interrupt Enable Flag */ +#define RTCOFIFG (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */ +#define RTCTEVIFG (0x0004u) /* RTC Time Event Interrupt Flag */ +#define RTCAIFG (0x0002u) /* RTC Alarm Interrupt Flag */ +#define RTCRDYIFG (0x0001u) /* RTC Ready Interrupt Flag */ + +/* RTCCTL01 Control Bits */ +//#define RESERVED (0x2000u) /* RESERVED */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x0400u) /* RESERVED */ +#define RTCOFIE_L (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */ +#define RTCTEVIE_L (0x0040u) /* RTC Time Event Interrupt Enable Flag */ +#define RTCAIE_L (0x0020u) /* RTC Alarm Interrupt Enable Flag */ +#define RTCRDYIE_L (0x0010u) /* RTC Ready Interrupt Enable Flag */ +#define RTCOFIFG_L (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */ +#define RTCTEVIFG_L (0x0004u) /* RTC Time Event Interrupt Flag */ +#define RTCAIFG_L (0x0002u) /* RTC Alarm Interrupt Flag */ +#define RTCRDYIFG_L (0x0001u) /* RTC Ready Interrupt Flag */ + +/* RTCCTL01 Control Bits */ +#define RTCBCD_H (0x0080u) /* RTC BCD 0:Binary / 1:BCD */ +#define RTCHOLD_H (0x0040u) /* RTC Hold */ +//#define RESERVED (0x2000u) /* RESERVED */ +#define RTCRDY_H (0x0010u) /* RTC Ready */ +//#define RESERVED (0x0800u) /* RESERVED */ +//#define RESERVED (0x0400u) /* RESERVED */ +#define RTCTEV1_H (0x0002u) /* RTC Time Event 1 */ +#define RTCTEV0_H (0x0001u) /* RTC Time Event 0 */ + +#define RTCTEV_0 (0x0000u) /* RTC Time Event: 0 (Min. changed) */ +#define RTCTEV_1 (0x0100u) /* RTC Time Event: 1 (Hour changed) */ +#define RTCTEV_2 (0x0200u) /* RTC Time Event: 2 (12:00 changed) */ +#define RTCTEV_3 (0x0300u) /* RTC Time Event: 3 (00:00 changed) */ +#define RTCTEV__MIN (0x0000u) /* RTC Time Event: 0 (Min. changed) */ +#define RTCTEV__HOUR (0x0100u) /* RTC Time Event: 1 (Hour changed) */ +#define RTCTEV__0000 (0x0200u) /* RTC Time Event: 2 (00:00 changed) */ +#define RTCTEV__1200 (0x0300u) /* RTC Time Event: 3 (12:00 changed) */ + +/* RTCCTL23 Control Bits */ +#define RTCCALF1 (0x0200u) /* RTC Calibration Frequency Bit 1 */ +#define RTCCALF0 (0x0100u) /* RTC Calibration Frequency Bit 0 */ +#define RTCCALS (0x0080u) /* RTC Calibration Sign */ +//#define Reserved (0x0040u) +#define RTCCAL5 (0x0020u) /* RTC Calibration Bit 5 */ +#define RTCCAL4 (0x0010u) /* RTC Calibration Bit 4 */ +#define RTCCAL3 (0x0008u) /* RTC Calibration Bit 3 */ +#define RTCCAL2 (0x0004u) /* RTC Calibration Bit 2 */ +#define RTCCAL1 (0x0002u) /* RTC Calibration Bit 1 */ +#define RTCCAL0 (0x0001u) /* RTC Calibration Bit 0 */ + +/* RTCCTL23 Control Bits */ +#define RTCCALS_L (0x0080u) /* RTC Calibration Sign */ +//#define Reserved (0x0040u) +#define RTCCAL5_L (0x0020u) /* RTC Calibration Bit 5 */ +#define RTCCAL4_L (0x0010u) /* RTC Calibration Bit 4 */ +#define RTCCAL3_L (0x0008u) /* RTC Calibration Bit 3 */ +#define RTCCAL2_L (0x0004u) /* RTC Calibration Bit 2 */ +#define RTCCAL1_L (0x0002u) /* RTC Calibration Bit 1 */ +#define RTCCAL0_L (0x0001u) /* RTC Calibration Bit 0 */ + +/* RTCCTL23 Control Bits */ +#define RTCCALF1_H (0x0002u) /* RTC Calibration Frequency Bit 1 */ +#define RTCCALF0_H (0x0001u) /* RTC Calibration Frequency Bit 0 */ +//#define Reserved (0x0040u) + +#define RTCCALF_0 (0x0000u) /* RTC Calibration Frequency: No Output */ +#define RTCCALF_1 (0x0100u) /* RTC Calibration Frequency: 512 Hz */ +#define RTCCALF_2 (0x0200u) /* RTC Calibration Frequency: 256 Hz */ +#define RTCCALF_3 (0x0300u) /* RTC Calibration Frequency: 1 Hz */ + +#define RTCAE (0x80) /* Real Time Clock Alarm enable */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x0080u) +//#define Reserved (0x0040u) +//#define Reserved (0x0020u) +#define RT0IP2 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ +#define RT0IP1 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ +#define RT0IP0 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ +#define RT0PSIE (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */ +#define RT0PSIFG (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x0080u) +//#define Reserved (0x0040u) +//#define Reserved (0x0020u) +#define RT0IP2_L (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ +#define RT0IP1_L (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ +#define RT0IP0_L (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ +#define RT0PSIE_L (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */ +#define RT0PSIFG_L (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */ + +#define RT0IP_0 (0x0000u) /* RTC Prescale Timer 0 Interrupt Interval /2 */ +#define RT0IP_1 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval /4 */ +#define RT0IP_2 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval /8 */ +#define RT0IP_3 (0x000Cu) /* RTC Prescale Timer 0 Interrupt Interval /16 */ +#define RT0IP_4 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval /32 */ +#define RT0IP_5 (0x0014u) /* RTC Prescale Timer 0 Interrupt Interval /64 */ +#define RT0IP_6 (0x0018u) /* RTC Prescale Timer 0 Interrupt Interval /128 */ +#define RT0IP_7 (0x001Cu) /* RTC Prescale Timer 0 Interrupt Interval /256 */ + +#define RT0IP__2 (0x0000u) /* RTC Prescale Timer 0 Interrupt Interval /2 */ +#define RT0IP__4 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval /4 */ +#define RT0IP__8 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval /8 */ +#define RT0IP__16 (0x000Cu) /* RTC Prescale Timer 0 Interrupt Interval /16 */ +#define RT0IP__32 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval /32 */ +#define RT0IP__64 (0x0014u) /* RTC Prescale Timer 0 Interrupt Interval /64 */ +#define RT0IP__128 (0x0018u) /* RTC Prescale Timer 0 Interrupt Interval /128 */ +#define RT0IP__256 (0x001Cu) /* RTC Prescale Timer 0 Interrupt Interval /256 */ + +/* RTCPS1CTL Control Bits */ +//#define Reserved (0x0080u) +//#define Reserved (0x0040u) +//#define Reserved (0x0020u) +#define RT1IP2 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ +#define RT1IP1 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ +#define RT1IP0 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ +#define RT1PSIE (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */ +#define RT1PSIFG (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */ + +/* RTCPS1CTL Control Bits */ +//#define Reserved (0x0080u) +//#define Reserved (0x0040u) +//#define Reserved (0x0020u) +#define RT1IP2_L (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ +#define RT1IP1_L (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ +#define RT1IP0_L (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ +#define RT1PSIE_L (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */ +#define RT1PSIFG_L (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */ + +#define RT1IP_0 (0x0000u) /* RTC Prescale Timer 1 Interrupt Interval /2 */ +#define RT1IP_1 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval /4 */ +#define RT1IP_2 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval /8 */ +#define RT1IP_3 (0x000Cu) /* RTC Prescale Timer 1 Interrupt Interval /16 */ +#define RT1IP_4 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval /32 */ +#define RT1IP_5 (0x0014u) /* RTC Prescale Timer 1 Interrupt Interval /64 */ +#define RT1IP_6 (0x0018u) /* RTC Prescale Timer 1 Interrupt Interval /128 */ +#define RT1IP_7 (0x001Cu) /* RTC Prescale Timer 1 Interrupt Interval /256 */ + +#define RT1IP__2 (0x0000u) /* RTC Prescale Timer 1 Interrupt Interval /2 */ +#define RT1IP__4 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval /4 */ +#define RT1IP__8 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval /8 */ +#define RT1IP__16 (0x000Cu) /* RTC Prescale Timer 1 Interrupt Interval /16 */ +#define RT1IP__32 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval /32 */ +#define RT1IP__64 (0x0014u) /* RTC Prescale Timer 1 Interrupt Interval /64 */ +#define RT1IP__128 (0x0018u) /* RTC Prescale Timer 1 Interrupt Interval /128 */ +#define RT1IP__256 (0x001Cu) /* RTC Prescale Timer 1 Interrupt Interval /256 */ + +/* RTC Definitions */ +#define RTCIV_NONE (0x0000u) /* No Interrupt pending */ +#define RTCIV_RTCRDYIFG (0x0002u) /* RTC ready: RTCRDYIFG */ +#define RTCIV_RTCTEVIFG (0x0004u) /* RTC interval timer: RTCTEVIFG */ +#define RTCIV_RTCAIFG (0x0006u) /* RTC user alarm: RTCAIFG */ +#define RTCIV_RT0PSIFG (0x0008u) /* RTC prescaler 0: RT0PSIFG */ +#define RTCIV_RT1PSIFG (0x000Au) /* RTC prescaler 1: RT1PSIFG */ +#define RTCIV_RTCOFIFG (0x000Cu) /* RTC Oscillator fault */ + +/* Legacy Definitions */ +#define RTC_NONE (0x0000u) /* No Interrupt pending */ +#define RTC_RTCRDYIFG (0x0002u) /* RTC ready: RTCRDYIFG */ +#define RTC_RTCTEVIFG (0x0004u) /* RTC interval timer: RTCTEVIFG */ +#define RTC_RTCAIFG (0x0006u) /* RTC user alarm: RTCAIFG */ +#define RTC_RT0PSIFG (0x0008u) /* RTC prescaler 0: RT0PSIFG */ +#define RTC_RT1PSIFG (0x000Au) /* RTC prescaler 1: RT1PSIFG */ +#define RTC_RTCOFIFG (0x000Cu) /* RTC Oscillator fault */ + +#endif +/************************************************************ +* Real Time Clock +************************************************************/ +#ifdef __MSP430_HAS_RTC_C__ /* Definition to show that Module is available */ + +#define OFS_RTCCTL0 (0x0000u) /* Real Timer Clock Control 0/Key */ +#define OFS_RTCCTL0_L OFS_RTCCTL0 +#define OFS_RTCCTL0_H OFS_RTCCTL0+1 +#define OFS_RTCCTL13 (0x0002u) /* Real Timer Clock Control 1/3 */ +#define OFS_RTCCTL13_L OFS_RTCCTL13 +#define OFS_RTCCTL13_H OFS_RTCCTL13+1 +#define RTCCTL1 RTCCTL13_L +#define RTCCTL3 RTCCTL13_H +#define OFS_RTCOCAL (0x0004u) /* Real Timer Clock Offset Calibartion */ +#define OFS_RTCOCAL_L OFS_RTCOCAL +#define OFS_RTCOCAL_H OFS_RTCOCAL+1 +#define OFS_RTCTCMP (0x0006u) /* Real Timer Temperature Compensation */ +#define OFS_RTCTCMP_L OFS_RTCTCMP +#define OFS_RTCTCMP_H OFS_RTCTCMP+1 +#define OFS_RTCPS0CTL (0x0008u) /* Real Timer Prescale Timer 0 Control */ +#define OFS_RTCPS0CTL_L OFS_RTCPS0CTL +#define OFS_RTCPS0CTL_H OFS_RTCPS0CTL+1 +#define OFS_RTCPS1CTL (0x000Au) /* Real Timer Prescale Timer 1 Control */ +#define OFS_RTCPS1CTL_L OFS_RTCPS1CTL +#define OFS_RTCPS1CTL_H OFS_RTCPS1CTL+1 +#define OFS_RTCPS (0x000Cu) /* Real Timer Prescale Timer Control */ +#define OFS_RTCPS_L OFS_RTCPS +#define OFS_RTCPS_H OFS_RTCPS+1 +#define OFS_RTCIV (0x000Eu) /* Real Time Clock Interrupt Vector */ +#define OFS_RTCTIM0 (0x0010u) /* Real Time Clock Time 0 */ +#define OFS_RTCTIM0_L OFS_RTCTIM0 +#define OFS_RTCTIM0_H OFS_RTCTIM0+1 +#define OFS_RTCTIM1 (0x0012u) /* Real Time Clock Time 1 */ +#define OFS_RTCTIM1_L OFS_RTCTIM1 +#define OFS_RTCTIM1_H OFS_RTCTIM1+1 +#define OFS_RTCDATE (0x0014u) /* Real Time Clock Date */ +#define OFS_RTCDATE_L OFS_RTCDATE +#define OFS_RTCDATE_H OFS_RTCDATE+1 +#define OFS_RTCYEAR (0x0016u) /* Real Time Clock Year */ +#define OFS_RTCYEAR_L OFS_RTCYEAR +#define OFS_RTCYEAR_H OFS_RTCYEAR+1 +#define OFS_RTCAMINHR (0x0018u) /* Real Time Clock Alarm Min/Hour */ +#define OFS_RTCAMINHR_L OFS_RTCAMINHR +#define OFS_RTCAMINHR_H OFS_RTCAMINHR+1 +#define OFS_RTCADOWDAY (0x001Au) /* Real Time Clock Alarm day of week/day */ +#define OFS_RTCADOWDAY_L OFS_RTCADOWDAY +#define OFS_RTCADOWDAY_H OFS_RTCADOWDAY+1 +#define OFS_BIN2BCD (0x001Cu) /* Real Time Binary-to-BCD conversion register */ +#define OFS_BCD2BIN (0x001Eu) /* Real Time BCD-to-binary conversion register */ +#define OFS_RTCSEC (0x0010u) +#define OFS_RTCMIN (0x0011u) +#define OFS_RTCHOUR (0x0012u) +#define OFS_RTCDOW (0x0013u) +#define OFS_RTCDAY (0x0014u) +#define OFS_RTCMON (0x0015u) +#define OFS_RTCAMIN (0x0018u) +#define OFS_RTCAHOUR (0x0019u) +#define OFS_RTCADOW (0x001Au) +#define OFS_RTCADAY (0x001Bu) + +#define RTCSEC RTCTIM0_L +#define RTCMIN RTCTIM0_H +#define RTCHOUR RTCTIM1_L +#define RTCDOW RTCTIM1_H +#define RTCDAY RTCDATE_L +#define RTCMON RTCDATE_H +#define RTCYEARL RTCYEAR_L +#define RT0PS RTCPS_L +#define RT1PS RTCPS_H +#define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */ +#define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */ +#define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */ +#define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */ + +/* RTCCTL0 Control Bits */ +#define RTCOFIE (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */ +#define RTCTEVIE (0x0040u) /* RTC Time Event Interrupt Enable Flag */ +#define RTCAIE (0x0020u) /* RTC Alarm Interrupt Enable Flag */ +#define RTCRDYIE (0x0010u) /* RTC Ready Interrupt Enable Flag */ +#define RTCOFIFG (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */ +#define RTCTEVIFG (0x0004u) /* RTC Time Event Interrupt Flag */ +#define RTCAIFG (0x0002u) /* RTC Alarm Interrupt Flag */ +#define RTCRDYIFG (0x0001u) /* RTC Ready Interrupt Flag */ + +/* RTCCTL0 Control Bits */ +#define RTCOFIE_L (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */ +#define RTCTEVIE_L (0x0040u) /* RTC Time Event Interrupt Enable Flag */ +#define RTCAIE_L (0x0020u) /* RTC Alarm Interrupt Enable Flag */ +#define RTCRDYIE_L (0x0010u) /* RTC Ready Interrupt Enable Flag */ +#define RTCOFIFG_L (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */ +#define RTCTEVIFG_L (0x0004u) /* RTC Time Event Interrupt Flag */ +#define RTCAIFG_L (0x0002u) /* RTC Alarm Interrupt Flag */ +#define RTCRDYIFG_L (0x0001u) /* RTC Ready Interrupt Flag */ + +#define RTCKEY (0xA500u) /* RTC Key for RTC write access */ +#define RTCKEY_H (0xA5) /* RTC Key for RTC write access (high word) */ + +/* RTCCTL13 Control Bits */ +#define RTCCALF1 (0x0200u) /* RTC Calibration Frequency Bit 1 */ +#define RTCCALF0 (0x0100u) /* RTC Calibration Frequency Bit 0 */ +#define RTCBCD (0x0080u) /* RTC BCD 0:Binary / 1:BCD */ +#define RTCHOLD (0x0040u) /* RTC Hold */ +#define RTCMODE (0x0020u) /* RTC Mode 0:Counter / 1: Calendar */ +#define RTCRDY (0x0010u) /* RTC Ready */ +#define RTCSSEL1 (0x0008u) /* RTC Source Select 1 */ +#define RTCSSEL0 (0x0004u) /* RTC Source Select 0 */ +#define RTCTEV1 (0x0002u) /* RTC Time Event 1 */ +#define RTCTEV0 (0x0001u) /* RTC Time Event 0 */ + +/* RTCCTL13 Control Bits */ +#define RTCBCD_L (0x0080u) /* RTC BCD 0:Binary / 1:BCD */ +#define RTCHOLD_L (0x0040u) /* RTC Hold */ +#define RTCMODE_L (0x0020u) /* RTC Mode 0:Counter / 1: Calendar */ +#define RTCRDY_L (0x0010u) /* RTC Ready */ +#define RTCSSEL1_L (0x0008u) /* RTC Source Select 1 */ +#define RTCSSEL0_L (0x0004u) /* RTC Source Select 0 */ +#define RTCTEV1_L (0x0002u) /* RTC Time Event 1 */ +#define RTCTEV0_L (0x0001u) /* RTC Time Event 0 */ + +/* RTCCTL13 Control Bits */ +#define RTCCALF1_H (0x0002u) /* RTC Calibration Frequency Bit 1 */ +#define RTCCALF0_H (0x0001u) /* RTC Calibration Frequency Bit 0 */ + +#define RTCSSEL_0 (0x0000u) /* RTC Source Select ACLK */ +#define RTCSSEL_1 (0x0004u) /* RTC Source Select SMCLK */ +#define RTCSSEL_2 (0x0008u) /* RTC Source Select RT1PS */ +#define RTCSSEL_3 (0x000Cu) /* RTC Source Select RT1PS */ +#define RTCSSEL__ACLK (0x0000u) /* RTC Source Select ACLK */ +#define RTCSSEL__SMCLK (0x0004u) /* RTC Source Select SMCLK */ +#define RTCSSEL__RT1PS (0x0008u) /* RTC Source Select RT1PS */ + +#define RTCTEV_0 (0x0000u) /* RTC Time Event: 0 (Min. changed) */ +#define RTCTEV_1 (0x0001u) /* RTC Time Event: 1 (Hour changed) */ +#define RTCTEV_2 (0x0002u) /* RTC Time Event: 2 (12:00 changed) */ +#define RTCTEV_3 (0x0003u) /* RTC Time Event: 3 (00:00 changed) */ +#define RTCTEV__MIN (0x0000u) /* RTC Time Event: 0 (Min. changed) */ +#define RTCTEV__HOUR (0x0001u) /* RTC Time Event: 1 (Hour changed) */ +#define RTCTEV__0000 (0x0002u) /* RTC Time Event: 2 (00:00 changed) */ +#define RTCTEV__1200 (0x0003u) /* RTC Time Event: 3 (12:00 changed) */ + +#define RTCCALF_0 (0x0000u) /* RTC Calibration Frequency: No Output */ +#define RTCCALF_1 (0x0100u) /* RTC Calibration Frequency: 512 Hz */ +#define RTCCALF_2 (0x0200u) /* RTC Calibration Frequency: 256 Hz */ +#define RTCCALF_3 (0x0300u) /* RTC Calibration Frequency: 1 Hz */ + +/* RTCOCAL Control Bits */ +#define RTCOCALS (0x8000u) /* RTC Offset Calibration Sign */ +#define RTCOCAL7 (0x0080u) /* RTC Offset Calibration Bit 7 */ +#define RTCOCAL6 (0x0040u) /* RTC Offset Calibration Bit 6 */ +#define RTCOCAL5 (0x0020u) /* RTC Offset Calibration Bit 5 */ +#define RTCOCAL4 (0x0010u) /* RTC Offset Calibration Bit 4 */ +#define RTCOCAL3 (0x0008u) /* RTC Offset Calibration Bit 3 */ +#define RTCOCAL2 (0x0004u) /* RTC Offset Calibration Bit 2 */ +#define RTCOCAL1 (0x0002u) /* RTC Offset Calibration Bit 1 */ +#define RTCOCAL0 (0x0001u) /* RTC Offset Calibration Bit 0 */ + +/* RTCOCAL Control Bits */ +#define RTCOCAL7_L (0x0080u) /* RTC Offset Calibration Bit 7 */ +#define RTCOCAL6_L (0x0040u) /* RTC Offset Calibration Bit 6 */ +#define RTCOCAL5_L (0x0020u) /* RTC Offset Calibration Bit 5 */ +#define RTCOCAL4_L (0x0010u) /* RTC Offset Calibration Bit 4 */ +#define RTCOCAL3_L (0x0008u) /* RTC Offset Calibration Bit 3 */ +#define RTCOCAL2_L (0x0004u) /* RTC Offset Calibration Bit 2 */ +#define RTCOCAL1_L (0x0002u) /* RTC Offset Calibration Bit 1 */ +#define RTCOCAL0_L (0x0001u) /* RTC Offset Calibration Bit 0 */ + +/* RTCOCAL Control Bits */ +#define RTCOCALS_H (0x0080u) /* RTC Offset Calibration Sign */ + +/* RTCTCMP Control Bits */ +#define RTCTCMPS (0x8000u) /* RTC Temperature Compensation Sign */ +#define RTCTCRDY (0x4000u) /* RTC Temperature compensation ready */ +#define RTCTCOK (0x2000u) /* RTC Temperature compensation write OK */ +#define RTCTCMP7 (0x0080u) /* RTC Temperature Compensation Bit 7 */ +#define RTCTCMP6 (0x0040u) /* RTC Temperature Compensation Bit 6 */ +#define RTCTCMP5 (0x0020u) /* RTC Temperature Compensation Bit 5 */ +#define RTCTCMP4 (0x0010u) /* RTC Temperature Compensation Bit 4 */ +#define RTCTCMP3 (0x0008u) /* RTC Temperature Compensation Bit 3 */ +#define RTCTCMP2 (0x0004u) /* RTC Temperature Compensation Bit 2 */ +#define RTCTCMP1 (0x0002u) /* RTC Temperature Compensation Bit 1 */ +#define RTCTCMP0 (0x0001u) /* RTC Temperature Compensation Bit 0 */ + +/* RTCTCMP Control Bits */ +#define RTCTCMP7_L (0x0080u) /* RTC Temperature Compensation Bit 7 */ +#define RTCTCMP6_L (0x0040u) /* RTC Temperature Compensation Bit 6 */ +#define RTCTCMP5_L (0x0020u) /* RTC Temperature Compensation Bit 5 */ +#define RTCTCMP4_L (0x0010u) /* RTC Temperature Compensation Bit 4 */ +#define RTCTCMP3_L (0x0008u) /* RTC Temperature Compensation Bit 3 */ +#define RTCTCMP2_L (0x0004u) /* RTC Temperature Compensation Bit 2 */ +#define RTCTCMP1_L (0x0002u) /* RTC Temperature Compensation Bit 1 */ +#define RTCTCMP0_L (0x0001u) /* RTC Temperature Compensation Bit 0 */ + +/* RTCTCMP Control Bits */ +#define RTCTCMPS_H (0x0080u) /* RTC Temperature Compensation Sign */ +#define RTCTCRDY_H (0x0040u) /* RTC Temperature compensation ready */ +#define RTCTCOK_H (0x0020u) /* RTC Temperature compensation write OK */ + +#define RTCAE (0x80) /* Real Time Clock Alarm enable */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x8000u) +//#define Reserved (0x4000u) +#define RT0PSDIV2 (0x2000u) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */ +#define RT0PSDIV1 (0x1000u) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */ +#define RT0PSDIV0 (0x0800u) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */ +//#define Reserved (0x0400u) +//#define Reserved (0x0200u) +#define RT0PSHOLD (0x0100u) /* RTC Prescale Timer 0 Hold */ +//#define Reserved (0x0080u) +//#define Reserved (0x0040u) +//#define Reserved (0x0020u) +#define RT0IP2 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ +#define RT0IP1 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ +#define RT0IP0 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ +#define RT0PSIE (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */ +#define RT0PSIFG (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x8000u) +//#define Reserved (0x4000u) +//#define Reserved (0x0400u) +//#define Reserved (0x0200u) +//#define Reserved (0x0080u) +//#define Reserved (0x0040u) +//#define Reserved (0x0020u) +#define RT0IP2_L (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ +#define RT0IP1_L (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ +#define RT0IP0_L (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ +#define RT0PSIE_L (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */ +#define RT0PSIFG_L (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x8000u) +//#define Reserved (0x4000u) +#define RT0PSDIV2_H (0x0020u) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */ +#define RT0PSDIV1_H (0x0010u) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */ +#define RT0PSDIV0_H (0x0008u) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */ +//#define Reserved (0x0400u) +//#define Reserved (0x0200u) +#define RT0PSHOLD_H (0x0001u) /* RTC Prescale Timer 0 Hold */ +//#define Reserved (0x0080u) +//#define Reserved (0x0040u) +//#define Reserved (0x0020u) + +#define RT0IP_0 (0x0000u) /* RTC Prescale Timer 0 Interrupt Interval /2 */ +#define RT0IP_1 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval /4 */ +#define RT0IP_2 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval /8 */ +#define RT0IP_3 (0x000Cu) /* RTC Prescale Timer 0 Interrupt Interval /16 */ +#define RT0IP_4 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval /32 */ +#define RT0IP_5 (0x0014u) /* RTC Prescale Timer 0 Interrupt Interval /64 */ +#define RT0IP_6 (0x0018u) /* RTC Prescale Timer 0 Interrupt Interval /128 */ +#define RT0IP_7 (0x001Cu) /* RTC Prescale Timer 0 Interrupt Interval /256 */ + +/* RTCPS1CTL Control Bits */ +#define RT1SSEL1 (0x8000u) /* RTC Prescale Timer 1 Source Select Bit 1 */ +#define RT1SSEL0 (0x4000u) /* RTC Prescale Timer 1 Source Select Bit 0 */ +#define RT1PSDIV2 (0x2000u) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */ +#define RT1PSDIV1 (0x1000u) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */ +#define RT1PSDIV0 (0x0800u) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */ +//#define Reserved (0x0400u) +//#define Reserved (0x0200u) +#define RT1PSHOLD (0x0100u) /* RTC Prescale Timer 1 Hold */ +//#define Reserved (0x0080u) +//#define Reserved (0x0040u) +//#define Reserved (0x0020u) +#define RT1IP2 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ +#define RT1IP1 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ +#define RT1IP0 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ +#define RT1PSIE (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */ +#define RT1PSIFG (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */ + +/* RTCPS1CTL Control Bits */ +//#define Reserved (0x0400u) +//#define Reserved (0x0200u) +//#define Reserved (0x0080u) +//#define Reserved (0x0040u) +//#define Reserved (0x0020u) +#define RT1IP2_L (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ +#define RT1IP1_L (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ +#define RT1IP0_L (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ +#define RT1PSIE_L (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */ +#define RT1PSIFG_L (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */ + +/* RTCPS1CTL Control Bits */ +#define RT1SSEL1_H (0x0080u) /* RTC Prescale Timer 1 Source Select Bit 1 */ +#define RT1SSEL0_H (0x0040u) /* RTC Prescale Timer 1 Source Select Bit 0 */ +#define RT1PSDIV2_H (0x0020u) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */ +#define RT1PSDIV1_H (0x0010u) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */ +#define RT1PSDIV0_H (0x0008u) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */ +//#define Reserved (0x0400u) +//#define Reserved (0x0200u) +#define RT1PSHOLD_H (0x0001u) /* RTC Prescale Timer 1 Hold */ +//#define Reserved (0x0080u) +//#define Reserved (0x0040u) +//#define Reserved (0x0020u) + +#define RT1IP_0 (0x0000u) /* RTC Prescale Timer 1 Interrupt Interval /2 */ +#define RT1IP_1 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval /4 */ +#define RT1IP_2 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval /8 */ +#define RT1IP_3 (0x000Cu) /* RTC Prescale Timer 1 Interrupt Interval /16 */ +#define RT1IP_4 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval /32 */ +#define RT1IP_5 (0x0014u) /* RTC Prescale Timer 1 Interrupt Interval /64 */ +#define RT1IP_6 (0x0018u) /* RTC Prescale Timer 1 Interrupt Interval /128 */ +#define RT1IP_7 (0x001Cu) /* RTC Prescale Timer 1 Interrupt Interval /256 */ + +/* RTC Definitions */ +#define RTCIV_NONE (0x0000u) /* No Interrupt pending */ +#define RTCIV_RTCOFIFG (0x0002u) /* RTC Osc fault: RTCOFIFG */ +#define RTCIV_RTCRDYIFG (0x0004u) /* RTC ready: RTCRDYIFG */ +#define RTCIV_RTCTEVIFG (0x0006u) /* RTC interval timer: RTCTEVIFG */ +#define RTCIV_RTCAIFG (0x0008u) /* RTC user alarm: RTCAIFG */ +#define RTCIV_RT0PSIFG (0x000Au) /* RTC prescaler 0: RT0PSIFG */ +#define RTCIV_RT1PSIFG (0x000Cu) /* RTC prescaler 1: RT1PSIFG */ + +/* Legacy Definitions */ +#define RTC_NONE (0x0000u) /* No Interrupt pending */ +#define RTC_RTCOFIFG (0x0002u) /* RTC Osc fault: RTCOFIFG */ +#define RTC_RTCRDYIFG (0x0004u) /* RTC ready: RTCRDYIFG */ +#define RTC_RTCTEVIFG (0x0006u) /* RTC interval timer: RTCTEVIFG */ +#define RTC_RTCAIFG (0x0008u) /* RTC user alarm: RTCAIFG */ +#define RTC_RT0PSIFG (0x000Au) /* RTC prescaler 0: RT0PSIFG */ +#define RTC_RT1PSIFG (0x000Cu) /* RTC prescaler 1: RT1PSIFG */ + +#endif +/************************************************************ +* SFR - Special Function Register Module +************************************************************/ +#ifdef __MSP430_HAS_SFR__ /* Definition to show that Module is available */ + +#define OFS_SFRIE1 (0x0000u) /* Interrupt Enable 1 */ +#define OFS_SFRIE1_L OFS_SFRIE1 +#define OFS_SFRIE1_H OFS_SFRIE1+1 + +/* SFRIE1 Control Bits */ +#define WDTIE (0x0001u) /* WDT Interrupt Enable */ +#define OFIE (0x0002u) /* Osc Fault Enable */ +//#define Reserved (0x0004u) +#define VMAIE (0x0008u) /* Vacant Memory Interrupt Enable */ +#define NMIIE (0x0010u) /* NMI Interrupt Enable */ +#define JMBINIE (0x0040u) /* JTAG Mail Box input Interrupt Enable */ +#define JMBOUTIE (0x0080u) /* JTAG Mail Box output Interrupt Enable */ + +#define WDTIE_L (0x0001u) /* WDT Interrupt Enable */ +#define OFIE_L (0x0002u) /* Osc Fault Enable */ +//#define Reserved (0x0004u) +#define VMAIE_L (0x0008u) /* Vacant Memory Interrupt Enable */ +#define NMIIE_L (0x0010u) /* NMI Interrupt Enable */ +#define JMBINIE_L (0x0040u) /* JTAG Mail Box input Interrupt Enable */ +#define JMBOUTIE_L (0x0080u) /* JTAG Mail Box output Interrupt Enable */ + +#define OFS_SFRIFG1 (0x0002u) /* Interrupt Flag 1 */ +#define OFS_SFRIFG1_L OFS_SFRIFG1 +#define OFS_SFRIFG1_H OFS_SFRIFG1+1 +/* SFRIFG1 Control Bits */ +#define WDTIFG (0x0001u) /* WDT Interrupt Flag */ +#define OFIFG (0x0002u) /* Osc Fault Flag */ +//#define Reserved (0x0004u) +#define VMAIFG (0x0008u) /* Vacant Memory Interrupt Flag */ +#define NMIIFG (0x0010u) /* NMI Interrupt Flag */ +//#define Reserved (0x0020u) +#define JMBINIFG (0x0040u) /* JTAG Mail Box input Interrupt Flag */ +#define JMBOUTIFG (0x0080u) /* JTAG Mail Box output Interrupt Flag */ + +#define WDTIFG_L (0x0001u) /* WDT Interrupt Flag */ +#define OFIFG_L (0x0002u) /* Osc Fault Flag */ +//#define Reserved (0x0004u) +#define VMAIFG_L (0x0008u) /* Vacant Memory Interrupt Flag */ +#define NMIIFG_L (0x0010u) /* NMI Interrupt Flag */ +//#define Reserved (0x0020u) +#define JMBINIFG_L (0x0040u) /* JTAG Mail Box input Interrupt Flag */ +#define JMBOUTIFG_L (0x0080u) /* JTAG Mail Box output Interrupt Flag */ + +#define OFS_SFRRPCR (0x0004u) /* RESET Pin Control Register */ +#define OFS_SFRRPCR_L OFS_SFRRPCR +#define OFS_SFRRPCR_H OFS_SFRRPCR+1 +/* SFRRPCR Control Bits */ +#define SYSNMI (0x0001u) /* NMI select */ +#define SYSNMIIES (0x0002u) /* NMI edge select */ +#define SYSRSTUP (0x0004u) /* RESET Pin pull down/up select */ +#define SYSRSTRE (0x0008u) /* RESET Pin Resistor enable */ + +#define SYSNMI_L (0x0001u) /* NMI select */ +#define SYSNMIIES_L (0x0002u) /* NMI edge select */ +#define SYSRSTUP_L (0x0004u) /* RESET Pin pull down/up select */ +#define SYSRSTRE_L (0x0008u) /* RESET Pin Resistor enable */ + +#endif +/************************************************************ +* SYS - System Module +************************************************************/ +#ifdef __MSP430_HAS_SYS__ /* Definition to show that Module is available */ + +#define OFS_SYSCTL (0x0000u) /* System control */ +#define OFS_SYSCTL_L OFS_SYSCTL +#define OFS_SYSCTL_H OFS_SYSCTL+1 +#define OFS_SYSBSLC (0x0002u) /* Boot strap configuration area */ +#define OFS_SYSBSLC_L OFS_SYSBSLC +#define OFS_SYSBSLC_H OFS_SYSBSLC+1 +#define OFS_SYSJMBC (0x0006u) /* JTAG mailbox control */ +#define OFS_SYSJMBC_L OFS_SYSJMBC +#define OFS_SYSJMBC_H OFS_SYSJMBC+1 +#define OFS_SYSJMBI0 (0x0008u) /* JTAG mailbox input 0 */ +#define OFS_SYSJMBI0_L OFS_SYSJMBI0 +#define OFS_SYSJMBI0_H OFS_SYSJMBI0+1 +#define OFS_SYSJMBI1 (0x000Au) /* JTAG mailbox input 1 */ +#define OFS_SYSJMBI1_L OFS_SYSJMBI1 +#define OFS_SYSJMBI1_H OFS_SYSJMBI1+1 +#define OFS_SYSJMBO0 (0x000Cu) /* JTAG mailbox output 0 */ +#define OFS_SYSJMBO0_L OFS_SYSJMBO0 +#define OFS_SYSJMBO0_H OFS_SYSJMBO0+1 +#define OFS_SYSJMBO1 (0x000Eu) /* JTAG mailbox output 1 */ +#define OFS_SYSJMBO1_L OFS_SYSJMBO1 +#define OFS_SYSJMBO1_H OFS_SYSJMBO1+1 + +#define OFS_SYSBERRIV (0x0018u) /* Bus Error vector generator */ +#define OFS_SYSBERRIV_L OFS_SYSBERRIV +#define OFS_SYSBERRIV_H OFS_SYSBERRIV+1 +#define OFS_SYSUNIV (0x001Au) /* User NMI vector generator */ +#define OFS_SYSUNIV_L OFS_SYSUNIV +#define OFS_SYSUNIV_H OFS_SYSUNIV+1 +#define OFS_SYSSNIV (0x001Cu) /* System NMI vector generator */ +#define OFS_SYSSNIV_L OFS_SYSSNIV +#define OFS_SYSSNIV_H OFS_SYSSNIV+1 +#define OFS_SYSRSTIV (0x001Eu) /* Reset vector generator */ +#define OFS_SYSRSTIV_L OFS_SYSRSTIV +#define OFS_SYSRSTIV_H OFS_SYSRSTIV+1 + +/* SYSCTL Control Bits */ +#define SYSRIVECT (0x0001u) /* SYS - RAM based interrupt vectors */ +//#define RESERVED (0x0002u) /* SYS - Reserved */ +#define SYSPMMPE (0x0004u) /* SYS - PMM access protect */ +//#define RESERVED (0x0008u) /* SYS - Reserved */ +#define SYSBSLIND (0x0010u) /* SYS - TCK/RST indication detected */ +#define SYSJTAGPIN (0x0020u) /* SYS - Dedicated JTAG pins enabled */ +//#define RESERVED (0x0040u) /* SYS - Reserved */ +//#define RESERVED (0x0080u) /* SYS - Reserved */ +//#define RESERVED (0x0100u) /* SYS - Reserved */ +//#define RESERVED (0x0200u) /* SYS - Reserved */ +//#define RESERVED (0x0400u) /* SYS - Reserved */ +//#define RESERVED (0x0800u) /* SYS - Reserved */ +//#define RESERVED (0x1000u) /* SYS - Reserved */ +//#define RESERVED (0x2000u) /* SYS - Reserved */ +//#define RESERVED (0x4000u) /* SYS - Reserved */ +//#define RESERVED (0x8000u) /* SYS - Reserved */ + +/* SYSCTL Control Bits */ +#define SYSRIVECT_L (0x0001u) /* SYS - RAM based interrupt vectors */ +//#define RESERVED (0x0002u) /* SYS - Reserved */ +#define SYSPMMPE_L (0x0004u) /* SYS - PMM access protect */ +//#define RESERVED (0x0008u) /* SYS - Reserved */ +#define SYSBSLIND_L (0x0010u) /* SYS - TCK/RST indication detected */ +#define SYSJTAGPIN_L (0x0020u) /* SYS - Dedicated JTAG pins enabled */ +//#define RESERVED (0x0040u) /* SYS - Reserved */ +//#define RESERVED (0x0080u) /* SYS - Reserved */ +//#define RESERVED (0x0100u) /* SYS - Reserved */ +//#define RESERVED (0x0200u) /* SYS - Reserved */ +//#define RESERVED (0x0400u) /* SYS - Reserved */ +//#define RESERVED (0x0800u) /* SYS - Reserved */ +//#define RESERVED (0x1000u) /* SYS - Reserved */ +//#define RESERVED (0x2000u) /* SYS - Reserved */ +//#define RESERVED (0x4000u) /* SYS - Reserved */ +//#define RESERVED (0x8000u) /* SYS - Reserved */ + +/* SYSBSLC Control Bits */ +#define SYSBSLSIZE0 (0x0001u) /* SYS - BSL Protection Size 0 */ +#define SYSBSLSIZE1 (0x0002u) /* SYS - BSL Protection Size 1 */ +#define SYSBSLR (0x0004u) /* SYS - RAM assigned to BSL */ +//#define RESERVED (0x0008u) /* SYS - Reserved */ +//#define RESERVED (0x0010u) /* SYS - Reserved */ +//#define RESERVED (0x0020u) /* SYS - Reserved */ +//#define RESERVED (0x0040u) /* SYS - Reserved */ +//#define RESERVED (0x0080u) /* SYS - Reserved */ +//#define RESERVED (0x0100u) /* SYS - Reserved */ +//#define RESERVED (0x0200u) /* SYS - Reserved */ +//#define RESERVED (0x0400u) /* SYS - Reserved */ +//#define RESERVED (0x0800u) /* SYS - Reserved */ +//#define RESERVED (0x1000u) /* SYS - Reserved */ +//#define RESERVED (0x2000u) /* SYS - Reserved */ +#define SYSBSLOFF (0x4000u) /* SYS - BSL Memory disabled */ +#define SYSBSLPE (0x8000u) /* SYS - BSL Memory protection enabled */ + +/* SYSBSLC Control Bits */ +#define SYSBSLSIZE0_L (0x0001u) /* SYS - BSL Protection Size 0 */ +#define SYSBSLSIZE1_L (0x0002u) /* SYS - BSL Protection Size 1 */ +#define SYSBSLR_L (0x0004u) /* SYS - RAM assigned to BSL */ +//#define RESERVED (0x0008u) /* SYS - Reserved */ +//#define RESERVED (0x0010u) /* SYS - Reserved */ +//#define RESERVED (0x0020u) /* SYS - Reserved */ +//#define RESERVED (0x0040u) /* SYS - Reserved */ +//#define RESERVED (0x0080u) /* SYS - Reserved */ +//#define RESERVED (0x0100u) /* SYS - Reserved */ +//#define RESERVED (0x0200u) /* SYS - Reserved */ +//#define RESERVED (0x0400u) /* SYS - Reserved */ +//#define RESERVED (0x0800u) /* SYS - Reserved */ +//#define RESERVED (0x1000u) /* SYS - Reserved */ +//#define RESERVED (0x2000u) /* SYS - Reserved */ + +/* SYSBSLC Control Bits */ +//#define RESERVED (0x0008u) /* SYS - Reserved */ +//#define RESERVED (0x0010u) /* SYS - Reserved */ +//#define RESERVED (0x0020u) /* SYS - Reserved */ +//#define RESERVED (0x0040u) /* SYS - Reserved */ +//#define RESERVED (0x0080u) /* SYS - Reserved */ +//#define RESERVED (0x0100u) /* SYS - Reserved */ +//#define RESERVED (0x0200u) /* SYS - Reserved */ +//#define RESERVED (0x0400u) /* SYS - Reserved */ +//#define RESERVED (0x0800u) /* SYS - Reserved */ +//#define RESERVED (0x1000u) /* SYS - Reserved */ +//#define RESERVED (0x2000u) /* SYS - Reserved */ +#define SYSBSLOFF_H (0x0040u) /* SYS - BSL Memory disabled */ +#define SYSBSLPE_H (0x0080u) /* SYS - BSL Memory protection enabled */ + +/* SYSJMBC Control Bits */ +#define JMBIN0FG (0x0001u) /* SYS - Incoming JTAG Mailbox 0 Flag */ +#define JMBIN1FG (0x0002u) /* SYS - Incoming JTAG Mailbox 1 Flag */ +#define JMBOUT0FG (0x0004u) /* SYS - Outgoing JTAG Mailbox 0 Flag */ +#define JMBOUT1FG (0x0008u) /* SYS - Outgoing JTAG Mailbox 1 Flag */ +#define JMBMODE (0x0010u) /* SYS - JMB 16/32 Bit Mode */ +//#define RESERVED (0x0020u) /* SYS - Reserved */ +#define JMBCLR0OFF (0x0040u) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */ +#define JMBCLR1OFF (0x0080u) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */ +//#define RESERVED (0x0100u) /* SYS - Reserved */ +//#define RESERVED (0x0200u) /* SYS - Reserved */ +//#define RESERVED (0x0400u) /* SYS - Reserved */ +//#define RESERVED (0x0800u) /* SYS - Reserved */ +//#define RESERVED (0x1000u) /* SYS - Reserved */ +//#define RESERVED (0x2000u) /* SYS - Reserved */ +//#define RESERVED (0x4000u) /* SYS - Reserved */ +//#define RESERVED (0x8000u) /* SYS - Reserved */ + +/* SYSJMBC Control Bits */ +#define JMBIN0FG_L (0x0001u) /* SYS - Incoming JTAG Mailbox 0 Flag */ +#define JMBIN1FG_L (0x0002u) /* SYS - Incoming JTAG Mailbox 1 Flag */ +#define JMBOUT0FG_L (0x0004u) /* SYS - Outgoing JTAG Mailbox 0 Flag */ +#define JMBOUT1FG_L (0x0008u) /* SYS - Outgoing JTAG Mailbox 1 Flag */ +#define JMBMODE_L (0x0010u) /* SYS - JMB 16/32 Bit Mode */ +//#define RESERVED (0x0020u) /* SYS - Reserved */ +#define JMBCLR0OFF_L (0x0040u) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */ +#define JMBCLR1OFF_L (0x0080u) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */ +//#define RESERVED (0x0100u) /* SYS - Reserved */ +//#define RESERVED (0x0200u) /* SYS - Reserved */ +//#define RESERVED (0x0400u) /* SYS - Reserved */ +//#define RESERVED (0x0800u) /* SYS - Reserved */ +//#define RESERVED (0x1000u) /* SYS - Reserved */ +//#define RESERVED (0x2000u) /* SYS - Reserved */ +//#define RESERVED (0x4000u) /* SYS - Reserved */ +//#define RESERVED (0x8000u) /* SYS - Reserved */ + + +#endif +/************************************************************ +* Timerx_A7 +************************************************************/ +#ifdef __MSP430_HAS_TxA7__ /* Definition to show that Module is available */ + +#define OFS_TAxCTL (0x0000u) /* Timerx_A7 Control */ +#define OFS_TAxCCTL0 (0x0002u) /* Timerx_A7 Capture/Compare Control 0 */ +#define OFS_TAxCCTL1 (0x0004u) /* Timerx_A7 Capture/Compare Control 1 */ +#define OFS_TAxCCTL2 (0x0006u) /* Timerx_A7 Capture/Compare Control 2 */ +#define OFS_TAxCCTL3 (0x0008u) /* Timerx_A7 Capture/Compare Control 3 */ +#define OFS_TAxCCTL4 (0x000Au) /* Timerx_A7 Capture/Compare Control 4 */ +#define OFS_TAxCCTL5 (0x000Cu) /* Timerx_A7 Capture/Compare Control 5 */ +#define OFS_TAxCCTL6 (0x000Eu) /* Timerx_A7 Capture/Compare Control 6 */ +#define OFS_TAxR (0x0010u) /* Timerx_A7 */ +#define OFS_TAxCCR0 (0x0012u) /* Timerx_A7 Capture/Compare 0 */ +#define OFS_TAxCCR1 (0x0014u) /* Timerx_A7 Capture/Compare 1 */ +#define OFS_TAxCCR2 (0x0016u) /* Timerx_A7 Capture/Compare 2 */ +#define OFS_TAxCCR3 (0x0018u) /* Timerx_A7 Capture/Compare 3 */ +#define OFS_TAxCCR4 (0x001Au) /* Timerx_A7 Capture/Compare 4 */ +#define OFS_TAxCCR5 (0x001Cu) /* Timerx_A7 Capture/Compare 5 */ +#define OFS_TAxCCR6 (0x001Eu) /* Timerx_A7 Capture/Compare 6 */ +#define OFS_TAxIV (0x002Eu) /* Timerx_A7 Interrupt Vector Word */ +#define OFS_TAxEX0 (0x0020u) /* Timerx_A7 Expansion Register 0 */ + +/* Bits are already defined within the Timer0_Ax */ + +/* TAxIV Definitions */ +#define TAxIV_NONE (0x0000u) /* No Interrupt pending */ +#define TAxIV_TACCR1 (0x0002u) /* TAxCCR1_CCIFG */ +#define TAxIV_TACCR2 (0x0004u) /* TAxCCR2_CCIFG */ +#define TAxIV_TACCR3 (0x0006u) /* TAxCCR3_CCIFG */ +#define TAxIV_TACCR4 (0x0008u) /* TAxCCR4_CCIFG */ +#define TAxIV_TACCR5 (0x000Au) /* TAxCCR5_CCIFG */ +#define TAxIV_TACCR6 (0x000Cu) /* TAxCCR6_CCIFG */ +#define TAxIV_TAIFG (0x000Eu) /* TAxIFG */ + +/* Legacy Defines */ +#define TAxIV_TAxCCR1 (0x0002u) /* TAxCCR1_CCIFG */ +#define TAxIV_TAxCCR2 (0x0004u) /* TAxCCR2_CCIFG */ +#define TAxIV_TAxCCR3 (0x0006u) /* TAxCCR3_CCIFG */ +#define TAxIV_TAxCCR4 (0x0008u) /* TAxCCR4_CCIFG */ +#define TAxIV_TAxCCR5 (0x000Au) /* TAxCCR5_CCIFG */ +#define TAxIV_TAxCCR6 (0x000Cu) /* TAxCCR6_CCIFG */ +#define TAxIV_TAxIFG (0x000Eu) /* TAxIFG */ + +/* TAxCTL Control Bits */ +#define TASSEL1 (0x0200u) /* Timer A clock source select 1 */ +#define TASSEL0 (0x0100u) /* Timer A clock source select 0 */ +#define ID1 (0x0080u) /* Timer A clock input divider 1 */ +#define ID0 (0x0040u) /* Timer A clock input divider 0 */ +#define MC1 (0x0020u) /* Timer A mode control 1 */ +#define MC0 (0x0010u) /* Timer A mode control 0 */ +#define TACLR (0x0004u) /* Timer A counter clear */ +#define TAIE (0x0002u) /* Timer A counter interrupt enable */ +#define TAIFG (0x0001u) /* Timer A counter interrupt flag */ + +#define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */ +#define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */ +#define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continuous up */ +#define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */ +#define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */ +#define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */ +#define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */ +#define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */ +#define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */ +#define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */ +#define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */ +#define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */ +#define MC__STOP (0*0x10u) /* Timer A mode control: 0 - Stop */ +#define MC__UP (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */ +#define MC__CONTINUOUS (2*0x10u) /* Timer A mode control: 2 - Continuous up */ +#define MC__CONTINOUS (2*0x10u) /* Legacy define */ +#define MC__UPDOWN (3*0x10u) /* Timer A mode control: 3 - Up/Down */ +#define ID__1 (0*0x40u) /* Timer A input divider: 0 - /1 */ +#define ID__2 (1*0x40u) /* Timer A input divider: 1 - /2 */ +#define ID__4 (2*0x40u) /* Timer A input divider: 2 - /4 */ +#define ID__8 (3*0x40u) /* Timer A input divider: 3 - /8 */ +#define TASSEL__TACLK (0*0x100u) /* Timer A clock source select: 0 - TACLK */ +#define TASSEL__ACLK (1*0x100u) /* Timer A clock source select: 1 - ACLK */ +#define TASSEL__SMCLK (2*0x100u) /* Timer A clock source select: 2 - SMCLK */ +#define TASSEL__INCLK (3*0x100u) /* Timer A clock source select: 3 - INCLK */ + +/* TAxCCTLx Control Bits */ +#define CM1 (0x8000u) /* Capture mode 1 */ +#define CM0 (0x4000u) /* Capture mode 0 */ +#define CCIS1 (0x2000u) /* Capture input select 1 */ +#define CCIS0 (0x1000u) /* Capture input select 0 */ +#define SCS (0x0800u) /* Capture sychronize */ +#define SCCI (0x0400u) /* Latched capture signal (read) */ +#define CAP (0x0100u) /* Capture mode: 1 /Compare mode : 0 */ +#define OUTMOD2 (0x0080u) /* Output mode 2 */ +#define OUTMOD1 (0x0040u) /* Output mode 1 */ +#define OUTMOD0 (0x0020u) /* Output mode 0 */ +#define CCIE (0x0010u) /* Capture/compare interrupt enable */ +#define CCI (0x0008u) /* Capture input signal (read) */ +#define OUT (0x0004u) /* PWM Output signal if output mode 0 */ +#define COV (0x0002u) /* Capture/compare overflow flag */ +#define CCIFG (0x0001u) /* Capture/compare interrupt flag */ + +#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */ +#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */ +#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */ +#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */ +#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */ +#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */ +#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */ +#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */ +#define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */ +#define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */ +#define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */ +#define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */ +#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */ +#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */ +#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */ +#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */ + +/* TAxEX0 Control Bits */ +#define TAIDEX0 (0x0001u) /* Timer A Input divider expansion Bit: 0 */ +#define TAIDEX1 (0x0002u) /* Timer A Input divider expansion Bit: 1 */ +#define TAIDEX2 (0x0004u) /* Timer A Input divider expansion Bit: 2 */ + +#define TAIDEX_0 (0*0x0001u) /* Timer A Input divider expansion : /1 */ +#define TAIDEX_1 (1*0x0001u) /* Timer A Input divider expansion : /2 */ +#define TAIDEX_2 (2*0x0001u) /* Timer A Input divider expansion : /3 */ +#define TAIDEX_3 (3*0x0001u) /* Timer A Input divider expansion : /4 */ +#define TAIDEX_4 (4*0x0001u) /* Timer A Input divider expansion : /5 */ +#define TAIDEX_5 (5*0x0001u) /* Timer A Input divider expansion : /6 */ +#define TAIDEX_6 (6*0x0001u) /* Timer A Input divider expansion : /7 */ +#define TAIDEX_7 (7*0x0001u) /* Timer A Input divider expansion : /8 */ + +#endif +/************************************************************ +* Timerx_B7 +************************************************************/ +#ifdef __MSP430_HAS_TxB7__ /* Definition to show that Module is available */ + +#define OFS_TBxCTL (0x0000u) /* Timerx_B7 Control */ +#define OFS_TBxCCTL0 (0x0002u) /* Timerx_B7 Capture/Compare Control 0 */ +#define OFS_TBxCCTL1 (0x0004u) /* Timerx_B7 Capture/Compare Control 1 */ +#define OFS_TBxCCTL2 (0x0006u) /* Timerx_B7 Capture/Compare Control 2 */ +#define OFS_TBxCCTL3 (0x0008u) /* Timerx_B7 Capture/Compare Control 3 */ +#define OFS_TBxCCTL4 (0x000Au) /* Timerx_B7 Capture/Compare Control 4 */ +#define OFS_TBxCCTL5 (0x000Cu) /* Timerx_B7 Capture/Compare Control 5 */ +#define OFS_TBxCCTL6 (0x000Eu) /* Timerx_B7 Capture/Compare Control 6 */ +#define OFS_TBxR (0x0010u) /* Timerx_B7 */ +#define OFS_TBxCCR0 (0x0012u) /* Timerx_B7 Capture/Compare 0 */ +#define OFS_TBxCCR1 (0x0014u) /* Timerx_B7 Capture/Compare 1 */ +#define OFS_TBxCCR2 (0x0016u) /* Timerx_B7 Capture/Compare 2 */ +#define OFS_TBxCCR3 (0x0018u) /* Timerx_B7 Capture/Compare 3 */ +#define OFS_TBxCCR4 (0x001Au) /* Timerx_B7 Capture/Compare 4 */ +#define OFS_TBxCCR5 (0x001Cu) /* Timerx_B7 Capture/Compare 5 */ +#define OFS_TBxCCR6 (0x001Eu) /* Timerx_B7 Capture/Compare 6 */ +#define OFS_TBxIV (0x002Eu) /* Timerx_B7 Interrupt Vector Word */ +#define OFS_TBxEX0 (0x0020u) /* Timerx_B7 Expansion Register 0 */ + +/* Bits are already defined within the Timer0_Ax */ + +/* TBxIV Definitions */ +#define TBxIV_NONE (0x0000u) /* No Interrupt pending */ +#define TBxIV_TBCCR1 (0x0002u) /* TBxCCR1_CCIFG */ +#define TBxIV_TBCCR2 (0x0004u) /* TBxCCR2_CCIFG */ +#define TBxIV_TBCCR3 (0x0006u) /* TBxCCR3_CCIFG */ +#define TBxIV_TBCCR4 (0x0008u) /* TBxCCR4_CCIFG */ +#define TBxIV_TBCCR5 (0x000Au) /* TBxCCR5_CCIFG */ +#define TBxIV_TBCCR6 (0x000Cu) /* TBxCCR6_CCIFG */ +#define TBxIV_TBIFG (0x000Eu) /* TBxIFG */ + +/* Legacy Defines */ +#define TBxIV_TBxCCR1 (0x0002u) /* TBxCCR1_CCIFG */ +#define TBxIV_TBxCCR2 (0x0004u) /* TBxCCR2_CCIFG */ +#define TBxIV_TBxCCR3 (0x0006u) /* TBxCCR3_CCIFG */ +#define TBxIV_TBxCCR4 (0x0008u) /* TBxCCR4_CCIFG */ +#define TBxIV_TBxCCR5 (0x000Au) /* TBxCCR5_CCIFG */ +#define TBxIV_TBxCCR6 (0x000Cu) /* TBxCCR6_CCIFG */ +#define TBxIV_TBxIFG (0x000Eu) /* TBxIFG */ + +/* TBxCTL Control Bits */ +#define TBCLGRP1 (0x4000u) /* Timer_B7 Compare latch load group 1 */ +#define TBCLGRP0 (0x2000u) /* Timer_B7 Compare latch load group 0 */ +#define CNTL1 (0x1000u) /* Counter lenght 1 */ +#define CNTL0 (0x0800u) /* Counter lenght 0 */ +#define TBSSEL1 (0x0200u) /* Clock source 1 */ +#define TBSSEL0 (0x0100u) /* Clock source 0 */ +#define TBCLR (0x0004u) /* Timer_B7 counter clear */ +#define TBIE (0x0002u) /* Timer_B7 interrupt enable */ +#define TBIFG (0x0001u) /* Timer_B7 interrupt flag */ + +#define SHR1 (0x4000u) /* Timer_B7 Compare latch load group 1 */ +#define SHR0 (0x2000u) /* Timer_B7 Compare latch load group 0 */ + +#define TBSSEL_0 (0*0x0100u) /* Clock Source: TBCLK */ +#define TBSSEL_1 (1*0x0100u) /* Clock Source: ACLK */ +#define TBSSEL_2 (2*0x0100u) /* Clock Source: SMCLK */ +#define TBSSEL_3 (3*0x0100u) /* Clock Source: INCLK */ +#define CNTL_0 (0*0x0800u) /* Counter lenght: 16 bit */ +#define CNTL_1 (1*0x0800u) /* Counter lenght: 12 bit */ +#define CNTL_2 (2*0x0800u) /* Counter lenght: 10 bit */ +#define CNTL_3 (3*0x0800u) /* Counter lenght: 8 bit */ +#define SHR_0 (0*0x2000u) /* Timer_B7 Group: 0 - individually */ +#define SHR_1 (1*0x2000u) /* Timer_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */ +#define SHR_2 (2*0x2000u) /* Timer_B7 Group: 2 - 2 groups (1-3, 4-6)*/ +#define SHR_3 (3*0x2000u) /* Timer_B7 Group: 3 - 1 group (all) */ +#define TBCLGRP_0 (0*0x2000u) /* Timer_B7 Group: 0 - individually */ +#define TBCLGRP_1 (1*0x2000u) /* Timer_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */ +#define TBCLGRP_2 (2*0x2000u) /* Timer_B7 Group: 2 - 2 groups (1-3, 4-6)*/ +#define TBCLGRP_3 (3*0x2000u) /* Timer_B7 Group: 3 - 1 group (all) */ +#define TBSSEL__TBCLK (0*0x100u) /* Timer0_B7 clock source select: 0 - TBCLK */ +#define TBSSEL__TACLK (0*0x100u) /* Timer0_B7 clock source select: 0 - TBCLK (legacy) */ +#define TBSSEL__ACLK (1*0x100u) /* Timer_B7 clock source select: 1 - ACLK */ +#define TBSSEL__SMCLK (2*0x100u) /* Timer_B7 clock source select: 2 - SMCLK */ +#define TBSSEL__INCLK (3*0x100u) /* Timer_B7 clock source select: 3 - INCLK */ +#define CNTL__16 (0*0x0800u) /* Counter lenght: 16 bit */ +#define CNTL__12 (1*0x0800u) /* Counter lenght: 12 bit */ +#define CNTL__10 (2*0x0800u) /* Counter lenght: 10 bit */ +#define CNTL__8 (3*0x0800u) /* Counter lenght: 8 bit */ + +/* Additional Timer B Control Register bits are defined in Timer A */ +/* TBxCCTLx Control Bits */ +#define CLLD1 (0x0400u) /* Compare latch load source 1 */ +#define CLLD0 (0x0200u) /* Compare latch load source 0 */ + +#define SLSHR1 (0x0400u) /* Compare latch load source 1 */ +#define SLSHR0 (0x0200u) /* Compare latch load source 0 */ + +#define SLSHR_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */ +#define SLSHR_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */ +#define SLSHR_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */ +#define SLSHR_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */ + +#define CLLD_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */ +#define CLLD_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */ +#define CLLD_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */ +#define CLLD_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */ + +/* TBxEX0 Control Bits */ +#define TBIDEX0 (0x0001u) /* Timer_B7 Input divider expansion Bit: 0 */ +#define TBIDEX1 (0x0002u) /* Timer_B7 Input divider expansion Bit: 1 */ +#define TBIDEX2 (0x0004u) /* Timer_B7 Input divider expansion Bit: 2 */ + +#define TBIDEX_0 (0*0x0001u) /* Timer_B7 Input divider expansion : /1 */ +#define TBIDEX_1 (1*0x0001u) /* Timer_B7 Input divider expansion : /2 */ +#define TBIDEX_2 (2*0x0001u) /* Timer_B7 Input divider expansion : /3 */ +#define TBIDEX_3 (3*0x0001u) /* Timer_B7 Input divider expansion : /4 */ +#define TBIDEX_4 (4*0x0001u) /* Timer_B7 Input divider expansion : /5 */ +#define TBIDEX_5 (5*0x0001u) /* Timer_B7 Input divider expansion : /6 */ +#define TBIDEX_6 (6*0x0001u) /* Timer_B7 Input divider expansion : /7 */ +#define TBIDEX_7 (7*0x0001u) /* Timer_B7 Input divider expansion : /8 */ +#define TBIDEX__1 (0*0x0001u) /* Timer_B7 Input divider expansion : /1 */ +#define TBIDEX__2 (1*0x0001u) /* Timer_B7 Input divider expansion : /2 */ +#define TBIDEX__3 (2*0x0001u) /* Timer_B7 Input divider expansion : /3 */ +#define TBIDEX__4 (3*0x0001u) /* Timer_B7 Input divider expansion : /4 */ +#define TBIDEX__5 (4*0x0001u) /* Timer_B7 Input divider expansion : /5 */ +#define TBIDEX__6 (5*0x0001u) /* Timer_B7 Input divider expansion : /6 */ +#define TBIDEX__7 (6*0x0001u) /* Timer_B7 Input divider expansion : /7 */ +#define TBIDEX__8 (7*0x0001u) /* Timer_B7 Input divider expansion : /8 */ + + +#define ID1 (0x0080u) /* Timer B clock input divider 1 */ +#define ID0 (0x0040u) /* Timer B clock input divider 0 */ +#define MC1 (0x0020u) /* Timer B mode control 1 */ +#define MC0 (0x0010u) /* Timer B mode control 0 */ +#define MC__STOP (0*0x10u) /* Timer B mode control: 0 - Stop */ +#define MC__UP (1*0x10u) /* Timer B mode control: 1 - Up to CCR0 */ +#define MC__CONTINUOUS (2*0x10u) /* Timer B mode control: 2 - Continuous up */ +#define MC__CONTINOUS (2*0x10u) /* Legacy define */ +#define MC__UPDOWN (3*0x10u) /* Timer B mode control: 3 - Up/Down */ +#define CM1 (0x8000u) /* Capture mode 1 */ +#define CM0 (0x4000u) /* Capture mode 0 */ +#define MC_0 (0*0x10u) /* Timer B mode control: 0 - Stop */ +#define MC_1 (1*0x10u) /* Timer B mode control: 1 - Up to CCR0 */ +#define MC_2 (2*0x10u) /* Timer B mode control: 2 - Continuous up */ +#define MC_3 (3*0x10u) /* Timer B mode control: 3 - Up/Down */ +#define CAP (0x0100u) /* Capture mode: 1 /Compare mode : 0 */ +#define CCIE (0x0010u) /* Capture/compare interrupt enable */ +#define CCIFG (0x0001u) /* Capture/compare interrupt flag */ +#define CCIS_0 (0*0x1000u) +#define CCIS_1 (1*0x1000u) +#define CCIS_2 (2*0x1000u) +#define CCIS_3 (3*0x1000u) +#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */ +#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */ +#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */ +#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */ +#define OUT (0x0004u) /* PWM Output signal if output mode 0 */ +#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */ +#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */ +#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */ +#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */ +#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */ +#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */ +#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */ +#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */ +#define SCCI (0x0400u) /* Latched capture signal (read) */ +#define SCS (0x0800u) /* Capture sychronize */ +#define CCI (0x0008u) /* Capture input signal (read) */ +#define ID__1 (0*0x40u) /* Timer B input divider: 0 - /1 */ +#define ID__2 (1*0x40u) /* Timer B input divider: 1 - /2 */ +#define ID__4 (2*0x40u) /* Timer B input divider: 2 - /4 */ +#define ID__8 (3*0x40u) /* Timer B input divider: 3 - /8 */ +#define ID_0 (0*0x40u) /* Timer B input divider: 0 - /1 */ +#define ID_1 (1*0x40u) /* Timer B input divider: 1 - /2 */ +#define ID_2 (2*0x40u) /* Timer B input divider: 2 - /4 */ +#define ID_3 (3*0x40u) /* Timer B input divider: 3 - /8 */ + +#endif +/************************************************************ +* USCI Ax +************************************************************/ +#ifdef __MSP430_HAS_EUSCI_Ax__ /* Definition to show that Module is available */ + +#define OFS_UCAxCTLW0 (0x0000u) /* USCI Ax Control Word Register 0 */ +#define OFS_UCAxCTLW0_L OFS_UCAxCTLW0 +#define OFS_UCAxCTLW0_H OFS_UCAxCTLW0+1 +#define OFS_UCAxCTL0 (0x0001u) +#define OFS_UCAxCTL1 (0x0000u) +#define UCAxCTL1 UCAxCTLW0_L /* USCI Ax Control Register 1 */ +#define UCAxCTL0 UCAxCTLW0_H /* USCI Ax Control Register 0 */ +#define OFS_UCAxCTLW1 (0x0002u) /* USCI Ax Control Word Register 1 */ +#define OFS_UCAxCTLW1_L OFS_UCAxCTLW1 +#define OFS_UCAxCTLW1_H OFS_UCAxCTLW1+1 +#define OFS_UCAxBRW (0x0006u) /* USCI Ax Baud Word Rate 0 */ +#define OFS_UCAxBRW_L OFS_UCAxBRW +#define OFS_UCAxBRW_H OFS_UCAxBRW+1 +#define OFS_UCAxBR0 (0x0006u) +#define OFS_UCAxBR1 (0x0007u) +#define UCAxBR0 UCAxBRW_L /* USCI Ax Baud Rate 0 */ +#define UCAxBR1 UCAxBRW_H /* USCI Ax Baud Rate 1 */ +#define OFS_UCAxMCTLW (0x0008u) /* USCI Ax Modulation Control */ +#define OFS_UCAxMCTLW_L OFS_UCAxMCTLW +#define OFS_UCAxMCTLW_H OFS_UCAxMCTLW+1 +#define OFS_UCAxSTATW (0x000Au) /* USCI Ax Status Register */ +#define OFS_UCAxRXBUF (0x000Cu) /* USCI Ax Receive Buffer */ +#define OFS_UCAxRXBUF_L OFS_UCAxRXBUF +#define OFS_UCAxRXBUF_H OFS_UCAxRXBUF+1 +#define OFS_UCAxTXBUF (0x000Eu) /* USCI Ax Transmit Buffer */ +#define OFS_UCAxTXBUF_L OFS_UCAxTXBUF +#define OFS_UCAxTXBUF_H OFS_UCAxTXBUF+1 +#define OFS_UCAxABCTL (0x0010u) /* USCI Ax LIN Control */ +#define OFS_UCAxIRCTL (0x0012u) /* USCI Ax IrDA Transmit Control */ +#define OFS_UCAxIRCTL_L OFS_UCAxIRCTL +#define OFS_UCAxIRCTL_H OFS_UCAxIRCTL+1 +#define OFS_UCAxIRTCTL (0x0012u) +#define OFS_UCAxIRRCTL (0x0013u) +#define UCAxIRTCTL UCAxIRCTL_L /* USCI Ax IrDA Transmit Control */ +#define UCAxIRRCTL UCAxIRCTL_H /* USCI Ax IrDA Receive Control */ +#define OFS_UCAxIE (0x001Au) /* USCI Ax Interrupt Enable Register */ +#define OFS_UCAxIE_L OFS_UCAxIE +#define OFS_UCAxIE_H OFS_UCAxIE+1 +#define OFS_UCAxIFG (0x001Cu) /* USCI Ax Interrupt Flags Register */ +#define OFS_UCAxIFG_L OFS_UCAxIFG +#define OFS_UCAxIFG_H OFS_UCAxIFG+1 +#define OFS_UCAxIE__UART (0x001Au) +#define OFS_UCAxIE__UART_L OFS_UCAxIE__UART +#define OFS_UCAxIE__UART_H OFS_UCAxIE__UART+1 +#define OFS_UCAxIFG__UART (0x001Cu) +#define OFS_UCAxIFG__UART_L OFS_UCAxIFG__UART +#define OFS_UCAxIFG__UART_H OFS_UCAxIFG__UART+1 +#define OFS_UCAxIV (0x001Eu) /* USCI Ax Interrupt Vector Register */ + +#define OFS_UCAxCTLW0__SPI (0x0000u) +#define OFS_UCAxCTLW0__SPI_L OFS_UCAxCTLW0__SPI +#define OFS_UCAxCTLW0__SPI_H OFS_UCAxCTLW0__SPI+1 +#define OFS_UCAxCTL0__SPI (0x0001u) +#define OFS_UCAxCTL1__SPI (0x0000u) +#define OFS_UCAxBRW__SPI (0x0006u) +#define OFS_UCAxBRW__SPI_L OFS_UCAxBRW__SPI +#define OFS_UCAxBRW__SPI_H OFS_UCAxBRW__SPI+1 +#define OFS_UCAxBR0__SPI (0x0006u) +#define OFS_UCAxBR1__SPI (0x0007u) +#define OFS_UCAxSTATW__SPI (0x000Au) +#define OFS_UCAxRXBUF__SPI (0x000Cu) +#define OFS_UCAxRXBUF__SPI_L OFS_UCAxRXBUF__SPI +#define OFS_UCAxRXBUF__SPI_H OFS_UCAxRXBUF__SPI+1 +#define OFS_UCAxTXBUF__SPI (0x000Eu) +#define OFS_UCAxTXBUF__SPI_L OFS_UCAxTXBUF__SPI +#define OFS_UCAxTXBUF__SPI_H OFS_UCAxTXBUF__SPI+1 +#define OFS_UCAxIE__SPI (0x001Au) +#define OFS_UCAxIFG__SPI (0x001Cu) +#define OFS_UCAxIV__SPI (0x001Eu) + +#endif +/************************************************************ +* USCI Bx +************************************************************/ +#ifdef __MSP430_HAS_EUSCI_Bx__ /* Definition to show that Module is available */ + +#define OFS_UCBxCTLW0__SPI (0x0000u) +#define OFS_UCBxCTLW0__SPI_L OFS_UCBxCTLW0__SPI +#define OFS_UCBxCTLW0__SPI_H OFS_UCBxCTLW0__SPI+1 +#define OFS_UCBxCTL0__SPI (0x0001u) +#define OFS_UCBxCTL1__SPI (0x0000u) +#define OFS_UCBxBRW__SPI (0x0006u) +#define OFS_UCBxBRW__SPI_L OFS_UCBxBRW__SPI +#define OFS_UCBxBRW__SPI_H OFS_UCBxBRW__SPI+1 +#define OFS_UCBxBR0__SPI (0x0006u) +#define OFS_UCBxBR1__SPI (0x0007u) +#define OFS_UCBxSTATW__SPI (0x0008u) +#define OFS_UCBxSTATW__SPI_L OFS_UCBxSTATW__SPI +#define OFS_UCBxSTATW__SPI_H OFS_UCBxSTATW__SPI+1 +#define OFS_UCBxRXBUF__SPI (0x000Cu) +#define OFS_UCBxRXBUF__SPI_L OFS_UCBxRXBUF__SPI +#define OFS_UCBxRXBUF__SPI_H OFS_UCBxRXBUF__SPI+1 +#define OFS_UCBxTXBUF__SPI (0x000Eu) +#define OFS_UCBxTXBUF__SPI_L OFS_UCBxTXBUF__SPI +#define OFS_UCBxTXBUF__SPI_H OFS_UCBxTXBUF__SPI+1 +#define OFS_UCBxIE__SPI (0x002Au) +#define OFS_UCBxIE__SPI_L OFS_UCBxIE__SPI +#define OFS_UCBxIE__SPI_H OFS_UCBxIE__SPI+1 +#define OFS_UCBxIFG__SPI (0x002Cu) +#define OFS_UCBxIFG__SPI_L OFS_UCBxIFG__SPI +#define OFS_UCBxIFG__SPI_H OFS_UCBxIFG__SPI+1 +#define OFS_UCBxIV__SPI (0x002Eu) + +#define OFS_UCBxCTLW0 (0x0000u) /* USCI Bx Control Word Register 0 */ +#define OFS_UCBxCTLW0_L OFS_UCBxCTLW0 +#define OFS_UCBxCTLW0_H OFS_UCBxCTLW0+1 +#define OFS_UCBxCTL0 (0x0001u) +#define OFS_UCBxCTL1 (0x0000u) +#define UCBxCTL1 UCBxCTLW0_L /* USCI Bx Control Register 1 */ +#define UCBxCTL0 UCBxCTLW0_H /* USCI Bx Control Register 0 */ +#define OFS_UCBxCTLW1 (0x0002u) /* USCI Bx Control Word Register 1 */ +#define OFS_UCBxCTLW1_L OFS_UCBxCTLW1 +#define OFS_UCBxCTLW1_H OFS_UCBxCTLW1+1 +#define OFS_UCBxBRW (0x0006u) /* USCI Bx Baud Word Rate 0 */ +#define OFS_UCBxBRW_L OFS_UCBxBRW +#define OFS_UCBxBRW_H OFS_UCBxBRW+1 +#define OFS_UCBxBR0 (0x0006u) +#define OFS_UCBxBR1 (0x0007u) +#define UCBxBR0 UCBxBRW_L /* USCI Bx Baud Rate 0 */ +#define UCBxBR1 UCBxBRW_H /* USCI Bx Baud Rate 1 */ +#define OFS_UCBxSTATW (0x0008u) /* USCI Bx Status Word Register */ +#define OFS_UCBxSTATW_L OFS_UCBxSTATW +#define OFS_UCBxSTATW_H OFS_UCBxSTATW+1 +#define OFS_UCBxSTATW__I2C (0x0008u) +#define OFS_UCBxSTAT__I2C (0x0008u) +#define OFS_UCBxBCNT__I2C (0x0009u) +#define UCBxSTAT UCBxSTATW_L /* USCI Bx Status Register */ +#define UCBxBCNT UCBxSTATW_H /* USCI Bx Byte Counter Register */ +#define OFS_UCBxTBCNT (0x000Au) /* USCI Bx Byte Counter Threshold Register */ +#define OFS_UCBxTBCNT_L OFS_UCBxTBCNT +#define OFS_UCBxTBCNT_H OFS_UCBxTBCNT+1 +#define OFS_UCBxRXBUF (0x000Cu) /* USCI Bx Receive Buffer */ +#define OFS_UCBxRXBUF_L OFS_UCBxRXBUF +#define OFS_UCBxRXBUF_H OFS_UCBxRXBUF+1 +#define OFS_UCBxTXBUF (0x000Eu) /* USCI Bx Transmit Buffer */ +#define OFS_UCBxTXBUF_L OFS_UCBxTXBUF +#define OFS_UCBxTXBUF_H OFS_UCBxTXBUF+1 +#define OFS_UCBxI2COA0 (0x0014u) /* USCI Bx I2C Own Address 0 */ +#define OFS_UCBxI2COA0_L OFS_UCBxI2COA0 +#define OFS_UCBxI2COA0_H OFS_UCBxI2COA0+1 +#define OFS_UCBxI2COA1 (0x0016u) /* USCI Bx I2C Own Address 1 */ +#define OFS_UCBxI2COA1_L OFS_UCBxI2COA1 +#define OFS_UCBxI2COA1_H OFS_UCBxI2COA1+1 +#define OFS_UCBxI2COA2 (0x0018u) /* USCI Bx I2C Own Address 2 */ +#define OFS_UCBxI2COA2_L OFS_UCBxI2COA2 +#define OFS_UCBxI2COA2_H OFS_UCBxI2COA2+1 +#define OFS_UCBxI2COA3 (0x001Au) /* USCI Bx I2C Own Address 3 */ +#define OFS_UCBxI2COA3_L OFS_UCBxI2COA3 +#define OFS_UCBxI2COA3_H OFS_UCBxI2COA3+1 +#define OFS_UCBxADDRX (0x001Cu) /* USCI Bx Received Address Register */ +#define OFS_UCBxADDRX_L OFS_UCBxADDRX +#define OFS_UCBxADDRX_H OFS_UCBxADDRX+1 +#define OFS_UCBxADDMASK (0x001Eu) /* USCI Bx Address Mask Register */ +#define OFS_UCBxADDMASK_L OFS_UCBxADDMASK +#define OFS_UCBxADDMASK_H OFS_UCBxADDMASK+1 +#define OFS_UCBxI2CSA (0x0020u) /* USCI Bx I2C Slave Address */ +#define OFS_UCBxI2CSA_L OFS_UCBxI2CSA +#define OFS_UCBxI2CSA_H OFS_UCBxI2CSA+1 +#define OFS_UCBxIE (0x002Au) /* USCI Bx Interrupt Enable Register */ +#define OFS_UCBxIE_L OFS_UCBxIE +#define OFS_UCBxIE_H OFS_UCBxIE+1 +#define OFS_UCBxIFG (0x002Cu) /* USCI Bx Interrupt Flags Register */ +#define OFS_UCBxIFG_L OFS_UCBxIFG +#define OFS_UCBxIFG_H OFS_UCBxIFG+1 +#define OFS_UCBxIE__I2C (0x002Au) +#define OFS_UCBxIE__I2C_L OFS_UCBxIE__I2C +#define OFS_UCBxIE__I2C_H OFS_UCBxIE__I2C+1 +#define OFS_UCBxIFG__I2C (0x002Cu) +#define OFS_UCBxIFG__I2C_L OFS_UCBxIFG__I2C +#define OFS_UCBxIFG__I2C_H OFS_UCBxIFG__I2C+1 +#define OFS_UCBxIV (0x002Eu) /* USCI Bx Interrupt Vector Register */ + +#endif +#if (defined(__MSP430_HAS_EUSCI_Ax__) || defined(__MSP430_HAS_EUSCI_Bx__)) + +// UCAxCTLW0 UART-Mode Control Bits +#define UCPEN (0x8000u) /* Async. Mode: Parity enable */ +#define UCPAR (0x4000u) /* Async. Mode: Parity 0:odd / 1:even */ +#define UCMSB (0x2000u) /* Async. Mode: MSB first 0:LSB / 1:MSB */ +#define UC7BIT (0x1000u) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */ +#define UCSPB (0x0800u) /* Async. Mode: Stop Bits 0:one / 1: two */ +#define UCMODE1 (0x0400u) /* Async. Mode: USCI Mode 1 */ +#define UCMODE0 (0x0200u) /* Async. Mode: USCI Mode 0 */ +#define UCSYNC (0x0100u) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */ +#define UCSSEL1 (0x0080u) /* USCI 0 Clock Source Select 1 */ +#define UCSSEL0 (0x0040u) /* USCI 0 Clock Source Select 0 */ +#define UCRXEIE (0x0020u) /* RX Error interrupt enable */ +#define UCBRKIE (0x0010u) /* Break interrupt enable */ +#define UCDORM (0x0008u) /* Dormant (Sleep) Mode */ +#define UCTXADDR (0x0004u) /* Send next Data as Address */ +#define UCTXBRK (0x0002u) /* Send next Data as Break */ +#define UCSWRST (0x0001u) /* USCI Software Reset */ + +// UCAxCTLW0 UART-Mode Control Bits +#define UCSSEL1_L (0x0080u) /* USCI 0 Clock Source Select 1 */ +#define UCSSEL0_L (0x0040u) /* USCI 0 Clock Source Select 0 */ +#define UCRXEIE_L (0x0020u) /* RX Error interrupt enable */ +#define UCBRKIE_L (0x0010u) /* Break interrupt enable */ +#define UCDORM_L (0x0008u) /* Dormant (Sleep) Mode */ +#define UCTXADDR_L (0x0004u) /* Send next Data as Address */ +#define UCTXBRK_L (0x0002u) /* Send next Data as Break */ +#define UCSWRST_L (0x0001u) /* USCI Software Reset */ + +// UCAxCTLW0 UART-Mode Control Bits +#define UCPEN_H (0x0080u) /* Async. Mode: Parity enable */ +#define UCPAR_H (0x0040u) /* Async. Mode: Parity 0:odd / 1:even */ +#define UCMSB_H (0x0020u) /* Async. Mode: MSB first 0:LSB / 1:MSB */ +#define UC7BIT_H (0x0010u) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */ +#define UCSPB_H (0x0008u) /* Async. Mode: Stop Bits 0:one / 1: two */ +#define UCMODE1_H (0x0004u) /* Async. Mode: USCI Mode 1 */ +#define UCMODE0_H (0x0002u) /* Async. Mode: USCI Mode 0 */ +#define UCSYNC_H (0x0001u) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */ + +// UCxxCTLW0 SPI-Mode Control Bits +#define UCCKPH (0x8000u) /* Sync. Mode: Clock Phase */ +#define UCCKPL (0x4000u) /* Sync. Mode: Clock Polarity */ +#define UCMST (0x0800u) /* Sync. Mode: Master Select */ +//#define res (0x0020u) /* reserved */ +//#define res (0x0010u) /* reserved */ +//#define res (0x0008u) /* reserved */ +//#define res (0x0004u) /* reserved */ +#define UCSTEM (0x0002u) /* USCI STE Mode */ + +// UCBxCTLW0 I2C-Mode Control Bits +#define UCA10 (0x8000u) /* 10-bit Address Mode */ +#define UCSLA10 (0x4000u) /* 10-bit Slave Address Mode */ +#define UCMM (0x2000u) /* Multi-Master Environment */ +//#define res (0x1000u) /* reserved */ +//#define res (0x0100u) /* reserved */ +#define UCTXACK (0x0020u) /* Transmit ACK */ +#define UCTR (0x0010u) /* Transmit/Receive Select/Flag */ +#define UCTXNACK (0x0008u) /* Transmit NACK */ +#define UCTXSTP (0x0004u) /* Transmit STOP */ +#define UCTXSTT (0x0002u) /* Transmit START */ + +// UCBxCTLW0 I2C-Mode Control Bits +//#define res (0x1000u) /* reserved */ +//#define res (0x0100u) /* reserved */ +#define UCTXACK_L (0x0020u) /* Transmit ACK */ +#define UCTR_L (0x0010u) /* Transmit/Receive Select/Flag */ +#define UCTXNACK_L (0x0008u) /* Transmit NACK */ +#define UCTXSTP_L (0x0004u) /* Transmit STOP */ +#define UCTXSTT_L (0x0002u) /* Transmit START */ + +// UCBxCTLW0 I2C-Mode Control Bits +#define UCA10_H (0x0080u) /* 10-bit Address Mode */ +#define UCSLA10_H (0x0040u) /* 10-bit Slave Address Mode */ +#define UCMM_H (0x0020u) /* Multi-Master Environment */ +//#define res (0x1000u) /* reserved */ +//#define res (0x0100u) /* reserved */ + +#define UCMODE_0 (0x0000u) /* Sync. Mode: USCI Mode: 0 */ +#define UCMODE_1 (0x0200u) /* Sync. Mode: USCI Mode: 1 */ +#define UCMODE_2 (0x0400u) /* Sync. Mode: USCI Mode: 2 */ +#define UCMODE_3 (0x0600u) /* Sync. Mode: USCI Mode: 3 */ + +#define UCSSEL_0 (0x0000u) /* USCI 0 Clock Source: 0 */ +#define UCSSEL_1 (0x0040u) /* USCI 0 Clock Source: 1 */ +#define UCSSEL_2 (0x0080u) /* USCI 0 Clock Source: 2 */ +#define UCSSEL_3 (0x00C0u) /* USCI 0 Clock Source: 3 */ +#define UCSSEL__UCLK (0x0000u) /* USCI 0 Clock Source: UCLK */ +#define UCSSEL__ACLK (0x0040u) /* USCI 0 Clock Source: ACLK */ +#define UCSSEL__SMCLK (0x0080u) /* USCI 0 Clock Source: SMCLK */ + +// UCAxCTLW1 UART-Mode Control Bits +#define UCGLIT1 (0x0002u) /* USCI Deglitch Time Bit 1 */ +#define UCGLIT0 (0x0001u) /* USCI Deglitch Time Bit 0 */ + +// UCAxCTLW1 UART-Mode Control Bits +#define UCGLIT1_L (0x0002u) /* USCI Deglitch Time Bit 1 */ +#define UCGLIT0_L (0x0001u) /* USCI Deglitch Time Bit 0 */ + +// UCBxCTLW1 I2C-Mode Control Bits +#define UCETXINT (0x0100u) /* USCI Early UCTXIFG0 */ +#define UCCLTO1 (0x0080u) /* USCI Clock low timeout Bit: 1 */ +#define UCCLTO0 (0x0040u) /* USCI Clock low timeout Bit: 0 */ +#define UCSTPNACK (0x0020u) /* USCI Acknowledge Stop last byte */ +#define UCSWACK (0x0010u) /* USCI Software controlled ACK */ +#define UCASTP1 (0x0008u) /* USCI Automatic Stop condition generation Bit: 1 */ +#define UCASTP0 (0x0004u) /* USCI Automatic Stop condition generation Bit: 0 */ +#define UCGLIT1 (0x0002u) /* USCI Deglitch time Bit: 1 */ +#define UCGLIT0 (0x0001u) /* USCI Deglitch time Bit: 0 */ + +// UCBxCTLW1 I2C-Mode Control Bits +#define UCCLTO1_L (0x0080u) /* USCI Clock low timeout Bit: 1 */ +#define UCCLTO0_L (0x0040u) /* USCI Clock low timeout Bit: 0 */ +#define UCSTPNACK_L (0x0020u) /* USCI Acknowledge Stop last byte */ +#define UCSWACK_L (0x0010u) /* USCI Software controlled ACK */ +#define UCASTP1_L (0x0008u) /* USCI Automatic Stop condition generation Bit: 1 */ +#define UCASTP0_L (0x0004u) /* USCI Automatic Stop condition generation Bit: 0 */ +#define UCGLIT1_L (0x0002u) /* USCI Deglitch time Bit: 1 */ +#define UCGLIT0_L (0x0001u) /* USCI Deglitch time Bit: 0 */ + +// UCBxCTLW1 I2C-Mode Control Bits +#define UCETXINT_H (0x0001u) /* USCI Early UCTXIFG0 */ + +#define UCGLIT_0 (0x0000u) /* USCI Deglitch time: 0 */ +#define UCGLIT_1 (0x0001u) /* USCI Deglitch time: 1 */ +#define UCGLIT_2 (0x0002u) /* USCI Deglitch time: 2 */ +#define UCGLIT_3 (0x0003u) /* USCI Deglitch time: 3 */ + +#define UCASTP_0 (0x0000u) /* USCI Automatic Stop condition generation: 0 */ +#define UCASTP_1 (0x0004u) /* USCI Automatic Stop condition generation: 1 */ +#define UCASTP_2 (0x0008u) /* USCI Automatic Stop condition generation: 2 */ +#define UCASTP_3 (0x000Cu) /* USCI Automatic Stop condition generation: 3 */ + +#define UCCLTO_0 (0x0000u) /* USCI Clock low timeout: 0 */ +#define UCCLTO_1 (0x0040u) /* USCI Clock low timeout: 1 */ +#define UCCLTO_2 (0x0080u) /* USCI Clock low timeout: 2 */ +#define UCCLTO_3 (0x00C0u) /* USCI Clock low timeout: 3 */ + +/* UCAxMCTLW Control Bits */ +#define UCBRS7 (0x8000u) /* USCI Second Stage Modulation Select 7 */ +#define UCBRS6 (0x4000u) /* USCI Second Stage Modulation Select 6 */ +#define UCBRS5 (0x2000u) /* USCI Second Stage Modulation Select 5 */ +#define UCBRS4 (0x1000u) /* USCI Second Stage Modulation Select 4 */ +#define UCBRS3 (0x0800u) /* USCI Second Stage Modulation Select 3 */ +#define UCBRS2 (0x0400u) /* USCI Second Stage Modulation Select 2 */ +#define UCBRS1 (0x0200u) /* USCI Second Stage Modulation Select 1 */ +#define UCBRS0 (0x0100u) /* USCI Second Stage Modulation Select 0 */ +#define UCBRF3 (0x0080u) /* USCI First Stage Modulation Select 3 */ +#define UCBRF2 (0x0040u) /* USCI First Stage Modulation Select 2 */ +#define UCBRF1 (0x0020u) /* USCI First Stage Modulation Select 1 */ +#define UCBRF0 (0x0010u) /* USCI First Stage Modulation Select 0 */ +#define UCOS16 (0x0001u) /* USCI 16-times Oversampling enable */ + +/* UCAxMCTLW Control Bits */ +#define UCBRF3_L (0x0080u) /* USCI First Stage Modulation Select 3 */ +#define UCBRF2_L (0x0040u) /* USCI First Stage Modulation Select 2 */ +#define UCBRF1_L (0x0020u) /* USCI First Stage Modulation Select 1 */ +#define UCBRF0_L (0x0010u) /* USCI First Stage Modulation Select 0 */ +#define UCOS16_L (0x0001u) /* USCI 16-times Oversampling enable */ + +/* UCAxMCTLW Control Bits */ +#define UCBRS7_H (0x0080u) /* USCI Second Stage Modulation Select 7 */ +#define UCBRS6_H (0x0040u) /* USCI Second Stage Modulation Select 6 */ +#define UCBRS5_H (0x0020u) /* USCI Second Stage Modulation Select 5 */ +#define UCBRS4_H (0x0010u) /* USCI Second Stage Modulation Select 4 */ +#define UCBRS3_H (0x0008u) /* USCI Second Stage Modulation Select 3 */ +#define UCBRS2_H (0x0004u) /* USCI Second Stage Modulation Select 2 */ +#define UCBRS1_H (0x0002u) /* USCI Second Stage Modulation Select 1 */ +#define UCBRS0_H (0x0001u) /* USCI Second Stage Modulation Select 0 */ + +#define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */ +#define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */ +#define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */ +#define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */ +#define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */ +#define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */ +#define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */ +#define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */ +#define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */ +#define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */ +#define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */ +#define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */ +#define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */ +#define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */ +#define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */ +#define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */ + +/* UCAxSTATW Control Bits */ +#define UCLISTEN (0x0080u) /* USCI Listen mode */ +#define UCFE (0x0040u) /* USCI Frame Error Flag */ +#define UCOE (0x0020u) /* USCI Overrun Error Flag */ +#define UCPE (0x0010u) /* USCI Parity Error Flag */ +#define UCBRK (0x0008u) /* USCI Break received */ +#define UCRXERR (0x0004u) /* USCI RX Error Flag */ +#define UCADDR (0x0002u) /* USCI Address received Flag */ +#define UCBUSY (0x0001u) /* USCI Busy Flag */ +#define UCIDLE (0x0002u) /* USCI Idle line detected Flag */ + +/* UCBxSTATW I2C Control Bits */ +#define UCBCNT7 (0x8000u) /* USCI Byte Counter Bit 7 */ +#define UCBCNT6 (0x4000u) /* USCI Byte Counter Bit 6 */ +#define UCBCNT5 (0x2000u) /* USCI Byte Counter Bit 5 */ +#define UCBCNT4 (0x1000u) /* USCI Byte Counter Bit 4 */ +#define UCBCNT3 (0x0800u) /* USCI Byte Counter Bit 3 */ +#define UCBCNT2 (0x0400u) /* USCI Byte Counter Bit 2 */ +#define UCBCNT1 (0x0200u) /* USCI Byte Counter Bit 1 */ +#define UCBCNT0 (0x0100u) /* USCI Byte Counter Bit 0 */ +#define UCSCLLOW (0x0040u) /* SCL low */ +#define UCGC (0x0020u) /* General Call address received Flag */ +#define UCBBUSY (0x0010u) /* Bus Busy Flag */ + +/* UCBxTBCNT I2C Control Bits */ +#define UCTBCNT7 (0x0080u) /* USCI Byte Counter Bit 7 */ +#define UCTBCNT6 (0x0040u) /* USCI Byte Counter Bit 6 */ +#define UCTBCNT5 (0x0020u) /* USCI Byte Counter Bit 5 */ +#define UCTBCNT4 (0x0010u) /* USCI Byte Counter Bit 4 */ +#define UCTBCNT3 (0x0008u) /* USCI Byte Counter Bit 3 */ +#define UCTBCNT2 (0x0004u) /* USCI Byte Counter Bit 2 */ +#define UCTBCNT1 (0x0002u) /* USCI Byte Counter Bit 1 */ +#define UCTBCNT0 (0x0001u) /* USCI Byte Counter Bit 0 */ + +/* UCAxIRCTL Control Bits */ +#define UCIRRXFL5 (0x8000u) /* IRDA Receive Filter Length 5 */ +#define UCIRRXFL4 (0x4000u) /* IRDA Receive Filter Length 4 */ +#define UCIRRXFL3 (0x2000u) /* IRDA Receive Filter Length 3 */ +#define UCIRRXFL2 (0x1000u) /* IRDA Receive Filter Length 2 */ +#define UCIRRXFL1 (0x0800u) /* IRDA Receive Filter Length 1 */ +#define UCIRRXFL0 (0x0400u) /* IRDA Receive Filter Length 0 */ +#define UCIRRXPL (0x0200u) /* IRDA Receive Input Polarity */ +#define UCIRRXFE (0x0100u) /* IRDA Receive Filter enable */ +#define UCIRTXPL5 (0x0080u) /* IRDA Transmit Pulse Length 5 */ +#define UCIRTXPL4 (0x0040u) /* IRDA Transmit Pulse Length 4 */ +#define UCIRTXPL3 (0x0020u) /* IRDA Transmit Pulse Length 3 */ +#define UCIRTXPL2 (0x0010u) /* IRDA Transmit Pulse Length 2 */ +#define UCIRTXPL1 (0x0008u) /* IRDA Transmit Pulse Length 1 */ +#define UCIRTXPL0 (0x0004u) /* IRDA Transmit Pulse Length 0 */ +#define UCIRTXCLK (0x0002u) /* IRDA Transmit Pulse Clock Select */ +#define UCIREN (0x0001u) /* IRDA Encoder/Decoder enable */ + +/* UCAxIRCTL Control Bits */ +#define UCIRTXPL5_L (0x0080u) /* IRDA Transmit Pulse Length 5 */ +#define UCIRTXPL4_L (0x0040u) /* IRDA Transmit Pulse Length 4 */ +#define UCIRTXPL3_L (0x0020u) /* IRDA Transmit Pulse Length 3 */ +#define UCIRTXPL2_L (0x0010u) /* IRDA Transmit Pulse Length 2 */ +#define UCIRTXPL1_L (0x0008u) /* IRDA Transmit Pulse Length 1 */ +#define UCIRTXPL0_L (0x0004u) /* IRDA Transmit Pulse Length 0 */ +#define UCIRTXCLK_L (0x0002u) /* IRDA Transmit Pulse Clock Select */ +#define UCIREN_L (0x0001u) /* IRDA Encoder/Decoder enable */ + +/* UCAxIRCTL Control Bits */ +#define UCIRRXFL5_H (0x0080u) /* IRDA Receive Filter Length 5 */ +#define UCIRRXFL4_H (0x0040u) /* IRDA Receive Filter Length 4 */ +#define UCIRRXFL3_H (0x0020u) /* IRDA Receive Filter Length 3 */ +#define UCIRRXFL2_H (0x0010u) /* IRDA Receive Filter Length 2 */ +#define UCIRRXFL1_H (0x0008u) /* IRDA Receive Filter Length 1 */ +#define UCIRRXFL0_H (0x0004u) /* IRDA Receive Filter Length 0 */ +#define UCIRRXPL_H (0x0002u) /* IRDA Receive Input Polarity */ +#define UCIRRXFE_H (0x0001u) /* IRDA Receive Filter enable */ + +/* UCAxABCTL Control Bits */ +//#define res (0x80) /* reserved */ +//#define res (0x40) /* reserved */ +#define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */ +#define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */ +#define UCSTOE (0x08) /* Sync-Field Timeout error */ +#define UCBTOE (0x04) /* Break Timeout error */ +//#define res (0x02) /* reserved */ +#define UCABDEN (0x01) /* Auto Baud Rate detect enable */ + +/* UCBxI2COA0 Control Bits */ +#define UCGCEN (0x8000u) /* I2C General Call enable */ +#define UCOAEN (0x0400u) /* I2C Own Address enable */ +#define UCOA9 (0x0200u) /* I2C Own Address Bit 9 */ +#define UCOA8 (0x0100u) /* I2C Own Address Bit 8 */ +#define UCOA7 (0x0080u) /* I2C Own Address Bit 7 */ +#define UCOA6 (0x0040u) /* I2C Own Address Bit 6 */ +#define UCOA5 (0x0020u) /* I2C Own Address Bit 5 */ +#define UCOA4 (0x0010u) /* I2C Own Address Bit 4 */ +#define UCOA3 (0x0008u) /* I2C Own Address Bit 3 */ +#define UCOA2 (0x0004u) /* I2C Own Address Bit 2 */ +#define UCOA1 (0x0002u) /* I2C Own Address Bit 1 */ +#define UCOA0 (0x0001u) /* I2C Own Address Bit 0 */ + +/* UCBxI2COA0 Control Bits */ +#define UCOA7_L (0x0080u) /* I2C Own Address Bit 7 */ +#define UCOA6_L (0x0040u) /* I2C Own Address Bit 6 */ +#define UCOA5_L (0x0020u) /* I2C Own Address Bit 5 */ +#define UCOA4_L (0x0010u) /* I2C Own Address Bit 4 */ +#define UCOA3_L (0x0008u) /* I2C Own Address Bit 3 */ +#define UCOA2_L (0x0004u) /* I2C Own Address Bit 2 */ +#define UCOA1_L (0x0002u) /* I2C Own Address Bit 1 */ +#define UCOA0_L (0x0001u) /* I2C Own Address Bit 0 */ + +/* UCBxI2COA0 Control Bits */ +#define UCGCEN_H (0x0080u) /* I2C General Call enable */ +#define UCOAEN_H (0x0004u) /* I2C Own Address enable */ +#define UCOA9_H (0x0002u) /* I2C Own Address Bit 9 */ +#define UCOA8_H (0x0001u) /* I2C Own Address Bit 8 */ + +/* UCBxI2COAx Control Bits */ +#define UCOAEN (0x0400u) /* I2C Own Address enable */ +#define UCOA9 (0x0200u) /* I2C Own Address Bit 9 */ +#define UCOA8 (0x0100u) /* I2C Own Address Bit 8 */ +#define UCOA7 (0x0080u) /* I2C Own Address Bit 7 */ +#define UCOA6 (0x0040u) /* I2C Own Address Bit 6 */ +#define UCOA5 (0x0020u) /* I2C Own Address Bit 5 */ +#define UCOA4 (0x0010u) /* I2C Own Address Bit 4 */ +#define UCOA3 (0x0008u) /* I2C Own Address Bit 3 */ +#define UCOA2 (0x0004u) /* I2C Own Address Bit 2 */ +#define UCOA1 (0x0002u) /* I2C Own Address Bit 1 */ +#define UCOA0 (0x0001u) /* I2C Own Address Bit 0 */ + +/* UCBxI2COAx Control Bits */ +#define UCOA7_L (0x0080u) /* I2C Own Address Bit 7 */ +#define UCOA6_L (0x0040u) /* I2C Own Address Bit 6 */ +#define UCOA5_L (0x0020u) /* I2C Own Address Bit 5 */ +#define UCOA4_L (0x0010u) /* I2C Own Address Bit 4 */ +#define UCOA3_L (0x0008u) /* I2C Own Address Bit 3 */ +#define UCOA2_L (0x0004u) /* I2C Own Address Bit 2 */ +#define UCOA1_L (0x0002u) /* I2C Own Address Bit 1 */ +#define UCOA0_L (0x0001u) /* I2C Own Address Bit 0 */ + +/* UCBxI2COAx Control Bits */ +#define UCOAEN_H (0x0004u) /* I2C Own Address enable */ +#define UCOA9_H (0x0002u) /* I2C Own Address Bit 9 */ +#define UCOA8_H (0x0001u) /* I2C Own Address Bit 8 */ + +/* UCBxADDRX Control Bits */ +#define UCADDRX9 (0x0200u) /* I2C Receive Address Bit 9 */ +#define UCADDRX8 (0x0100u) /* I2C Receive Address Bit 8 */ +#define UCADDRX7 (0x0080u) /* I2C Receive Address Bit 7 */ +#define UCADDRX6 (0x0040u) /* I2C Receive Address Bit 6 */ +#define UCADDRX5 (0x0020u) /* I2C Receive Address Bit 5 */ +#define UCADDRX4 (0x0010u) /* I2C Receive Address Bit 4 */ +#define UCADDRX3 (0x0008u) /* I2C Receive Address Bit 3 */ +#define UCADDRX2 (0x0004u) /* I2C Receive Address Bit 2 */ +#define UCADDRX1 (0x0002u) /* I2C Receive Address Bit 1 */ +#define UCADDRX0 (0x0001u) /* I2C Receive Address Bit 0 */ + +/* UCBxADDRX Control Bits */ +#define UCADDRX7_L (0x0080u) /* I2C Receive Address Bit 7 */ +#define UCADDRX6_L (0x0040u) /* I2C Receive Address Bit 6 */ +#define UCADDRX5_L (0x0020u) /* I2C Receive Address Bit 5 */ +#define UCADDRX4_L (0x0010u) /* I2C Receive Address Bit 4 */ +#define UCADDRX3_L (0x0008u) /* I2C Receive Address Bit 3 */ +#define UCADDRX2_L (0x0004u) /* I2C Receive Address Bit 2 */ +#define UCADDRX1_L (0x0002u) /* I2C Receive Address Bit 1 */ +#define UCADDRX0_L (0x0001u) /* I2C Receive Address Bit 0 */ + +/* UCBxADDRX Control Bits */ +#define UCADDRX9_H (0x0002u) /* I2C Receive Address Bit 9 */ +#define UCADDRX8_H (0x0001u) /* I2C Receive Address Bit 8 */ + +/* UCBxADDMASK Control Bits */ +#define UCADDMASK9 (0x0200u) /* I2C Address Mask Bit 9 */ +#define UCADDMASK8 (0x0100u) /* I2C Address Mask Bit 8 */ +#define UCADDMASK7 (0x0080u) /* I2C Address Mask Bit 7 */ +#define UCADDMASK6 (0x0040u) /* I2C Address Mask Bit 6 */ +#define UCADDMASK5 (0x0020u) /* I2C Address Mask Bit 5 */ +#define UCADDMASK4 (0x0010u) /* I2C Address Mask Bit 4 */ +#define UCADDMASK3 (0x0008u) /* I2C Address Mask Bit 3 */ +#define UCADDMASK2 (0x0004u) /* I2C Address Mask Bit 2 */ +#define UCADDMASK1 (0x0002u) /* I2C Address Mask Bit 1 */ +#define UCADDMASK0 (0x0001u) /* I2C Address Mask Bit 0 */ + +/* UCBxADDMASK Control Bits */ +#define UCADDMASK7_L (0x0080u) /* I2C Address Mask Bit 7 */ +#define UCADDMASK6_L (0x0040u) /* I2C Address Mask Bit 6 */ +#define UCADDMASK5_L (0x0020u) /* I2C Address Mask Bit 5 */ +#define UCADDMASK4_L (0x0010u) /* I2C Address Mask Bit 4 */ +#define UCADDMASK3_L (0x0008u) /* I2C Address Mask Bit 3 */ +#define UCADDMASK2_L (0x0004u) /* I2C Address Mask Bit 2 */ +#define UCADDMASK1_L (0x0002u) /* I2C Address Mask Bit 1 */ +#define UCADDMASK0_L (0x0001u) /* I2C Address Mask Bit 0 */ + +/* UCBxADDMASK Control Bits */ +#define UCADDMASK9_H (0x0002u) /* I2C Address Mask Bit 9 */ +#define UCADDMASK8_H (0x0001u) /* I2C Address Mask Bit 8 */ + +/* UCBxI2CSA Control Bits */ +#define UCSA9 (0x0200u) /* I2C Slave Address Bit 9 */ +#define UCSA8 (0x0100u) /* I2C Slave Address Bit 8 */ +#define UCSA7 (0x0080u) /* I2C Slave Address Bit 7 */ +#define UCSA6 (0x0040u) /* I2C Slave Address Bit 6 */ +#define UCSA5 (0x0020u) /* I2C Slave Address Bit 5 */ +#define UCSA4 (0x0010u) /* I2C Slave Address Bit 4 */ +#define UCSA3 (0x0008u) /* I2C Slave Address Bit 3 */ +#define UCSA2 (0x0004u) /* I2C Slave Address Bit 2 */ +#define UCSA1 (0x0002u) /* I2C Slave Address Bit 1 */ +#define UCSA0 (0x0001u) /* I2C Slave Address Bit 0 */ + +/* UCBxI2CSA Control Bits */ +#define UCSA7_L (0x0080u) /* I2C Slave Address Bit 7 */ +#define UCSA6_L (0x0040u) /* I2C Slave Address Bit 6 */ +#define UCSA5_L (0x0020u) /* I2C Slave Address Bit 5 */ +#define UCSA4_L (0x0010u) /* I2C Slave Address Bit 4 */ +#define UCSA3_L (0x0008u) /* I2C Slave Address Bit 3 */ +#define UCSA2_L (0x0004u) /* I2C Slave Address Bit 2 */ +#define UCSA1_L (0x0002u) /* I2C Slave Address Bit 1 */ +#define UCSA0_L (0x0001u) /* I2C Slave Address Bit 0 */ + +/* UCBxI2CSA Control Bits */ +#define UCSA9_H (0x0002u) /* I2C Slave Address Bit 9 */ +#define UCSA8_H (0x0001u) /* I2C Slave Address Bit 8 */ + +/* UCAxIE UART Control Bits */ +#define UCTXCPTIE (0x0008u) /* UART Transmit Complete Interrupt Enable */ +#define UCSTTIE (0x0004u) /* UART Start Bit Interrupt Enalble */ +#define UCTXIE (0x0002u) /* UART Transmit Interrupt Enable */ +#define UCRXIE (0x0001u) /* UART Receive Interrupt Enable */ + +/* UCAxIE/UCBxIE SPI Control Bits */ + +/* UCBxIE I2C Control Bits */ +#define UCBIT9IE (0x4000u) /* I2C Bit 9 Position Interrupt Enable 3 */ +#define UCTXIE3 (0x2000u) /* I2C Transmit Interrupt Enable 3 */ +#define UCRXIE3 (0x1000u) /* I2C Receive Interrupt Enable 3 */ +#define UCTXIE2 (0x0800u) /* I2C Transmit Interrupt Enable 2 */ +#define UCRXIE2 (0x0400u) /* I2C Receive Interrupt Enable 2 */ +#define UCTXIE1 (0x0200u) /* I2C Transmit Interrupt Enable 1 */ +#define UCRXIE1 (0x0100u) /* I2C Receive Interrupt Enable 1 */ +#define UCCLTOIE (0x0080u) /* I2C Clock Low Timeout interrupt enable */ +#define UCBCNTIE (0x0040u) /* I2C Automatic stop assertion interrupt enable */ +#define UCNACKIE (0x0020u) /* I2C NACK Condition interrupt enable */ +#define UCALIE (0x0010u) /* I2C Arbitration Lost interrupt enable */ +#define UCSTPIE (0x0008u) /* I2C STOP Condition interrupt enable */ +#define UCSTTIE (0x0004u) /* I2C START Condition interrupt enable */ +#define UCTXIE0 (0x0002u) /* I2C Transmit Interrupt Enable 0 */ +#define UCRXIE0 (0x0001u) /* I2C Receive Interrupt Enable 0 */ + +/* UCAxIFG UART Control Bits */ +#define UCTXCPTIFG (0x0008u) /* UART Transmit Complete Interrupt Flag */ +#define UCSTTIFG (0x0004u) /* UART Start Bit Interrupt Flag */ +#define UCTXIFG (0x0002u) /* UART Transmit Interrupt Flag */ +#define UCRXIFG (0x0001u) /* UART Receive Interrupt Flag */ + +/* UCAxIFG/UCBxIFG SPI Control Bits */ +#define UCTXIFG (0x0002u) /* SPI Transmit Interrupt Flag */ +#define UCRXIFG (0x0001u) /* SPI Receive Interrupt Flag */ + +/* UCBxIFG Control Bits */ +#define UCBIT9IFG (0x4000u) /* I2C Bit 9 Possition Interrupt Flag 3 */ +#define UCTXIFG3 (0x2000u) /* I2C Transmit Interrupt Flag 3 */ +#define UCRXIFG3 (0x1000u) /* I2C Receive Interrupt Flag 3 */ +#define UCTXIFG2 (0x0800u) /* I2C Transmit Interrupt Flag 2 */ +#define UCRXIFG2 (0x0400u) /* I2C Receive Interrupt Flag 2 */ +#define UCTXIFG1 (0x0200u) /* I2C Transmit Interrupt Flag 1 */ +#define UCRXIFG1 (0x0100u) /* I2C Receive Interrupt Flag 1 */ +#define UCCLTOIFG (0x0080u) /* I2C Clock low Timeout interrupt Flag */ +#define UCBCNTIFG (0x0040u) /* I2C Byte counter interrupt flag */ +#define UCNACKIFG (0x0020u) /* I2C NACK Condition interrupt Flag */ +#define UCALIFG (0x0010u) /* I2C Arbitration Lost interrupt Flag */ +#define UCSTPIFG (0x0008u) /* I2C STOP Condition interrupt Flag */ +#define UCSTTIFG (0x0004u) /* I2C START Condition interrupt Flag */ +#define UCTXIFG0 (0x0002u) /* I2C Transmit Interrupt Flag 0 */ +#define UCRXIFG0 (0x0001u) /* I2C Receive Interrupt Flag 0 */ + +/* USCI UART Definitions */ +#define USCI_NONE (0x0000u) /* No Interrupt pending */ +#define USCI_UART_UCRXIFG (0x0002u) /* USCI UCRXIFG */ +#define USCI_UART_UCTXIFG (0x0004u) /* USCI UCTXIFG */ +#define USCI_UART_UCSTTIFG (0x0006u) /* USCI UCSTTIFG */ +#define USCI_UART_UCTXCPTIFG (0x0008u) /* USCI UCTXCPTIFG */ + +/* USCI SPI Definitions */ +#define USCI_SPI_UCRXIFG (0x0002u) /* USCI UCRXIFG */ +#define USCI_SPI_UCTXIFG (0x0004u) /* USCI UCTXIFG */ + +/* USCI I2C Definitions */ +#define USCI_I2C_UCALIFG (0x0002u) /* USCI I2C Mode: UCALIFG */ +#define USCI_I2C_UCNACKIFG (0x0004u) /* USCI I2C Mode: UCNACKIFG */ +#define USCI_I2C_UCSTTIFG (0x0006u) /* USCI I2C Mode: UCSTTIFG*/ +#define USCI_I2C_UCSTPIFG (0x0008u) /* USCI I2C Mode: UCSTPIFG*/ +#define USCI_I2C_UCRXIFG3 (0x000Au) /* USCI I2C Mode: UCRXIFG3 */ +#define USCI_I2C_UCTXIFG3 (0x000Cu) /* USCI I2C Mode: UCTXIFG3 */ +#define USCI_I2C_UCRXIFG2 (0x000Eu) /* USCI I2C Mode: UCRXIFG2 */ +#define USCI_I2C_UCTXIFG2 (0x0010u) /* USCI I2C Mode: UCTXIFG2 */ +#define USCI_I2C_UCRXIFG1 (0x0012u) /* USCI I2C Mode: UCRXIFG1 */ +#define USCI_I2C_UCTXIFG1 (0x0014u) /* USCI I2C Mode: UCTXIFG1 */ +#define USCI_I2C_UCRXIFG0 (0x0016u) /* USCI I2C Mode: UCRXIFG0 */ +#define USCI_I2C_UCTXIFG0 (0x0018u) /* USCI I2C Mode: UCTXIFG0 */ +#define USCI_I2C_UCBCNTIFG (0x001Au) /* USCI I2C Mode: UCBCNTIFG */ +#define USCI_I2C_UCCLTOIFG (0x001Cu) /* USCI I2C Mode: UCCLTOIFG */ +#define USCI_I2C_UCBIT9IFG (0x001Eu) /* USCI I2C Mode: UCBIT9IFG */ + +#endif +/************************************************************ +* WATCHDOG TIMER A +************************************************************/ +#ifdef __MSP430_HAS_WDT_A__ /* Definition to show that Module is available */ + +#define OFS_WDTCTL (0x000Cu) /* Watchdog Timer Control */ +#define OFS_WDTCTL_L OFS_WDTCTL +#define OFS_WDTCTL_H OFS_WDTCTL+1 +/* The bit names have been prefixed with "WDT" */ +/* WDTCTL Control Bits */ +#define WDTIS0 (0x0001u) /* WDT - Timer Interval Select 0 */ +#define WDTIS1 (0x0002u) /* WDT - Timer Interval Select 1 */ +#define WDTIS2 (0x0004u) /* WDT - Timer Interval Select 2 */ +#define WDTCNTCL (0x0008u) /* WDT - Timer Clear */ +#define WDTTMSEL (0x0010u) /* WDT - Timer Mode Select */ +#define WDTSSEL0 (0x0020u) /* WDT - Timer Clock Source Select 0 */ +#define WDTSSEL1 (0x0040u) /* WDT - Timer Clock Source Select 1 */ +#define WDTHOLD (0x0080u) /* WDT - Timer hold */ + +/* WDTCTL Control Bits */ +#define WDTIS0_L (0x0001u) /* WDT - Timer Interval Select 0 */ +#define WDTIS1_L (0x0002u) /* WDT - Timer Interval Select 1 */ +#define WDTIS2_L (0x0004u) /* WDT - Timer Interval Select 2 */ +#define WDTCNTCL_L (0x0008u) /* WDT - Timer Clear */ +#define WDTTMSEL_L (0x0010u) /* WDT - Timer Mode Select */ +#define WDTSSEL0_L (0x0020u) /* WDT - Timer Clock Source Select 0 */ +#define WDTSSEL1_L (0x0040u) /* WDT - Timer Clock Source Select 1 */ +#define WDTHOLD_L (0x0080u) /* WDT - Timer hold */ + +#define WDTPW (0x5A00u) + +#define WDTIS_0 (0*0x0001u) /* WDT - Timer Interval Select: /2G */ +#define WDTIS_1 (1*0x0001u) /* WDT - Timer Interval Select: /128M */ +#define WDTIS_2 (2*0x0001u) /* WDT - Timer Interval Select: /8192k */ +#define WDTIS_3 (3*0x0001u) /* WDT - Timer Interval Select: /512k */ +#define WDTIS_4 (4*0x0001u) /* WDT - Timer Interval Select: /32k */ +#define WDTIS_5 (5*0x0001u) /* WDT - Timer Interval Select: /8192 */ +#define WDTIS_6 (6*0x0001u) /* WDT - Timer Interval Select: /512 */ +#define WDTIS_7 (7*0x0001u) /* WDT - Timer Interval Select: /64 */ +#define WDTIS__2G (0*0x0001u) /* WDT - Timer Interval Select: /2G */ +#define WDTIS__128M (1*0x0001u) /* WDT - Timer Interval Select: /128M */ +#define WDTIS__8192K (2*0x0001u) /* WDT - Timer Interval Select: /8192k */ +#define WDTIS__512K (3*0x0001u) /* WDT - Timer Interval Select: /512k */ +#define WDTIS__32K (4*0x0001u) /* WDT - Timer Interval Select: /32k */ +#define WDTIS__8192 (5*0x0001u) /* WDT - Timer Interval Select: /8192 */ +#define WDTIS__512 (6*0x0001u) /* WDT - Timer Interval Select: /512 */ +#define WDTIS__64 (7*0x0001u) /* WDT - Timer Interval Select: /64 */ + +#define WDTSSEL_0 (0*0x0020u) /* WDT - Timer Clock Source Select: SMCLK */ +#define WDTSSEL_1 (1*0x0020u) /* WDT - Timer Clock Source Select: ACLK */ +#define WDTSSEL_2 (2*0x0020u) /* WDT - Timer Clock Source Select: VLO_CLK */ +#define WDTSSEL_3 (3*0x0020u) /* WDT - Timer Clock Source Select: reserved */ +#define WDTSSEL__SMCLK (0*0x0020u) /* WDT - Timer Clock Source Select: SMCLK */ +#define WDTSSEL__ACLK (1*0x0020u) /* WDT - Timer Clock Source Select: ACLK */ +#define WDTSSEL__VLO (2*0x0020u) /* WDT - Timer Clock Source Select: VLO_CLK */ + +/* WDT-interval times [1ms] coded with Bits 0-2 */ +/* WDT is clocked by fSMCLK (assumed 1MHz) */ +#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2) /* 32ms interval (default) */ +#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */ +#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */ +#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */ +/* WDT is clocked by fACLK (assumed 32KHz) */ +#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0) /* 1000ms " */ +#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0) /* 250ms " */ +#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1) /* 16ms " */ +#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0) /* 1.9ms " */ +/* Watchdog mode -> reset after expired time */ +/* WDT is clocked by fSMCLK (assumed 1MHz) */ +#define WDT_MRST_32 (WDTPW+WDTCNTCL+WDTIS2) /* 32ms interval (default) */ +#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */ +#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */ +#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */ +/* WDT is clocked by fACLK (assumed 32KHz) */ +#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2) /* 1000ms " */ +#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0) /* 250ms " */ +#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1) /* 16ms " */ +#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0) /* 1.9ms " */ + +#endif + +/************************************************************ +* TLV Descriptors +************************************************************/ +#define __MSP430_HAS_TLV__ /* Definition to show that Module is available */ +#define TLV_BASE __MSP430_BASEADDRESS_TLV__ + +#define TLV_START (0x1A08u) /* Start Address of the TLV structure */ +#define TLV_END (0x1AFFu) /* End Address of the TLV structure */ + +#define TLV_LDTAG (0x01) /* Legacy descriptor (1xx, 2xx, 4xx families) */ +#define TLV_PDTAG (0x02) /* Peripheral discovery descriptor */ +#define TLV_Reserved3 (0x03) /* Future usage */ +#define TLV_Reserved4 (0x04) /* Future usage */ +#define TLV_BLANK (0x05) /* Blank descriptor */ +#define TLV_Reserved6 (0x06) /* Future usage */ +#define TLV_Reserved7 (0x07) /* Serial Number */ +#define TLV_DIERECORD (0x08) /* Die Record */ +#define TLV_ADCCAL (0x11) /* ADC12 calibration */ +#define TLV_ADC12CAL (0x11) /* ADC12 calibration */ +#define TLV_REFCAL (0x12) /* REF calibration */ +#define TLV_ADC10CAL (0x13) /* ADC10 calibration */ +#define TLV_TIMERDCAL (0x15) /* TIMER_D calibration */ +#define TLV_TAGEXT (0xFE) /* Tag extender */ +#define TLV_TAGEND (0xFF) /* Tag End of Table */ + +/************************************************************ +* Interrupt Vectors (offset from 0xFF80) +************************************************************/ + + +/************************************************************ +* End of Modules +************************************************************/ +#pragma language=default + +#endif /* #ifndef __msp430FR5XX_FR6XXGENERIC */ + diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/dma.c b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/dma.c new file mode 100644 index 000000000..8b2ec9d1d --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/dma.c @@ -0,0 +1,199 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// dma.c - Driver for the dma Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup dma_api dma +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#if defined(__MSP430_HAS_DMAX_3__) || defined(__MSP430_HAS_DMAX_6__) +#include "dma.h" + +#include + +void DMA_init(DMA_initParam *param){ + uint8_t triggerOffset = (param->channelSelect >> 4); + + //Reset and Set DMA Control 0 Register + HWREG16(DMA_BASE + param->channelSelect + OFS_DMA0CTL) = + param->transferModeSelect //Set Transfer Mode + + param->transferUnitSelect //Set Transfer Unit Size + + param->triggerTypeSelect; //Set Trigger Type + + //Set Transfer Size Amount + HWREG16(DMA_BASE + param->channelSelect + OFS_DMA0SZ) = param->transferSize; + + if(triggerOffset & 0x01) //Odd Channel + { + HWREG16(DMA_BASE + (triggerOffset & 0x0E)) &= 0x00FF; //Reset Trigger Select + HWREG16(DMA_BASE + + (triggerOffset & 0x0E)) |= (param->triggerSourceSelect << 8); + } + else //Even Channel + { + HWREG16(DMA_BASE + (triggerOffset & 0x0E)) &= 0xFF00; //Reset Trigger Select + HWREG16(DMA_BASE + + (triggerOffset & 0x0E)) |= param->triggerSourceSelect; + } +} + +void DMA_setTransferSize(uint8_t channelSelect, + uint16_t transferSize) +{ + //Set Transfer Size Amount + HWREG16(DMA_BASE + channelSelect + OFS_DMA0SZ) = transferSize; +} + +uint16_t DMA_getTransferSize(uint8_t channelSelect) +{ + //Get Transfer Size Amount + return(HWREG16(DMA_BASE + channelSelect + OFS_DMA0SZ)); +} + +void DMA_setSrcAddress(uint8_t channelSelect, + uint32_t srcAddress, + uint16_t directionSelect) +{ + //Set the Source Address + __data16_write_addr((unsigned short)(DMA_BASE + channelSelect + OFS_DMA0SA), + srcAddress); + + //Reset bits before setting them + HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) &= ~(DMASRCINCR_3); + HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) |= directionSelect; +} + +void DMA_setDstAddress(uint8_t channelSelect, + uint32_t dstAddress, + uint16_t directionSelect) +{ + //Set the Destination Address + __data16_write_addr((unsigned short)(DMA_BASE + channelSelect + OFS_DMA0DA), + dstAddress); + + //Reset bits before setting them + HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) &= ~(DMADSTINCR_3); + HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) |= (directionSelect << 2); +} + +void DMA_enableTransfers(uint8_t channelSelect) +{ + HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) |= DMAEN; +} + +void DMA_disableTransfers(uint8_t channelSelect) +{ + HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) &= ~(DMAEN); +} + +void DMA_startTransfer(uint8_t channelSelect) +{ + HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) |= DMAREQ; +} + +void DMA_enableInterrupt(uint8_t channelSelect) +{ + HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) |= DMAIE; +} + +void DMA_disableInterrupt(uint8_t channelSelect) +{ + HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) &= ~(DMAIE); +} + +uint16_t DMA_getInterruptStatus(uint8_t channelSelect) +{ + return (HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) & DMAIFG); +} + +void DMA_clearInterrupt(uint8_t channelSelect) +{ + HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) &= ~(DMAIFG); +} + +uint16_t DMA_getNMIAbortStatus(uint8_t channelSelect) +{ + return (HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) & DMAABORT); +} + +void DMA_clearNMIAbort(uint8_t channelSelect) +{ + HWREG16(DMA_BASE + channelSelect + OFS_DMA0CTL) &= ~(DMAABORT); +} + +void DMA_disableTransferDuringReadModifyWrite(void) +{ + HWREG16(DMA_BASE + OFS_DMACTL4) |= DMARMWDIS; +} + +void DMA_enableTransferDuringReadModifyWrite(void) +{ + HWREG16(DMA_BASE + OFS_DMACTL4) &= ~(DMARMWDIS); +} + +void DMA_enableRoundRobinPriority(void) +{ + HWREG16(DMA_BASE + OFS_DMACTL4) |= ROUNDROBIN; +} + +void DMA_disableRoundRobinPriority(void) +{ + HWREG16(DMA_BASE + OFS_DMACTL4) &= ~(ROUNDROBIN); +} + +void DMA_enableNMIAbort(void) +{ + HWREG16(DMA_BASE + OFS_DMACTL4) |= ENNMI; +} + +void DMA_disableNMIAbort(void) +{ + HWREG16(DMA_BASE + OFS_DMACTL4) &= ~(ENNMI); +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for dma_api +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/dma.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/dma.h new file mode 100644 index 000000000..f72736589 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/dma.h @@ -0,0 +1,738 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// dma.h - Driver for the DMA Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_DMA_H__ +#define __MSP430WARE_DMA_H__ + +#include "inc/hw_memmap.h" + +#if defined(__MSP430_HAS_DMAX_3__) || defined(__MSP430_HAS_DMAX_6__) + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "inc/hw_regaccess.h" +//***************************************************************************** +// +//! \brief Used in the DMA_init() function as the param parameter. +// +//***************************************************************************** +typedef struct DMA_initParam +{ + //! Is the specified channel to initialize. + //! \n Valid values are: + //! - \b DMA_CHANNEL_0 + //! - \b DMA_CHANNEL_1 + //! - \b DMA_CHANNEL_2 + //! - \b DMA_CHANNEL_3 + //! - \b DMA_CHANNEL_4 + //! - \b DMA_CHANNEL_5 + //! - \b DMA_CHANNEL_6 + //! - \b DMA_CHANNEL_7 + uint8_t channelSelect; + //! Is the transfer mode of the selected channel. + //! \n Valid values are: + //! - \b DMA_TRANSFER_SINGLE [Default] + //! - \b DMA_TRANSFER_BLOCK + //! - \b DMA_TRANSFER_BURSTBLOCK + //! - \b DMA_TRANSFER_REPEATED_SINGLE + //! - \b DMA_TRANSFER_REPEATED_BLOCK + //! - \b DMA_TRANSFER_REPEATED_BURSTBLOCK + uint16_t transferModeSelect; + //! Is the amount of transfers to complete in a block transfer mode, as + //! well as how many transfers to complete before the interrupt flag is + //! set. Valid value is between 1-65535, if 0, no transfers will occur. + uint16_t transferSize; + //! Is the source that will trigger the start of each transfer, note that + //! the sources are device specific. + //! \n Valid values are: + //! - \b DMA_TRIGGERSOURCE_0 [Default] + //! - \b DMA_TRIGGERSOURCE_1 + //! - \b DMA_TRIGGERSOURCE_2 + //! - \b DMA_TRIGGERSOURCE_3 + //! - \b DMA_TRIGGERSOURCE_4 + //! - \b DMA_TRIGGERSOURCE_5 + //! - \b DMA_TRIGGERSOURCE_6 + //! - \b DMA_TRIGGERSOURCE_7 + //! - \b DMA_TRIGGERSOURCE_8 + //! - \b DMA_TRIGGERSOURCE_9 + //! - \b DMA_TRIGGERSOURCE_10 + //! - \b DMA_TRIGGERSOURCE_11 + //! - \b DMA_TRIGGERSOURCE_12 + //! - \b DMA_TRIGGERSOURCE_13 + //! - \b DMA_TRIGGERSOURCE_14 + //! - \b DMA_TRIGGERSOURCE_15 + //! - \b DMA_TRIGGERSOURCE_16 + //! - \b DMA_TRIGGERSOURCE_17 + //! - \b DMA_TRIGGERSOURCE_18 + //! - \b DMA_TRIGGERSOURCE_19 + //! - \b DMA_TRIGGERSOURCE_20 + //! - \b DMA_TRIGGERSOURCE_21 + //! - \b DMA_TRIGGERSOURCE_22 + //! - \b DMA_TRIGGERSOURCE_23 + //! - \b DMA_TRIGGERSOURCE_24 + //! - \b DMA_TRIGGERSOURCE_25 + //! - \b DMA_TRIGGERSOURCE_26 + //! - \b DMA_TRIGGERSOURCE_27 + //! - \b DMA_TRIGGERSOURCE_28 + //! - \b DMA_TRIGGERSOURCE_29 + //! - \b DMA_TRIGGERSOURCE_30 + //! - \b DMA_TRIGGERSOURCE_31 + uint8_t triggerSourceSelect; + //! Is the specified size of transfers. + //! \n Valid values are: + //! - \b DMA_SIZE_SRCWORD_DSTWORD [Default] + //! - \b DMA_SIZE_SRCBYTE_DSTWORD + //! - \b DMA_SIZE_SRCWORD_DSTBYTE + //! - \b DMA_SIZE_SRCBYTE_DSTBYTE + uint8_t transferUnitSelect; + //! Is the type of trigger that the trigger signal needs to be to start a + //! transfer. + //! \n Valid values are: + //! - \b DMA_TRIGGER_RISINGEDGE [Default] + //! - \b DMA_TRIGGER_HIGH + uint8_t triggerTypeSelect; +} DMA_initParam; + +//***************************************************************************** +// +// The following are values that can be passed to the triggerSourceSelect +// parameter for functions: DMA_init(); the param parameter for functions: +// DMA_init(). +// +//***************************************************************************** +#define DMA_TRIGGERSOURCE_0 (0x00) +#define DMA_TRIGGERSOURCE_1 (0x01) +#define DMA_TRIGGERSOURCE_2 (0x02) +#define DMA_TRIGGERSOURCE_3 (0x03) +#define DMA_TRIGGERSOURCE_4 (0x04) +#define DMA_TRIGGERSOURCE_5 (0x05) +#define DMA_TRIGGERSOURCE_6 (0x06) +#define DMA_TRIGGERSOURCE_7 (0x07) +#define DMA_TRIGGERSOURCE_8 (0x08) +#define DMA_TRIGGERSOURCE_9 (0x09) +#define DMA_TRIGGERSOURCE_10 (0x0A) +#define DMA_TRIGGERSOURCE_11 (0x0B) +#define DMA_TRIGGERSOURCE_12 (0x0C) +#define DMA_TRIGGERSOURCE_13 (0x0D) +#define DMA_TRIGGERSOURCE_14 (0x0E) +#define DMA_TRIGGERSOURCE_15 (0x0F) +#define DMA_TRIGGERSOURCE_16 (0x10) +#define DMA_TRIGGERSOURCE_17 (0x11) +#define DMA_TRIGGERSOURCE_18 (0x12) +#define DMA_TRIGGERSOURCE_19 (0x13) +#define DMA_TRIGGERSOURCE_20 (0x14) +#define DMA_TRIGGERSOURCE_21 (0x15) +#define DMA_TRIGGERSOURCE_22 (0x16) +#define DMA_TRIGGERSOURCE_23 (0x17) +#define DMA_TRIGGERSOURCE_24 (0x18) +#define DMA_TRIGGERSOURCE_25 (0x19) +#define DMA_TRIGGERSOURCE_26 (0x1A) +#define DMA_TRIGGERSOURCE_27 (0x1B) +#define DMA_TRIGGERSOURCE_28 (0x1C) +#define DMA_TRIGGERSOURCE_29 (0x1D) +#define DMA_TRIGGERSOURCE_30 (0x1E) +#define DMA_TRIGGERSOURCE_31 (0x1F) + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: DMA_init(); the transferModeSelect parameter for functions: +// DMA_init(). +// +//***************************************************************************** +#define DMA_TRANSFER_SINGLE (DMADT_0) +#define DMA_TRANSFER_BLOCK (DMADT_1) +#define DMA_TRANSFER_BURSTBLOCK (DMADT_2) +#define DMA_TRANSFER_REPEATED_SINGLE (DMADT_4) +#define DMA_TRANSFER_REPEATED_BLOCK (DMADT_5) +#define DMA_TRANSFER_REPEATED_BURSTBLOCK (DMADT_6) + +//***************************************************************************** +// +// The following are values that can be passed to the channelSelect parameter +// for functions: DMA_init(), DMA_setTransferSize(), DMA_getTransferSize(), +// DMA_setSrcAddress(), DMA_setDstAddress(), DMA_enableTransfers(), +// DMA_disableTransfers(), DMA_startTransfer(), DMA_enableInterrupt(), +// DMA_disableInterrupt(), DMA_getInterruptStatus(), DMA_clearInterrupt(), +// DMA_getNMIAbortStatus(), and DMA_clearNMIAbort(); the param parameter for +// functions: DMA_init(). +// +//***************************************************************************** +#define DMA_CHANNEL_0 (0x00) +#define DMA_CHANNEL_1 (0x10) +#define DMA_CHANNEL_2 (0x20) +#define DMA_CHANNEL_3 (0x30) +#define DMA_CHANNEL_4 (0x40) +#define DMA_CHANNEL_5 (0x50) +#define DMA_CHANNEL_6 (0x60) +#define DMA_CHANNEL_7 (0x70) + +//***************************************************************************** +// +// The following are values that can be passed to the triggerTypeSelect +// parameter for functions: DMA_init(); the param parameter for functions: +// DMA_init(). +// +//***************************************************************************** +#define DMA_TRIGGER_RISINGEDGE (!(DMALEVEL)) +#define DMA_TRIGGER_HIGH (DMALEVEL) + +//***************************************************************************** +// +// The following are values that can be passed to the transferUnitSelect +// parameter for functions: DMA_init(); the param parameter for functions: +// DMA_init(). +// +//***************************************************************************** +#define DMA_SIZE_SRCWORD_DSTWORD (!(DMASRCBYTE + DMADSTBYTE)) +#define DMA_SIZE_SRCBYTE_DSTWORD (DMASRCBYTE) +#define DMA_SIZE_SRCWORD_DSTBYTE (DMADSTBYTE) +#define DMA_SIZE_SRCBYTE_DSTBYTE (DMASRCBYTE + DMADSTBYTE) + +//***************************************************************************** +// +// The following are values that can be passed to the directionSelect parameter +// for functions: DMA_setSrcAddress(), and DMA_setDstAddress(). +// +//***************************************************************************** +#define DMA_DIRECTION_UNCHANGED (DMASRCINCR_0) +#define DMA_DIRECTION_DECREMENT (DMASRCINCR_2) +#define DMA_DIRECTION_INCREMENT (DMASRCINCR_3) + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the DMA_getInterruptStatus() function. +// +//***************************************************************************** +#define DMA_INT_INACTIVE (0x0) +#define DMA_INT_ACTIVE (DMAIFG) + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the DMA_getNMIAbortStatus() function. +// +//***************************************************************************** +#define DMA_NOTABORTED (0x0) +#define DMA_ABORTED (DMAABORT) + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Initializes the specified DMA channel. +//! +//! This function initializes the specified DMA channel. Upon successful +//! completion of initialization of the selected channel the control registers +//! will be cleared and the given variables will be set. Please note, if +//! transfers have been enabled with the enableTransfers() function, then a +//! call to disableTransfers() is necessary before re-initialization. Also +//! note, that the trigger sources are device dependent and can be found in the +//! device family data sheet. The amount of DMA channels available are also +//! device specific. +//! +//! \param param is the pointer to struct for initialization. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the initialization process. +// +//***************************************************************************** +extern void DMA_init(DMA_initParam *param); + +//***************************************************************************** +// +//! \brief Sets the specified amount of transfers for the selected DMA channel. +//! +//! This function sets the specified amount of transfers for the selected DMA +//! channel without having to reinitialize the DMA channel. +//! +//! \param channelSelect is the specified channel to set source address +//! direction for. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! \param transferSize is the amount of transfers to complete in a block +//! transfer mode, as well as how many transfers to complete before the +//! interrupt flag is set. Valid value is between 1-65535, if 0, no +//! transfers will occur. +//! \n Modified bits are \b DMAxSZ of \b DMAxSZ register. +//! +//! \return None +// +//***************************************************************************** +extern void DMA_setTransferSize(uint8_t channelSelect, + uint16_t transferSize); + +//***************************************************************************** +// +//! \brief Gets the amount of transfers for the selected DMA channel. +//! +//! This function gets the amount of transfers for the selected DMA channel +//! without having to reinitialize the DMA channel. +//! +//! \param channelSelect is the specified channel to set source address +//! direction for. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! +//! \return the amount of transfers +// +//***************************************************************************** +extern uint16_t DMA_getTransferSize(uint8_t channelSelect); + +//***************************************************************************** +// +//! \brief Sets source address and the direction that the source address will +//! move after a transfer. +//! +//! This function sets the source address and the direction that the source +//! address will move after a transfer is complete. It may be incremented, +//! decremented or unchanged. +//! +//! \param channelSelect is the specified channel to set source address +//! direction for. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! \param srcAddress is the address of where the data will be transferred +//! from. +//! \n Modified bits are \b DMAxSA of \b DMAxSA register. +//! \param directionSelect is the specified direction of the source address +//! after a transfer. +//! Valid values are: +//! - \b DMA_DIRECTION_UNCHANGED +//! - \b DMA_DIRECTION_DECREMENT +//! - \b DMA_DIRECTION_INCREMENT +//! \n Modified bits are \b DMASRCINCR of \b DMAxCTL register. +//! +//! \return None +// +//***************************************************************************** +extern void DMA_setSrcAddress(uint8_t channelSelect, + uint32_t srcAddress, + uint16_t directionSelect); + +//***************************************************************************** +// +//! \brief Sets the destination address and the direction that the destination +//! address will move after a transfer. +//! +//! This function sets the destination address and the direction that the +//! destination address will move after a transfer is complete. It may be +//! incremented, decremented, or unchanged. +//! +//! \param channelSelect is the specified channel to set the destination +//! address direction for. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! \param dstAddress is the address of where the data will be transferred to. +//! \n Modified bits are \b DMAxDA of \b DMAxDA register. +//! \param directionSelect is the specified direction of the destination +//! address after a transfer. +//! Valid values are: +//! - \b DMA_DIRECTION_UNCHANGED +//! - \b DMA_DIRECTION_DECREMENT +//! - \b DMA_DIRECTION_INCREMENT +//! \n Modified bits are \b DMADSTINCR of \b DMAxCTL register. +//! +//! \return None +// +//***************************************************************************** +extern void DMA_setDstAddress(uint8_t channelSelect, + uint32_t dstAddress, + uint16_t directionSelect); + +//***************************************************************************** +// +//! \brief Enables transfers to be triggered. +//! +//! This function enables transfers upon appropriate trigger of the selected +//! trigger source for the selected channel. +//! +//! \param channelSelect is the specified channel to enable transfer for. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! +//! \return None +// +//***************************************************************************** +extern void DMA_enableTransfers(uint8_t channelSelect); + +//***************************************************************************** +// +//! \brief Disables transfers from being triggered. +//! +//! This function disables transfer from being triggered for the selected +//! channel. This function should be called before any re-initialization of the +//! selected DMA channel. +//! +//! \param channelSelect is the specified channel to disable transfers for. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! +//! \return None +// +//***************************************************************************** +extern void DMA_disableTransfers(uint8_t channelSelect); + +//***************************************************************************** +// +//! \brief Starts a transfer if using the default trigger source selected in +//! initialization. +//! +//! This functions triggers a transfer of data from source to destination if +//! the trigger source chosen from initialization is the DMA_TRIGGERSOURCE_0. +//! Please note, this function needs to be called for each (repeated-)single +//! transfer, and when transferAmount of transfers have been complete in +//! (repeated-)block transfers. +//! +//! \param channelSelect is the specified channel to start transfers for. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! +//! \return None +// +//***************************************************************************** +extern void DMA_startTransfer(uint8_t channelSelect); + +//***************************************************************************** +// +//! \brief Enables the DMA interrupt for the selected channel. +//! +//! Enables the DMA interrupt source. Only the sources that are enabled can be +//! reflected to the processor interrupt; disabled sources have no effect on +//! the processor. Does not clear interrupt flags. +//! +//! \param channelSelect is the specified channel to enable the interrupt for. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! +//! \return None +// +//***************************************************************************** +extern void DMA_enableInterrupt(uint8_t channelSelect); + +//***************************************************************************** +// +//! \brief Disables the DMA interrupt for the selected channel. +//! +//! Disables the DMA interrupt source. Only the sources that are enabled can be +//! reflected to the processor interrupt; disabled sources have no effect on +//! the processor. +//! +//! \param channelSelect is the specified channel to disable the interrupt for. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! +//! \return None +// +//***************************************************************************** +extern void DMA_disableInterrupt(uint8_t channelSelect); + +//***************************************************************************** +// +//! \brief Returns the status of the interrupt flag for the selected channel. +//! +//! Returns the status of the interrupt flag for the selected channel. +//! +//! \param channelSelect is the specified channel to return the interrupt flag +//! status from. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! +//! \return One of the following: +//! - \b DMA_INT_INACTIVE +//! - \b DMA_INT_ACTIVE +//! \n indicating the status of the current interrupt flag +// +//***************************************************************************** +extern uint16_t DMA_getInterruptStatus(uint8_t channelSelect); + +//***************************************************************************** +// +//! \brief Clears the interrupt flag for the selected channel. +//! +//! This function clears the DMA interrupt flag is cleared, so that it no +//! longer asserts. +//! +//! \param channelSelect is the specified channel to clear the interrupt flag +//! for. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! +//! \return None +// +//***************************************************************************** +extern void DMA_clearInterrupt(uint8_t channelSelect); + +//***************************************************************************** +// +//! \brief Returns the status of the NMIAbort for the selected channel. +//! +//! This function returns the status of the NMI Abort flag for the selected +//! channel. If this flag has been set, it is because a transfer on this +//! channel was aborted due to a interrupt from an NMI. +//! +//! \param channelSelect is the specified channel to return the status of the +//! NMI Abort flag for. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! +//! \return One of the following: +//! - \b DMA_NOTABORTED +//! - \b DMA_ABORTED +//! \n indicating the status of the NMIAbort for the selected channel +// +//***************************************************************************** +extern uint16_t DMA_getNMIAbortStatus(uint8_t channelSelect); + +//***************************************************************************** +// +//! \brief Clears the status of the NMIAbort to proceed with transfers for the +//! selected channel. +//! +//! This function clears the status of the NMI Abort flag for the selected +//! channel to allow for transfers on the channel to continue. +//! +//! \param channelSelect is the specified channel to clear the NMI Abort flag +//! for. +//! Valid values are: +//! - \b DMA_CHANNEL_0 +//! - \b DMA_CHANNEL_1 +//! - \b DMA_CHANNEL_2 +//! - \b DMA_CHANNEL_3 +//! - \b DMA_CHANNEL_4 +//! - \b DMA_CHANNEL_5 +//! - \b DMA_CHANNEL_6 +//! - \b DMA_CHANNEL_7 +//! +//! \return None +// +//***************************************************************************** +extern void DMA_clearNMIAbort(uint8_t channelSelect); + +//***************************************************************************** +// +//! \brief Disables the DMA from stopping the CPU during a Read-Modify-Write +//! Operation to start a transfer. +//! +//! This function allows the CPU to finish any read-modify-write operations it +//! may be in the middle of before transfers of and DMA channel stop the CPU. +//! +//! +//! \return None +// +//***************************************************************************** +extern void DMA_disableTransferDuringReadModifyWrite(void); + +//***************************************************************************** +// +//! \brief Enables the DMA to stop the CPU during a Read-Modify-Write Operation +//! to start a transfer. +//! +//! This function allows the DMA to stop the CPU in the middle of a read- +//! modify-write operation to transfer data. +//! +//! +//! \return None +// +//***************************************************************************** +extern void DMA_enableTransferDuringReadModifyWrite(void); + +//***************************************************************************** +// +//! \brief Enables Round Robin prioritization. +//! +//! This function enables Round Robin Prioritization of DMA channels. In the +//! case of Round Robin Prioritization, the last DMA channel to have +//! transferred data then has the last priority, which comes into play when +//! multiple DMA channels are ready to transfer at the same time. +//! +//! +//! \return None +// +//***************************************************************************** +extern void DMA_enableRoundRobinPriority(void); + +//***************************************************************************** +// +//! \brief Disables Round Robin prioritization. +//! +//! This function disables Round Robin Prioritization, enabling static +//! prioritization of the DMA channels. In static prioritization, the DMA +//! channels are prioritized with the lowest DMA channel index having the +//! highest priority (i.e. DMA Channel 0 has the highest priority). +//! +//! +//! \return None +// +//***************************************************************************** +extern void DMA_disableRoundRobinPriority(void); + +//***************************************************************************** +// +//! \brief Enables a NMI to interrupt a DMA transfer. +//! +//! This function allow NMI's to interrupting any DMA transfer currently in +//! progress and stops any future transfers to begin before the NMI is done +//! processing. +//! +//! +//! \return None +// +//***************************************************************************** +extern void DMA_enableNMIAbort(void); + +//***************************************************************************** +// +//! \brief Disables any NMI from interrupting a DMA transfer. +//! +//! This function disables NMI's from interrupting any DMA transfer currently +//! in progress. +//! +//! +//! \return None +// +//***************************************************************************** +extern void DMA_disableNMIAbort(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_DMA_H__ diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/driverlib.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/driverlib.h new file mode 100644 index 000000000..a33349ec3 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/driverlib.h @@ -0,0 +1,61 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +#include "inc/hw_memmap.h" + +#include "adc12_b.h" +#include "aes256.h" +#include "comp_e.h" +#include "crc.h" +#include "crc32.h" +#include "cs.h" +#include "dma.h" +#include "esi.h" +#include "eusci_a_spi.h" +#include "eusci_a_uart.h" +#include "eusci_b_i2c.h" +#include "eusci_b_spi.h" +#include "framctl.h" +#include "gpio.h" +#include "lcd_c.h" +#include "mpu.h" +#include "mpy32.h" +#include "pmm.h" +#include "ram.h" +#include "ref_a.h" +#include "rtc_b.h" +#include "rtc_c.h" +#include "sfr.h" +#include "sysctl.h" +#include "timer_a.h" +#include "timer_b.h" +#include "tlv.h" +#include "wdt_a.h" diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/esi.c b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/esi.c new file mode 100644 index 000000000..edc1020f5 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/esi.c @@ -0,0 +1,1478 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// esi.h - Driver for the ESI Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup esi_api +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_ESI__ +#include "esi.h" + +#include + +// Uncomment for finding lower peak of the lower half cycle. +// This required to set ESI comparator output as inverted +#define INVERTED + +static uint16_t measureESIOSC(void); +static void FindDAC(uint8_t selected_channel, + uint8_t software_trigger); + +const ESI_AFE1_InitParams ESI_AFE1_INITPARAMS_DEFAULT = +{ESI_EXCITATION_CIRCUIT_DISABLED, + ESI_SAMPLE_HOLD_DISABLED, + ESI_MID_VOLTAGE_GENERATOR_DISABLED, + ESI_SAMPLE_HOLD_VSS_TO_ESIVSS, + ESI_INVERTER_FOR_AFE1_DISABLE}; + +const ESI_AFE2_InitParams ESI_AFE2_INITPARAMS_DEFAULT = { + ESI_AFE2_INPUT_SELECT_CHx, + ESI_INVERTER_FOR_AFE2_DISABLE, + ESI_TSM_COMPARATOR_CONTROL_AFE2_DISABLE, + ESI_TSM_DAC_CONTROL_AFE2_DISABLE +}; + +const ESI_TSM_InitParams ESI_TSM_INITPARAMS_DEFAULT = { ESI_TSM_SMCLK_DIV_1, + ESI_TSM_ACLK_DIV_1, + ESI_TSM_START_TRIGGER_DIV_2, + ESI_TSM_REPEAT_NEW_TRIGGER, + ESI_TSM_STOP_SEQUENCE, + ESI_TSM_HIGH_FREQ_CLK_FUNCTION_ON}; + +const ESI_PSM_InitParams ESI_PSM_INITPARAMS_DEFAULT = { ESI_PSM_Q6_DISABLE, + ESI_PSM_Q7_TRIGGER_DISABLE, + ESI_PSM_CNT0_DISABLE, + ESI_PSM_CNT0_RESET, + ESI_PSM_CNT1_DISABLE, + ESI_PSM_CNT1_RESET, + ESI_PSM_CNT2_DISABLE, + ESI_PSM_CNT2_RESET, + ESI_PSM_S3_SELECT, + ESI_PSM_TEST4_IS_Q2,}; + +//***************************************************************************** +// +//! Get ESI PSM Counter 0 Value +//! +//! This function reads the ESI Counter 0 register +//! +//! \return Counter value +// +//***************************************************************************** +uint16_t ESI_getCounter0(void) +{ + return (ESICNT0); +} + +//***************************************************************************** +// +//! Get ESI PSM Counter 1 Value +//! +//! This function reads the ESI Counter1 register +//! +//! \return Counter value +// +//***************************************************************************** +uint16_t ESI_getCounter1(void) +{ + return (ESICNT1); +} + +//***************************************************************************** +// +//! Get ESI PSM Counter 2 Value +//! +//! This function reads the ESI Counter2 register +//! +//! \return Counter value +// +//***************************************************************************** +uint16_t ESI_getCounter2(void) +{ + return (ESICNT2); +} + +//***************************************************************************** +// +//! Get ESI PSM Oscillator Counter Value +//! +//! This function reads the ESI Oscillator Counter register +//! +//! \return Counter value +// +//***************************************************************************** +uint16_t ESI_getOscCounter(void) +{ + return (ESICNT3); +} + +//***************************************************************************** +// +//! Initializes the ESI analog front end AFE1 +//! +//! \param params is ESI_AFE1_InitParams struct +//! +//! This functions initializes the ESI analog front end AFE1. +//! +//! \return None +// +//***************************************************************************** + +void ESI_AFE1_init(ESI_AFE1_InitParams *params) +{ + // Unset the AFE1 bits + ESIAFE &= ~(ESITEN + ESISH + ESIVCC2 + ESIVSS + ESICACI3 + ESICISEL + + ESICA1X + ESICA1INV); + ESIAFE |= + params->excitationCircuitSelect + + params->sampleAndHoldSelect + + params->midVoltageGeneratorSelect + + params->sampleAndHoldVSSConnect + + params->inverterSelectOutputAFE1 + ; + + switch(params->inputSelectAFE1) + { + case ESI_AFE1_INPUT_SELECT_CHx: + break; + case ESI_AFE1_INPUT_SELECT_CIx: + ESIAFE |= ESICA1X; + break; + case ESI_AFE1_INPUT_SELECT_CI3: + ESIAFE |= ESICA1X; + ESIAFE &= ~ESICISEL; + ESIAFE |= ESICACI3; + break; + case ESI_AFE1_INPUT_SELECT_CI: + ESIAFE |= ESICA1X; + ESIAFE |= ESICISEL; + break; + default: + break; + } +} + +//***************************************************************************** +// +//! Initializes the ESI analog front end - AFE2 +//! +//! \param params is ESI_AFE2_InitParams struct +//! +//! This functions initializes the ESI analog front end AFE2 +//! +//! \return None +// +//***************************************************************************** + +void ESI_AFE2_init(ESI_AFE2_InitParams *params) +{ + // Unset the AFE2 bits + ESIAFE &= ~(ESICA2X + ESICA2INV + ESICA2EN + ESIDAC2EN); + + ESIAFE |= + params->inputSelectAFE2 + + params->inverterSelectOutputAFE2 + + params->tsmControlComparatorAFE2 + + params->tsmControlDacAFE2 + ; +} + +//***************************************************************************** +// +//! Reads the latched comparator outputs form the AFEs +//! +//! \param channelSelect. Valid values are +//! ESI_AFE1_CHANNEL0_SELECT +//! ESI_AFE1_CHANNEL1_SELECT +//! ESI_AFE1_CHANNEL2_SELECT +//! ESI_AFE1_CHANNEL3_SELECT +//! ESI_AFE2_CHANNEL0_SELECT +//! ESI_AFE2_CHANNEL1_SELECT +//! ESI_AFE2_CHANNEL2_SELECT +//! ESI_AFE2_CHANNEL3_SELECT +//! ESI_AFE1_TEST_CHANNEL0_SELECT +//! ESI_AFE1_TEST_CHANNEL1_SELECT +//! +//! This function gets the ESIPPU register to get latched output values of the +//! comparator outputs for AFE1 and AFE2 +//! +//! \return Valid values are +//! ESI_AFE_OUTPUT_LOW +//! ESI_AFE_OUTPUT_HIGH +// +//***************************************************************************** +uint16_t ESI_getLatchedComparatorOutput(uint16_t channelSelect) +{ + uint16_t result; + + result = ESIPPU; + + return (result &= channelSelect); +} + +//***************************************************************************** +// +//! Initializes the TSM +//! +//! \param params is ESI_TSM_InitParams struct +//! +//! This function initializes the TSM. +//! +//! \return None +// +//***************************************************************************** + +void ESI_TSM_init(ESI_TSM_InitParams *params) +{ + ESITSM = + params->smclkDivider + + params->aclkDivider + + params->startTriggerAclkDivider + + params->repeatMode + + params->startTriggerSelection + + params->tsmFunctionSelection + ; +} + +//***************************************************************************** +// +//! Clear TSM entries +//! +//! This function clears all TSM entries +//! +//! \return None +// +//***************************************************************************** +void ESI_TSM_clearTable(void) +{ + uint16_t *pTsm, i; + + // Clear TSM Table (for testing only. not neccessary in real application) + pTsm = (uint16_t *)&ESITSM0; + for(i = 0; i < 32; i++) + { + *pTsm++ = 0x0200; + } +} + +//***************************************************************************** +// +//! Copy TSM entries +//! +//! This function copies all TSM entries +//! +//! \return None +// +//***************************************************************************** +void ESI_TSM_copyTable(uint16_t* tsmTable, + uint16_t size) +{ + uint16_t *pt_tsmTable; + uint16_t i; + + // Copy the TSM_Table into ESI TSM registers + // Destination pointer + pt_tsmTable = (uint16_t *)&ESITSM0; + // Divided by 2 because of unsigned integer (2bytes) + i = size / 2; + + do + { + *pt_tsmTable++ = *tsmTable++; + } + while(--i); +} + +//***************************************************************************** +// +//! TSM trigger using software +//! +//! This function starts a software initiated TSM sequence +//! +//! \return None +// +//***************************************************************************** +void ESI_TSM_softwareTrigger(void) +{ + ESITSM |= ESISTART; +} + +//***************************************************************************** +// +//! TSM trigger using software +//! +//! This function starts a software initiated TSM sequence +//! +//! \return ESIREATx bits from selected stateRegNum +// +//***************************************************************************** +uint8_t ESI_TSM_getTSMStateDuration(uint8_t stateRegNum) +{ + volatile uint16_t* stateRegBase = (volatile uint16_t*)&ESITSM0; + + return((*(stateRegBase + stateRegNum) & 0xf800) >> 11); +} + +//***************************************************************************** +// +//! TSM trigger using software +//! +//! This function starts a software initiated TSM sequence +//! +//! \return ESIREATx bits from selected stateRegNum +// +//***************************************************************************** +void ESI_TSM_setTSMStateDuration(uint8_t stateRegNum, + uint8_t duration) +{ + assert(stateRegNum <= ESI_TSM_STATE_REG_31); + assert(duration <= ESI_TSM_STATE_DURATION_MAX); + + volatile uint16_t* stateRegBase = (volatile uint16_t*)&ESITSM0; + + *(stateRegBase + stateRegNum) &= ~0xF800; + + *(stateRegBase + stateRegNum) |= (duration << 11); +} + +//***************************************************************************** +// +//! Initialize Processing State Machine +// +//! \param params is ESI_PSM_InitParams struct +//! +//! This function initializes the PSM registers. +//! +//! \return None +// +//***************************************************************************** +void ESI_PSM_init(ESI_PSM_InitParams *params) +{ + ESIPSM = + params->Q6Select + + params->Q7TriggerSelect + + params->count0Select + + params->count0Reset + + params->count1Select + + params->count1Reset + + params->count2Select + + params->count2Reset + + params->V2Select + + params->TEST4Select + ; +} + +//***************************************************************************** +// +//! Clear PSM entries +//! +//! This function clears all PSM entries +//! +//! \return None +// +//***************************************************************************** +void ESI_PSM_clearTable(void) +{ + uint8_t *pPsm, i; + + // Clear TSM Table (for testing only. not neccessary in real application) + pPsm = (uint8_t *)&ESIRAM0; + for(i = 0; i < 128; i++) + { + *pPsm++ = 0x0; + } +} + +//***************************************************************************** +// +//! Copy PSM entries +//! +//! This function copies all PSM entries +//! +//! \return None +// +//***************************************************************************** +void ESI_PSM_copyTable(uint8_t* psmTable, + uint8_t size) +{ + uint8_t *pt_psmTable; + uint8_t i; + + assert(size <= 128); + + // Copy the TSM_Table into ESI TSM registers + pt_psmTable = (uint8_t *)&ESIRAM0; // Destination pointer + i = size; + + do + { + *pt_psmTable++ = *psmTable++; + } + while(--i); +} + +//***************************************************************************** +// +//! Reset PSM counters +//! +//! \param counterToReset is the counter that needs t be reset +//! +//! This function resets the PSM counters +//! +//! \return None +// +//***************************************************************************** +void ESI_PSM_resetCounter(uint16_t counterToReset) +{ + ESIPSM |= counterToReset; +} + +//***************************************************************************** +// +//! Enables the internal Oscillator +//! +//! +//! This function enables the high frequency internal oscillator +//! +//! \return None +// +//***************************************************************************** +void ESI_enableInternalOscillator(void) +{ + ESIOSC |= ESIHFSEL; +} + +//***************************************************************************** +// +//! Disables the internal Oscillator +//! +//! +//! This function disables the high frequency internal oscillator +//! +//! \return None +// +//***************************************************************************** +void ESI_disableInternalOscillator(void) +{ + ESIOSC &= ~ESIHFSEL; +} + +//***************************************************************************** +// +//! Connects comparator output to timerA input +//! +//! \param counterToReset ESI_TIMERA_INPUT_TSM_COMPOUT or +//! ESI_TIMERA_INPUT_TSM_PPUSRC +//! +//! This function connects the chosen comparator output to TimerA +//! +//! \return None +// +//***************************************************************************** +void ESI_timerAInputSelect(uint16_t select) +{ + ESICTL |= select; +} + +//***************************************************************************** +// +//! Connects psm source to comparator output +//! +//! \param sourceNum PSM_S1_SOURCE, PSM_S2_SOURCE or PSM_S3_SOURCE +//! \param sourceSelect can have the following values +//! ESI_PSM_SOURCE_IS_ESIOUT0 +//! ESI_PSM_SOURCE_IS_ESIOUT1 +//! ESI_PSM_SOURCE_IS_ESIOUT2 +//! ESI_PSM_SOURCE_IS_ESIOUT3 +//! ESI_PSM_SOURCE_IS_ESIOUT4 +//! ESI_PSM_SOURCE_IS_ESIOUT5 +//! ESI_PSM_SOURCE_IS_ESIOUT6 +//! ESI_PSM_SOURCE_IS_ESIOUT7 +//! +//! This function connects the chosen comparator output to TimerA +//! +//! \return None +// +//***************************************************************************** +void ESI_psmSourceSelect(uint16_t sourceNum, + uint16_t sourceSelect) +{ + switch(sourceNum) + { + case PSM_S1_SOURCE: + ESICTL &= ~(ESIS1SEL0 | ESIS1SEL1 | ESIS1SEL2); + ESICTL |= (sourceSelect << 7); + break; + case PSM_S2_SOURCE: + ESICTL &= ~(ESIS2SEL0 | ESIS2SEL1 | ESIS2SEL2); + ESICTL |= (sourceSelect << 10); + break; + case PSM_S3_SOURCE: + ESICTL &= ~(ESIS3SEL0 | ESIS3SEL1 | ESIS3SEL2); + ESICTL |= (sourceSelect << 13); + break; + default: + break; + } +} + +//***************************************************************************** +// +//! Connects testChannel0 to comparator input +//! +//! \param sourceSelect can have the following values +//! ESI_TEST_CHANNEL0_SOURCE_IS_CH0_CI0 +//! ESI_TEST_CHANNEL0_SOURCE_IS_CH1_CI1 +//! ESI_TEST_CHANNEL0_SOURCE_IS_CH2_CI2 +//! ESI_TEST_CHANNEL0_SOURCE_IS_CH3_CI3 +//! +//! This function connects the chosen comparator input to the test channel0 +//! +//! \return None +// +//***************************************************************************** +void ESI_testChannel0SourceSelect(uint16_t sourceSelect) +{ + ESICTL &= ~(ESI_TEST_CHANNEL0_SOURCE_IS_CH3_CI3); + ESICTL |= sourceSelect; +} + +//***************************************************************************** +// +//! Connects testChannel1to comparator input +//! +//! \param sourceSelect can have the following values +//! ESI_TEST_CHANNEL1_SOURCE_IS_CH0_CI0 +//! ESI_TEST_CHANNEL1_SOURCE_IS_CH1_CI1 +//! ESI_TEST_CHANNEL1_SOURCE_IS_CH2_CI2 +//! ESI_TEST_CHANNEL1_SOURCE_IS_CH3_CI3 +//! +//! This function connects the chosen comparator input to the test channel1 +//! +//! \return None +// +//***************************************************************************** +void ESI_testChannel1SourceSelect(uint16_t sourceSelect) +{ + ESICTL &= ~(ESI_TEST_CHANNEL1_SOURCE_IS_CH3_CI3); + ESICTL |= sourceSelect; +} + +//***************************************************************************** +// +//! Enable ESI peripheral +//! +//! \return None +// +//***************************************************************************** +void ESI_enable(void) +{ + ESICTL |= ESIEN; +} + +//***************************************************************************** +// +//! Disable ESI peripheral +//! +//! \return None +// +//***************************************************************************** +void ESI_disable(void) +{ + ESICTL &= ~ESIEN; +} + +//***************************************************************************** +// +//! Start calibration on ESI internal Oscillator +//! +//! This function starts calibration of internal osciallator. After calling this +//! function the user and use ESI_adjustInternalOscFreq() to adjust the freq. of +//! the oscillator. +//! +//! \return None +// +//***************************************************************************** +void ESI_startInternalOscCal(void) +{ + assert(ESIOSC | ESIHFSEL); + ESIOSC |= ESICLKGON; +} + +//***************************************************************************** +// +//! Adjusts frequency ESI internal Oscillator +//! +//! This function adjusts frequency ESI internal Oscillator. It increases or +//! decrease the freq by 3% based on incOrDec value. +//! +//! \return None +// +//***************************************************************************** +void ESI_adjustInternalOscFreq(uint16_t incOrDec) +{ + uint16_t adjustValue; + + assert(ESIOSC | ESIHFSEL); + + adjustValue = ESIOSC >> 8; + + if(incOrDec == ESI_INTERNAL_OSC_FREQ_INCREASE) + { + adjustValue = adjustValue + 1; + adjustValue = adjustValue << 8; + } + else + { + adjustValue = adjustValue - 1; + adjustValue = adjustValue << 8; + } + + ESIOSC |= adjustValue; +} + +//***************************************************************************** +// +//! Sets frequency of ESI internal Oscillator +//! +//! +//! \return None +// +//***************************************************************************** +void ESI_setNominalInternalOscFreq(void) +{ + ESIOSC = ESICLKFQ5 + ESICLKGON + ESIHFSEL; +} + +//***************************************************************************** +// +//! The following function return the number of ESIOSC cycle during an ACLK +//! cycle. +//! +//! +//! \return None +// +//***************************************************************************** +static uint16_t measureESIOSC(void){ + // This and next instruction realizes a clear->set ESICLKGON bit. + ESIOSC &= ~(ESICLKGON); + + // This starts measurement. + ESIOSC |= ESICLKGON + ESIHFSEL; + + // Reading ESICNT3 while counting always result in reading a 0x01. + while(ESICNT3 == 1) + { + ; + } + + // Stop ESIOSC oscillator + ESIOSC &= ~(ESICLKGON); + + return (ESICNT3); +} + +//****************************************************************************** +//! The following function returns the ESICLKFQx bits on ESIOSC register +// +//! \param none +// +//! \return ESICLKFQ bits only +//****************************************************************************** + +uint8_t ESI_getESICLKFQ(void){ + uint16_t temp; + + // Store ESIOSC content + temp = ESIOSC; + // Get ESICLKFQx bits + temp = (temp >> 8) & 0x3F; + + return(temp); +} + +//****************************************************************************** +//! The following function sets ESICLKFQx bits on ESIOSC register +// +//! \param setting is to the loaded to ESIOSC. Valid parameters a value between +//! 0x00 and 0x3F. 0x00 corresponds to minimum frequency, 0x20 +//! corresponds to nominal frequency and 0x3F corresponds to maximum +//! frequency. +// +//! \return none +//****************************************************************************** +void ESI_setESICLKFQ(uint8_t setting) +{ + uint16_t temp; + + assert(setting < 0x40); + + temp = ESIOSC; // get actual ESIOSC register content + temp &= ~(0x3F00); + temp = ((uint16_t) setting << 8) + temp; // and update ESICLKFQ bits + ESIOSC = temp; +} + +//***************************************************************************** +// +//! Calibrate ESI internal Oscillator +//! +//! +//! \return None +// +//***************************************************************************** +void ESI_calibrateInternalOscFreq(uint16_t targetAclkCounts) +{ + ESI_setNominalInternalOscFreq(); + + ESI_measureESIOSC(ESI_ESIOSC_OVERSAMPLE_4); + + if(ESICNT3 > targetAclkCounts) + { + //freq is too high + do + { + ESI_adjustInternalOscFreq(ESI_INTERNAL_OSC_FREQ_DECREASE); + } + while(ESI_measureESIOSC(ESI_ESIOSC_OVERSAMPLE_4) > targetAclkCounts); + } + else + { + //freq is too low + do + { + ESI_adjustInternalOscFreq(ESI_INTERNAL_OSC_FREQ_INCREASE); + } + while(ESI_measureESIOSC(ESI_ESIOSC_OVERSAMPLE_4) > targetAclkCounts); + ESI_adjustInternalOscFreq(ESI_INTERNAL_OSC_FREQ_DECREASE); + } +} + +//***************************************************************************** +// +//! The following function returns an average of ESIOSC measurement. +//! +//! \param +//! +//! \return averaged ESIOSC measurement. +// +//***************************************************************************** +uint16_t ESI_measureESIOSC(uint8_t oversample){ + uint8_t i; + uint16_t temp = 0; + + assert(oversample < 9); + + for(i = oversample; i > 0; i--) + { + temp += measureESIOSC(); + } + + temp /= oversample; + return(temp); +} + +//***************************************************************************** +// +//! Set upper threshold for PSM counter 1 +//! +//! \param threshold is the upper threashold that causes ESIIFG3 to get set. +//! +//! This function sets the threshold value for PSM counter 1. ESIIFG3 gets set +//! when counter value and this threahold are equal. +//! +//! \return None +// +//***************************************************************************** +void ESI_setPSMCounter1UpperThreshold(uint16_t threshold) +{ + ESITHR1 = threshold; +} + +//***************************************************************************** +// +//! Set lower threshold for PSM counter 1 +//! +//! \param threshold is the lower threashold that causes ESIIFG3 to get set. +//! +//! This function set the threshold value for PSM counter 1. ESIIFG3 gets set +//! when counter value and this threahold are equal. +//! +//! \return None +// +//***************************************************************************** +void ESI_setPSMCounter1LowerThreshold(uint16_t threshold) +{ + ESITHR2 = threshold; +} + +//***************************************************************************** +// +//! sets AFE1 DAC threshold Value +//! +//! \param dacValue is value to be written to DAC register. +//! \param dacRegNum is DAC register number +//! +//! Write DAC threshold value into selected DAC register +//! +//! \return None +// +//***************************************************************************** +void ESI_setAFE1DACValue(uint16_t dacValue, + uint8_t dacRegNum) +{ + volatile uint16_t* dacRegBase = (volatile uint16_t*) &ESIDAC1R0; + *(dacRegBase + dacRegNum) = dacValue; +} + +//***************************************************************************** +// +//! gets AFE1 DAC threshold Value +//! +//! \param dacValue is value to be written to DAC register. +//! \param dacRegNum is DAC register number +//! +//! Read DAC threshold value into selected DAC register +//! +//! \return DAC value from selected DAC register. +// +//***************************************************************************** +uint16_t ESI_getAFE1DACValue(uint8_t dacRegNum) +{ + volatile uint16_t* dacRegBase = (volatile uint16_t*) &ESIDAC1R0; + return(*(dacRegBase + dacRegNum)); +} + +//***************************************************************************** +// +//! sets AFE2 DAC threshold Value +//! +//! \param dacValue is value to be written to DAC register. +//! \param dacRegNum is DAC register number +//! +//! Write DAC threshold value into selected DAC register +//! +//! \return None +// +//***************************************************************************** +void ESI_setAFE2DACValue(uint16_t dacValue, + uint8_t dacRegNum) +{ + volatile uint16_t* dacRegBase = (volatile uint16_t*) &ESIDAC2R0; + *(dacRegBase + dacRegNum) = dacValue; +} + +//***************************************************************************** +// +//! gets AFE2 DAC threshold Value +//! +//! \param dacValue is value to be written to DAC register. +//! \param dacRegNum is DAC register number +//! +//! Read DAC threshold value into selected DAC register +//! +//! \return DAC value from selected DAC register. +// +//***************************************************************************** +uint16_t ESI_getAFE2DACValue(uint8_t dacRegNum) +{ + volatile uint16_t* dacRegBase = (volatile uint16_t*) &ESIDAC2R0; + return(*(dacRegBase + dacRegNum)); +} + +//***************************************************************************** +// +//! sets TSM state register +//! +//! \param params constructs the state value +//! \param stateRegNum is state register offset +//! +//! Sets selected TSM state register. +//! +//! \return None +// +//***************************************************************************** +void ESI_setTSMstateReg(ESI_TSM_StateParams *params, + uint8_t stateRegNum) +{ + volatile uint16_t* stateRegBase = (volatile uint16_t*) &ESITSM0; + *(stateRegBase + stateRegNum) = + (params->inputChannelSelect + + params->LCDampingSelect + + params->excitationSelect + + params->comparatorSelect + + params->highFreqClkOn_or_compAutoZeroCycle + + params->outputLatchSelect + + params->testCycleSelect + + params->dacSelect + + params->tsmStop + + params->tsmClkSrc) | + (params->duration << 11); +} + +//***************************************************************************** +// +//! Get ESI interrupt Vector Register +//! +//! \return None +// +//***************************************************************************** +uint16_t ESI_getInterruptVectorRegister(void) +{ + return (ESIIV); +} + +//***************************************************************************** +// +//! Enables ESI interrupts +//! +//! \param interruptMask is the bit mask of the interrupt sources to +//! be enabled. Mask value is the logical OR of any of the following: +//! \b ESI_INTERRUPT_AFE1_ESIOUTX +//! \b ESI_INTERRUPT_ESISTOP +//! \b ESI_INTERRUPT_ESISTART +//! \b ESI_INTERRUPT_ESICNT1 +//! \b ESI_INTERRUPT_ESICNT2 +//! \b ESI_INTERRUPT_Q6_BIT_SET +//! \b ESI_INTERRUPT_Q7_BIT_SET +//! \b ESI_INTERRUPT_ESICNT0_COUNT_INTERVAL +//! \b ESI_INTERRUPT_AFE2_ESIOUTX +//! +//! Modified bits of \b ESIINT1 register. +//! +//! \return None +// +//***************************************************************************** +void ESI_enableInterrupt(uint16_t interruptMask) +{ + ESIINT1 |= (interruptMask); +} + +//***************************************************************************** +// +//! Disables ESI interrupts +//! +//! \param interruptMask is the bit mask of the interrupt sources to +//! be disabled. Mask value is the logical OR of any of the following: +//! \b ESI_INTERRUPT_AFE1_ESIOUTX +//! \b ESI_INTERRUPT_ESISTOP +//! \b ESI_INTERRUPT_ESISTART +//! \b ESI_INTERRUPT_ESICNT1 +//! \b ESI_INTERRUPT_ESICNT2 +//! \b ESI_INTERRUPT_Q6_BIT_SET +//! \b ESI_INTERRUPT_Q7_BIT_SET +//! \b ESI_INTERRUPT_ESICNT0_COUNT_INTERVAL +//! \b ESI_INTERRUPT_AFE2_ESIOUTX +//! +//! Modified bits of \b ESIINT1 register. +//! +//! \return None +// +//***************************************************************************** +void ESI_disableInterrupt(uint16_t interruptMask) +{ + ESIINT1 &= ~(interruptMask); +} + +//***************************************************************************** +// +//! Get ESI interrupt status +//! +//! \param interruptMask is the masked interrupt flag status to be returned. +//! Mask value is the logical OR of any of the following: +//! - \b ESI_INTERRUPT_FLAG_AFE1_ESIOUTX +//! - \b ESI_INTERRUPT_FLAG_ESISTOP +//! - \b ESI_INTERRUPT_FLAG_ESISTART +//! - \b ESI_INTERRUPT_FLAG_ESICNT1 +//! - \b ESI_INTERRUPT_FLAG_ESICNT2 +//! - \b ESI_INTERRUPT_FLAG_Q6_BIT_SET +//! - \b ESI_INTERRUPT_FLAG_Q7_BIT_SET +//! - \b ESI_INTERRUPT_FLAG_ESICNT0_COUNT_INTERVAL +//! - \b ESI_INTERRUPT_FLAG_AFE2_ESIOUTX +//! +//! \return Logical OR of any of the following: +//! - \b ESI_INTERRUPT_FLAG_AFE1_ESIOUTX +//! - \b ESI_INTERRUPT_FLAG_ESISTOP +//! - \b ESI_INTERRUPT_FLAG_ESISTART +//! - \b ESI_INTERRUPT_FLAG_ESICNT1 +//! - \b ESI_INTERRUPT_FLAG_ESICNT2 +//! - \b ESI_INTERRUPT_FLAG_Q6_BIT_SET +//! - \b ESI_INTERRUPT_FLAG_Q7_BIT_SET +//! - \b ESI_INTERRUPT_FLAG_ESICNT0_COUNT_INTERVAL +//! - \b ESI_INTERRUPT_FLAG_AFE2_ESIOUTX +//! \n indicating the status of the masked flags +// +//***************************************************************************** +uint16_t ESI_getInterruptStatus(uint16_t interruptMask) +{ + return (ESIINT2 & interruptMask); +} + +//***************************************************************************** +// +//! Clear ESI interrupt flag +//! +//! \param interruptMask is the masked interrupt flag status to be returned. +//! Mask value is the logical OR of any of the following: +//! - \b ESI_INTERRUPT_FLAG_AFE1_ESIOUTX +//! - \b ESI_INTERRUPT_FLAG_ESISTOP +//! - \b ESI_INTERRUPT_FLAG_ESISTART +//! - \b ESI_INTERRUPT_FLAG_ESICNT1 +//! - \b ESI_INTERRUPT_FLAG_ESICNT2 +//! - \b ESI_INTERRUPT_FLAG_Q6_BIT_SET +//! - \b ESI_INTERRUPT_FLAG_Q7_BIT_SET +//! - \b ESI_INTERRUPT_FLAG_ESICNT0_COUNT_INTERVAL +//! - \b ESI_INTERRUPT_FLAG_AFE2_ESIOUTX +//! +//! \return None +// +//***************************************************************************** +void ESI_clearInterrupt(uint16_t interruptMask) +{ + ESIINT2 &= ~(interruptMask); +} + +//***************************************************************************** +// +//! Set source of IFG0 interrupt flag +//! +//! \param ifg0Src values are as follows +//! ESI_IFG0_SET_WHEN_ESIOUT0_SET +//! ESI_IFG0_SET_WHEN_ESIOUT0_RESET +//! ESI_IFG0_SET_WHEN_ESIOUT1_SET +//! ESI_IFG0_SET_WHEN_ESIOUT1_RESET +//! ESI_IFG0_SET_WHEN_ESIOUT2_SET +//! ESI_IFG0_SET_WHEN_ESIOUT2_RESET +//! ESI_IFG0_SET_WHEN_ESIOUT3_SET +//! ESI_IFG0_SET_WHEN_ESIOUT3_RESET +//! +//! \return None +// +//***************************************************************************** +void ESI_setIFG0Source(uint16_t ifg0Src) +{ + ESIINT1 &= ~ESI_IFG0_SET_WHEN_ESIOUT3_RESET; + ESIINT1 |= ifg0Src; +} + +//***************************************************************************** +// +//! Set source of IFG8 interrupt flag +//! +//! \param ifg8Src values are as follows +//! ESI_IFG8_SET_WHEN_ESIOUT4_SET +//! ESI_IFG8_SET_WHEN_ESIOUT4_RESET +//! ESI_IFG8_SET_WHEN_ESIOUT5_SET +//! ESI_IFG8_SET_WHEN_ESIOUT5_RESET +//! ESI_IFG8_SET_WHEN_ESIOUT6_SET +//! ESI_IFG8_SET_WHEN_ESIOUT6_RESET +//! ESI_IFG8_SET_WHEN_ESIOUT7_SET +//! ESI_IFG8_SET_WHEN_ESIOUT7_RESET +//! +//! \return None +// +//***************************************************************************** +void ESI_setIFG8Source(uint16_t ifg8Src) +{ + ESIINT1 &= ~ESI_IFG8_SET_WHEN_ESIOUT7_RESET; + ESIINT1 |= ifg8Src; +} + +//***************************************************************************** +// +//! Set source of IFG7 interrupt flag +//! +//! \param ifg7Src values are as follows +//! ESI_IFG7_SOURCE_EVERY_COUNT_OF_CNT0 +//! ESI_IFG7_SOURCE_CNT0_MOD4 +//! ESI_IFG7_SOURCE_CNT0_MOD256 +//! ESI_IFG7_SOURCE_CNT0_ROLLOVER +//! +//! \return None +// +//***************************************************************************** +void ESI_setIFG7Source(uint16_t ifg7Src) +{ + ESIINT2 &= ~ESI_IFG7_SOURCE_CNT0_ROLLOVER; + ESIINT2 |= ifg7Src; +} + +//***************************************************************************** +// +//! Set source of IFG4 interrupt flag +//! +//! \param ifg4Src values are as follows +//! ESI_IFG4_SOURCE_EVERY_COUNT_OF_CNT2 +//! ESI_IFG4_SOURCE_CNT2_MOD4 +//! ESI_IFG4_SOURCE_CNT2_MOD256 +//! ESI_IFG4_SOURCE_CNT2_ROLLOVER +//! +//! \return None +// +//***************************************************************************** +void ESI_setIFG4Source(uint16_t ifg4Src) +{ + ESIINT2 &= ~ESI_IFG4_SOURCE_CNT2_ROLLOVER; + ESIINT2 |= ifg4Src; +} + +//***************************************************************************** +// +//! Simple DAC calibration code using pre-defined TSM +//! Supports AFE1 only. +//! \param selected_channel acceptable values +//! ESI_AFE1_CHANNEL0_SELECT +//! ESI_AFE1_CHANNEL1_SELECT +//! ESI_AFE1_CHANNEL2_SELECT +//! ESI_AFE1_CHANNEL3_SELECT +//! +//! +//! \return None +// +//***************************************************************************** +void ESI_LC_DAC_calibration(uint8_t selected_channel) +{ +#define NUM_SENSOR_CAL 4 +#define MIN_HYSTERESIS 30 +#define STEP_TO_FINISH 4 + + unsigned int i; + unsigned char test_bit, done; + unsigned int hysteresis[NUM_SENSOR_CAL], + hysteresis_hi[NUM_SENSOR_CAL], + hysteresis_lo[NUM_SENSOR_CAL], + current[NUM_SENSOR_CAL], + average[NUM_SENSOR_CAL], + max[NUM_SENSOR_CAL], + min[NUM_SENSOR_CAL]; + + // State: 0 = output low + // 1 = output high + // 2 = undetermined (between 2 hysteresis level) + unsigned char previous_state[NUM_SENSOR_CAL], + current_state[NUM_SENSOR_CAL], + step[NUM_SENSOR_CAL]; + + // Reset values + for(i = 0; i < NUM_SENSOR_CAL; i++) + { + max[i] = 0; + min[i] = 0xffff; + previous_state[i] = 2; + step[i] = 0; + } + + do + { + // Find the current oscillating level, using software mode + FindDAC(selected_channel, 1); + + test_bit = 1; + done = 1; + + for(i = 0; i < NUM_SENSOR_CAL; i++) + { + // skip if the channel is not selected + if(test_bit & selected_channel) + { + current[i] = ESI_getAFE1DACValue(i * 2); + + // Record max and min value + if(current[i] > max[i]) + { + max[i] = current[i]; + } + if(current[i] < min[i]) + { + min[i] = current[i]; + } + + // Update average and hysteresis level + average[i] = (max[i] + min[i]) >> 1; + hysteresis[i] = (max[i] - min[i]) >> 3; + + if(hysteresis[i] < MIN_HYSTERESIS) + { + hysteresis[i] = MIN_HYSTERESIS; + } + + hysteresis[i] >>= 1; + hysteresis_hi[i] = average[i] + hysteresis[i]; + hysteresis_lo[i] = average[i] - hysteresis[i]; + + // Determine output state based on hysteresis_hi and hysteresis_lo + if(current[i] < hysteresis_lo[i]) + { + current_state[i] = 0; + } + else if(current[i] > hysteresis_hi[i]) + { + current_state[i] = 1; + } + else + { + current_state[i] = 2; + } + + // If there is state change, proceed to next step + switch(current_state[i]) + { + case 0: + case 1: + if(previous_state[i] != current_state[i]) + { + step[i]++; + previous_state[i] = current_state[i]; + } + break; + + default: + break; + } + + // Any selected sensor which has not finished calibration will set done to zero + if(step[i] < STEP_TO_FINISH) + { + done = 0; + } + } + test_bit <<= 1; + } + } + while(!done); + + // Record DAC Values + test_bit = 1; + done = ESI_DAC1_REG0; // Temp value for recording DAC + for(i = 0; i < NUM_SENSOR_CAL; i++) + { + if(test_bit & selected_channel) + { + ESI_setAFE1DACValue(hysteresis_hi[i], done++); + ESI_setAFE1DACValue(hysteresis_lo[i], done++); + } + test_bit <<= 1; + } +} + +//***************************************************************************** +// +//! Find the current oscillating level, using software mode +//! +//! +//! \return None +// +//***************************************************************************** + +static void FindDAC(unsigned char selected_channel, + unsigned char software_trigger) +{ + // DAC Level tester, using successive approximation approach + unsigned int DAC_BIT = 0x0800, Prev_DAC_BIT = 0x0C00; + + unsigned int i; + unsigned int test_bit, DAC_index; + + // Set initial DAC value for each selected channel + + // AFE 1 + if(selected_channel & 0x0f) + { + test_bit = 0x01; + DAC_index = ESI_DAC1_REG0; + for(i = 0; i < 4; i++) + { + if(selected_channel & test_bit) + { + ESI_setAFE1DACValue(DAC_BIT, DAC_index++); + ESI_setAFE1DACValue(DAC_BIT, DAC_index++); + } + else + { + DAC_index += 2; + } + test_bit <<= 1; + } + } + + // AFE 2 + if(selected_channel & 0xf0) + { + test_bit = 0x10; + DAC_index = ESI_DAC2_REG0; + for(i = 0; i < 4; i++) + { + if(selected_channel & test_bit) + { + ESI_setAFE2DACValue(DAC_BIT, DAC_index++); + ESI_setAFE2DACValue(DAC_BIT, DAC_index++); + } + else + { + DAC_index += 2; + } + test_bit <<= 1; + } + } + + ESI_enableInterrupt(ESI_INTERRUPT_ESISTOP); // enable ESISTOP INT + + // Find the DAC value for each selected channel + do + { + ESI_clearInterrupt (ESI_INTERRUPT_FLAG_ESISTOP); + + if(software_trigger) + { + ESI_TSM_softwareTrigger(); + } + + __bis_SR_register(LPM3_bits + GIE); // wait for the ESISTOP flag + DAC_BIT >>= 1; // right shift one bit + + // AFE 1 + if(selected_channel & 0x0f) + { + test_bit = 0x01; + DAC_index = ESI_DAC1_REG0; + for(i = 0; i < 4; i++) + { + if(selected_channel & test_bit) + { +#ifndef INVERTED + if(ESI_getLatchedComparatorOutput(test_bit) == + ESI_AFE_OUTPUT_HIGH) +#else + if(ESI_getLatchedComparatorOutput(test_bit) == + ESI_AFE_OUTPUT_LOW) +#endif + { + ESI_setAFE1DACValue(ESI_getAFE1DACValue( + DAC_index) | DAC_BIT, + DAC_index); + DAC_index++; + ESI_setAFE1DACValue(ESI_getAFE1DACValue( + DAC_index) | DAC_BIT, + DAC_index); + DAC_index++; + } + else + { + ESI_setAFE1DACValue(ESI_getAFE1DACValue( + DAC_index) ^ Prev_DAC_BIT, + DAC_index); + DAC_index++; + ESI_setAFE1DACValue(ESI_getAFE1DACValue( + DAC_index) ^ Prev_DAC_BIT, + DAC_index); + DAC_index++; + } + } + else + { + DAC_index += 2; + } + test_bit <<= 1; + } + } + + // AFE 2 + if(selected_channel & 0xf0) + { + test_bit = 0x10; + DAC_index = ESI_DAC2_REG0; + for(i = 0; i < 4; i++) + { + if(selected_channel & test_bit) + { +#ifndef INVERTED + if(ESI_getLatchedComparatorOutput(test_bit) == + ESI_AFE_OUTPUT_HIGH) +#else + if(ESI_getLatchedComparatorOutput(test_bit) == + ESI_AFE_OUTPUT_LOW) +#endif + { + ESI_setAFE1DACValue(ESI_getAFE2DACValue( + DAC_index) | DAC_BIT, + DAC_index); + DAC_index++; + ESI_setAFE1DACValue(ESI_getAFE2DACValue( + DAC_index) | DAC_BIT, + DAC_index); + DAC_index++; + } + else + { + ESI_setAFE1DACValue(ESI_getAFE2DACValue( + DAC_index) ^ Prev_DAC_BIT, + DAC_index); + DAC_index++; + ESI_setAFE1DACValue(ESI_getAFE2DACValue( + DAC_index) ^ Prev_DAC_BIT, + DAC_index); + DAC_index++; + } + } + else + { + DAC_index += 2; + } + test_bit <<= 1; + } + } + Prev_DAC_BIT >>= 1; // right shift one bit + } + while(DAC_BIT); + + ESI_disableInterrupt(ESI_INTERRUPT_ESISTOP); + __no_operation(); +} + +//***************************************************************************** +// +//! Close the doxygen group for esi_api +//! @} +// +//***************************************************************************** +#endif diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/esi.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/esi.h new file mode 100644 index 000000000..581c3a22a --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/esi.h @@ -0,0 +1,904 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// esi.h - Driver for the ESI Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_ESI_H__ +#define __MSP430WARE_ESI_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_ESI__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +uint16_t ESI_getCounter0(void); +uint16_t ESI_getCounter1(void); +uint16_t ESI_getCounter2(void); +uint16_t ESI_getOscCounter(void); + +//***************************************************************************** +// +//The following are values that can be passed to excitationCircuitSelect +//parameter in ESI_AFE_InitParams +// +//***************************************************************************** +#define ESI_EXCITATION_CIRCUIT_DISABLED 0x0 +#define ESI_EXCITATION_CIRCUIT_ENABLED ESITEN + +//***************************************************************************** +// +//The following are values that can be passed to sampleAndHoldSelect +//parameter in ESI_AFE_InitParams +// +//***************************************************************************** +#define ESI_SAMPLE_HOLD_DISABLED 0x0 +#define ESI_SAMPLE_HOLD_ENABLED ESISH + +//***************************************************************************** +// +//The following are values that can be passed to midVoltageGeneratorSelect +//parameter in ESI_AFE_InitParams +// +//***************************************************************************** +#define ESI_MID_VOLTAGE_GENERATOR_DISABLED 0x0 +#define ESI_MID_VOLTAGE_GENERATOR_ENABLED ESIVCC2 + +//***************************************************************************** +// +//The following are values that can be passed to sampleAndHoldVSSConnect +//parameter in ESI_AFE_InitParams +// +//***************************************************************************** +#define ESI_SAMPLE_HOLD_VSS_TO_ESIVSS 0x0 +#define ESI_SAMPLE_HOLD_VSS_BY_TSM ESIVSS + +//***************************************************************************** +// +//The following are values that can be passed to +//inputSelectAFE1 parameter in ESI_AFE1_InitParams +// +//***************************************************************************** +#define ESI_AFE1_INPUT_SELECT_CHx 0 +#define ESI_AFE1_INPUT_SELECT_CIx 1 +#define ESI_AFE1_INPUT_SELECT_CI3 2 +#define ESI_AFE1_INPUT_SELECT_CI 3 + +//***************************************************************************** +// +//The following are values that can be passed to +//inputSelectAFE2 parameter in ESI_AFE2_InitParams +// +//***************************************************************************** +#define ESI_AFE2_INPUT_SELECT_CHx 0 +#define ESI_AFE2_INPUT_SELECT_CIx ESICA2X + +//***************************************************************************** +// +//The following are values that can be passed to +//inverterSelectOutputAFE1 parameter in ESI_AFE1_InitParams +// +//***************************************************************************** +#define ESI_INVERTER_FOR_AFE1_DISABLE 0x0 +#define ESI_INVERTER_FOR_AFE1_ENABLE ESICA1INV + +//***************************************************************************** +// +//The following are values that can be passed to +//inverterSelectOutputAFE2 parameter in ESI_AFE2_InitParams +// +//***************************************************************************** +#define ESI_INVERTER_FOR_AFE2_DISABLE 0x0 +#define ESI_INVERTER_FOR_AFE2_ENABLE ESICA2INV + +//***************************************************************************** +// +//The following are values that can be passed to +//tsmControlOfComparatorAFE2 parameter in ESI_AFE2_InitParams +// +//***************************************************************************** +#define ESI_TSM_COMPARATOR_CONTROL_AFE2_DISABLE 0x0 +#define ESI_TSM_COMPARATOR_CONTROL_AFE2_ENABLE ESICA2EN + +//***************************************************************************** +// +//The following are values that can be passed to +//tsmControlDacAFE2 parameter in ESI_AFE2_InitParams +// +//***************************************************************************** +#define ESI_TSM_DAC_CONTROL_AFE2_DISABLE 0x0 +#define ESI_TSM_DAC_CONTROL_AFE2_ENABLE ESIDAC2EN + +typedef struct ESI_AFE1_InitParams +{ + uint16_t excitationCircuitSelect; + uint16_t sampleAndHoldSelect; + uint16_t midVoltageGeneratorSelect; + uint16_t sampleAndHoldVSSConnect; + uint16_t inputSelectAFE1; + uint16_t inverterSelectOutputAFE1; +} ESI_AFE1_InitParams; + +extern const ESI_AFE1_InitParams ESI_AFE1_INITPARAMS_DEFAULT; + +void ESI_AFE1_init(ESI_AFE1_InitParams *params); + +typedef struct ESI_AFE2_InitParams +{ + uint16_t inputSelectAFE2; + uint16_t inverterSelectOutputAFE2; + uint16_t tsmControlComparatorAFE2; + uint16_t tsmControlDacAFE2; +} ESI_AFE2_InitParams; + +extern const ESI_AFE2_InitParams ESI_AFE2_INITPARAMS_DEFAULT; + +void ESI_AFE2_init(ESI_AFE2_InitParams *params); + +//***************************************************************************** +// +//The following are values that can be passed to +//channelSelect parameter in ESI_getLatchedComparatorOutput +// +//***************************************************************************** +#define ESI_AFE1_CHANNEL0_SELECT ESIOUT0 +#define ESI_AFE1_CHANNEL1_SELECT ESIOUT1 +#define ESI_AFE1_CHANNEL2_SELECT ESIOUT2 +#define ESI_AFE1_CHANNEL3_SELECT ESIOUT3 +#define ESI_AFE2_CHANNEL0_SELECT ESIOUT4 +#define ESI_AFE2_CHANNEL1_SELECT ESIOUT5 +#define ESI_AFE2_CHANNEL2_SELECT ESIOUT6 +#define ESI_AFE2_CHANNEL3_SELECT ESIOUT7 +#define ESI_AFE1_TEST_CHANNEL0_SELECT ESITCHOUT0 +#define ESI_AFE1_TEST_CHANNEL1_SELECT ESITCHOUT1 + +//***************************************************************************** +// +//The following are values that are returned by ESI_getLatchedComparatorOutput +// +//***************************************************************************** +#define ESI_AFE_OUTPUT_HIGH 0x1 +#define ESI_AFE_OUTPUT_LOW 0x0 + +uint16_t ESI_getLatchedComparatorOutput(uint16_t channelSelect); + +//***************************************************************************** +// +//The following are values that can be passed to +//smclkDivider parameter in ESI_TSM_InitParams +// +//***************************************************************************** +#define ESI_TSM_SMCLK_DIV_1 0x0 +#define ESI_TSM_SMCLK_DIV_2 ESIDIV10 +#define ESI_TSM_SMCLK_DIV_4 ESIDIV11 +#define ESI_TSM_SMCLK_DIV_8 ESIDIV10 + ESIDIV11 + +//***************************************************************************** +// +//The following are values that can be passed to +//aclkDivider parameter in ESI_TSM_InitParams +// +//***************************************************************************** +#define ESI_TSM_ACLK_DIV_1 0x0 +#define ESI_TSM_ACLK_DIV_2 ESIDIV20 +#define ESI_TSM_ACLK_DIV_4 ESIDIV21 +#define ESI_TSM_ACLK_DIV_8 ESIDIV20 + ESIDIV21 + +//***************************************************************************** +// +//The following are values that can be passed to +//startTriggerAclkDivider parameter in ESI_TSM_InitParams +// +//***************************************************************************** +#define ESI_TSM_START_TRIGGER_DIV_2 0x0 +#define ESI_TSM_START_TRIGGER_DIV_6 ESIDIV3A0 +#define ESI_TSM_START_TRIGGER_DIV_10 ESIDIV3A1 +#define ESI_TSM_START_TRIGGER_DIV_14 ESIDIV3A0 + ESIDIV3A1 +#define ESI_TSM_START_TRIGGER_DIV_18 ESIDIV3A2 +#define ESI_TSM_START_TRIGGER_DIV_22 ESIDIV3A2 + ESIDIV3A0 +#define ESI_TSM_START_TRIGGER_DIV_26 ESIDIV3A2 + ESIDIV3A1 +#define ESI_TSM_START_TRIGGER_DIV_30 ESIDIV3A2 + ESIDIV3A1 + ESIDIV3A0 +#define ESI_TSM_START_TRIGGER_DIV_42 ESIDIV3A0 + ESIDIV3A1 + ESIDIV3B0 +#define ESI_TSM_START_TRIGGER_DIV_50 ESIDIV3A1 + ESIDIV3B1 +#define ESI_TSM_START_TRIGGER_DIV_54 ESIDIV3A2 + ESIDIV3B0 +#define ESI_TSM_START_TRIGGER_DIV_66 ESIDIV3A2 + ESIDIV3A0 + ESIDIV3B0 +#define ESI_TSM_START_TRIGGER_DIV_70 ESIDIV3A1 + ESIDIV3A0 + ESIDIV3B1 +#define ESI_TSM_START_TRIGGER_DIV_78 ESIDIV3A2 + ESIDIV3A1 + ESIDIV3B0 +#define ESI_TSM_START_TRIGGER_DIV_90 ESIDIV3A2 + ESIDIV3A1 + ESIDIV3A0 + \ + ESIDIV3B0 +#define ESI_TSM_START_TRIGGER_DIV_98 ESIDIV3A0 + ESIDIV3A1 + ESIDIV3B0 + \ + ESIDIV3B1 +#define ESI_TSM_START_TRIGGER_DIV_110 ESIDIV3A2 + ESIDIV3A0 + ESIDIV3B1 +#define ESI_TSM_START_TRIGGER_DIV_126 ESIDIV3A2 + ESIDIV3B0 + ESIDIV3B1 +#define ESI_TSM_START_TRIGGER_DIV_130 ESIDIV3A2 + ESIDIV3A1 + ESIDIV3B1 +#define ESI_TSM_START_TRIGGER_DIV_150 ESIDIV3A2 + ESIDIV3A1 + ESIDIV3A0 + \ + ESIDIV3B1 +#define ESI_TSM_START_TRIGGER_DIV_154 ESIDIV3A2 + ESIDIV3A0 + ESIDIV3B0 + \ + ESIDIV3B1 +#define ESI_TSM_START_TRIGGER_DIV_162 ESIDIV3A2 + ESIDIV3B2 +#define ESI_TSM_START_TRIGGER_DIV_182 ESIDIV3A2 + ESIDIV3A1 + ESIDIV3B0 + \ + ESIDIV3B1 +#define ESI_TSM_START_TRIGGER_DIV_198 ESIDIV3A2 + ESIDIV3A0 + ESIDIV3B2 +#define ESI_TSM_START_TRIGGER_DIV_210 ESIDIV3A2 + ESIDIV3A1 + ESIDIV3A0 + \ + ESIDIV3B0 + ESIDIV3B1 +#define ESI_TSM_START_TRIGGER_DIV_234 ESIDIV3A2 + ESIDIV3A1 + ESIDIV3B2 +#define ESI_TSM_START_TRIGGER_DIV_242 ESIDIV3A2 + ESIDIV3A0 + ESIDIV3B2 + \ + ESIDIV3B0 +#define ESI_TSM_START_TRIGGER_DIV_270 ESIDIV3A2 + ESIDIV3A1 + ESIDIV3A0 + \ + ESIDIV3B2 +#define ESI_TSM_START_TRIGGER_DIV_286 ESIDIV3A2 + ESIDIV3A1 + ESIDIV3B2 + \ + ESIDIV3B0 +#define ESI_TSM_START_TRIGGER_DIV_330 ESIDIV3A2 + ESIDIV3A1 + ESIDIV3A0 + \ + ESIDIV3B2 + ESIDIV3B0 +#define ESI_TSM_START_TRIGGER_DIV_338 ESIDIV3A2 + ESIDIV3A1 + ESIDIV3B2 + \ + ESIDIV3B1 +#define ESI_TSM_START_TRIGGER_DIV_390 ESIDIV3A2 + ESIDIV3A1 + ESIDIV3A0 + \ + ESIDIV3B2 + ESIDIV3B1 +#define ESI_TSM_START_TRIGGER_DIV_450 ESIDIV3A2 + ESIDIV3A1 + ESIDIV3A0 + \ + ESIDIV3B2 + ESIDIV3B1 + ESIDIV3B0 + +//***************************************************************************** +// +//The following are values that can be passed to +//repeatMode parameter in ESI_TSM_InitParams +// +//***************************************************************************** +#define ESI_TSM_REPEAT_NEW_TRIGGER 0x0 +#define ESI_TSM_REPEAT_END_OF_PREVIOUS_SEQ ESITSMRP + +//***************************************************************************** +// +//The following are values that can be passed to +//startTriggerSelection parameter in ESI_TSM_InitParams +// +//***************************************************************************** +#define ESI_TSM_STOP_SEQUENCE 0x0 +#define ESI_TSM_START_TRIGGER_ACLK ESITSMTRG0 +#define ESI_TSM_START_TRIGGER_SOFTWARE ESITSMTRG1 +#define ESI_TSM_START_TRIGGER_ACLK_OR_SOFTWARE ESITSMTRG1 + ESITSMTRG0 + +//***************************************************************************** +// +//The following are values that can be passed to +//tsmFunctionalitySelection parameter in ESI_TSM_InitParams +// +//***************************************************************************** +#define ESI_TSM_HIGH_FREQ_CLK_FUNCTION_ON 0x0 +#define ESI_TSM_AUTOZERO_CYCLE_FUNCTION_ON ESICLKAZSEL + +typedef struct ESI_TSM_InitParams +{ + uint16_t smclkDivider; + uint16_t aclkDivider; + uint16_t startTriggerAclkDivider; + uint16_t repeatMode; + uint16_t startTriggerSelection; + uint16_t tsmFunctionSelection; +} ESI_TSM_InitParams; + +extern const ESI_TSM_InitParams ESI_TSM_INITPARAMS_DEFAULT; + +void ESI_TSM_init(ESI_TSM_InitParams *params); + +void ESI_TSM_clearTable(void); + +void ESI_TSM_copyTable(uint16_t* tsmTable, + uint16_t size); + +void ESI_TSM_softwareTrigger(void); + +uint8_t ESI_TSM_getTSMStateDuration(uint8_t stateRegNum); + +void ESI_TSM_setTSMStateDuration(uint8_t stateRegNum, + uint8_t duration); + +//***************************************************************************** +// +//The following are values that can be passed to +//Q6Select parameter in ESI_PSM_InitParams +// +//***************************************************************************** +#define ESI_PSM_Q6_DISABLE 0x0 +#define ESI_PSM_Q6_ENABLE ESIQ6EN + +//***************************************************************************** +// +//The following are values that can be passed to +//Q7TriggerSelect parameter in ESI_PSM_InitParams +// +//***************************************************************************** +#define ESI_PSM_Q7_TRIGGER_DISABLE 0x0 +#define ESI_PSM_Q7_TRIGGER_ENABLE ESIQ7TRG + +//***************************************************************************** +// +//The following are values that can be passed to +//count0Select parameter in ESI_PSM_InitParams +// +//***************************************************************************** +#define ESI_PSM_CNT0_DISABLE 0x0 +#define ESI_PSM_CNT0_ENABLE ESICNT0EN + +//***************************************************************************** +// +//The following are values that can be passed to +//count0Reset parameter in ESI_PSM_InitParams +// +//***************************************************************************** +#define ESI_PSM_CNT0_NO_RESET 0x0 +#define ESI_PSM_CNT0_RESET ESICNT0RST + +//***************************************************************************** +// +//The following are values that can be passed to +//count1Select parameter in ESI_PSM_InitParams +// +//***************************************************************************** +#define ESI_PSM_CNT1_DISABLE 0x0 +#define ESI_PSM_CNT1_ENABLE ESICNT1EN + +//***************************************************************************** +// +//The following are values that can be passed to +//count1Reset parameter in ESI_PSM_InitParams +// +//***************************************************************************** +#define ESI_PSM_CNT1_NO_RESET 0x0 +#define ESI_PSM_CNT1_RESET ESICNT1RST + +//***************************************************************************** +// +//The following are values that can be passed to +//count2Select parameter in ESI_PSM_InitParams +// +//***************************************************************************** +#define ESI_PSM_CNT2_DISABLE 0x0 +#define ESI_PSM_CNT2_ENABLE ESICNT2EN + +//***************************************************************************** +// +//The following are values that can be passed to +//count2Reset parameter in ESI_PSM_InitParams +// +//***************************************************************************** +#define ESI_PSM_CNT2_NO_RESET 0x0 +#define ESI_PSM_CNT2_RESET ESICNT2RST + +//***************************************************************************** +// +//The following are values that can be passed to +//V2Select parameter in ESI_PSM_InitParams +// +//***************************************************************************** +#define ESI_PSM_S3_SELECT 0x0 +#define ESI_PSM_Q0_SELECT ESIV2SEL + +//***************************************************************************** +// +//The following are values that can be passed to +//TEST4Select parameter in ESI_PSM_InitParams +// +//***************************************************************************** +#define ESI_PSM_TEST4_IS_Q2 0x0 +#define ESI_PSM_TEST4_IS_Q1 ESITEST4SEL0 +#define ESI_PSM_TEST4_IS_TSM_CLK ESITEST4SEL1 +#define ESI_PSM_TEST4_IS_AFE1_COMPARATOR ESITEST4SEL0 + ESITEST4SEL1 + +typedef struct ESI_PSM_InitParams +{ + uint16_t Q6Select; + uint16_t Q7TriggerSelect; + uint16_t count0Select; + uint16_t count0Reset; + uint16_t count1Select; + uint16_t count1Reset; + uint16_t count2Select; + uint16_t count2Reset; + uint16_t V2Select; + uint16_t TEST4Select; +} ESI_PSM_InitParams; + +extern const ESI_PSM_InitParams ESI_PSM_INITPARAMS_DEFAULT; + +void ESI_PSM_init(ESI_PSM_InitParams *params); + +void ESI_PSM_clearTable(void); +void ESI_PSM_copyTable(uint8_t * psmTable, + uint8_t size); + +//***************************************************************************** +// +//The following are values that can be passed to +//counterToReset parameter in ESI_PSM_counterReset +// +//***************************************************************************** +#define ESI_PSM_CNT0_RST ESICNT0RST +#define ESI_PSM_CNT1_RST ESICNT1RST +#define ESI_PSM_CNT2_RST ESICNT2RST + +void ESI_PSM_resetCounter(uint16_t counterToReset); + +//***************************************************************************** +// +//The following are values that can be passed to +//testCycleInsertion parameter in ESI_InitParams +// +//***************************************************************************** +#define ESI_TEST_CYCLE_INSERTION_DISABLE 0x0 +#define ESI_TEST_CYCLE_INSERTION_ENABLE ESITESTD + +//***************************************************************************** +// +//The following are values that can be passed to +//timerAInputSelection parameter in ESI_InitParams +// +//***************************************************************************** +#define ESI_TIMERA_INPUT_TSM_COMPOUT 0x0 +#define ESI_TIMERA_INPUT_TSM_PPUSRC ESICS + +//***************************************************************************** +// +//The following are values that can be passed to +//testChannel0Select parameter in ESI_InitParams +// +//***************************************************************************** +#define ESI_TEST_CHANNEL0_SOURCE_IS_CH0_CI0 0x0 +#define ESI_TEST_CHANNEL0_SOURCE_IS_CH1_CI1 ESITCH00 +#define ESI_TEST_CHANNEL0_SOURCE_IS_CH2_CI2 ESITCH01 +#define ESI_TEST_CHANNEL0_SOURCE_IS_CH3_CI3 ESITCH00 + ESITCH01 + +//***************************************************************************** +// +//The following are values that can be passed to +//testChannel1Select parameter in ESI_InitParams +// +//***************************************************************************** +#define ESI_TEST_CHANNEL1_SOURCE_IS_CH0_CI0 0x0 +#define ESI_TEST_CHANNEL1_SOURCE_IS_CH1_CI1 ESITCH10 +#define ESI_TEST_CHANNEL1_SOURCE_IS_CH2_CI2 ESITCH11 +#define ESI_TEST_CHANNEL1_SOURCE_IS_CH3_CI3 ESITCH10 + ESITCH11 + +//***************************************************************************** +// +//The following are values that can be passed to +//internalOscSelect parameter in ESI_InitParams +// +//***************************************************************************** +#define ESI_INTERNAL_OSC_DISABLE 0x0 +#define ESI_INTERNAL_OSC_ENABLE ESIHFSEL + +//***************************************************************************** +// +//The following are values that can be passed to +//sourceNum parameter in ESI_psmSourceSelect +// +//***************************************************************************** +#define PSM_S1_SOURCE 1 +#define PSM_S2_SOURCE 2 +#define PSM_S3_SOURCE 3 + +//***************************************************************************** +// +//The following are values that can be passed to +//sourceSelect parameter in ESI_psmSourceSelect +// +//***************************************************************************** +#define ESI_PSM_SOURCE_IS_ESIOUT0 0 +#define ESI_PSM_SOURCE_IS_ESIOUT1 1 +#define ESI_PSM_SOURCE_IS_ESIOUT2 2 +#define ESI_PSM_SOURCE_IS_ESIOUT3 3 +#define ESI_PSM_SOURCE_IS_ESIOUT4 4 +#define ESI_PSM_SOURCE_IS_ESIOUT5 5 +#define ESI_PSM_SOURCE_IS_ESIOUT6 6 +#define ESI_PSM_SOURCE_IS_ESIOUT7 7 + +void ESI_timerAInputSelect(uint16_t select); +void ESI_psmSourceSelect(uint16_t sourceNum, + uint16_t sourceSelect); +void ESI_testChannel0SourceSelect(uint16_t sourceSelect); +void ESI_testChannel1SourceSelect(uint16_t sourceSelect); +void ESI_enable(void); +void ESI_disable(void); + +void ESI_enableInternalOscillator(); +void ESI_disableInternalOscillator(); +void ESI_startInternalOscCal(void); +void ESI_stopInternalOscCal(void); + +//***************************************************************************** +// +//The following are values that can be passed to +//oversample parameter in ESI_measureESIOSCOversample +// +//***************************************************************************** +#define ESI_ESIOSC_NO_OVERSAMPLE 0 +#define ESI_ESIOSC_OVERSAMPLE_2 2 +#define ESI_ESIOSC_OVERSAMPLE_4 4 +#define ESI_ESIOSC_OVERSAMPLE_8 8 +uint16_t ESI_measureESIOSC(uint8_t oversample); +uint8_t ESI_getESICLKFQ(void); + +//***************************************************************************** +// +//The following are values that can be passed to +//incOrDec parameter in ESI_adjustInternalOscFreq +// +//***************************************************************************** +#define ESI_INTERNAL_OSC_FREQ_DECREASE 0x0 +#define ESI_INTERNAL_OSC_FREQ_INCREASE 0x1 + +void ESI_adjustInternalOscFreq(uint16_t incOrDec); +void ESI_setNominalInternalOscFreq(void); +void ESI_calibrateInternalOscFreq(uint16_t targetAclkCounts); +void ESI_setPSMCounter1IncreaseThreshold(uint16_t threshold); + +void ESI_setPSMCounter1DecreaseThreshold(uint16_t threshold); + +//***************************************************************************** +// +//The following are values that can be passed to +//resultNum parameter in ESI_getConversionResult +// +//***************************************************************************** +#define ESI_CONVERSION_RESULT_1 ESIADMEM1 +#define ESI_CONVERSION_RESULT_2 ESIADMEM2 +#define ESI_CONVERSION_RESULT_3 ESIADMEM3 +#define ESI_CONVERSION_RESULT_4 ESIADMEM4 + +uint16_t ESI_getConversionResult(uint16_t resultNum); + +//***************************************************************************** +// +//The following are values that can be passed to +//dacRegNum parameter in ESI_setAFE1DACValue and ESI_getAFE1DACValue +// +//***************************************************************************** +#define ESI_DAC1_REG0 0 +#define ESI_DAC1_REG1 1 +#define ESI_DAC1_REG2 2 +#define ESI_DAC1_REG3 3 +#define ESI_DAC1_REG4 4 +#define ESI_DAC1_REG5 5 +#define ESI_DAC1_REG6 6 +#define ESI_DAC1_REG7 7 + +void ESI_setAFE1DACValue(uint16_t dacValue, + uint8_t dacRegNum); +uint16_t ESI_getAFE1DACValue(uint8_t dacRegNum); + +//***************************************************************************** +// +//The following are values that can be passed to +//dacRegNum parameter in ESI_setAFE2DACValue and ESI_getAFE2DACValue +// +//***************************************************************************** +#define ESI_DAC2_REG0 0 +#define ESI_DAC2_REG1 1 +#define ESI_DAC2_REG2 2 +#define ESI_DAC2_REG3 3 +#define ESI_DAC2_REG4 4 +#define ESI_DAC2_REG5 5 +#define ESI_DAC2_REG6 6 +#define ESI_DAC2_REG7 7 + +void ESI_setAFE2DACValue(uint16_t dacValue, + uint8_t dacRegNum); +uint16_t ESI_getAFE2DACValue(uint8_t dacRegNum); + +//***************************************************************************** +// +//The following are values that can be passed to +//stateRegNum parameter in ESI_setTSMstateReg +// +//***************************************************************************** +#define ESI_TSM_STATE_REG_0 0 +#define ESI_TSM_STATE_REG_1 1 +#define ESI_TSM_STATE_REG_2 2 +#define ESI_TSM_STATE_REG_3 3 +#define ESI_TSM_STATE_REG_4 4 +#define ESI_TSM_STATE_REG_5 5 +#define ESI_TSM_STATE_REG_6 6 +#define ESI_TSM_STATE_REG_7 7 +#define ESI_TSM_STATE_REG_8 8 +#define ESI_TSM_STATE_REG_9 9 +#define ESI_TSM_STATE_REG_10 10 +#define ESI_TSM_STATE_REG_11 11 +#define ESI_TSM_STATE_REG_12 12 +#define ESI_TSM_STATE_REG_13 13 +#define ESI_TSM_STATE_REG_14 14 +#define ESI_TSM_STATE_REG_15 15 +#define ESI_TSM_STATE_REG_16 16 +#define ESI_TSM_STATE_REG_17 17 +#define ESI_TSM_STATE_REG_18 18 +#define ESI_TSM_STATE_REG_19 19 +#define ESI_TSM_STATE_REG_20 20 +#define ESI_TSM_STATE_REG_21 21 +#define ESI_TSM_STATE_REG_22 22 +#define ESI_TSM_STATE_REG_23 23 +#define ESI_TSM_STATE_REG_24 24 +#define ESI_TSM_STATE_REG_25 25 +#define ESI_TSM_STATE_REG_26 26 +#define ESI_TSM_STATE_REG_27 27 +#define ESI_TSM_STATE_REG_28 28 +#define ESI_TSM_STATE_REG_29 29 +#define ESI_TSM_STATE_REG_30 30 +#define ESI_TSM_STATE_REG_31 31 + +//***************************************************************************** +// +//The following are values that can be passed to +//inputChannelSelect parameter in ESI_TSM_StateParams +// +//***************************************************************************** +#define ESI_TSM_STATE_CHANNEL_SELECT_CH0 0 +#define ESI_TSM_STATE_CHANNEL_SELECT_CH1 ESICH0 +#define ESI_TSM_STATE_CHANNEL_SELECT_CH2 ESICH1 +#define ESI_TSM_STATE_CHANNEL_SELECT_CH3 (ESICH1 | ESICH0) + +//***************************************************************************** +// +//The following are values that can be passed to +//LCDampingSelect parameter in ESI_TSM_StateParams +// +//***************************************************************************** +#define ESI_TSM_STATE_LC_DAMPING_DISABLE 0x0 +#define ESI_TSM_STATE_LC_DAMPING_ENABLE ESILCEN + +//***************************************************************************** +// +//The following are values that can be passed to +//excitationSelect parameter in ESI_TSM_StateParams +// +//***************************************************************************** +#define ESI_TSM_STATE_EXCITATION_DISABLE 0x0 +#define ESI_TSM_STATE_EXCITATION_ENABLE ESIEX + +//***************************************************************************** +// +//The following are values that can be passed to +//comparatorSelect parameter in ESI_TSM_StateParams +// +//***************************************************************************** +#define ESI_TSM_STATE_COMPARATOR_DISABLE 0x0 +#define ESI_TSM_STATE_COMPARATOR_ENABLE ESICA + +//***************************************************************************** +// +//The following are values that can be passed to +//highFreqClkOn_or_compAutoZeroCycle parameter in ESI_TSM_StateParams +// +//***************************************************************************** +#define ESI_TSM_STATE_HIGH_FREQ_CLK_ON 0x0 +#define ESI_TSM_STATE_COMP_AUTOZERO_CYCLE ESICLKON + +//***************************************************************************** +// +//The following are values that can be passed to +//outputLatchSelect parameter in ESI_TSM_StateParams +// +//***************************************************************************** +#define ESI_TSM_STATE_OUTPUT_LATCH_DISABLE 0x0 +#define ESI_TSM_STATE_OUTPUT_LATCH_ENABLE ESIRSON + +//***************************************************************************** +// +//The following are values that can be passed to +//testCycleSelect parameter in ESI_TSM_StateParams +// +//***************************************************************************** +#define ESI_TSM_STATE_TEST_CYCLE_DISABLE 0x0 +#define ESI_TSM_STATE_TEST_CYCLE_ENABLE ESITESTS1 + +//***************************************************************************** +// +//The following are values that can be passed to +//dacSelect parameter in ESI_TSM_StateParams +// +//***************************************************************************** +#define ESI_TSM_STATE_DAC_DISABLE 0x0 +#define ESI_TSM_STATE_DAC_ENABLE ESIDAC + +//***************************************************************************** +// +//The following are values that can be passed to +//tsmStop parameter in ESI_TSM_StateParams +// +//***************************************************************************** +#define ESI_TSM_STATE_CONTINUE 0x0 +#define ESI_TSM_STATE_STOP ESISTOP + +//***************************************************************************** +// +//The following are values that can be passed to +//tsmClkSrc parameter in ESI_TSM_StateParams +// +//***************************************************************************** +#define ESI_TSM_STATE_HIGH_FREQ_CLK 0x0 +#define ESI_TSM_STATE_ACLK ESICLK + +//***************************************************************************** +// +//Values between these min and max can be pased to +//duration parameter in ESI_TSM_StateParams +// +//***************************************************************************** +#define ESI_TSM_STATE_DURATION_MIN 0x00 +#define ESI_TSM_STATE_DURATION_MAX 0x1F + +typedef struct ESI_TSM_StateParams +{ + uint16_t inputChannelSelect; + uint16_t LCDampingSelect; + uint16_t excitationSelect; + uint16_t comparatorSelect; + uint16_t highFreqClkOn_or_compAutoZeroCycle; + uint16_t outputLatchSelect; + uint16_t testCycleSelect; + uint16_t dacSelect; + uint16_t tsmStop; + uint16_t tsmClkSrc; + uint16_t duration; +} ESI_TSM_StateParams; + +void ESI_setTSMstateReg(ESI_TSM_StateParams *params, + uint8_t stateRegNum); + +uint16_t ESIgetInterruptVectorRegister(void); + +//***************************************************************************** +// +//The following values can be be used to form the interrupt mask for +//ESI_enableInterrupt and ESI_disableInterrupt +// +//***************************************************************************** +#define ESI_INTERRUPT_AFE1_ESIOUTX \ + ESIIE0 +#define ESI_INTERRUPT_ESISTOP ESIIE1 +#define ESI_INTERRUPT_ESISTART ESIIE2 +#define ESI_INTERRUPT_ESICNT1 ESIIE3 +#define ESI_INTERRUPT_ESICNT2 ESIIE4 +#define ESI_INTERRUPT_Q6_BIT_SET ESIIE5 +#define ESI_INTERRUPT_Q7_BIT_SET ESIIE6 +#define ESI_INTERRUPT_ESICNT0_COUNT_INTERVAL ESIIE7 +#define ESI_INTERRUPT_AFE2_ESIOUTX \ + ESIIE8 + +void ESI_enableInterrupt(uint16_t interruptMask); +void ESI_disableInterrupt(uint16_t interruptMask); + +//***************************************************************************** +// +//Return values for ESI_getInterruptStatus +// +//***************************************************************************** +#define ESI_INTERRUPT_FLAG_AFE1_ESIOUTX ESIIFG0 +#define ESI_INTERRUPT_FLAG_ESISTOP ESIIFG1 +#define ESI_INTERRUPT_FLAG_ESISTART ESIIFG2 +#define ESI_INTERRUPT_FLAG_ESICNT1 ESIIFG3 +#define ESI_INTERRUPT_FLAG_ESICNT2 ESIIFG4 +#define ESI_INTERRUPT_FLAG_Q6_BIT_SET ESIIFG5 +#define ESI_INTERRUPT_FLAG_Q7_BIT_SET ESIIFG6 +#define ESI_INTERRUPT_FLAG_ESICNT0_COUNT_INTERVAL ESIIFG7 +#define ESI_INTERRUPT_FLAG_AFE2_ESIOUTX ESIIFG8 + +uint16_t ESI_getInterruptStatus(uint16_t interruptMask); +void ESI_clearInterrupt(uint16_t interruptMask); + +//***************************************************************************** +// +//Values for ifg0Src in ESI_setIFG0Source +// +//***************************************************************************** +#define ESI_IFG0_SET_WHEN_ESIOUT0_SET ESIIFGSET1_0 +#define ESI_IFG0_SET_WHEN_ESIOUT0_RESET ESIIFGSET1_1 +#define ESI_IFG0_SET_WHEN_ESIOUT1_SET ESIIFGSET1_2 +#define ESI_IFG0_SET_WHEN_ESIOUT1_RESET ESIIFGSET1_3 +#define ESI_IFG0_SET_WHEN_ESIOUT2_SET ESIIFGSET1_4 +#define ESI_IFG0_SET_WHEN_ESIOUT2_RESET ESIIFGSET1_5 +#define ESI_IFG0_SET_WHEN_ESIOUT3_SET ESIIFGSET1_6 +#define ESI_IFG0_SET_WHEN_ESIOUT3_RESET ESIIFGSET1_7 + +void ESI_setIFG0Source(uint16_t ifg0Src); + +//***************************************************************************** +// +//Values for ifg8Src in ESI_setIFG8Source +// +//***************************************************************************** +#define ESI_IFG8_SET_WHEN_ESIOUT4_SET ESIIFGSET2_0 +#define ESI_IFG8_SET_WHEN_ESIOUT4_RESET ESIIFGSET2_1 +#define ESI_IFG8_SET_WHEN_ESIOUT5_SET ESIIFGSET2_2 +#define ESI_IFG8_SET_WHEN_ESIOUT5_RESET ESIIFGSET2_3 +#define ESI_IFG8_SET_WHEN_ESIOUT6_SET ESIIFGSET2_4 +#define ESI_IFG8_SET_WHEN_ESIOUT6_RESET ESIIFGSET2_5 +#define ESI_IFG8_SET_WHEN_ESIOUT7_SET ESIIFGSET2_6 +#define ESI_IFG8_SET_WHEN_ESIOUT7_RESET ESIIFGSET2_7 + +void ESI_setIFG8Source(uint16_t ifg8Src); + +//***************************************************************************** +// +//Values for ifg7Src in ESI_setIFG7Source +// +//***************************************************************************** +#define ESI_IFG7_SOURCE_EVERY_COUNT_OF_CNT0 ESIIS0_0 +#define ESI_IFG7_SOURCE_CNT0_MOD4 ESIIS0_1 +#define ESI_IFG7_SOURCE_CNT0_MOD256 ESIIS0_2 +#define ESI_IFG7_SOURCE_CNT0_ROLLOVER ESIIS0_3 + +void ESI_setIFG7Source(uint16_t ifg7Src); + +//***************************************************************************** +// +//Values for ifg4Src in ESI_setIFG4Source +// +//***************************************************************************** +#define ESI_IFG4_SOURCE_EVERY_COUNT_OF_CNT2 ESIIS2_0 +#define ESI_IFG4_SOURCE_CNT2_MOD4 ESIIS2_1 +#define ESI_IFG4_SOURCE_CNT2_MOD256 ESIIS2_2 +#define ESI_IFG4_SOURCE_CNT2_ROLLOVER ESIIS2_3 + +void ESI_setIFG4Source(uint16_t ifg4Src); + +void ESI_setPSMCounter1UpperThreshold(uint16_t threshold); +void ESI_setPSMCounter1LowerThreshold(uint16_t threshold); + +//***************************************************************************** +// +// Set correct DAC values for LC sensors +// +//***************************************************************************** +void ESI_LC_DAC_calibration(uint8_t selected_channel); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/eusci_a_spi.c b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/eusci_a_spi.c new file mode 100644 index 000000000..679afba5f --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/eusci_a_spi.c @@ -0,0 +1,222 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// eusci_a_spi.c - Driver for the eusci_a_spi Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup eusci_a_spi_api eusci_a_spi +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_EUSCI_Ax__ +#include "eusci_a_spi.h" + +#include + +void EUSCI_A_SPI_initMaster(uint16_t baseAddress, + EUSCI_A_SPI_initMasterParam *param) +{ + //Disable the USCI Module + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST; + + //Reset OFS_UCAxCTLW0 values + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCCKPH + UCCKPL + UC7BIT + UCMSB + + UCMST + UCMODE_3 + UCSYNC); + + //Reset OFS_UCAxCTLW0 values + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCSSEL_3); + + //Select Clock + HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->selectClockSource; + + HWREG16(baseAddress + OFS_UCAxBRW) = + (uint16_t)(param->clockSourceFrequency / param->desiredSpiClock); + + /* + * Configure as SPI master mode. + * Clock phase select, polarity, msb + * UCMST = Master mode + * UCSYNC = Synchronous mode + * UCMODE_0 = 3-pin SPI + */ + HWREG16(baseAddress + OFS_UCAxCTLW0) |= ( + param->msbFirst + + param->clockPhase + + param->clockPolarity + + UCMST + + UCSYNC + + param->spiMode + ); + //No modulation + HWREG16(baseAddress + OFS_UCAxMCTLW) = 0; +} + +void EUSCI_A_SPI_select4PinFunctionality(uint16_t baseAddress, + uint8_t select4PinFunctionality) +{ + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCSTEM; + HWREG16(baseAddress + OFS_UCAxCTLW0) |= select4PinFunctionality; +} + +void EUSCI_A_SPI_changeMasterClock(uint16_t baseAddress, + EUSCI_A_SPI_changeMasterClockParam *param) +{ + //Disable the USCI Module + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST; + + HWREG16(baseAddress + OFS_UCAxBRW) = + (uint16_t)(param->clockSourceFrequency / param->desiredSpiClock); + + //Reset the UCSWRST bit to enable the USCI Module + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCSWRST); +} + +void EUSCI_A_SPI_initSlave(uint16_t baseAddress, + EUSCI_A_SPI_initSlaveParam *param) +{ + //Disable USCI Module + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST; + + //Reset OFS_UCAxCTLW0 register + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCMSB + + UC7BIT + + UCMST + + UCCKPL + + UCCKPH + + UCMODE_3 + ); + + //Clock polarity, phase select, msbFirst, SYNC, Mode0 + HWREG16(baseAddress + OFS_UCAxCTLW0) |= (param->clockPhase + + param->clockPolarity + + param->msbFirst + + UCSYNC + + param->spiMode + ); +} + +void EUSCI_A_SPI_changeClockPhasePolarity(uint16_t baseAddress, + uint16_t clockPhase, + uint16_t clockPolarity) +{ + //Disable the USCI Module + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST; + + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCCKPH + UCCKPL); + + HWREG16(baseAddress + OFS_UCAxCTLW0) |= ( + clockPhase + + clockPolarity + ); + + //Reset the UCSWRST bit to enable the USCI Module + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCSWRST); +} + +void EUSCI_A_SPI_transmitData(uint16_t baseAddress, + uint8_t transmitData) +{ + HWREG16(baseAddress + OFS_UCAxTXBUF) = transmitData; +} + +uint8_t EUSCI_A_SPI_receiveData(uint16_t baseAddress) +{ + return (HWREG16(baseAddress + OFS_UCAxRXBUF)); +} + +void EUSCI_A_SPI_enableInterrupt(uint16_t baseAddress, + uint8_t mask) +{ + HWREG16(baseAddress + OFS_UCAxIE) |= mask; +} + +void EUSCI_A_SPI_disableInterrupt(uint16_t baseAddress, + uint8_t mask) +{ + HWREG16(baseAddress + OFS_UCAxIE) &= ~mask; +} + +uint8_t EUSCI_A_SPI_getInterruptStatus(uint16_t baseAddress, + uint8_t mask) +{ + return (HWREG16(baseAddress + OFS_UCAxIFG) & mask); +} + +void EUSCI_A_SPI_clearInterrupt(uint16_t baseAddress, + uint8_t mask) +{ + HWREG16(baseAddress + OFS_UCAxIFG) &= ~mask; +} + +void EUSCI_A_SPI_enable(uint16_t baseAddress) +{ + //Reset the UCSWRST bit to enable the USCI Module + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCSWRST); +} + +void EUSCI_A_SPI_disable(uint16_t baseAddress) +{ + //Set the UCSWRST bit to disable the USCI Module + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST; +} + +uint32_t EUSCI_A_SPI_getReceiveBufferAddress(uint16_t baseAddress) +{ + return (baseAddress + OFS_UCAxRXBUF); +} + +uint32_t EUSCI_A_SPI_getTransmitBufferAddress(uint16_t baseAddress) +{ + return (baseAddress + OFS_UCAxTXBUF); +} + +uint16_t EUSCI_A_SPI_isBusy(uint16_t baseAddress) +{ + //Return the bus busy status. + return (HWREG16(baseAddress + OFS_UCAxSTATW) & UCBUSY); +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for eusci_a_spi_api +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/eusci_a_spi.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/eusci_a_spi.h new file mode 100644 index 000000000..6225d4d3c --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/eusci_a_spi.h @@ -0,0 +1,527 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// eusci_a_spi.h - Driver for the EUSCI_A_SPI Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_EUSCI_A_SPI_H__ +#define __MSP430WARE_EUSCI_A_SPI_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_EUSCI_Ax__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "inc/hw_regaccess.h" +//***************************************************************************** +// +//! \brief Used in the EUSCI_A_SPI_changeMasterClock() function as the param +//! parameter. +// +//***************************************************************************** +typedef struct EUSCI_A_SPI_changeMasterClockParam +{ + //! Is the frequency of the selected clock source + uint32_t clockSourceFrequency; + //! Is the desired clock rate for SPI communication + uint32_t desiredSpiClock; +} EUSCI_A_SPI_changeMasterClockParam; + +//***************************************************************************** +// +//! \brief Used in the EUSCI_A_SPI_initSlave() function as the param parameter. +// +//***************************************************************************** +typedef struct EUSCI_A_SPI_initSlaveParam +{ + //! Controls the direction of the receive and transmit shift register. + //! \n Valid values are: + //! - \b EUSCI_A_SPI_MSB_FIRST + //! - \b EUSCI_A_SPI_LSB_FIRST [Default] + uint16_t msbFirst; + //! Is clock phase select. + //! \n Valid values are: + //! - \b EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT [Default] + //! - \b EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT + uint16_t clockPhase; + //! Is clock polarity select + //! \n Valid values are: + //! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH + //! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default] + uint16_t clockPolarity; + //! Is SPI mode select + //! \n Valid values are: + //! - \b EUSCI_A_SPI_3PIN + //! - \b EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH + //! - \b EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW + uint16_t spiMode; +} EUSCI_A_SPI_initSlaveParam; + +//***************************************************************************** +// +//! \brief Used in the EUSCI_A_SPI_initMaster() function as the param +//! parameter. +// +//***************************************************************************** +typedef struct EUSCI_A_SPI_initMasterParam +{ + //! Selects Clock source. + //! \n Valid values are: + //! - \b EUSCI_A_SPI_CLOCKSOURCE_ACLK + //! - \b EUSCI_A_SPI_CLOCKSOURCE_SMCLK + uint8_t selectClockSource; + //! Is the frequency of the selected clock source + uint32_t clockSourceFrequency; + //! Is the desired clock rate for SPI communication + uint32_t desiredSpiClock; + //! Controls the direction of the receive and transmit shift register. + //! \n Valid values are: + //! - \b EUSCI_A_SPI_MSB_FIRST + //! - \b EUSCI_A_SPI_LSB_FIRST [Default] + uint16_t msbFirst; + //! Is clock phase select. + //! \n Valid values are: + //! - \b EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT [Default] + //! - \b EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT + uint16_t clockPhase; + //! Is clock polarity select + //! \n Valid values are: + //! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH + //! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default] + uint16_t clockPolarity; + //! Is SPI mode select + //! \n Valid values are: + //! - \b EUSCI_A_SPI_3PIN + //! - \b EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH + //! - \b EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW + uint16_t spiMode; +} EUSCI_A_SPI_initMasterParam; + +//***************************************************************************** +// +// The following are values that can be passed to the clockPhase parameter for +// functions: EUSCI_A_SPI_changeClockPhasePolarity(); the param parameter for +// functions: EUSCI_A_SPI_initMaster(), and EUSCI_A_SPI_initSlave(). +// +//***************************************************************************** +#define EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT 0x00 +#define EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT UCCKPH + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: EUSCI_A_SPI_initMaster(), and EUSCI_A_SPI_initSlave(). +// +//***************************************************************************** +#define EUSCI_A_SPI_MSB_FIRST UCMSB +#define EUSCI_A_SPI_LSB_FIRST 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: EUSCI_A_SPI_initMaster(), and EUSCI_A_SPI_initSlave(); the +// clockPolarity parameter for functions: +// EUSCI_A_SPI_changeClockPhasePolarity(). +// +//***************************************************************************** +#define EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH UCCKPL +#define EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: EUSCI_A_SPI_initMaster(). +// +//***************************************************************************** +#define EUSCI_A_SPI_CLOCKSOURCE_ACLK UCSSEL__ACLK +#define EUSCI_A_SPI_CLOCKSOURCE_SMCLK UCSSEL__SMCLK + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: EUSCI_A_SPI_initMaster(), and EUSCI_A_SPI_initSlave(). +// +//***************************************************************************** +#define EUSCI_A_SPI_3PIN UCMODE_0 +#define EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH UCMODE_1 +#define EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW UCMODE_2 + +//***************************************************************************** +// +// The following are values that can be passed to the select4PinFunctionality +// parameter for functions: EUSCI_A_SPI_select4PinFunctionality(). +// +//***************************************************************************** +#define EUSCI_A_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS 0x00 +#define EUSCI_A_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE UCSTEM + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: EUSCI_A_SPI_enableInterrupt(), EUSCI_A_SPI_disableInterrupt(), +// EUSCI_A_SPI_getInterruptStatus(), and EUSCI_A_SPI_clearInterrupt() as well +// as returned by the EUSCI_A_SPI_getInterruptStatus() function. +// +//***************************************************************************** +#define EUSCI_A_SPI_TRANSMIT_INTERRUPT UCTXIE +#define EUSCI_A_SPI_RECEIVE_INTERRUPT UCRXIE + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the EUSCI_A_SPI_isBusy() function. +// +//***************************************************************************** +#define EUSCI_A_SPI_BUSY UCBUSY +#define EUSCI_A_SPI_NOT_BUSY 0x00 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Initializes the SPI Master block. +//! +//! Upon successful initialization of the SPI master block, this function will +//! have set the bus speed for the master, but the SPI Master block still +//! remains disabled and must be enabled with EUSCI_A_SPI_enable() +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI Master module. +//! \param param is the pointer to struct for master initialization. +//! +//! Modified bits are \b UCCKPH, \b UCCKPL, \b UC7BIT, \b UCMSB, \b UCSSELx and +//! \b UCSWRST of \b UCAxCTLW0 register. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +extern void EUSCI_A_SPI_initMaster(uint16_t baseAddress, + EUSCI_A_SPI_initMasterParam *param); + +//***************************************************************************** +// +//! \brief Selects 4Pin Functionality +//! +//! This function should be invoked only in 4-wire mode. Invoking this function +//! has no effect in 3-wire mode. +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI module. +//! \param select4PinFunctionality selects 4 pin functionality +//! Valid values are: +//! - \b EUSCI_A_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS +//! - \b EUSCI_A_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE +//! +//! Modified bits are \b UCSTEM of \b UCAxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_A_SPI_select4PinFunctionality(uint16_t baseAddress, + uint8_t select4PinFunctionality); + +//***************************************************************************** +// +//! \brief Initializes the SPI Master clock. At the end of this function call, +//! SPI module is left enabled. +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI module. +//! \param param is the pointer to struct for master clock setting. +//! +//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_A_SPI_changeMasterClock(uint16_t baseAddress, + EUSCI_A_SPI_changeMasterClockParam *param); + +//***************************************************************************** +// +//! \brief Initializes the SPI Slave block. +//! +//! Upon successful initialization of the SPI slave block, this function will +//! have initialized the slave block, but the SPI Slave block still remains +//! disabled and must be enabled with EUSCI_A_SPI_enable() +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI Slave module. +//! \param param is the pointer to struct for slave initialization. +//! +//! Modified bits are \b UCMSB, \b UCMST, \b UC7BIT, \b UCCKPL, \b UCCKPH, \b +//! UCMODE and \b UCSWRST of \b UCAxCTLW0 register. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +extern void EUSCI_A_SPI_initSlave(uint16_t baseAddress, + EUSCI_A_SPI_initSlaveParam *param); + +//***************************************************************************** +// +//! \brief Changes the SPI clock phase and polarity. At the end of this +//! function call, SPI module is left enabled. +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI module. +//! \param clockPhase is clock phase select. +//! Valid values are: +//! - \b EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT +//! [Default] +//! - \b EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT +//! \param clockPolarity is clock polarity select +//! Valid values are: +//! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH +//! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default] +//! +//! Modified bits are \b UCCKPL, \b UCCKPH and \b UCSWRST of \b UCAxCTLW0 +//! register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_A_SPI_changeClockPhasePolarity(uint16_t baseAddress, + uint16_t clockPhase, + uint16_t clockPolarity); + +//***************************************************************************** +// +//! \brief Transmits a byte from the SPI Module. +//! +//! This function will place the supplied data into SPI transmit data register +//! to start transmission. +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI module. +//! \param transmitData data to be transmitted from the SPI module +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_A_SPI_transmitData(uint16_t baseAddress, + uint8_t transmitData); + +//***************************************************************************** +// +//! \brief Receives a byte that has been sent to the SPI Module. +//! +//! This function reads a byte of data from the SPI receive data Register. +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI module. +//! +//! \return Returns the byte received from by the SPI module, cast as an +//! uint8_t. +// +//***************************************************************************** +extern uint8_t EUSCI_A_SPI_receiveData(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Enables individual SPI interrupt sources. +//! +//! Enables the indicated SPI interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. Does not clear interrupt flags. +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI module. +//! \param mask is the bit mask of the interrupt sources to be enabled. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT +//! - \b EUSCI_A_SPI_RECEIVE_INTERRUPT +//! +//! Modified bits of \b UCAxIFG register and bits of \b UCAxIE register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_A_SPI_enableInterrupt(uint16_t baseAddress, + uint8_t mask); + +//***************************************************************************** +// +//! \brief Disables individual SPI interrupt sources. +//! +//! Disables the indicated SPI interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI module. +//! \param mask is the bit mask of the interrupt sources to be disabled. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT +//! - \b EUSCI_A_SPI_RECEIVE_INTERRUPT +//! +//! Modified bits of \b UCAxIE register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_A_SPI_disableInterrupt(uint16_t baseAddress, + uint8_t mask); + +//***************************************************************************** +// +//! \brief Gets the current SPI interrupt status. +//! +//! This returns the interrupt status for the SPI module based on which flag is +//! passed. +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI module. +//! \param mask is the masked interrupt flag status to be returned. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT +//! - \b EUSCI_A_SPI_RECEIVE_INTERRUPT +//! +//! \return Logical OR of any of the following: +//! - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT +//! - \b EUSCI_A_SPI_RECEIVE_INTERRUPT +//! \n indicating the status of the masked interrupts +// +//***************************************************************************** +extern uint8_t EUSCI_A_SPI_getInterruptStatus(uint16_t baseAddress, + uint8_t mask); + +//***************************************************************************** +// +//! \brief Clears the selected SPI interrupt status flag. +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI module. +//! \param mask is the masked interrupt flag to be cleared. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT +//! - \b EUSCI_A_SPI_RECEIVE_INTERRUPT +//! +//! Modified bits of \b UCAxIFG register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_A_SPI_clearInterrupt(uint16_t baseAddress, + uint8_t mask); + +//***************************************************************************** +// +//! \brief Enables the SPI block. +//! +//! This will enable operation of the SPI block. +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI module. +//! +//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_A_SPI_enable(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Disables the SPI block. +//! +//! This will disable operation of the SPI block. +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI module. +//! +//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_A_SPI_disable(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Returns the address of the RX Buffer of the SPI for the DMA module. +//! +//! Returns the address of the SPI RX Buffer. This can be used in conjunction +//! with the DMA to store the received data directly to memory. +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI module. +//! +//! \return the address of the RX Buffer +// +//***************************************************************************** +extern uint32_t EUSCI_A_SPI_getReceiveBufferAddress(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Returns the address of the TX Buffer of the SPI for the DMA module. +//! +//! Returns the address of the SPI TX Buffer. This can be used in conjunction +//! with the DMA to obtain transmitted data directly from memory. +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI module. +//! +//! \return the address of the TX Buffer +// +//***************************************************************************** +extern uint32_t EUSCI_A_SPI_getTransmitBufferAddress(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Indicates whether or not the SPI bus is busy. +//! +//! This function returns an indication of whether or not the SPI bus is +//! busy.This function checks the status of the bus via UCBBUSY bit +//! +//! \param baseAddress is the base address of the EUSCI_A_SPI module. +//! +//! \return One of the following: +//! - \b EUSCI_A_SPI_BUSY +//! - \b EUSCI_A_SPI_NOT_BUSY +//! \n indicating if the EUSCI_A_SPI is busy +// +//***************************************************************************** +extern uint16_t EUSCI_A_SPI_isBusy(uint16_t baseAddress); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_EUSCI_A_SPI_H__ diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/eusci_a_uart.c b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/eusci_a_uart.c new file mode 100644 index 000000000..5bfdbf10c --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/eusci_a_uart.c @@ -0,0 +1,283 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// eusci_a_uart.c - Driver for the eusci_a_uart Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup eusci_a_uart_api eusci_a_uart +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_EUSCI_Ax__ +#include "eusci_a_uart.h" + +#include + +bool EUSCI_A_UART_init(uint16_t baseAddress, + EUSCI_A_UART_initParam *param) +{ + bool retVal = STATUS_SUCCESS; + + //Disable the USCI Module + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST; + + //Clock source select + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCSSEL_3; + HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->selectClockSource; + + //MSB, LSB select + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCMSB; + HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->msborLsbFirst; + + //UCSPB = 0(1 stop bit) OR 1(2 stop bits) + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCSPB; + HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->numberofStopBits; + + //Parity + switch(param->parity) + { + case EUSCI_A_UART_NO_PARITY: + //No Parity + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCPEN; + break; + case EUSCI_A_UART_ODD_PARITY: + //Odd Parity + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCPEN; + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCPAR; + break; + case EUSCI_A_UART_EVEN_PARITY: + //Even Parity + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCPEN; + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCPAR; + break; + } + + //BaudRate Control Register + HWREG16(baseAddress + OFS_UCAxBRW) = param->clockPrescalar; + //Modulation Control Register + HWREG16(baseAddress + OFS_UCAxMCTLW) = ((param->secondModReg << 8) + + (param->firstModReg << + 4) + param->overSampling); + + //Asynchronous mode & 8 bit character select & clear mode + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCSYNC + + UC7BIT + + UCMODE_3 + ); + + //Configure UART mode. + HWREG16(baseAddress + OFS_UCAxCTLW0) |= param->uartMode; + + //Reset UCRXIE, UCBRKIE, UCDORM, UCTXADDR, UCTXBRK + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCRXEIE + UCBRKIE + UCDORM + + UCTXADDR + UCTXBRK + ); + return (retVal); +} + +void EUSCI_A_UART_transmitData(uint16_t baseAddress, + uint8_t transmitData) +{ + //If interrupts are not used, poll for flags + if(!(HWREG16(baseAddress + OFS_UCAxIE) & UCTXIE)) + { + //Poll for transmit interrupt flag + while(!(HWREG16(baseAddress + OFS_UCAxIFG) & UCTXIFG)) + { + ; + } + } + + HWREG16(baseAddress + OFS_UCAxTXBUF) = transmitData; +} + +uint8_t EUSCI_A_UART_receiveData(uint16_t baseAddress) +{ + //If interrupts are not used, poll for flags + if(!(HWREG16(baseAddress + OFS_UCAxIE) & UCRXIE)) + { + //Poll for receive interrupt flag + while(!(HWREG16(baseAddress + OFS_UCAxIFG) & UCRXIFG)) + { + ; + } + } + + return (HWREG16(baseAddress + OFS_UCAxRXBUF)); +} + +void EUSCI_A_UART_enableInterrupt(uint16_t baseAddress, + uint8_t mask) +{ + uint8_t locMask; + + locMask = (mask & (EUSCI_A_UART_RECEIVE_INTERRUPT + | EUSCI_A_UART_TRANSMIT_INTERRUPT + | EUSCI_A_UART_STARTBIT_INTERRUPT + | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT)); + + HWREG16(baseAddress + OFS_UCAxIE) |= locMask; + + locMask = (mask & (EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT + | EUSCI_A_UART_BREAKCHAR_INTERRUPT)); + HWREG16(baseAddress + OFS_UCAxCTLW0) |= locMask; +} + +void EUSCI_A_UART_disableInterrupt(uint16_t baseAddress, + uint8_t mask) +{ + uint8_t locMask; + + locMask = (mask & (EUSCI_A_UART_RECEIVE_INTERRUPT + | EUSCI_A_UART_TRANSMIT_INTERRUPT + | EUSCI_A_UART_STARTBIT_INTERRUPT + | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT)); + HWREG16(baseAddress + OFS_UCAxIE) &= ~locMask; + + locMask = (mask & (EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT + | EUSCI_A_UART_BREAKCHAR_INTERRUPT)); + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~locMask; +} + +uint8_t EUSCI_A_UART_getInterruptStatus(uint16_t baseAddress, + uint8_t mask) +{ + return (HWREG16(baseAddress + OFS_UCAxIFG) & mask); +} + +void EUSCI_A_UART_clearInterrupt(uint16_t baseAddress, + uint8_t mask) +{ + //Clear the UART interrupt source. + HWREG16(baseAddress + OFS_UCAxIFG) &= ~(mask); +} + +void EUSCI_A_UART_enable(uint16_t baseAddress) +{ + //Reset the UCSWRST bit to enable the USCI Module + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~(UCSWRST); +} + +void EUSCI_A_UART_disable(uint16_t baseAddress) +{ + //Set the UCSWRST bit to disable the USCI Module + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCSWRST; +} + +uint8_t EUSCI_A_UART_queryStatusFlags(uint16_t baseAddress, + uint8_t mask) +{ + return (HWREG16(baseAddress + OFS_UCAxSTATW) & mask); +} + +void EUSCI_A_UART_setDormant(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCDORM; +} + +void EUSCI_A_UART_resetDormant(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_UCAxCTLW0) &= ~UCDORM; +} + +void EUSCI_A_UART_transmitAddress(uint16_t baseAddress, + uint8_t transmitAddress) +{ + //Set UCTXADDR bit + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCTXADDR; + + //Place next byte to be sent into the transmit buffer + HWREG16(baseAddress + OFS_UCAxTXBUF) = transmitAddress; +} + +void EUSCI_A_UART_transmitBreak(uint16_t baseAddress) +{ + //Set UCTXADDR bit + HWREG16(baseAddress + OFS_UCAxCTLW0) |= UCTXBRK; + + //If current mode is automatic baud-rate detection + if(EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE == + (HWREG16(baseAddress + OFS_UCAxCTLW0) & + EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE)) + { + HWREG16(baseAddress + + OFS_UCAxTXBUF) = EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC; + } + else + { + HWREG16(baseAddress + OFS_UCAxTXBUF) = DEFAULT_SYNC; + } + + //If interrupts are not used, poll for flags + if(!(HWREG16(baseAddress + OFS_UCAxIE) & UCTXIE)) + { + //Poll for transmit interrupt flag + while(!(HWREG16(baseAddress + OFS_UCAxIFG) & UCTXIFG)) + { + ; + } + } +} + +uint32_t EUSCI_A_UART_getReceiveBufferAddress(uint16_t baseAddress) +{ + return (baseAddress + OFS_UCAxRXBUF); +} + +uint32_t EUSCI_A_UART_getTransmitBufferAddress(uint16_t baseAddress) +{ + return (baseAddress + OFS_UCAxTXBUF); +} + +void EUSCI_A_UART_selectDeglitchTime(uint16_t baseAddress, + uint16_t deglitchTime) +{ + HWREG16(baseAddress + OFS_UCAxCTLW1) &= ~(UCGLIT1 + UCGLIT0); + + HWREG16(baseAddress + OFS_UCAxCTLW1) |= deglitchTime; +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for eusci_a_uart_api +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/eusci_a_uart.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/eusci_a_uart.h new file mode 100644 index 000000000..e5c797048 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/eusci_a_uart.h @@ -0,0 +1,601 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// eusci_a_uart.h - Driver for the EUSCI_A_UART Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_EUSCI_A_UART_H__ +#define __MSP430WARE_EUSCI_A_UART_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_EUSCI_Ax__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "inc/hw_regaccess.h" +//***************************************************************************** +// +// The following values are the sync characters possible. +// +//***************************************************************************** +#define DEFAULT_SYNC 0x00 +#define EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC 0x55 + +//***************************************************************************** +// +//! \brief Used in the EUSCI_A_UART_init() function as the param parameter. +// +//***************************************************************************** +typedef struct EUSCI_A_UART_initParam +{ + //! Selects Clock source. + //! \n Valid values are: + //! - \b EUSCI_A_UART_CLOCKSOURCE_SMCLK + //! - \b EUSCI_A_UART_CLOCKSOURCE_ACLK + uint8_t selectClockSource; + //! Is the value to be written into UCBRx bits + uint16_t clockPrescalar; + //! Is First modulation stage register setting. This value is a pre- + //! calculated value which can be obtained from the Device Users Guide. + //! This value is written into UCBRFx bits of UCAxMCTLW. + uint8_t firstModReg; + //! Is Second modulation stage register setting. This value is a pre- + //! calculated value which can be obtained from the Device Users Guide. + //! This value is written into UCBRSx bits of UCAxMCTLW. + uint8_t secondModReg; + //! Is the desired parity. + //! \n Valid values are: + //! - \b EUSCI_A_UART_NO_PARITY [Default] + //! - \b EUSCI_A_UART_ODD_PARITY + //! - \b EUSCI_A_UART_EVEN_PARITY + uint8_t parity; + //! Controls direction of receive and transmit shift register. + //! \n Valid values are: + //! - \b EUSCI_A_UART_MSB_FIRST + //! - \b EUSCI_A_UART_LSB_FIRST [Default] + uint16_t msborLsbFirst; + //! Indicates one/two STOP bits + //! \n Valid values are: + //! - \b EUSCI_A_UART_ONE_STOP_BIT [Default] + //! - \b EUSCI_A_UART_TWO_STOP_BITS + uint16_t numberofStopBits; + //! Selects the mode of operation + //! \n Valid values are: + //! - \b EUSCI_A_UART_MODE [Default] + //! - \b EUSCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE + //! - \b EUSCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE + //! - \b EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE + uint16_t uartMode; + //! Indicates low frequency or oversampling baud generation + //! \n Valid values are: + //! - \b EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION + //! - \b EUSCI_A_UART_LOW_FREQUENCY_BAUDRATE_GENERATION + uint8_t overSampling; +} EUSCI_A_UART_initParam; + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: EUSCI_A_UART_init(). +// +//***************************************************************************** +#define EUSCI_A_UART_NO_PARITY 0x00 +#define EUSCI_A_UART_ODD_PARITY 0x01 +#define EUSCI_A_UART_EVEN_PARITY 0x02 + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: EUSCI_A_UART_init(). +// +//***************************************************************************** +#define EUSCI_A_UART_MSB_FIRST UCMSB +#define EUSCI_A_UART_LSB_FIRST 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: EUSCI_A_UART_init(). +// +//***************************************************************************** +#define EUSCI_A_UART_MODE UCMODE_0 +#define EUSCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE UCMODE_1 +#define EUSCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE UCMODE_2 +#define EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE UCMODE_3 + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: EUSCI_A_UART_init(). +// +//***************************************************************************** +#define EUSCI_A_UART_CLOCKSOURCE_SMCLK UCSSEL__SMCLK +#define EUSCI_A_UART_CLOCKSOURCE_ACLK UCSSEL__ACLK + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: EUSCI_A_UART_init(). +// +//***************************************************************************** +#define EUSCI_A_UART_ONE_STOP_BIT 0x00 +#define EUSCI_A_UART_TWO_STOP_BITS UCSPB + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: EUSCI_A_UART_init(). +// +//***************************************************************************** +#define EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION 0x01 +#define EUSCI_A_UART_LOW_FREQUENCY_BAUDRATE_GENERATION 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: EUSCI_A_UART_enableInterrupt(), and +// EUSCI_A_UART_disableInterrupt(). +// +//***************************************************************************** +#define EUSCI_A_UART_RECEIVE_INTERRUPT UCRXIE +#define EUSCI_A_UART_TRANSMIT_INTERRUPT UCTXIE +#define EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT UCRXEIE +#define EUSCI_A_UART_BREAKCHAR_INTERRUPT UCBRKIE +#define EUSCI_A_UART_STARTBIT_INTERRUPT UCSTTIE +#define EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT UCTXCPTIE + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: EUSCI_A_UART_getInterruptStatus(), and +// EUSCI_A_UART_clearInterrupt() as well as returned by the +// EUSCI_A_UART_getInterruptStatus() function. +// +//***************************************************************************** +#define EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG UCRXIFG +#define EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG UCTXIFG +#define EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG UCSTTIFG +#define EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG UCTXCPTIFG + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: EUSCI_A_UART_queryStatusFlags() as well as returned by the +// EUSCI_A_UART_queryStatusFlags() function. +// +//***************************************************************************** +#define EUSCI_A_UART_LISTEN_ENABLE UCLISTEN +#define EUSCI_A_UART_FRAMING_ERROR UCFE +#define EUSCI_A_UART_OVERRUN_ERROR UCOE +#define EUSCI_A_UART_PARITY_ERROR UCPE +#define EUSCI_A_UART_BREAK_DETECT UCBRK +#define EUSCI_A_UART_RECEIVE_ERROR UCRXERR +#define EUSCI_A_UART_ADDRESS_RECEIVED UCADDR +#define EUSCI_A_UART_IDLELINE UCIDLE +#define EUSCI_A_UART_BUSY UCBUSY + +//***************************************************************************** +// +// The following are values that can be passed to the deglitchTime parameter +// for functions: EUSCI_A_UART_selectDeglitchTime(). +// +//***************************************************************************** +#define EUSCI_A_UART_DEGLITCH_TIME_2ns 0x00 +#define EUSCI_A_UART_DEGLITCH_TIME_50ns UCGLIT0 +#define EUSCI_A_UART_DEGLITCH_TIME_100ns UCGLIT1 +#define EUSCI_A_UART_DEGLITCH_TIME_200ns (UCGLIT0 + UCGLIT1) + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Advanced initialization routine for the UART block. The values to be +//! written into the clockPrescalar, firstModReg, secondModReg and overSampling +//! parameters should be pre-computed and passed into the initialization +//! function. +//! +//! Upon successful initialization of the UART block, this function will have +//! initialized the module, but the UART block still remains disabled and must +//! be enabled with EUSCI_A_UART_enable(). To calculate values for +//! clockPrescalar, firstModReg, secondModReg and overSampling please use the +//! link below. +//! +//! http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSP430BaudRateConverter/index.html +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! \param param is the pointer to struct for initialization. +//! +//! Modified bits are \b UCPEN, \b UCPAR, \b UCMSB, \b UC7BIT, \b UCSPB, \b +//! UCMODEx and \b UCSYNC of \b UCAxCTL0 register; bits \b UCSSELx and \b +//! UCSWRST of \b UCAxCTL1 register. +//! +//! \return STATUS_SUCCESS or STATUS_FAIL of the initialization process +// +//***************************************************************************** +extern bool EUSCI_A_UART_init(uint16_t baseAddress, + EUSCI_A_UART_initParam *param); + +//***************************************************************************** +// +//! \brief Transmits a byte from the UART Module. +//! +//! This function will place the supplied data into UART transmit data register +//! to start transmission +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! \param transmitData data to be transmitted from the UART module +//! +//! Modified bits of \b UCAxTXBUF register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_A_UART_transmitData(uint16_t baseAddress, + uint8_t transmitData); + +//***************************************************************************** +// +//! \brief Receives a byte that has been sent to the UART Module. +//! +//! This function reads a byte of data from the UART receive data Register. +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! +//! Modified bits of \b UCAxRXBUF register. +//! +//! \return Returns the byte received from by the UART module, cast as an +//! uint8_t. +// +//***************************************************************************** +extern uint8_t EUSCI_A_UART_receiveData(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Enables individual UART interrupt sources. +//! +//! Enables the indicated UART interrupt sources. The interrupt flag is first +//! and then the corresponding interrupt is enabled. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. Does not clear interrupt flags. +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! \param mask is the bit mask of the interrupt sources to be enabled. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_A_UART_RECEIVE_INTERRUPT - Receive interrupt +//! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT - Transmit interrupt +//! - \b EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT - Receive +//! erroneous-character interrupt enable +//! - \b EUSCI_A_UART_BREAKCHAR_INTERRUPT - Receive break character +//! interrupt enable +//! - \b EUSCI_A_UART_STARTBIT_INTERRUPT - Start bit received interrupt +//! enable +//! - \b EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT - Transmit complete +//! interrupt enable +//! +//! Modified bits of \b UCAxCTL1 register and bits of \b UCAxIE register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_A_UART_enableInterrupt(uint16_t baseAddress, + uint8_t mask); + +//***************************************************************************** +// +//! \brief Disables individual UART interrupt sources. +//! +//! Disables the indicated UART interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! \param mask is the bit mask of the interrupt sources to be disabled. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_A_UART_RECEIVE_INTERRUPT - Receive interrupt +//! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT - Transmit interrupt +//! - \b EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT - Receive +//! erroneous-character interrupt enable +//! - \b EUSCI_A_UART_BREAKCHAR_INTERRUPT - Receive break character +//! interrupt enable +//! - \b EUSCI_A_UART_STARTBIT_INTERRUPT - Start bit received interrupt +//! enable +//! - \b EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT - Transmit complete +//! interrupt enable +//! +//! Modified bits of \b UCAxCTL1 register and bits of \b UCAxIE register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_A_UART_disableInterrupt(uint16_t baseAddress, + uint8_t mask); + +//***************************************************************************** +// +//! \brief Gets the current UART interrupt status. +//! +//! This returns the interrupt status for the UART module based on which flag +//! is passed. +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! \param mask is the masked interrupt flag status to be returned. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG +//! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG +//! - \b EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG +//! - \b EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG +//! +//! Modified bits of \b UCAxIFG register. +//! +//! \return Logical OR of any of the following: +//! - \b EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG +//! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG +//! - \b EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG +//! - \b EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG +//! \n indicating the status of the masked flags +// +//***************************************************************************** +extern uint8_t EUSCI_A_UART_getInterruptStatus(uint16_t baseAddress, + uint8_t mask); + +//***************************************************************************** +// +//! \brief Clears UART interrupt sources. +//! +//! The UART interrupt source is cleared, so that it no longer asserts. The +//! highest interrupt flag is automatically cleared when an interrupt vector +//! generator is used. +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! \param mask is a bit mask of the interrupt sources to be cleared. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG +//! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG +//! - \b EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG +//! - \b EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG +//! +//! Modified bits of \b UCAxIFG register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_A_UART_clearInterrupt(uint16_t baseAddress, + uint8_t mask); + +//***************************************************************************** +// +//! \brief Enables the UART block. +//! +//! This will enable operation of the UART block. +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! +//! Modified bits are \b UCSWRST of \b UCAxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_A_UART_enable(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Disables the UART block. +//! +//! This will disable operation of the UART block. +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! +//! Modified bits are \b UCSWRST of \b UCAxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_A_UART_disable(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Gets the current UART status flags. +//! +//! This returns the status for the UART module based on which flag is passed. +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! \param mask is the masked interrupt flag status to be returned. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_A_UART_LISTEN_ENABLE +//! - \b EUSCI_A_UART_FRAMING_ERROR +//! - \b EUSCI_A_UART_OVERRUN_ERROR +//! - \b EUSCI_A_UART_PARITY_ERROR +//! - \b EUSCI_A_UART_BREAK_DETECT +//! - \b EUSCI_A_UART_RECEIVE_ERROR +//! - \b EUSCI_A_UART_ADDRESS_RECEIVED +//! - \b EUSCI_A_UART_IDLELINE +//! - \b EUSCI_A_UART_BUSY +//! +//! Modified bits of \b UCAxSTAT register. +//! +//! \return Logical OR of any of the following: +//! - \b EUSCI_A_UART_LISTEN_ENABLE +//! - \b EUSCI_A_UART_FRAMING_ERROR +//! - \b EUSCI_A_UART_OVERRUN_ERROR +//! - \b EUSCI_A_UART_PARITY_ERROR +//! - \b EUSCI_A_UART_BREAK_DETECT +//! - \b EUSCI_A_UART_RECEIVE_ERROR +//! - \b EUSCI_A_UART_ADDRESS_RECEIVED +//! - \b EUSCI_A_UART_IDLELINE +//! - \b EUSCI_A_UART_BUSY +//! \n indicating the status of the masked interrupt flags +// +//***************************************************************************** +extern uint8_t EUSCI_A_UART_queryStatusFlags(uint16_t baseAddress, + uint8_t mask); + +//***************************************************************************** +// +//! \brief Sets the UART module in dormant mode +//! +//! Puts USCI in sleep mode Only characters that are preceded by an idle-line +//! or with address bit set UCRXIFG. In UART mode with automatic baud-rate +//! detection, only the combination of a break and sync field sets UCRXIFG. +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! +//! Modified bits of \b UCAxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_A_UART_setDormant(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Re-enables UART module from dormant mode +//! +//! Not dormant. All received characters set UCRXIFG. +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! +//! Modified bits are \b UCDORM of \b UCAxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_A_UART_resetDormant(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Transmits the next byte to be transmitted marked as address +//! depending on selected multiprocessor mode +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! \param transmitAddress is the next byte to be transmitted +//! +//! Modified bits of \b UCAxTXBUF register and bits of \b UCAxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_A_UART_transmitAddress(uint16_t baseAddress, + uint8_t transmitAddress); + +//***************************************************************************** +// +//! \brief Transmit break. +//! +//! Transmits a break with the next write to the transmit buffer. In UART mode +//! with automatic baud-rate detection, +//! EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC(0x55) must be written into UCAxTXBUF to +//! generate the required break/sync fields. Otherwise, DEFAULT_SYNC(0x00) must +//! be written into the transmit buffer. Also ensures module is ready for +//! transmitting the next data. +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! +//! Modified bits of \b UCAxTXBUF register and bits of \b UCAxCTL1 register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_A_UART_transmitBreak(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Returns the address of the RX Buffer of the UART for the DMA module. +//! +//! Returns the address of the UART RX Buffer. This can be used in conjunction +//! with the DMA to store the received data directly to memory. +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! +//! \return Address of RX Buffer +// +//***************************************************************************** +extern uint32_t EUSCI_A_UART_getReceiveBufferAddress(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Returns the address of the TX Buffer of the UART for the DMA module. +//! +//! Returns the address of the UART TX Buffer. This can be used in conjunction +//! with the DMA to obtain transmitted data directly from memory. +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! +//! \return Address of TX Buffer +// +//***************************************************************************** +extern uint32_t EUSCI_A_UART_getTransmitBufferAddress(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Sets the deglitch time +//! +//! \param baseAddress is the base address of the EUSCI_A_UART module. +//! \param deglitchTime is the selected deglitch time +//! Valid values are: +//! - \b EUSCI_A_UART_DEGLITCH_TIME_2ns +//! - \b EUSCI_A_UART_DEGLITCH_TIME_50ns +//! - \b EUSCI_A_UART_DEGLITCH_TIME_100ns +//! - \b EUSCI_A_UART_DEGLITCH_TIME_200ns +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_A_UART_selectDeglitchTime(uint16_t baseAddress, + uint16_t deglitchTime); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_EUSCI_A_UART_H__ diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/eusci_b_i2c.c b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/eusci_b_i2c.c new file mode 100644 index 000000000..a018ab15d --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/eusci_b_i2c.c @@ -0,0 +1,644 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// eusci_b_i2c.c - Driver for the eusci_b_i2c Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup eusci_b_i2c_api eusci_b_i2c +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_EUSCI_Bx__ +#include "eusci_b_i2c.h" + +#include + +void EUSCI_B_I2C_initMaster(uint16_t baseAddress, + EUSCI_B_I2C_initMasterParam *param) +{ + uint16_t preScalarValue; + + //Disable the USCI module and clears the other bits of control register + HWREG16(baseAddress + OFS_UCBxCTLW0) = UCSWRST; + + //Configure Automatic STOP condition generation + HWREG16(baseAddress + OFS_UCBxCTLW1) &= ~UCASTP_3; + HWREG16(baseAddress + OFS_UCBxCTLW1) |= param->autoSTOPGeneration; + + //Byte Count Threshold + HWREG16(baseAddress + OFS_UCBxTBCNT) = param->byteCounterThreshold; + /* + * Configure as I2C master mode. + * UCMST = Master mode + * UCMODE_3 = I2C mode + * UCSYNC = Synchronous mode + */ + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCMST + UCMODE_3 + UCSYNC; + + //Configure I2C clock source + HWREG16(baseAddress + + OFS_UCBxCTLW0) |= (param->selectClockSource + UCSWRST); + + /* + * Compute the clock divider that achieves the fastest speed less than or + * equal to the desired speed. The numerator is biased to favor a larger + * clock divider so that the resulting clock is always less than or equal + * to the desired clock, never greater. + */ + preScalarValue = (uint16_t)(param->i2cClk / param->dataRate); + HWREG16(baseAddress + OFS_UCBxBRW) = preScalarValue; +} + +void EUSCI_B_I2C_initSlave(uint16_t baseAddress, + EUSCI_B_I2C_initSlaveParam *param) +{ + //Disable the USCI module + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST; + + //Clear USCI master mode + HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~UCMST; + + //Configure I2C as Slave and Synchronous mode + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCMODE_3 + UCSYNC; + + //Set up the slave address. + HWREG16(baseAddress + OFS_UCBxI2COA0 + param->slaveAddressOffset) + = param->slaveAddress + param->slaveOwnAddressEnable; +} + +void EUSCI_B_I2C_enable(uint16_t baseAddress) +{ + //Reset the UCSWRST bit to enable the USCI Module + HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCSWRST); +} + +void EUSCI_B_I2C_disable(uint16_t baseAddress) +{ + //Set the UCSWRST bit to disable the USCI Module + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST; +} + +void EUSCI_B_I2C_setSlaveAddress(uint16_t baseAddress, + uint8_t slaveAddress) +{ + //Set the address of the slave with which the master will communicate. + HWREG16(baseAddress + OFS_UCBxI2CSA) = (slaveAddress); +} + +void EUSCI_B_I2C_setMode(uint16_t baseAddress, + uint8_t mode) +{ + HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~EUSCI_B_I2C_TRANSMIT_MODE; + HWREG16(baseAddress + OFS_UCBxCTLW0) |= mode; +} + +uint8_t EUSCI_B_I2C_getMode(uint16_t baseAddress) +{ + //Read the I2C mode. + return ((HWREG16(baseAddress + OFS_UCBxCTLW0) & UCTR)); +} + +void EUSCI_B_I2C_slavePutData(uint16_t baseAddress, + uint8_t transmitData) +{ + //Send single byte data. + HWREG16(baseAddress + OFS_UCBxTXBUF) = transmitData; +} + +uint8_t EUSCI_B_I2C_slaveGetData(uint16_t baseAddress) +{ + //Read a byte. + return (HWREG16(baseAddress + OFS_UCBxRXBUF)); +} + +uint16_t EUSCI_B_I2C_isBusBusy(uint16_t baseAddress) +{ + //Return the bus busy status. + return (HWREG16(baseAddress + OFS_UCBxSTATW) & UCBBUSY); +} + +uint16_t EUSCI_B_I2C_masterIsStopSent(uint16_t baseAddress) +{ + return (HWREG16(baseAddress + OFS_UCBxCTLW0) & UCTXSTP); +} + +uint16_t EUSCI_B_I2C_masterIsStartSent(uint16_t baseAddress) +{ + return (HWREG16(baseAddress + OFS_UCBxCTLW0) & UCTXSTT); +} + +void EUSCI_B_I2C_enableInterrupt(uint16_t baseAddress, + uint16_t mask) +{ + //Enable the interrupt masked bit + HWREG16(baseAddress + OFS_UCBxIE) |= mask; +} + +void EUSCI_B_I2C_disableInterrupt(uint16_t baseAddress, + uint16_t mask) +{ + //Disable the interrupt masked bit + HWREG16(baseAddress + OFS_UCBxIE) &= ~(mask); +} + +void EUSCI_B_I2C_clearInterrupt(uint16_t baseAddress, + uint16_t mask) +{ + //Clear the I2C interrupt source. + HWREG16(baseAddress + OFS_UCBxIFG) &= ~(mask); +} + +uint16_t EUSCI_B_I2C_getInterruptStatus(uint16_t baseAddress, + uint16_t mask) +{ + //Return the interrupt status of the request masked bit. + return (HWREG16(baseAddress + OFS_UCBxIFG) & mask); +} + +void EUSCI_B_I2C_masterSendSingleByte(uint16_t baseAddress, + uint8_t txData) +{ + //Store current TXIE status + uint16_t txieStatus = HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE; + + //Disable transmit interrupt enable + HWREG16(baseAddress + OFS_UCBxIE) &= ~(UCTXIE); + + //Send start condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTR + UCTXSTT; + + //Poll for transmit interrupt flag. + while(!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) + { + ; + } + + //Send single byte data. + HWREG16(baseAddress + OFS_UCBxTXBUF) = txData; + + //Poll for transmit interrupt flag. + while(!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) + { + ; + } + + //Send stop condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP; + + //Clear transmit interrupt flag before enabling interrupt again + HWREG16(baseAddress + OFS_UCBxIFG) &= ~(UCTXIFG); + + //Reinstate transmit interrupt enable + HWREG16(baseAddress + OFS_UCBxIE) |= txieStatus; +} + +uint8_t EUSCI_B_I2C_masterReceiveSingleByte(uint16_t baseAddress) +{ + //Set USCI in Receive mode + HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~UCTR; + + //Send start + HWREG16(baseAddress + OFS_UCBxCTLW0) |= (UCTXSTT + UCTXSTP); + + //Poll for receive interrupt flag. + while(!(HWREG16(baseAddress + OFS_UCBxIFG) & UCRXIFG)) + { + ; + } + + //Send single byte data. + return (HWREG16(baseAddress + OFS_UCBxRXBUF)); +} + +bool EUSCI_B_I2C_masterSendSingleByteWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout) +{ + // Creating variable for second timeout scenario + uint32_t timeout2 = timeout; + + //Store current TXIE status + uint16_t txieStatus = HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE; + + //Disable transmit interrupt enable + HWREG16(baseAddress + OFS_UCBxIE) &= ~(UCTXIE); + + //Send start condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTR + UCTXSTT; + + //Poll for transmit interrupt flag. + while((!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout) + { + ; + } + + //Check if transfer timed out + if(timeout == 0) + { + return (STATUS_FAIL); + } + + //Send single byte data. + HWREG16(baseAddress + OFS_UCBxTXBUF) = txData; + + //Poll for transmit interrupt flag. + while((!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout2) + { + ; + } + + //Check if transfer timed out + if(timeout2 == 0) + { + return (STATUS_FAIL); + } + + //Send stop condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP; + + //Clear transmit interrupt flag before enabling interrupt again + HWREG16(baseAddress + OFS_UCBxIFG) &= ~(UCTXIFG); + + //Reinstate transmit interrupt enable + HWREG16(baseAddress + OFS_UCBxIE) |= txieStatus; + + return (STATUS_SUCCESS); +} + +void EUSCI_B_I2C_masterSendMultiByteStart(uint16_t baseAddress, + uint8_t txData) +{ + //Store current transmit interrupt enable + uint16_t txieStatus = HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE; + + //Disable transmit interrupt enable + HWREG16(baseAddress + OFS_UCBxIE) &= ~(UCTXIE); + + //Send start condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTR + UCTXSTT; + + //Poll for transmit interrupt flag. + while(!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) + { + ; + } + + //Send single byte data. + HWREG16(baseAddress + OFS_UCBxTXBUF) = txData; + + //Reinstate transmit interrupt enable + HWREG16(baseAddress + OFS_UCBxIE) |= txieStatus; +} + +bool EUSCI_B_I2C_masterSendMultiByteStartWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout) +{ + //Store current transmit interrupt enable + uint16_t txieStatus = HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE; + + //Disable transmit interrupt enable + HWREG16(baseAddress + OFS_UCBxIE) &= ~(UCTXIE); + + //Send start condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTR + UCTXSTT; + + //Poll for transmit interrupt flag. + while((!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout) + { + ; + } + + //Check if transfer timed out + if(timeout == 0) + { + return (STATUS_FAIL); + } + + //Send single byte data. + HWREG16(baseAddress + OFS_UCBxTXBUF) = txData; + + //Reinstate transmit interrupt enable + HWREG16(baseAddress + OFS_UCBxIE) |= txieStatus; + + return(STATUS_SUCCESS); +} + +void EUSCI_B_I2C_masterSendMultiByteNext(uint16_t baseAddress, + uint8_t txData) +{ + //If interrupts are not used, poll for flags + if(!(HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE)) + { + //Poll for transmit interrupt flag. + while(!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) + { + ; + } + } + + //Send single byte data. + HWREG16(baseAddress + OFS_UCBxTXBUF) = txData; +} + +bool EUSCI_B_I2C_masterSendMultiByteNextWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout) +{ + //If interrupts are not used, poll for flags + if(!(HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE)) + { + //Poll for transmit interrupt flag. + while((!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout) + { + ; + } + + //Check if transfer timed out + if(timeout == 0) + { + return (STATUS_FAIL); + } + } + + //Send single byte data. + HWREG16(baseAddress + OFS_UCBxTXBUF) = txData; + + return(STATUS_SUCCESS); +} + +void EUSCI_B_I2C_masterSendMultiByteFinish(uint16_t baseAddress, + uint8_t txData) +{ + //If interrupts are not used, poll for flags + if(!(HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE)) + { + //Poll for transmit interrupt flag. + while(!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) + { + ; + } + } + + //Send single byte data. + HWREG16(baseAddress + OFS_UCBxTXBUF) = txData; + + //Poll for transmit interrupt flag. + while(!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) + { + ; + } + + //Send stop condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP; +} + +bool EUSCI_B_I2C_masterSendMultiByteFinishWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout) +{ + uint32_t timeout2 = timeout; + + //If interrupts are not used, poll for flags + if(!(HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE)) + { + //Poll for transmit interrupt flag. + while((!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout) + { + ; + } + + //Check if transfer timed out + if(timeout == 0) + { + return (STATUS_FAIL); + } + } + + //Send single byte data. + HWREG16(baseAddress + OFS_UCBxTXBUF) = txData; + + //Poll for transmit interrupt flag. + while((!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout2) + { + ; + } + + //Check if transfer timed out + if(timeout2 == 0) + { + return (STATUS_FAIL); + } + + //Send stop condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP; + + return(STATUS_SUCCESS); +} + +void EUSCI_B_I2C_masterSendStart(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTT; +} + +void EUSCI_B_I2C_masterSendMultiByteStop(uint16_t baseAddress) +{ + //If interrupts are not used, poll for flags + if(!(HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE)) + { + //Poll for transmit interrupt flag. + while(!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) + { + ; + } + } + + //Send stop condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP; +} + +bool EUSCI_B_I2C_masterSendMultiByteStopWithTimeout(uint16_t baseAddress, + uint32_t timeout) +{ + //If interrupts are not used, poll for flags + if(!(HWREG16(baseAddress + OFS_UCBxIE) & UCTXIE)) + { + //Poll for transmit interrupt flag. + while((!(HWREG16(baseAddress + OFS_UCBxIFG) & UCTXIFG)) && --timeout) + { + ; + } + + //Check if transfer timed out + if(timeout == 0) + { + return (STATUS_FAIL); + } + } + + //Send stop condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP; + + return (STATUS_SUCCESS); +} + +void EUSCI_B_I2C_masterReceiveStart(uint16_t baseAddress) +{ + //Set USCI in Receive mode + HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~UCTR; + //Send start + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTT; +} + +uint8_t EUSCI_B_I2C_masterReceiveMultiByteNext(uint16_t baseAddress) +{ + return (HWREG16(baseAddress + OFS_UCBxRXBUF)); +} + +uint8_t EUSCI_B_I2C_masterReceiveMultiByteFinish(uint16_t baseAddress) +{ + //Send stop condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP; + + //Wait for Stop to finish + while(HWREG16(baseAddress + OFS_UCBxCTLW0) & UCTXSTP) + { + // Wait for RX buffer + while(!(HWREG16(baseAddress + OFS_UCBxIFG) & UCRXIFG)) + { + ; + } + } + + //Capture data from receive buffer after setting stop bit due to + //MSP430 I2C critical timing. + return (HWREG16(baseAddress + OFS_UCBxRXBUF)); +} + +bool EUSCI_B_I2C_masterReceiveMultiByteFinishWithTimeout(uint16_t baseAddress, + uint8_t *txData, + uint32_t timeout) +{ + uint32_t timeout2 = timeout; + + //Send stop condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP; + + //Wait for Stop to finish + while((HWREG16(baseAddress + OFS_UCBxCTLW0) & UCTXSTP) && --timeout) + { + ; + } + + //Check if transfer timed out + if(timeout == 0) + { + return (STATUS_FAIL); + } + + // Wait for RX buffer + while((!(HWREG16(baseAddress + OFS_UCBxIFG) & UCRXIFG)) && --timeout2) + { + ; + } + + //Check if transfer timed out + if(timeout2 == 0) + { + return (STATUS_FAIL); + } + + //Capture data from receive buffer after setting stop bit due to + //MSP430 I2C critical timing. + *txData = (HWREG8(baseAddress + OFS_UCBxRXBUF)); + + return (STATUS_SUCCESS); +} + +void EUSCI_B_I2C_masterReceiveMultiByteStop(uint16_t baseAddress) +{ + //Send stop condition. + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCTXSTP; +} + +void EUSCI_B_I2C_enableMultiMasterMode(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST; + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCMM; +} + +void EUSCI_B_I2C_disableMultiMasterMode(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST; + HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~UCMM; +} + +uint8_t EUSCI_B_I2C_masterReceiveSingle(uint16_t baseAddress) +{ + //Polling RXIFG0 if RXIE is not enabled + if(!(HWREG16(baseAddress + OFS_UCBxIE) & UCRXIE0)) + { + while(!(HWREG16(baseAddress + OFS_UCBxIFG) & UCRXIFG0)) + { + ; + } + } + + //Read a byte. + return (HWREG16(baseAddress + OFS_UCBxRXBUF)); +} + +uint32_t EUSCI_B_I2C_getReceiveBufferAddress(uint16_t baseAddress) +{ + return (baseAddress + OFS_UCBxRXBUF); +} + +uint32_t EUSCI_B_I2C_getTransmitBufferAddress(uint16_t baseAddress) +{ + return (baseAddress + OFS_UCBxTXBUF); +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for eusci_b_i2c_api +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/eusci_b_i2c.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/eusci_b_i2c.h new file mode 100644 index 000000000..4b101b07b --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/eusci_b_i2c.h @@ -0,0 +1,1009 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// eusci_b_i2c.h - Driver for the EUSCI_B_I2C Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_EUSCI_B_I2C_H__ +#define __MSP430WARE_EUSCI_B_I2C_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_EUSCI_Bx__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "inc/hw_regaccess.h" +//***************************************************************************** +// +//! \brief Used in the EUSCI_B_I2C_initMaster() function as the param +//! parameter. +// +//***************************************************************************** +typedef struct EUSCI_B_I2C_initMasterParam +{ + //! Is the clocksource. + //! \n Valid values are: + //! - \b EUSCI_B_I2C_CLOCKSOURCE_ACLK + //! - \b EUSCI_B_I2C_CLOCKSOURCE_SMCLK + uint8_t selectClockSource; + //! Is the rate of the clock supplied to the I2C module (the frequency in + //! Hz of the clock source specified in selectClockSource). + uint32_t i2cClk; + //! Setup for selecting data transfer rate. + //! \n Valid values are: + //! - \b EUSCI_B_I2C_SET_DATA_RATE_400KBPS + //! - \b EUSCI_B_I2C_SET_DATA_RATE_100KBPS + uint32_t dataRate; + //! Sets threshold for automatic STOP or UCSTPIFG + uint8_t byteCounterThreshold; + //! Sets up the STOP condition generation. + //! \n Valid values are: + //! - \b EUSCI_B_I2C_NO_AUTO_STOP + //! - \b EUSCI_B_I2C_SET_BYTECOUNT_THRESHOLD_FLAG + //! - \b EUSCI_B_I2C_SEND_STOP_AUTOMATICALLY_ON_BYTECOUNT_THRESHOLD + uint8_t autoSTOPGeneration; +} EUSCI_B_I2C_initMasterParam; + +//***************************************************************************** +// +//! \brief Used in the EUSCI_B_I2C_initSlave() function as the param parameter. +// +//***************************************************************************** +typedef struct EUSCI_B_I2C_initSlaveParam +{ + //! 7-bit slave address + uint8_t slaveAddress; + //! Own address Offset referred to- 'x' value of UCBxI2COAx. + //! \n Valid values are: + //! - \b EUSCI_B_I2C_OWN_ADDRESS_OFFSET0 + //! - \b EUSCI_B_I2C_OWN_ADDRESS_OFFSET1 + //! - \b EUSCI_B_I2C_OWN_ADDRESS_OFFSET2 + //! - \b EUSCI_B_I2C_OWN_ADDRESS_OFFSET3 + uint8_t slaveAddressOffset; + //! Selects if the specified address is enabled or disabled. + //! \n Valid values are: + //! - \b EUSCI_B_I2C_OWN_ADDRESS_DISABLE + //! - \b EUSCI_B_I2C_OWN_ADDRESS_ENABLE + uint32_t slaveOwnAddressEnable; +} EUSCI_B_I2C_initSlaveParam; + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: EUSCI_B_I2C_initMaster(). +// +//***************************************************************************** +#define EUSCI_B_I2C_NO_AUTO_STOP UCASTP_0 +#define EUSCI_B_I2C_SET_BYTECOUNT_THRESHOLD_FLAG UCASTP_1 +#define EUSCI_B_I2C_SEND_STOP_AUTOMATICALLY_ON_BYTECOUNT_THRESHOLD UCASTP_2 + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: EUSCI_B_I2C_initMaster(). +// +//***************************************************************************** +#define EUSCI_B_I2C_SET_DATA_RATE_400KBPS 400000 +#define EUSCI_B_I2C_SET_DATA_RATE_100KBPS 100000 + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: EUSCI_B_I2C_initMaster(). +// +//***************************************************************************** +#define EUSCI_B_I2C_CLOCKSOURCE_ACLK UCSSEL__ACLK +#define EUSCI_B_I2C_CLOCKSOURCE_SMCLK UCSSEL__SMCLK + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: EUSCI_B_I2C_initSlave(). +// +//***************************************************************************** +#define EUSCI_B_I2C_OWN_ADDRESS_OFFSET0 0x00 +#define EUSCI_B_I2C_OWN_ADDRESS_OFFSET1 0x02 +#define EUSCI_B_I2C_OWN_ADDRESS_OFFSET2 0x04 +#define EUSCI_B_I2C_OWN_ADDRESS_OFFSET3 0x06 + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: EUSCI_B_I2C_initSlave(). +// +//***************************************************************************** +#define EUSCI_B_I2C_OWN_ADDRESS_DISABLE 0x00 +#define EUSCI_B_I2C_OWN_ADDRESS_ENABLE UCOAEN + +//***************************************************************************** +// +// The following are values that can be passed to the mode parameter for +// functions: EUSCI_B_I2C_setMode() as well as returned by the +// EUSCI_B_I2C_getMode() function. +// +//***************************************************************************** +#define EUSCI_B_I2C_TRANSMIT_MODE UCTR +#define EUSCI_B_I2C_RECEIVE_MODE 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: EUSCI_B_I2C_enableInterrupt(), EUSCI_B_I2C_disableInterrupt(), +// EUSCI_B_I2C_clearInterrupt(), and EUSCI_B_I2C_getInterruptStatus() as well +// as returned by the EUSCI_B_I2C_getInterruptStatus() function. +// +//***************************************************************************** +#define EUSCI_B_I2C_NAK_INTERRUPT UCNACKIE +#define EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT UCALIE +#define EUSCI_B_I2C_STOP_INTERRUPT UCSTPIE +#define EUSCI_B_I2C_START_INTERRUPT UCSTTIE +#define EUSCI_B_I2C_TRANSMIT_INTERRUPT0 UCTXIE0 +#define EUSCI_B_I2C_TRANSMIT_INTERRUPT1 UCTXIE1 +#define EUSCI_B_I2C_TRANSMIT_INTERRUPT2 UCTXIE2 +#define EUSCI_B_I2C_TRANSMIT_INTERRUPT3 UCTXIE3 +#define EUSCI_B_I2C_RECEIVE_INTERRUPT0 UCRXIE0 +#define EUSCI_B_I2C_RECEIVE_INTERRUPT1 UCRXIE1 +#define EUSCI_B_I2C_RECEIVE_INTERRUPT2 UCRXIE2 +#define EUSCI_B_I2C_RECEIVE_INTERRUPT3 UCRXIE3 +#define EUSCI_B_I2C_BIT9_POSITION_INTERRUPT UCBIT9IE +#define EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT UCCLTOIE +#define EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT UCBCNTIE + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the EUSCI_B_I2C_isBusBusy() function. +// +//***************************************************************************** +#define EUSCI_B_I2C_BUS_BUSY UCBBUSY +#define EUSCI_B_I2C_BUS_NOT_BUSY 0x00 + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the EUSCI_B_I2C_masterIsStopSent() function. +// +//***************************************************************************** +#define EUSCI_B_I2C_STOP_SEND_COMPLETE 0x00 +#define EUSCI_B_I2C_SENDING_STOP UCTXSTP + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the EUSCI_B_I2C_masterIsStartSent() function. +// +//***************************************************************************** +#define EUSCI_B_I2C_START_SEND_COMPLETE 0x00 +#define EUSCI_B_I2C_SENDING_START UCTXSTT + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Initializes the I2C Master block. +//! +//! This function initializes operation of the I2C Master block. Upon +//! successful initialization of the I2C block, this function will have set the +//! bus speed for the master; however I2C module is still disabled till +//! EUSCI_B_I2C_enable is invoked. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param param is the pointer to the struct for master initialization. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_B_I2C_initMaster(uint16_t baseAddress, + EUSCI_B_I2C_initMasterParam *param); + +//***************************************************************************** +// +//! \brief Initializes the I2C Slave block. +//! +//! This function initializes operation of the I2C as a Slave mode. Upon +//! successful initialization of the I2C blocks, this function will have set +//! the slave address but the I2C module is still disabled till +//! EUSCI_B_I2C_enable is invoked. +//! +//! \param baseAddress is the base address of the I2C Slave module. +//! \param param is the pointer to the struct for slave initialization. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_B_I2C_initSlave(uint16_t baseAddress, + EUSCI_B_I2C_initSlaveParam *param); + +//***************************************************************************** +// +//! \brief Enables the I2C block. +//! +//! This will enable operation of the I2C block. +//! +//! \param baseAddress is the base address of the USCI I2C module. +//! +//! Modified bits are \b UCSWRST of \b UCBxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_B_I2C_enable(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Disables the I2C block. +//! +//! This will disable operation of the I2C block. +//! +//! \param baseAddress is the base address of the USCI I2C module. +//! +//! Modified bits are \b UCSWRST of \b UCBxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_B_I2C_disable(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Sets the address that the I2C Master will place on the bus. +//! +//! This function will set the address that the I2C Master will place on the +//! bus when initiating a transaction. +//! +//! \param baseAddress is the base address of the USCI I2C module. +//! \param slaveAddress 7-bit slave address +//! +//! Modified bits of \b UCBxI2CSA register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_B_I2C_setSlaveAddress(uint16_t baseAddress, + uint8_t slaveAddress); + +//***************************************************************************** +// +//! \brief Sets the mode of the I2C device +//! +//! When the receive parameter is set to EUSCI_B_I2C_TRANSMIT_MODE, the address +//! will indicate that the I2C module is in receive mode; otherwise, the I2C +//! module is in send mode. +//! +//! \param baseAddress is the base address of the USCI I2C module. +//! \param mode Mode for the EUSCI_B_I2C module +//! Valid values are: +//! - \b EUSCI_B_I2C_TRANSMIT_MODE [Default] +//! - \b EUSCI_B_I2C_RECEIVE_MODE +//! +//! Modified bits are \b UCTR of \b UCBxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_B_I2C_setMode(uint16_t baseAddress, + uint8_t mode); + +//***************************************************************************** +// +//! \brief Gets the mode of the I2C device +//! +//! Current I2C transmit/receive mode. +//! +//! \param baseAddress is the base address of the I2C module. +//! +//! Modified bits are \b UCTR of \b UCBxCTLW0 register. +//! +//! \return One of the following: +//! - \b EUSCI_B_I2C_TRANSMIT_MODE +//! - \b EUSCI_B_I2C_RECEIVE_MODE +//! \n indicating the current mode +// +//***************************************************************************** +extern uint8_t EUSCI_B_I2C_getMode(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Transmits a byte from the I2C Module. +//! +//! This function will place the supplied data into I2C transmit data register +//! to start transmission. +//! +//! \param baseAddress is the base address of the I2C Slave module. +//! \param transmitData data to be transmitted from the I2C module +//! +//! Modified bits of \b UCBxTXBUF register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_B_I2C_slavePutData(uint16_t baseAddress, + uint8_t transmitData); + +//***************************************************************************** +// +//! \brief Receives a byte that has been sent to the I2C Module. +//! +//! This function reads a byte of data from the I2C receive data Register. +//! +//! \param baseAddress is the base address of the I2C Slave module. +//! +//! \return Returns the byte received from by the I2C module, cast as an +//! uint8_t. +// +//***************************************************************************** +extern uint8_t EUSCI_B_I2C_slaveGetData(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Indicates whether or not the I2C bus is busy. +//! +//! This function returns an indication of whether or not the I2C bus is busy. +//! This function checks the status of the bus via UCBBUSY bit in UCBxSTAT +//! register. +//! +//! \param baseAddress is the base address of the I2C module. +//! +//! \return One of the following: +//! - \b EUSCI_B_I2C_BUS_BUSY +//! - \b EUSCI_B_I2C_BUS_NOT_BUSY +//! \n indicating whether the bus is busy +// +//***************************************************************************** +extern uint16_t EUSCI_B_I2C_isBusBusy(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Indicates whether STOP got sent. +//! +//! This function returns an indication of whether or not STOP got sent This +//! function checks the status of the bus via UCTXSTP bit in UCBxCTL1 register. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! \return One of the following: +//! - \b EUSCI_B_I2C_STOP_SEND_COMPLETE +//! - \b EUSCI_B_I2C_SENDING_STOP +//! \n indicating whether the stop was sent +// +//***************************************************************************** +extern uint16_t EUSCI_B_I2C_masterIsStopSent(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Indicates whether Start got sent. +//! +//! This function returns an indication of whether or not Start got sent This +//! function checks the status of the bus via UCTXSTT bit in UCBxCTL1 register. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! \return One of the following: +//! - \b EUSCI_B_I2C_START_SEND_COMPLETE +//! - \b EUSCI_B_I2C_SENDING_START +//! \n indicating whether the start was sent +// +//***************************************************************************** +extern uint16_t EUSCI_B_I2C_masterIsStartSent(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Enables individual I2C interrupt sources. +//! +//! Enables the indicated I2C interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! \param baseAddress is the base address of the I2C module. +//! \param mask is the bit mask of the interrupt sources to be enabled. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_B_I2C_NAK_INTERRUPT - Not-acknowledge interrupt +//! - \b EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT - Arbitration lost +//! interrupt +//! - \b EUSCI_B_I2C_STOP_INTERRUPT - STOP condition interrupt +//! - \b EUSCI_B_I2C_START_INTERRUPT - START condition interrupt +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT0 - Transmit interrupt0 +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT1 - Transmit interrupt1 +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT2 - Transmit interrupt2 +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT3 - Transmit interrupt3 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT0 - Receive interrupt0 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT1 - Receive interrupt1 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT2 - Receive interrupt2 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT3 - Receive interrupt3 +//! - \b EUSCI_B_I2C_BIT9_POSITION_INTERRUPT - Bit position 9 interrupt +//! - \b EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT - Clock low timeout +//! interrupt enable +//! - \b EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT - Byte counter interrupt +//! enable +//! +//! Modified bits of \b UCBxIE register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_B_I2C_enableInterrupt(uint16_t baseAddress, + uint16_t mask); + +//***************************************************************************** +// +//! \brief Disables individual I2C interrupt sources. +//! +//! Disables the indicated I2C interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! \param baseAddress is the base address of the I2C module. +//! \param mask is the bit mask of the interrupt sources to be disabled. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_B_I2C_NAK_INTERRUPT - Not-acknowledge interrupt +//! - \b EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT - Arbitration lost +//! interrupt +//! - \b EUSCI_B_I2C_STOP_INTERRUPT - STOP condition interrupt +//! - \b EUSCI_B_I2C_START_INTERRUPT - START condition interrupt +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT0 - Transmit interrupt0 +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT1 - Transmit interrupt1 +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT2 - Transmit interrupt2 +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT3 - Transmit interrupt3 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT0 - Receive interrupt0 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT1 - Receive interrupt1 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT2 - Receive interrupt2 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT3 - Receive interrupt3 +//! - \b EUSCI_B_I2C_BIT9_POSITION_INTERRUPT - Bit position 9 interrupt +//! - \b EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT - Clock low timeout +//! interrupt enable +//! - \b EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT - Byte counter interrupt +//! enable +//! +//! Modified bits of \b UCBxIE register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_B_I2C_disableInterrupt(uint16_t baseAddress, + uint16_t mask); + +//***************************************************************************** +// +//! \brief Clears I2C interrupt sources. +//! +//! The I2C interrupt source is cleared, so that it no longer asserts. The +//! highest interrupt flag is automatically cleared when an interrupt vector +//! generator is used. +//! +//! \param baseAddress is the base address of the I2C module. +//! \param mask is a bit mask of the interrupt sources to be cleared. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_B_I2C_NAK_INTERRUPT - Not-acknowledge interrupt +//! - \b EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT - Arbitration lost +//! interrupt +//! - \b EUSCI_B_I2C_STOP_INTERRUPT - STOP condition interrupt +//! - \b EUSCI_B_I2C_START_INTERRUPT - START condition interrupt +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT0 - Transmit interrupt0 +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT1 - Transmit interrupt1 +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT2 - Transmit interrupt2 +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT3 - Transmit interrupt3 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT0 - Receive interrupt0 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT1 - Receive interrupt1 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT2 - Receive interrupt2 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT3 - Receive interrupt3 +//! - \b EUSCI_B_I2C_BIT9_POSITION_INTERRUPT - Bit position 9 interrupt +//! - \b EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT - Clock low timeout +//! interrupt enable +//! - \b EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT - Byte counter interrupt +//! enable +//! +//! Modified bits of \b UCBxIFG register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_B_I2C_clearInterrupt(uint16_t baseAddress, + uint16_t mask); + +//***************************************************************************** +// +//! \brief Gets the current I2C interrupt status. +//! +//! This returns the interrupt status for the I2C module based on which flag is +//! passed. +//! +//! \param baseAddress is the base address of the I2C module. +//! \param mask is the masked interrupt flag status to be returned. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_B_I2C_NAK_INTERRUPT - Not-acknowledge interrupt +//! - \b EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT - Arbitration lost +//! interrupt +//! - \b EUSCI_B_I2C_STOP_INTERRUPT - STOP condition interrupt +//! - \b EUSCI_B_I2C_START_INTERRUPT - START condition interrupt +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT0 - Transmit interrupt0 +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT1 - Transmit interrupt1 +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT2 - Transmit interrupt2 +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT3 - Transmit interrupt3 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT0 - Receive interrupt0 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT1 - Receive interrupt1 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT2 - Receive interrupt2 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT3 - Receive interrupt3 +//! - \b EUSCI_B_I2C_BIT9_POSITION_INTERRUPT - Bit position 9 interrupt +//! - \b EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT - Clock low timeout +//! interrupt enable +//! - \b EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT - Byte counter interrupt +//! enable +//! +//! \return Logical OR of any of the following: +//! - \b EUSCI_B_I2C_NAK_INTERRUPT Not-acknowledge interrupt +//! - \b EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT Arbitration lost +//! interrupt +//! - \b EUSCI_B_I2C_STOP_INTERRUPT STOP condition interrupt +//! - \b EUSCI_B_I2C_START_INTERRUPT START condition interrupt +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT0 Transmit interrupt0 +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT1 Transmit interrupt1 +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT2 Transmit interrupt2 +//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT3 Transmit interrupt3 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT0 Receive interrupt0 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT1 Receive interrupt1 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT2 Receive interrupt2 +//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT3 Receive interrupt3 +//! - \b EUSCI_B_I2C_BIT9_POSITION_INTERRUPT Bit position 9 interrupt +//! - \b EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT Clock low timeout +//! interrupt enable +//! - \b EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT Byte counter interrupt +//! enable +//! \n indicating the status of the masked interrupts +// +//***************************************************************************** +extern uint16_t EUSCI_B_I2C_getInterruptStatus(uint16_t baseAddress, + uint16_t mask); + +//***************************************************************************** +// +//! \brief Does single byte transmission from Master to Slave +//! +//! This function is used by the Master module to send a single byte. This +//! function sends a start, then transmits the byte to the slave and then sends +//! a stop. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the data byte to be transmitted +//! +//! Modified bits of \b UCBxTXBUF register, bits of \b UCBxCTLW0 register, bits +//! of \b UCBxIE register and bits of \b UCBxIFG register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_B_I2C_masterSendSingleByte(uint16_t baseAddress, + uint8_t txData); + +//***************************************************************************** +// +//! \brief Does single byte reception from Slave +//! +//! This function is used by the Master module to receive a single byte. This +//! function sends start and stop, waits for data reception and then receives +//! the data from the slave +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! Modified bits of \b UCBxTXBUF register, bits of \b UCBxCTLW0 register, bits +//! of \b UCBxIE register and bits of \b UCBxIFG register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process. +// +//***************************************************************************** +extern uint8_t EUSCI_B_I2C_masterReceiveSingleByte(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Does single byte transmission from Master to Slave with timeout +//! +//! This function is used by the Master module to send a single byte. This +//! function sends a start, then transmits the byte to the slave and then sends +//! a stop. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the data byte to be transmitted +//! \param timeout is the amount of time to wait until giving up +//! +//! Modified bits of \b UCBxTXBUF register, bits of \b UCBxCTLW0 register, bits +//! of \b UCBxIE register and bits of \b UCBxIFG register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process. +// +//***************************************************************************** +extern bool EUSCI_B_I2C_masterSendSingleByteWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout); + +//***************************************************************************** +// +//! \brief Starts multi-byte transmission from Master to Slave +//! +//! This function is used by the master module to start a multi byte +//! transaction. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the first data byte to be transmitted +//! +//! Modified bits of \b UCBxTXBUF register, bits of \b UCBxCTLW0 register, bits +//! of \b UCBxIE register and bits of \b UCBxIFG register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_B_I2C_masterSendMultiByteStart(uint16_t baseAddress, + uint8_t txData); + +//***************************************************************************** +// +//! \brief Starts multi-byte transmission from Master to Slave with timeout +//! +//! This function is used by the master module to start a multi byte +//! transaction. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the first data byte to be transmitted +//! \param timeout is the amount of time to wait until giving up +//! +//! Modified bits of \b UCBxTXBUF register, bits of \b UCBxCTLW0 register, bits +//! of \b UCBxIE register and bits of \b UCBxIFG register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process. +// +//***************************************************************************** +extern bool EUSCI_B_I2C_masterSendMultiByteStartWithTimeout( + uint16_t baseAddress, + uint8_t txData, + uint32_t timeout); + +//***************************************************************************** +// +//! \brief Continues multi-byte transmission from Master to Slave +//! +//! This function is used by the Master module continue each byte of a multi- +//! byte transmission. This function transmits each data byte of a multi-byte +//! transmission to the slave. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the next data byte to be transmitted +//! +//! Modified bits of \b UCBxTXBUF register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_B_I2C_masterSendMultiByteNext(uint16_t baseAddress, + uint8_t txData); + +//***************************************************************************** +// +//! \brief Continues multi-byte transmission from Master to Slave with timeout +//! +//! This function is used by the Master module continue each byte of a multi- +//! byte transmission. This function transmits each data byte of a multi-byte +//! transmission to the slave. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the next data byte to be transmitted +//! \param timeout is the amount of time to wait until giving up +//! +//! Modified bits of \b UCBxTXBUF register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process. +// +//***************************************************************************** +extern bool EUSCI_B_I2C_masterSendMultiByteNextWithTimeout(uint16_t baseAddress, + uint8_t txData, + uint32_t timeout); + +//***************************************************************************** +// +//! \brief Finishes multi-byte transmission from Master to Slave +//! +//! This function is used by the Master module to send the last byte and STOP. +//! This function transmits the last data byte of a multi-byte transmission to +//! the slave and then sends a stop. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the last data byte to be transmitted in a multi-byte +//! transmission +//! +//! Modified bits of \b UCBxTXBUF register and bits of \b UCBxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_B_I2C_masterSendMultiByteFinish(uint16_t baseAddress, + uint8_t txData); + +//***************************************************************************** +// +//! \brief Finishes multi-byte transmission from Master to Slave with timeout +//! +//! This function is used by the Master module to send the last byte and STOP. +//! This function transmits the last data byte of a multi-byte transmission to +//! the slave and then sends a stop. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is the last data byte to be transmitted in a multi-byte +//! transmission +//! \param timeout is the amount of time to wait until giving up +//! +//! Modified bits of \b UCBxTXBUF register and bits of \b UCBxCTLW0 register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process. +// +//***************************************************************************** +extern bool EUSCI_B_I2C_masterSendMultiByteFinishWithTimeout( + uint16_t baseAddress, + uint8_t txData, + uint32_t timeout); + +//***************************************************************************** +// +//! \brief This function is used by the Master module to initiate START +//! +//! This function is used by the Master module to initiate START +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! Modified bits are \b UCTXSTT of \b UCBxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_B_I2C_masterSendStart(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Send STOP byte at the end of a multi-byte transmission from Master +//! to Slave +//! +//! This function is used by the Master module send STOP at the end of a multi- +//! byte transmission. This function sends a stop after current transmission is +//! complete. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! Modified bits are \b UCTXSTP of \b UCBxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_B_I2C_masterSendMultiByteStop(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Send STOP byte at the end of a multi-byte transmission from Master +//! to Slave with timeout +//! +//! This function is used by the Master module send STOP at the end of a multi- +//! byte transmission. This function sends a stop after current transmission is +//! complete. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param timeout is the amount of time to wait until giving up +//! +//! Modified bits are \b UCTXSTP of \b UCBxCTLW0 register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the transmission process. +// +//***************************************************************************** +extern bool EUSCI_B_I2C_masterSendMultiByteStopWithTimeout(uint16_t baseAddress, + uint32_t timeout); + +//***************************************************************************** +// +//! \brief Starts reception at the Master end +//! +//! This function is used by the Master module initiate reception of a single +//! byte. This function sends a start. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! Modified bits are \b UCTXSTT of \b UCBxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_B_I2C_masterReceiveStart(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Starts multi-byte reception at the Master end one byte at a time +//! +//! This function is used by the Master module to receive each byte of a multi- +//! byte reception. This function reads currently received byte. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! \return Received byte at Master end. +// +//***************************************************************************** +extern uint8_t EUSCI_B_I2C_masterReceiveMultiByteNext(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Finishes multi-byte reception at the Master end +//! +//! This function is used by the Master module to initiate completion of a +//! multi-byte reception. This function receives the current byte and initiates +//! the STOP from master to slave. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! Modified bits are \b UCTXSTP of \b UCBxCTLW0 register. +//! +//! \return Received byte at Master end. +// +//***************************************************************************** +extern uint8_t EUSCI_B_I2C_masterReceiveMultiByteFinish(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Finishes multi-byte reception at the Master end with timeout +//! +//! This function is used by the Master module to initiate completion of a +//! multi-byte reception. This function receives the current byte and initiates +//! the STOP from master to slave. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! \param txData is a pointer to the location to store the received byte at +//! master end +//! \param timeout is the amount of time to wait until giving up +//! +//! Modified bits are \b UCTXSTP of \b UCBxCTLW0 register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of the reception process +// +//***************************************************************************** +extern bool EUSCI_B_I2C_masterReceiveMultiByteFinishWithTimeout( + uint16_t baseAddress, + uint8_t *txData, + uint32_t timeout); + +//***************************************************************************** +// +//! \brief Sends the STOP at the end of a multi-byte reception at the Master +//! end +//! +//! This function is used by the Master module to initiate STOP +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! Modified bits are \b UCTXSTP of \b UCBxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_B_I2C_masterReceiveMultiByteStop(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Enables Multi Master Mode +//! +//! At the end of this function, the I2C module is still disabled till +//! EUSCI_B_I2C_enable is invoked +//! +//! \param baseAddress is the base address of the I2C module. +//! +//! Modified bits are \b UCSWRST and \b UCMM of \b UCBxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_B_I2C_enableMultiMasterMode(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Disables Multi Master Mode +//! +//! At the end of this function, the I2C module is still disabled till +//! EUSCI_B_I2C_enable is invoked +//! +//! \param baseAddress is the base address of the I2C module. +//! +//! Modified bits are \b UCSWRST and \b UCMM of \b UCBxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_B_I2C_disableMultiMasterMode(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief receives a byte that has been sent to the I2C Master Module. +//! +//! This function reads a byte of data from the I2C receive data Register. +//! +//! \param baseAddress is the base address of the I2C Master module. +//! +//! \return Returns the byte received from by the I2C module, cast as an +//! uint8_t. +// +//***************************************************************************** +extern uint8_t EUSCI_B_I2C_masterReceiveSingle(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Returns the address of the RX Buffer of the I2C for the DMA module. +//! +//! Returns the address of the I2C RX Buffer. This can be used in conjunction +//! with the DMA to store the received data directly to memory. +//! +//! \param baseAddress is the base address of the I2C module. +//! +//! \return The address of the I2C RX Buffer +// +//***************************************************************************** +extern uint32_t EUSCI_B_I2C_getReceiveBufferAddress(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Returns the address of the TX Buffer of the I2C for the DMA module. +//! +//! Returns the address of the I2C TX Buffer. This can be used in conjunction +//! with the DMA to obtain transmitted data directly from memory. +//! +//! \param baseAddress is the base address of the I2C module. +//! +//! \return The address of the I2C TX Buffer +// +//***************************************************************************** +extern uint32_t EUSCI_B_I2C_getTransmitBufferAddress(uint16_t baseAddress); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_EUSCI_B_I2C_H__ diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/eusci_b_spi.c b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/eusci_b_spi.c new file mode 100644 index 000000000..a96aeee30 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/eusci_b_spi.c @@ -0,0 +1,220 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// eusci_b_spi.c - Driver for the eusci_b_spi Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup eusci_b_spi_api eusci_b_spi +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_EUSCI_Bx__ +#include "eusci_b_spi.h" + +#include + +void EUSCI_B_SPI_initMaster(uint16_t baseAddress, + EUSCI_B_SPI_initMasterParam *param) +{ + //Disable the USCI Module + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST; + + //Reset OFS_UCBxCTLW0 values + HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCCKPH + UCCKPL + UC7BIT + UCMSB + + UCMST + UCMODE_3 + UCSYNC); + + //Reset OFS_UCBxCTLW0 values + HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCSSEL_3); + + //Select Clock + HWREG16(baseAddress + OFS_UCBxCTLW0) |= param->selectClockSource; + + HWREG16(baseAddress + OFS_UCBxBRW) = + (uint16_t)(param->clockSourceFrequency / param->desiredSpiClock); + + /* + * Configure as SPI master mode. + * Clock phase select, polarity, msb + * UCMST = Master mode + * UCSYNC = Synchronous mode + * UCMODE_0 = 3-pin SPI + */ + HWREG16(baseAddress + OFS_UCBxCTLW0) |= ( + param->msbFirst + + param->clockPhase + + param->clockPolarity + + UCMST + + UCSYNC + + param->spiMode + ); +} + +void EUSCI_B_SPI_select4PinFunctionality(uint16_t baseAddress, + uint8_t select4PinFunctionality) +{ + HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~UCSTEM; + HWREG16(baseAddress + OFS_UCBxCTLW0) |= select4PinFunctionality; +} + +void EUSCI_B_SPI_changeMasterClock(uint16_t baseAddress, + EUSCI_B_SPI_changeMasterClockParam *param) +{ + //Disable the USCI Module + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST; + + HWREG16(baseAddress + OFS_UCBxBRW) = + (uint16_t)(param->clockSourceFrequency / param->desiredSpiClock); + + //Reset the UCSWRST bit to enable the USCI Module + HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCSWRST); +} + +void EUSCI_B_SPI_initSlave(uint16_t baseAddress, + EUSCI_B_SPI_initSlaveParam *param) +{ + //Disable USCI Module + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST; + + //Reset OFS_UCBxCTLW0 register + HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCMSB + + UC7BIT + + UCMST + + UCCKPL + + UCCKPH + + UCMODE_3 + ); + + //Clock polarity, phase select, msbFirst, SYNC, Mode0 + HWREG16(baseAddress + OFS_UCBxCTLW0) |= (param->clockPhase + + param->clockPolarity + + param->msbFirst + + UCSYNC + + param->spiMode + ); +} + +void EUSCI_B_SPI_changeClockPhasePolarity(uint16_t baseAddress, + uint16_t clockPhase, + uint16_t clockPolarity) +{ + //Disable the USCI Module + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST; + + HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCCKPH + UCCKPL); + + HWREG16(baseAddress + OFS_UCBxCTLW0) |= ( + clockPhase + + clockPolarity + ); + + //Reset the UCSWRST bit to enable the USCI Module + HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCSWRST); +} + +void EUSCI_B_SPI_transmitData(uint16_t baseAddress, + uint8_t transmitData) +{ + HWREG16(baseAddress + OFS_UCBxTXBUF) = transmitData; +} + +uint8_t EUSCI_B_SPI_receiveData(uint16_t baseAddress) +{ + return (HWREG16(baseAddress + OFS_UCBxRXBUF)); +} + +void EUSCI_B_SPI_enableInterrupt(uint16_t baseAddress, + uint8_t mask) +{ + HWREG16(baseAddress + OFS_UCBxIE) |= mask; +} + +void EUSCI_B_SPI_disableInterrupt(uint16_t baseAddress, + uint8_t mask) +{ + HWREG16(baseAddress + OFS_UCBxIE) &= ~mask; +} + +uint8_t EUSCI_B_SPI_getInterruptStatus(uint16_t baseAddress, + uint8_t mask) +{ + return (HWREG16(baseAddress + OFS_UCBxIFG) & mask); +} + +void EUSCI_B_SPI_clearInterrupt(uint16_t baseAddress, + uint8_t mask) +{ + HWREG16(baseAddress + OFS_UCBxIFG) &= ~mask; +} + +void EUSCI_B_SPI_enable(uint16_t baseAddress) +{ + //Reset the UCSWRST bit to enable the USCI Module + HWREG16(baseAddress + OFS_UCBxCTLW0) &= ~(UCSWRST); +} + +void EUSCI_B_SPI_disable(uint16_t baseAddress) +{ + //Set the UCSWRST bit to disable the USCI Module + HWREG16(baseAddress + OFS_UCBxCTLW0) |= UCSWRST; +} + +uint32_t EUSCI_B_SPI_getReceiveBufferAddress(uint16_t baseAddress) +{ + return (baseAddress + OFS_UCBxRXBUF); +} + +uint32_t EUSCI_B_SPI_getTransmitBufferAddress(uint16_t baseAddress) +{ + return (baseAddress + OFS_UCBxTXBUF); +} + +uint16_t EUSCI_B_SPI_isBusy(uint16_t baseAddress) +{ + //Return the bus busy status. + return (HWREG16(baseAddress + OFS_UCBxSTATW) & UCBUSY); +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for eusci_b_spi_api +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/eusci_b_spi.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/eusci_b_spi.h new file mode 100644 index 000000000..398777c69 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/eusci_b_spi.h @@ -0,0 +1,527 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// eusci_b_spi.h - Driver for the EUSCI_B_SPI Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_EUSCI_B_SPI_H__ +#define __MSP430WARE_EUSCI_B_SPI_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_EUSCI_Bx__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "inc/hw_regaccess.h" +//***************************************************************************** +// +//! \brief Used in the EUSCI_B_SPI_initMaster() function as the param +//! parameter. +// +//***************************************************************************** +typedef struct EUSCI_B_SPI_initMasterParam +{ + //! Selects Clock source. + //! \n Valid values are: + //! - \b EUSCI_B_SPI_CLOCKSOURCE_ACLK + //! - \b EUSCI_B_SPI_CLOCKSOURCE_SMCLK + uint8_t selectClockSource; + //! Is the frequency of the selected clock source + uint32_t clockSourceFrequency; + //! Is the desired clock rate for SPI communication + uint32_t desiredSpiClock; + //! Controls the direction of the receive and transmit shift register. + //! \n Valid values are: + //! - \b EUSCI_B_SPI_MSB_FIRST + //! - \b EUSCI_B_SPI_LSB_FIRST [Default] + uint16_t msbFirst; + //! Is clock phase select. + //! \n Valid values are: + //! - \b EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT [Default] + //! - \b EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT + uint16_t clockPhase; + //! Is clock polarity select + //! \n Valid values are: + //! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH + //! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default] + uint16_t clockPolarity; + //! Is SPI mode select + //! \n Valid values are: + //! - \b EUSCI_B_SPI_3PIN + //! - \b EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH + //! - \b EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW + uint16_t spiMode; +} EUSCI_B_SPI_initMasterParam; + +//***************************************************************************** +// +//! \brief Used in the EUSCI_B_SPI_initSlave() function as the param parameter. +// +//***************************************************************************** +typedef struct EUSCI_B_SPI_initSlaveParam +{ + //! Controls the direction of the receive and transmit shift register. + //! \n Valid values are: + //! - \b EUSCI_B_SPI_MSB_FIRST + //! - \b EUSCI_B_SPI_LSB_FIRST [Default] + uint16_t msbFirst; + //! Is clock phase select. + //! \n Valid values are: + //! - \b EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT [Default] + //! - \b EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT + uint16_t clockPhase; + //! Is clock polarity select + //! \n Valid values are: + //! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH + //! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default] + uint16_t clockPolarity; + //! Is SPI mode select + //! \n Valid values are: + //! - \b EUSCI_B_SPI_3PIN + //! - \b EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH + //! - \b EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW + uint16_t spiMode; +} EUSCI_B_SPI_initSlaveParam; + +//***************************************************************************** +// +//! \brief Used in the EUSCI_B_SPI_changeMasterClock() function as the param +//! parameter. +// +//***************************************************************************** +typedef struct EUSCI_B_SPI_changeMasterClockParam +{ + //! Is the frequency of the selected clock source + uint32_t clockSourceFrequency; + //! Is the desired clock rate for SPI communication + uint32_t desiredSpiClock; +} EUSCI_B_SPI_changeMasterClockParam; + +//***************************************************************************** +// +// The following are values that can be passed to the clockPhase parameter for +// functions: EUSCI_B_SPI_changeClockPhasePolarity(); the param parameter for +// functions: EUSCI_B_SPI_initMaster(), and EUSCI_B_SPI_initSlave(). +// +//***************************************************************************** +#define EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT 0x00 +#define EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT UCCKPH + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: EUSCI_B_SPI_initMaster(), and EUSCI_B_SPI_initSlave(). +// +//***************************************************************************** +#define EUSCI_B_SPI_MSB_FIRST UCMSB +#define EUSCI_B_SPI_LSB_FIRST 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: EUSCI_B_SPI_initMaster(), and EUSCI_B_SPI_initSlave(); the +// clockPolarity parameter for functions: +// EUSCI_B_SPI_changeClockPhasePolarity(). +// +//***************************************************************************** +#define EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH UCCKPL +#define EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: EUSCI_B_SPI_initMaster(). +// +//***************************************************************************** +#define EUSCI_B_SPI_CLOCKSOURCE_ACLK UCSSEL__ACLK +#define EUSCI_B_SPI_CLOCKSOURCE_SMCLK UCSSEL__SMCLK + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: EUSCI_B_SPI_initMaster(), and EUSCI_B_SPI_initSlave(). +// +//***************************************************************************** +#define EUSCI_B_SPI_3PIN UCMODE_0 +#define EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH UCMODE_1 +#define EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW UCMODE_2 + +//***************************************************************************** +// +// The following are values that can be passed to the select4PinFunctionality +// parameter for functions: EUSCI_B_SPI_select4PinFunctionality(). +// +//***************************************************************************** +#define EUSCI_B_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS 0x00 +#define EUSCI_B_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE UCSTEM + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: EUSCI_B_SPI_enableInterrupt(), EUSCI_B_SPI_disableInterrupt(), +// EUSCI_B_SPI_getInterruptStatus(), and EUSCI_B_SPI_clearInterrupt() as well +// as returned by the EUSCI_B_SPI_getInterruptStatus() function. +// +//***************************************************************************** +#define EUSCI_B_SPI_TRANSMIT_INTERRUPT UCTXIE +#define EUSCI_B_SPI_RECEIVE_INTERRUPT UCRXIE + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the EUSCI_B_SPI_isBusy() function. +// +//***************************************************************************** +#define EUSCI_B_SPI_BUSY UCBUSY +#define EUSCI_B_SPI_NOT_BUSY 0x00 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Initializes the SPI Master block. +//! +//! Upon successful initialization of the SPI master block, this function will +//! have set the bus speed for the master, but the SPI Master block still +//! remains disabled and must be enabled with EUSCI_B_SPI_enable() +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI Master module. +//! \param param is the pointer to struct for master initialization. +//! +//! Modified bits are \b UCCKPH, \b UCCKPL, \b UC7BIT, \b UCMSB, \b UCSSELx and +//! \b UCSWRST of \b UCAxCTLW0 register. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +extern void EUSCI_B_SPI_initMaster(uint16_t baseAddress, + EUSCI_B_SPI_initMasterParam *param); + +//***************************************************************************** +// +//! \brief Selects 4Pin Functionality +//! +//! This function should be invoked only in 4-wire mode. Invoking this function +//! has no effect in 3-wire mode. +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI module. +//! \param select4PinFunctionality selects 4 pin functionality +//! Valid values are: +//! - \b EUSCI_B_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS +//! - \b EUSCI_B_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE +//! +//! Modified bits are \b UCSTEM of \b UCAxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_B_SPI_select4PinFunctionality(uint16_t baseAddress, + uint8_t select4PinFunctionality); + +//***************************************************************************** +// +//! \brief Initializes the SPI Master clock. At the end of this function call, +//! SPI module is left enabled. +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI module. +//! \param param is the pointer to struct for master clock setting. +//! +//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_B_SPI_changeMasterClock(uint16_t baseAddress, + EUSCI_B_SPI_changeMasterClockParam *param); + +//***************************************************************************** +// +//! \brief Initializes the SPI Slave block. +//! +//! Upon successful initialization of the SPI slave block, this function will +//! have initialized the slave block, but the SPI Slave block still remains +//! disabled and must be enabled with EUSCI_B_SPI_enable() +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI Slave module. +//! \param param is the pointer to struct for slave initialization. +//! +//! Modified bits are \b UCMSB, \b UCMST, \b UC7BIT, \b UCCKPL, \b UCCKPH, \b +//! UCMODE and \b UCSWRST of \b UCAxCTLW0 register. +//! +//! \return STATUS_SUCCESS +// +//***************************************************************************** +extern void EUSCI_B_SPI_initSlave(uint16_t baseAddress, + EUSCI_B_SPI_initSlaveParam *param); + +//***************************************************************************** +// +//! \brief Changes the SPI clock phase and polarity. At the end of this +//! function call, SPI module is left enabled. +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI module. +//! \param clockPhase is clock phase select. +//! Valid values are: +//! - \b EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT +//! [Default] +//! - \b EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT +//! \param clockPolarity is clock polarity select +//! Valid values are: +//! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH +//! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default] +//! +//! Modified bits are \b UCCKPL, \b UCCKPH and \b UCSWRST of \b UCAxCTLW0 +//! register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_B_SPI_changeClockPhasePolarity(uint16_t baseAddress, + uint16_t clockPhase, + uint16_t clockPolarity); + +//***************************************************************************** +// +//! \brief Transmits a byte from the SPI Module. +//! +//! This function will place the supplied data into SPI transmit data register +//! to start transmission. +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI module. +//! \param transmitData data to be transmitted from the SPI module +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_B_SPI_transmitData(uint16_t baseAddress, + uint8_t transmitData); + +//***************************************************************************** +// +//! \brief Receives a byte that has been sent to the SPI Module. +//! +//! This function reads a byte of data from the SPI receive data Register. +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI module. +//! +//! \return Returns the byte received from by the SPI module, cast as an +//! uint8_t. +// +//***************************************************************************** +extern uint8_t EUSCI_B_SPI_receiveData(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Enables individual SPI interrupt sources. +//! +//! Enables the indicated SPI interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. Does not clear interrupt flags. +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI module. +//! \param mask is the bit mask of the interrupt sources to be enabled. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT +//! - \b EUSCI_B_SPI_RECEIVE_INTERRUPT +//! +//! Modified bits of \b UCAxIFG register and bits of \b UCAxIE register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_B_SPI_enableInterrupt(uint16_t baseAddress, + uint8_t mask); + +//***************************************************************************** +// +//! \brief Disables individual SPI interrupt sources. +//! +//! Disables the indicated SPI interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI module. +//! \param mask is the bit mask of the interrupt sources to be disabled. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT +//! - \b EUSCI_B_SPI_RECEIVE_INTERRUPT +//! +//! Modified bits of \b UCAxIE register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_B_SPI_disableInterrupt(uint16_t baseAddress, + uint8_t mask); + +//***************************************************************************** +// +//! \brief Gets the current SPI interrupt status. +//! +//! This returns the interrupt status for the SPI module based on which flag is +//! passed. +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI module. +//! \param mask is the masked interrupt flag status to be returned. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT +//! - \b EUSCI_B_SPI_RECEIVE_INTERRUPT +//! +//! \return Logical OR of any of the following: +//! - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT +//! - \b EUSCI_B_SPI_RECEIVE_INTERRUPT +//! \n indicating the status of the masked interrupts +// +//***************************************************************************** +extern uint8_t EUSCI_B_SPI_getInterruptStatus(uint16_t baseAddress, + uint8_t mask); + +//***************************************************************************** +// +//! \brief Clears the selected SPI interrupt status flag. +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI module. +//! \param mask is the masked interrupt flag to be cleared. +//! Mask value is the logical OR of any of the following: +//! - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT +//! - \b EUSCI_B_SPI_RECEIVE_INTERRUPT +//! +//! Modified bits of \b UCAxIFG register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_B_SPI_clearInterrupt(uint16_t baseAddress, + uint8_t mask); + +//***************************************************************************** +// +//! \brief Enables the SPI block. +//! +//! This will enable operation of the SPI block. +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI module. +//! +//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_B_SPI_enable(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Disables the SPI block. +//! +//! This will disable operation of the SPI block. +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI module. +//! +//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register. +//! +//! \return None +// +//***************************************************************************** +extern void EUSCI_B_SPI_disable(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Returns the address of the RX Buffer of the SPI for the DMA module. +//! +//! Returns the address of the SPI RX Buffer. This can be used in conjunction +//! with the DMA to store the received data directly to memory. +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI module. +//! +//! \return the address of the RX Buffer +// +//***************************************************************************** +extern uint32_t EUSCI_B_SPI_getReceiveBufferAddress(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Returns the address of the TX Buffer of the SPI for the DMA module. +//! +//! Returns the address of the SPI TX Buffer. This can be used in conjunction +//! with the DMA to obtain transmitted data directly from memory. +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI module. +//! +//! \return the address of the TX Buffer +// +//***************************************************************************** +extern uint32_t EUSCI_B_SPI_getTransmitBufferAddress(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Indicates whether or not the SPI bus is busy. +//! +//! This function returns an indication of whether or not the SPI bus is +//! busy.This function checks the status of the bus via UCBBUSY bit +//! +//! \param baseAddress is the base address of the EUSCI_B_SPI module. +//! +//! \return One of the following: +//! - \b EUSCI_B_SPI_BUSY +//! - \b EUSCI_B_SPI_NOT_BUSY +//! \n indicating if the EUSCI_B_SPI is busy +// +//***************************************************************************** +extern uint16_t EUSCI_B_SPI_isBusy(uint16_t baseAddress); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_EUSCI_B_SPI_H__ diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/framctl.c b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/framctl.c new file mode 100644 index 000000000..78165d84b --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/framctl.c @@ -0,0 +1,157 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// framctl.c - Driver for the framctl Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup framctl_api framctl +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_FRAM__ +#include "framctl.h" + +#include + +void FRAMCtl_write8(uint8_t *dataPtr, + uint8_t *framPtr, + uint16_t numberOfBytes) +{ + while(numberOfBytes > 0) + { + //Write to Fram + *framPtr++ = *dataPtr++; + numberOfBytes--; + } +} + +void FRAMCtl_write16(uint16_t *dataPtr, + uint16_t *framPtr, + uint16_t numberOfWords) +{ + while(numberOfWords > 0) + { + //Write to Fram + *framPtr++ = *dataPtr++; + numberOfWords--; + } +} + +void FRAMCtl_write32(uint32_t *dataPtr, + uint32_t *framPtr, + uint16_t count) +{ + while(count > 0) + { + //Write to Fram + *framPtr++ = *dataPtr++; + count--; + } +} + +void FRAMCtl_fillMemory32(uint32_t value, + uint32_t *framPtr, + uint16_t count) +{ + while(count > 0) + { + //Write to Fram + *framPtr++ = value; + count--; + } +} + +void FRAMCtl_enableInterrupt(uint8_t interruptMask) +{ + uint8_t waitSelection; + + waitSelection = (HWREG8(FRAM_BASE + OFS_FRCTL0) & 0xFF); + // Clear lock in FRAM control registers + HWREG16(FRAM_BASE + OFS_FRCTL0) = FWPW | waitSelection; + + // Enable user selected interrupt sources + HWREG16(FRAM_BASE + OFS_GCCTL0) |= interruptMask; +} + +uint8_t FRAMCtl_getInterruptStatus(uint16_t interruptFlagMask) +{ + return (HWREG16(FRAM_BASE + OFS_GCCTL1) & interruptFlagMask); +} + +void FRAMCtl_disableInterrupt(uint16_t interruptMask) +{ + uint8_t waitSelection; + + waitSelection = (HWREG8(FRAM_BASE + OFS_FRCTL0) & 0xFF); + //Clear lock in FRAM control registers + HWREG16(FRAM_BASE + OFS_FRCTL0) = FWPW | waitSelection; + + HWREG16(FRAM_BASE + OFS_GCCTL0) &= ~(interruptMask); +} + +void FRAMCtl_configureWaitStateControl(uint8_t waitState) +{ + // Clear lock in FRAM control registers + HWREG16(FRAM_BASE + OFS_FRCTL0) = FWPW; + + HWREG8(FRAM_BASE + OFS_FRCTL0_L) &= ~NWAITS_7; + HWREG8(FRAM_BASE + OFS_FRCTL0_L) |= (waitState); +} + +void FRAMCtl_delayPowerUpFromLPM(uint8_t delayStatus) +{ + uint8_t waitSelection; + + waitSelection = (HWREG8(FRAM_BASE + OFS_FRCTL0) & 0xFF); + + // Clear lock in FRAM control registers + HWREG16(FRAM_BASE + OFS_FRCTL0) = FWPW | waitSelection; + + HWREG8(FRAM_BASE + OFS_GCCTL0_L) &= ~0x02; + HWREG8(FRAM_BASE + OFS_GCCTL0_L) |= delayStatus; +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for framctl_api +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/framctl.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/framctl.h new file mode 100644 index 000000000..0742b3402 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/framctl.h @@ -0,0 +1,303 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// framctl.h - Driver for the FRAMCTL Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_FRAMCTL_H__ +#define __MSP430WARE_FRAMCTL_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_FRAM__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the interruptMask parameter +// for functions: FRAMCtl_enableInterrupt(), and FRAMCtl_disableInterrupt(). +// +//***************************************************************************** +#define FRAMCTL_PUC_ON_UNCORRECTABLE_BIT UBDRSTEN +#define FRAMCTL_UNCORRECTABLE_BIT_INTERRUPT UBDIE +#define FRAMCTL_CORRECTABLE_BIT_INTERRUPT CBDIE + +//***************************************************************************** +// +// The following are values that can be passed to the interruptFlagMask +// parameter for functions: FRAMCtl_getInterruptStatus() as well as returned by +// the FRAMCtl_getInterruptStatus() function. +// +//***************************************************************************** +#define FRAMCTL_ACCESS_TIME_ERROR_FLAG ACCTEIFG +#define FRAMCTL_UNCORRECTABLE_BIT_FLAG UBDIFG +#define FRAMCTL_CORRECTABLE_BIT_FLAG CBDIFG + +//***************************************************************************** +// +// The following are values that can be passed to the waitState parameter for +// functions: FRAMCtl_configureWaitStateControl(). +// +//***************************************************************************** +#define FRAMCTL_ACCESS_TIME_CYCLES_0 NWAITS_0 +#define FRAMCTL_ACCESS_TIME_CYCLES_1 NWAITS_1 +#define FRAMCTL_ACCESS_TIME_CYCLES_2 NWAITS_2 +#define FRAMCTL_ACCESS_TIME_CYCLES_3 NWAITS_3 +#define FRAMCTL_ACCESS_TIME_CYCLES_4 NWAITS_4 +#define FRAMCTL_ACCESS_TIME_CYCLES_5 NWAITS_5 +#define FRAMCTL_ACCESS_TIME_CYCLES_6 NWAITS_6 +#define FRAMCTL_ACCESS_TIME_CYCLES_7 NWAITS_7 + +//***************************************************************************** +// +// The following are values that can be passed to the delayStatus parameter for +// functions: FRAMCtl_delayPowerUpFromLPM(). +// +//***************************************************************************** +#define FRAMCTL_DELAY_FROM_LPM_ENABLE 0x00 +#define FRAMCTL_DELAY_FROM_LPM_DISABLE 0x02 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Write data into the fram memory in byte format. +//! +//! \param dataPtr is the pointer to the data to be written +//! \param framPtr is the pointer into which to write the data +//! \param numberOfBytes is the number of bytes to be written +//! +//! \return None +// +//***************************************************************************** +extern void FRAMCtl_write8(uint8_t *dataPtr, + uint8_t *framPtr, + uint16_t numberOfBytes); + +//***************************************************************************** +// +//! \brief Write data into the fram memory in word format. +//! +//! \param dataPtr is the pointer to the data to be written +//! \param framPtr is the pointer into which to write the data +//! \param numberOfWords is the number of words to be written +//! +//! \return None +// +//***************************************************************************** +extern void FRAMCtl_write16(uint16_t *dataPtr, + uint16_t *framPtr, + uint16_t numberOfWords); + +//***************************************************************************** +// +//! \brief Write data into the fram memory in long format, pass by reference +//! +//! \param dataPtr is the pointer to the data to be written +//! \param framPtr is the pointer into which to write the data +//! \param count is the number of 32 bit words to be written +//! +//! \return None +// +//***************************************************************************** +extern void FRAMCtl_write32(uint32_t *dataPtr, + uint32_t *framPtr, + uint16_t count); + +//***************************************************************************** +// +//! \brief Write data into the fram memory in long format, pass by value +//! +//! \param value is the value to written to FRAMCTL memory +//! \param framPtr is the pointer into which to write the data +//! \param count is the number of 32 bit addresses to fill +//! +//! \return None +// +//***************************************************************************** +extern void FRAMCtl_fillMemory32(uint32_t value, + uint32_t *framPtr, + uint16_t count); + +//***************************************************************************** +// +//! \brief Enables selected FRAMCtl interrupt sources. +//! +//! Enables the indicated FRAMCtl interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. Does not clear interrupt flags. +//! +//! \param interruptMask is the bit mask of the memory buffer interrupt sources +//! to be disabled. +//! Mask value is the logical OR of any of the following: +//! - \b FRAMCTL_PUC_ON_UNCORRECTABLE_BIT - Enable PUC reset if FRAMCtl +//! uncorrectable bit error detected. +//! - \b FRAMCTL_UNCORRECTABLE_BIT_INTERRUPT - Interrupts when an +//! uncorrectable bit error is detected. +//! - \b FRAMCTL_CORRECTABLE_BIT_INTERRUPT - Interrupts when a +//! correctable bit error is detected. +//! +//! Modified bits of \b GCCTL0 register and bits of \b FRCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void FRAMCtl_enableInterrupt(uint8_t interruptMask); + +//***************************************************************************** +// +//! \brief Returns the status of the selected FRAMCtl interrupt flags. +//! +//! \param interruptFlagMask is a bit mask of the interrupt flags status to be +//! returned. +//! Mask value is the logical OR of any of the following: +//! - \b FRAMCTL_ACCESS_TIME_ERROR_FLAG - Interrupt flag is set if a +//! wrong setting for NPRECHG and NACCESS is set and FRAMCtl access +//! time is not hold. +//! - \b FRAMCTL_UNCORRECTABLE_BIT_FLAG - Interrupt flag is set if an +//! uncorrectable bit error has been detected in the FRAMCtl memory +//! error detection logic. +//! - \b FRAMCTL_CORRECTABLE_BIT_FLAG - Interrupt flag is set if a +//! correctable bit error has been detected and corrected in the +//! FRAMCtl memory error detection logic. +//! +//! \return Logical OR of any of the following: +//! - \b FRAMCtl_ACCESS_TIME_ERROR_FLAG Interrupt flag is set if a +//! wrong setting for NPRECHG and NACCESS is set and FRAMCtl access +//! time is not hold. +//! - \b FRAMCtl_UNCORRECTABLE_BIT_FLAG Interrupt flag is set if an +//! uncorrectable bit error has been detected in the FRAMCtl memory +//! error detection logic. +//! - \b FRAMCtl_CORRECTABLE_BIT_FLAG Interrupt flag is set if a +//! correctable bit error has been detected and corrected in the +//! FRAMCtl memory error detection logic. +//! \n indicating the status of the masked flags +// +//***************************************************************************** +extern uint8_t FRAMCtl_getInterruptStatus(uint16_t interruptFlagMask); + +//***************************************************************************** +// +//! \brief Disables selected FRAMCtl interrupt sources. +//! +//! Disables the indicated FRAMCtl interrupt sources. Only the sources that +//! are enabled can be reflected to the processor interrupt; disabled sources +//! have no effect on the processor. +//! +//! \param interruptMask is the bit mask of the memory buffer interrupt sources +//! to be disabled. +//! Mask value is the logical OR of any of the following: +//! - \b FRAMCTL_PUC_ON_UNCORRECTABLE_BIT - Enable PUC reset if FRAMCtl +//! uncorrectable bit error detected. +//! - \b FRAMCTL_UNCORRECTABLE_BIT_INTERRUPT - Interrupts when an +//! uncorrectable bit error is detected. +//! - \b FRAMCTL_CORRECTABLE_BIT_INTERRUPT - Interrupts when a +//! correctable bit error is detected. +//! +//! \return None +// +//***************************************************************************** +extern void FRAMCtl_disableInterrupt(uint16_t interruptMask); + +//***************************************************************************** +// +//! \brief Configures the access time of the FRAMCtl module +//! +//! Configures the access time of the FRAMCtl module. +//! +//! \param waitState defines the number of CPU cycles required for access time +//! defined in the datasheet +//! Valid values are: +//! - \b FRAMCTL_ACCESS_TIME_CYCLES_0 +//! - \b FRAMCTL_ACCESS_TIME_CYCLES_1 +//! - \b FRAMCTL_ACCESS_TIME_CYCLES_2 +//! - \b FRAMCTL_ACCESS_TIME_CYCLES_3 +//! - \b FRAMCTL_ACCESS_TIME_CYCLES_4 +//! - \b FRAMCTL_ACCESS_TIME_CYCLES_5 +//! - \b FRAMCTL_ACCESS_TIME_CYCLES_6 +//! - \b FRAMCTL_ACCESS_TIME_CYCLES_7 +//! +//! Modified bits are \b NWAITS of \b GCCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void FRAMCtl_configureWaitStateControl(uint8_t waitState); + +//***************************************************************************** +// +//! \brief Configures when the FRAMCtl module will power up after LPM exit +//! +//! Configures when the FRAMCtl module will power up after LPM exit. The module +//! can either wait until the first FRAMCtl access to power up or power up +//! immediately after leaving LPM. If FRAMCtl power is disabled, a memory +//! access will automatically insert wait states to ensure sufficient timing +//! for the FRAMCtl power-up and access. +//! +//! \param delayStatus chooses if FRAMCTL should power up instantly with LPM +//! exit or to wait until first FRAMCTL access after LPM exit +//! Valid values are: +//! - \b FRAMCTL_DELAY_FROM_LPM_ENABLE +//! - \b FRAMCTL_DELAY_FROM_LPM_DISABLE +//! +//! \return None +// +//***************************************************************************** +extern void FRAMCtl_delayPowerUpFromLPM(uint8_t delayStatus); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_FRAMCTL_H__ diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/gpio.c b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/gpio.c new file mode 100644 index 000000000..d87d69032 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/gpio.c @@ -0,0 +1,513 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// gpio.c - Driver for the gpio Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup gpio_api gpio +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#if defined(__MSP430_HAS_PORT1_R__) || defined(__MSP430_HAS_PORT2_R__) || \ + defined(__MSP430_HAS_PORTA_R__) +#include "gpio.h" + +#include + +static const uint16_t GPIO_PORT_TO_BASE[] = { + 0x00, +#if defined(__MSP430_HAS_PORT1_R__) + __MSP430_BASEADDRESS_PORT1_R__, +#elif defined(__MSP430_HAS_PORT1__) + __MSP430_BASEADDRESS_PORT1__, +#else + 0xFFFF, +#endif +#if defined(__MSP430_HAS_PORT2_R__) + __MSP430_BASEADDRESS_PORT2_R__, +#elif defined(__MSP430_HAS_PORT2__) + __MSP430_BASEADDRESS_PORT2__, +#else + 0xFFFF, +#endif +#if defined(__MSP430_HAS_PORT3_R__) + __MSP430_BASEADDRESS_PORT3_R__, +#elif defined(__MSP430_HAS_PORT3__) + __MSP430_BASEADDRESS_PORT3__, +#else + 0xFFFF, +#endif +#if defined(__MSP430_HAS_PORT4_R__) + __MSP430_BASEADDRESS_PORT4_R__, +#elif defined(__MSP430_HAS_PORT4__) + __MSP430_BASEADDRESS_PORT4__, +#else + 0xFFFF, +#endif +#if defined(__MSP430_HAS_PORT5_R__) + __MSP430_BASEADDRESS_PORT5_R__, +#elif defined(__MSP430_HAS_PORT5__) + __MSP430_BASEADDRESS_PORT5__, +#else + 0xFFFF, +#endif +#if defined(__MSP430_HAS_PORT6_R__) + __MSP430_BASEADDRESS_PORT6_R__, +#elif defined(__MSP430_HAS_PORT6__) + __MSP430_BASEADDRESS_PORT6__, +#else + 0xFFFF, +#endif +#if defined(__MSP430_HAS_PORT7_R__) + __MSP430_BASEADDRESS_PORT7_R__, +#elif defined(__MSP430_HAS_PORT7__) + __MSP430_BASEADDRESS_PORT7__, +#else + 0xFFFF, +#endif +#if defined(__MSP430_HAS_PORT8_R__) + __MSP430_BASEADDRESS_PORT8_R__, +#elif defined(__MSP430_HAS_PORT8__) + __MSP430_BASEADDRESS_PORT8__, +#else + 0xFFFF, +#endif +#if defined(__MSP430_HAS_PORT9_R__) + __MSP430_BASEADDRESS_PORT9_R__, +#elif defined(__MSP430_HAS_PORT9__) + __MSP430_BASEADDRESS_PORT9__, +#else + 0xFFFF, +#endif +#if defined(__MSP430_HAS_PORT10_R__) + __MSP430_BASEADDRESS_PORT10_R__, +#elif defined(__MSP430_HAS_PORT10__) + __MSP430_BASEADDRESS_PORT10__, +#else + 0xFFFF, +#endif +#if defined(__MSP430_HAS_PORT11_R__) + __MSP430_BASEADDRESS_PORT11_R__, +#elif defined(__MSP430_HAS_PORT11__) + __MSP430_BASEADDRESS_PORT11__, +#else + 0xFFFF, +#endif + 0xFFFF, +#if defined(__MSP430_HAS_PORTJ_R__) + __MSP430_BASEADDRESS_PORTJ_R__ +#elif defined(__MSP430_HAS_PORTJ__) + __MSP430_BASEADDRESS_PORTJ__ +#else + 0xFFFF +#endif +}; + +void GPIO_setAsOutputPin(uint8_t selectedPort, + uint16_t selectedPins) { + uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; + + #ifndef NDEBUG + if(baseAddress == 0xFFFF) + { + return; + } + #endif + + // Shift by 8 if port is even (upper 8-bits) + if((selectedPort & 1) ^ 1) + { + selectedPins <<= 8; + } + + HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins; + HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins; + HWREG16(baseAddress + OFS_PADIR) |= selectedPins; + + return; +} + +void GPIO_setAsInputPin(uint8_t selectedPort, + uint16_t selectedPins) { + uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; + + #ifndef NDEBUG + if(baseAddress == 0xFFFF) + { + return; + } + #endif + + // Shift by 8 if port is even (upper 8-bits) + if((selectedPort & 1) ^ 1) + { + selectedPins <<= 8; + } + + HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins; + HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins; + HWREG16(baseAddress + OFS_PADIR) &= ~selectedPins; + HWREG16(baseAddress + OFS_PAREN) &= ~selectedPins; +} + +void GPIO_setAsPeripheralModuleFunctionOutputPin(uint8_t selectedPort, + uint16_t selectedPins + , + uint8_t mode) { + uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; + + #ifndef NDEBUG + if(baseAddress == 0xFFFF) + { + return; + } + #endif + + // Shift by 8 if port is even (upper 8-bits) + if((selectedPort & 1) ^ 1) + { + selectedPins <<= 8; + } + + HWREG16(baseAddress + OFS_PADIR) |= selectedPins; + switch(mode) + { + case GPIO_PRIMARY_MODULE_FUNCTION: + HWREG16(baseAddress + OFS_PASEL0) |= selectedPins; + HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins; + break; + case GPIO_SECONDARY_MODULE_FUNCTION: + HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins; + HWREG16(baseAddress + OFS_PASEL1) |= selectedPins; + break; + case GPIO_TERNARY_MODULE_FUNCTION: + HWREG16(baseAddress + OFS_PASEL0) |= selectedPins; + HWREG16(baseAddress + OFS_PASEL1) |= selectedPins; + break; + } +} + +void GPIO_setAsPeripheralModuleFunctionInputPin(uint8_t selectedPort, + uint16_t selectedPins + , + uint8_t mode) { + uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; + + #ifndef NDEBUG + if(baseAddress == 0xFFFF) + { + return; + } + #endif + + // Shift by 8 if port is even (upper 8-bits) + if((selectedPort & 1) ^ 1) + { + selectedPins <<= 8; + } + + HWREG16(baseAddress + OFS_PADIR) &= ~selectedPins; + switch(mode) + { + case GPIO_PRIMARY_MODULE_FUNCTION: + HWREG16(baseAddress + OFS_PASEL0) |= selectedPins; + HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins; + break; + case GPIO_SECONDARY_MODULE_FUNCTION: + HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins; + HWREG16(baseAddress + OFS_PASEL1) |= selectedPins; + break; + case GPIO_TERNARY_MODULE_FUNCTION: + HWREG16(baseAddress + OFS_PASEL0) |= selectedPins; + HWREG16(baseAddress + OFS_PASEL1) |= selectedPins; + break; + } +} + +void GPIO_setOutputHighOnPin(uint8_t selectedPort, + uint16_t selectedPins) { + uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; + + #ifndef NDEBUG + if(baseAddress == 0xFFFF) + { + return; + } + #endif + + // Shift by 8 if port is even (upper 8-bits) + if((selectedPort & 1) ^ 1) + { + selectedPins <<= 8; + } + + HWREG16(baseAddress + OFS_PAOUT) |= selectedPins; +} + +void GPIO_setOutputLowOnPin(uint8_t selectedPort, + uint16_t selectedPins) { + uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; + + #ifndef NDEBUG + if(baseAddress == 0xFFFF) + { + return; + } + #endif + + // Shift by 8 if port is even (upper 8-bits) + if((selectedPort & 1) ^ 1) + { + selectedPins <<= 8; + } + + HWREG16(baseAddress + OFS_PAOUT) &= ~selectedPins; +} + +void GPIO_toggleOutputOnPin(uint8_t selectedPort, + uint16_t selectedPins) { + uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; + + #ifndef NDEBUG + if(baseAddress == 0xFFFF) + { + return; + } + #endif + + // Shift by 8 if port is even (upper 8-bits) + if((selectedPort & 1) ^ 1) + { + selectedPins <<= 8; + } + + HWREG16(baseAddress + OFS_PAOUT) ^= selectedPins; +} + +void GPIO_setAsInputPinWithPullDownResistor(uint8_t selectedPort, + uint16_t selectedPins) { + uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; + + #ifndef NDEBUG + if(baseAddress == 0xFFFF) + { + return; + } + #endif + + // Shift by 8 if port is even (upper 8-bits) + if((selectedPort & 1) ^ 1) + { + selectedPins <<= 8; + } + + HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins; + HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins; + + HWREG16(baseAddress + OFS_PADIR) &= ~selectedPins; + HWREG16(baseAddress + OFS_PAREN) |= selectedPins; + HWREG16(baseAddress + OFS_PAOUT) &= ~selectedPins; +} + +void GPIO_setAsInputPinWithPullUpResistor(uint8_t selectedPort, + uint16_t selectedPins) { + uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; + + #ifndef NDEBUG + if(baseAddress == 0xFFFF) + { + return; + } + #endif + + // Shift by 8 if port is even (upper 8-bits) + if((selectedPort & 1) ^ 1) + { + selectedPins <<= 8; + } + + HWREG16(baseAddress + OFS_PASEL0) &= ~selectedPins; + HWREG16(baseAddress + OFS_PASEL1) &= ~selectedPins; + HWREG16(baseAddress + OFS_PADIR) &= ~selectedPins; + HWREG16(baseAddress + OFS_PAREN) |= selectedPins; + HWREG16(baseAddress + OFS_PAOUT) |= selectedPins; +} + +uint8_t GPIO_getInputPinValue(uint8_t selectedPort, + uint16_t selectedPins) { + uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; + + #ifndef NDEBUG + if(baseAddress == 0xFFFF) + { + return; + } + #endif + + // Shift by 8 if port is even (upper 8-bits) + if((selectedPort & 1) ^ 1) + { + selectedPins <<= 8; + } + + uint16_t inputPinValue = HWREG16(baseAddress + OFS_PAIN) & (selectedPins); + + if(inputPinValue > 0) + { + return (GPIO_INPUT_PIN_HIGH); + } + return (GPIO_INPUT_PIN_LOW); +} + +void GPIO_enableInterrupt(uint8_t selectedPort, + uint16_t selectedPins) { + uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; + + #ifndef NDEBUG + if(baseAddress == 0xFFFF) + { + return; + } + #endif + + // Shift by 8 if port is even (upper 8-bits) + if((selectedPort & 1) ^ 1) + { + selectedPins <<= 8; + } + + HWREG16(baseAddress + OFS_PAIE) |= selectedPins; +} + +void GPIO_disableInterrupt(uint8_t selectedPort, + uint16_t selectedPins) { + uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; + + #ifndef NDEBUG + if(baseAddress == 0xFFFF) + { + return; + } + #endif + + // Shift by 8 if port is even (upper 8-bits) + if((selectedPort & 1) ^ 1) + { + selectedPins <<= 8; + } + + HWREG16(baseAddress + OFS_PAIE) &= ~selectedPins; +} + +uint16_t GPIO_getInterruptStatus(uint8_t selectedPort, + uint16_t selectedPins) { + uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; + + #ifndef NDEBUG + if(baseAddress == 0xFFFF) + { + return; + } + #endif + + // Shift by 8 if port is even (upper 8-bits) + if((selectedPort & 1) ^ 1) + { + selectedPins <<= 8; + } + + return (HWREG16(baseAddress + OFS_PAIFG) & selectedPins); +} + +void GPIO_clearInterrupt(uint8_t selectedPort, + uint16_t selectedPins) { + uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; + + #ifndef NDEBUG + if(baseAddress == 0xFFFF) + { + return; + } + #endif + + // Shift by 8 if port is even (upper 8-bits) + if((selectedPort & 1) ^ 1) + { + selectedPins <<= 8; + } + + HWREG16(baseAddress + OFS_PAIFG) &= ~selectedPins; +} + +void GPIO_selectInterruptEdge(uint8_t selectedPort, + uint16_t selectedPins, + uint8_t edgeSelect) { + uint16_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; + + #ifndef NDEBUG + if(baseAddress == 0xFFFF) + { + return; + } + #endif + + // Shift by 8 if port is even (upper 8-bits) + if((selectedPort & 1) ^ 1) + { + selectedPins <<= 8; + } + + if(GPIO_LOW_TO_HIGH_TRANSITION == edgeSelect) + { + HWREG16(baseAddress + OFS_PAIES) &= ~selectedPins; + } + else + { + HWREG16(baseAddress + OFS_PAIES) |= selectedPins; + } +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for gpio_api +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/gpio.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/gpio.h new file mode 100644 index 000000000..0f612ba45 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/gpio.h @@ -0,0 +1,1017 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// gpio.h - Driver for the GPIO Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_GPIO_H__ +#define __MSP430WARE_GPIO_H__ + +#include "inc/hw_memmap.h" + +#if defined(__MSP430_HAS_PORT1_R__) || defined(__MSP430_HAS_PORT2_R__) || \ + defined(__MSP430_HAS_PORTA_R__) + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the selectedPort parameter +// for functions: GPIO_setAsOutputPin(), GPIO_setAsInputPin(), +// GPIO_setAsPeripheralModuleFunctionOutputPin(), +// GPIO_setAsPeripheralModuleFunctionInputPin(), GPIO_setOutputHighOnPin(), +// GPIO_setOutputLowOnPin(), GPIO_toggleOutputOnPin(), +// GPIO_setAsInputPinWithPullDownResistor(), +// GPIO_setAsInputPinWithPullUpResistor(), GPIO_getInputPinValue(), +// GPIO_selectInterruptEdge(), GPIO_enableInterrupt(), GPIO_disableInterrupt(), +// GPIO_getInterruptStatus(), and GPIO_clearInterrupt(). +// +//***************************************************************************** +#define GPIO_PORT_P1 1 +#define GPIO_PORT_P2 2 +#define GPIO_PORT_P3 3 +#define GPIO_PORT_P4 4 +#define GPIO_PORT_P5 5 +#define GPIO_PORT_P6 6 +#define GPIO_PORT_P7 7 +#define GPIO_PORT_P8 8 +#define GPIO_PORT_P9 9 +#define GPIO_PORT_P10 10 +#define GPIO_PORT_P11 11 +#define GPIO_PORT_PA 1 +#define GPIO_PORT_PB 3 +#define GPIO_PORT_PC 5 +#define GPIO_PORT_PD 7 +#define GPIO_PORT_PE 9 +#define GPIO_PORT_PF 11 +#define GPIO_PORT_PJ 13 + +//***************************************************************************** +// +// The following are values that can be passed to the selectedPins parameter +// for functions: GPIO_setAsOutputPin(), GPIO_setAsInputPin(), +// GPIO_setAsPeripheralModuleFunctionOutputPin(), +// GPIO_setAsPeripheralModuleFunctionInputPin(), GPIO_setOutputHighOnPin(), +// GPIO_setOutputLowOnPin(), GPIO_toggleOutputOnPin(), +// GPIO_setAsInputPinWithPullDownResistor(), +// GPIO_setAsInputPinWithPullUpResistor(), GPIO_getInputPinValue(), +// GPIO_enableInterrupt(), GPIO_disableInterrupt(), GPIO_getInterruptStatus(), +// GPIO_clearInterrupt(), and GPIO_selectInterruptEdge() as well as returned by +// the GPIO_getInterruptStatus() function. +// +//***************************************************************************** +#define GPIO_PIN0 (0x0001) +#define GPIO_PIN1 (0x0002) +#define GPIO_PIN2 (0x0004) +#define GPIO_PIN3 (0x0008) +#define GPIO_PIN4 (0x0010) +#define GPIO_PIN5 (0x0020) +#define GPIO_PIN6 (0x0040) +#define GPIO_PIN7 (0x0080) +#define GPIO_PIN8 (0x0100) +#define GPIO_PIN9 (0x0200) +#define GPIO_PIN10 (0x0400) +#define GPIO_PIN11 (0x0800) +#define GPIO_PIN12 (0x1000) +#define GPIO_PIN13 (0x2000) +#define GPIO_PIN14 (0x4000) +#define GPIO_PIN15 (0x8000) + +//***************************************************************************** +// +// The following are values that can be passed to the mode parameter for +// functions: GPIO_setAsPeripheralModuleFunctionOutputPin(), and +// GPIO_setAsPeripheralModuleFunctionInputPin(). +// +//***************************************************************************** +#define GPIO_PRIMARY_MODULE_FUNCTION (0x01) +#define GPIO_SECONDARY_MODULE_FUNCTION (0x02) +#define GPIO_TERNARY_MODULE_FUNCTION (0x03) + +//***************************************************************************** +// +// The following are values that can be passed to the edgeSelect parameter for +// functions: GPIO_selectInterruptEdge(). +// +//***************************************************************************** +#define GPIO_HIGH_TO_LOW_TRANSITION (0x01) +#define GPIO_LOW_TO_HIGH_TRANSITION (0x00) + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the GPIO_getInputPinValue() function. +// +//***************************************************************************** +#define GPIO_INPUT_PIN_HIGH (0x01) +#define GPIO_INPUT_PIN_LOW (0x00) + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief This function configures the selected Pin as output pin +//! +//! This function selected pins on a selected port as output pins. +//! +//! \param selectedPort is the selected port. +//! Valid values are: +//! - \b GPIO_PORT_P1 +//! - \b GPIO_PORT_P2 +//! - \b GPIO_PORT_P3 +//! - \b GPIO_PORT_P4 +//! - \b GPIO_PORT_P5 +//! - \b GPIO_PORT_P6 +//! - \b GPIO_PORT_P7 +//! - \b GPIO_PORT_P8 +//! - \b GPIO_PORT_P9 +//! - \b GPIO_PORT_P10 +//! - \b GPIO_PORT_P11 +//! - \b GPIO_PORT_PA +//! - \b GPIO_PORT_PB +//! - \b GPIO_PORT_PC +//! - \b GPIO_PORT_PD +//! - \b GPIO_PORT_PE +//! - \b GPIO_PORT_PF +//! - \b GPIO_PORT_PJ +//! \param selectedPins is the specified pin in the selected port. +//! Mask value is the logical OR of any of the following: +//! - \b GPIO_PIN0 +//! - \b GPIO_PIN1 +//! - \b GPIO_PIN2 +//! - \b GPIO_PIN3 +//! - \b GPIO_PIN4 +//! - \b GPIO_PIN5 +//! - \b GPIO_PIN6 +//! - \b GPIO_PIN7 +//! - \b GPIO_PIN8 +//! - \b GPIO_PIN9 +//! - \b GPIO_PIN10 +//! - \b GPIO_PIN11 +//! - \b GPIO_PIN12 +//! - \b GPIO_PIN13 +//! - \b GPIO_PIN14 +//! - \b GPIO_PIN15 +//! +//! Modified bits of \b PxDIR register and bits of \b PxSEL register. +//! +//! \return None +// +//***************************************************************************** +extern void GPIO_setAsOutputPin(uint8_t selectedPort, + uint16_t selectedPins); + +//***************************************************************************** +// +//! \brief This function configures the selected Pin as input pin +//! +//! This function selected pins on a selected port as input pins. +//! +//! \param selectedPort is the selected port. +//! Valid values are: +//! - \b GPIO_PORT_P1 +//! - \b GPIO_PORT_P2 +//! - \b GPIO_PORT_P3 +//! - \b GPIO_PORT_P4 +//! - \b GPIO_PORT_P5 +//! - \b GPIO_PORT_P6 +//! - \b GPIO_PORT_P7 +//! - \b GPIO_PORT_P8 +//! - \b GPIO_PORT_P9 +//! - \b GPIO_PORT_P10 +//! - \b GPIO_PORT_P11 +//! - \b GPIO_PORT_PA +//! - \b GPIO_PORT_PB +//! - \b GPIO_PORT_PC +//! - \b GPIO_PORT_PD +//! - \b GPIO_PORT_PE +//! - \b GPIO_PORT_PF +//! - \b GPIO_PORT_PJ +//! \param selectedPins is the specified pin in the selected port. +//! Mask value is the logical OR of any of the following: +//! - \b GPIO_PIN0 +//! - \b GPIO_PIN1 +//! - \b GPIO_PIN2 +//! - \b GPIO_PIN3 +//! - \b GPIO_PIN4 +//! - \b GPIO_PIN5 +//! - \b GPIO_PIN6 +//! - \b GPIO_PIN7 +//! - \b GPIO_PIN8 +//! - \b GPIO_PIN9 +//! - \b GPIO_PIN10 +//! - \b GPIO_PIN11 +//! - \b GPIO_PIN12 +//! - \b GPIO_PIN13 +//! - \b GPIO_PIN14 +//! - \b GPIO_PIN15 +//! +//! Modified bits of \b PxDIR register, bits of \b PxREN register and bits of +//! \b PxSEL register. +//! +//! \return None +// +//***************************************************************************** +extern void GPIO_setAsInputPin(uint8_t selectedPort, + uint16_t selectedPins); + +//***************************************************************************** +// +//! \brief This function configures the peripheral module function in the +//! output direction for the selected pin. +//! +//! This function configures the peripheral module function in the output +//! direction for the selected pin for either primary, secondary or ternary +//! module function modes. Note that MSP430F5xx/6xx family doesn't support +//! these function modes. +//! +//! \param selectedPort is the selected port. +//! Valid values are: +//! - \b GPIO_PORT_P1 +//! - \b GPIO_PORT_P2 +//! - \b GPIO_PORT_P3 +//! - \b GPIO_PORT_P4 +//! - \b GPIO_PORT_P5 +//! - \b GPIO_PORT_P6 +//! - \b GPIO_PORT_P7 +//! - \b GPIO_PORT_P8 +//! - \b GPIO_PORT_P9 +//! - \b GPIO_PORT_P10 +//! - \b GPIO_PORT_P11 +//! - \b GPIO_PORT_PA +//! - \b GPIO_PORT_PB +//! - \b GPIO_PORT_PC +//! - \b GPIO_PORT_PD +//! - \b GPIO_PORT_PE +//! - \b GPIO_PORT_PF +//! - \b GPIO_PORT_PJ +//! \param selectedPins is the specified pin in the selected port. +//! Mask value is the logical OR of any of the following: +//! - \b GPIO_PIN0 +//! - \b GPIO_PIN1 +//! - \b GPIO_PIN2 +//! - \b GPIO_PIN3 +//! - \b GPIO_PIN4 +//! - \b GPIO_PIN5 +//! - \b GPIO_PIN6 +//! - \b GPIO_PIN7 +//! - \b GPIO_PIN8 +//! - \b GPIO_PIN9 +//! - \b GPIO_PIN10 +//! - \b GPIO_PIN11 +//! - \b GPIO_PIN12 +//! - \b GPIO_PIN13 +//! - \b GPIO_PIN14 +//! - \b GPIO_PIN15 +//! \param mode is the specified mode that the pin should be configured for the +//! module function. +//! Valid values are: +//! - \b GPIO_PRIMARY_MODULE_FUNCTION +//! - \b GPIO_SECONDARY_MODULE_FUNCTION +//! - \b GPIO_TERNARY_MODULE_FUNCTION +//! +//! Modified bits of \b PxDIR register and bits of \b PxSEL register. +//! +//! \return None +// +//***************************************************************************** +extern void GPIO_setAsPeripheralModuleFunctionOutputPin(uint8_t selectedPort, + uint16_t selectedPins, + uint8_t mode); + +//***************************************************************************** +// +//! \brief This function configures the peripheral module function in the input +//! direction for the selected pin. +//! +//! This function configures the peripheral module function in the input +//! direction for the selected pin for either primary, secondary or ternary +//! module function modes. Note that MSP430F5xx/6xx family doesn't support +//! these function modes. +//! +//! \param selectedPort is the selected port. +//! Valid values are: +//! - \b GPIO_PORT_P1 +//! - \b GPIO_PORT_P2 +//! - \b GPIO_PORT_P3 +//! - \b GPIO_PORT_P4 +//! - \b GPIO_PORT_P5 +//! - \b GPIO_PORT_P6 +//! - \b GPIO_PORT_P7 +//! - \b GPIO_PORT_P8 +//! - \b GPIO_PORT_P9 +//! - \b GPIO_PORT_P10 +//! - \b GPIO_PORT_P11 +//! - \b GPIO_PORT_PA +//! - \b GPIO_PORT_PB +//! - \b GPIO_PORT_PC +//! - \b GPIO_PORT_PD +//! - \b GPIO_PORT_PE +//! - \b GPIO_PORT_PF +//! - \b GPIO_PORT_PJ +//! \param selectedPins is the specified pin in the selected port. +//! Mask value is the logical OR of any of the following: +//! - \b GPIO_PIN0 +//! - \b GPIO_PIN1 +//! - \b GPIO_PIN2 +//! - \b GPIO_PIN3 +//! - \b GPIO_PIN4 +//! - \b GPIO_PIN5 +//! - \b GPIO_PIN6 +//! - \b GPIO_PIN7 +//! - \b GPIO_PIN8 +//! - \b GPIO_PIN9 +//! - \b GPIO_PIN10 +//! - \b GPIO_PIN11 +//! - \b GPIO_PIN12 +//! - \b GPIO_PIN13 +//! - \b GPIO_PIN14 +//! - \b GPIO_PIN15 +//! \param mode is the specified mode that the pin should be configured for the +//! module function. +//! Valid values are: +//! - \b GPIO_PRIMARY_MODULE_FUNCTION +//! - \b GPIO_SECONDARY_MODULE_FUNCTION +//! - \b GPIO_TERNARY_MODULE_FUNCTION +//! +//! Modified bits of \b PxDIR register and bits of \b PxSEL register. +//! +//! \return None +// +//***************************************************************************** +extern void GPIO_setAsPeripheralModuleFunctionInputPin(uint8_t selectedPort, + uint16_t selectedPins, + uint8_t mode); + +//***************************************************************************** +// +//! \brief This function sets output HIGH on the selected Pin +//! +//! This function sets output HIGH on the selected port's pin. +//! +//! \param selectedPort is the selected port. +//! Valid values are: +//! - \b GPIO_PORT_P1 +//! - \b GPIO_PORT_P2 +//! - \b GPIO_PORT_P3 +//! - \b GPIO_PORT_P4 +//! - \b GPIO_PORT_P5 +//! - \b GPIO_PORT_P6 +//! - \b GPIO_PORT_P7 +//! - \b GPIO_PORT_P8 +//! - \b GPIO_PORT_P9 +//! - \b GPIO_PORT_P10 +//! - \b GPIO_PORT_P11 +//! - \b GPIO_PORT_PA +//! - \b GPIO_PORT_PB +//! - \b GPIO_PORT_PC +//! - \b GPIO_PORT_PD +//! - \b GPIO_PORT_PE +//! - \b GPIO_PORT_PF +//! - \b GPIO_PORT_PJ +//! \param selectedPins is the specified pin in the selected port. +//! Mask value is the logical OR of any of the following: +//! - \b GPIO_PIN0 +//! - \b GPIO_PIN1 +//! - \b GPIO_PIN2 +//! - \b GPIO_PIN3 +//! - \b GPIO_PIN4 +//! - \b GPIO_PIN5 +//! - \b GPIO_PIN6 +//! - \b GPIO_PIN7 +//! - \b GPIO_PIN8 +//! - \b GPIO_PIN9 +//! - \b GPIO_PIN10 +//! - \b GPIO_PIN11 +//! - \b GPIO_PIN12 +//! - \b GPIO_PIN13 +//! - \b GPIO_PIN14 +//! - \b GPIO_PIN15 +//! +//! Modified bits of \b PxOUT register. +//! +//! \return None +// +//***************************************************************************** +extern void GPIO_setOutputHighOnPin(uint8_t selectedPort, + uint16_t selectedPins); + +//***************************************************************************** +// +//! \brief This function sets output LOW on the selected Pin +//! +//! This function sets output LOW on the selected port's pin. +//! +//! \param selectedPort is the selected port. +//! Valid values are: +//! - \b GPIO_PORT_P1 +//! - \b GPIO_PORT_P2 +//! - \b GPIO_PORT_P3 +//! - \b GPIO_PORT_P4 +//! - \b GPIO_PORT_P5 +//! - \b GPIO_PORT_P6 +//! - \b GPIO_PORT_P7 +//! - \b GPIO_PORT_P8 +//! - \b GPIO_PORT_P9 +//! - \b GPIO_PORT_P10 +//! - \b GPIO_PORT_P11 +//! - \b GPIO_PORT_PA +//! - \b GPIO_PORT_PB +//! - \b GPIO_PORT_PC +//! - \b GPIO_PORT_PD +//! - \b GPIO_PORT_PE +//! - \b GPIO_PORT_PF +//! - \b GPIO_PORT_PJ +//! \param selectedPins is the specified pin in the selected port. +//! Mask value is the logical OR of any of the following: +//! - \b GPIO_PIN0 +//! - \b GPIO_PIN1 +//! - \b GPIO_PIN2 +//! - \b GPIO_PIN3 +//! - \b GPIO_PIN4 +//! - \b GPIO_PIN5 +//! - \b GPIO_PIN6 +//! - \b GPIO_PIN7 +//! - \b GPIO_PIN8 +//! - \b GPIO_PIN9 +//! - \b GPIO_PIN10 +//! - \b GPIO_PIN11 +//! - \b GPIO_PIN12 +//! - \b GPIO_PIN13 +//! - \b GPIO_PIN14 +//! - \b GPIO_PIN15 +//! +//! Modified bits of \b PxOUT register. +//! +//! \return None +// +//***************************************************************************** +extern void GPIO_setOutputLowOnPin(uint8_t selectedPort, + uint16_t selectedPins); + +//***************************************************************************** +// +//! \brief This function toggles the output on the selected Pin +//! +//! This function toggles the output on the selected port's pin. +//! +//! \param selectedPort is the selected port. +//! Valid values are: +//! - \b GPIO_PORT_P1 +//! - \b GPIO_PORT_P2 +//! - \b GPIO_PORT_P3 +//! - \b GPIO_PORT_P4 +//! - \b GPIO_PORT_P5 +//! - \b GPIO_PORT_P6 +//! - \b GPIO_PORT_P7 +//! - \b GPIO_PORT_P8 +//! - \b GPIO_PORT_P9 +//! - \b GPIO_PORT_P10 +//! - \b GPIO_PORT_P11 +//! - \b GPIO_PORT_PA +//! - \b GPIO_PORT_PB +//! - \b GPIO_PORT_PC +//! - \b GPIO_PORT_PD +//! - \b GPIO_PORT_PE +//! - \b GPIO_PORT_PF +//! - \b GPIO_PORT_PJ +//! \param selectedPins is the specified pin in the selected port. +//! Mask value is the logical OR of any of the following: +//! - \b GPIO_PIN0 +//! - \b GPIO_PIN1 +//! - \b GPIO_PIN2 +//! - \b GPIO_PIN3 +//! - \b GPIO_PIN4 +//! - \b GPIO_PIN5 +//! - \b GPIO_PIN6 +//! - \b GPIO_PIN7 +//! - \b GPIO_PIN8 +//! - \b GPIO_PIN9 +//! - \b GPIO_PIN10 +//! - \b GPIO_PIN11 +//! - \b GPIO_PIN12 +//! - \b GPIO_PIN13 +//! - \b GPIO_PIN14 +//! - \b GPIO_PIN15 +//! +//! Modified bits of \b PxOUT register. +//! +//! \return None +// +//***************************************************************************** +extern void GPIO_toggleOutputOnPin(uint8_t selectedPort, + uint16_t selectedPins); + +//***************************************************************************** +// +//! \brief This function sets the selected Pin in input Mode with Pull Down +//! resistor +//! +//! This function sets the selected Pin in input Mode with Pull Down resistor. +//! +//! \param selectedPort is the selected port. +//! Valid values are: +//! - \b GPIO_PORT_P1 +//! - \b GPIO_PORT_P2 +//! - \b GPIO_PORT_P3 +//! - \b GPIO_PORT_P4 +//! - \b GPIO_PORT_P5 +//! - \b GPIO_PORT_P6 +//! - \b GPIO_PORT_P7 +//! - \b GPIO_PORT_P8 +//! - \b GPIO_PORT_P9 +//! - \b GPIO_PORT_P10 +//! - \b GPIO_PORT_P11 +//! - \b GPIO_PORT_PA +//! - \b GPIO_PORT_PB +//! - \b GPIO_PORT_PC +//! - \b GPIO_PORT_PD +//! - \b GPIO_PORT_PE +//! - \b GPIO_PORT_PF +//! - \b GPIO_PORT_PJ +//! \param selectedPins is the specified pin in the selected port. +//! Mask value is the logical OR of any of the following: +//! - \b GPIO_PIN0 +//! - \b GPIO_PIN1 +//! - \b GPIO_PIN2 +//! - \b GPIO_PIN3 +//! - \b GPIO_PIN4 +//! - \b GPIO_PIN5 +//! - \b GPIO_PIN6 +//! - \b GPIO_PIN7 +//! - \b GPIO_PIN8 +//! - \b GPIO_PIN9 +//! - \b GPIO_PIN10 +//! - \b GPIO_PIN11 +//! - \b GPIO_PIN12 +//! - \b GPIO_PIN13 +//! - \b GPIO_PIN14 +//! - \b GPIO_PIN15 +//! +//! Modified bits of \b PxDIR register, bits of \b PxOUT register and bits of +//! \b PxREN register. +//! +//! \return None +// +//***************************************************************************** +extern void GPIO_setAsInputPinWithPullDownResistor(uint8_t selectedPort, + uint16_t selectedPins); + +//***************************************************************************** +// +//! \brief This function sets the selected Pin in input Mode with Pull Up +//! resistor +//! +//! This function sets the selected Pin in input Mode with Pull Up resistor. +//! +//! \param selectedPort is the selected port. +//! Valid values are: +//! - \b GPIO_PORT_P1 +//! - \b GPIO_PORT_P2 +//! - \b GPIO_PORT_P3 +//! - \b GPIO_PORT_P4 +//! - \b GPIO_PORT_P5 +//! - \b GPIO_PORT_P6 +//! - \b GPIO_PORT_P7 +//! - \b GPIO_PORT_P8 +//! - \b GPIO_PORT_P9 +//! - \b GPIO_PORT_P10 +//! - \b GPIO_PORT_P11 +//! - \b GPIO_PORT_PA +//! - \b GPIO_PORT_PB +//! - \b GPIO_PORT_PC +//! - \b GPIO_PORT_PD +//! - \b GPIO_PORT_PE +//! - \b GPIO_PORT_PF +//! - \b GPIO_PORT_PJ +//! \param selectedPins is the specified pin in the selected port. +//! Mask value is the logical OR of any of the following: +//! - \b GPIO_PIN0 +//! - \b GPIO_PIN1 +//! - \b GPIO_PIN2 +//! - \b GPIO_PIN3 +//! - \b GPIO_PIN4 +//! - \b GPIO_PIN5 +//! - \b GPIO_PIN6 +//! - \b GPIO_PIN7 +//! - \b GPIO_PIN8 +//! - \b GPIO_PIN9 +//! - \b GPIO_PIN10 +//! - \b GPIO_PIN11 +//! - \b GPIO_PIN12 +//! - \b GPIO_PIN13 +//! - \b GPIO_PIN14 +//! - \b GPIO_PIN15 +//! +//! Modified bits of \b PxDIR register, bits of \b PxOUT register and bits of +//! \b PxREN register. +//! +//! \return None +// +//***************************************************************************** +extern void GPIO_setAsInputPinWithPullUpResistor(uint8_t selectedPort, + uint16_t selectedPins); + +//***************************************************************************** +// +//! \brief This function gets the input value on the selected pin +//! +//! This function gets the input value on the selected pin. +//! +//! \param selectedPort is the selected port. +//! Valid values are: +//! - \b GPIO_PORT_P1 +//! - \b GPIO_PORT_P2 +//! - \b GPIO_PORT_P3 +//! - \b GPIO_PORT_P4 +//! - \b GPIO_PORT_P5 +//! - \b GPIO_PORT_P6 +//! - \b GPIO_PORT_P7 +//! - \b GPIO_PORT_P8 +//! - \b GPIO_PORT_P9 +//! - \b GPIO_PORT_P10 +//! - \b GPIO_PORT_P11 +//! - \b GPIO_PORT_PA +//! - \b GPIO_PORT_PB +//! - \b GPIO_PORT_PC +//! - \b GPIO_PORT_PD +//! - \b GPIO_PORT_PE +//! - \b GPIO_PORT_PF +//! - \b GPIO_PORT_PJ +//! \param selectedPins is the specified pin in the selected port. +//! Valid values are: +//! - \b GPIO_PIN0 +//! - \b GPIO_PIN1 +//! - \b GPIO_PIN2 +//! - \b GPIO_PIN3 +//! - \b GPIO_PIN4 +//! - \b GPIO_PIN5 +//! - \b GPIO_PIN6 +//! - \b GPIO_PIN7 +//! - \b GPIO_PIN8 +//! - \b GPIO_PIN9 +//! - \b GPIO_PIN10 +//! - \b GPIO_PIN11 +//! - \b GPIO_PIN12 +//! - \b GPIO_PIN13 +//! - \b GPIO_PIN14 +//! - \b GPIO_PIN15 +//! +//! \return One of the following: +//! - \b GPIO_INPUT_PIN_HIGH +//! - \b GPIO_INPUT_PIN_LOW +//! \n indicating the status of the pin +// +//***************************************************************************** +extern uint8_t GPIO_getInputPinValue(uint8_t selectedPort, + uint16_t selectedPins); + +//***************************************************************************** +// +//! \brief This function enables the port interrupt on the selected pin +//! +//! This function enables the port interrupt on the selected pin. Please refer +//! to family user's guide for available ports with interrupt capability. +//! +//! \param selectedPort is the selected port. +//! Valid values are: +//! - \b GPIO_PORT_P1 +//! - \b GPIO_PORT_P2 +//! - \b GPIO_PORT_P3 +//! - \b GPIO_PORT_P4 +//! - \b GPIO_PORT_P5 +//! - \b GPIO_PORT_P6 +//! - \b GPIO_PORT_P7 +//! - \b GPIO_PORT_P8 +//! - \b GPIO_PORT_P9 +//! - \b GPIO_PORT_P10 +//! - \b GPIO_PORT_P11 +//! - \b GPIO_PORT_PA +//! - \b GPIO_PORT_PB +//! - \b GPIO_PORT_PC +//! - \b GPIO_PORT_PD +//! - \b GPIO_PORT_PE +//! - \b GPIO_PORT_PF +//! - \b GPIO_PORT_PJ +//! \param selectedPins is the specified pin in the selected port. +//! Mask value is the logical OR of any of the following: +//! - \b GPIO_PIN0 +//! - \b GPIO_PIN1 +//! - \b GPIO_PIN2 +//! - \b GPIO_PIN3 +//! - \b GPIO_PIN4 +//! - \b GPIO_PIN5 +//! - \b GPIO_PIN6 +//! - \b GPIO_PIN7 +//! - \b GPIO_PIN8 +//! - \b GPIO_PIN9 +//! - \b GPIO_PIN10 +//! - \b GPIO_PIN11 +//! - \b GPIO_PIN12 +//! - \b GPIO_PIN13 +//! - \b GPIO_PIN14 +//! - \b GPIO_PIN15 +//! +//! Modified bits of \b PxIE register. +//! +//! \return None +// +//***************************************************************************** +extern void GPIO_enableInterrupt(uint8_t selectedPort, + uint16_t selectedPins); + +//***************************************************************************** +// +//! \brief This function disables the port interrupt on the selected pin +//! +//! This function disables the port interrupt on the selected pin. Please refer +//! to family user's guide for available ports with interrupt capability. +//! +//! \param selectedPort is the selected port. +//! Valid values are: +//! - \b GPIO_PORT_P1 +//! - \b GPIO_PORT_P2 +//! - \b GPIO_PORT_P3 +//! - \b GPIO_PORT_P4 +//! - \b GPIO_PORT_P5 +//! - \b GPIO_PORT_P6 +//! - \b GPIO_PORT_P7 +//! - \b GPIO_PORT_P8 +//! - \b GPIO_PORT_P9 +//! - \b GPIO_PORT_P10 +//! - \b GPIO_PORT_P11 +//! - \b GPIO_PORT_PA +//! - \b GPIO_PORT_PB +//! - \b GPIO_PORT_PC +//! - \b GPIO_PORT_PD +//! - \b GPIO_PORT_PE +//! - \b GPIO_PORT_PF +//! - \b GPIO_PORT_PJ +//! \param selectedPins is the specified pin in the selected port. +//! Mask value is the logical OR of any of the following: +//! - \b GPIO_PIN0 +//! - \b GPIO_PIN1 +//! - \b GPIO_PIN2 +//! - \b GPIO_PIN3 +//! - \b GPIO_PIN4 +//! - \b GPIO_PIN5 +//! - \b GPIO_PIN6 +//! - \b GPIO_PIN7 +//! - \b GPIO_PIN8 +//! - \b GPIO_PIN9 +//! - \b GPIO_PIN10 +//! - \b GPIO_PIN11 +//! - \b GPIO_PIN12 +//! - \b GPIO_PIN13 +//! - \b GPIO_PIN14 +//! - \b GPIO_PIN15 +//! +//! Modified bits of \b PxIE register. +//! +//! \return None +// +//***************************************************************************** +extern void GPIO_disableInterrupt(uint8_t selectedPort, + uint16_t selectedPins); + +//***************************************************************************** +// +//! \brief This function gets the interrupt status of the selected pin +//! +//! This function gets the interrupt status of the selected pin. Please refer +//! to family user's guide for available ports with interrupt capability. +//! +//! \param selectedPort is the selected port. +//! Valid values are: +//! - \b GPIO_PORT_P1 +//! - \b GPIO_PORT_P2 +//! - \b GPIO_PORT_P3 +//! - \b GPIO_PORT_P4 +//! - \b GPIO_PORT_P5 +//! - \b GPIO_PORT_P6 +//! - \b GPIO_PORT_P7 +//! - \b GPIO_PORT_P8 +//! - \b GPIO_PORT_P9 +//! - \b GPIO_PORT_P10 +//! - \b GPIO_PORT_P11 +//! - \b GPIO_PORT_PA +//! - \b GPIO_PORT_PB +//! - \b GPIO_PORT_PC +//! - \b GPIO_PORT_PD +//! - \b GPIO_PORT_PE +//! - \b GPIO_PORT_PF +//! - \b GPIO_PORT_PJ +//! \param selectedPins is the specified pin in the selected port. +//! Mask value is the logical OR of any of the following: +//! - \b GPIO_PIN0 +//! - \b GPIO_PIN1 +//! - \b GPIO_PIN2 +//! - \b GPIO_PIN3 +//! - \b GPIO_PIN4 +//! - \b GPIO_PIN5 +//! - \b GPIO_PIN6 +//! - \b GPIO_PIN7 +//! - \b GPIO_PIN8 +//! - \b GPIO_PIN9 +//! - \b GPIO_PIN10 +//! - \b GPIO_PIN11 +//! - \b GPIO_PIN12 +//! - \b GPIO_PIN13 +//! - \b GPIO_PIN14 +//! - \b GPIO_PIN15 +//! +//! \return Logical OR of any of the following: +//! - \b GPIO_PIN0 +//! - \b GPIO_PIN1 +//! - \b GPIO_PIN2 +//! - \b GPIO_PIN3 +//! - \b GPIO_PIN4 +//! - \b GPIO_PIN5 +//! - \b GPIO_PIN6 +//! - \b GPIO_PIN7 +//! - \b GPIO_PIN8 +//! - \b GPIO_PIN9 +//! - \b GPIO_PIN10 +//! - \b GPIO_PIN11 +//! - \b GPIO_PIN12 +//! - \b GPIO_PIN13 +//! - \b GPIO_PIN14 +//! - \b GPIO_PIN15 +//! \n indicating the interrupt status of the selected pins [Default: +//! 0] +// +//***************************************************************************** +extern uint16_t GPIO_getInterruptStatus(uint8_t selectedPort, + uint16_t selectedPins); + +//***************************************************************************** +// +//! \brief This function clears the interrupt flag on the selected pin +//! +//! This function clears the interrupt flag on the selected pin. Please refer +//! to family user's guide for available ports with interrupt capability. +//! +//! \param selectedPort is the selected port. +//! Valid values are: +//! - \b GPIO_PORT_P1 +//! - \b GPIO_PORT_P2 +//! - \b GPIO_PORT_P3 +//! - \b GPIO_PORT_P4 +//! - \b GPIO_PORT_P5 +//! - \b GPIO_PORT_P6 +//! - \b GPIO_PORT_P7 +//! - \b GPIO_PORT_P8 +//! - \b GPIO_PORT_P9 +//! - \b GPIO_PORT_P10 +//! - \b GPIO_PORT_P11 +//! - \b GPIO_PORT_PA +//! - \b GPIO_PORT_PB +//! - \b GPIO_PORT_PC +//! - \b GPIO_PORT_PD +//! - \b GPIO_PORT_PE +//! - \b GPIO_PORT_PF +//! - \b GPIO_PORT_PJ +//! \param selectedPins is the specified pin in the selected port. +//! Mask value is the logical OR of any of the following: +//! - \b GPIO_PIN0 +//! - \b GPIO_PIN1 +//! - \b GPIO_PIN2 +//! - \b GPIO_PIN3 +//! - \b GPIO_PIN4 +//! - \b GPIO_PIN5 +//! - \b GPIO_PIN6 +//! - \b GPIO_PIN7 +//! - \b GPIO_PIN8 +//! - \b GPIO_PIN9 +//! - \b GPIO_PIN10 +//! - \b GPIO_PIN11 +//! - \b GPIO_PIN12 +//! - \b GPIO_PIN13 +//! - \b GPIO_PIN14 +//! - \b GPIO_PIN15 +//! +//! Modified bits of \b PxIFG register. +//! +//! \return None +// +//***************************************************************************** +extern void GPIO_clearInterrupt(uint8_t selectedPort, + uint16_t selectedPins); + +//***************************************************************************** +// +//! \brief This function selects on what edge the port interrupt flag should be +//! set for a transition +//! +//! This function selects on what edge the port interrupt flag should be set +//! for a transition. Values for edgeSelect should be +//! GPIO_LOW_TO_HIGH_TRANSITION or GPIO_HIGH_TO_LOW_TRANSITION. Please refer to +//! family user's guide for available ports with interrupt capability. +//! +//! \param selectedPort is the selected port. +//! Valid values are: +//! - \b GPIO_PORT_P1 +//! - \b GPIO_PORT_P2 +//! - \b GPIO_PORT_P3 +//! - \b GPIO_PORT_P4 +//! - \b GPIO_PORT_P5 +//! - \b GPIO_PORT_P6 +//! - \b GPIO_PORT_P7 +//! - \b GPIO_PORT_P8 +//! - \b GPIO_PORT_P9 +//! - \b GPIO_PORT_P10 +//! - \b GPIO_PORT_P11 +//! - \b GPIO_PORT_PA +//! - \b GPIO_PORT_PB +//! - \b GPIO_PORT_PC +//! - \b GPIO_PORT_PD +//! - \b GPIO_PORT_PE +//! - \b GPIO_PORT_PF +//! - \b GPIO_PORT_PJ +//! \param selectedPins is the specified pin in the selected port. +//! Mask value is the logical OR of any of the following: +//! - \b GPIO_PIN0 +//! - \b GPIO_PIN1 +//! - \b GPIO_PIN2 +//! - \b GPIO_PIN3 +//! - \b GPIO_PIN4 +//! - \b GPIO_PIN5 +//! - \b GPIO_PIN6 +//! - \b GPIO_PIN7 +//! - \b GPIO_PIN8 +//! - \b GPIO_PIN9 +//! - \b GPIO_PIN10 +//! - \b GPIO_PIN11 +//! - \b GPIO_PIN12 +//! - \b GPIO_PIN13 +//! - \b GPIO_PIN14 +//! - \b GPIO_PIN15 +//! \param edgeSelect specifies what transition sets the interrupt flag +//! Valid values are: +//! - \b GPIO_HIGH_TO_LOW_TRANSITION +//! - \b GPIO_LOW_TO_HIGH_TRANSITION +//! +//! Modified bits of \b PxIES register. +//! +//! \return None +// +//***************************************************************************** +extern void GPIO_selectInterruptEdge(uint8_t selectedPort, + uint16_t selectedPins, + uint8_t edgeSelect); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_GPIO_H__ diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/inc/hw_memmap.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/inc/hw_memmap.h new file mode 100644 index 000000000..39643133b --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/inc/hw_memmap.h @@ -0,0 +1,502 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +#ifndef __HW_MEMMAP__ +#define __HW_MEMMAP__ + +#define __DRIVERLIB_MSP430FR5XX_6XX_FAMILY__ +//***************************************************************************** +// +// Include device specific header file +// +//***************************************************************************** +#if defined (__MSP430FR6989__) + #include +#else + #include +#endif + +#if defined(__IAR_SYSTEMS_ICC__) +#include "../deprecated/IAR/msp430fr5xx_6xxgeneric.h" +#elif defined(__TI_COMPILER_VERSION__) +#include "../deprecated/CCS/msp430fr5xx_6xxgeneric.h" +#elif defined(__GNUC__) +#include "msp430fr5xx_6xxgeneric.h" +#else +#include "msp430fr5xx_6xxgeneric.h" +#endif + +#include "stdint.h" +#include "stdbool.h" + +//***************************************************************************** +// +// SUCCESS and FAILURE for API return value +// +//***************************************************************************** +#define STATUS_SUCCESS 0x01 +#define STATUS_FAIL 0x00 + +//***************************************************************************** +// +// The following are defines for the base address of the peripherals. +// +//***************************************************************************** +#ifdef __MSP430_HAS_ADC10_A__ + #define \ + ADC10_A_BASE __MSP430_BASEADDRESS_ADC10_A__ +#endif +#ifdef __MSP430_HAS_ADC10_B__ + #define \ + ADC10_B_BASE __MSP430_BASEADDRESS_ADC10_B__ +#endif +#ifdef __MSP430_HAS_ADC12_B__ + #define \ + ADC12_B_BASE __MSP430_BASEADDRESS_ADC12_B__ +#endif +#ifdef __MSP430_HAS_ADC12_PLUS__ + #define \ + ADC12_A_BASE __MSP430_BASEADDRESS_ADC12_PLUS__ +#endif +#ifdef __MSP430_HAS_AES256__ + #define \ + AES256_BASE __MSP430_BASEADDRESS_AES256__ +#endif +#ifdef __MSP430_HAS_AES__ + #define \ + AES_BASE __MSP430_BASEADDRESS_AES__ +#endif +#ifdef __MSP430_HAS_AUX_SUPPLY__ + #define \ + AUX_SUPPLY_BASE __MSP430_BASEADDRESS_AUX_SUPPLY__ +#endif +#ifdef __MSP430_HAS_BACKUP_RAM__ + #define \ + BAK_RAM_BASE __MSP430_BASEADDRESS_BACKUP_RAM__ +#endif +#ifdef __MSP430_HAS_BATTERY_CHARGER__ + #define \ + BAK_BATT_BASE __MSP430_BASEADDRESS_BATTERY_CHARGER__ +#endif +#ifdef __MSP430_HAS_CAP_SENSE_IO_0__ + #define \ + CAP_TOUCH_0_BASE __MSP430_BASEADDRESS_CAP_SENSE_IO_0__ +#endif +#ifdef __MSP430_HAS_CAP_SENSE_IO_1__ + #define \ + CAP_TOUCH_1_BASE __MSP430_BASEADDRESS_CAP_SENSE_IO_1__ +#endif +#ifdef __MSP430_HAS_COMPB__ + #define \ + COMP_B_BASE __MSP430_BASEADDRESS_COMPB__ +#endif +#ifdef __MSP430_HAS_COMPD__ + #define \ + COMP_D_BASE __MSP430_BASEADDRESS_COMPD__ +#endif +#ifdef __MSP430_HAS_COMP_E__ + #define \ + COMP_E_BASE __MSP430_BASEADDRESS_COMP_E__ +#endif +#ifdef __MSP430_HAS_COMPE__ + #define \ + __MSP430_BASEADDRESS_COMP_E__ __MSP430_BASEADDRESS_COMPE__ +#ifndef COMP_E_VECTOR +#ifdef COMP_B_VECTOR +#define COMP_E_VECTOR COMP_B_VECTOR +#endif +#endif + +#ifndef COMP_B_VECTOR +#ifdef COMP_E_VECTOR +#define COMP_B_VECTOR COMP_E_VECTOR +#endif +#endif +#endif + +#ifdef __MSP430_HAS_COMP_E__ + #define \ + __MSP430_BASEADDRESS_COMPE__ __MSP430_BASEADDRESS_COMP_E__ +#ifndef COMP_B_VECTOR +#ifdef COMP_E_VECTOR +#define COMP_B_VECTOR COMP_E_VECTOR +#endif +#endif +#ifndef COMP_E_VECTOR +#ifdef COMP_B_VECTOR +#define COMP_E_VECTOR COMP_B_VECTOR +#endif +#endif +#endif +#ifdef __MSP430_HAS_CRC__ + #define \ + CRC_BASE __MSP430_BASEADDRESS_CRC__ +#endif +#ifdef __MSP430_HAS_CS__ + +#ifndef __MSP430_BASEADDRESS_CS_A__ +#define __MSP430_BASEADDRESS_CS_A__ __MSP430_BASEADDRESS_CS__ +#endif +#endif +#ifdef __MSP430_HAS_CS_A__ + #define \ + CS_BASE __MSP430_BASEADDRESS_CS_A__ +#ifndef __MSP430_BASEADDRESS_CS__ +#define __MSP430_BASEADDRESS_CS__ __MSP430_BASEADDRESS_CS_A__ +#endif +#endif +#ifdef __MSP430_HAS_DAC12_2__ + #define \ + DAC12_A_BASE __MSP430_BASEADDRESS_DAC12_2__ +#endif +#ifdef __MSP430_HAS_DMAX_3__ + #define \ + DMA_BASE __MSP430_BASEADDRESS_DMAX_3__ +#endif +#ifdef __MSP430_HAS_DMAX_6__ + #define \ + DMA_BASE __MSP430_BASEADDRESS_DMAX_6__ +#endif +#ifdef __MSP430_HAS_EUSCI_A0__ + #define \ + EUSCI_A0_BASE __MSP430_BASEADDRESS_EUSCI_A0__ +#endif +#ifdef __MSP430_HAS_EUSCI_A1__ + #define \ + EUSCI_A1_BASE __MSP430_BASEADDRESS_EUSCI_A1__ +#endif +#ifdef __MSP430_HAS_EUSCI_A2__ + #define \ + EUSCI_A2_BASE __MSP430_BASEADDRESS_EUSCI_A2__ +#endif +#ifdef __MSP430_HAS_EUSCI_A3__ + #define \ + EUSCI_A3_BASE __MSP430_BASEADDRESS_EUSCI_A3__ +#endif +#ifdef __MSP430_HAS_EUSCI_B0__ + #define \ + EUSCI_B0_BASE __MSP430_BASEADDRESS_EUSCI_B0__ +#endif +#ifdef __MSP430_HAS_EUSCI_B1__ + #define \ + EUSCI_B1_BASE __MSP430_BASEADDRESS_EUSCI_B1__ +#endif +#ifdef __MSP430_HAS_FLASH__ + #define \ + FLASH_BASE __MSP430_BASEADDRESS_FLASH__ +#endif +#ifdef __MSP430_HAS_FRAM_FR5XX__ + #define \ + FRAM_BASE __MSP430_BASEADDRESS_FRAM_FR5XX__ +#endif +#ifdef __MSP430_HAS_FRAM__ + #define \ + FRAM_BASE __MSP430_BASEADDRESS_FRAM__ +#endif +#ifdef __MSP430_HAS_LCD_B__ + #define \ + LCD_B_BASE __MSP430_BASEADDRESS_LCD_B__ +#endif +#ifdef __MSP430_HAS_LCD_C__ + #define \ + LCD_C_BASE __MSP430_BASEADDRESS_LCD_C__ +#endif +#ifdef __MSP430_HAS_MPU_A__ + #define \ + MPU_BASE __MSP430_BASEADDRESS_MPU_A__ +#ifndef __MSP430_BASEADDRESS_MPU__ +#define __MSP430_BASEADDRESS_MPU__ __MSP430_BASEADDRESS_MPU_A__ +#endif +#endif +#ifdef __MSP430_HAS_MPU__ + +#ifndef __MSP430_BASEADDRESS_MPU_A__ +#define __MSP430_BASEADDRESS_MPU_A__ __MSP430_BASEADDRESS_MPU__ +#endif +#endif +#ifdef __MSP430_HAS_MPY32__ + #define \ + MPY32_BASE __MSP430_BASEADDRESS_MPY32__ +#endif +#ifdef __MSP430_HAS_PMM_FR5xx__ + #define \ + PMM_BASE __MSP430_BASEADDRESS_PMM_FR5xx__ +#endif +#ifdef __MSP430_HAS_PMM_FRAM__ + #define \ + PMM_BASE __MSP430_BASEADDRESS_PMM_FRAM__ +#endif +#ifdef __MSP430_HAS_PMM__ + #define \ + PMM_BASE __MSP430_BASEADDRESS_PMM__ +#endif +#ifdef __MSP430_HAS_PORT10_R__ + #define \ + P10_BASE __MSP430_BASEADDRESS_PORT10_R__ +#endif +#ifdef __MSP430_HAS_PORT11_R__ + #define \ + P11_BASE __MSP430_BASEADDRESS_PORT11_R__ +#endif +#ifdef __MSP430_HAS_PORT1_MAPPING__ + #define \ + P1MAP_BASE __MSP430_BASEADDRESS_PORT1_MAPPING__ +#endif +#ifdef __MSP430_HAS_PORT1_R__ + #define \ + P1_BASE __MSP430_BASEADDRESS_PORT1_R__ +#endif +#ifdef __MSP430_HAS_PORT2_MAPPING__ + #define \ + P2MAP_BASE __MSP430_BASEADDRESS_PORT2_MAPPING__ +#endif +#ifdef __MSP430_HAS_PORT2_R__ + #define \ + P2_BASE __MSP430_BASEADDRESS_PORT2_R__ +#endif +#ifdef __MSP430_HAS_PORT3_MAPPING__ + #define \ + P3MAP_BASE __MSP430_BASEADDRESS_PORT3_MAPPING__ +#endif +#ifdef __MSP430_HAS_PORT3_R__ + #define \ + P3_BASE __MSP430_BASEADDRESS_PORT3_R__ +#endif +#ifdef __MSP430_HAS_PORT4_MAPPING__ + #define \ + P4MAP_BASE __MSP430_BASEADDRESS_PORT4_MAPPING__ +#endif +#ifdef __MSP430_HAS_PORT4_R__ + #define \ + P4_BASE __MSP430_BASEADDRESS_PORT4_R__ +#endif +#ifdef __MSP430_HAS_PORT5_R__ + #define \ + P5_BASE __MSP430_BASEADDRESS_PORT5_R__ +#endif +#ifdef __MSP430_HAS_PORT6_R__ + #define \ + P6_BASE __MSP430_BASEADDRESS_PORT6_R__ +#endif +#ifdef __MSP430_HAS_PORT7_R__ + #define \ + P7_BASE __MSP430_BASEADDRESS_PORT7_R__ +#endif +#ifdef __MSP430_HAS_PORT8_R__ + #define \ + P8_BASE __MSP430_BASEADDRESS_PORT8_R__ +#endif +#ifdef __MSP430_HAS_PORT9_R__ + #define \ + P9_BASE __MSP430_BASEADDRESS_PORT9_R__ +#endif +#ifdef __MSP430_HAS_PORTA_R__ + #define \ + PA_BASE __MSP430_BASEADDRESS_PORTA_R__ +#endif +#ifdef __MSP430_HAS_PORTB_R__ + #define \ + PB_BASE __MSP430_BASEADDRESS_PORTB_R__ +#endif +#ifdef __MSP430_HAS_PORTC_R__ + #define \ + PC_BASE __MSP430_BASEADDRESS_PORTC_R__ +#endif +#ifdef __MSP430_HAS_PORTD_R__ + #define \ + PD_BASE __MSP430_BASEADDRESS_PORTD_R__ +#endif +#ifdef __MSP430_HAS_PORTE_R__ + #define \ + PE_BASE __MSP430_BASEADDRESS_PORTE_R__ +#endif +#ifdef __MSP430_HAS_PORTF_R__ + #define \ + PF_BASE __MSP430_BASEADDRESS_PORTF_R__ +#endif +#ifdef __MSP430_HAS_PORTJ_R__ + #define \ + PJ_BASE __MSP430_BASEADDRESS_PORTJ_R__ +#endif +#ifdef __MSP430_HAS_PORT_MAPPING__ + #define \ + PMAP_CTRL_BASE __MSP430_BASEADDRESS_PORT_MAPPING__ +#endif +#ifdef __MSP430_HAS_PU__ + #define \ + LDOPWR_BASE __MSP430_BASEADDRESS_PU__ +#endif +#ifdef __MSP430_HAS_RC__ + #define \ + RAM_BASE __MSP430_BASEADDRESS_RC__ +#endif +#ifdef __MSP430_HAS_REF_A__ + #define \ + REF_A_BASE __MSP430_BASEADDRESS_REF_A__ +#endif +#ifdef __MSP430_HAS_REF__ + #define \ + REF_BASE __MSP430_BASEADDRESS_REF__ +#endif +#ifdef __MSP430_HAS_RTC_B__ + #define \ + RTC_B_BASE __MSP430_BASEADDRESS_RTC_B__ +#endif +#ifdef __MSP430_HAS_RTC_C__ + #define \ + RTC_C_BASE __MSP430_BASEADDRESS_RTC_C__ +#endif +#ifdef __MSP430_HAS_RTC_D__ + #define \ + RTC_D_BASE __MSP430_BASEADDRESS_RTC_D__ +#endif +#ifdef __MSP430_HAS_RTC__ + #define \ + RTC_A_BASE __MSP430_BASEADDRESS_RTC__ +#endif +#ifdef __MSP430_HAS_SD24_B__ + #define \ + SD24_BASE __MSP430_BASEADDRESS_SD24_B__ +#endif +#ifdef __MSP430_HAS_SFR__ + #define \ + SFR_BASE __MSP430_BASEADDRESS_SFR__ +#endif +#ifdef __MSP430_HAS_SYS__ + #define \ + SYS_BASE __MSP430_BASEADDRESS_SYS__ +#endif +#ifdef __MSP430_HAS_T0A3__ + #define \ + TIMER_A0_BASE __MSP430_BASEADDRESS_T0A3__ +#endif +#ifdef __MSP430_HAS_T0A5__ + #define \ + TIMER_A0_BASE __MSP430_BASEADDRESS_T0A5__ +#endif +#ifdef __MSP430_HAS_T0B3__ + #define \ + TIMER_B0_BASE __MSP430_BASEADDRESS_T0B3__ +#endif +#ifdef __MSP430_HAS_T0B7__ + #define \ + TIMER_B0_BASE __MSP430_BASEADDRESS_T0B7__ +#endif +#ifdef __MSP430_HAS_T0D3__ + #define \ + TIMER_D0_BASE __MSP430_BASEADDRESS_T0D3__ +#endif +#ifdef __MSP430_HAS_T1A2__ + #define \ + TIMER_A1_BASE __MSP430_BASEADDRESS_T1A2__ +#endif +#ifdef __MSP430_HAS_T1A3__ + #define \ + TIMER_A1_BASE __MSP430_BASEADDRESS_T1A3__ +#endif +#ifdef __MSP430_HAS_T1B3__ + #define \ + TIMER_B1_BASE __MSP430_BASEADDRESS_T1B3__ +#endif +#ifdef __MSP430_HAS_T1D3__ + #define \ + TIMER_D1_BASE __MSP430_BASEADDRESS_T1D3__ +#endif +#ifdef __MSP430_HAS_T2A2__ + #define \ + TIMER_A2_BASE __MSP430_BASEADDRESS_T2A2__ +#endif +#ifdef __MSP430_HAS_T2A3__ + #define \ + TIMER_A2_BASE __MSP430_BASEADDRESS_T2A3__ +#endif +#ifdef __MSP430_HAS_T2B3__ + #define \ + TIMER_B2_BASE __MSP430_BASEADDRESS_T2B3__ +#endif +#ifdef __MSP430_HAS_T3A2__ + #define \ + TIMER_A3_BASE __MSP430_BASEADDRESS_T3A2__ +#endif +#ifdef __MSP430_HAS_TEV0__ + #define \ + TEC0_BASE __MSP430_BASEADDRESS_TEV0__ +#endif +#ifdef __MSP430_HAS_TEV1__ + #define \ + TEC1_BASE __MSP430_BASEADDRESS_TEV1__ +#endif +#ifdef __MSP430_HAS_UCS__ + #define \ + UCS_BASE __MSP430_BASEADDRESS_UCS__ +#endif +#ifdef __MSP430_HAS_USB__ + #define \ + USB_BASE __MSP430_BASEADDRESS_USB__ +#endif +#ifdef __MSP430_HAS_USCI_A0__ + #define \ + USCI_A0_BASE __MSP430_BASEADDRESS_USCI_A0__ +#endif +#ifdef __MSP430_HAS_USCI_A1__ + #define \ + USCI_A1_BASE __MSP430_BASEADDRESS_USCI_A1__ +#endif +#ifdef __MSP430_HAS_USCI_A2__ + #define \ + USCI_A2_BASE __MSP430_BASEADDRESS_USCI_A2__ +#endif +#ifdef __MSP430_HAS_USCI_A3__ + #define \ + USCI_A3_BASE __MSP430_BASEADDRESS_USCI_A3__ +#endif +#ifdef __MSP430_HAS_USCI_B0__ + #define \ + USCI_B0_BASE __MSP430_BASEADDRESS_USCI_B0__ +#endif +#ifdef __MSP430_HAS_USCI_B1__ + #define \ + USCI_B1_BASE __MSP430_BASEADDRESS_USCI_B1__ +#endif +#ifdef __MSP430_HAS_USCI_B2__ + #define \ + USCI_B2_BASE __MSP430_BASEADDRESS_USCI_B2__ +#endif +#ifdef __MSP430_HAS_USCI_B3__ + #define \ + USCI_B3_BASE __MSP430_BASEADDRESS_USCI_B3__ +#endif +#ifdef __MSP430_HAS_WDT_A__ + #define \ + WDT_A_BASE __MSP430_BASEADDRESS_WDT_A__ +#endif + +#endif // #ifndef __HW_MEMMAP__ diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/inc/hw_regaccess.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/inc/hw_regaccess.h new file mode 100644 index 000000000..a2b58d71c --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/inc/hw_regaccess.h @@ -0,0 +1,64 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +#ifndef __HW_REGACCESS__ +#define __HW_REGACCESS__ + +#include "stdint.h" +#include "stdbool.h" + +//***************************************************************************** +// +// Macro for enabling assert statements for debugging +// +//***************************************************************************** +#define NDEBUG +//***************************************************************************** +// +// Macros for hardware access +// +//***************************************************************************** +#define HWREG32(x) \ + (*((volatile uint32_t *)((uint16_t)x))) +#define HWREG16(x) \ + (*((volatile uint16_t *)((uint16_t)x))) +#define HWREG8(x) \ + (*((volatile uint8_t *)((uint16_t)x))) + +//***************************************************************************** +// +// SUCCESS and FAILURE for API return value +// +//***************************************************************************** +#define STATUS_SUCCESS 0x01 +#define STATUS_FAIL 0x00 + +#endif // #ifndef __HW_REGACCESS__ diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/inc/hw_types.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/inc/hw_types.h new file mode 100644 index 000000000..cd9ed02a5 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/inc/hw_types.h @@ -0,0 +1,60 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +#ifndef __HW_TYPES__ +#define __HW_TYPES__ + +//***************************************************************************** +// +// Macro for enabling assert statements for debugging +// +//***************************************************************************** +#define NDEBUG + +//***************************************************************************** +// +// Macros for hardware access +// +//***************************************************************************** +#define HWREG(x) \ + (*((volatile unsigned int *)(x))) +#define HWREGB(x) \ + (*((volatile unsigned char *)(x))) + +//***************************************************************************** +// +// SUCCESS and FAILURE for API return value +// +//***************************************************************************** +#define STATUS_SUCCESS 0x01 +#define STATUS_FAIL 0x00 + +#endif // #ifndef __HW_TYPES__ diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/inc/version.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/inc/version.h new file mode 100644 index 000000000..e0e024974 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/inc/version.h @@ -0,0 +1,42 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +#ifndef __DRIVERLIB_VERSION__ + #define DRIVERLIB_VER_MAJOR 2 + #define DRIVERLIB_VER_MINOR 00 + #define DRIVERLIB_VER_PATCH 00 + #define DRIVERLIB_VER_BUILD 16 +#endif + +#define getVersion() ((uint32_t)DRIVERLIB_VER_MAJOR << 24 | \ + (uint32_t)DRIVERLIB_VER_MINOR << 16 | \ + (uint32_t)DRIVERLIB_VER_PATCH << 8 | \ + (uint32_t)DRIVERLIB_VER_BUILD) diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/lcd_c.c b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/lcd_c.c new file mode 100644 index 000000000..7286ac937 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/lcd_c.c @@ -0,0 +1,371 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// lcd_c.c - Driver for the lcd_c Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup lcd_c_api lcd_c +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_LCD_C__ +#include "lcd_c.h" + +#include + +//***************************************************************************** +// +// Initialization parameter instance +// +//***************************************************************************** +const LCD_C_initParam LCD_C_INIT_PARAM = { + LCD_C_CLOCKSOURCE_ACLK, + LCD_C_CLOCKDIVIDER_1, + LCD_C_CLOCKPRESCALAR_1, + LCD_C_STATIC, + LCD_C_STANDARD_WAVEFORMS, + LCD_C_SEGMENTS_DISABLED +}; + +static void setLCDFunction(uint16_t baseAddress, + uint8_t index, + uint16_t value) +{ + switch(index) + { + case 0: + HWREG16(baseAddress + OFS_LCDCPCTL0) |= value; + break; + case 1: + HWREG16(baseAddress + OFS_LCDCPCTL1) |= value; + break; + case 2: + HWREG16(baseAddress + OFS_LCDCPCTL2) |= value; + break; + case 3: + HWREG16(baseAddress + OFS_LCDCPCTL3) |= value; + break; + default: break; + } +} + +void LCD_C_init(uint16_t baseAddress, + LCD_C_initParam *initParams) +{ + HWREG16(baseAddress + OFS_LCDCCTL0) &= ~LCDON; + HWREG16(baseAddress + OFS_LCDCCTL0) &= ~(LCDMX0 | LCDMX1 | LCDMX2 | LCDSSEL + | LCDLP | LCDSON | LCDDIV_31); + + HWREG16(baseAddress + OFS_LCDCCTL0) |= initParams->muxRate; + HWREG16(baseAddress + OFS_LCDCCTL0) |= initParams->clockSource; + HWREG16(baseAddress + OFS_LCDCCTL0) |= initParams->waveforms; + HWREG16(baseAddress + OFS_LCDCCTL0) |= initParams->segments; + HWREG16(baseAddress + OFS_LCDCCTL0) |= initParams->clockDivider; + HWREG16(baseAddress + OFS_LCDCCTL0) |= initParams->clockPrescalar; +} + +void LCD_C_on(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_LCDCCTL0) |= LCDON; +} + +void LCD_C_off(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_LCDCCTL0) &= ~LCDON; +} + +void LCD_C_clearInterrupt(uint16_t baseAddress, + uint16_t mask) +{ + HWREG8(baseAddress + OFS_LCDCCTL1_L) &= ~(mask >> 8); +} + +uint16_t LCD_C_getInterruptStatus(uint16_t baseAddress, + uint16_t mask) +{ + return (HWREG8(baseAddress + OFS_LCDCCTL1_L) & (mask >> 8)); +} + +void LCD_C_enableInterrupt(uint16_t baseAddress, + uint16_t mask) +{ + HWREG16(baseAddress + OFS_LCDCCTL1) |= mask; +} + +void LCD_C_disableInterrupt(uint16_t baseAddress, + uint16_t mask) +{ + HWREG16(baseAddress + OFS_LCDCCTL1) &= ~mask; +} + +void LCD_C_clearMemory(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_LCDCMEMCTL) |= LCDCLRM; +} + +void LCD_C_clearBlinkingMemory(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_LCDCMEMCTL) |= LCDCLRBM; +} + +void LCD_C_selectDisplayMemory(uint16_t baseAddress, + uint16_t displayMemory) +{ + HWREG16(baseAddress + OFS_LCDCMEMCTL) &= ~LCDDISP; + HWREG16(baseAddress + OFS_LCDCMEMCTL) |= displayMemory; +} + +void LCD_C_setBlinkingControl(uint16_t baseAddress, + uint8_t clockDivider, + uint8_t clockPrescalar, + uint8_t mode) +{ + HWREG16(baseAddress + + OFS_LCDCBLKCTL) &= ~(LCDBLKDIV0 | LCDBLKDIV1 | LCDBLKDIV2 | + LCDBLKPRE0 | LCDBLKPRE1 | + LCDBLKPRE2 | + LCDBLKMOD0 | LCDBLKMOD1 + ); + HWREG16(baseAddress + + OFS_LCDCBLKCTL) |= clockDivider | clockPrescalar | mode; +} + +void LCD_C_enableChargePump(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_LCDCCTL0) &= ~LCDON; + HWREG16(baseAddress + OFS_LCDCVCTL) |= LCDCPEN; +} + +void LCD_C_disableChargePump(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_LCDCCTL0) &= ~LCDON; + HWREG16(baseAddress + OFS_LCDCVCTL) &= ~LCDCPEN; +} + +void LCD_C_selectBias(uint16_t baseAddress, + uint16_t bias) +{ + HWREG16(baseAddress + OFS_LCDCCTL0) &= ~LCDON; + HWREG16(baseAddress + OFS_LCDCVCTL) &= ~LCD2B; + + HWREG16(baseAddress + OFS_LCDCVCTL) |= bias; +} + +void LCD_C_selectChargePumpReference(uint16_t baseAddress, + uint16_t reference) +{ + HWREG16(baseAddress + OFS_LCDCCTL0) &= ~LCDON; + HWREG16(baseAddress + OFS_LCDCVCTL) &= ~VLCDREF_3; + + HWREG16(baseAddress + OFS_LCDCVCTL) |= reference; +} + +void LCD_C_setVLCDSource(uint16_t baseAddress, + uint16_t vlcdSource, + uint16_t v2v3v4Source, + uint16_t v5Source) +{ + HWREG16(baseAddress + OFS_LCDCCTL0) &= ~LCDON; + HWREG16(baseAddress + OFS_LCDCVCTL) &= ~VLCDEXT; + HWREG16(baseAddress + OFS_LCDCVCTL) &= ~LCDREXT; + HWREG16(baseAddress + OFS_LCDCVCTL) &= ~LCDEXTBIAS; + HWREG16(baseAddress + OFS_LCDCVCTL) &= ~R03EXT; + + HWREG16(baseAddress + OFS_LCDCVCTL) |= vlcdSource; + HWREG16(baseAddress + OFS_LCDCVCTL) |= v2v3v4Source; + HWREG16(baseAddress + OFS_LCDCVCTL) |= v5Source; +} + +void LCD_C_setVLCDVoltage(uint16_t baseAddress, + uint16_t voltage) +{ + HWREG16(baseAddress + OFS_LCDCCTL0) &= ~LCDON; + HWREG16(baseAddress + OFS_LCDCVCTL) &= ~VLCD_15; + + HWREG16(baseAddress + OFS_LCDCVCTL) |= voltage; +} + +void LCD_C_setPinAsLCDFunction(uint16_t baseAddress, + uint8_t pin) +{ + HWREG16(baseAddress + OFS_LCDCCTL0) &= ~LCDON; + + uint8_t idx = pin >> 4; + uint16_t val = 1 << (pin & 0xF); + + setLCDFunction(baseAddress, idx, val); +} + +void LCD_C_setPinAsPortFunction(uint16_t baseAddress, + uint8_t pin) +{ + HWREG16(baseAddress + OFS_LCDCCTL0) &= ~LCDON; + + uint8_t idx = pin >> 4; + uint16_t val = 1 << (pin & 0xF); + + switch(idx) + { + case 0: + HWREG16(baseAddress + OFS_LCDCPCTL0) &= ~val; + break; + case 1: + HWREG16(baseAddress + OFS_LCDCPCTL1) &= ~val; + break; + case 2: + HWREG16(baseAddress + OFS_LCDCPCTL2) &= ~val; + break; + case 3: + HWREG16(baseAddress + OFS_LCDCPCTL3) &= ~val; + break; + default: break; + } +} + +void LCD_C_setPinAsLCDFunctionEx(uint16_t baseAddress, + uint8_t startPin, + uint8_t endPin) +{ + uint8_t startIdx = startPin >> 4; + uint8_t endIdx = endPin >> 4; + uint8_t startPos = startPin & 0xF; + uint8_t endPos = endPin & 0xF; + uint16_t val = 0; + uint8_t i = 0; + + HWREG16(baseAddress + OFS_LCDCCTL0) &= ~LCDON; + + if(startIdx == endIdx) + { + val = (0xFFFF >> (15 - endPos)) & (0xFFFF << startPos); + + setLCDFunction(baseAddress, startIdx, val); + } + else + { + val = 0xFFFF >> (15 - endPos); + setLCDFunction(baseAddress, endIdx, val); + + for(i = endIdx - 1; i > startIdx; i--) + { + setLCDFunction(baseAddress, i, 0xFFFF); + } + + val = 0xFFFF << startPos; + setLCDFunction(baseAddress, startIdx, val); + } +} + +void LCD_C_setMemory(uint16_t baseAddress, + uint8_t pin, + uint8_t value) +{ + uint8_t muxRate = HWREG16(baseAddress + OFS_LCDCCTL0) + & (LCDMX2 | LCDMX1 | LCDMX0); + + // static, 2-mux, 3-mux, 4-mux + if(muxRate <= (LCDMX1 | LCDMX0)) + { + if(pin & 1) + { + HWREG8(baseAddress + OFS_LCDM1 + pin / 2) &= 0x0F; + HWREG8(baseAddress + OFS_LCDM1 + pin / 2) |= (value & 0xF) << 4; + } + else + { + HWREG8(baseAddress + OFS_LCDM1 + pin / 2) &= 0xF0; + HWREG8(baseAddress + OFS_LCDM1 + pin / 2) |= (value & 0xF); + } + } + else + { + //5-mux, 6-mux, 7-mux, 8-mux + HWREG8(baseAddress + OFS_LCDM1 + pin) = value; + } +} + +void LCD_C_setBlinkingMemory(uint16_t baseAddress, + uint8_t pin, + uint8_t value) +{ + uint8_t muxRate = HWREG16(baseAddress + OFS_LCDCCTL0) + & (LCDMX2 | LCDMX1 | LCDMX0); + + // static, 2-mux, 3-mux, 4-mux + if(muxRate <= (LCDMX1 | LCDMX0)) + { + if(pin & 1) + { + HWREG8(baseAddress + OFS_LCDBM1 + pin / 2) &= 0x0F; + HWREG8(baseAddress + OFS_LCDBM1 + pin / 2) |= (value & 0xF) << 4; + } + else + { + HWREG8(baseAddress + OFS_LCDBM1 + pin / 2) &= 0xF0; + HWREG8(baseAddress + OFS_LCDBM1 + pin / 2) |= (value & 0xF); + } + } + else + { + //5-mux, 6-mux, 7-mux, 8-mux + HWREG8(baseAddress + OFS_LCDBM1 + pin) = value; + } +} + +void LCD_C_configChargePump(uint16_t baseAddress, + uint16_t syncToClock, + uint16_t functionControl) +{ + HWREG16(baseAddress + OFS_LCDCCPCTL) &= ~(LCDCPCLKSYNC); + HWREG16(baseAddress + OFS_LCDCCPCTL) &= ~(LCDCPDIS7 | LCDCPDIS6 | LCDCPDIS5 + | LCDCPDIS4 | LCDCPDIS3 | + LCDCPDIS2 | LCDCPDIS1 | + LCDCPDIS0); + + HWREG16(baseAddress + OFS_LCDCCPCTL) |= syncToClock | functionControl; +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for lcd_c_api +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/lcd_c.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/lcd_c.h new file mode 100644 index 000000000..3ff950539 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/lcd_c.h @@ -0,0 +1,1327 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// lcd_c.h - Driver for the LCD_C Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_LCD_C_H__ +#define __MSP430WARE_LCD_C_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_LCD_C__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "inc/hw_regaccess.h" +//***************************************************************************** +// +//! \brief Used in the LCD_C_init() function as the initParams parameter. +// +//***************************************************************************** +typedef struct LCD_C_initParam +{ + //! Selects the clock that will be used by the LCD. + //! \n Valid values are: + //! - \b LCD_C_CLOCKSOURCE_ACLK [Default] + //! - \b LCD_C_CLOCKSOURCE_VLOCLK + uint16_t clockSource; + //! Selects the divider for LCD_frequency. + //! \n Valid values are: + //! - \b LCD_C_CLOCKDIVIDER_1 [Default] + //! - \b LCD_C_CLOCKDIVIDER_2 + //! - \b LCD_C_CLOCKDIVIDER_3 + //! - \b LCD_C_CLOCKDIVIDER_4 + //! - \b LCD_C_CLOCKDIVIDER_5 + //! - \b LCD_C_CLOCKDIVIDER_6 + //! - \b LCD_C_CLOCKDIVIDER_7 + //! - \b LCD_C_CLOCKDIVIDER_8 + //! - \b LCD_C_CLOCKDIVIDER_9 + //! - \b LCD_C_CLOCKDIVIDER_10 + //! - \b LCD_C_CLOCKDIVIDER_11 + //! - \b LCD_C_CLOCKDIVIDER_12 + //! - \b LCD_C_CLOCKDIVIDER_13 + //! - \b LCD_C_CLOCKDIVIDER_14 + //! - \b LCD_C_CLOCKDIVIDER_15 + //! - \b LCD_C_CLOCKDIVIDER_16 + //! - \b LCD_C_CLOCKDIVIDER_17 + //! - \b LCD_C_CLOCKDIVIDER_18 + //! - \b LCD_C_CLOCKDIVIDER_19 + //! - \b LCD_C_CLOCKDIVIDER_20 + //! - \b LCD_C_CLOCKDIVIDER_21 + //! - \b LCD_C_CLOCKDIVIDER_22 + //! - \b LCD_C_CLOCKDIVIDER_23 + //! - \b LCD_C_CLOCKDIVIDER_24 + //! - \b LCD_C_CLOCKDIVIDER_25 + //! - \b LCD_C_CLOCKDIVIDER_26 + //! - \b LCD_C_CLOCKDIVIDER_27 + //! - \b LCD_C_CLOCKDIVIDER_28 + //! - \b LCD_C_CLOCKDIVIDER_29 + //! - \b LCD_C_CLOCKDIVIDER_30 + //! - \b LCD_C_CLOCKDIVIDER_31 + //! - \b LCD_C_CLOCKDIVIDER_32 + uint16_t clockDivider; + //! Selects the prescalar for frequency. + //! \n Valid values are: + //! - \b LCD_C_CLOCKPRESCALAR_1 [Default] + //! - \b LCD_C_CLOCKPRESCALAR_2 + //! - \b LCD_C_CLOCKPRESCALAR_4 + //! - \b LCD_C_CLOCKPRESCALAR_8 + //! - \b LCD_C_CLOCKPRESCALAR_16 + //! - \b LCD_C_CLOCKPRESCALAR_32 + uint16_t clockPrescalar; + //! Selects LCD mux rate. + //! \n Valid values are: + //! - \b LCD_C_STATIC [Default] + //! - \b LCD_C_2_MUX + //! - \b LCD_C_3_MUX + //! - \b LCD_C_4_MUX + //! - \b LCD_C_5_MUX + //! - \b LCD_C_6_MUX + //! - \b LCD_C_7_MUX + //! - \b LCD_C_8_MUX + uint16_t muxRate; + //! Selects LCD waveform mode. + //! \n Valid values are: + //! - \b LCD_C_STANDARD_WAVEFORMS [Default] + //! - \b LCD_C_LOW_POWER_WAVEFORMS + uint16_t waveforms; + //! Sets LCD segment on/off. + //! \n Valid values are: + //! - \b LCD_C_SEGMENTS_DISABLED [Default] + //! - \b LCD_C_SEGMENTS_ENABLED + uint16_t segments; +} LCD_C_initParam; + +extern const LCD_C_initParam LCD_C_INIT_PARAM; + +//***************************************************************************** +// +// The following are values that can be passed to the initParams parameter for +// functions: LCD_C_init(). +// +//***************************************************************************** +#define LCD_C_CLOCKSOURCE_ACLK (0x0) +#define LCD_C_CLOCKSOURCE_VLOCLK (LCDSSEL) + +//***************************************************************************** +// +// The following are values that can be passed to the initParams parameter for +// functions: LCD_C_init(). +// +//***************************************************************************** +#define LCD_C_CLOCKDIVIDER_1 (LCDDIV_0) +#define LCD_C_CLOCKDIVIDER_2 (LCDDIV_1) +#define LCD_C_CLOCKDIVIDER_3 (LCDDIV_2) +#define LCD_C_CLOCKDIVIDER_4 (LCDDIV_3) +#define LCD_C_CLOCKDIVIDER_5 (LCDDIV_4) +#define LCD_C_CLOCKDIVIDER_6 (LCDDIV_5) +#define LCD_C_CLOCKDIVIDER_7 (LCDDIV_6) +#define LCD_C_CLOCKDIVIDER_8 (LCDDIV_7) +#define LCD_C_CLOCKDIVIDER_9 (LCDDIV_8) +#define LCD_C_CLOCKDIVIDER_10 (LCDDIV_9) +#define LCD_C_CLOCKDIVIDER_11 (LCDDIV_10) +#define LCD_C_CLOCKDIVIDER_12 (LCDDIV_11) +#define LCD_C_CLOCKDIVIDER_13 (LCDDIV_12) +#define LCD_C_CLOCKDIVIDER_14 (LCDDIV_13) +#define LCD_C_CLOCKDIVIDER_15 (LCDDIV_14) +#define LCD_C_CLOCKDIVIDER_16 (LCDDIV_15) +#define LCD_C_CLOCKDIVIDER_17 (LCDDIV_16) +#define LCD_C_CLOCKDIVIDER_18 (LCDDIV_17) +#define LCD_C_CLOCKDIVIDER_19 (LCDDIV_18) +#define LCD_C_CLOCKDIVIDER_20 (LCDDIV_19) +#define LCD_C_CLOCKDIVIDER_21 (LCDDIV_20) +#define LCD_C_CLOCKDIVIDER_22 (LCDDIV_21) +#define LCD_C_CLOCKDIVIDER_23 (LCDDIV_22) +#define LCD_C_CLOCKDIVIDER_24 (LCDDIV_23) +#define LCD_C_CLOCKDIVIDER_25 (LCDDIV_24) +#define LCD_C_CLOCKDIVIDER_26 (LCDDIV_25) +#define LCD_C_CLOCKDIVIDER_27 (LCDDIV_26) +#define LCD_C_CLOCKDIVIDER_28 (LCDDIV_27) +#define LCD_C_CLOCKDIVIDER_29 (LCDDIV_28) +#define LCD_C_CLOCKDIVIDER_30 (LCDDIV_29) +#define LCD_C_CLOCKDIVIDER_31 (LCDDIV_30) +#define LCD_C_CLOCKDIVIDER_32 (LCDDIV_31) + +//***************************************************************************** +// +// The following are values that can be passed to the initParams parameter for +// functions: LCD_C_init(). +// +//***************************************************************************** +#define LCD_C_CLOCKPRESCALAR_1 (LCDPRE_0) +#define LCD_C_CLOCKPRESCALAR_2 (LCDPRE_1) +#define LCD_C_CLOCKPRESCALAR_4 (LCDPRE_2) +#define LCD_C_CLOCKPRESCALAR_8 (LCDPRE_3) +#define LCD_C_CLOCKPRESCALAR_16 (LCDPRE_4) +#define LCD_C_CLOCKPRESCALAR_32 (LCDPRE_5) + +//***************************************************************************** +// +// The following are values that can be passed to the initParams parameter for +// functions: LCD_C_init(). +// +//***************************************************************************** +#define LCD_C_STATIC (0x0) +#define LCD_C_2_MUX (LCDMX0) +#define LCD_C_3_MUX (LCDMX1) +#define LCD_C_4_MUX (LCDMX1 | LCDMX0) +#define LCD_C_5_MUX (LCDMX2) +#define LCD_C_6_MUX (LCDMX2 | LCDMX0) +#define LCD_C_7_MUX (LCDMX2 | LCDMX1) +#define LCD_C_8_MUX (LCDMX2 | LCDMX1 | LCDMX0) + +//***************************************************************************** +// +// The following are values that can be passed to the initParams parameter for +// functions: LCD_C_init(). +// +//***************************************************************************** +#define LCD_C_STANDARD_WAVEFORMS (0x0) +#define LCD_C_LOW_POWER_WAVEFORMS (LCDLP) + +//***************************************************************************** +// +// The following are values that can be passed to the initParams parameter for +// functions: LCD_C_init(). +// +//***************************************************************************** +#define LCD_C_SEGMENTS_DISABLED (0x0) +#define LCD_C_SEGMENTS_ENABLED (LCDSON) + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: LCD_C_clearInterrupt(), LCD_C_getInterruptStatus(), +// LCD_C_enableInterrupt(), and LCD_C_disableInterrupt() as well as returned by +// the LCD_C_getInterruptStatus() function. +// +//***************************************************************************** +#define LCD_C_NO_CAPACITANCE_CONNECTED_INTERRUPT (LCDNOCAPIE) +#define LCD_C_BLINKING_SEGMENTS_ON_INTERRUPT (LCDBLKONIE) +#define LCD_C_BLINKING_SEGMENTS_OFF_INTERRUPT (LCDBLKOFFIE) +#define LCD_C_FRAME_INTERRUPT (LCDFRMIE) + +//***************************************************************************** +// +// The following are values that can be passed to the displayMemory parameter +// for functions: LCD_C_selectDisplayMemory(). +// +//***************************************************************************** +#define LCD_C_DISPLAYSOURCE_MEMORY (0x0) +#define LCD_C_DISPLAYSOURCE_BLINKINGMEMORY (LCDDISP) + +//***************************************************************************** +// +// The following are values that can be passed to the clockDivider parameter +// for functions: LCD_C_setBlinkingControl(). +// +//***************************************************************************** +#define LCD_C_BLINK_FREQ_CLOCK_DIVIDER_1 (0x0) +#define LCD_C_BLINK_FREQ_CLOCK_DIVIDER_2 (LCDBLKDIV0) +#define LCD_C_BLINK_FREQ_CLOCK_DIVIDER_3 (LCDBLKDIV1) +#define LCD_C_BLINK_FREQ_CLOCK_DIVIDER_4 (LCDBLKDIV0 | LCDBLKDIV1) +#define LCD_C_BLINK_FREQ_CLOCK_DIVIDER_5 (LCDBLKDIV2) +#define LCD_C_BLINK_FREQ_CLOCK_DIVIDER_6 (LCDBLKDIV2 | LCDBLKDIV0) +#define LCD_C_BLINK_FREQ_CLOCK_DIVIDER_7 (LCDBLKDIV2 | LCDBLKDIV1) +#define LCD_C_BLINK_FREQ_CLOCK_DIVIDER_8 (LCDBLKDIV2 | LCDBLKDIV1 | LCDBLKDIV0) + +//***************************************************************************** +// +// The following are values that can be passed to the clockPrescalar parameter +// for functions: LCD_C_setBlinkingControl(). +// +//***************************************************************************** +#define LCD_C_BLINK_FREQ_CLOCK_PRESCALAR_512 (0x0) +#define LCD_C_BLINK_FREQ_CLOCK_PRESCALAR_1024 (LCDBLKPRE0) +#define LCD_C_BLINK_FREQ_CLOCK_PRESCALAR_2048 (LCDBLKPRE1) +#define LCD_C_BLINK_FREQ_CLOCK_PRESCALAR_4096 (LCDBLKPRE1 | LCDBLKPRE0) +#define LCD_C_BLINK_FREQ_CLOCK_PRESCALAR_8162 (LCDBLKPRE2) +#define LCD_C_BLINK_FREQ_CLOCK_PRESCALAR_16384 (LCDBLKPRE2 | LCDBLKPRE0) +#define LCD_C_BLINK_FREQ_CLOCK_PRESCALAR_32768 (LCDBLKPRE2 | LCDBLKPRE1) +#define LCD_C_BLINK_FREQ_CLOCK_PRESCALAR_65536 \ + (LCDBLKPRE2 | LCDBLKPRE1 | LCDBLKPRE0) + +//***************************************************************************** +// +// The following are values that can be passed to the blinkingMode parameter +// for functions: LCD_C_setBlinkingControl(). +// +//***************************************************************************** +#define LCD_C_BLINK_MODE_DISABLED (LCDBLKMOD_0) +#define LCD_C_BLINK_MODE_INDIVIDUAL_SEGMENTS (LCDBLKMOD_1) +#define LCD_C_BLINK_MODE_ALL_SEGMENTS (LCDBLKMOD_2) +#define LCD_C_BLINK_MODE_SWITCHING_BETWEEN_DISPLAY_CONTENTS (LCDBLKMOD_3) + +//***************************************************************************** +// +// The following are values that can be passed to the bias parameter for +// functions: LCD_C_selectBias(). +// +//***************************************************************************** +#define LCD_C_BIAS_1_3 (0x0) +#define LCD_C_BIAS_1_2 (LCD2B) + +//***************************************************************************** +// +// The following are values that can be passed to the reference parameter for +// functions: LCD_C_selectChargePumpReference(). +// +//***************************************************************************** +#define LCD_C_INTERNAL_REFERENCE_VOLTAGE (VLCDREF_0) +#define LCD_C_EXTERNAL_REFERENCE_VOLTAGE (VLCDREF_1) +#define LCD_C_INTERNAL_REFERENCE_VOLTAGE_SWITCHED_TO_EXTERNAL_PIN (VLCDREF_2) + +//***************************************************************************** +// +// The following are values that can be passed to the vlcdSource parameter for +// functions: LCD_C_setVLCDSource(). +// +//***************************************************************************** +#define LCD_C_VLCD_GENERATED_INTERNALLY (0x0) +#define LCD_C_VLCD_SOURCED_EXTERNALLY (VLCDEXT) + +//***************************************************************************** +// +// The following are values that can be passed to the v2v3v4Source parameter +// for functions: LCD_C_setVLCDSource(). +// +//***************************************************************************** +#define LCD_C_V2V3V4_GENERATED_INTERNALLY_NOT_SWITCHED_TO_PINS (0x0) +#define LCD_C_V2V3V4_GENERATED_INTERNALLY_SWITCHED_TO_PINS (LCDREXT) +#define LCD_C_V2V3V4_SOURCED_EXTERNALLY (LCDEXTBIAS) + +//***************************************************************************** +// +// The following are values that can be passed to the v5Source parameter for +// functions: LCD_C_setVLCDSource(). +// +//***************************************************************************** +#define LCD_C_V5_VSS (0x0) +#define LCD_C_V5_SOURCED_FROM_R03 (R03EXT) + +//***************************************************************************** +// +// The following are values that can be passed to the voltage parameter for +// functions: LCD_C_setVLCDVoltage(). +// +//***************************************************************************** +#define LCD_C_CHARGEPUMP_DISABLED (0x0) +#define LCD_C_CHARGEPUMP_VOLTAGE_2_60V_OR_2_17VREF (VLCD0) +#define LCD_C_CHARGEPUMP_VOLTAGE_2_66V_OR_2_22VREF (VLCD1) +#define LCD_C_CHARGEPUMP_VOLTAGE_2_72V_OR_2_27VREF (VLCD1 | VLCD0) +#define LCD_C_CHARGEPUMP_VOLTAGE_2_78V_OR_2_32VREF (VLCD2) +#define LCD_C_CHARGEPUMP_VOLTAGE_2_84V_OR_2_37VREF (VLCD2 | VLCD0) +#define LCD_C_CHARGEPUMP_VOLTAGE_2_90V_OR_2_42VREF (VLCD2 | VLCD1) +#define LCD_C_CHARGEPUMP_VOLTAGE_2_96V_OR_2_47VREF (VLCD2 | VLCD1 | VLCD0) +#define LCD_C_CHARGEPUMP_VOLTAGE_3_02V_OR_2_52VREF (VLCD3) +#define LCD_C_CHARGEPUMP_VOLTAGE_3_08V_OR_2_57VREF (VLCD3 | VLCD0) +#define LCD_C_CHARGEPUMP_VOLTAGE_3_14V_OR_2_62VREF (VLCD3 | VLCD1) +#define LCD_C_CHARGEPUMP_VOLTAGE_3_20V_OR_2_67VREF (VLCD3 | VLCD1 | VLCD0) +#define LCD_C_CHARGEPUMP_VOLTAGE_3_26V_OR_2_72VREF (VLCD3 | VLCD2) +#define LCD_C_CHARGEPUMP_VOLTAGE_3_32V_OR_2_77VREF (VLCD3 | VLCD2 | VLCD0) +#define LCD_C_CHARGEPUMP_VOLTAGE_3_38V_OR_2_82VREF (VLCD3 | VLCD2 | VLCD1) +#define LCD_C_CHARGEPUMP_VOLTAGE_3_44V_OR_2_87VREF \ + (VLCD3 | VLCD2 | VLCD1 | VLCD0) + +//***************************************************************************** +// +// The following are values that can be passed to the startPin parameter for +// functions: LCD_C_setPinAsLCDFunctionEx(); the endPin parameter for +// functions: LCD_C_setPinAsLCDFunctionEx(); the pin parameter for functions: +// LCD_C_setPinAsLCDFunction(), LCD_C_setPinAsPortFunction(), +// LCD_C_setMemory(), and LCD_C_setBlinkingMemory(). +// +//***************************************************************************** +#define LCD_C_SEGMENT_LINE_0 (0) +#define LCD_C_SEGMENT_LINE_1 (1) +#define LCD_C_SEGMENT_LINE_2 (2) +#define LCD_C_SEGMENT_LINE_3 (3) +#define LCD_C_SEGMENT_LINE_4 (4) +#define LCD_C_SEGMENT_LINE_5 (5) +#define LCD_C_SEGMENT_LINE_6 (6) +#define LCD_C_SEGMENT_LINE_7 (7) +#define LCD_C_SEGMENT_LINE_8 (8) +#define LCD_C_SEGMENT_LINE_9 (9) +#define LCD_C_SEGMENT_LINE_10 (10) +#define LCD_C_SEGMENT_LINE_11 (11) +#define LCD_C_SEGMENT_LINE_12 (12) +#define LCD_C_SEGMENT_LINE_13 (13) +#define LCD_C_SEGMENT_LINE_14 (14) +#define LCD_C_SEGMENT_LINE_15 (15) +#define LCD_C_SEGMENT_LINE_16 (16) +#define LCD_C_SEGMENT_LINE_17 (17) +#define LCD_C_SEGMENT_LINE_18 (18) +#define LCD_C_SEGMENT_LINE_19 (19) +#define LCD_C_SEGMENT_LINE_20 (20) +#define LCD_C_SEGMENT_LINE_21 (21) +#define LCD_C_SEGMENT_LINE_22 (22) +#define LCD_C_SEGMENT_LINE_23 (23) +#define LCD_C_SEGMENT_LINE_24 (24) +#define LCD_C_SEGMENT_LINE_25 (25) +#define LCD_C_SEGMENT_LINE_26 (26) +#define LCD_C_SEGMENT_LINE_27 (27) +#define LCD_C_SEGMENT_LINE_28 (28) +#define LCD_C_SEGMENT_LINE_29 (29) +#define LCD_C_SEGMENT_LINE_30 (30) +#define LCD_C_SEGMENT_LINE_31 (31) +#define LCD_C_SEGMENT_LINE_32 (32) +#define LCD_C_SEGMENT_LINE_33 (33) +#define LCD_C_SEGMENT_LINE_34 (34) +#define LCD_C_SEGMENT_LINE_35 (35) +#define LCD_C_SEGMENT_LINE_36 (36) +#define LCD_C_SEGMENT_LINE_37 (37) +#define LCD_C_SEGMENT_LINE_38 (38) +#define LCD_C_SEGMENT_LINE_39 (39) +#define LCD_C_SEGMENT_LINE_40 (40) +#define LCD_C_SEGMENT_LINE_41 (41) +#define LCD_C_SEGMENT_LINE_42 (42) +#define LCD_C_SEGMENT_LINE_43 (43) +#define LCD_C_SEGMENT_LINE_44 (44) +#define LCD_C_SEGMENT_LINE_45 (45) +#define LCD_C_SEGMENT_LINE_46 (46) +#define LCD_C_SEGMENT_LINE_47 (47) +#define LCD_C_SEGMENT_LINE_48 (48) +#define LCD_C_SEGMENT_LINE_49 (49) +#define LCD_C_SEGMENT_LINE_50 (50) +#define LCD_C_SEGMENT_LINE_51 (51) +#define LCD_C_SEGMENT_LINE_52 (52) +#define LCD_C_SEGMENT_LINE_53 (53) +#define LCD_C_SEGMENT_LINE_54 (54) +#define LCD_C_SEGMENT_LINE_55 (55) +#define LCD_C_SEGMENT_LINE_56 (56) +#define LCD_C_SEGMENT_LINE_57 (57) +#define LCD_C_SEGMENT_LINE_58 (58) +#define LCD_C_SEGMENT_LINE_59 (59) +#define LCD_C_SEGMENT_LINE_60 (60) +#define LCD_C_SEGMENT_LINE_61 (61) +#define LCD_C_SEGMENT_LINE_62 (62) +#define LCD_C_SEGMENT_LINE_63 (63) + +//***************************************************************************** +// +// The following are values that can be passed to the syncToClock parameter for +// functions: LCD_C_configChargePump(). +// +//***************************************************************************** +#define LCD_C_SYNCHRONIZATION_DISABLED (0x0) +#define LCD_C_SYNCHRONIZATION_ENABLED (LCDCPCLKSYNC) + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Initializes the LCD Module. +//! +//! his function initializes the LCD but without turning on. It bascially setup +//! the clock source, clock divider, clock prescalar, mux rate, low-power +//! waveform and segments on/off. After calling this function, user can config +//! charge pump, internal reference voltage and voltage sources. +//! +//! \param baseAddress is the base address of the LCD_C module. +//! \param initParams is the pointer to LCD_InitParam structure. See the +//! following parameters for each field. +//! +//! \return None +// +//***************************************************************************** +extern void LCD_C_init(uint16_t baseAddress, + LCD_C_initParam *initParams); + +//***************************************************************************** +// +//! \brief Turns on the LCD module. +//! +//! \param baseAddress is the base address of the LCD_C module. +//! +//! Modified bits are \b LCDON of \b LCDCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void LCD_C_on(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Turns off the LCD module. +//! +//! \param baseAddress is the base address of the LCD_C module. +//! +//! Modified bits are \b LCDON of \b LCDCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void LCD_C_off(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Clears the LCD interrupt flags. +//! +//! \param baseAddress is the base address of the LCD_C module. +//! \param mask is the masked interrupt flag to be cleared. +//! Valid values are: +//! - \b LCD_C_NO_CAPACITANCE_CONNECTED_INTERRUPT +//! - \b LCD_C_BLINKING_SEGMENTS_ON_INTERRUPT +//! - \b LCD_C_BLINKING_SEGMENTS_OFF_INTERRUPT +//! - \b LCD_C_FRAME_INTERRUPT +//! \n Modified bits are \b LCDCAPIFG, \b LCDBLKONIFG, \b LCDBLKOFFIFG +//! and \b LCDFRMIFG of \b LCDCTL1 register. +//! +//! \return None +// +//***************************************************************************** +extern void LCD_C_clearInterrupt(uint16_t baseAddress, + uint16_t mask); + +//***************************************************************************** +// +//! \brief Gets the LCD interrupt status. +//! +//! \param baseAddress is the base address of the LCD_C module. +//! \param mask is the masked interrupt flags. +//! Valid values are: +//! - \b LCD_C_NO_CAPACITANCE_CONNECTED_INTERRUPT +//! - \b LCD_C_BLINKING_SEGMENTS_ON_INTERRUPT +//! - \b LCD_C_BLINKING_SEGMENTS_OFF_INTERRUPT +//! - \b LCD_C_FRAME_INTERRUPT +//! +//! \return None +//! Return Logical OR of any of the following: +//! - \b LCD_C_NO_CAPACITANCE_CONNECTED_INTERRUPT +//! - \b LCD_C_BLINKING_SEGMENTS_ON_INTERRUPT +//! - \b LCD_C_BLINKING_SEGMENTS_OFF_INTERRUPT +//! - \b LCD_C_FRAME_INTERRUPT +//! \n indicating the status of the masked interrupts +// +//***************************************************************************** +extern uint16_t LCD_C_getInterruptStatus(uint16_t baseAddress, + uint16_t mask); + +//***************************************************************************** +// +//! \brief Enables LCD interrupt sources. +//! +//! \param baseAddress is the base address of the LCD_C module. +//! \param mask is the interrupts to be enabled. +//! Valid values are: +//! - \b LCD_C_NO_CAPACITANCE_CONNECTED_INTERRUPT +//! - \b LCD_C_BLINKING_SEGMENTS_ON_INTERRUPT +//! - \b LCD_C_BLINKING_SEGMENTS_OFF_INTERRUPT +//! - \b LCD_C_FRAME_INTERRUPT +//! \n Modified bits are \b LCDCAPIE, \b LCDBLKONIE, \b LCDBLKOFFIE and +//! \b LCDFRMIE of \b LCDCTL1 register. +//! +//! \return None +// +//***************************************************************************** +extern void LCD_C_enableInterrupt(uint16_t baseAddress, + uint16_t mask); + +//***************************************************************************** +// +//! \brief Disables LCD interrupt sources. +//! +//! \param baseAddress is the base address of the LCD_C module. +//! \param mask is the interrupts to be disabled. +//! Valid values are: +//! - \b LCD_C_NO_CAPACITANCE_CONNECTED_INTERRUPT +//! - \b LCD_C_BLINKING_SEGMENTS_ON_INTERRUPT +//! - \b LCD_C_BLINKING_SEGMENTS_OFF_INTERRUPT +//! - \b LCD_C_FRAME_INTERRUPT +//! \n Modified bits are \b LCDCAPIE, \b LCDBLKONIE, \b LCDBLKOFFIE and +//! \b LCDFRMIE of \b LCDCTL1 register. +//! +//! \return None +// +//***************************************************************************** +extern void LCD_C_disableInterrupt(uint16_t baseAddress, + uint16_t mask); + +//***************************************************************************** +// +//! \brief Clears all LCD memory registers. +//! +//! \param baseAddress is the base address of the LCD_C module. +//! +//! Modified bits are \b LCDCLRM of \b LCDMEMCTL register. +//! +//! \return None +// +//***************************************************************************** +extern void LCD_C_clearMemory(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Clears all LCD blinking memory registers. +//! +//! \param baseAddress is the base address of the LCD_C module. +//! +//! Modified bits are \b LCDCLRBM of \b LCDMEMCTL register. +//! +//! \return None +// +//***************************************************************************** +extern void LCD_C_clearBlinkingMemory(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Selects display memory. +//! +//! This function selects display memory either from memory or blinking memory. +//! Please note if the blinking mode is selected as +//! LCD_BLINKMODE_INDIVIDUALSEGMENTS or LCD_BLINKMODE_ALLSEGMENTS or mux rate +//! >=5, display memory can not be changed. If +//! LCD_BLINKMODE_SWITCHDISPLAYCONTENTS is selected, display memory bit +//! reflects current displayed memory. +//! +//! \param baseAddress is the base address of the LCD_C module. +//! \param displayMemory is the desired displayed memory. +//! Valid values are: +//! - \b LCD_C_DISPLAYSOURCE_MEMORY [Default] +//! - \b LCD_C_DISPLAYSOURCE_BLINKINGMEMORY +//! \n Modified bits are \b LCDDISP of \b LCDMEMCTL register. +//! +//! \return None +// +//***************************************************************************** +extern void LCD_C_selectDisplayMemory(uint16_t baseAddress, + uint16_t displayMemory); + +//***************************************************************************** +// +//! \brief Sets the blink settings. +//! +//! \param baseAddress is the base address of the LCD_C module. +//! \param clockDivider is the clock divider for blinking frequency. +//! Valid values are: +//! - \b LCD_C_BLINK_FREQ_CLOCK_DIVIDER_1 [Default] +//! - \b LCD_C_BLINK_FREQ_CLOCK_DIVIDER_2 +//! - \b LCD_C_BLINK_FREQ_CLOCK_DIVIDER_3 +//! - \b LCD_C_BLINK_FREQ_CLOCK_DIVIDER_4 +//! - \b LCD_C_BLINK_FREQ_CLOCK_DIVIDER_5 +//! - \b LCD_C_BLINK_FREQ_CLOCK_DIVIDER_6 +//! - \b LCD_C_BLINK_FREQ_CLOCK_DIVIDER_7 +//! - \b LCD_C_BLINK_FREQ_CLOCK_DIVIDER_8 +//! \n Modified bits are \b LCDBLKDIVx of \b LCDBLKCTL register. +//! \param clockPrescalar is the clock pre-scalar for blinking frequency. +//! Valid values are: +//! - \b LCD_C_BLINK_FREQ_CLOCK_PRESCALAR_512 [Default] +//! - \b LCD_C_BLINK_FREQ_CLOCK_PRESCALAR_1024 +//! - \b LCD_C_BLINK_FREQ_CLOCK_PRESCALAR_2048 +//! - \b LCD_C_BLINK_FREQ_CLOCK_PRESCALAR_4096 +//! - \b LCD_C_BLINK_FREQ_CLOCK_PRESCALAR_8162 +//! - \b LCD_C_BLINK_FREQ_CLOCK_PRESCALAR_16384 +//! - \b LCD_C_BLINK_FREQ_CLOCK_PRESCALAR_32768 +//! - \b LCD_C_BLINK_FREQ_CLOCK_PRESCALAR_65536 +//! \n Modified bits are \b LCDBLKPREx of \b LCDBLKCTL register. +//! +//! \return None +// +//***************************************************************************** +extern void LCD_C_setBlinkingControl(uint16_t baseAddress, + uint8_t clockDivider, + uint8_t clockPrescalar, + uint8_t mode); + +//***************************************************************************** +// +//! \brief Enables the charge pump. +//! +//! \param baseAddress is the base address of the LCD_C module. +//! +//! Modified bits are \b LCDCPEN of \b LCDVCTL register; bits \b LCDON of \b +//! LCDCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void LCD_C_enableChargePump(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Disables the charge pump. +//! +//! \param baseAddress is the base address of the LCD_C module. +//! +//! Modified bits are \b LCDCPEN of \b LCDVCTL register; bits \b LCDON of \b +//! LCDCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void LCD_C_disableChargePump(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Selects the bias level. +//! +//! \param baseAddress is the base address of the LCD_C module. +//! \param bias is the select for bias level. +//! Valid values are: +//! - \b LCD_C_BIAS_1_3 [Default] - 1/3 bias +//! - \b LCD_C_BIAS_1_2 - 1/2 bias +//! +//! Modified bits are \b LCD2B of \b LCDVCTL register; bits \b LCDON of \b +//! LCDCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void LCD_C_selectBias(uint16_t baseAddress, + uint16_t bias); + +//***************************************************************************** +// +//! \brief Selects the charge pump reference. +//! +//! The charge pump reference does not support +//! LCD_C_EXTERNAL_REFERENCE_VOLTAGE, +//! LCD_C_INTERNAL_REFERENCE_VOLTAGE_SWITCHED_TO_EXTERNAL_PIN when +//! LCD_C_V2V3V4_SOURCED_EXTERNALLY or +//! LCD_C_V2V3V4_GENERATED_INTERNALLY_SWITCHED_TO_PINS is selected. +//! +//! \param baseAddress is the base address of the LCD_C module. +//! \param reference is the select for charge pump reference. +//! Valid values are: +//! - \b LCD_C_INTERNAL_REFERENCE_VOLTAGE [Default] +//! - \b LCD_C_EXTERNAL_REFERENCE_VOLTAGE +//! - \b LCD_C_INTERNAL_REFERENCE_VOLTAGE_SWITCHED_TO_EXTERNAL_PIN +//! +//! Modified bits are \b VLCDREFx of \b LCDVCTL register; bits \b LCDON of \b +//! LCDCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void LCD_C_selectChargePumpReference(uint16_t baseAddress, + uint16_t reference); + +//***************************************************************************** +// +//! \brief Sets the voltage source for V2/V3/V4 and V5. +//! +//! The charge pump reference does not support +//! LCD_C_EXTERNAL_REFERENCE_VOLTAGE, +//! LCD_C_INTERNAL_REFERENCE_VOLTAGE_SWITCHED_TO_EXTERNAL_PIN when +//! LCD_C_V2V3V4_SOURCED_EXTERNALLY or +//! LCD_C_V2V3V4_GENERATED_INTERNALLY_SWITCHED_TO_PINS is selected. +//! +//! \param baseAddress is the base address of the LCD_C module. +//! \param vlcdSource is the V(LCD) source select. +//! Valid values are: +//! - \b LCD_C_VLCD_GENERATED_INTERNALLY [Default] +//! - \b LCD_C_VLCD_SOURCED_EXTERNALLY +//! \param v2v3v4Source is the V2/V3/V4 source select. +//! Valid values are: +//! - \b LCD_C_V2V3V4_GENERATED_INTERNALLY_NOT_SWITCHED_TO_PINS +//! [Default] +//! - \b LCD_C_V2V3V4_GENERATED_INTERNALLY_SWITCHED_TO_PINS +//! - \b LCD_C_V2V3V4_SOURCED_EXTERNALLY +//! \param v5Source is the V5 source select. +//! Valid values are: +//! - \b LCD_C_V5_VSS [Default] +//! - \b LCD_C_V5_SOURCED_FROM_R03 +//! +//! Modified bits are \b VLCDEXT, \b LCDREXT, \b LCDEXTBIAS and \b R03EXT of \b +//! LCDVCTL register; bits \b LCDON of \b LCDCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void LCD_C_setVLCDSource(uint16_t baseAddress, + uint16_t vlcdSource, + uint16_t v2v3v4Source, + uint16_t v5Source); + +//***************************************************************************** +// +//! \brief Selects the charge pump reference. +//! +//! Sets LCD charge pump voltage. +//! +//! \param baseAddress is the base address of the LCD_C module. +//! \param voltage is the charge pump select. +//! Valid values are: +//! - \b LCD_C_CHARGEPUMP_DISABLED [Default] +//! - \b LCD_C_CHARGEPUMP_VOLTAGE_2_60V_OR_2_17VREF +//! - \b LCD_C_CHARGEPUMP_VOLTAGE_2_66V_OR_2_22VREF +//! - \b LCD_C_CHARGEPUMP_VOLTAGE_2_72V_OR_2_27VREF +//! - \b LCD_C_CHARGEPUMP_VOLTAGE_2_78V_OR_2_32VREF +//! - \b LCD_C_CHARGEPUMP_VOLTAGE_2_84V_OR_2_37VREF +//! - \b LCD_C_CHARGEPUMP_VOLTAGE_2_90V_OR_2_42VREF +//! - \b LCD_C_CHARGEPUMP_VOLTAGE_2_96V_OR_2_47VREF +//! - \b LCD_C_CHARGEPUMP_VOLTAGE_3_02V_OR_2_52VREF +//! - \b LCD_C_CHARGEPUMP_VOLTAGE_3_08V_OR_2_57VREF +//! - \b LCD_C_CHARGEPUMP_VOLTAGE_3_14V_OR_2_62VREF +//! - \b LCD_C_CHARGEPUMP_VOLTAGE_3_20V_OR_2_67VREF +//! - \b LCD_C_CHARGEPUMP_VOLTAGE_3_26V_OR_2_72VREF +//! - \b LCD_C_CHARGEPUMP_VOLTAGE_3_32V_OR_2_77VREF +//! - \b LCD_C_CHARGEPUMP_VOLTAGE_3_38V_OR_2_82VREF +//! - \b LCD_C_CHARGEPUMP_VOLTAGE_3_44V_OR_2_87VREF +//! +//! Modified bits are \b VLCDx of \b LCDVCTL register; bits \b LCDON of \b +//! LCDCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void LCD_C_setVLCDVoltage(uint16_t baseAddress, + uint16_t voltage); + +//***************************************************************************** +// +//! \brief Sets the LCD Pin as LCD functions. +//! +//! \param baseAddress is the base address of the LCD_C module. +//! \param pin is the select pin set as LCD function. +//! Valid values are: +//! - \b LCD_C_SEGMENT_LINE_0 +//! - \b LCD_C_SEGMENT_LINE_1 +//! - \b LCD_C_SEGMENT_LINE_2 +//! - \b LCD_C_SEGMENT_LINE_3 +//! - \b LCD_C_SEGMENT_LINE_4 +//! - \b LCD_C_SEGMENT_LINE_5 +//! - \b LCD_C_SEGMENT_LINE_6 +//! - \b LCD_C_SEGMENT_LINE_7 +//! - \b LCD_C_SEGMENT_LINE_8 +//! - \b LCD_C_SEGMENT_LINE_9 +//! - \b LCD_C_SEGMENT_LINE_10 +//! - \b LCD_C_SEGMENT_LINE_11 +//! - \b LCD_C_SEGMENT_LINE_12 +//! - \b LCD_C_SEGMENT_LINE_13 +//! - \b LCD_C_SEGMENT_LINE_14 +//! - \b LCD_C_SEGMENT_LINE_15 +//! - \b LCD_C_SEGMENT_LINE_16 +//! - \b LCD_C_SEGMENT_LINE_17 +//! - \b LCD_C_SEGMENT_LINE_18 +//! - \b LCD_C_SEGMENT_LINE_19 +//! - \b LCD_C_SEGMENT_LINE_20 +//! - \b LCD_C_SEGMENT_LINE_21 +//! - \b LCD_C_SEGMENT_LINE_22 +//! - \b LCD_C_SEGMENT_LINE_23 +//! - \b LCD_C_SEGMENT_LINE_24 +//! - \b LCD_C_SEGMENT_LINE_25 +//! - \b LCD_C_SEGMENT_LINE_26 +//! - \b LCD_C_SEGMENT_LINE_27 +//! - \b LCD_C_SEGMENT_LINE_28 +//! - \b LCD_C_SEGMENT_LINE_29 +//! - \b LCD_C_SEGMENT_LINE_30 +//! - \b LCD_C_SEGMENT_LINE_31 +//! - \b LCD_C_SEGMENT_LINE_32 +//! - \b LCD_C_SEGMENT_LINE_33 +//! - \b LCD_C_SEGMENT_LINE_34 +//! - \b LCD_C_SEGMENT_LINE_35 +//! - \b LCD_C_SEGMENT_LINE_36 +//! - \b LCD_C_SEGMENT_LINE_37 +//! - \b LCD_C_SEGMENT_LINE_38 +//! - \b LCD_C_SEGMENT_LINE_39 +//! - \b LCD_C_SEGMENT_LINE_40 +//! - \b LCD_C_SEGMENT_LINE_41 +//! - \b LCD_C_SEGMENT_LINE_42 +//! - \b LCD_C_SEGMENT_LINE_43 +//! - \b LCD_C_SEGMENT_LINE_44 +//! - \b LCD_C_SEGMENT_LINE_45 +//! - \b LCD_C_SEGMENT_LINE_46 +//! - \b LCD_C_SEGMENT_LINE_47 +//! - \b LCD_C_SEGMENT_LINE_48 +//! - \b LCD_C_SEGMENT_LINE_49 +//! - \b LCD_C_SEGMENT_LINE_50 +//! - \b LCD_C_SEGMENT_LINE_51 +//! - \b LCD_C_SEGMENT_LINE_52 +//! - \b LCD_C_SEGMENT_LINE_53 +//! - \b LCD_C_SEGMENT_LINE_54 +//! - \b LCD_C_SEGMENT_LINE_55 +//! - \b LCD_C_SEGMENT_LINE_56 +//! - \b LCD_C_SEGMENT_LINE_57 +//! - \b LCD_C_SEGMENT_LINE_58 +//! - \b LCD_C_SEGMENT_LINE_59 +//! - \b LCD_C_SEGMENT_LINE_60 +//! - \b LCD_C_SEGMENT_LINE_61 +//! - \b LCD_C_SEGMENT_LINE_62 +//! - \b LCD_C_SEGMENT_LINE_63 +//! +//! Modified bits are \b LCDSx of \b LCDPCTLx register; bits \b LCDON of \b +//! LCDCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void LCD_C_setPinAsLCDFunction(uint16_t baseAddress, + uint8_t pin); + +//***************************************************************************** +// +//! \brief Sets the LCD Pin as Port functions. +//! +//! \param baseAddress is the base address of the LCD_C module. +//! \param pin is the select pin set as Port function. +//! Valid values are: +//! - \b LCD_C_SEGMENT_LINE_0 +//! - \b LCD_C_SEGMENT_LINE_1 +//! - \b LCD_C_SEGMENT_LINE_2 +//! - \b LCD_C_SEGMENT_LINE_3 +//! - \b LCD_C_SEGMENT_LINE_4 +//! - \b LCD_C_SEGMENT_LINE_5 +//! - \b LCD_C_SEGMENT_LINE_6 +//! - \b LCD_C_SEGMENT_LINE_7 +//! - \b LCD_C_SEGMENT_LINE_8 +//! - \b LCD_C_SEGMENT_LINE_9 +//! - \b LCD_C_SEGMENT_LINE_10 +//! - \b LCD_C_SEGMENT_LINE_11 +//! - \b LCD_C_SEGMENT_LINE_12 +//! - \b LCD_C_SEGMENT_LINE_13 +//! - \b LCD_C_SEGMENT_LINE_14 +//! - \b LCD_C_SEGMENT_LINE_15 +//! - \b LCD_C_SEGMENT_LINE_16 +//! - \b LCD_C_SEGMENT_LINE_17 +//! - \b LCD_C_SEGMENT_LINE_18 +//! - \b LCD_C_SEGMENT_LINE_19 +//! - \b LCD_C_SEGMENT_LINE_20 +//! - \b LCD_C_SEGMENT_LINE_21 +//! - \b LCD_C_SEGMENT_LINE_22 +//! - \b LCD_C_SEGMENT_LINE_23 +//! - \b LCD_C_SEGMENT_LINE_24 +//! - \b LCD_C_SEGMENT_LINE_25 +//! - \b LCD_C_SEGMENT_LINE_26 +//! - \b LCD_C_SEGMENT_LINE_27 +//! - \b LCD_C_SEGMENT_LINE_28 +//! - \b LCD_C_SEGMENT_LINE_29 +//! - \b LCD_C_SEGMENT_LINE_30 +//! - \b LCD_C_SEGMENT_LINE_31 +//! - \b LCD_C_SEGMENT_LINE_32 +//! - \b LCD_C_SEGMENT_LINE_33 +//! - \b LCD_C_SEGMENT_LINE_34 +//! - \b LCD_C_SEGMENT_LINE_35 +//! - \b LCD_C_SEGMENT_LINE_36 +//! - \b LCD_C_SEGMENT_LINE_37 +//! - \b LCD_C_SEGMENT_LINE_38 +//! - \b LCD_C_SEGMENT_LINE_39 +//! - \b LCD_C_SEGMENT_LINE_40 +//! - \b LCD_C_SEGMENT_LINE_41 +//! - \b LCD_C_SEGMENT_LINE_42 +//! - \b LCD_C_SEGMENT_LINE_43 +//! - \b LCD_C_SEGMENT_LINE_44 +//! - \b LCD_C_SEGMENT_LINE_45 +//! - \b LCD_C_SEGMENT_LINE_46 +//! - \b LCD_C_SEGMENT_LINE_47 +//! - \b LCD_C_SEGMENT_LINE_48 +//! - \b LCD_C_SEGMENT_LINE_49 +//! - \b LCD_C_SEGMENT_LINE_50 +//! - \b LCD_C_SEGMENT_LINE_51 +//! - \b LCD_C_SEGMENT_LINE_52 +//! - \b LCD_C_SEGMENT_LINE_53 +//! - \b LCD_C_SEGMENT_LINE_54 +//! - \b LCD_C_SEGMENT_LINE_55 +//! - \b LCD_C_SEGMENT_LINE_56 +//! - \b LCD_C_SEGMENT_LINE_57 +//! - \b LCD_C_SEGMENT_LINE_58 +//! - \b LCD_C_SEGMENT_LINE_59 +//! - \b LCD_C_SEGMENT_LINE_60 +//! - \b LCD_C_SEGMENT_LINE_61 +//! - \b LCD_C_SEGMENT_LINE_62 +//! - \b LCD_C_SEGMENT_LINE_63 +//! +//! Modified bits are \b LCDSx of \b LCDPCTLx register; bits \b LCDON of \b +//! LCDCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void LCD_C_setPinAsPortFunction(uint16_t baseAddress, + uint8_t pin); + +//***************************************************************************** +// +//! \brief Sets the LCD pins as LCD function pin. +//! +//! This function sets the LCD pins as LCD function pin. Instead of passing the +//! all the possible pins, it just requires the start pin and the end pin. +//! +//! \param baseAddress is the base address of the LCD_C module. +//! \param startPin is the starting pin to be configed as LCD function pin. +//! Valid values are: +//! - \b LCD_C_SEGMENT_LINE_0 +//! - \b LCD_C_SEGMENT_LINE_1 +//! - \b LCD_C_SEGMENT_LINE_2 +//! - \b LCD_C_SEGMENT_LINE_3 +//! - \b LCD_C_SEGMENT_LINE_4 +//! - \b LCD_C_SEGMENT_LINE_5 +//! - \b LCD_C_SEGMENT_LINE_6 +//! - \b LCD_C_SEGMENT_LINE_7 +//! - \b LCD_C_SEGMENT_LINE_8 +//! - \b LCD_C_SEGMENT_LINE_9 +//! - \b LCD_C_SEGMENT_LINE_10 +//! - \b LCD_C_SEGMENT_LINE_11 +//! - \b LCD_C_SEGMENT_LINE_12 +//! - \b LCD_C_SEGMENT_LINE_13 +//! - \b LCD_C_SEGMENT_LINE_14 +//! - \b LCD_C_SEGMENT_LINE_15 +//! - \b LCD_C_SEGMENT_LINE_16 +//! - \b LCD_C_SEGMENT_LINE_17 +//! - \b LCD_C_SEGMENT_LINE_18 +//! - \b LCD_C_SEGMENT_LINE_19 +//! - \b LCD_C_SEGMENT_LINE_20 +//! - \b LCD_C_SEGMENT_LINE_21 +//! - \b LCD_C_SEGMENT_LINE_22 +//! - \b LCD_C_SEGMENT_LINE_23 +//! - \b LCD_C_SEGMENT_LINE_24 +//! - \b LCD_C_SEGMENT_LINE_25 +//! - \b LCD_C_SEGMENT_LINE_26 +//! - \b LCD_C_SEGMENT_LINE_27 +//! - \b LCD_C_SEGMENT_LINE_28 +//! - \b LCD_C_SEGMENT_LINE_29 +//! - \b LCD_C_SEGMENT_LINE_30 +//! - \b LCD_C_SEGMENT_LINE_31 +//! - \b LCD_C_SEGMENT_LINE_32 +//! - \b LCD_C_SEGMENT_LINE_33 +//! - \b LCD_C_SEGMENT_LINE_34 +//! - \b LCD_C_SEGMENT_LINE_35 +//! - \b LCD_C_SEGMENT_LINE_36 +//! - \b LCD_C_SEGMENT_LINE_37 +//! - \b LCD_C_SEGMENT_LINE_38 +//! - \b LCD_C_SEGMENT_LINE_39 +//! - \b LCD_C_SEGMENT_LINE_40 +//! - \b LCD_C_SEGMENT_LINE_41 +//! - \b LCD_C_SEGMENT_LINE_42 +//! - \b LCD_C_SEGMENT_LINE_43 +//! - \b LCD_C_SEGMENT_LINE_44 +//! - \b LCD_C_SEGMENT_LINE_45 +//! - \b LCD_C_SEGMENT_LINE_46 +//! - \b LCD_C_SEGMENT_LINE_47 +//! - \b LCD_C_SEGMENT_LINE_48 +//! - \b LCD_C_SEGMENT_LINE_49 +//! - \b LCD_C_SEGMENT_LINE_50 +//! - \b LCD_C_SEGMENT_LINE_51 +//! - \b LCD_C_SEGMENT_LINE_52 +//! - \b LCD_C_SEGMENT_LINE_53 +//! - \b LCD_C_SEGMENT_LINE_54 +//! - \b LCD_C_SEGMENT_LINE_55 +//! - \b LCD_C_SEGMENT_LINE_56 +//! - \b LCD_C_SEGMENT_LINE_57 +//! - \b LCD_C_SEGMENT_LINE_58 +//! - \b LCD_C_SEGMENT_LINE_59 +//! - \b LCD_C_SEGMENT_LINE_60 +//! - \b LCD_C_SEGMENT_LINE_61 +//! - \b LCD_C_SEGMENT_LINE_62 +//! - \b LCD_C_SEGMENT_LINE_63 +//! \param endPin is the ending pin to be configed as LCD function pin. +//! Valid values are: +//! - \b LCD_C_SEGMENT_LINE_0 +//! - \b LCD_C_SEGMENT_LINE_1 +//! - \b LCD_C_SEGMENT_LINE_2 +//! - \b LCD_C_SEGMENT_LINE_3 +//! - \b LCD_C_SEGMENT_LINE_4 +//! - \b LCD_C_SEGMENT_LINE_5 +//! - \b LCD_C_SEGMENT_LINE_6 +//! - \b LCD_C_SEGMENT_LINE_7 +//! - \b LCD_C_SEGMENT_LINE_8 +//! - \b LCD_C_SEGMENT_LINE_9 +//! - \b LCD_C_SEGMENT_LINE_10 +//! - \b LCD_C_SEGMENT_LINE_11 +//! - \b LCD_C_SEGMENT_LINE_12 +//! - \b LCD_C_SEGMENT_LINE_13 +//! - \b LCD_C_SEGMENT_LINE_14 +//! - \b LCD_C_SEGMENT_LINE_15 +//! - \b LCD_C_SEGMENT_LINE_16 +//! - \b LCD_C_SEGMENT_LINE_17 +//! - \b LCD_C_SEGMENT_LINE_18 +//! - \b LCD_C_SEGMENT_LINE_19 +//! - \b LCD_C_SEGMENT_LINE_20 +//! - \b LCD_C_SEGMENT_LINE_21 +//! - \b LCD_C_SEGMENT_LINE_22 +//! - \b LCD_C_SEGMENT_LINE_23 +//! - \b LCD_C_SEGMENT_LINE_24 +//! - \b LCD_C_SEGMENT_LINE_25 +//! - \b LCD_C_SEGMENT_LINE_26 +//! - \b LCD_C_SEGMENT_LINE_27 +//! - \b LCD_C_SEGMENT_LINE_28 +//! - \b LCD_C_SEGMENT_LINE_29 +//! - \b LCD_C_SEGMENT_LINE_30 +//! - \b LCD_C_SEGMENT_LINE_31 +//! - \b LCD_C_SEGMENT_LINE_32 +//! - \b LCD_C_SEGMENT_LINE_33 +//! - \b LCD_C_SEGMENT_LINE_34 +//! - \b LCD_C_SEGMENT_LINE_35 +//! - \b LCD_C_SEGMENT_LINE_36 +//! - \b LCD_C_SEGMENT_LINE_37 +//! - \b LCD_C_SEGMENT_LINE_38 +//! - \b LCD_C_SEGMENT_LINE_39 +//! - \b LCD_C_SEGMENT_LINE_40 +//! - \b LCD_C_SEGMENT_LINE_41 +//! - \b LCD_C_SEGMENT_LINE_42 +//! - \b LCD_C_SEGMENT_LINE_43 +//! - \b LCD_C_SEGMENT_LINE_44 +//! - \b LCD_C_SEGMENT_LINE_45 +//! - \b LCD_C_SEGMENT_LINE_46 +//! - \b LCD_C_SEGMENT_LINE_47 +//! - \b LCD_C_SEGMENT_LINE_48 +//! - \b LCD_C_SEGMENT_LINE_49 +//! - \b LCD_C_SEGMENT_LINE_50 +//! - \b LCD_C_SEGMENT_LINE_51 +//! - \b LCD_C_SEGMENT_LINE_52 +//! - \b LCD_C_SEGMENT_LINE_53 +//! - \b LCD_C_SEGMENT_LINE_54 +//! - \b LCD_C_SEGMENT_LINE_55 +//! - \b LCD_C_SEGMENT_LINE_56 +//! - \b LCD_C_SEGMENT_LINE_57 +//! - \b LCD_C_SEGMENT_LINE_58 +//! - \b LCD_C_SEGMENT_LINE_59 +//! - \b LCD_C_SEGMENT_LINE_60 +//! - \b LCD_C_SEGMENT_LINE_61 +//! - \b LCD_C_SEGMENT_LINE_62 +//! - \b LCD_C_SEGMENT_LINE_63 +//! +//! Modified bits are \b LCDSx of \b LCDPCTLx register; bits \b LCDON of \b +//! LCDCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void LCD_C_setPinAsLCDFunctionEx(uint16_t baseAddress, + uint8_t startPin, + uint8_t endPin); + +//***************************************************************************** +// +//! \brief Sets the LCD memory register. +//! +//! \param baseAddress is the base address of the LCD_C module. +//! \param pin is the select pin for setting value. +//! Valid values are: +//! - \b LCD_C_SEGMENT_LINE_0 +//! - \b LCD_C_SEGMENT_LINE_1 +//! - \b LCD_C_SEGMENT_LINE_2 +//! - \b LCD_C_SEGMENT_LINE_3 +//! - \b LCD_C_SEGMENT_LINE_4 +//! - \b LCD_C_SEGMENT_LINE_5 +//! - \b LCD_C_SEGMENT_LINE_6 +//! - \b LCD_C_SEGMENT_LINE_7 +//! - \b LCD_C_SEGMENT_LINE_8 +//! - \b LCD_C_SEGMENT_LINE_9 +//! - \b LCD_C_SEGMENT_LINE_10 +//! - \b LCD_C_SEGMENT_LINE_11 +//! - \b LCD_C_SEGMENT_LINE_12 +//! - \b LCD_C_SEGMENT_LINE_13 +//! - \b LCD_C_SEGMENT_LINE_14 +//! - \b LCD_C_SEGMENT_LINE_15 +//! - \b LCD_C_SEGMENT_LINE_16 +//! - \b LCD_C_SEGMENT_LINE_17 +//! - \b LCD_C_SEGMENT_LINE_18 +//! - \b LCD_C_SEGMENT_LINE_19 +//! - \b LCD_C_SEGMENT_LINE_20 +//! - \b LCD_C_SEGMENT_LINE_21 +//! - \b LCD_C_SEGMENT_LINE_22 +//! - \b LCD_C_SEGMENT_LINE_23 +//! - \b LCD_C_SEGMENT_LINE_24 +//! - \b LCD_C_SEGMENT_LINE_25 +//! - \b LCD_C_SEGMENT_LINE_26 +//! - \b LCD_C_SEGMENT_LINE_27 +//! - \b LCD_C_SEGMENT_LINE_28 +//! - \b LCD_C_SEGMENT_LINE_29 +//! - \b LCD_C_SEGMENT_LINE_30 +//! - \b LCD_C_SEGMENT_LINE_31 +//! - \b LCD_C_SEGMENT_LINE_32 +//! - \b LCD_C_SEGMENT_LINE_33 +//! - \b LCD_C_SEGMENT_LINE_34 +//! - \b LCD_C_SEGMENT_LINE_35 +//! - \b LCD_C_SEGMENT_LINE_36 +//! - \b LCD_C_SEGMENT_LINE_37 +//! - \b LCD_C_SEGMENT_LINE_38 +//! - \b LCD_C_SEGMENT_LINE_39 +//! - \b LCD_C_SEGMENT_LINE_40 +//! - \b LCD_C_SEGMENT_LINE_41 +//! - \b LCD_C_SEGMENT_LINE_42 +//! - \b LCD_C_SEGMENT_LINE_43 +//! - \b LCD_C_SEGMENT_LINE_44 +//! - \b LCD_C_SEGMENT_LINE_45 +//! - \b LCD_C_SEGMENT_LINE_46 +//! - \b LCD_C_SEGMENT_LINE_47 +//! - \b LCD_C_SEGMENT_LINE_48 +//! - \b LCD_C_SEGMENT_LINE_49 +//! - \b LCD_C_SEGMENT_LINE_50 +//! - \b LCD_C_SEGMENT_LINE_51 +//! - \b LCD_C_SEGMENT_LINE_52 +//! - \b LCD_C_SEGMENT_LINE_53 +//! - \b LCD_C_SEGMENT_LINE_54 +//! - \b LCD_C_SEGMENT_LINE_55 +//! - \b LCD_C_SEGMENT_LINE_56 +//! - \b LCD_C_SEGMENT_LINE_57 +//! - \b LCD_C_SEGMENT_LINE_58 +//! - \b LCD_C_SEGMENT_LINE_59 +//! - \b LCD_C_SEGMENT_LINE_60 +//! - \b LCD_C_SEGMENT_LINE_61 +//! - \b LCD_C_SEGMENT_LINE_62 +//! - \b LCD_C_SEGMENT_LINE_63 +//! \param value is the designated value for corresponding pin. +//! +//! Modified bits are \b MBITx of \b LCDMx register. +//! +//! \return None +// +//***************************************************************************** +extern void LCD_C_setMemory(uint16_t baseAddress, + uint8_t pin, + uint8_t value); + +//***************************************************************************** +// +//! \brief Sets the LCD blink memory register. +//! +//! \param baseAddress is the base address of the LCD_C module. +//! \param pin is the select pin for setting value. +//! Valid values are: +//! - \b LCD_C_SEGMENT_LINE_0 +//! - \b LCD_C_SEGMENT_LINE_1 +//! - \b LCD_C_SEGMENT_LINE_2 +//! - \b LCD_C_SEGMENT_LINE_3 +//! - \b LCD_C_SEGMENT_LINE_4 +//! - \b LCD_C_SEGMENT_LINE_5 +//! - \b LCD_C_SEGMENT_LINE_6 +//! - \b LCD_C_SEGMENT_LINE_7 +//! - \b LCD_C_SEGMENT_LINE_8 +//! - \b LCD_C_SEGMENT_LINE_9 +//! - \b LCD_C_SEGMENT_LINE_10 +//! - \b LCD_C_SEGMENT_LINE_11 +//! - \b LCD_C_SEGMENT_LINE_12 +//! - \b LCD_C_SEGMENT_LINE_13 +//! - \b LCD_C_SEGMENT_LINE_14 +//! - \b LCD_C_SEGMENT_LINE_15 +//! - \b LCD_C_SEGMENT_LINE_16 +//! - \b LCD_C_SEGMENT_LINE_17 +//! - \b LCD_C_SEGMENT_LINE_18 +//! - \b LCD_C_SEGMENT_LINE_19 +//! - \b LCD_C_SEGMENT_LINE_20 +//! - \b LCD_C_SEGMENT_LINE_21 +//! - \b LCD_C_SEGMENT_LINE_22 +//! - \b LCD_C_SEGMENT_LINE_23 +//! - \b LCD_C_SEGMENT_LINE_24 +//! - \b LCD_C_SEGMENT_LINE_25 +//! - \b LCD_C_SEGMENT_LINE_26 +//! - \b LCD_C_SEGMENT_LINE_27 +//! - \b LCD_C_SEGMENT_LINE_28 +//! - \b LCD_C_SEGMENT_LINE_29 +//! - \b LCD_C_SEGMENT_LINE_30 +//! - \b LCD_C_SEGMENT_LINE_31 +//! - \b LCD_C_SEGMENT_LINE_32 +//! - \b LCD_C_SEGMENT_LINE_33 +//! - \b LCD_C_SEGMENT_LINE_34 +//! - \b LCD_C_SEGMENT_LINE_35 +//! - \b LCD_C_SEGMENT_LINE_36 +//! - \b LCD_C_SEGMENT_LINE_37 +//! - \b LCD_C_SEGMENT_LINE_38 +//! - \b LCD_C_SEGMENT_LINE_39 +//! - \b LCD_C_SEGMENT_LINE_40 +//! - \b LCD_C_SEGMENT_LINE_41 +//! - \b LCD_C_SEGMENT_LINE_42 +//! - \b LCD_C_SEGMENT_LINE_43 +//! - \b LCD_C_SEGMENT_LINE_44 +//! - \b LCD_C_SEGMENT_LINE_45 +//! - \b LCD_C_SEGMENT_LINE_46 +//! - \b LCD_C_SEGMENT_LINE_47 +//! - \b LCD_C_SEGMENT_LINE_48 +//! - \b LCD_C_SEGMENT_LINE_49 +//! - \b LCD_C_SEGMENT_LINE_50 +//! - \b LCD_C_SEGMENT_LINE_51 +//! - \b LCD_C_SEGMENT_LINE_52 +//! - \b LCD_C_SEGMENT_LINE_53 +//! - \b LCD_C_SEGMENT_LINE_54 +//! - \b LCD_C_SEGMENT_LINE_55 +//! - \b LCD_C_SEGMENT_LINE_56 +//! - \b LCD_C_SEGMENT_LINE_57 +//! - \b LCD_C_SEGMENT_LINE_58 +//! - \b LCD_C_SEGMENT_LINE_59 +//! - \b LCD_C_SEGMENT_LINE_60 +//! - \b LCD_C_SEGMENT_LINE_61 +//! - \b LCD_C_SEGMENT_LINE_62 +//! - \b LCD_C_SEGMENT_LINE_63 +//! \param value is the designated value for corresponding blink pin. +//! +//! Modified bits are \b MBITx of \b LCDBMx register. +//! +//! \return None +// +//***************************************************************************** +extern void LCD_C_setBlinkingMemory(uint16_t baseAddress, + uint8_t pin, + uint8_t value); + +//***************************************************************************** +// +//! \brief Configs the charge pump for synchronization and disabled capability. +//! +//! This function is device-specific. The charge pump clock can be synchronized +//! to a device-specific clock, and also can be disabled by connected function. +//! +//! \param baseAddress is the base address of the LCD_C module. +//! \param syncToClock is the synchronization select. +//! Valid values are: +//! - \b LCD_C_SYNCHRONIZATION_DISABLED [Default] +//! - \b LCD_C_SYNCHRONIZATION_ENABLED +//! \param functionControl is the connected function control select. Setting 0 +//! to make connected function not disable charge pump. +//! +//! Modified bits are \b MBITx of \b LCDBMx register. +//! +//! \return None +// +//***************************************************************************** +extern void LCD_C_configChargePump(uint16_t baseAddress, + uint16_t syncToClock, + uint16_t functionControl); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_LCD_C_H__ diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/mpu.c b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/mpu.c new file mode 100644 index 000000000..98e55e2d7 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/mpu.c @@ -0,0 +1,360 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// mpu.c - Driver for the mpu Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup mpu_api mpu +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_MPU__ +#include "mpu.h" + +#include + +//***************************************************************************** +// +// The following value is used by createTwoSegments, createThreeSegments to +// check the user has passed a valid segmentation value. This value was +// obtained from the User's Guide. +// +//***************************************************************************** +#define MPU_MAX_SEG_VALUE 0x13C1 + +void MPU_initTwoSegments(uint16_t baseAddress, + uint16_t seg1boundary, + uint8_t seg1accmask, + uint8_t seg2accmask) +{ + // Write MPU password to allow MPU register configuration + HWREG16(baseAddress + OFS_MPUCTL0) = MPUPW | HWREG8( + baseAddress + OFS_MPUCTL0); + + // Create two memory segmentations + HWREG16(baseAddress + OFS_MPUSEGB1) = seg1boundary; + HWREG16(baseAddress + OFS_MPUSEGB2) = seg1boundary; + + // Set access rights based on user's selection for segment1 + switch(seg1accmask) + { + case MPU_EXEC | MPU_READ: + HWREG16(baseAddress + OFS_MPUSAM) &= ~MPUSEG1WE; + HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG1XE + MPUSEG1RE; + break; + case MPU_READ | MPU_WRITE: + HWREG16(baseAddress + OFS_MPUSAM) &= ~MPUSEG1XE; + HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG1RE + MPUSEG1WE; + break; + case MPU_READ: + HWREG16(baseAddress + OFS_MPUSAM) &= ~(MPUSEG1XE + MPUSEG1WE); + HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG1RE; + break; + case MPU_EXEC | MPU_READ | MPU_WRITE: + HWREG16(baseAddress + + OFS_MPUSAM) |= (MPUSEG1XE + MPUSEG1WE + MPUSEG1RE); + break; + case MPU_NO_READ_WRITE_EXEC: + HWREG16(baseAddress + + OFS_MPUSAM) &= ~(MPUSEG1XE + MPUSEG1WE + MPUSEG1RE); + break; + default: + break; + } + + // Set access rights based on user's selection for segment2 + switch(seg2accmask) + { + case MPU_EXEC | MPU_READ: + HWREG16(baseAddress + OFS_MPUSAM) &= ~(MPUSEG3WE + MPUSEG2WE); + HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG3XE + MPUSEG3RE + + MPUSEG2XE + MPUSEG2RE; + break; + case MPU_READ | MPU_WRITE: + HWREG16(baseAddress + OFS_MPUSAM) &= ~(MPUSEG3XE + MPUSEG2XE); + HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG3RE + MPUSEG3WE + + MPUSEG2RE + MPUSEG2WE; + break; + case MPU_READ: + HWREG16(baseAddress + OFS_MPUSAM) &= ~(MPUSEG3XE + MPUSEG3WE + + MPUSEG2XE + MPUSEG2WE); + HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG3RE + MPUSEG2RE; + break; + case MPU_EXEC | MPU_READ | MPU_WRITE: + HWREG16(baseAddress + OFS_MPUSAM) |= (MPUSEG3XE + MPUSEG3WE + + MPUSEG3RE + MPUSEG2XE + + MPUSEG2WE + MPUSEG2RE); + break; + case MPU_NO_READ_WRITE_EXEC: + HWREG16(baseAddress + OFS_MPUSAM) &= ~(MPUSEG3XE + MPUSEG3WE + + MPUSEG3RE + MPUSEG2XE + + MPUSEG2WE + MPUSEG2RE); + break; + default: + break; + } + + //Lock MPU to disable writing to all registers + HWREG8(baseAddress + OFS_MPUCTL0_H) = 0x00; +} + +void MPU_initThreeSegments(uint16_t baseAddress, + MPU_initThreeSegmentsParam *param) +{ + // Write MPU password to allow MPU register configuration + HWREG16(baseAddress + OFS_MPUCTL0) = MPUPW | HWREG8( + baseAddress + OFS_MPUCTL0); + + // Create two memory segmentations + HWREG16(baseAddress + OFS_MPUSEGB1) = param->seg1boundary; + HWREG16(baseAddress + OFS_MPUSEGB2) = param->seg2boundary; + + // Set access rights based on user's selection for segment1 + switch(param->seg1accmask) + { + case MPU_EXEC | MPU_READ: + HWREG16(baseAddress + OFS_MPUSAM) &= ~MPUSEG1WE; + HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG1XE + MPUSEG1RE; + break; + case MPU_READ | MPU_WRITE: + HWREG16(baseAddress + OFS_MPUSAM) &= ~MPUSEG1XE; + HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG1RE + MPUSEG1WE; + break; + case MPU_READ: + HWREG16(baseAddress + OFS_MPUSAM) &= ~(MPUSEG1XE + MPUSEG1WE); + HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG1RE; + break; + case MPU_EXEC | MPU_READ | MPU_WRITE: + HWREG16(baseAddress + + OFS_MPUSAM) |= (MPUSEG1XE + MPUSEG1WE + MPUSEG1RE); + break; + case MPU_NO_READ_WRITE_EXEC: + HWREG16(baseAddress + + OFS_MPUSAM) &= ~(MPUSEG1XE + MPUSEG1WE + MPUSEG1RE); + break; + default: + break; + } + + // Set access rights based on user's selection for segment2 + switch(param->seg2accmask) + { + case MPU_EXEC | MPU_READ: + HWREG16(baseAddress + OFS_MPUSAM) &= ~MPUSEG2WE; + HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG2XE + MPUSEG2RE; + break; + case MPU_READ | MPU_WRITE: + HWREG16(baseAddress + OFS_MPUSAM) &= ~MPUSEG2XE; + HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG2RE + MPUSEG2WE; + break; + case MPU_READ: + HWREG16(baseAddress + OFS_MPUSAM) &= ~(MPUSEG2XE + MPUSEG2WE); + HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG2RE; + break; + case MPU_EXEC | MPU_READ | MPU_WRITE: + HWREG16(baseAddress + + OFS_MPUSAM) |= (MPUSEG2XE + MPUSEG2WE + MPUSEG2RE); + break; + case MPU_NO_READ_WRITE_EXEC: + HWREG16(baseAddress + + OFS_MPUSAM) &= ~(MPUSEG2XE + MPUSEG2WE + MPUSEG2RE); + break; + default: + break; + } + + // Set access rights based on user's selection for segment3 + switch(param->seg3accmask) + { + case MPU_EXEC | MPU_READ: + HWREG16(baseAddress + OFS_MPUSAM) &= ~MPUSEG3WE; + HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG3XE + MPUSEG3RE; + break; + case MPU_READ | MPU_WRITE: + HWREG16(baseAddress + OFS_MPUSAM) &= ~MPUSEG3XE; + HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG3RE + MPUSEG3WE; + break; + case MPU_READ: + HWREG16(baseAddress + OFS_MPUSAM) &= ~(MPUSEG3XE + MPUSEG3WE); + HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG3RE; + break; + case MPU_EXEC | MPU_READ | MPU_WRITE: + HWREG16(baseAddress + + OFS_MPUSAM) |= (MPUSEG3XE + MPUSEG3WE + MPUSEG3WE); + break; + case MPU_NO_READ_WRITE_EXEC: + HWREG16(baseAddress + + OFS_MPUSAM) &= ~(MPUSEG3XE + MPUSEG3WE + MPUSEG3WE); + break; + default: + break; + } + + //Lock MPU to disable writing to all registers + HWREG8(baseAddress + OFS_MPUCTL0_H) = 0x00; +} + +void MPU_initInfoSegment(uint16_t baseAddress, + uint8_t accmask) +{ + // Write MPU password to allow MPU register configuration + HWREG16(baseAddress + OFS_MPUCTL0) = MPUPW | HWREG8( + baseAddress + OFS_MPUCTL0); + + // Set access rights based on user's selection for segment1 + switch(accmask) + { + case MPU_EXEC | MPU_READ: + HWREG16(baseAddress + OFS_MPUSAM) &= ~MPUSEGIWE; + HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEGIXE + MPUSEGIRE; + break; + case MPU_READ | MPU_WRITE: + HWREG16(baseAddress + OFS_MPUSAM) &= ~MPUSEGIXE; + HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEGIRE + MPUSEGIWE; + break; + case MPU_READ: + HWREG16(baseAddress + OFS_MPUSAM) &= ~(MPUSEGIXE + MPUSEGIWE); + HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEGIRE; + break; + case MPU_EXEC | MPU_READ | MPU_WRITE: + HWREG16(baseAddress + + OFS_MPUSAM) |= (MPUSEGIXE + MPUSEGIWE + MPUSEGIRE); + break; + case MPU_NO_READ_WRITE_EXEC: + HWREG16(baseAddress + + OFS_MPUSAM) &= ~(MPUSEGIXE + MPUSEGIWE + MPUSEGIRE); + break; + default: + break; + } + + //Lock MPU to disable writing to all registers + HWREG8(baseAddress + OFS_MPUCTL0_H) = 0x00; +} + +void MPU_enableNMIevent(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_MPUCTL0) = MPUPW | MPUSEGIE | + HWREG8(baseAddress + OFS_MPUCTL0); + + //Lock MPU to disable writing to all registers + HWREG8(baseAddress + OFS_MPUCTL0_H) = 0x00; +} + +void MPU_start(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_MPUCTL0) = MPUPW | MPUENA | HWREG8( + baseAddress + OFS_MPUCTL0); + + //Lock MPU to disable writing to all registers + HWREG8(baseAddress + OFS_MPUCTL0_H) = 0x00; +} + +void MPU_enablePUCOnViolation(uint16_t baseAddress, + uint16_t segment) +{ + HWREG16(baseAddress + OFS_MPUCTL0) = MPUPW | HWREG8( + baseAddress + OFS_MPUCTL0); + HWREG16(baseAddress + OFS_MPUSAM) |= segment; + + //Lock MPU to disable writing to all registers + HWREG8(baseAddress + OFS_MPUCTL0_H) = 0x00; +} + +void MPU_disablePUCOnViolation(uint16_t baseAddress, + uint16_t segment) +{ + HWREG16(baseAddress + OFS_MPUCTL0) = MPUPW | HWREG8( + baseAddress + OFS_MPUCTL0); + HWREG16(baseAddress + OFS_MPUSAM) &= ~segment; + + //Lock MPU to disable writing to all registers + HWREG8(baseAddress + OFS_MPUCTL0_H) = 0x00; +} + +uint16_t MPU_getInterruptStatus(uint16_t baseAddress, + uint16_t memAccFlag) +{ + return (HWREG16(baseAddress + OFS_MPUCTL1) & memAccFlag); +} + +uint16_t MPU_clearInterrupt(uint16_t baseAddress, + uint16_t memAccFlag) +{ + HWREG16(baseAddress + OFS_MPUCTL0) = MPUPW | HWREG8( + baseAddress + OFS_MPUCTL0); + HWREG16(baseAddress + OFS_MPUCTL1) &= ~memAccFlag; + + //Lock MPU to disable writing to all registers + HWREG8(baseAddress + OFS_MPUCTL0_H) = 0x00; + + return (HWREG16(baseAddress + OFS_MPUCTL1) & memAccFlag); +} + +uint16_t MPU_clearAllInterrupts(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_MPUCTL0) = MPUPW | HWREG8( + baseAddress + OFS_MPUCTL0); + HWREG16(baseAddress + + OFS_MPUCTL1) &= ~(MPUSEG1IFG + MPUSEG2IFG + MPUSEG3IFG); + + //Lock MPU to disable writing to all registers + HWREG8(baseAddress + OFS_MPUCTL0_H) = 0x00; + + return (HWREG16(baseAddress + + OFS_MPUCTL1) & (MPUSEG1IFG + MPUSEG2IFG + MPUSEG3IFG)); +} + +void MPU_lockMPU(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_MPUCTL0) = MPUPW | MPULOCK | + HWREG8(baseAddress + OFS_MPUCTL0); + + //Lock MPU to disable writing to all registers + HWREG8(baseAddress + OFS_MPUCTL0_H) = 0x00; +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for mpu_api +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/mpu.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/mpu.h new file mode 100644 index 000000000..440a2de99 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/mpu.h @@ -0,0 +1,423 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// mpu.h - Driver for the MPU Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_MPU_H__ +#define __MSP430WARE_MPU_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_MPU__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "inc/hw_regaccess.h" +//***************************************************************************** +// +//! \brief Used in the MPU_initThreeSegments() function as the param parameter. +// +//***************************************************************************** +typedef struct MPU_initThreeSegmentsParam +{ + //! Valid values can be found in the Family User's Guide + uint16_t seg1boundary; + //! Valid values can be found in the Family User's Guide + uint16_t seg2boundary; + //! Is the bit mask of access right for memory segment 1. + //! \n Logical OR of any of the following: + //! - \b MPU_READ + //! - \b MPU_WRITE + //! - \b MPU_EXEC + //! - \b MPU_NO_READ_WRITE_EXEC + uint8_t seg1accmask; + //! Is the bit mask of access right for memory segment 2. + //! \n Logical OR of any of the following: + //! - \b MPU_READ + //! - \b MPU_WRITE + //! - \b MPU_EXEC + //! - \b MPU_NO_READ_WRITE_EXEC + uint8_t seg2accmask; + //! Is the bit mask of access right for memory segment 3. + //! \n Logical OR of any of the following: + //! - \b MPU_READ + //! - \b MPU_WRITE + //! - \b MPU_EXEC + //! - \b MPU_NO_READ_WRITE_EXEC + uint8_t seg3accmask; +} MPU_initThreeSegmentsParam; + +//***************************************************************************** +// +// The following are values that can be passed to the accmask parameter for +// functions: MPU_initInfoSegment(); the seg2accmask parameter for functions: +// MPU_initTwoSegments(); the seg1accmask parameter for functions: +// MPU_initTwoSegments(); the param parameter for functions: +// MPU_initThreeSegments(), MPU_initThreeSegments(), and +// MPU_initThreeSegments(). +// +//***************************************************************************** +#define MPU_READ MPUSEG1RE +#define MPU_WRITE MPUSEG1WE +#define MPU_EXEC MPUSEG1XE +#define MPU_NO_READ_WRITE_EXEC (0x0000) + +//***************************************************************************** +// +// The following are values that can be passed to the segment parameter for +// functions: MPU_enablePUCOnViolation(), and MPU_disablePUCOnViolation(). +// +//***************************************************************************** +#define MPU_FIRST_SEG MPUSEG1VS +#define MPU_SECOND_SEG MPUSEG2VS +#define MPU_THIRD_SEG MPUSEG3VS +#define MPU_INFO_SEG MPUSEGIVS + +//***************************************************************************** +// +// The following are values that can be passed to the memAccFlag parameter for +// functions: MPU_getInterruptStatus(), and MPU_clearInterrupt() as well as +// returned by the MPU_getInterruptStatus() function, the +// MPU_clearAllInterrupts() function and the MPU_clearInterrupt() function. +// +//***************************************************************************** +#define MPU_SEG_1_ACCESS_VIOLATION MPUSEG1IFG +#define MPU_SEG_2_ACCESS_VIOLATION MPUSEG2IFG +#define MPU_SEG_3_ACCESS_VIOLATION MPUSEG3IFG +#define MPU_SEG_INFO_ACCESS_VIOLATION MPUSEGIIFG + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Initializes MPU with two memory segments +//! +//! This function creates two memory segments in FRAM allowing the user to set +//! access right to each segment. To set the correct value for seg1boundary, +//! the user must consult the Device Family User's Guide and provide the MPUSBx +//! value corresponding to the memory address where the user wants to create +//! the partition. Consult the "Segment Border Setting" section in the User's +//! Guide to find the options available for MPUSBx. +//! +//! \param baseAddress is the base address of the MPU module. +//! \param seg1boundary Valid values can be found in the Family User's Guide +//! \param seg1accmask is the bit mask of access right for memory segment 1. +//! Mask value is the logical OR of any of the following: +//! - \b MPU_READ - Read rights +//! - \b MPU_WRITE - Write rights +//! - \b MPU_EXEC - Execute rights +//! - \b MPU_NO_READ_WRITE_EXEC - no read/write/execute rights +//! \param seg2accmask is the bit mask of access right for memory segment 2 +//! Mask value is the logical OR of any of the following: +//! - \b MPU_READ - Read rights +//! - \b MPU_WRITE - Write rights +//! - \b MPU_EXEC - Execute rights +//! - \b MPU_NO_READ_WRITE_EXEC - no read/write/execute rights +//! +//! Modified bits of \b MPUSAM register, bits of \b MPUSEG register and bits of +//! \b MPUCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void MPU_initTwoSegments(uint16_t baseAddress, + uint16_t seg1boundary, + uint8_t seg1accmask, + uint8_t seg2accmask); + +//***************************************************************************** +// +//! \brief Initializes MPU with three memory segments +//! +//! This function creates three memory segments in FRAM allowing the user to +//! set access right to each segment. To set the correct value for +//! seg1boundary, the user must consult the Device Family User's Guide and +//! provide the MPUSBx value corresponding to the memory address where the user +//! wants to create the partition. Consult the "Segment Border Setting" section +//! in the User's Guide to find the options available for MPUSBx. +//! +//! \param baseAddress is the base address of the MPU module. +//! \param param is the pointer to struct for initializing three segments. +//! +//! Modified bits of \b MPUSAM register, bits of \b MPUSEG register and bits of +//! \b MPUCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void MPU_initThreeSegments(uint16_t baseAddress, + MPU_initThreeSegmentsParam *param); + +//***************************************************************************** +// +//! \brief Initializes user information memory segment +//! +//! This function initializes user information memory segment with specified +//! access rights. +//! +//! \param baseAddress is the base address of the MPU module. +//! \param accmask is the bit mask of access right for user information memory +//! segment. +//! Mask value is the logical OR of any of the following: +//! - \b MPU_READ - Read rights +//! - \b MPU_WRITE - Write rights +//! - \b MPU_EXEC - Execute rights +//! - \b MPU_NO_READ_WRITE_EXEC - no read/write/execute rights +//! +//! Modified bits of \b MPUSAM register and bits of \b MPUCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void MPU_initInfoSegment(uint16_t baseAddress, + uint8_t accmask); + +//***************************************************************************** +// +//! \brief The following function enables the NMI Event if a Segment violation +//! has occurred. +//! +//! \param baseAddress is the base address of the MPU module. +//! +//! Modified bits of \b MPUCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void MPU_enableNMIevent(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief The following function enables the MPU module in the device. +//! +//! This function needs to be called once all memory segmentation has been +//! done. If this function is not called the MPU module will not be activated. +//! +//! \param baseAddress is the base address of the MPU module. +//! +//! Modified bits of \b MPUCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void MPU_start(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief The following function enables PUC generation when an access +//! violation has occurred on the memory segment selected by the user. +//! +//! Note that only specified segments for PUC generation are enabled. Other +//! segments for PUC generation are left untouched. Users may call +//! MPU_enablePUCOnViolation() and MPU_disablePUCOnViolation() to assure that +//! all the bits will be set and/or cleared. +//! +//! \param baseAddress is the base address of the MPU module. +//! \param segment is the bit mask of memory segment that will generate a PUC +//! when an access violation occurs. +//! Mask value is the logical OR of any of the following: +//! - \b MPU_FIRST_SEG - PUC generation on first memory segment +//! - \b MPU_SECOND_SEG - PUC generation on second memory segment +//! - \b MPU_THIRD_SEG - PUC generation on third memory segment +//! - \b MPU_INFO_SEG - PUC generation on user information memory +//! segment +//! +//! Modified bits of \b MPUSAM register and bits of \b MPUCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void MPU_enablePUCOnViolation(uint16_t baseAddress, + uint16_t segment); + +//***************************************************************************** +// +//! \brief The following function disables PUC generation when an access +//! violation has occurred on the memory segment selected by the user. +//! +//! Note that only specified segments for PUC generation are disabled. Other +//! segments for PUC generation are left untouched. Users may call +//! MPU_enablePUCOnViolation() and MPU_disablePUCOnViolation() to assure that +//! all the bits will be set and/or cleared. +//! +//! \param baseAddress is the base address of the MPU module. +//! \param segment is the bit mask of memory segment that will NOT generate a +//! PUC when an access violation occurs. +//! Mask value is the logical OR of any of the following: +//! - \b MPU_FIRST_SEG - PUC generation on first memory segment +//! - \b MPU_SECOND_SEG - PUC generation on second memory segment +//! - \b MPU_THIRD_SEG - PUC generation on third memory segment +//! - \b MPU_INFO_SEG - PUC generation on user information memory +//! segment +//! +//! Modified bits of \b MPUSAM register and bits of \b MPUCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void MPU_disablePUCOnViolation(uint16_t baseAddress, + uint16_t segment); + +//***************************************************************************** +// +//! \brief Returns the memory segment violation flag status requested by the +//! user. +//! +//! \param baseAddress is the base address of the MPU module. +//! \param memAccFlag is the is the memory access violation flag. +//! Mask value is the logical OR of any of the following: +//! - \b MPU_SEG_1_ACCESS_VIOLATION - is set if an access violation in +//! Main Memory Segment 1 is detected +//! - \b MPU_SEG_2_ACCESS_VIOLATION - is set if an access violation in +//! Main Memory Segment 2 is detected +//! - \b MPU_SEG_3_ACCESS_VIOLATION - is set if an access violation in +//! Main Memory Segment 3 is detected +//! - \b MPU_SEG_INFO_ACCESS_VIOLATION - is set if an access violation +//! in User Information Memory Segment is detected +//! +//! \return Logical OR of any of the following: +//! - \b MPU_SEG_1_ACCESS_VIOLATION is set if an access violation in +//! Main Memory Segment 1 is detected +//! - \b MPU_SEG_2_ACCESS_VIOLATION is set if an access violation in +//! Main Memory Segment 2 is detected +//! - \b MPU_SEG_3_ACCESS_VIOLATION is set if an access violation in +//! Main Memory Segment 3 is detected +//! - \b MPU_SEG_INFO_ACCESS_VIOLATION is set if an access violation in +//! User Information Memory Segment is detected +//! \n indicating the status of the masked flags. +// +//***************************************************************************** +extern uint16_t MPU_getInterruptStatus(uint16_t baseAddress, + uint16_t memAccFlag); + +//***************************************************************************** +// +//! \brief Clears the masked interrupt flags +//! +//! Returns the memory segment violation flag status requested by the user or +//! if user is providing a bit mask value, the function will return a value +//! indicating if all flags were cleared. +//! +//! \param baseAddress is the base address of the MPU module. +//! \param memAccFlag is the is the memory access violation flag. +//! Mask value is the logical OR of any of the following: +//! - \b MPU_SEG_1_ACCESS_VIOLATION - is set if an access violation in +//! Main Memory Segment 1 is detected +//! - \b MPU_SEG_2_ACCESS_VIOLATION - is set if an access violation in +//! Main Memory Segment 2 is detected +//! - \b MPU_SEG_3_ACCESS_VIOLATION - is set if an access violation in +//! Main Memory Segment 3 is detected +//! - \b MPU_SEG_INFO_ACCESS_VIOLATION - is set if an access violation +//! in User Information Memory Segment is detected +//! +//! \return Logical OR of any of the following: +//! - \b MPU_SEG_1_ACCESS_VIOLATION is set if an access violation in +//! Main Memory Segment 1 is detected +//! - \b MPU_SEG_2_ACCESS_VIOLATION is set if an access violation in +//! Main Memory Segment 2 is detected +//! - \b MPU_SEG_3_ACCESS_VIOLATION is set if an access violation in +//! Main Memory Segment 3 is detected +//! - \b MPU_SEG_INFO_ACCESS_VIOLATION is set if an access violation in +//! User Information Memory Segment is detected +//! \n indicating the status of the masked flags. +// +//***************************************************************************** +extern uint16_t MPU_clearInterrupt(uint16_t baseAddress, + uint16_t memAccFlag); + +//***************************************************************************** +// +//! \brief Clears all Memory Segment Access Violation Interrupt Flags. +//! +//! \param baseAddress is the base address of the MPU module. +//! +//! Modified bits of \b MPUCTL1 register. +//! +//! \return Logical OR of any of the following: +//! - \b MPU_SEG_1_ACCESS_VIOLATION is set if an access violation in +//! Main Memory Segment 1 is detected +//! - \b MPU_SEG_2_ACCESS_VIOLATION is set if an access violation in +//! Main Memory Segment 2 is detected +//! - \b MPU_SEG_3_ACCESS_VIOLATION is set if an access violation in +//! Main Memory Segment 3 is detected +//! - \b MPU_SEG_INFO_ACCESS_VIOLATION is set if an access violation in +//! User Information Memory Segment is detected +//! \n indicating the status of the interrupt flags. +// +//***************************************************************************** +extern uint16_t MPU_clearAllInterrupts(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Lock MPU to protect from write access. +//! +//! Sets MPULOCK to protect MPU from write access on all MPU registers except +//! MPUCTL1, MPUIPC0 and MPUIPSEGBx until a BOR occurs. MPULOCK bit cannot be +//! cleared manually. MPU_clearInterrupt() and MPU_clearAllInterrupts() still +//! can be used after this API is called. +//! +//! \param baseAddress is the base address of the MPU module. +//! +//! Modified bits are \b MPULOCK of \b MPUCTL1 register. +//! +//! \return None +// +//***************************************************************************** +extern void MPU_lockMPU(uint16_t baseAddress); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_MPU_H__ diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/mpy32.c b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/mpy32.c new file mode 100644 index 000000000..6639df98e --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/mpy32.c @@ -0,0 +1,179 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// mpy32.c - Driver for the mpy32 Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup mpy32_api mpy32 +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_MPY32__ +#include "mpy32.h" + +#include + +void MPY32_setWriteDelay(uint16_t writeDelaySelect) +{ + HWREG16(MPY32_BASE + OFS_MPY32CTL0) &= ~(MPYDLY32 + MPYDLYWRTEN); + HWREG16(MPY32_BASE + OFS_MPY32CTL0) |= writeDelaySelect; +} + +void MPY32_enableSaturationMode(void) +{ + HWREG8(MPY32_BASE + OFS_MPY32CTL0_L) |= MPYSAT; +} + +void MPY32_disableSaturationMode(void) +{ + HWREG8(MPY32_BASE + OFS_MPY32CTL0_L) &= ~(MPYSAT); +} + +uint8_t MPY32_getSaturationMode(void) +{ + return (HWREG8(MPY32_BASE + OFS_MPY32CTL0_L) & (MPYSAT)); +} + +void MPY32_enableFractionalMode(void) +{ + HWREG8(MPY32_BASE + OFS_MPY32CTL0_L) |= MPYFRAC; +} + +void MPY32_disableFractionalMode(void) +{ + HWREG8(MPY32_BASE + OFS_MPY32CTL0_L) &= ~(MPYFRAC); +} + +uint8_t MPY32_getFractionalMode(void) +{ + return (HWREG8(MPY32_BASE + OFS_MPY32CTL0_L) & (MPYFRAC)); +} + +void MPY32_setOperandOne8Bit(uint8_t multiplicationType, + uint8_t operand) +{ + HWREG8(MPY32_BASE + OFS_MPY + multiplicationType) = operand; +} + +void MPY32_setOperandOne16Bit(uint8_t multiplicationType, + uint16_t operand) +{ + HWREG16(MPY32_BASE + OFS_MPY + multiplicationType) = operand; +} + +void MPY32_setOperandOne24Bit(uint8_t multiplicationType, + uint32_t operand) +{ + multiplicationType <<= 1; + HWREG16(MPY32_BASE + OFS_MPY32L + multiplicationType) = operand; + HWREG8(MPY32_BASE + OFS_MPY32H + multiplicationType) = (operand >> 16); +} + +void MPY32_setOperandOne32Bit(uint8_t multiplicationType, + uint32_t operand) +{ + multiplicationType <<= 1; + HWREG16(MPY32_BASE + OFS_MPY32L + multiplicationType) = operand; + HWREG16(MPY32_BASE + OFS_MPY32H + multiplicationType) = (operand >> 16); +} + +void MPY32_setOperandTwo8Bit(uint8_t operand) +{ + HWREG8(MPY32_BASE + OFS_OP2) = operand; +} + +void MPY32_setOperandTwo16Bit(uint16_t operand) +{ + HWREG16(MPY32_BASE + OFS_OP2) = operand; +} + +void MPY32_setOperandTwo24Bit(uint32_t operand) +{ + HWREG16(MPY32_BASE + OFS_OP2L) = operand; + HWREG8(MPY32_BASE + OFS_OP2H) = (operand >> 16); +} + +void MPY32_setOperandTwo32Bit(uint32_t operand) +{ + HWREG16(MPY32_BASE + OFS_OP2L) = operand; + HWREG16(MPY32_BASE + OFS_OP2H) = (operand >> 16); +} + +uint64_t MPY32_getResult(void) +{ + uint64_t result; + + result = HWREG16(MPY32_BASE + OFS_RES0); + result += ((uint64_t)HWREG16(MPY32_BASE + OFS_RES1) << 16); + result += ((uint64_t)HWREG16(MPY32_BASE + OFS_RES2) << 32); + result += ((uint64_t)HWREG16(MPY32_BASE + OFS_RES3) << 48); + return (result); +} + +uint16_t MPY32_getSumExtension(void) +{ + return (HWREG16(MPY32_BASE + OFS_SUMEXT)); +} + +uint16_t MPY32_getCarryBitValue(void) +{ + return (HWREG16(MPY32_BASE + OFS_MPY32CTL0) | MPYC); +} + +void MPY32_clearCarryBitValue(void) +{ + HWREG16(MPY32_BASE + OFS_MPY32CTL0) &= ~MPYC; +} + +void MPY32_preloadResult(uint64_t result) +{ + HWREG16(MPY32_BASE + OFS_RES0) = (result & 0xFFFF); + HWREG16(MPY32_BASE + OFS_RES1) = ((result >> 16) & 0xFFFF); + HWREG16(MPY32_BASE + OFS_RES2) = ((result >> 32) & 0xFFFF); + HWREG16(MPY32_BASE + OFS_RES3) = ((result >> 48) & 0xFFFF); +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for mpy32_api +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/mpy32.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/mpy32.h new file mode 100644 index 000000000..e229b4a4b --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/mpy32.h @@ -0,0 +1,445 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// mpy32.h - Driver for the MPY32 Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_MPY32_H__ +#define __MSP430WARE_MPY32_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_MPY32__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "inc/hw_regaccess.h" + +//***************************************************************************** +// +// The following are values that can be passed to the writeDelaySelect +// parameter for functions: MPY32_setWriteDelay(). +// +//***************************************************************************** +#define MPY32_WRITEDELAY_OFF (!(MPYDLY32 + MPYDLYWRTEN)) +#define MPY32_WRITEDELAY_32BIT (MPYDLYWRTEN) +#define MPY32_WRITEDELAY_64BIT (MPYDLY32 + MPYDLYWRTEN) + +//***************************************************************************** +// +// The following are values that can be passed to the multiplicationType +// parameter for functions: MPY32_setOperandOne8Bit(), +// MPY32_setOperandOne16Bit(), MPY32_setOperandOne24Bit(), and +// MPY32_setOperandOne32Bit(). +// +//***************************************************************************** +#define MPY32_MULTIPLY_UNSIGNED (0x00) +#define MPY32_MULTIPLY_SIGNED (0x02) +#define MPY32_MULTIPLYACCUMULATE_UNSIGNED (0x04) +#define MPY32_MULTIPLYACCUMULATE_SIGNED (0x06) + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the MPY32_getSaturationMode() function. +// +//***************************************************************************** +#define MPY32_SATURATION_MODE_DISABLED 0x00 +#define MPY32_SATURATION_MODE_ENABLED MPYSAT + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the MPY32_getFractionalMode() function. +// +//***************************************************************************** +#define MPY32_FRACTIONAL_MODE_DISABLED 0x00 +#define MPY32_FRACTIONAL_MODE_ENABLED MPYFRAC + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Sets the write delay setting for the MPY32 module. +//! +//! This function sets up a write delay to the MPY module's registers, which +//! holds any writes to the registers until all calculations are complete. +//! There are two different settings, one which waits for 32-bit results to be +//! ready, and one which waits for 64-bit results to be ready. This prevents +//! unpredicatble results if registers are changed before the results are +//! ready. +//! +//! \param writeDelaySelect delays the write to any MPY32 register until the +//! selected bit size of result has been written. +//! Valid values are: +//! - \b MPY32_WRITEDELAY_OFF [Default] - writes are not delayed +//! - \b MPY32_WRITEDELAY_32BIT - writes are delayed until a 32-bit +//! result is available in the result registers +//! - \b MPY32_WRITEDELAY_64BIT - writes are delayed until a 64-bit +//! result is available in the result registers +//! \n Modified bits are \b MPYDLY32 and \b MPYDLYWRTEN of \b MPY32CTL0 +//! register. +//! +//! \return None +// +//***************************************************************************** +extern void MPY32_setWriteDelay(uint16_t writeDelaySelect); + +//***************************************************************************** +// +//! \brief Enables Saturation Mode. +//! +//! This function enables saturation mode. When this is enabled, the result +//! read out from the MPY result registers is converted to the most-positive +//! number in the case of an overflow, or the most-negative number in the case +//! of an underflow. Please note, that the raw value in the registers does not +//! reflect the result returned, and if the saturation mode is disabled, then +//! the raw value of the registers will be returned instead. +//! +//! +//! \return None +// +//***************************************************************************** +extern void MPY32_enableSaturationMode(void); + +//***************************************************************************** +// +//! \brief Disables Saturation Mode. +//! +//! This function disables saturation mode, which allows the raw result of the +//! MPY result registers to be returned. +//! +//! +//! \return None +// +//***************************************************************************** +extern void MPY32_disableSaturationMode(void); + +//***************************************************************************** +// +//! \brief Gets the Saturation Mode. +//! +//! This function gets the current saturation mode. +//! +//! +//! \return Gets the Saturation Mode +//! Return one of the following: +//! - \b MPY32_SATURATION_MODE_DISABLED +//! - \b MPY32_SATURATION_MODE_ENABLED +//! \n Gets the Saturation Mode +// +//***************************************************************************** +extern uint8_t MPY32_getSaturationMode(void); + +//***************************************************************************** +// +//! \brief Enables Fraction Mode. +//! +//! This function enables fraction mode. +//! +//! +//! \return None +// +//***************************************************************************** +extern void MPY32_enableFractionalMode(void); + +//***************************************************************************** +// +//! \brief Disables Fraction Mode. +//! +//! This function disables fraction mode. +//! +//! +//! \return None +// +//***************************************************************************** +extern void MPY32_disableFractionalMode(void); + +//***************************************************************************** +// +//! \brief Gets the Fractional Mode. +//! +//! This function gets the current fractional mode. +//! +//! +//! \return Gets the fractional mode +//! Return one of the following: +//! - \b MPY32_FRACTIONAL_MODE_DISABLED +//! - \b MPY32_FRACTIONAL_MODE_ENABLED +//! \n Gets the Fractional Mode +// +//***************************************************************************** +extern uint8_t MPY32_getFractionalMode(void); + +//***************************************************************************** +// +//! \brief Sets an 8-bit value into operand 1. +//! +//! This function sets the first operand for multiplication and determines what +//! type of operation should be performed. Once the second operand is set, then +//! the operation will begin. +//! +//! \param multiplicationType is the type of multiplication to perform once the +//! second operand is set. +//! Valid values are: +//! - \b MPY32_MULTIPLY_UNSIGNED +//! - \b MPY32_MULTIPLY_SIGNED +//! - \b MPY32_MULTIPLYACCUMULATE_UNSIGNED +//! - \b MPY32_MULTIPLYACCUMULATE_SIGNED +//! \param operand is the 8-bit value to load into the 1st operand. +//! +//! \return None +// +//***************************************************************************** +extern void MPY32_setOperandOne8Bit(uint8_t multiplicationType, + uint8_t operand); + +//***************************************************************************** +// +//! \brief Sets an 16-bit value into operand 1. +//! +//! This function sets the first operand for multiplication and determines what +//! type of operation should be performed. Once the second operand is set, then +//! the operation will begin. +//! +//! \param multiplicationType is the type of multiplication to perform once the +//! second operand is set. +//! Valid values are: +//! - \b MPY32_MULTIPLY_UNSIGNED +//! - \b MPY32_MULTIPLY_SIGNED +//! - \b MPY32_MULTIPLYACCUMULATE_UNSIGNED +//! - \b MPY32_MULTIPLYACCUMULATE_SIGNED +//! \param operand is the 16-bit value to load into the 1st operand. +//! +//! \return None +// +//***************************************************************************** +extern void MPY32_setOperandOne16Bit(uint8_t multiplicationType, + uint16_t operand); + +//***************************************************************************** +// +//! \brief Sets an 24-bit value into operand 1. +//! +//! This function sets the first operand for multiplication and determines what +//! type of operation should be performed. Once the second operand is set, then +//! the operation will begin. +//! +//! \param multiplicationType is the type of multiplication to perform once the +//! second operand is set. +//! Valid values are: +//! - \b MPY32_MULTIPLY_UNSIGNED +//! - \b MPY32_MULTIPLY_SIGNED +//! - \b MPY32_MULTIPLYACCUMULATE_UNSIGNED +//! - \b MPY32_MULTIPLYACCUMULATE_SIGNED +//! \param operand is the 24-bit value to load into the 1st operand. +//! +//! \return None +// +//***************************************************************************** +extern void MPY32_setOperandOne24Bit(uint8_t multiplicationType, + uint32_t operand); + +//***************************************************************************** +// +//! \brief Sets an 32-bit value into operand 1. +//! +//! This function sets the first operand for multiplication and determines what +//! type of operation should be performed. Once the second operand is set, then +//! the operation will begin. +//! +//! \param multiplicationType is the type of multiplication to perform once the +//! second operand is set. +//! Valid values are: +//! - \b MPY32_MULTIPLY_UNSIGNED +//! - \b MPY32_MULTIPLY_SIGNED +//! - \b MPY32_MULTIPLYACCUMULATE_UNSIGNED +//! - \b MPY32_MULTIPLYACCUMULATE_SIGNED +//! \param operand is the 32-bit value to load into the 1st operand. +//! +//! \return None +// +//***************************************************************************** +extern void MPY32_setOperandOne32Bit(uint8_t multiplicationType, + uint32_t operand); + +//***************************************************************************** +// +//! \brief Sets an 8-bit value into operand 2, which starts the multiplication. +//! +//! This function sets the second operand of the multiplication operation and +//! starts the operation. +//! +//! \param operand is the 8-bit value to load into the 2nd operand. +//! +//! \return None +// +//***************************************************************************** +extern void MPY32_setOperandTwo8Bit(uint8_t operand); + +//***************************************************************************** +// +//! \brief Sets an 16-bit value into operand 2, which starts the +//! multiplication. +//! +//! This function sets the second operand of the multiplication operation and +//! starts the operation. +//! +//! \param operand is the 16-bit value to load into the 2nd operand. +//! +//! \return None +// +//***************************************************************************** +extern void MPY32_setOperandTwo16Bit(uint16_t operand); + +//***************************************************************************** +// +//! \brief Sets an 24-bit value into operand 2, which starts the +//! multiplication. +//! +//! This function sets the second operand of the multiplication operation and +//! starts the operation. +//! +//! \param operand is the 24-bit value to load into the 2nd operand. +//! +//! \return None +// +//***************************************************************************** +extern void MPY32_setOperandTwo24Bit(uint32_t operand); + +//***************************************************************************** +// +//! \brief Sets an 32-bit value into operand 2, which starts the +//! multiplication. +//! +//! This function sets the second operand of the multiplication operation and +//! starts the operation. +//! +//! \param operand is the 32-bit value to load into the 2nd operand. +//! +//! \return None +// +//***************************************************************************** +extern void MPY32_setOperandTwo32Bit(uint32_t operand); + +//***************************************************************************** +// +//! \brief Returns an 64-bit result of the last multiplication operation. +//! +//! This function returns all 64 bits of the result registers +//! +//! +//! \return The 64-bit result is returned as a uint64_t type +// +//***************************************************************************** +extern uint64_t MPY32_getResult(void); + +//***************************************************************************** +// +//! \brief Returns the Sum Extension of the last multiplication operation. +//! +//! This function returns the Sum Extension of the MPY module, which either +//! gives the sign after a signed operation or shows a carry after a multiply- +//! and-accumulate operation. The Sum Extension acts as a check for overflows +//! or underflows. +//! +//! +//! \return The value of the MPY32 module Sum Extension. +// +//***************************************************************************** +extern uint16_t MPY32_getSumExtension(void); + +//***************************************************************************** +// +//! \brief Returns the Carry Bit of the last multiplication operation. +//! +//! This function returns the Carry Bit of the MPY module, which either gives +//! the sign after a signed operation or shows a carry after a multiply- and- +//! accumulate operation. +//! +//! +//! \return The value of the MPY32 module Carry Bit 0x0 or 0x1. +// +//***************************************************************************** +extern uint16_t MPY32_getCarryBitValue(void); + +//***************************************************************************** +// +//! \brief Clears the Carry Bit of the last multiplication operation. +//! +//! This function clears the Carry Bit of the MPY module +//! +//! +//! \return The value of the MPY32 module Carry Bit 0x0 or 0x1. +// +//***************************************************************************** +extern void MPY32_clearCarryBitValue(void); + +//***************************************************************************** +// +//! \brief Preloads the result register +//! +//! This function Preloads the result register +//! +//! \param result value to preload the result register to +//! +//! \return None +// +//***************************************************************************** +extern void MPY32_preloadResult(uint64_t result); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_MPY32_H__ diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/pmm.c b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/pmm.c new file mode 100644 index 000000000..5310ea6dc --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/pmm.c @@ -0,0 +1,132 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// pmm.c - Driver for the pmm Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup pmm_api pmm +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_PMM_FRAM__ +#include "pmm.h" + +#include + +void PMM_enableLowPowerReset(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = PMMPW_H; + HWREG8(PMM_BASE + OFS_PMMCTL0) |= PMMLPRST; + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +void PMM_disableLowPowerReset(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = PMMPW_H; + HWREG8(PMM_BASE + OFS_PMMCTL0) &= ~PMMLPRST; + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +void PMM_enableSVSH(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = PMMPW_H; + HWREG8(PMM_BASE + OFS_PMMCTL0_L) |= SVSHE; + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +void PMM_disableSVSH(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = PMMPW_H; + HWREG8(PMM_BASE + OFS_PMMCTL0_L) &= ~SVSHE; + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +void PMM_turnOnRegulator(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = PMMPW_H; + HWREG8(PMM_BASE + OFS_PMMCTL0) &= ~PMMREGOFF; + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +void PMM_turnOffRegulator(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = PMMPW_H; + HWREG8(PMM_BASE + OFS_PMMCTL0) |= PMMREGOFF; + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +void PMM_trigPOR(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = PMMPW_H; + HWREG8(PMM_BASE + OFS_PMMCTL0) |= PMMSWPOR; + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +void PMM_trigBOR(void) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = PMMPW_H; + HWREG8(PMM_BASE + OFS_PMMCTL0) |= PMMSWBOR; + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +void PMM_clearInterrupt(uint16_t mask) +{ + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = PMMPW_H; + HWREG16(PMM_BASE + OFS_PMMIFG) &= ~mask; + HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00; +} + +uint16_t PMM_getInterruptStatus(uint16_t mask) +{ + return ((HWREG16(PMM_BASE + OFS_PMMIFG)) & mask); +} + +void PMM_unlockLPM5(void) +{ + HWREG8(PMM_BASE + OFS_PM5CTL0) &= ~LOCKLPM5; +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for pmm_api +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/pmm.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/pmm.h new file mode 100644 index 000000000..55698b2bd --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/pmm.h @@ -0,0 +1,244 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// pmm.h - Driver for the PMM Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_PMM_H__ +#define __MSP430WARE_PMM_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_PMM_FRAM__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: PMM_clearInterrupt(), and PMM_getInterruptStatus() as well as +// returned by the PMM_getInterruptStatus() function. +// +//***************************************************************************** +#define PMM_BOR_INTERRUPT PMMBORIFG +#define PMM_RST_INTERRUPT PMMRSTIFG +#define PMM_POR_INTERRUPT PMMPORIFG +#define PMM_SVSH_INTERRUPT SVSHIFG +#define PMM_LPM5_INTERRUPT PMMLPM5IFG +#define PMM_ALL (0xA7) + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Enables the low power reset. SVSH does not reset device, but +//! triggers a system NMI +//! +//! +//! Modified bits of \b PMMCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void PMM_enableLowPowerReset(void); + +//***************************************************************************** +// +//! \brief Disables the low power reset. SVSH resets device. +//! +//! +//! Modified bits of \b PMMCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void PMM_disableLowPowerReset(void); + +//***************************************************************************** +// +//! \brief Enables the high-side SVS circuitry +//! +//! +//! Modified bits of \b PMMCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void PMM_enableSVSH(void); + +//***************************************************************************** +// +//! \brief Disables the high-side SVS circuitry +//! +//! +//! Modified bits of \b PMMCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void PMM_disableSVSH(void); + +//***************************************************************************** +// +//! \brief Makes the low-dropout voltage regulator (LDO) remain ON when going +//! into LPM 3/4. +//! +//! +//! Modified bits of \b PMMCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void PMM_turnOnRegulator(void); + +//***************************************************************************** +// +//! \brief Turns OFF the low-dropout voltage regulator (LDO) when going into +//! LPM3/4, thus the system will enter LPM3.5 or LPM4.5 respectively +//! +//! +//! Modified bits of \b PMMCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void PMM_turnOffRegulator(void); + +//***************************************************************************** +// +//! \brief Calling this function will trigger a software Power On Reset (POR). +//! +//! +//! Modified bits of \b PMMCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void PMM_trigPOR(void); + +//***************************************************************************** +// +//! \brief Calling this function will trigger a software Brown Out Rest (BOR). +//! +//! +//! Modified bits of \b PMMCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void PMM_trigBOR(void); + +//***************************************************************************** +// +//! \brief Clears interrupt flags for the PMM +//! +//! \param mask is the mask for specifying the required flag +//! Mask value is the logical OR of any of the following: +//! - \b PMM_BOR_INTERRUPT - Software BOR interrupt +//! - \b PMM_RST_INTERRUPT - RESET pin interrupt +//! - \b PMM_POR_INTERRUPT - Software POR interrupt +//! - \b PMM_SVSH_INTERRUPT - SVS high side interrupt +//! - \b PMM_LPM5_INTERRUPT - LPM5 indication +//! - \b PMM_ALL - All interrupts +//! +//! Modified bits of \b PMMCTL0 register and bits of \b PMMIFG register. +//! +//! \return None +// +//***************************************************************************** +extern void PMM_clearInterrupt(uint16_t mask); + +//***************************************************************************** +// +//! \brief Returns interrupt status +//! +//! \param mask is the mask for specifying the required flag +//! Mask value is the logical OR of any of the following: +//! - \b PMM_BOR_INTERRUPT - Software BOR interrupt +//! - \b PMM_RST_INTERRUPT - RESET pin interrupt +//! - \b PMM_POR_INTERRUPT - Software POR interrupt +//! - \b PMM_SVSH_INTERRUPT - SVS high side interrupt +//! - \b PMM_LPM5_INTERRUPT - LPM5 indication +//! - \b PMM_ALL - All interrupts +//! +//! \return Logical OR of any of the following: +//! - \b PMM_BOR_INTERRUPT Software BOR interrupt +//! - \b PMM_RST_INTERRUPT RESET pin interrupt +//! - \b PMM_POR_INTERRUPT Software POR interrupt +//! - \b PMM_SVSH_INTERRUPT SVS high side interrupt +//! - \b PMM_LPM5_INTERRUPT LPM5 indication +//! - \b PMM_ALL All interrupts +//! \n indicating the status of the selected interrupt flags +// +//***************************************************************************** +extern uint16_t PMM_getInterruptStatus(uint16_t mask); + +//***************************************************************************** +// +//! \brief Unlock LPM5 +//! +//! LPMx.5 configuration is not locked and defaults to its reset condition. +//! Disable the GPIO power-on default high-impedance mode to activate +//! previously configured port settings. +//! +//! +//! \return None +// +//***************************************************************************** +extern void PMM_unlockLPM5(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_PMM_H__ diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/ram.c b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/ram.c new file mode 100644 index 000000000..051314819 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/ram.c @@ -0,0 +1,74 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// ram.c - Driver for the ram Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ram_api ram +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_RC_FRAM__ +#include "ram.h" + +#include + +void RAM_setSectorOff(uint8_t sector, + uint8_t mode) +{ + uint8_t sectorPos = sector << 1; + uint8_t val = HWREG8(RAM_BASE + OFS_RCCTL0_L) & ~(0x3 << sectorPos); + + HWREG16(RAM_BASE + OFS_RCCTL0) = (RCKEY | val | (mode << sectorPos)); +} + +uint8_t RAM_getSectorState(uint8_t sector) +{ + uint8_t sectorPos = sector << 1; + return((HWREG8(RAM_BASE + OFS_RCCTL0_L) & (0x3 << sectorPos)) >> sectorPos); +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for ram_api +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/ram.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/ram.h new file mode 100644 index 000000000..248879ffe --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/ram.h @@ -0,0 +1,138 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// ram.h - Driver for the RAM Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_RAM_H__ +#define __MSP430WARE_RAM_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_RC_FRAM__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the sector parameter for +// functions: RAM_setSectorOff(), and RAM_getSectorState(). +// +//***************************************************************************** +#define RAM_SECTOR0 (0x00) +#define RAM_SECTOR1 (0x01) +#define RAM_SECTOR2 (0x02) +#define RAM_SECTOR3 (0x03) + +//***************************************************************************** +// +// The following are values that can be passed to the mode parameter for +// functions: RAM_setSectorOff() as well as returned by the +// RAM_getSectorState() function. +// +//***************************************************************************** +#define RAM_RETENTION_MODE (0x00) +#define RAM_OFF_WAKEUP_MODE (RCRS0OFF0) +#define RAM_OFF_NON_WAKEUP_MODE (RCRS0OFF1) + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Set specified RAM sector off +//! +//! \param sector is specified sector to be set off. +//! Valid values are: +//! - \b RAM_SECTOR0 +//! - \b RAM_SECTOR1 +//! - \b RAM_SECTOR2 +//! - \b RAM_SECTOR3 +//! \param mode is sector off mode +//! Valid values are: +//! - \b RAM_RETENTION_MODE +//! - \b RAM_OFF_WAKEUP_MODE +//! - \b RAM_OFF_NON_WAKEUP_MODE +//! +//! Modified bits of \b RCCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void RAM_setSectorOff(uint8_t sector, + uint8_t mode); + +//***************************************************************************** +// +//! \brief Get RAM sector ON/OFF status +//! +//! \param sector is specified sector +//! Valid values are: +//! - \b RAM_SECTOR0 +//! - \b RAM_SECTOR1 +//! - \b RAM_SECTOR2 +//! - \b RAM_SECTOR3 +//! +//! \return One of the following: +//! - \b RAM_RETENTION_MODE +//! - \b RAM_OFF_WAKEUP_MODE +//! - \b RAM_OFF_NON_WAKEUP_MODE +//! \n indicating the status of the masked sectors +// +//***************************************************************************** +extern uint8_t RAM_getSectorState(uint8_t sector); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_RAM_H__ diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/ref_a.c b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/ref_a.c new file mode 100644 index 000000000..e5d07fbb2 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/ref_a.c @@ -0,0 +1,164 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// ref_a.c - Driver for the ref_a Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup ref_a_api ref_a +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_REF_A__ +#include "ref_a.h" + +#include + +void Ref_A_setReferenceVoltage(uint16_t baseAddress, + uint8_t referenceVoltageSelect) +{ + HWREG8(baseAddress + OFS_REFCTL0_L) &= ~(REFVSEL_3); + HWREG8(baseAddress + OFS_REFCTL0_L) |= referenceVoltageSelect; +} + +void Ref_A_disableTempSensor(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_REFCTL0_L) |= REFTCOFF; +} + +void Ref_A_enableTempSensor(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_REFCTL0_L) &= ~(REFTCOFF); +} + +void Ref_A_enableReferenceVoltageOutput(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_REFCTL0_L) |= REFOUT; +} + +void Ref_A_disableReferenceVoltageOutput(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_REFCTL0_L) &= ~(REFOUT); +} + +void Ref_A_enableReferenceVoltage(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_REFCTL0_L) |= REFON; +} + +void Ref_A_disableReferenceVoltage(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_REFCTL0_L) &= ~(REFON); +} + +uint16_t Ref_A_getBandgapMode(uint16_t baseAddress) +{ + return (HWREG16((baseAddress) + OFS_REFCTL0) & BGMODE); +} + +bool Ref_A_isBandgapActive(uint16_t baseAddress) +{ + if(HWREG16((baseAddress) + OFS_REFCTL0) & REFBGACT) + { + return (REF_A_ACTIVE); + } + else + { + return (REF_A_INACTIVE); + } +} + +uint16_t Ref_A_isRefGenBusy(uint16_t baseAddress) +{ + return (HWREG16((baseAddress) + OFS_REFCTL0) & REFGENBUSY); +} + +bool Ref_A_isRefGenActive(uint16_t baseAddress) +{ + if(HWREG16((baseAddress) + OFS_REFCTL0) & REFGENACT) + { + return (REF_A_ACTIVE); + } + else + { + return (REF_A_INACTIVE); + } +} + +bool Ref_A_isBufferedBandgapVoltageReady(uint16_t baseAddress) +{ + if(HWREG16((baseAddress) + OFS_REFCTL0) & REFBGRDY) + { + return (REF_A_READY); + } + else + { + return (REF_A_NOTREADY); + } +} + +bool Ref_A_isVariableReferenceVoltageOutputReady(uint16_t baseAddress) +{ + if(HWREG16((baseAddress) + OFS_REFCTL0) & REFGENRDY) + { + return (REF_A_READY); + } + else + { + return (REF_A_NOTREADY); + } +} + +void Ref_A_setReferenceVoltageOneTimeTrigger(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_REFCTL0_L) |= REFGENOT; +} + +void Ref_A_setBufferedBandgapVoltageOneTimeTrigger(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_REFCTL0_L) |= REFBGOT; +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for ref_a_api +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/ref_a.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/ref_a.h new file mode 100644 index 000000000..d36ed9ac4 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/ref_a.h @@ -0,0 +1,407 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// ref_a.h - Driver for the REF_A Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_REF_A_H__ +#define __MSP430WARE_REF_A_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_REF_A__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the referenceVoltageSelect +// parameter for functions: Ref_A_setReferenceVoltage(). +// +//***************************************************************************** +#define REF_A_VREF1_2V (REFVSEL_0) +#define REF_A_VREF2_0V (REFVSEL_1) +#define REF_A_VREF2_5V (REFVSEL_2) + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the Ref_A_isBandgapActive() function and the +// Ref_A_isRefGenActive() function. +// +//***************************************************************************** +#define REF_A_ACTIVE true +#define REF_A_INACTIVE false + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the Ref_A_getBandgapMode() function. +// +//***************************************************************************** +#define REF_A_STATICMODE 0x00 +#define REF_A_SAMPLEMODE BGMODE + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the Ref_A_isRefGenBusy() function. +// +//***************************************************************************** +#define REF_A_NOTBUSY 0x00 +#define REF_A_BUSY REFGENBUSY + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the Ref_A_isVariableReferenceVoltageOutputReady() +// function and the Ref_A_isBufferedBandgapVoltageReady() function. +// +//***************************************************************************** +#define REF_A_NOTREADY false +#define REF_A_READY true + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Sets the reference voltage for the voltage generator. +//! +//! This function sets the reference voltage generated by the voltage generator +//! to be used by other peripherals. This reference voltage will only be valid +//! while the Ref_A module is in control. Please note, if the +//! Ref_A_isRefGenBusy() returns Ref_A_BUSY, this function will have no effect. +//! +//! \param baseAddress is the base address of the REF_A module. +//! \param referenceVoltageSelect is the desired voltage to generate for a +//! reference voltage. +//! Valid values are: +//! - \b REF_A_VREF1_2V [Default] +//! - \b REF_A_VREF2_0V +//! - \b REF_A_VREF2_5V +//! \n Modified bits are \b REFVSEL of \b REFCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void Ref_A_setReferenceVoltage(uint16_t baseAddress, + uint8_t referenceVoltageSelect); + +//***************************************************************************** +// +//! \brief Disables the internal temperature sensor to save power consumption. +//! +//! This function is used to turn off the internal temperature sensor to save +//! on power consumption. The temperature sensor is enabled by default. Please +//! note, that giving ADC12 module control over the Ref_A module, the state of +//! the temperature sensor is dependent on the controls of the ADC12 module. +//! Please note, if the Ref_A_isRefGenBusy() returns Ref_A_BUSY, this function +//! will have no effect. +//! +//! \param baseAddress is the base address of the REF_A module. +//! +//! Modified bits are \b REFTCOFF of \b REFCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void Ref_A_disableTempSensor(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Enables the internal temperature sensor. +//! +//! This function is used to turn on the internal temperature sensor to use by +//! other peripherals. The temperature sensor is enabled by default. Please +//! note, if the Ref_A_isRefGenBusy() returns Ref_A_BUSY, this function will +//! have no effect. +//! +//! \param baseAddress is the base address of the REF_A module. +//! +//! Modified bits are \b REFTCOFF of \b REFCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void Ref_A_enableTempSensor(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Outputs the reference voltage to an output pin. +//! +//! This function is used to output the reference voltage being generated to an +//! output pin. Please note, the output pin is device specific. Please note, +//! that giving ADC12 module control over the Ref_A module, the state of the +//! reference voltage as an output to a pin is dependent on the controls of the +//! ADC12 module. Please note, if the Ref_A_isRefGenBusy() returns Ref_A_BUSY, +//! this function will have no effect. +//! +//! \param baseAddress is the base address of the REF_A module. +//! +//! Modified bits are \b REFOUT of \b REFCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void Ref_A_enableReferenceVoltageOutput(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Disables the reference voltage as an output to a pin. +//! +//! This function is used to disables the reference voltage being generated to +//! be given to an output pin. Please note, if the Ref_A_isRefGenBusy() returns +//! Ref_A_BUSY, this function will have no effect. +//! +//! \param baseAddress is the base address of the REF_A module. +//! +//! Modified bits are \b REFOUT of \b REFCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void Ref_A_disableReferenceVoltageOutput(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Enables the reference voltage to be used by peripherals. +//! +//! This function is used to enable the generated reference voltage to be used +//! other peripherals or by an output pin, if enabled. Please note, that giving +//! ADC12 module control over the Ref_A module, the state of the reference +//! voltage is dependent on the controls of the ADC12 module. Please note, if +//! the Ref_A_isRefGenBusy() returns Ref_A_BUSY, this function will have no +//! effect. +//! +//! \param baseAddress is the base address of the REF_A module. +//! +//! Modified bits are \b REFON of \b REFCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void Ref_A_enableReferenceVoltage(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Disables the reference voltage. +//! +//! This function is used to disable the generated reference voltage. Please +//! note, if the Ref_A_isRefGenBusy() returns Ref_A_BUSY, this function will +//! have no effect. +//! +//! \param baseAddress is the base address of the REF_A module. +//! +//! Modified bits are \b REFON of \b REFCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void Ref_A_disableReferenceVoltage(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Returns the bandgap mode of the Ref_A module. +//! +//! This function is used to return the bandgap mode of the Ref_A module, +//! requested by the peripherals using the bandgap. If a peripheral requests +//! static mode, then the bandgap mode will be static for all modules, whereas +//! if all of the peripherals using the bandgap request sample mode, then that +//! will be the mode returned. Sample mode allows the bandgap to be active only +//! when necessary to save on power consumption, static mode requires the +//! bandgap to be active until no peripherals are using it anymore. +//! +//! \param baseAddress is the base address of the REF_A module. +//! +//! \return One of the following: +//! - \b Ref_A_STATICMODE if the bandgap is operating in static mode +//! - \b Ref_A_SAMPLEMODE if the bandgap is operating in sample mode +//! \n indicating the bandgap mode of the module +// +//***************************************************************************** +extern uint16_t Ref_A_getBandgapMode(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Returns the active status of the bandgap in the Ref_A module. +//! +//! This function is used to return the active status of the bandgap in the +//! Ref_A module. If the bandgap is in use by a peripheral, then the status +//! will be seen as active. +//! +//! \param baseAddress is the base address of the REF_A module. +//! +//! \return One of the following: +//! - \b Ref_A_ACTIVE if active +//! - \b Ref_A_INACTIVE if not active +//! \n indicating the bandgap active status of the module +// +//***************************************************************************** +extern bool Ref_A_isBandgapActive(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Returns the busy status of the reference generator in the Ref_A +//! module. +//! +//! This function is used to return the busy status of the reference generator +//! in the Ref_A module. If the ref generator is in use by a peripheral, then +//! the status will be seen as busy. +//! +//! \param baseAddress is the base address of the REF_A module. +//! +//! \return One of the following: +//! - \b Ref_A_NOTBUSY if the reference generator is not being used +//! - \b Ref_A_BUSY if the reference generator is being used, +//! disallowing changes to be made to the Ref_A module controls +//! \n indicating the reference generator busy status of the module +// +//***************************************************************************** +extern uint16_t Ref_A_isRefGenBusy(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Returns the active status of the reference generator in the Ref_A +//! module. +//! +//! This function is used to return the active status of the reference +//! generator in the Ref_A module. If the ref generator is on and ready to use, +//! then the status will be seen as active. +//! +//! \param baseAddress is the base address of the REF_A module. +//! +//! \return One of the following: +//! - \b Ref_A_ACTIVE if active +//! - \b Ref_A_INACTIVE if not active +//! \n indicating the reference generator active status of the module +// +//***************************************************************************** +extern bool Ref_A_isRefGenActive(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Returns the busy status of the reference generator in the Ref_A +//! module. +//! +//! This function is used to return the buys status of the buffered bandgap +//! voltage in the Ref_A module. If the ref generator is on and ready to use, +//! then the status will be seen as active. +//! +//! \param baseAddress is the base address of the REF_A module. +//! +//! \return One of the following: +//! - \b Ref_A_NOTREADY if NOT ready to be used +//! - \b Ref_A_READY if ready to be used +//! \n indicating the the busy status of the reference generator in the +//! module +// +//***************************************************************************** +extern bool Ref_A_isBufferedBandgapVoltageReady(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Returns the busy status of the variable reference voltage in the +//! Ref_A module. +//! +//! This function is used to return the busy status of the variable reference +//! voltage in the Ref_A module. If the ref generator is on and ready to use, +//! then the status will be seen as active. +//! +//! \param baseAddress is the base address of the REF_A module. +//! +//! \return One of the following: +//! - \b Ref_A_NOTREADY if NOT ready to be used +//! - \b Ref_A_READY if ready to be used +//! \n indicating the the busy status of the variable reference voltage +//! in the module +// +//***************************************************************************** +extern bool Ref_A_isVariableReferenceVoltageOutputReady(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Enables the one-time trigger of the reference voltage. +//! +//! Triggers the one-time generation of the variable reference voltage. Once +//! the reference voltage request is set, this bit is cleared by hardware +//! +//! \param baseAddress is the base address of the REF_A module. +//! +//! Modified bits are \b REFGENOT of \b REFCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void Ref_A_setReferenceVoltageOneTimeTrigger(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Enables the one-time trigger of the buffered bandgap voltage. +//! +//! Triggers the one-time generation of the buffered bandgap voltage. Once the +//! buffered bandgap voltage request is set, this bit is cleared by hardware +//! +//! \param baseAddress is the base address of the REF_A module. +//! +//! Modified bits are \b REFBGOT of \b REFCTL0 register. +//! +//! \return None +// +//***************************************************************************** +extern void Ref_A_setBufferedBandgapVoltageOneTimeTrigger(uint16_t baseAddress); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_REF_A_H__ diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/rtc_b.c b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/rtc_b.c new file mode 100644 index 000000000..e99af60d8 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/rtc_b.c @@ -0,0 +1,292 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// rtc_b.c - Driver for the rtc_b Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup rtc_b_api rtc_b +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_RTC_B__ +#include "rtc_b.h" + +#include + +void RTC_B_startClock(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_RTCCTL01_H) &= ~(RTCHOLD_H); +} + +void RTC_B_holdClock(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_RTCCTL01_H) |= RTCHOLD_H; +} + +void RTC_B_setCalibrationFrequency(uint16_t baseAddress, + uint16_t frequencySelect) +{ + HWREG16(baseAddress + OFS_RTCCTL23) &= ~(RTCCALF_3); + HWREG16(baseAddress + OFS_RTCCTL23) |= frequencySelect; +} + +void RTC_B_setCalibrationData(uint16_t baseAddress, + uint8_t offsetDirection, + uint8_t offsetValue) +{ + HWREG8(baseAddress + OFS_RTCCTL23_L) = offsetValue + offsetDirection; +} + +void RTC_B_initCalendar(uint16_t baseAddress, + Calendar *CalendarTime, + uint16_t formatSelect) +{ + HWREG8(baseAddress + OFS_RTCCTL01_H) |= RTCHOLD_H; + + HWREG16(baseAddress + OFS_RTCCTL01) &= ~(RTCBCD); + HWREG16(baseAddress + OFS_RTCCTL01) |= formatSelect; + + HWREG8(baseAddress + OFS_RTCTIM0_L) = CalendarTime->Seconds; + HWREG8(baseAddress + OFS_RTCTIM0_H) = CalendarTime->Minutes; + HWREG8(baseAddress + OFS_RTCTIM1_L) = CalendarTime->Hours; + HWREG8(baseAddress + OFS_RTCTIM1_H) = CalendarTime->DayOfWeek; + HWREG8(baseAddress + OFS_RTCDATE_L) = CalendarTime->DayOfMonth; + HWREG8(baseAddress + OFS_RTCDATE_H) = CalendarTime->Month; + HWREG16(baseAddress + OFS_RTCYEAR) = CalendarTime->Year; +} + +Calendar RTC_B_getCalendarTime(uint16_t baseAddress) +{ + Calendar tempCal; + + while(!(HWREG16(baseAddress + OFS_RTCCTL01) & RTCRDY)) + { + ; + } + + tempCal.Seconds = HWREG8(baseAddress + OFS_RTCTIM0_L); + tempCal.Minutes = HWREG8(baseAddress + OFS_RTCTIM0_H); + tempCal.Hours = HWREG8(baseAddress + OFS_RTCTIM1_L); + tempCal.DayOfWeek = HWREG8(baseAddress + OFS_RTCTIM1_H); + tempCal.DayOfMonth = HWREG8(baseAddress + OFS_RTCDATE_L); + tempCal.Month = HWREG8(baseAddress + OFS_RTCDATE_H); + tempCal.Year = HWREG16(baseAddress + OFS_RTCYEAR); + + return (tempCal); +} + +void RTC_B_configureCalendarAlarm(uint16_t baseAddress, + RTC_B_configureCalendarAlarmParam *param) +{ + //Each of these is XORed with 0x80 to turn on if an integer is passed, + //or turn OFF if RTC_B_ALARM_OFF (0x80) is passed. + HWREG8(baseAddress + OFS_RTCAMINHR_L) = (param->minutesAlarm ^ 0x80); + HWREG8(baseAddress + OFS_RTCAMINHR_H) = (param->hoursAlarm ^ 0x80); + HWREG8(baseAddress + OFS_RTCADOWDAY_L) = (param->dayOfWeekAlarm ^ 0x80); + HWREG8(baseAddress + OFS_RTCADOWDAY_H) = (param->dayOfMonthAlarm ^ 0x80); +} + +void RTC_B_setCalendarEvent(uint16_t baseAddress, + uint16_t eventSelect) +{ + HWREG16(baseAddress + OFS_RTCCTL01) &= ~(RTCTEV_3); //Reset bits + HWREG16(baseAddress + OFS_RTCCTL01) |= eventSelect; +} + +void RTC_B_definePrescaleEvent(uint16_t baseAddress, + uint8_t prescaleSelect, + uint8_t prescaleEventDivider) +{ + HWREG8(baseAddress + OFS_RTCPS0CTL_L + prescaleSelect) &= ~(RT0IP_7); + HWREG8(baseAddress + OFS_RTCPS0CTL_L + + prescaleSelect) |= prescaleEventDivider; +} + +uint8_t RTC_B_getPrescaleValue(uint16_t baseAddress, + uint8_t prescaleSelect) +{ + if(RTC_B_PRESCALE_0 == prescaleSelect) + { + return (HWREG8(baseAddress + OFS_RTCPS_L)); + } + else if(RTC_B_PRESCALE_1 == prescaleSelect) + { + return (HWREG8(baseAddress + OFS_RTCPS_H)); + } + else + { + return (0); + } +} + +void RTC_B_setPrescaleValue(uint16_t baseAddress, + uint8_t prescaleSelect, + uint8_t prescaleCounterValue) +{ + if(RTC_B_PRESCALE_0 == prescaleSelect) + { + HWREG8(baseAddress + OFS_RTCPS_L) = prescaleCounterValue; + } + else if(RTC_B_PRESCALE_1 == prescaleSelect) + { + HWREG8(baseAddress + OFS_RTCPS_H) = prescaleCounterValue; + } +} + +void RTC_B_enableInterrupt(uint16_t baseAddress, + uint8_t interruptMask) +{ + if(interruptMask & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE)) + { + HWREG8(baseAddress + OFS_RTCCTL01_L) |= + (interruptMask & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE)); + } + + if(interruptMask & RTC_B_PRESCALE_TIMER0_INTERRUPT) + { + HWREG8(baseAddress + OFS_RTCPS0CTL) |= RT0PSIE; + } + + if(interruptMask & RTC_B_PRESCALE_TIMER1_INTERRUPT) + { + HWREG8(baseAddress + OFS_RTCPS1CTL) |= RT1PSIE; + } +} + +void RTC_B_disableInterrupt(uint16_t baseAddress, + uint8_t interruptMask) +{ + if(interruptMask & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE)) + { + HWREG8(baseAddress + OFS_RTCCTL01_L) &= + ~(interruptMask & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE)); + } + + if(interruptMask & RTC_B_PRESCALE_TIMER0_INTERRUPT) + { + HWREG8(baseAddress + OFS_RTCPS0CTL) &= ~(RT0PSIE); + } + + if(interruptMask & RTC_B_PRESCALE_TIMER1_INTERRUPT) + { + HWREG8(baseAddress + OFS_RTCPS1CTL) &= ~(RT1PSIE); + } +} + +uint8_t RTC_B_getInterruptStatus(uint16_t baseAddress, + uint8_t interruptFlagMask) +{ + uint8_t tempInterruptFlagMask = 0x0000; + + tempInterruptFlagMask |= (HWREG8(baseAddress + OFS_RTCCTL01_L) + & ((interruptFlagMask >> 4) + & (RTCOFIFG + + RTCTEVIFG + + RTCAIFG + + RTCRDYIFG))); + + tempInterruptFlagMask = tempInterruptFlagMask << 4; + + if(interruptFlagMask & RTC_B_PRESCALE_TIMER0_INTERRUPT) + { + if(HWREG8(baseAddress + OFS_RTCPS0CTL) & RT0PSIFG) + { + tempInterruptFlagMask |= RTC_B_PRESCALE_TIMER0_INTERRUPT; + } + } + + if(interruptFlagMask & RTC_B_PRESCALE_TIMER1_INTERRUPT) + { + if(HWREG8(baseAddress + OFS_RTCPS1CTL) & RT1PSIFG) + { + tempInterruptFlagMask |= RTC_B_PRESCALE_TIMER1_INTERRUPT; + } + } + + return (tempInterruptFlagMask); +} + +void RTC_B_clearInterrupt(uint16_t baseAddress, + uint8_t interruptFlagMask) +{ + if(interruptFlagMask & (RTC_B_TIME_EVENT_INTERRUPT + + RTC_B_CLOCK_ALARM_INTERRUPT + + RTC_B_CLOCK_READ_READY_INTERRUPT + + RTC_B_OSCILLATOR_FAULT_INTERRUPT)) + { + HWREG8(baseAddress + OFS_RTCCTL01_L) &= + ~((interruptFlagMask >> 4) & (RTCOFIFG + + RTCTEVIFG + + RTCAIFG + + RTCRDYIFG)); + } + + if(interruptFlagMask & RTC_B_PRESCALE_TIMER0_INTERRUPT) + { + HWREG8(baseAddress + OFS_RTCPS0CTL) &= ~(RT0PSIFG); + } + + if(interruptFlagMask & RTC_B_PRESCALE_TIMER1_INTERRUPT) + { + HWREG8(baseAddress + OFS_RTCPS1CTL) &= ~(RT1PSIFG); + } +} + +uint16_t RTC_B_convertBCDToBinary(uint16_t baseAddress, + uint16_t valueToConvert) +{ + HWREG16(baseAddress + OFS_BCD2BIN) = valueToConvert; + return (HWREG16(baseAddress + OFS_BCD2BIN)); +} + +uint16_t RTC_B_convertBinaryToBCD(uint16_t baseAddress, + uint16_t valueToConvert) +{ + HWREG16(baseAddress + OFS_BIN2BCD) = valueToConvert; + return (HWREG16(baseAddress + OFS_BIN2BCD)); +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for rtc_b_api +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/rtc_b.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/rtc_b.h new file mode 100644 index 000000000..784df8016 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/rtc_b.h @@ -0,0 +1,633 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// rtc_b.h - Driver for the RTC_B Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_RTC_B_H__ +#define __MSP430WARE_RTC_B_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_RTC_B__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "inc/hw_regaccess.h" +//***************************************************************************** +// +//! \brief Used in the RTC_B_initCalendar() function as the CalendarTime +//! parameter. +// +//***************************************************************************** +typedef struct Calendar +{ + //! Seconds of minute between 0-59 + uint8_t Seconds; + //! Minutes of hour between 0-59 + uint8_t Minutes; + //! Hour of day between 0-23 + uint8_t Hours; + //! Day of week between 0-6 + uint8_t DayOfWeek; + //! Day of month between 1-31 + uint8_t DayOfMonth; + //! Month between 0-11 + uint8_t Month; + //! Year between 0-4095 + uint16_t Year; +} Calendar; + +//***************************************************************************** +// +//! \brief Used in the RTC_B_configureCalendarAlarm() function as the param +//! parameter. +// +//***************************************************************************** +typedef struct RTC_B_configureCalendarAlarmParam +{ + //! Is the alarm condition for the minutes. + //! \n Valid values are: + //! - \b RTC_B_ALARMCONDITION_OFF [Default] + uint8_t minutesAlarm; + //! Is the alarm condition for the hours. + //! \n Valid values are: + //! - \b RTC_B_ALARMCONDITION_OFF [Default] + uint8_t hoursAlarm; + //! Is the alarm condition for the day of week. + //! \n Valid values are: + //! - \b RTC_B_ALARMCONDITION_OFF [Default] + uint8_t dayOfWeekAlarm; + //! Is the alarm condition for the day of the month. + //! \n Valid values are: + //! - \b RTC_B_ALARMCONDITION_OFF [Default] + uint8_t dayOfMonthAlarm; +} RTC_B_configureCalendarAlarmParam; + +//***************************************************************************** +// +// The following are values that can be passed to the frequencySelect parameter +// for functions: RTC_B_setCalibrationFrequency(). +// +//***************************************************************************** +#define RTC_B_CALIBRATIONFREQ_OFF (RTCCALF_0) +#define RTC_B_CALIBRATIONFREQ_512HZ (RTCCALF_1) +#define RTC_B_CALIBRATIONFREQ_256HZ (RTCCALF_2) +#define RTC_B_CALIBRATIONFREQ_1HZ (RTCCALF_3) + +//***************************************************************************** +// +// The following are values that can be passed to the offsetDirection parameter +// for functions: RTC_B_setCalibrationData(). +// +//***************************************************************************** +#define RTC_B_CALIBRATION_DOWN2PPM (!(RTCCALS)) +#define RTC_B_CALIBRATION_UP4PPM (RTCCALS) + +//***************************************************************************** +// +// The following are values that can be passed to the formatSelect parameter +// for functions: RTC_B_initCalendar(). +// +//***************************************************************************** +#define RTC_B_FORMAT_BINARY (!(RTCBCD)) +#define RTC_B_FORMAT_BCD (RTCBCD) + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: RTC_B_configureCalendarAlarm(), RTC_B_configureCalendarAlarm(), +// RTC_B_configureCalendarAlarm(), and RTC_B_configureCalendarAlarm(). +// +//***************************************************************************** +#define RTC_B_ALARMCONDITION_OFF (0x80) + +//***************************************************************************** +// +// The following are values that can be passed to the eventSelect parameter for +// functions: RTC_B_setCalendarEvent(). +// +//***************************************************************************** +#define RTC_B_CALENDAREVENT_MINUTECHANGE (RTCTEV_0) +#define RTC_B_CALENDAREVENT_HOURCHANGE (RTCTEV_1) +#define RTC_B_CALENDAREVENT_NOON (RTCTEV_2) +#define RTC_B_CALENDAREVENT_MIDNIGHT (RTCTEV_3) + +//***************************************************************************** +// +// The following are values that can be passed to the prescaleEventDivider +// parameter for functions: RTC_B_definePrescaleEvent(). +// +//***************************************************************************** +#define RTC_B_PSEVENTDIVIDER_2 (RT0IP_0) +#define RTC_B_PSEVENTDIVIDER_4 (RT0IP_1) +#define RTC_B_PSEVENTDIVIDER_8 (RT0IP_2) +#define RTC_B_PSEVENTDIVIDER_16 (RT0IP_3) +#define RTC_B_PSEVENTDIVIDER_32 (RT0IP_4) +#define RTC_B_PSEVENTDIVIDER_64 (RT0IP_5) +#define RTC_B_PSEVENTDIVIDER_128 (RT0IP_6) +#define RTC_B_PSEVENTDIVIDER_256 (RT0IP_7) + +//***************************************************************************** +// +// The following are values that can be passed to the prescaleSelect parameter +// for functions: RTC_B_definePrescaleEvent(), RTC_B_getPrescaleValue(), and +// RTC_B_setPrescaleValue(). +// +//***************************************************************************** +#define RTC_B_PRESCALE_0 (0x0) +#define RTC_B_PRESCALE_1 (0x2) + +//***************************************************************************** +// +// The following are values that can be passed to the interruptMask parameter +// for functions: RTC_B_enableInterrupt(), and RTC_B_disableInterrupt(); the +// interruptFlagMask parameter for functions: RTC_B_getInterruptStatus(), and +// RTC_B_clearInterrupt() as well as returned by the RTC_B_getInterruptStatus() +// function. +// +//***************************************************************************** +#define RTC_B_TIME_EVENT_INTERRUPT RTCTEVIE +#define RTC_B_CLOCK_ALARM_INTERRUPT RTCAIE +#define RTC_B_CLOCK_READ_READY_INTERRUPT RTCRDYIE +#define RTC_B_PRESCALE_TIMER0_INTERRUPT 0x02 +#define RTC_B_PRESCALE_TIMER1_INTERRUPT 0x01 +#define RTC_B_OSCILLATOR_FAULT_INTERRUPT RTCOFIE + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Starts the RTC. +//! +//! This function clears the RTC main hold bit to allow the RTC to function. +//! +//! \param baseAddress is the base address of the RTC_B module. +//! +//! \return None +// +//***************************************************************************** +extern void RTC_B_startClock(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Holds the RTC. +//! +//! This function sets the RTC main hold bit to disable RTC functionality. +//! +//! \param baseAddress is the base address of the RTC_B module. +//! +//! \return None +// +//***************************************************************************** +extern void RTC_B_holdClock(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Allows and Sets the frequency output to RTCCLK pin for calibration +//! measurement. +//! +//! This function sets a frequency to measure at the RTCCLK output pin. After +//! testing the set frequency, the calibration could be set accordingly. +//! +//! \param baseAddress is the base address of the RTC_B module. +//! \param frequencySelect is the frequency output to RTCCLK. +//! Valid values are: +//! - \b RTC_B_CALIBRATIONFREQ_OFF [Default] - turn off calibration +//! output +//! - \b RTC_B_CALIBRATIONFREQ_512HZ - output signal at 512Hz for +//! calibration +//! - \b RTC_B_CALIBRATIONFREQ_256HZ - output signal at 256Hz for +//! calibration +//! - \b RTC_B_CALIBRATIONFREQ_1HZ - output signal at 1Hz for +//! calibration +//! \n Modified bits are \b RTCCALF of \b RTCCTL3 register. +//! +//! \return None +// +//***************************************************************************** +extern void RTC_B_setCalibrationFrequency(uint16_t baseAddress, + uint16_t frequencySelect); + +//***************************************************************************** +// +//! \brief Sets the specified calibration for the RTC. +//! +//! This function sets the calibration offset to make the RTC as accurate as +//! possible. The offsetDirection can be either +4-ppm or -2-ppm, and the +//! offsetValue should be from 1-63 and is multiplied by the direction setting +//! (i.e. +4-ppm * 8 (offsetValue) = +32-ppm). Please note, when measuring the +//! frequency after setting the calibration, you will only see a change on the +//! 1Hz frequency. +//! +//! \param baseAddress is the base address of the RTC_B module. +//! \param offsetDirection is the direction that the calibration offset will +//! go. +//! Valid values are: +//! - \b RTC_B_CALIBRATION_DOWN2PPM - calibrate at steps of -2 +//! - \b RTC_B_CALIBRATION_UP4PPM - calibrate at steps of +4 +//! \n Modified bits are \b RTCCALS of \b RTCCTL2 register. +//! \param offsetValue is the value that the offset will be a factor of; a +//! valid value is any integer from 1-63. +//! \n Modified bits are \b RTCCAL of \b RTCCTL2 register. +//! +//! \return None +// +//***************************************************************************** +extern void RTC_B_setCalibrationData(uint16_t baseAddress, + uint8_t offsetDirection, + uint8_t offsetValue); + +//***************************************************************************** +// +//! \brief Initializes the settings to operate the RTC in calendar mode +//! +//! This function initializes the Calendar mode of the RTC module. To prevent +//! potential erroneous alarm conditions from occurring, the alarm should be +//! disabled by clearing the RTCAIE, RTCAIFG and AE bits with APIs: +//! RTC_B_disableInterrupt(), RTC_B_clearInterrupt() and +//! RTC_B_configureCalendarAlarm() before calendar initialization. +//! +//! \param baseAddress is the base address of the RTC_B module. +//! \param CalendarTime is the pointer to the structure containing the values +//! for the Calendar to be initialized to. Valid values should be of +//! type pointer to Calendar and should contain the following members +//! and corresponding values: \b Seconds between 0-59 \b Minutes between +//! 0-59 \b Hours between 0-23 \b DayOfWeek between 0-6 \b DayOfMonth +//! between 1-31 \b Year between 0-4095 NOTE: Values beyond the ones +//! specified may result in erratic behavior. +//! \param formatSelect is the format for the Calendar registers to use. +//! Valid values are: +//! - \b RTC_B_FORMAT_BINARY [Default] +//! - \b RTC_B_FORMAT_BCD +//! \n Modified bits are \b RTCBCD of \b RTCCTL1 register. +//! +//! \return None +// +//***************************************************************************** +extern void RTC_B_initCalendar(uint16_t baseAddress, + Calendar *CalendarTime, + uint16_t formatSelect); + +//***************************************************************************** +// +//! \brief Returns the Calendar Time stored in the Calendar registers of the +//! RTC. +//! +//! This function returns the current Calendar time in the form of a Calendar +//! structure. The RTCRDY polling is used in this function to prevent reading +//! invalid time. +//! +//! \param baseAddress is the base address of the RTC_B module. +//! +//! \return A Calendar structure containing the current time. +// +//***************************************************************************** +extern Calendar RTC_B_getCalendarTime(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Sets and Enables the desired Calendar Alarm settings. +//! +//! This function sets a Calendar interrupt condition to assert the RTCAIFG +//! interrupt flag. The condition is a logical and of all of the parameters. +//! For example if the minutes and hours alarm is set, then the interrupt will +//! only assert when the minutes AND the hours change to the specified setting. +//! Use the RTC_B_ALARM_OFF for any alarm settings that should not be apart of +//! the alarm condition. +//! +//! \param baseAddress is the base address of the RTC_B module. +//! \param param is the pointer to struct for calendar alarm configuration. +//! +//! \return None +// +//***************************************************************************** +extern void RTC_B_configureCalendarAlarm(uint16_t baseAddress, + RTC_B_configureCalendarAlarmParam *param); + +//***************************************************************************** +// +//! \brief Sets a single specified Calendar interrupt condition +//! +//! This function sets a specified event to assert the RTCTEVIFG interrupt. +//! This interrupt is independent from the Calendar alarm interrupt. +//! +//! \param baseAddress is the base address of the RTC_B module. +//! \param eventSelect is the condition selected. +//! Valid values are: +//! - \b RTC_B_CALENDAREVENT_MINUTECHANGE - assert interrupt on every +//! minute +//! - \b RTC_B_CALENDAREVENT_HOURCHANGE - assert interrupt on every hour +//! - \b RTC_B_CALENDAREVENT_NOON - assert interrupt when hour is 12 +//! - \b RTC_B_CALENDAREVENT_MIDNIGHT - assert interrupt when hour is 0 +//! \n Modified bits are \b RTCTEV of \b RTCCTL register. +//! +//! \return None +// +//***************************************************************************** +extern void RTC_B_setCalendarEvent(uint16_t baseAddress, + uint16_t eventSelect); + +//***************************************************************************** +// +//! \brief Sets up an interrupt condition for the selected Prescaler. +//! +//! This function sets the condition for an interrupt to assert based on the +//! individual prescalers. +//! +//! \param baseAddress is the base address of the RTC_B module. +//! \param prescaleSelect is the prescaler to define an interrupt for. +//! Valid values are: +//! - \b RTC_B_PRESCALE_0 +//! - \b RTC_B_PRESCALE_1 +//! \param prescaleEventDivider is a divider to specify when an interrupt can +//! occur based on the clock source of the selected prescaler. (Does not +//! affect timer of the selected prescaler). +//! Valid values are: +//! - \b RTC_B_PSEVENTDIVIDER_2 [Default] +//! - \b RTC_B_PSEVENTDIVIDER_4 +//! - \b RTC_B_PSEVENTDIVIDER_8 +//! - \b RTC_B_PSEVENTDIVIDER_16 +//! - \b RTC_B_PSEVENTDIVIDER_32 +//! - \b RTC_B_PSEVENTDIVIDER_64 +//! - \b RTC_B_PSEVENTDIVIDER_128 +//! - \b RTC_B_PSEVENTDIVIDER_256 +//! \n Modified bits are \b RTxIP of \b RTCPSxCTL register. +//! +//! \return None +// +//***************************************************************************** +extern void RTC_B_definePrescaleEvent(uint16_t baseAddress, + uint8_t prescaleSelect, + uint8_t prescaleEventDivider); + +//***************************************************************************** +// +//! \brief Returns the selected prescaler value. +//! +//! This function returns the value of the selected prescale counter register. +//! Note that the counter value should be held by calling RTC_B_holdClock() +//! before calling this API. +//! +//! \param baseAddress is the base address of the RTC_B module. +//! \param prescaleSelect is the prescaler to obtain the value of. +//! Valid values are: +//! - \b RTC_B_PRESCALE_0 +//! - \b RTC_B_PRESCALE_1 +//! +//! \return The value of the specified prescaler count register +// +//***************************************************************************** +extern uint8_t RTC_B_getPrescaleValue(uint16_t baseAddress, + uint8_t prescaleSelect); + +//***************************************************************************** +// +//! \brief Sets the selected prescaler value. +//! +//! This function sets the prescale counter value. Before setting the prescale +//! counter, it should be held by calling RTC_B_holdClock(). +//! +//! \param baseAddress is the base address of the RTC_B module. +//! \param prescaleSelect is the prescaler to set the value for. +//! Valid values are: +//! - \b RTC_B_PRESCALE_0 +//! - \b RTC_B_PRESCALE_1 +//! \param prescaleCounterValue is the specified value to set the prescaler to. +//! Valid values are any integer between 0-255 +//! \n Modified bits are \b RTxPS of \b RTxPS register. +//! +//! \return None +// +//***************************************************************************** +extern void RTC_B_setPrescaleValue(uint16_t baseAddress, + uint8_t prescaleSelect, + uint8_t prescaleCounterValue); + +//***************************************************************************** +// +//! \brief Enables selected RTC interrupt sources. +//! +//! This function enables the selected RTC interrupt source. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. Does not clear interrupt flags. +//! +//! \param baseAddress is the base address of the RTC_B module. +//! \param interruptMask is a bit mask of the interrupts to enable. +//! Mask value is the logical OR of any of the following: +//! - \b RTC_B_TIME_EVENT_INTERRUPT - asserts when counter overflows in +//! counter mode or when Calendar event condition defined by +//! defineCalendarEvent() is met. +//! - \b RTC_B_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in +//! Calendar mode is met. +//! - \b RTC_B_CLOCK_READ_READY_INTERRUPT - asserts when Calendar +//! registers are settled. +//! - \b RTC_B_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0 +//! event condition is met. +//! - \b RTC_B_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1 +//! event condition is met. +//! - \b RTC_B_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a +//! problem with the 32kHz oscillator, while the RTC is running. +//! +//! \return None +// +//***************************************************************************** +extern void RTC_B_enableInterrupt(uint16_t baseAddress, + uint8_t interruptMask); + +//***************************************************************************** +// +//! \brief Disables selected RTC interrupt sources. +//! +//! This function disables the selected RTC interrupt source. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. +//! +//! \param baseAddress is the base address of the RTC_B module. +//! \param interruptMask is a bit mask of the interrupts to disable. +//! Mask value is the logical OR of any of the following: +//! - \b RTC_B_TIME_EVENT_INTERRUPT - asserts when counter overflows in +//! counter mode or when Calendar event condition defined by +//! defineCalendarEvent() is met. +//! - \b RTC_B_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in +//! Calendar mode is met. +//! - \b RTC_B_CLOCK_READ_READY_INTERRUPT - asserts when Calendar +//! registers are settled. +//! - \b RTC_B_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0 +//! event condition is met. +//! - \b RTC_B_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1 +//! event condition is met. +//! - \b RTC_B_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a +//! problem with the 32kHz oscillator, while the RTC is running. +//! +//! \return None +// +//***************************************************************************** +extern void RTC_B_disableInterrupt(uint16_t baseAddress, + uint8_t interruptMask); + +//***************************************************************************** +// +//! \brief Returns the status of the selected interrupts flags. +//! +//! This function returns the status of the interrupt flag for the selected +//! channel. +//! +//! \param baseAddress is the base address of the RTC_B module. +//! \param interruptFlagMask is a bit mask of the interrupt flags to return the +//! status of. +//! Mask value is the logical OR of any of the following: +//! - \b RTC_B_TIME_EVENT_INTERRUPT - asserts when counter overflows in +//! counter mode or when Calendar event condition defined by +//! defineCalendarEvent() is met. +//! - \b RTC_B_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in +//! Calendar mode is met. +//! - \b RTC_B_CLOCK_READ_READY_INTERRUPT - asserts when Calendar +//! registers are settled. +//! - \b RTC_B_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0 +//! event condition is met. +//! - \b RTC_B_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1 +//! event condition is met. +//! - \b RTC_B_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a +//! problem with the 32kHz oscillator, while the RTC is running. +//! +//! \return Logical OR of any of the following: +//! - \b RTC_B_TIME_EVENT_INTERRUPT asserts when counter overflows in +//! counter mode or when Calendar event condition defined by +//! defineCalendarEvent() is met. +//! - \b RTC_B_CLOCK_ALARM_INTERRUPT asserts when alarm condition in +//! Calendar mode is met. +//! - \b RTC_B_CLOCK_READ_READY_INTERRUPT asserts when Calendar +//! registers are settled. +//! - \b RTC_B_PRESCALE_TIMER0_INTERRUPT asserts when Prescaler 0 event +//! condition is met. +//! - \b RTC_B_PRESCALE_TIMER1_INTERRUPT asserts when Prescaler 1 event +//! condition is met. +//! - \b RTC_B_OSCILLATOR_FAULT_INTERRUPT asserts if there is a problem +//! with the 32kHz oscillator, while the RTC is running. +//! \n indicating the status of the masked interrupts +// +//***************************************************************************** +extern uint8_t RTC_B_getInterruptStatus(uint16_t baseAddress, + uint8_t interruptFlagMask); + +//***************************************************************************** +// +//! \brief Clears selected RTC interrupt flags. +//! +//! This function clears the RTC interrupt flag is cleared, so that it no +//! longer asserts. +//! +//! \param baseAddress is the base address of the RTC_B module. +//! \param interruptFlagMask is a bit mask of the interrupt flags to be +//! cleared. +//! Mask value is the logical OR of any of the following: +//! - \b RTC_B_TIME_EVENT_INTERRUPT - asserts when counter overflows in +//! counter mode or when Calendar event condition defined by +//! defineCalendarEvent() is met. +//! - \b RTC_B_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in +//! Calendar mode is met. +//! - \b RTC_B_CLOCK_READ_READY_INTERRUPT - asserts when Calendar +//! registers are settled. +//! - \b RTC_B_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0 +//! event condition is met. +//! - \b RTC_B_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1 +//! event condition is met. +//! - \b RTC_B_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a +//! problem with the 32kHz oscillator, while the RTC is running. +//! +//! \return None +// +//***************************************************************************** +extern void RTC_B_clearInterrupt(uint16_t baseAddress, + uint8_t interruptFlagMask); + +//***************************************************************************** +// +//! \brief Convert the given BCD value to binary format +//! +//! This function converts BCD values to binary format. This API uses the +//! hardware registers to perform the conversion rather than a software method. +//! +//! \param baseAddress is the base address of the RTC_B module. +//! \param valueToConvert is the raw value in BCD format to convert to Binary. +//! \n Modified bits are \b BCD2BIN of \b BCD2BIN register. +//! +//! \return The binary version of the input parameter +// +//***************************************************************************** +extern uint16_t RTC_B_convertBCDToBinary(uint16_t baseAddress, + uint16_t valueToConvert); + +//***************************************************************************** +// +//! \brief Convert the given binary value to BCD format +//! +//! This function converts binary values to BCD format. This API uses the +//! hardware registers to perform the conversion rather than a software method. +//! +//! \param baseAddress is the base address of the RTC_B module. +//! \param valueToConvert is the raw value in Binary format to convert to BCD. +//! \n Modified bits are \b BIN2BCD of \b BIN2BCD register. +//! +//! \return The BCD version of the valueToConvert parameter +// +//***************************************************************************** +extern uint16_t RTC_B_convertBinaryToBCD(uint16_t baseAddress, + uint16_t valueToConvert); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_RTC_B_H__ diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/rtc_c.c b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/rtc_c.c new file mode 100644 index 000000000..82ccb3cbe --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/rtc_c.c @@ -0,0 +1,403 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// rtc_c.c - Driver for the rtc_c Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup rtc_c_api rtc_c +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_RTC_C__ +#include "rtc_c.h" + +#include + +void RTC_C_startClock(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_RTCCTL0_H) = RTCKEY_H; + HWREG8(baseAddress + OFS_RTCCTL13_L) &= ~(RTCHOLD); + HWREG8(baseAddress + OFS_RTCCTL0_H) = 0x00; +} + +void RTC_C_holdClock(uint16_t baseAddress) +{ + HWREG8(baseAddress + OFS_RTCCTL0_H) = RTCKEY_H; + HWREG8(baseAddress + OFS_RTCCTL13_L) |= RTCHOLD; + HWREG8(baseAddress + OFS_RTCCTL0_H) = 0x00; +} + +void RTC_C_setCalibrationFrequency(uint16_t baseAddress, + uint16_t frequencySelect) +{ + HWREG8(baseAddress + OFS_RTCCTL0_H) = RTCKEY_H; + HWREG16(baseAddress + OFS_RTCCTL13) &= ~(RTCCALF_3); + HWREG16(baseAddress + OFS_RTCCTL13) |= frequencySelect; + HWREG8(baseAddress + OFS_RTCCTL0_H) = 0x00; +} + +void RTC_C_setCalibrationData(uint16_t baseAddress, + uint8_t offsetDirection, + uint8_t offsetValue) +{ + HWREG8(baseAddress + OFS_RTCCTL0_H) = RTCKEY_H; + HWREG16(baseAddress + OFS_RTCOCAL) = offsetValue + offsetDirection; + HWREG8(baseAddress + OFS_RTCCTL0_H) = 0x00; +} + +void RTC_C_initCounter(uint16_t baseAddress, + uint16_t clockSelect, + uint16_t counterSizeSelect) +{ + HWREG8(baseAddress + OFS_RTCCTL13) |= RTCHOLD; + HWREG8(baseAddress + OFS_RTCCTL13) &= ~(RTCMODE); + + HWREG16(baseAddress + OFS_RTCCTL13) &= ~(RTCSSEL_3 | RTCTEV_3); + HWREG16(baseAddress + OFS_RTCCTL13) |= clockSelect + counterSizeSelect; +} + +bool RTC_C_setTemperatureCompensation(uint16_t baseAddress, + uint16_t offsetDirection, + uint8_t offsetValue) +{ + while(!(HWREG8(baseAddress + OFS_RTCTCMP_H) & RTCTCRDY_H)) + { + ; + } + + HWREG16(baseAddress + OFS_RTCTCMP) = offsetValue + offsetDirection; + + if(HWREG8(baseAddress + OFS_RTCTCMP_H) & RTCTCOK_H) + { + return(STATUS_SUCCESS); + } + else + { + return(STATUS_FAIL); + } +} + +void RTC_C_initCalendar(uint16_t baseAddress, + Calendar *CalendarTime, + uint16_t formatSelect) +{ + HWREG8(baseAddress + OFS_RTCCTL0_H) = RTCKEY_H; + + HWREG8(baseAddress + OFS_RTCCTL13_L) |= RTCHOLD; + + HWREG16(baseAddress + OFS_RTCCTL13_L) &= ~(RTCBCD); + HWREG16(baseAddress + OFS_RTCCTL13_L) |= formatSelect; + + HWREG8(baseAddress + OFS_RTCTIM0_L) = CalendarTime->Seconds; + HWREG8(baseAddress + OFS_RTCTIM0_H) = CalendarTime->Minutes; + HWREG8(baseAddress + OFS_RTCTIM1_L) = CalendarTime->Hours; + HWREG8(baseAddress + OFS_RTCTIM1_H) = CalendarTime->DayOfWeek; + HWREG8(baseAddress + OFS_RTCDATE_L) = CalendarTime->DayOfMonth; + HWREG8(baseAddress + OFS_RTCDATE_H) = CalendarTime->Month; + HWREG16(baseAddress + OFS_RTCYEAR) = CalendarTime->Year; + + HWREG8(baseAddress + OFS_RTCCTL0_H) = 0x00; +} + +Calendar RTC_C_getCalendarTime(uint16_t baseAddress) +{ + Calendar tempCal; + + while(!(HWREG8(baseAddress + OFS_RTCCTL13_L) & RTCRDY)) + { + ; + } + + tempCal.Seconds = HWREG8(baseAddress + OFS_RTCTIM0_L); + tempCal.Minutes = HWREG8(baseAddress + OFS_RTCTIM0_H); + tempCal.Hours = HWREG8(baseAddress + OFS_RTCTIM1_L); + tempCal.DayOfWeek = HWREG8(baseAddress + OFS_RTCTIM1_H); + tempCal.DayOfMonth = HWREG8(baseAddress + OFS_RTCDATE_L); + tempCal.Month = HWREG8(baseAddress + OFS_RTCDATE_H); + tempCal.Year = HWREG16(baseAddress + OFS_RTCYEAR); + + return (tempCal); +} + +void RTC_C_configureCalendarAlarm(uint16_t baseAddress, + RTC_C_configureCalendarAlarmParam *param) +{ + //Each of these is XORed with 0x80 to turn on if an integer is passed, + //or turn OFF if RTC_C_ALARM_OFF (0x80) is passed. + HWREG8(baseAddress + OFS_RTCAMINHR_L) = (param->minutesAlarm ^ 0x80); + HWREG8(baseAddress + OFS_RTCAMINHR_H) = (param->hoursAlarm ^ 0x80); + HWREG8(baseAddress + OFS_RTCADOWDAY_L) = (param->dayOfWeekAlarm ^ 0x80); + HWREG8(baseAddress + OFS_RTCADOWDAY_H) = (param->dayOfMonthAlarm ^ 0x80); +} + +void RTC_C_setCalendarEvent(uint16_t baseAddress, + uint16_t eventSelect) +{ + HWREG8(baseAddress + OFS_RTCCTL0_H) = RTCKEY_H; + HWREG8(baseAddress + OFS_RTCCTL13_L) &= ~(RTCTEV_3); //Reset bits + HWREG8(baseAddress + OFS_RTCCTL13_L) |= eventSelect; + HWREG8(baseAddress + OFS_RTCCTL0_H) = 0x00; +} + +uint32_t RTC_C_getCounterValue(uint16_t baseAddress) +{ + if((HWREG8(baseAddress + OFS_RTCCTL13) & RTCHOLD) + || (HWREG8(baseAddress + OFS_RTCPS1CTL) & RT1PSHOLD)) + { + return (0); + } + + uint32_t counterValue_L = HWREG16(baseAddress + OFS_RTCTIM0); + uint32_t counterValue_H = HWREG16(baseAddress + OFS_RTCTIM1); + return ((counterValue_H << 16) + counterValue_L); +} + +void RTC_C_setCounterValue(uint16_t baseAddress, + uint32_t counterValue) +{ + uint16_t mode = HWREG16(baseAddress + OFS_RTCCTL13) & RTCTEV_3; + + if(mode == RTC_C_COUNTERSIZE_8BIT && counterValue > 0xF) + { + counterValue = 0xF; + } + else if(mode == RTC_C_COUNTERSIZE_16BIT && counterValue > 0xFF) + { + counterValue = 0xFF; + } + else if(mode == RTC_C_COUNTERSIZE_24BIT && counterValue > 0xFFFFFF) + { + counterValue = 0xFFFFFF; + } + + HWREG16(baseAddress + OFS_RTCTIM0) = counterValue; + HWREG16(baseAddress + OFS_RTCTIM1) = (counterValue >> 16); +} + +void RTC_C_initCounterPrescale(uint16_t baseAddress, + uint8_t prescaleSelect, + uint16_t prescaleClockSelect, + uint16_t prescaleDivider) +{ + //Reset bits and set clock select + HWREG16(baseAddress + OFS_RTCPS0CTL + prescaleSelect) = + prescaleClockSelect + prescaleDivider; +} + +void RTC_C_holdCounterPrescale(uint16_t baseAddress, + uint8_t prescaleSelect) +{ + HWREG8(baseAddress + OFS_RTCPS0CTL_H + prescaleSelect) |= RT0PSHOLD_H; +} + +void RTC_C_startCounterPrescale(uint16_t baseAddress, + uint8_t prescaleSelect) +{ + HWREG8(baseAddress + OFS_RTCPS0CTL_H + prescaleSelect) &= ~(RT0PSHOLD_H); +} + +void RTC_C_definePrescaleEvent(uint16_t baseAddress, + uint8_t prescaleSelect, + uint8_t prescaleEventDivider) +{ + HWREG8(baseAddress + OFS_RTCPS0CTL_L + prescaleSelect) &= ~(RT0IP_7); + HWREG8(baseAddress + OFS_RTCPS0CTL_L + + prescaleSelect) |= prescaleEventDivider; +} + +uint8_t RTC_C_getPrescaleValue(uint16_t baseAddress, + uint8_t prescaleSelect) +{ + if(RTC_C_PRESCALE_0 == prescaleSelect) + { + return (HWREG8(baseAddress + OFS_RTCPS_L)); + } + else if(RTC_C_PRESCALE_1 == prescaleSelect) + { + return (HWREG8(baseAddress + OFS_RTCPS_H)); + } + else + { + return (0); + } +} + +void RTC_C_setPrescaleValue(uint16_t baseAddress, + uint8_t prescaleSelect, + uint8_t prescaleCounterValue) +{ + HWREG8(baseAddress + OFS_RTCCTL0_H) = RTCKEY_H; + if(RTC_C_PRESCALE_0 == prescaleSelect) + { + HWREG8(baseAddress + OFS_RTCPS_L) = prescaleCounterValue; + } + else if(RTC_C_PRESCALE_1 == prescaleSelect) + { + HWREG8(baseAddress + OFS_RTCPS_H) = prescaleCounterValue; + } + HWREG8(baseAddress + OFS_RTCCTL0_H) = 0x00; +} + +void RTC_C_enableInterrupt(uint16_t baseAddress, + uint8_t interruptMask) +{ + if(interruptMask & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE)) + { + HWREG8(baseAddress + OFS_RTCCTL0_H) = RTCKEY_H; + HWREG8(baseAddress + OFS_RTCCTL0_L) |= + (interruptMask & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE)); + HWREG8(baseAddress + OFS_RTCCTL0_H) = 0x00; + } + + if(interruptMask & RTC_C_PRESCALE_TIMER0_INTERRUPT) + { + HWREG8(baseAddress + OFS_RTCPS0CTL_L) |= RT0PSIE; + } + + if(interruptMask & RTC_C_PRESCALE_TIMER1_INTERRUPT) + { + HWREG8(baseAddress + OFS_RTCPS1CTL_L) |= RT1PSIE; + } +} + +void RTC_C_disableInterrupt(uint16_t baseAddress, + uint8_t interruptMask) +{ + if(interruptMask & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE)) + { + HWREG8(baseAddress + OFS_RTCCTL0_H) = RTCKEY_H; + HWREG8(baseAddress + OFS_RTCCTL0_L) &= + ~(interruptMask & (RTCOFIE + RTCTEVIE + RTCAIE + RTCRDYIE)); + HWREG8(baseAddress + OFS_RTCCTL0_H) = 0x00; + } + + if(interruptMask & RTC_C_PRESCALE_TIMER0_INTERRUPT) + { + HWREG8(baseAddress + OFS_RTCPS0CTL_L) &= ~(RT0PSIE); + } + + if(interruptMask & RTC_C_PRESCALE_TIMER1_INTERRUPT) + { + HWREG8(baseAddress + OFS_RTCPS1CTL_L) &= ~(RT1PSIE); + } +} + +uint8_t RTC_C_getInterruptStatus(uint16_t baseAddress, + uint8_t interruptFlagMask) +{ + uint8_t tempInterruptFlagMask = 0x0000; + + tempInterruptFlagMask |= (HWREG8(baseAddress + OFS_RTCCTL0_L) + & ((interruptFlagMask >> 4) + & (RTCOFIFG + + RTCTEVIFG + + RTCAIFG + + RTCRDYIFG))); + + tempInterruptFlagMask = tempInterruptFlagMask << 4; + + if(interruptFlagMask & RTC_C_PRESCALE_TIMER0_INTERRUPT) + { + if(HWREG8(baseAddress + OFS_RTCPS0CTL_L) & RT0PSIFG) + { + tempInterruptFlagMask |= RTC_C_PRESCALE_TIMER0_INTERRUPT; + } + } + + if(interruptFlagMask & RTC_C_PRESCALE_TIMER1_INTERRUPT) + { + if(HWREG8(baseAddress + OFS_RTCPS1CTL_L) & RT1PSIFG) + { + tempInterruptFlagMask |= RTC_C_PRESCALE_TIMER1_INTERRUPT; + } + } + + return (tempInterruptFlagMask); +} + +void RTC_C_clearInterrupt(uint16_t baseAddress, + uint8_t interruptFlagMask) +{ + if(interruptFlagMask & (RTC_C_TIME_EVENT_INTERRUPT + + RTC_C_CLOCK_ALARM_INTERRUPT + + RTC_C_CLOCK_READ_READY_INTERRUPT + + RTC_C_OSCILLATOR_FAULT_INTERRUPT)) + { + HWREG8(baseAddress + OFS_RTCCTL0_H) = RTCKEY_H; + HWREG8(baseAddress + OFS_RTCCTL0_L) &= + ~((interruptFlagMask >> 4) & (RTCOFIFG + + RTCTEVIFG + + RTCAIFG + + RTCRDYIFG)); + HWREG8(baseAddress + OFS_RTCCTL0_H) = 0x00; + } + + if(interruptFlagMask & RTC_C_PRESCALE_TIMER0_INTERRUPT) + { + HWREG8(baseAddress + OFS_RTCPS0CTL_L) &= ~(RT0PSIFG); + } + + if(interruptFlagMask & RTC_C_PRESCALE_TIMER1_INTERRUPT) + { + HWREG8(baseAddress + OFS_RTCPS1CTL_L) &= ~(RT1PSIFG); + } +} + +uint16_t RTC_C_convertBCDToBinary(uint16_t baseAddress, + uint16_t valueToConvert) +{ + HWREG16(baseAddress + OFS_BCD2BIN) = valueToConvert; + return (HWREG16(baseAddress + OFS_BCD2BIN)); +} + +uint16_t RTC_C_convertBinaryToBCD(uint16_t baseAddress, + uint16_t valueToConvert) +{ + HWREG16(baseAddress + OFS_BIN2BCD) = valueToConvert; + return (HWREG16(baseAddress + OFS_BIN2BCD)); +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for rtc_c_api +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/rtc_c.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/rtc_c.h new file mode 100644 index 000000000..c7a240531 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/rtc_c.h @@ -0,0 +1,856 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// rtc_c.h - Driver for the RTC_C Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_RTC_C_H__ +#define __MSP430WARE_RTC_C_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_RTC_C__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "inc/hw_regaccess.h" +//***************************************************************************** +// +//! \brief Used in the RTC_C_initCalendar() function as the CalendarTime +//! parameter. +// +//***************************************************************************** +typedef struct Calendar +{ + //! Seconds of minute between 0-59 + uint8_t Seconds; + //! Minutes of hour between 0-59 + uint8_t Minutes; + //! Hour of day between 0-23 + uint8_t Hours; + //! Day of week between 0-6 + uint8_t DayOfWeek; + //! Day of month between 1-31 + uint8_t DayOfMonth; + //! Month between 0-11 + uint8_t Month; + //! Year between 0-4095 + uint16_t Year; +} Calendar; + +//***************************************************************************** +// +//! \brief Used in the RTC_C_configureCalendarAlarm() function as the param +//! parameter. +// +//***************************************************************************** +typedef struct RTC_C_configureCalendarAlarmParam +{ + //! Is the alarm condition for the minutes. + //! \n Valid values are: + //! - \b RTC_C_ALARMCONDITION_OFF [Default] + uint8_t minutesAlarm; + //! Is the alarm condition for the hours. + //! \n Valid values are: + //! - \b RTC_C_ALARMCONDITION_OFF [Default] + uint8_t hoursAlarm; + //! Is the alarm condition for the day of week. + //! \n Valid values are: + //! - \b RTC_C_ALARMCONDITION_OFF [Default] + uint8_t dayOfWeekAlarm; + //! Is the alarm condition for the day of the month. + //! \n Valid values are: + //! - \b RTC_C_ALARMCONDITION_OFF [Default] + uint8_t dayOfMonthAlarm; +} RTC_C_configureCalendarAlarmParam; + +//***************************************************************************** +// +// The following are values that can be passed to the frequencySelect parameter +// for functions: RTC_C_setCalibrationFrequency(). +// +//***************************************************************************** +#define RTC_C_CALIBRATIONFREQ_OFF (RTCCALF_0) +#define RTC_C_CALIBRATIONFREQ_512HZ (RTCCALF_1) +#define RTC_C_CALIBRATIONFREQ_256HZ (RTCCALF_2) +#define RTC_C_CALIBRATIONFREQ_1HZ (RTCCALF_3) + +//***************************************************************************** +// +// The following are values that can be passed to the offsetDirection parameter +// for functions: RTC_C_setCalibrationData(). +// +//***************************************************************************** +#define RTC_C_CALIBRATION_DOWN1PPM (!(RTCCALS)) +#define RTC_C_CALIBRATION_UP1PPM (RTCCALS) + +//***************************************************************************** +// +// The following are values that can be passed to the offsetDirection parameter +// for functions: RTC_C_setTemperatureCompensation(). +// +//***************************************************************************** +#define RTC_C_COMPENSATION_DOWN1PPM (!(RTCTCMPS)) +#define RTC_C_COMPENSATION_UP1PPM (RTCTCMPS) + +//***************************************************************************** +// +// The following are values that can be passed to the clockSelect parameter for +// functions: RTC_C_initCounter(). +// +//***************************************************************************** +#define RTC_C_CLOCKSELECT_32KHZ_OSC (RTCSSEL_0) +#define RTC_C_CLOCKSELECT_RT1PS (RTCSSEL_2) + +//***************************************************************************** +// +// The following are values that can be passed to the counterSizeSelect +// parameter for functions: RTC_C_initCounter(). +// +//***************************************************************************** +#define RTC_C_COUNTERSIZE_8BIT (RTCTEV_0) +#define RTC_C_COUNTERSIZE_16BIT (RTCTEV_1) +#define RTC_C_COUNTERSIZE_24BIT (RTCTEV_2) +#define RTC_C_COUNTERSIZE_32BIT (RTCTEV_3) + +//***************************************************************************** +// +// The following are values that can be passed to the formatSelect parameter +// for functions: RTC_C_initCalendar(). +// +//***************************************************************************** +#define RTC_C_FORMAT_BINARY (!(RTCBCD)) +#define RTC_C_FORMAT_BCD (RTCBCD) + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: RTC_C_configureCalendarAlarm(), RTC_C_configureCalendarAlarm(), +// RTC_C_configureCalendarAlarm(), and RTC_C_configureCalendarAlarm(). +// +//***************************************************************************** +#define RTC_C_ALARMCONDITION_OFF (0x80) + +//***************************************************************************** +// +// The following are values that can be passed to the eventSelect parameter for +// functions: RTC_C_setCalendarEvent(). +// +//***************************************************************************** +#define RTC_C_CALENDAREVENT_MINUTECHANGE (RTCTEV_0) +#define RTC_C_CALENDAREVENT_HOURCHANGE (RTCTEV_1) +#define RTC_C_CALENDAREVENT_NOON (RTCTEV_2) +#define RTC_C_CALENDAREVENT_MIDNIGHT (RTCTEV_3) + +//***************************************************************************** +// +// The following are values that can be passed to the prescaleDivider parameter +// for functions: RTC_C_initCounterPrescale(). +// +//***************************************************************************** +#define RTC_C_PSDIVIDER_2 (RT0PSDIV_0) +#define RTC_C_PSDIVIDER_4 (RT0PSDIV_1) +#define RTC_C_PSDIVIDER_8 (RT0PSDIV_2) +#define RTC_C_PSDIVIDER_16 (RT0PSDIV_3) +#define RTC_C_PSDIVIDER_32 (RT0PSDIV_4) +#define RTC_C_PSDIVIDER_64 (RT0PSDIV_5) +#define RTC_C_PSDIVIDER_128 (RT0PSDIV_6) +#define RTC_C_PSDIVIDER_256 (RT0PSDIV_7) + +//***************************************************************************** +// +// The following are values that can be passed to the prescaleClockSelect +// parameter for functions: RTC_C_initCounterPrescale(). +// +//***************************************************************************** +#define RTC_C_PSCLOCKSELECT_ACLK (RT1SSEL_0) +#define RTC_C_PSCLOCKSELECT_SMCLK (RT1SSEL_1) +#define RTC_C_PSCLOCKSELECT_RT0PS (RT1SSEL_2) + +//***************************************************************************** +// +// The following are values that can be passed to the prescaleEventDivider +// parameter for functions: RTC_C_definePrescaleEvent(). +// +//***************************************************************************** +#define RTC_C_PSEVENTDIVIDER_2 (RT0IP_0) +#define RTC_C_PSEVENTDIVIDER_4 (RT0IP_1) +#define RTC_C_PSEVENTDIVIDER_8 (RT0IP_2) +#define RTC_C_PSEVENTDIVIDER_16 (RT0IP_3) +#define RTC_C_PSEVENTDIVIDER_32 (RT0IP_4) +#define RTC_C_PSEVENTDIVIDER_64 (RT0IP_5) +#define RTC_C_PSEVENTDIVIDER_128 (RT0IP_6) +#define RTC_C_PSEVENTDIVIDER_256 (RT0IP_7) + +//***************************************************************************** +// +// The following are values that can be passed to the prescaleSelect parameter +// for functions: RTC_C_initCounterPrescale(), RTC_C_holdCounterPrescale(), +// RTC_C_startCounterPrescale(), RTC_C_definePrescaleEvent(), +// RTC_C_getPrescaleValue(), and RTC_C_setPrescaleValue(). +// +//***************************************************************************** +#define RTC_C_PRESCALE_0 (0x0) +#define RTC_C_PRESCALE_1 (0x2) + +//***************************************************************************** +// +// The following are values that can be passed to the interruptMask parameter +// for functions: RTC_C_enableInterrupt(), and RTC_C_disableInterrupt(); the +// interruptFlagMask parameter for functions: RTC_C_getInterruptStatus(), and +// RTC_C_clearInterrupt() as well as returned by the RTC_C_getInterruptStatus() +// function. +// +//***************************************************************************** +#define RTC_C_TIME_EVENT_INTERRUPT RTCTEVIE +#define RTC_C_CLOCK_ALARM_INTERRUPT RTCAIE +#define RTC_C_CLOCK_READ_READY_INTERRUPT RTCRDYIE +#define RTC_C_PRESCALE_TIMER0_INTERRUPT 0x02 +#define RTC_C_PRESCALE_TIMER1_INTERRUPT 0x01 +#define RTC_C_OSCILLATOR_FAULT_INTERRUPT RTCOFIE + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Starts the RTC. +//! +//! This function clears the RTC main hold bit to allow the RTC to function. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! +//! \return None +// +//***************************************************************************** +extern void RTC_C_startClock(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Holds the RTC. +//! +//! This function sets the RTC main hold bit to disable RTC functionality. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! +//! \return None +// +//***************************************************************************** +extern void RTC_C_holdClock(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Allows and Sets the frequency output to RTCCLK pin for calibration +//! measurement. +//! +//! This function sets a frequency to measure at the RTCCLK output pin. After +//! testing the set frequency, the calibration could be set accordingly. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param frequencySelect is the frequency output to RTCCLK. +//! Valid values are: +//! - \b RTC_C_CALIBRATIONFREQ_OFF [Default] - turn off calibration +//! output +//! - \b RTC_C_CALIBRATIONFREQ_512HZ - output signal at 512Hz for +//! calibration +//! - \b RTC_C_CALIBRATIONFREQ_256HZ - output signal at 256Hz for +//! calibration +//! - \b RTC_C_CALIBRATIONFREQ_1HZ - output signal at 1Hz for +//! calibration +//! \n Modified bits are \b RTCCALF of \b RTCCTL3 register. +//! +//! \return None +// +//***************************************************************************** +extern void RTC_C_setCalibrationFrequency(uint16_t baseAddress, + uint16_t frequencySelect); + +//***************************************************************************** +// +//! \brief Sets the specified calibration for the RTC. +//! +//! This function sets the calibration offset to make the RTC as accurate as +//! possible. The offsetDirection can be either +4-ppm or -2-ppm, and the +//! offsetValue should be from 1-63 and is multiplied by the direction setting +//! (i.e. +4-ppm * 8 (offsetValue) = +32-ppm). +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param offsetDirection is the direction that the calibration offset will +//! go. +//! Valid values are: +//! - \b RTC_C_CALIBRATION_DOWN1PPM - calibrate at steps of -1 +//! - \b RTC_C_CALIBRATION_UP1PPM - calibrate at steps of +1 +//! \n Modified bits are \b RTC0CALS of \b RTC0CAL register. +//! \param offsetValue is the value that the offset will be a factor of; a +//! valid value is any integer from 1-240. +//! \n Modified bits are \b RTC0CALx of \b RTC0CAL register. +//! +//! \return None +// +//***************************************************************************** +extern void RTC_C_setCalibrationData(uint16_t baseAddress, + uint8_t offsetDirection, + uint8_t offsetValue); + +//***************************************************************************** +// +//! \brief Initializes the settings to operate the RTC in Counter mode. +//! +//! This function initializes the Counter mode of the RTC_C. Setting the clock +//! source and counter size will allow an interrupt from the RTCTEVIFG once an +//! overflow to the counter register occurs. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param clockSelect is the selected clock for the counter mode to use. +//! Valid values are: +//! - \b RTC_C_CLOCKSELECT_32KHZ_OSC +//! - \b RTC_C_CLOCKSELECT_RT1PS +//! \n Modified bits are \b RTCSSEL of \b RTCCTL1 register. +//! \param counterSizeSelect is the size of the counter. +//! Valid values are: +//! - \b RTC_C_COUNTERSIZE_8BIT [Default] +//! - \b RTC_C_COUNTERSIZE_16BIT +//! - \b RTC_C_COUNTERSIZE_24BIT +//! - \b RTC_C_COUNTERSIZE_32BIT +//! \n Modified bits are \b RTCTEV of \b RTCCTL1 register. +//! +//! \return None +// +//***************************************************************************** +extern void RTC_C_initCounter(uint16_t baseAddress, + uint16_t clockSelect, + uint16_t counterSizeSelect); + +//***************************************************************************** +// +//! \brief Sets the specified temperature compensation for the RTC. +//! +//! This function sets the calibration offset to make the RTC as accurate as +//! possible. The offsetDirection can be either +1-ppm or -1-ppm, and the +//! offsetValue should be from 1-240 and is multiplied by the direction setting +//! (i.e. +1-ppm * 8 (offsetValue) = +8-ppm). +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param offsetDirection is the direction that the calibration offset wil go +//! Valid values are: +//! - \b RTC_C_COMPENSATION_DOWN1PPM +//! - \b RTC_C_COMPENSATION_UP1PPM +//! \n Modified bits are \b RTCTCMPS of \b RTCTCMP register. +//! \param offsetValue is the value that the offset will be a factor of; a +//! valid value is any integer from 1-240. +//! \n Modified bits are \b RTCTCMPx of \b RTCTCMP register. +//! +//! \return STATUS_SUCCESS or STATUS_FAILURE of setting the temperature +//! compensation +// +//***************************************************************************** +extern bool RTC_C_setTemperatureCompensation(uint16_t baseAddress, + uint16_t offsetDirection, + uint8_t offsetValue); + +//***************************************************************************** +// +//! \brief Initializes the settings to operate the RTC in calendar mode +//! +//! This function initializes the Calendar mode of the RTC module. To prevent +//! potential erroneous alarm conditions from occurring, the alarm should be +//! disabled by clearing the RTCAIE, RTCAIFG and AE bits with APIs: +//! RTC_C_disableInterrupt(), RTC_C_clearInterrupt() and +//! RTC_C_configureCalendarAlarm() before calendar initialization. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param CalendarTime is the pointer to the structure containing the values +//! for the Calendar to be initialized to. Valid values should be of +//! type pointer to Calendar and should contain the following members +//! and corresponding values: \b Seconds between 0-59 \b Minutes between +//! 0-59 \b Hours between 0-23 \b DayOfWeek between 0-6 \b DayOfMonth +//! between 1-31 \b Year between 0-4095 NOTE: Values beyond the ones +//! specified may result in erratic behavior. +//! \param formatSelect is the format for the Calendar registers to use. +//! Valid values are: +//! - \b RTC_C_FORMAT_BINARY [Default] +//! - \b RTC_C_FORMAT_BCD +//! \n Modified bits are \b RTCBCD of \b RTCCTL1 register. +//! +//! \return None +// +//***************************************************************************** +extern void RTC_C_initCalendar(uint16_t baseAddress, + Calendar *CalendarTime, + uint16_t formatSelect); + +//***************************************************************************** +// +//! \brief Returns the Calendar Time stored in the Calendar registers of the +//! RTC. +//! +//! This function returns the current Calendar time in the form of a Calendar +//! structure. The RTCRDY polling is used in this function to prevent reading +//! invalid time. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! +//! \return A Calendar structure containing the current time. +// +//***************************************************************************** +extern Calendar RTC_C_getCalendarTime(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Sets and Enables the desired Calendar Alarm settings. +//! +//! This function sets a Calendar interrupt condition to assert the RTCAIFG +//! interrupt flag. The condition is a logical and of all of the parameters. +//! For example if the minutes and hours alarm is set, then the interrupt will +//! only assert when the minutes AND the hours change to the specified setting. +//! Use the RTC_C_ALARM_OFF for any alarm settings that should not be apart of +//! the alarm condition. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param param is the pointer to struct for calendar alarm configuration. +//! +//! \return None +// +//***************************************************************************** +extern void RTC_C_configureCalendarAlarm(uint16_t baseAddress, + RTC_C_configureCalendarAlarmParam *param); + +//***************************************************************************** +// +//! \brief Sets a single specified Calendar interrupt condition +//! +//! This function sets a specified event to assert the RTCTEVIFG interrupt. +//! This interrupt is independent from the Calendar alarm interrupt. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param eventSelect is the condition selected. +//! Valid values are: +//! - \b RTC_C_CALENDAREVENT_MINUTECHANGE - assert interrupt on every +//! minute +//! - \b RTC_C_CALENDAREVENT_HOURCHANGE - assert interrupt on every hour +//! - \b RTC_C_CALENDAREVENT_NOON - assert interrupt when hour is 12 +//! - \b RTC_C_CALENDAREVENT_MIDNIGHT - assert interrupt when hour is 0 +//! \n Modified bits are \b RTCTEV of \b RTCCTL register. +//! +//! \return None +// +//***************************************************************************** +extern void RTC_C_setCalendarEvent(uint16_t baseAddress, + uint16_t eventSelect); + +//***************************************************************************** +// +//! \brief Returns the value of the Counter register. +//! +//! This function returns the value of the counter register for the RTC_C +//! module. It will return the 32-bit value no matter the size set during +//! initialization. The RTC should be held before trying to use this function. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! +//! \return The raw value of the full 32-bit Counter Register. +// +//***************************************************************************** +extern uint32_t RTC_C_getCounterValue(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Sets the value of the Counter register +//! +//! This function sets the counter register of the RTC_C module. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param counterValue is the value to set the Counter register to; a valid +//! value may be any 32-bit integer. +//! +//! \return None +// +//***************************************************************************** +extern void RTC_C_setCounterValue(uint16_t baseAddress, + uint32_t counterValue); + +//***************************************************************************** +// +//! \brief Initializes the Prescaler for Counter mode. +//! +//! This function initializes the selected prescaler for the counter mode in +//! the RTC_C module. If the RTC is initialized in Calendar mode, then these +//! are automatically initialized. The Prescalers can be used to divide a clock +//! source additionally before it gets to the main RTC clock. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param prescaleSelect is the prescaler to initialize. +//! Valid values are: +//! - \b RTC_C_PRESCALE_0 +//! - \b RTC_C_PRESCALE_1 +//! \param prescaleClockSelect is the clock to drive the selected prescaler. +//! Valid values are: +//! - \b RTC_C_PSCLOCKSELECT_ACLK +//! - \b RTC_C_PSCLOCKSELECT_SMCLK +//! - \b RTC_C_PSCLOCKSELECT_RT0PS - use Prescaler 0 as source to +//! Prescaler 1 (May only be used if prescaleSelect is +//! RTC_C_PRESCALE_1) +//! \n Modified bits are \b RTxSSEL of \b RTCPSxCTL register. +//! \param prescaleDivider is the divider for the selected clock source. +//! Valid values are: +//! - \b RTC_C_PSDIVIDER_2 [Default] +//! - \b RTC_C_PSDIVIDER_4 +//! - \b RTC_C_PSDIVIDER_8 +//! - \b RTC_C_PSDIVIDER_16 +//! - \b RTC_C_PSDIVIDER_32 +//! - \b RTC_C_PSDIVIDER_64 +//! - \b RTC_C_PSDIVIDER_128 +//! - \b RTC_C_PSDIVIDER_256 +//! \n Modified bits are \b RTxPSDIV of \b RTCPSxCTL register. +//! +//! \return None +// +//***************************************************************************** +extern void RTC_C_initCounterPrescale(uint16_t baseAddress, + uint8_t prescaleSelect, + uint16_t prescaleClockSelect, + uint16_t prescaleDivider); + +//***************************************************************************** +// +//! \brief Holds the selected Prescaler. +//! +//! This function holds the prescale counter from continuing. This will only +//! work in counter mode, in Calendar mode, the RTC_C_holdClock() must be used. +//! In counter mode, if using both prescalers in conjunction with the main RTC +//! counter, then stopping RT0PS will stop RT1PS, but stopping RT1PS will not +//! stop RT0PS. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param prescaleSelect is the prescaler to hold. +//! Valid values are: +//! - \b RTC_C_PRESCALE_0 +//! - \b RTC_C_PRESCALE_1 +//! +//! \return None +// +//***************************************************************************** +extern void RTC_C_holdCounterPrescale(uint16_t baseAddress, + uint8_t prescaleSelect); + +//***************************************************************************** +// +//! \brief Starts the selected Prescaler. +//! +//! This function starts the selected prescale counter. This function will only +//! work if the RTC is in counter mode. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param prescaleSelect is the prescaler to start. +//! Valid values are: +//! - \b RTC_C_PRESCALE_0 +//! - \b RTC_C_PRESCALE_1 +//! +//! \return None +// +//***************************************************************************** +extern void RTC_C_startCounterPrescale(uint16_t baseAddress, + uint8_t prescaleSelect); + +//***************************************************************************** +// +//! \brief Sets up an interrupt condition for the selected Prescaler. +//! +//! This function sets the condition for an interrupt to assert based on the +//! individual prescalers. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param prescaleSelect is the prescaler to define an interrupt for. +//! Valid values are: +//! - \b RTC_C_PRESCALE_0 +//! - \b RTC_C_PRESCALE_1 +//! \param prescaleEventDivider is a divider to specify when an interrupt can +//! occur based on the clock source of the selected prescaler. (Does not +//! affect timer of the selected prescaler). +//! Valid values are: +//! - \b RTC_C_PSEVENTDIVIDER_2 [Default] +//! - \b RTC_C_PSEVENTDIVIDER_4 +//! - \b RTC_C_PSEVENTDIVIDER_8 +//! - \b RTC_C_PSEVENTDIVIDER_16 +//! - \b RTC_C_PSEVENTDIVIDER_32 +//! - \b RTC_C_PSEVENTDIVIDER_64 +//! - \b RTC_C_PSEVENTDIVIDER_128 +//! - \b RTC_C_PSEVENTDIVIDER_256 +//! \n Modified bits are \b RTxIP of \b RTCPSxCTL register. +//! +//! \return None +// +//***************************************************************************** +extern void RTC_C_definePrescaleEvent(uint16_t baseAddress, + uint8_t prescaleSelect, + uint8_t prescaleEventDivider); + +//***************************************************************************** +// +//! \brief Returns the selected prescaler value. +//! +//! This function returns the value of the selected prescale counter register. +//! Note that the counter value should be held by calling RTC_C_holdClock() +//! before calling this API. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param prescaleSelect is the prescaler to obtain the value of. +//! Valid values are: +//! - \b RTC_C_PRESCALE_0 +//! - \b RTC_C_PRESCALE_1 +//! +//! \return The value of the specified prescaler count register +// +//***************************************************************************** +extern uint8_t RTC_C_getPrescaleValue(uint16_t baseAddress, + uint8_t prescaleSelect); + +//***************************************************************************** +// +//! \brief Sets the selected Prescaler value. +//! +//! This function sets the prescale counter value. Before setting the prescale +//! counter, it should be held by calling RTC_C_holdClock(). +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param prescaleSelect is the prescaler to set the value for. +//! Valid values are: +//! - \b RTC_C_PRESCALE_0 +//! - \b RTC_C_PRESCALE_1 +//! \param prescaleCounterValue is the specified value to set the prescaler to. +//! Valid values are any integer between 0-255 +//! \n Modified bits are \b RTxPS of \b RTxPS register. +//! +//! \return None +// +//***************************************************************************** +extern void RTC_C_setPrescaleValue(uint16_t baseAddress, + uint8_t prescaleSelect, + uint8_t prescaleCounterValue); + +//***************************************************************************** +// +//! \brief Enables selected RTC interrupt sources. +//! +//! This function enables the selected RTC interrupt source. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. Does not clear interrupt flags. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param interruptMask is a bit mask of the interrupts to enable. +//! Mask value is the logical OR of any of the following: +//! - \b RTC_C_TIME_EVENT_INTERRUPT - asserts when counter overflows in +//! counter mode or when Calendar event condition defined by +//! defineCalendarEvent() is met. +//! - \b RTC_C_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in +//! Calendar mode is met. +//! - \b RTC_C_CLOCK_READ_READY_INTERRUPT - asserts when Calendar +//! registers are settled. +//! - \b RTC_C_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0 +//! event condition is met. +//! - \b RTC_C_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1 +//! event condition is met. +//! - \b RTC_C_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a +//! problem with the 32kHz oscillator, while the RTC is running. +//! +//! \return None +// +//***************************************************************************** +extern void RTC_C_enableInterrupt(uint16_t baseAddress, + uint8_t interruptMask); + +//***************************************************************************** +// +//! \brief Disables selected RTC interrupt sources. +//! +//! This function disables the selected RTC interrupt source. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param interruptMask is a bit mask of the interrupts to disable. +//! Mask value is the logical OR of any of the following: +//! - \b RTC_C_TIME_EVENT_INTERRUPT - asserts when counter overflows in +//! counter mode or when Calendar event condition defined by +//! defineCalendarEvent() is met. +//! - \b RTC_C_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in +//! Calendar mode is met. +//! - \b RTC_C_CLOCK_READ_READY_INTERRUPT - asserts when Calendar +//! registers are settled. +//! - \b RTC_C_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0 +//! event condition is met. +//! - \b RTC_C_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1 +//! event condition is met. +//! - \b RTC_C_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a +//! problem with the 32kHz oscillator, while the RTC is running. +//! +//! \return None +// +//***************************************************************************** +extern void RTC_C_disableInterrupt(uint16_t baseAddress, + uint8_t interruptMask); + +//***************************************************************************** +// +//! \brief Returns the status of the selected interrupts flags. +//! +//! This function returns the status of the interrupt flag for the selected +//! channel. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param interruptFlagMask is a bit mask of the interrupt flags to return the +//! status of. +//! Mask value is the logical OR of any of the following: +//! - \b RTC_C_TIME_EVENT_INTERRUPT - asserts when counter overflows in +//! counter mode or when Calendar event condition defined by +//! defineCalendarEvent() is met. +//! - \b RTC_C_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in +//! Calendar mode is met. +//! - \b RTC_C_CLOCK_READ_READY_INTERRUPT - asserts when Calendar +//! registers are settled. +//! - \b RTC_C_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0 +//! event condition is met. +//! - \b RTC_C_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1 +//! event condition is met. +//! - \b RTC_C_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a +//! problem with the 32kHz oscillator, while the RTC is running. +//! +//! \return Logical OR of any of the following: +//! - \b RTC_C_TIME_EVENT_INTERRUPT asserts when counter overflows in +//! counter mode or when Calendar event condition defined by +//! defineCalendarEvent() is met. +//! - \b RTC_C_CLOCK_ALARM_INTERRUPT asserts when alarm condition in +//! Calendar mode is met. +//! - \b RTC_C_CLOCK_READ_READY_INTERRUPT asserts when Calendar +//! registers are settled. +//! - \b RTC_C_PRESCALE_TIMER0_INTERRUPT asserts when Prescaler 0 event +//! condition is met. +//! - \b RTC_C_PRESCALE_TIMER1_INTERRUPT asserts when Prescaler 1 event +//! condition is met. +//! - \b RTC_C_OSCILLATOR_FAULT_INTERRUPT asserts if there is a problem +//! with the 32kHz oscillator, while the RTC is running. +//! \n indicating the status of the masked interrupts +// +//***************************************************************************** +extern uint8_t RTC_C_getInterruptStatus(uint16_t baseAddress, + uint8_t interruptFlagMask); + +//***************************************************************************** +// +//! \brief Clears selected RTC interrupt flags. +//! +//! This function clears the RTC interrupt flag is cleared, so that it no +//! longer asserts. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param interruptFlagMask is a bit mask of the interrupt flags to be +//! cleared. +//! Mask value is the logical OR of any of the following: +//! - \b RTC_C_TIME_EVENT_INTERRUPT - asserts when counter overflows in +//! counter mode or when Calendar event condition defined by +//! defineCalendarEvent() is met. +//! - \b RTC_C_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in +//! Calendar mode is met. +//! - \b RTC_C_CLOCK_READ_READY_INTERRUPT - asserts when Calendar +//! registers are settled. +//! - \b RTC_C_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0 +//! event condition is met. +//! - \b RTC_C_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1 +//! event condition is met. +//! - \b RTC_C_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a +//! problem with the 32kHz oscillator, while the RTC is running. +//! +//! \return None +// +//***************************************************************************** +extern void RTC_C_clearInterrupt(uint16_t baseAddress, + uint8_t interruptFlagMask); + +//***************************************************************************** +// +//! \brief Convert the given BCD value to binary format +//! +//! This function converts BCD values to binary format. This API uses the +//! hardware registers to perform the conversion rather than a software method. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param valueToConvert is the raw value in BCD format to convert to Binary. +//! \n Modified bits are \b BCD2BIN of \b BCD2BIN register. +//! +//! \return The binary version of the input parameter +// +//***************************************************************************** +extern uint16_t RTC_C_convertBCDToBinary(uint16_t baseAddress, + uint16_t valueToConvert); + +//***************************************************************************** +// +//! \brief Convert the given binary value to BCD format +//! +//! This function converts binary values to BCD format. This API uses the +//! hardware registers to perform the conversion rather than a software method. +//! +//! \param baseAddress is the base address of the RTC_C module. +//! \param valueToConvert is the raw value in Binary format to convert to BCD. +//! \n Modified bits are \b BIN2BCD of \b BIN2BCD register. +//! +//! \return The BCD version of the valueToConvert parameter +// +//***************************************************************************** +extern uint16_t RTC_C_convertBinaryToBCD(uint16_t baseAddress, + uint16_t valueToConvert); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_RTC_C_H__ diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/sfr.c b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/sfr.c new file mode 100644 index 000000000..fe3580b67 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/sfr.c @@ -0,0 +1,97 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// sfr.c - Driver for the sfr Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup sfr_api sfr +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_SFR__ +#include "sfr.h" + +#include + +void SFR_enableInterrupt(uint8_t interruptMask) +{ + HWREG8(SFR_BASE + OFS_SFRIE1_L) |= interruptMask; +} + +void SFR_disableInterrupt(uint8_t interruptMask) +{ + HWREG8(SFR_BASE + OFS_SFRIE1_L) &= ~(interruptMask); +} + +uint8_t SFR_getInterruptStatus(uint8_t interruptFlagMask) +{ + return (HWREG8(SFR_BASE + OFS_SFRIFG1_L) & interruptFlagMask); +} + +void SFR_clearInterrupt(uint8_t interruptFlagMask) +{ + HWREG8(SFR_BASE + OFS_SFRIFG1_L) &= ~(interruptFlagMask); +} + +void SFR_setResetPinPullResistor(uint16_t pullResistorSetup) +{ + HWREG8(SFR_BASE + OFS_SFRRPCR_L) &= ~(SYSRSTRE + SYSRSTUP); + HWREG8(SFR_BASE + OFS_SFRRPCR_L) |= pullResistorSetup; +} + +void SFR_setNMIEdge(uint16_t edgeDirection) +{ + HWREG8(SFR_BASE + OFS_SFRRPCR_L) &= ~(SYSNMIIES); + HWREG8(SFR_BASE + OFS_SFRRPCR_L) |= edgeDirection; +} + +void SFR_setResetNMIPinFunction(uint8_t resetPinFunction) +{ + HWREG8(SFR_BASE + OFS_SFRRPCR_L) &= ~(SYSNMI); + HWREG8(SFR_BASE + OFS_SFRRPCR_L) |= resetPinFunction; +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for sfr_api +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/sfr.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/sfr.h new file mode 100644 index 000000000..5a6efcbd4 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/sfr.h @@ -0,0 +1,290 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// sfr.h - Driver for the SFR Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_SFR_H__ +#define __MSP430WARE_SFR_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_SFR__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the interruptMask parameter +// for functions: SFR_enableInterrupt(), and SFR_disableInterrupt(); the +// interruptFlagMask parameter for functions: SFR_getInterruptStatus(), and +// SFR_clearInterrupt() as well as returned by the SFR_getInterruptStatus() +// function. +// +//***************************************************************************** +#define SFR_JTAG_OUTBOX_INTERRUPT JMBOUTIE +#define SFR_JTAG_INBOX_INTERRUPT JMBINIE +#define SFR_NMI_PIN_INTERRUPT NMIIE +#define SFR_VACANT_MEMORY_ACCESS_INTERRUPT VMAIE +#define SFR_OSCILLATOR_FAULT_INTERRUPT OFIE +#define SFR_WATCHDOG_INTERVAL_TIMER_INTERRUPT WDTIE + +//***************************************************************************** +// +// The following are values that can be passed to the pullResistorSetup +// parameter for functions: SFR_setResetPinPullResistor(). +// +//***************************************************************************** +#define SFR_RESISTORDISABLE (!(SYSRSTRE + SYSRSTUP)) +#define SFR_RESISTORENABLE_PULLUP (SYSRSTRE + SYSRSTUP) +#define SFR_RESISTORENABLE_PULLDOWN (SYSRSTRE) + +//***************************************************************************** +// +// The following are values that can be passed to the edgeDirection parameter +// for functions: SFR_setNMIEdge(). +// +//***************************************************************************** +#define SFR_NMI_RISINGEDGE (!(SYSNMIIES)) +#define SFR_NMI_FALLINGEDGE (SYSNMIIES) + +//***************************************************************************** +// +// The following are values that can be passed to the resetPinFunction +// parameter for functions: SFR_setResetNMIPinFunction(). +// +//***************************************************************************** +#define SFR_RESETPINFUNC_RESET (!(SYSNMI)) +#define SFR_RESETPINFUNC_NMI (SYSNMI) + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Enables selected SFR interrupt sources. +//! +//! This function enables the selected SFR interrupt sources. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. Does not clear interrupt flags. +//! +//! \param interruptMask is the bit mask of interrupts that will be enabled. +//! Mask value is the logical OR of any of the following: +//! - \b SFR_JTAG_OUTBOX_INTERRUPT - JTAG outbox interrupt +//! - \b SFR_JTAG_INBOX_INTERRUPT - JTAG inbox interrupt +//! - \b SFR_NMI_PIN_INTERRUPT - NMI pin interrupt, if NMI function is +//! chosen +//! - \b SFR_VACANT_MEMORY_ACCESS_INTERRUPT - Vacant memory access +//! interrupt +//! - \b SFR_OSCILLATOR_FAULT_INTERRUPT - Oscillator fault interrupt +//! - \b SFR_WATCHDOG_INTERVAL_TIMER_INTERRUPT - Watchdog interval timer +//! interrupt +//! +//! \return None +// +//***************************************************************************** +extern void SFR_enableInterrupt(uint8_t interruptMask); + +//***************************************************************************** +// +//! \brief Disables selected SFR interrupt sources. +//! +//! This function disables the selected SFR interrupt sources. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. +//! +//! \param interruptMask is the bit mask of interrupts that will be disabled. +//! Mask value is the logical OR of any of the following: +//! - \b SFR_JTAG_OUTBOX_INTERRUPT - JTAG outbox interrupt +//! - \b SFR_JTAG_INBOX_INTERRUPT - JTAG inbox interrupt +//! - \b SFR_NMI_PIN_INTERRUPT - NMI pin interrupt, if NMI function is +//! chosen +//! - \b SFR_VACANT_MEMORY_ACCESS_INTERRUPT - Vacant memory access +//! interrupt +//! - \b SFR_OSCILLATOR_FAULT_INTERRUPT - Oscillator fault interrupt +//! - \b SFR_WATCHDOG_INTERVAL_TIMER_INTERRUPT - Watchdog interval timer +//! interrupt +//! +//! \return None +// +//***************************************************************************** +extern void SFR_disableInterrupt(uint8_t interruptMask); + +//***************************************************************************** +// +//! \brief Returns the status of the selected SFR interrupt flags. +//! +//! This function returns the status of the selected SFR interrupt flags in a +//! bit mask format matching that passed into the interruptFlagMask parameter. +//! +//! \param interruptFlagMask is the bit mask of interrupt flags that the status +//! of should be returned. +//! Mask value is the logical OR of any of the following: +//! - \b SFR_JTAG_OUTBOX_INTERRUPT - JTAG outbox interrupt +//! - \b SFR_JTAG_INBOX_INTERRUPT - JTAG inbox interrupt +//! - \b SFR_NMI_PIN_INTERRUPT - NMI pin interrupt, if NMI function is +//! chosen +//! - \b SFR_VACANT_MEMORY_ACCESS_INTERRUPT - Vacant memory access +//! interrupt +//! - \b SFR_OSCILLATOR_FAULT_INTERRUPT - Oscillator fault interrupt +//! - \b SFR_WATCHDOG_INTERVAL_TIMER_INTERRUPT - Watchdog interval timer +//! interrupt +//! +//! \return A bit mask of the status of the selected interrupt flags. +//! Return Logical OR of any of the following: +//! - \b SFR_JTAG_OUTBOX_INTERRUPT JTAG outbox interrupt +//! - \b SFR_JTAG_INBOX_INTERRUPT JTAG inbox interrupt +//! - \b SFR_NMI_PIN_INTERRUPT NMI pin interrupt, if NMI function is +//! chosen +//! - \b SFR_VACANT_MEMORY_ACCESS_INTERRUPT Vacant memory access +//! interrupt +//! - \b SFR_OSCILLATOR_FAULT_INTERRUPT Oscillator fault interrupt +//! - \b SFR_WATCHDOG_INTERVAL_TIMER_INTERRUPT Watchdog interval timer +//! interrupt +//! \n indicating the status of the masked interrupts +// +//***************************************************************************** +extern uint8_t SFR_getInterruptStatus(uint8_t interruptFlagMask); + +//***************************************************************************** +// +//! \brief Clears the selected SFR interrupt flags. +//! +//! This function clears the status of the selected SFR interrupt flags. +//! +//! \param interruptFlagMask is the bit mask of interrupt flags that will be +//! cleared. +//! Mask value is the logical OR of any of the following: +//! - \b SFR_JTAG_OUTBOX_INTERRUPT - JTAG outbox interrupt +//! - \b SFR_JTAG_INBOX_INTERRUPT - JTAG inbox interrupt +//! - \b SFR_NMI_PIN_INTERRUPT - NMI pin interrupt, if NMI function is +//! chosen +//! - \b SFR_VACANT_MEMORY_ACCESS_INTERRUPT - Vacant memory access +//! interrupt +//! - \b SFR_OSCILLATOR_FAULT_INTERRUPT - Oscillator fault interrupt +//! - \b SFR_WATCHDOG_INTERVAL_TIMER_INTERRUPT - Watchdog interval timer +//! interrupt +//! +//! \return None +// +//***************************************************************************** +extern void SFR_clearInterrupt(uint8_t interruptFlagMask); + +//***************************************************************************** +// +//! \brief Sets the pull-up/down resistor on the ~RST/NMI pin. +//! +//! This function sets the pull-up/down resistors on the ~RST/NMI pin to the +//! settings from the pullResistorSetup parameter. +//! +//! \param pullResistorSetup is the selection of how the pull-up/down resistor +//! on the ~RST/NMI pin should be setup or disabled. +//! Valid values are: +//! - \b SFR_RESISTORDISABLE +//! - \b SFR_RESISTORENABLE_PULLUP [Default] +//! - \b SFR_RESISTORENABLE_PULLDOWN +//! \n Modified bits are \b SYSRSTUP and \b SYSRSTRE of \b SFRRPCR +//! register. +//! +//! \return None +// +//***************************************************************************** +extern void SFR_setResetPinPullResistor(uint16_t pullResistorSetup); + +//***************************************************************************** +// +//! \brief Sets the edge direction that will assert an NMI from a signal on the +//! ~RST/NMI pin if NMI function is active. +//! +//! This function sets the edge direction that will assert an NMI from a signal +//! on the ~RST/NMI pin if the NMI function is active. To activate the NMI +//! function of the ~RST/NMI use the SFR_setResetNMIPinFunction() passing +//! SFR_RESETPINFUNC_NMI into the resetPinFunction parameter. +//! +//! \param edgeDirection is the direction that the signal on the ~RST/NMI pin +//! should go to signal an interrupt, if enabled. +//! Valid values are: +//! - \b SFR_NMI_RISINGEDGE [Default] +//! - \b SFR_NMI_FALLINGEDGE +//! \n Modified bits are \b SYSNMIIES of \b SFRRPCR register. +//! +//! \return None +// +//***************************************************************************** +extern void SFR_setNMIEdge(uint16_t edgeDirection); + +//***************************************************************************** +// +//! \brief Sets the function of the ~RST/NMI pin. +//! +//! This function sets the functionality of the ~RST/NMI pin, whether in reset +//! mode which will assert a reset if a low signal is observed on that pin, or +//! an NMI which will assert an interrupt from an edge of the signal dependent +//! on the setting of the edgeDirection parameter in SFR_setNMIEdge(). +//! +//! \param resetPinFunction is the function that the ~RST/NMI pin should take +//! on. +//! Valid values are: +//! - \b SFR_RESETPINFUNC_RESET [Default] +//! - \b SFR_RESETPINFUNC_NMI +//! \n Modified bits are \b SYSNMI of \b SFRRPCR register. +//! +//! \return None +// +//***************************************************************************** +extern void SFR_setResetNMIPinFunction(uint8_t resetPinFunction); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_SFR_H__ diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/sysctl.c b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/sysctl.c new file mode 100644 index 000000000..d52a4b1f0 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/sysctl.c @@ -0,0 +1,134 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// sysctl.c - Driver for the sysctl Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup sysctl_api sysctl +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_SYS__ +#include "sysctl.h" + +#include + +void SysCtl_enableDedicatedJTAGPins(void) +{ + HWREG8(SYS_BASE + OFS_SYSCTL_L) |= SYSJTAGPIN; +} + +uint8_t SysCtl_getBSLEntryIndication(void) +{ + if(HWREG8(SYS_BASE + OFS_SYSCTL_L) & SYSBSLIND) + { + return (SYSCTL_BSLENTRY_INDICATED); + } + else + { + return (SYSCTL_BSLENTRY_NOTINDICATED); + } +} + +void SysCtl_enablePMMAccessProtect(void) +{ + HWREG8(SYS_BASE + OFS_SYSCTL_L) |= SYSPMMPE; +} + +void SysCtl_enableRAMBasedInterruptVectors(void) +{ + HWREG8(SYS_BASE + OFS_SYSCTL_L) |= SYSRIVECT; +} + +void SysCtl_disableRAMBasedInterruptVectors(void) +{ + HWREG8(SYS_BASE + OFS_SYSCTL_L) &= ~(SYSRIVECT); +} + +void SysCtl_initJTAGMailbox(uint8_t mailboxSizeSelect, + uint8_t autoClearInboxFlagSelect) +{ + HWREG8(SYS_BASE + OFS_SYSJMBC_L) &= ~(JMBCLR1OFF + JMBCLR0OFF + JMBMODE); + HWREG8(SYS_BASE + OFS_SYSJMBC_L) |= + mailboxSizeSelect + autoClearInboxFlagSelect; +} + +uint8_t SysCtl_getJTAGMailboxFlagStatus(uint8_t mailboxFlagMask) +{ + return (HWREG8(SYS_BASE + OFS_SYSJMBC_L) & mailboxFlagMask); +} + +void SysCtl_clearJTAGMailboxFlagStatus(uint8_t mailboxFlagMask) +{ + HWREG8(SYS_BASE + OFS_SYSJMBC_L) &= ~(mailboxFlagMask); +} + +uint16_t SysCtl_getJTAGInboxMessage16Bit(uint8_t inboxSelect) +{ + return (HWREG16(SYS_BASE + OFS_SYSJMBI0 + inboxSelect)); +} + +uint32_t SysCtl_getJTAGInboxMessage32Bit(void) +{ + uint32_t JTAGInboxMessageLow = HWREG16(SYS_BASE + OFS_SYSJMBI0); + uint32_t JTAGInboxMessageHigh = HWREG16(SYS_BASE + OFS_SYSJMBI1); + + return ((JTAGInboxMessageHigh << 16) + JTAGInboxMessageLow); +} + +void SysCtl_setJTAGOutgoingMessage16Bit(uint8_t outboxSelect, + uint16_t outgoingMessage) +{ + HWREG16(SYS_BASE + OFS_SYSJMBO0 + outboxSelect) = outgoingMessage; +} + +void SysCtl_setJTAGOutgoingMessage32Bit(uint32_t outgoingMessage) +{ + HWREG16(SYS_BASE + OFS_SYSJMBO0) = (outgoingMessage); + HWREG16(SYS_BASE + OFS_SYSJMBO1) = (outgoingMessage >> 16); +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for sysctl_api +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/sysctl.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/sysctl.h new file mode 100644 index 000000000..7cb575274 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/sysctl.h @@ -0,0 +1,356 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// sysctl.h - Driver for the SYSCTL Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_SYSCTL_H__ +#define __MSP430WARE_SYSCTL_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_SYS__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the mailboxSizeSelect +// parameter for functions: SysCtl_initJTAGMailbox(). +// +//***************************************************************************** +#define SYSCTL_JTAGMBSIZE_16BIT (!(JMBMODE)) +#define SYSCTL_JTAGMBSIZE_32BIT (JMBMODE) + +//***************************************************************************** +// +// The following are values that can be passed to the autoClearInboxFlagSelect +// parameter for functions: SysCtl_initJTAGMailbox(). +// +//***************************************************************************** +#define SYSCTL_JTAGINBOX0AUTO_JTAGINBOX1AUTO (!(JMBCLR0OFF + JMBCLR1OFF)) +#define SYSCTL_JTAGINBOX0AUTO_JTAGINBOX1SW (JMBCLR1OFF) +#define SYSCTL_JTAGINBOX0SW_JTAGINBOX1AUTO (JMBCLR0OFF) +#define SYSCTL_JTAGINBOX0SW_JTAGINBOX1SW (JMBCLR0OFF + JMBCLR1OFF) + +//***************************************************************************** +// +// The following are values that can be passed to the mailboxFlagMask parameter +// for functions: SysCtl_getJTAGMailboxFlagStatus(), and +// SysCtl_clearJTAGMailboxFlagStatus(). +// +//***************************************************************************** +#define SYSCTL_JTAGOUTBOX_FLAG0 (JMBOUT0FG) +#define SYSCTL_JTAGOUTBOX_FLAG1 (JMBOUT1FG) +#define SYSCTL_JTAGINBOX_FLAG0 (JMBIN0FG) +#define SYSCTL_JTAGINBOX_FLAG1 (JMBIN1FG) + +//***************************************************************************** +// +// The following are values that can be passed to the inboxSelect parameter for +// functions: SysCtl_getJTAGInboxMessage16Bit(). +// +//***************************************************************************** +#define SYSCTL_JTAGINBOX_0 (0x0) +#define SYSCTL_JTAGINBOX_1 (0x2) + +//***************************************************************************** +// +// The following are values that can be passed to the outboxSelect parameter +// for functions: SysCtl_setJTAGOutgoingMessage16Bit(). +// +//***************************************************************************** +#define SYSCTL_JTAGOUTBOX_0 (0x0) +#define SYSCTL_JTAGOUTBOX_1 (0x2) + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the SysCtl_getBSLEntryIndication() function. +// +//***************************************************************************** +#define SYSCTL_BSLENTRY_INDICATED (0x1) +#define SYSCTL_BSLENTRY_NOTINDICATED (0x0) + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Sets the JTAG pins to be exclusively for JTAG until a BOR occurs. +//! +//! This function sets the JTAG pins to be exclusively used for the JTAG, and +//! not to be shared with the GPIO pins. This setting can only be cleared when +//! a BOR occurs. +//! +//! +//! \return None +// +//***************************************************************************** +extern void SysCtl_enableDedicatedJTAGPins(void); + +//***************************************************************************** +// +//! \brief Returns the indication of a BSL entry sequence from the Spy-Bi-Wire. +//! +//! This function returns the indication of a BSL entry sequence from the Spy- +//! Bi-Wire. +//! +//! +//! \return One of the following: +//! - \b SysCtl_BSLENTRY_INDICATED +//! - \b SysCtl_BSLENTRY_NOTINDICATED +//! \n indicating if a BSL entry sequence was detected +// +//***************************************************************************** +extern uint8_t SysCtl_getBSLEntryIndication(void); + +//***************************************************************************** +// +//! \brief Enables PMM Access Protection. +//! +//! This function enables the PMM Access Protection, which will lock any +//! changes on the PMM control registers until a BOR occurs. +//! +//! +//! \return None +// +//***************************************************************************** +extern void SysCtl_enablePMMAccessProtect(void); + +//***************************************************************************** +// +//! \brief Enables RAM-based Interrupt Vectors. +//! +//! This function enables RAM-base Interrupt Vectors, which means that +//! interrupt vectors are generated with the end address at the top of RAM, +//! instead of the top of the lower 64kB of flash. +//! +//! +//! \return None +// +//***************************************************************************** +extern void SysCtl_enableRAMBasedInterruptVectors(void); + +//***************************************************************************** +// +//! \brief Disables RAM-based Interrupt Vectors. +//! +//! This function disables the interrupt vectors from being generated at the +//! top of the RAM. +//! +//! +//! \return None +// +//***************************************************************************** +extern void SysCtl_disableRAMBasedInterruptVectors(void); + +//***************************************************************************** +// +//! \brief Initializes JTAG Mailbox with selected properties. +//! +//! This function sets the specified settings for the JTAG Mailbox system. The +//! settings that can be set are the size of the JTAG messages, and the auto- +//! clearing of the inbox flags. If the inbox flags are set to auto-clear, then +//! the inbox flags will be cleared upon reading of the inbox message buffer, +//! otherwise they will have to be reset by software using the +//! SYS_clearJTAGMailboxFlagStatus() function. +//! +//! \param mailboxSizeSelect is the size of the JTAG Mailboxes, whether 16- or +//! 32-bits. +//! Valid values are: +//! - \b SYSCTL_JTAGMBSIZE_16BIT [Default] - the JTAG messages will take +//! up only one JTAG mailbox (i. e. an outgoing message will take up +//! only 1 outbox of the JTAG mailboxes) +//! - \b SYSCTL_JTAGMBSIZE_32BIT - the JTAG messages will be contained +//! within both JTAG mailboxes (i. e. an outgoing message will take +//! up both Outboxes of the JTAG mailboxes) +//! \n Modified bits are \b JMBMODE of \b SYSJMBC register. +//! \param autoClearInboxFlagSelect decides how the JTAG inbox flags should be +//! cleared, whether automatically after the corresponding outbox has +//! been written to, or manually by software. +//! Valid values are: +//! - \b SYSCTL_JTAGINBOX0AUTO_JTAGINBOX1AUTO [Default] - both JTAG +//! inbox flags will be reset automatically when the corresponding +//! inbox is read from. +//! - \b SYSCTL_JTAGINBOX0AUTO_JTAGINBOX1SW - only JTAG inbox 0 flag is +//! reset automatically, while JTAG inbox 1 is reset with the +//! - \b SYSCTL_JTAGINBOX0SW_JTAGINBOX1AUTO - only JTAG inbox 1 flag is +//! reset automatically, while JTAG inbox 0 is reset with the +//! - \b SYSCTL_JTAGINBOX0SW_JTAGINBOX1SW - both JTAG inbox flags will +//! need to be reset manually by the +//! \n Modified bits are \b JMBCLR0OFF and \b JMBCLR1OFF of \b SYSJMBC +//! register. +//! +//! \return None +// +//***************************************************************************** +extern void SysCtl_initJTAGMailbox(uint8_t mailboxSizeSelect, + uint8_t autoClearInboxFlagSelect); + +//***************************************************************************** +// +//! \brief Returns the status of the selected JTAG Mailbox flags. +//! +//! This function will return the status of the selected JTAG Mailbox flags in +//! bit mask format matching that passed into the mailboxFlagMask parameter. +//! +//! \param mailboxFlagMask is the bit mask of JTAG mailbox flags that the +//! status of should be returned. +//! Mask value is the logical OR of any of the following: +//! - \b SYSCTL_JTAGOUTBOX_FLAG0 - flag for JTAG outbox 0 +//! - \b SYSCTL_JTAGOUTBOX_FLAG1 - flag for JTAG outbox 1 +//! - \b SYSCTL_JTAGINBOX_FLAG0 - flag for JTAG inbox 0 +//! - \b SYSCTL_JTAGINBOX_FLAG1 - flag for JTAG inbox 1 +//! +//! \return A bit mask of the status of the selected mailbox flags. +// +//***************************************************************************** +extern uint8_t SysCtl_getJTAGMailboxFlagStatus(uint8_t mailboxFlagMask); + +//***************************************************************************** +// +//! \brief Clears the status of the selected JTAG Mailbox flags. +//! +//! This function clears the selected JTAG Mailbox flags. +//! +//! \param mailboxFlagMask is the bit mask of JTAG mailbox flags that the +//! status of should be cleared. +//! Mask value is the logical OR of any of the following: +//! - \b SYSCTL_JTAGOUTBOX_FLAG0 - flag for JTAG outbox 0 +//! - \b SYSCTL_JTAGOUTBOX_FLAG1 - flag for JTAG outbox 1 +//! - \b SYSCTL_JTAGINBOX_FLAG0 - flag for JTAG inbox 0 +//! - \b SYSCTL_JTAGINBOX_FLAG1 - flag for JTAG inbox 1 +//! +//! \return None +// +//***************************************************************************** +extern void SysCtl_clearJTAGMailboxFlagStatus(uint8_t mailboxFlagMask); + +//***************************************************************************** +// +//! \brief Returns the contents of the selected JTAG Inbox in a 16 bit format. +//! +//! This function returns the message contents of the selected JTAG inbox. If +//! the auto clear settings for the Inbox flags were set, then using this +//! function will automatically clear the corresponding JTAG inbox flag. +//! +//! \param inboxSelect is the chosen JTAG inbox that the contents of should be +//! returned +//! Valid values are: +//! - \b SYSCTL_JTAGINBOX_0 - return contents of JTAG inbox 0 +//! - \b SYSCTL_JTAGINBOX_1 - return contents of JTAG inbox 1 +//! +//! \return The contents of the selected JTAG inbox in a 16 bit format. +// +//***************************************************************************** +extern uint16_t SysCtl_getJTAGInboxMessage16Bit(uint8_t inboxSelect); + +//***************************************************************************** +// +//! \brief Returns the contents of JTAG Inboxes in a 32 bit format. +//! +//! This function returns the message contents of both JTAG inboxes in a 32 bit +//! format. This function should be used if 32-bit messaging has been set in +//! the SYS_initJTAGMailbox() function. If the auto clear settings for the +//! Inbox flags were set, then using this function will automatically clear +//! both JTAG inbox flags. +//! +//! +//! \return The contents of both JTAG messages in a 32 bit format. +// +//***************************************************************************** +extern uint32_t SysCtl_getJTAGInboxMessage32Bit(void); + +//***************************************************************************** +// +//! \brief Sets a 16 bit outgoing message in to the selected JTAG Outbox. +//! +//! This function sets the outgoing message in the selected JTAG outbox. The +//! corresponding JTAG outbox flag is cleared after this function, and set +//! after the JTAG has read the message. +//! +//! \param outboxSelect is the chosen JTAG outbox that the message should be +//! set it. +//! Valid values are: +//! - \b SYSCTL_JTAGOUTBOX_0 - set the contents of JTAG outbox 0 +//! - \b SYSCTL_JTAGOUTBOX_1 - set the contents of JTAG outbox 1 +//! \param outgoingMessage is the message to send to the JTAG. +//! \n Modified bits are \b MSGHI and \b MSGLO of \b SYSJMBOx register. +//! +//! \return None +// +//***************************************************************************** +extern void SysCtl_setJTAGOutgoingMessage16Bit(uint8_t outboxSelect, + uint16_t outgoingMessage); + +//***************************************************************************** +// +//! \brief Sets a 32 bit message in to both JTAG Outboxes. +//! +//! This function sets the 32-bit outgoing message in both JTAG outboxes. The +//! JTAG outbox flags are cleared after this function, and set after the JTAG +//! has read the message. +//! +//! \param outgoingMessage is the message to send to the JTAG. +//! \n Modified bits are \b MSGHI and \b MSGLO of \b SYSJMBOx register. +//! +//! \return None +// +//***************************************************************************** +extern void SysCtl_setJTAGOutgoingMessage32Bit(uint32_t outgoingMessage); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_SYSCTL_H__ diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/timer_a.c b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/timer_a.c new file mode 100644 index 000000000..c9d983151 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/timer_a.c @@ -0,0 +1,373 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// timer_a.c - Driver for the timer_a Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup timer_a_api timer_a +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_TxA7__ +#include "timer_a.h" + +#include + +void Timer_A_startCounter(uint16_t baseAddress, + uint16_t timerMode) +{ + HWREG16(baseAddress + OFS_TAxCTL) |= timerMode; +} + +void Timer_A_initContinuousMode(uint16_t baseAddress, + Timer_A_initContinuousModeParam *param) +{ + HWREG16(baseAddress + + OFS_TAxCTL) &= ~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + + TIMER_A_UPDOWN_MODE + + TIMER_A_DO_CLEAR + + TIMER_A_TAIE_INTERRUPT_ENABLE + + ID__8 + ); + HWREG16(baseAddress + OFS_TAxEX0) &= ~TAIDEX_7; + + HWREG16(baseAddress + OFS_TAxEX0) |= param->clockSourceDivider & 0x7; + HWREG16(baseAddress + OFS_TAxCTL) |= (param->clockSource + + param->timerClear + + param->timerInterruptEnable_TAIE + + ((param->clockSourceDivider >> + 3) << 6)); + + if(param->startTimer) + { + HWREG16(baseAddress + OFS_TAxCTL) |= TIMER_A_CONTINUOUS_MODE; + } +} + +void Timer_A_initUpMode(uint16_t baseAddress, + Timer_A_initUpModeParam *param) +{ + HWREG16(baseAddress + OFS_TAxCTL) &= + ~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + + TIMER_A_UPDOWN_MODE + + TIMER_A_DO_CLEAR + + TIMER_A_TAIE_INTERRUPT_ENABLE + + ID__8 + ); + HWREG16(baseAddress + OFS_TAxEX0) &= ~TAIDEX_7; + + HWREG16(baseAddress + OFS_TAxEX0) |= param->clockSourceDivider & 0x7; + HWREG16(baseAddress + OFS_TAxCTL) |= (param->clockSource + + param->timerClear + + param->timerInterruptEnable_TAIE + + ((param->clockSourceDivider >> + 3) << 6)); + + if(param->startTimer) + { + HWREG16(baseAddress + OFS_TAxCTL) |= TIMER_A_UP_MODE; + } + + if(TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE == + param->captureCompareInterruptEnable_CCR0_CCIE) + { + HWREG16(baseAddress + + OFS_TAxCCTL0) |= TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE; + } + else + { + HWREG16(baseAddress + + OFS_TAxCCTL0) &= ~TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE; + } + + HWREG16(baseAddress + OFS_TAxCCR0) = param->timerPeriod; +} + +void Timer_A_initUpDownMode(uint16_t baseAddress, + Timer_A_initUpDownModeParam *param) +{ + HWREG16(baseAddress + OFS_TAxCTL) &= + ~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + + TIMER_A_UPDOWN_MODE + + TIMER_A_DO_CLEAR + + TIMER_A_TAIE_INTERRUPT_ENABLE + + ID__8 + ); + HWREG16(baseAddress + OFS_TAxEX0) &= ~TAIDEX_7; + + HWREG16(baseAddress + OFS_TAxEX0) |= param->clockSourceDivider & 0x7; + HWREG16(baseAddress + OFS_TAxCTL) |= (param->clockSource + + param->timerClear + + param->timerInterruptEnable_TAIE + + ((param->clockSourceDivider >> + 3) << 6)); + + if(param->startTimer) + { + HWREG16(baseAddress + OFS_TAxCTL) |= TIMER_A_UPDOWN_MODE; + } + + if(TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE == + param->captureCompareInterruptEnable_CCR0_CCIE) + { + HWREG16(baseAddress + + OFS_TAxCCTL0) |= TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE; + } + else + { + HWREG16(baseAddress + + OFS_TAxCCTL0) &= ~TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE; + } + + HWREG16(baseAddress + OFS_TAxCCR0) = param->timerPeriod; +} + +void Timer_A_initCaptureMode(uint16_t baseAddress, + Timer_A_initCaptureModeParam *param) +{ + HWREG16(baseAddress + param->captureRegister) |= CAP; + + HWREG16(baseAddress + param->captureRegister) &= + ~(TIMER_A_CAPTUREMODE_RISING_AND_FALLING_EDGE + + TIMER_A_CAPTURE_INPUTSELECT_Vcc + + TIMER_A_CAPTURE_SYNCHRONOUS + + TIMER_A_DO_CLEAR + + TIMER_A_TAIE_INTERRUPT_ENABLE + + CM_3 + ); + + HWREG16(baseAddress + param->captureRegister) |= (param->captureMode + + param->captureInputSelect + + + param-> + synchronizeCaptureSource + + param-> + captureInterruptEnable + + param->captureOutputMode + ); +} + +void Timer_A_initCompareMode(uint16_t baseAddress, + Timer_A_initCompareModeParam *param) +{ + HWREG16(baseAddress + param->compareRegister) &= ~CAP; + + HWREG16(baseAddress + param->compareRegister) &= + ~(TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE + + TIMER_A_OUTPUTMODE_RESET_SET + ); + + HWREG16(baseAddress + + param->compareRegister) |= (param->compareInterruptEnable + + param->compareOutputMode + ); + + HWREG16(baseAddress + param->compareRegister + + OFS_TAxR) = param->compareValue; +} + +void Timer_A_enableInterrupt(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_TAxCTL) |= TAIE; +} + +void Timer_A_disableInterrupt(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_TAxCTL) &= ~TAIE; +} + +uint32_t Timer_A_getInterruptStatus(uint16_t baseAddress) +{ + return (HWREG16(baseAddress + OFS_TAxCTL) & TAIFG); +} + +void Timer_A_enableCaptureCompareInterrupt(uint16_t baseAddress, + uint16_t captureCompareRegister) +{ + HWREG16(baseAddress + captureCompareRegister) |= CCIE; +} + +void Timer_A_disableCaptureCompareInterrupt(uint16_t baseAddress, + uint16_t captureCompareRegister) +{ + HWREG16(baseAddress + captureCompareRegister) &= ~CCIE; +} + +uint32_t Timer_A_getCaptureCompareInterruptStatus(uint16_t baseAddress, + uint16_t captureCompareRegister, + uint16_t mask) +{ + return (HWREG16(baseAddress + captureCompareRegister) & mask); +} + +void Timer_A_clear(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_TAxCTL) |= TACLR; +} + +uint8_t Timer_A_getSynchronizedCaptureCompareInput(uint16_t baseAddress, + uint16_t captureCompareRegister, + uint16_t synchronized) +{ + if(HWREG16(baseAddress + captureCompareRegister) & synchronized) + { + return (TIMER_A_CAPTURECOMPARE_INPUT_HIGH); + } + else + { + return (TIMER_A_CAPTURECOMPARE_INPUT_LOW); + } +} + +uint8_t Timer_A_getOutputForOutputModeOutBitValue(uint16_t baseAddress, + uint16_t captureCompareRegister) +{ + if(HWREG16(baseAddress + captureCompareRegister) & OUT) + { + return (TIMER_A_OUTPUTMODE_OUTBITVALUE_HIGH); + } + else + { + return (TIMER_A_OUTPUTMODE_OUTBITVALUE_LOW); + } +} + +uint16_t Timer_A_getCaptureCompareCount(uint16_t baseAddress, + uint16_t captureCompareRegister) +{ + return (HWREG16(baseAddress + OFS_TAxR + captureCompareRegister)); +} + +void Timer_A_setOutputForOutputModeOutBitValue(uint16_t baseAddress, + uint16_t captureCompareRegister, + uint8_t outputModeOutBitValue) +{ + HWREG16(baseAddress + captureCompareRegister) &= ~OUT; + HWREG16(baseAddress + captureCompareRegister) |= outputModeOutBitValue; +} + +void Timer_A_outputPWM(uint16_t baseAddress, + Timer_A_outputPWMParam *param) +{ + HWREG16(baseAddress + OFS_TAxCTL) &= + ~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + + TIMER_A_UPDOWN_MODE + TIMER_A_DO_CLEAR + + TIMER_A_TAIE_INTERRUPT_ENABLE + + ID__8 + ); + HWREG16(baseAddress + OFS_TAxEX0) &= ~TAIDEX_7; + + HWREG16(baseAddress + OFS_TAxEX0) |= param->clockSourceDivider & 0x7; + HWREG16(baseAddress + OFS_TAxCTL) |= (param->clockSource + + TIMER_A_UP_MODE + + TIMER_A_DO_CLEAR + + ((param->clockSourceDivider >> + 3) << 6)); + + HWREG16(baseAddress + OFS_TAxCCR0) = param->timerPeriod; + + HWREG16(baseAddress + OFS_TAxCCTL0) &= + ~(TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE + + TIMER_A_OUTPUTMODE_RESET_SET); + + HWREG16(baseAddress + param->compareRegister) |= param->compareOutputMode; + + HWREG16(baseAddress + param->compareRegister + OFS_TAxR) = param->dutyCycle; +} + +void Timer_A_stop(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_TAxCTL) &= ~MC_3; +} + +void Timer_A_setCompareValue(uint16_t baseAddress, + uint16_t compareRegister, + uint16_t compareValue) +{ + HWREG16(baseAddress + compareRegister + OFS_TAxR) = compareValue; +} + +void Timer_A_clearTimerInterrupt(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_TAxCTL) &= ~TAIFG; +} + +void Timer_A_clearCaptureCompareInterrupt(uint16_t baseAddress, + uint16_t captureCompareRegister) +{ + HWREG16(baseAddress + captureCompareRegister) &= ~CCIFG; +} + +uint16_t Timer_A_getCounterValue(uint16_t baseAddress) +{ + uint16_t voteOne, voteTwo, res; + + voteTwo = HWREG16(baseAddress + OFS_TAxR); + + do + { + voteOne = voteTwo; + voteTwo = HWREG16(baseAddress + OFS_TAxR); + + if(voteTwo > voteOne) + { + res = voteTwo - voteOne; + } + else if(voteOne > voteTwo) + { + res = voteOne - voteTwo; + } + else + { + res = 0; + } + } + while(res > TIMER_A_THRESHOLD); + + return(voteTwo); +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for timer_a_api +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/timer_a.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/timer_a.h new file mode 100644 index 000000000..32ce2dcba --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/timer_a.h @@ -0,0 +1,1065 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// timer_a.h - Driver for the TIMER_A Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_TIMER_A_H__ +#define __MSP430WARE_TIMER_A_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_TxA7__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "inc/hw_regaccess.h" +//***************************************************************************** +// +// The following is a parameter used for Timer_A_getCounterValue that +// determines the maximum difference in counts of the TAxR register for a +// majority vote. +// +//***************************************************************************** +#define TIMER_A_THRESHOLD 50 + +//***************************************************************************** +// +//! \brief Used in the Timer_A_initContinuousMode() function as the param +//! parameter. +// +//***************************************************************************** +typedef struct Timer_A_initContinuousModeParam +{ + //! Selects Clock source. + //! \n Valid values are: + //! - \b TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK [Default] + //! - \b TIMER_A_CLOCKSOURCE_ACLK + //! - \b TIMER_A_CLOCKSOURCE_SMCLK + //! - \b TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + uint16_t clockSource; + //! Is the desired divider for the clock source + //! \n Valid values are: + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_1 [Default] + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_2 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_3 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_4 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_5 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_6 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_7 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_8 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_10 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_12 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_14 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_16 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_20 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_24 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_28 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_32 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_40 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_48 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_56 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_64 + uint16_t clockSourceDivider; + //! Is to enable or disable Timer_A interrupt + //! \n Valid values are: + //! - \b TIMER_A_TAIE_INTERRUPT_ENABLE + //! - \b TIMER_A_TAIE_INTERRUPT_DISABLE [Default] + uint16_t timerInterruptEnable_TAIE; + //! Decides if Timer_A clock divider, count direction, count need to be + //! reset. + //! \n Valid values are: + //! - \b TIMER_A_DO_CLEAR + //! - \b TIMER_A_SKIP_CLEAR [Default] + uint16_t timerClear; + //! Whether to start the timer immediately + bool startTimer; +} Timer_A_initContinuousModeParam; + +//***************************************************************************** +// +//! \brief Used in the Timer_A_initCaptureMode() function as the param +//! parameter. +// +//***************************************************************************** +typedef struct Timer_A_initCaptureModeParam +{ + //! Selects the Capture register being used. Refer to datasheet to ensure + //! the device has the capture compare register being used. + //! \n Valid values are: + //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0 + //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1 + //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2 + //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3 + //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4 + //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5 + //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6 + uint16_t captureRegister; + //! Is the capture mode selected. + //! \n Valid values are: + //! - \b TIMER_A_CAPTUREMODE_NO_CAPTURE [Default] + //! - \b TIMER_A_CAPTUREMODE_RISING_EDGE + //! - \b TIMER_A_CAPTUREMODE_FALLING_EDGE + //! - \b TIMER_A_CAPTUREMODE_RISING_AND_FALLING_EDGE + uint16_t captureMode; + //! Decides the Input Select + //! \n Valid values are: + //! - \b TIMER_A_CAPTURE_INPUTSELECT_CCIxA + //! - \b TIMER_A_CAPTURE_INPUTSELECT_CCIxB + //! - \b TIMER_A_CAPTURE_INPUTSELECT_GND + //! - \b TIMER_A_CAPTURE_INPUTSELECT_Vcc + uint16_t captureInputSelect; + //! Decides if capture source should be synchronized with timer clock + //! \n Valid values are: + //! - \b TIMER_A_CAPTURE_ASYNCHRONOUS [Default] + //! - \b TIMER_A_CAPTURE_SYNCHRONOUS + uint16_t synchronizeCaptureSource; + //! Is to enable or disable timer captureComapre interrupt. + //! \n Valid values are: + //! - \b TIMER_A_CAPTURECOMPARE_INTERRUPT_DISABLE [Default] + //! - \b TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE + uint16_t captureInterruptEnable; + //! Specifies the output mode. + //! \n Valid values are: + //! - \b TIMER_A_OUTPUTMODE_OUTBITVALUE [Default] + //! - \b TIMER_A_OUTPUTMODE_SET + //! - \b TIMER_A_OUTPUTMODE_TOGGLE_RESET + //! - \b TIMER_A_OUTPUTMODE_SET_RESET + //! - \b TIMER_A_OUTPUTMODE_TOGGLE + //! - \b TIMER_A_OUTPUTMODE_RESET + //! - \b TIMER_A_OUTPUTMODE_TOGGLE_SET + //! - \b TIMER_A_OUTPUTMODE_RESET_SET + uint16_t captureOutputMode; +} Timer_A_initCaptureModeParam; + +//***************************************************************************** +// +//! \brief Used in the Timer_A_initUpDownMode() function as the param +//! parameter. +// +//***************************************************************************** +typedef struct Timer_A_initUpDownModeParam +{ + //! Selects Clock source. + //! \n Valid values are: + //! - \b TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK [Default] + //! - \b TIMER_A_CLOCKSOURCE_ACLK + //! - \b TIMER_A_CLOCKSOURCE_SMCLK + //! - \b TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + uint16_t clockSource; + //! Is the desired divider for the clock source + //! \n Valid values are: + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_1 [Default] + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_2 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_3 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_4 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_5 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_6 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_7 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_8 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_10 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_12 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_14 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_16 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_20 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_24 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_28 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_32 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_40 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_48 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_56 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_64 + uint16_t clockSourceDivider; + //! Is the specified Timer_A period + uint16_t timerPeriod; + //! Is to enable or disable Timer_A interrupt + //! \n Valid values are: + //! - \b TIMER_A_TAIE_INTERRUPT_ENABLE + //! - \b TIMER_A_TAIE_INTERRUPT_DISABLE [Default] + uint16_t timerInterruptEnable_TAIE; + //! Is to enable or disable Timer_A CCR0 captureComapre interrupt. + //! \n Valid values are: + //! - \b TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE + //! - \b TIMER_A_CCIE_CCR0_INTERRUPT_DISABLE [Default] + uint16_t captureCompareInterruptEnable_CCR0_CCIE; + //! Decides if Timer_A clock divider, count direction, count need to be + //! reset. + //! \n Valid values are: + //! - \b TIMER_A_DO_CLEAR + //! - \b TIMER_A_SKIP_CLEAR [Default] + uint16_t timerClear; + //! Whether to start the timer immediately + bool startTimer; +} Timer_A_initUpDownModeParam; + +//***************************************************************************** +// +//! \brief Used in the Timer_A_outputPWM() function as the param parameter. +// +//***************************************************************************** +typedef struct Timer_A_outputPWMParam +{ + //! Selects Clock source. + //! \n Valid values are: + //! - \b TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK [Default] + //! - \b TIMER_A_CLOCKSOURCE_ACLK + //! - \b TIMER_A_CLOCKSOURCE_SMCLK + //! - \b TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + uint16_t clockSource; + //! Is the desired divider for the clock source + //! \n Valid values are: + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_1 [Default] + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_2 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_3 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_4 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_5 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_6 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_7 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_8 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_10 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_12 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_14 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_16 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_20 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_24 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_28 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_32 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_40 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_48 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_56 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_64 + uint16_t clockSourceDivider; + //! Selects the desired timer period + uint16_t timerPeriod; + //! Selects the compare register being used. Refer to datasheet to ensure + //! the device has the capture compare register being used. + //! \n Valid values are: + //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0 + //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1 + //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2 + //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3 + //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4 + //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5 + //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6 + uint16_t compareRegister; + //! Specifies the output mode. + //! \n Valid values are: + //! - \b TIMER_A_OUTPUTMODE_OUTBITVALUE [Default] + //! - \b TIMER_A_OUTPUTMODE_SET + //! - \b TIMER_A_OUTPUTMODE_TOGGLE_RESET + //! - \b TIMER_A_OUTPUTMODE_SET_RESET + //! - \b TIMER_A_OUTPUTMODE_TOGGLE + //! - \b TIMER_A_OUTPUTMODE_RESET + //! - \b TIMER_A_OUTPUTMODE_TOGGLE_SET + //! - \b TIMER_A_OUTPUTMODE_RESET_SET + uint16_t compareOutputMode; + //! Specifies the dutycycle for the generated waveform + uint16_t dutyCycle; +} Timer_A_outputPWMParam; + +//***************************************************************************** +// +//! \brief Used in the Timer_A_initUpMode() function as the param parameter. +// +//***************************************************************************** +typedef struct Timer_A_initUpModeParam +{ + //! Selects Clock source. + //! \n Valid values are: + //! - \b TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK [Default] + //! - \b TIMER_A_CLOCKSOURCE_ACLK + //! - \b TIMER_A_CLOCKSOURCE_SMCLK + //! - \b TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + uint16_t clockSource; + //! Is the desired divider for the clock source + //! \n Valid values are: + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_1 [Default] + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_2 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_3 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_4 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_5 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_6 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_7 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_8 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_10 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_12 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_14 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_16 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_20 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_24 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_28 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_32 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_40 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_48 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_56 + //! - \b TIMER_A_CLOCKSOURCE_DIVIDER_64 + uint16_t clockSourceDivider; + //! Is the specified Timer_A period. This is the value that gets written + //! into the CCR0. Limited to 16 bits[uint16_t] + uint16_t timerPeriod; + //! Is to enable or disable Timer_A interrupt + //! \n Valid values are: + //! - \b TIMER_A_TAIE_INTERRUPT_ENABLE + //! - \b TIMER_A_TAIE_INTERRUPT_DISABLE [Default] + uint16_t timerInterruptEnable_TAIE; + //! Is to enable or disable Timer_A CCR0 captureComapre interrupt. + //! \n Valid values are: + //! - \b TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE + //! - \b TIMER_A_CCIE_CCR0_INTERRUPT_DISABLE [Default] + uint16_t captureCompareInterruptEnable_CCR0_CCIE; + //! Decides if Timer_A clock divider, count direction, count need to be + //! reset. + //! \n Valid values are: + //! - \b TIMER_A_DO_CLEAR + //! - \b TIMER_A_SKIP_CLEAR [Default] + uint16_t timerClear; + //! Whether to start the timer immediately + bool startTimer; +} Timer_A_initUpModeParam; + +//***************************************************************************** +// +//! \brief Used in the Timer_A_initCompareMode() function as the param +//! parameter. +// +//***************************************************************************** +typedef struct Timer_A_initCompareModeParam +{ + //! Selects the Capture register being used. Refer to datasheet to ensure + //! the device has the capture compare register being used. + //! \n Valid values are: + //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0 + //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1 + //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2 + //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3 + //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4 + //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5 + //! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6 + uint16_t compareRegister; + //! Is to enable or disable timer captureComapre interrupt. + //! \n Valid values are: + //! - \b TIMER_A_CAPTURECOMPARE_INTERRUPT_DISABLE [Default] + //! - \b TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE + uint16_t compareInterruptEnable; + //! Specifies the output mode. + //! \n Valid values are: + //! - \b TIMER_A_OUTPUTMODE_OUTBITVALUE [Default] + //! - \b TIMER_A_OUTPUTMODE_SET + //! - \b TIMER_A_OUTPUTMODE_TOGGLE_RESET + //! - \b TIMER_A_OUTPUTMODE_SET_RESET + //! - \b TIMER_A_OUTPUTMODE_TOGGLE + //! - \b TIMER_A_OUTPUTMODE_RESET + //! - \b TIMER_A_OUTPUTMODE_TOGGLE_SET + //! - \b TIMER_A_OUTPUTMODE_RESET_SET + uint16_t compareOutputMode; + //! Is the count to be compared with in compare mode + uint16_t compareValue; +} Timer_A_initCompareModeParam; + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: Timer_A_initContinuousMode(), Timer_A_initUpMode(), +// Timer_A_initUpDownMode(), and Timer_A_outputPWM(). +// +//***************************************************************************** +#define TIMER_A_CLOCKSOURCE_DIVIDER_1 0x00 +#define TIMER_A_CLOCKSOURCE_DIVIDER_2 0x08 +#define TIMER_A_CLOCKSOURCE_DIVIDER_3 0x02 +#define TIMER_A_CLOCKSOURCE_DIVIDER_4 0x10 +#define TIMER_A_CLOCKSOURCE_DIVIDER_5 0x04 +#define TIMER_A_CLOCKSOURCE_DIVIDER_6 0x05 +#define TIMER_A_CLOCKSOURCE_DIVIDER_7 0x06 +#define TIMER_A_CLOCKSOURCE_DIVIDER_8 0x18 +#define TIMER_A_CLOCKSOURCE_DIVIDER_10 0x0C +#define TIMER_A_CLOCKSOURCE_DIVIDER_12 0x0D +#define TIMER_A_CLOCKSOURCE_DIVIDER_14 0x0E +#define TIMER_A_CLOCKSOURCE_DIVIDER_16 0x0F +#define TIMER_A_CLOCKSOURCE_DIVIDER_20 0x14 +#define TIMER_A_CLOCKSOURCE_DIVIDER_24 0x15 +#define TIMER_A_CLOCKSOURCE_DIVIDER_28 0x16 +#define TIMER_A_CLOCKSOURCE_DIVIDER_32 0x17 +#define TIMER_A_CLOCKSOURCE_DIVIDER_40 0x1C +#define TIMER_A_CLOCKSOURCE_DIVIDER_48 0x1D +#define TIMER_A_CLOCKSOURCE_DIVIDER_56 0x1E +#define TIMER_A_CLOCKSOURCE_DIVIDER_64 0x1F + +//***************************************************************************** +// +// The following are values that can be passed to the timerMode parameter for +// functions: Timer_A_startCounter(). +// +//***************************************************************************** +#define TIMER_A_STOP_MODE MC_0 +#define TIMER_A_UP_MODE MC_1 +#define TIMER_A_CONTINUOUS_MODE MC_2 +#define TIMER_A_UPDOWN_MODE MC_3 + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: Timer_A_initContinuousMode(), Timer_A_initUpMode(), and +// Timer_A_initUpDownMode(). +// +//***************************************************************************** +#define TIMER_A_DO_CLEAR TACLR +#define TIMER_A_SKIP_CLEAR 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: Timer_A_initContinuousMode(), Timer_A_initUpMode(), +// Timer_A_initUpDownMode(), and Timer_A_outputPWM(). +// +//***************************************************************************** +#define TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK TASSEL__TACLK +#define TIMER_A_CLOCKSOURCE_ACLK TASSEL__ACLK +#define TIMER_A_CLOCKSOURCE_SMCLK TASSEL__SMCLK +#define TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK TASSEL__INCLK + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: Timer_A_initContinuousMode(), Timer_A_initUpMode(), and +// Timer_A_initUpDownMode(). +// +//***************************************************************************** +#define TIMER_A_TAIE_INTERRUPT_ENABLE TAIE +#define TIMER_A_TAIE_INTERRUPT_DISABLE 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: Timer_A_initUpMode(), and Timer_A_initUpDownMode(). +// +//***************************************************************************** +#define TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE CCIE +#define TIMER_A_CCIE_CCR0_INTERRUPT_DISABLE 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: Timer_A_initCaptureMode(), and Timer_A_initCompareMode(). +// +//***************************************************************************** +#define TIMER_A_CAPTURECOMPARE_INTERRUPT_DISABLE 0x00 +#define TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE CCIE + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: Timer_A_initCaptureMode(). +// +//***************************************************************************** +#define TIMER_A_CAPTURE_INPUTSELECT_CCIxA CCIS_0 +#define TIMER_A_CAPTURE_INPUTSELECT_CCIxB CCIS_1 +#define TIMER_A_CAPTURE_INPUTSELECT_GND CCIS_2 +#define TIMER_A_CAPTURE_INPUTSELECT_Vcc CCIS_3 + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: Timer_A_initCaptureMode(), Timer_A_initCompareMode(), and +// Timer_A_outputPWM(). +// +//***************************************************************************** +#define TIMER_A_OUTPUTMODE_OUTBITVALUE OUTMOD_0 +#define TIMER_A_OUTPUTMODE_SET OUTMOD_1 +#define TIMER_A_OUTPUTMODE_TOGGLE_RESET OUTMOD_2 +#define TIMER_A_OUTPUTMODE_SET_RESET OUTMOD_3 +#define TIMER_A_OUTPUTMODE_TOGGLE OUTMOD_4 +#define TIMER_A_OUTPUTMODE_RESET OUTMOD_5 +#define TIMER_A_OUTPUTMODE_TOGGLE_SET OUTMOD_6 +#define TIMER_A_OUTPUTMODE_RESET_SET OUTMOD_7 + +//***************************************************************************** +// +// The following are values that can be passed to the compareRegister parameter +// for functions: Timer_A_setCompareValue(); the captureCompareRegister +// parameter for functions: Timer_A_enableCaptureCompareInterrupt(), +// Timer_A_disableCaptureCompareInterrupt(), +// Timer_A_getCaptureCompareInterruptStatus(), +// Timer_A_getSynchronizedCaptureCompareInput(), +// Timer_A_getOutputForOutputModeOutBitValue(), +// Timer_A_getCaptureCompareCount(), +// Timer_A_setOutputForOutputModeOutBitValue(), and +// Timer_A_clearCaptureCompareInterrupt(); the param parameter for functions: +// Timer_A_initCaptureMode(), Timer_A_initCompareMode(), and +// Timer_A_outputPWM(). +// +//***************************************************************************** +#define TIMER_A_CAPTURECOMPARE_REGISTER_0 0x02 +#define TIMER_A_CAPTURECOMPARE_REGISTER_1 0x04 +#define TIMER_A_CAPTURECOMPARE_REGISTER_2 0x06 +#define TIMER_A_CAPTURECOMPARE_REGISTER_3 0x08 +#define TIMER_A_CAPTURECOMPARE_REGISTER_4 0x0A +#define TIMER_A_CAPTURECOMPARE_REGISTER_5 0x0C +#define TIMER_A_CAPTURECOMPARE_REGISTER_6 0x0E + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: Timer_A_initCaptureMode(). +// +//***************************************************************************** +#define TIMER_A_CAPTUREMODE_NO_CAPTURE CM_0 +#define TIMER_A_CAPTUREMODE_RISING_EDGE CM_1 +#define TIMER_A_CAPTUREMODE_FALLING_EDGE CM_2 +#define TIMER_A_CAPTUREMODE_RISING_AND_FALLING_EDGE CM_3 + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: Timer_A_initCaptureMode(). +// +//***************************************************************************** +#define TIMER_A_CAPTURE_ASYNCHRONOUS 0x00 +#define TIMER_A_CAPTURE_SYNCHRONOUS SCS + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: Timer_A_getCaptureCompareInterruptStatus() as well as returned by +// the Timer_A_getCaptureCompareInterruptStatus() function. +// +//***************************************************************************** +#define TIMER_A_CAPTURE_OVERFLOW COV +#define TIMER_A_CAPTURECOMPARE_INTERRUPT_FLAG CCIFG + +//***************************************************************************** +// +// The following are values that can be passed to the synchronized parameter +// for functions: Timer_A_getSynchronizedCaptureCompareInput(). +// +//***************************************************************************** +#define TIMER_A_READ_SYNCHRONIZED_CAPTURECOMPAREINPUT SCCI +#define TIMER_A_READ_CAPTURE_COMPARE_INPUT CCI + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the Timer_A_getSynchronizedCaptureCompareInput() +// function. +// +//***************************************************************************** +#define TIMER_A_CAPTURECOMPARE_INPUT_HIGH 0x01 +#define TIMER_A_CAPTURECOMPARE_INPUT_LOW 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the outputModeOutBitValue +// parameter for functions: Timer_A_setOutputForOutputModeOutBitValue() as well +// as returned by the Timer_A_getOutputForOutputModeOutBitValue() function. +// +//***************************************************************************** +#define TIMER_A_OUTPUTMODE_OUTBITVALUE_HIGH OUT +#define TIMER_A_OUTPUTMODE_OUTBITVALUE_LOW 0x00 + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the Timer_A_getInterruptStatus() function. +// +//***************************************************************************** +#define TIMER_A_INTERRUPT_NOT_PENDING 0x00 +#define TIMER_A_INTERRUPT_PENDING 0x01 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Starts Timer_A counter +//! +//! This function assumes that the timer has been previously configured using +//! Timer_A_configureContinuousMode, Timer_A_configureUpMode or +//! Timer_A_configureUpDownMode. +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param timerMode mode to put the timer in +//! Valid values are: +//! - \b TIMER_A_STOP_MODE +//! - \b TIMER_A_UP_MODE +//! - \b TIMER_A_CONTINUOUS_MODE [Default] +//! - \b TIMER_A_UPDOWN_MODE +//! +//! Modified bits of \b TAxCTL register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_A_startCounter(uint16_t baseAddress, + uint16_t timerMode); + +//***************************************************************************** +// +//! \brief Configures Timer_A in continuous mode. +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param param is the pointer to struct for continuous mode initialization. +//! +//! Modified bits of \b TAxCTL register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_A_initContinuousMode(uint16_t baseAddress, + Timer_A_initContinuousModeParam *param); + +//***************************************************************************** +// +//! \brief Configures Timer_A in up mode. +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param param is the pointer to struct for up mode initialization. +//! +//! Modified bits of \b TAxCTL register, bits of \b TAxCCTL0 register and bits +//! of \b TAxCCR0 register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_A_initUpMode(uint16_t baseAddress, + Timer_A_initUpModeParam *param); + +//***************************************************************************** +// +//! \brief Configures Timer_A in up down mode. +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param param is the pointer to struct for up-down mode initialization. +//! +//! Modified bits of \b TAxCTL register, bits of \b TAxCCTL0 register and bits +//! of \b TAxCCR0 register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_A_initUpDownMode(uint16_t baseAddress, + Timer_A_initUpDownModeParam *param); + +//***************************************************************************** +// +//! \brief Initializes Capture Mode +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param param is the pointer to struct for capture mode initialization. +//! +//! Modified bits of \b TAxCCTLn register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_A_initCaptureMode(uint16_t baseAddress, + Timer_A_initCaptureModeParam *param); + +//***************************************************************************** +// +//! \brief Initializes Compare Mode +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param param is the pointer to struct for compare mode initialization. +//! +//! Modified bits of \b TAxCCRn register and bits of \b TAxCCTLn register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_A_initCompareMode(uint16_t baseAddress, + Timer_A_initCompareModeParam *param); + +//***************************************************************************** +// +//! \brief Enable timer interrupt +//! +//! Does not clear interrupt flags +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! +//! Modified bits of \b TAxCTL register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_A_enableInterrupt(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Disable timer interrupt +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! +//! Modified bits of \b TAxCTL register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_A_disableInterrupt(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Get timer interrupt status +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! +//! \return One of the following: +//! - \b Timer_A_INTERRUPT_NOT_PENDING +//! - \b Timer_A_INTERRUPT_PENDING +//! \n indicating the Timer_A interrupt status +// +//***************************************************************************** +extern uint32_t Timer_A_getInterruptStatus(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Enable capture compare interrupt +//! +//! Does not clear interrupt flags +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param captureCompareRegister is the selected capture compare register +//! Valid values are: +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6 +//! +//! Modified bits of \b TAxCCTLn register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_A_enableCaptureCompareInterrupt(uint16_t baseAddress, + uint16_t captureCompareRegister); + +//***************************************************************************** +// +//! \brief Disable capture compare interrupt +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param captureCompareRegister is the selected capture compare register +//! Valid values are: +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6 +//! +//! Modified bits of \b TAxCCTLn register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_A_disableCaptureCompareInterrupt(uint16_t baseAddress, + uint16_t captureCompareRegister); + +//***************************************************************************** +// +//! \brief Return capture compare interrupt status +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param captureCompareRegister is the selected capture compare register +//! Valid values are: +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6 +//! \param mask is the mask for the interrupt status +//! Mask value is the logical OR of any of the following: +//! - \b TIMER_A_CAPTURE_OVERFLOW +//! - \b TIMER_A_CAPTURECOMPARE_INTERRUPT_FLAG +//! +//! \return Logical OR of any of the following: +//! - \b Timer_A_CAPTURE_OVERFLOW +//! - \b Timer_A_CAPTURECOMPARE_INTERRUPT_FLAG +//! \n indicating the status of the masked interrupts +// +//***************************************************************************** +extern uint32_t Timer_A_getCaptureCompareInterruptStatus(uint16_t baseAddress, + uint16_t captureCompareRegister, + uint16_t mask); + +//***************************************************************************** +// +//! \brief Reset/Clear the timer clock divider, count direction, count +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! +//! Modified bits of \b TAxCTL register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_A_clear(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Get synchronized capturecompare input +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param captureCompareRegister +//! Valid values are: +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6 +//! \param synchronized +//! Valid values are: +//! - \b TIMER_A_READ_SYNCHRONIZED_CAPTURECOMPAREINPUT +//! - \b TIMER_A_READ_CAPTURE_COMPARE_INPUT +//! +//! \return One of the following: +//! - \b Timer_A_CAPTURECOMPARE_INPUT_HIGH +//! - \b Timer_A_CAPTURECOMPARE_INPUT_LOW +// +//***************************************************************************** +extern uint8_t Timer_A_getSynchronizedCaptureCompareInput(uint16_t baseAddress, + uint16_t captureCompareRegister, + uint16_t synchronized); + +//***************************************************************************** +// +//! \brief Get output bit for output mode +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param captureCompareRegister +//! Valid values are: +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6 +//! +//! \return One of the following: +//! - \b Timer_A_OUTPUTMODE_OUTBITVALUE_HIGH +//! - \b Timer_A_OUTPUTMODE_OUTBITVALUE_LOW +// +//***************************************************************************** +extern uint8_t Timer_A_getOutputForOutputModeOutBitValue(uint16_t baseAddress, + uint16_t captureCompareRegister); + +//***************************************************************************** +// +//! \brief Get current capturecompare count +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param captureCompareRegister +//! Valid values are: +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6 +//! +//! \return Current count as an uint16_t +// +//***************************************************************************** +extern uint16_t Timer_A_getCaptureCompareCount(uint16_t baseAddress, + uint16_t captureCompareRegister); + +//***************************************************************************** +// +//! \brief Set output bit for output mode +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param captureCompareRegister +//! Valid values are: +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6 +//! \param outputModeOutBitValue is the value to be set for out bit +//! Valid values are: +//! - \b TIMER_A_OUTPUTMODE_OUTBITVALUE_HIGH +//! - \b TIMER_A_OUTPUTMODE_OUTBITVALUE_LOW +//! +//! Modified bits of \b TAxCCTLn register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_A_setOutputForOutputModeOutBitValue(uint16_t baseAddress, + uint16_t captureCompareRegister, + uint8_t outputModeOutBitValue); + +//***************************************************************************** +// +//! \brief Generate a PWM with timer running in up mode +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param param is the pointer to struct for PWM configuration. +//! +//! Modified bits of \b TAxCTL register, bits of \b TAxCCTL0 register, bits of +//! \b TAxCCR0 register and bits of \b TAxCCTLn register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_A_outputPWM(uint16_t baseAddress, + Timer_A_outputPWMParam *param); + +//***************************************************************************** +// +//! \brief Stops the timer +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! +//! Modified bits of \b TAxCTL register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_A_stop(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Sets the value of the capture-compare register +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param compareRegister selects the Capture register being used. Refer to +//! datasheet to ensure the device has the capture compare register +//! being used. +//! Valid values are: +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6 +//! \param compareValue is the count to be compared with in compare mode +//! +//! Modified bits of \b TAxCCRn register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_A_setCompareValue(uint16_t baseAddress, + uint16_t compareRegister, + uint16_t compareValue); + +//***************************************************************************** +// +//! \brief Clears the Timer TAIFG interrupt flag +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! +//! Modified bits are \b TAIFG of \b TAxCTL register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_A_clearTimerInterrupt(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Clears the capture-compare interrupt flag +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! \param captureCompareRegister selects the Capture-compare register being +//! used. +//! Valid values are: +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6 +//! +//! Modified bits are \b CCIFG of \b TAxCCTLn register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_A_clearCaptureCompareInterrupt(uint16_t baseAddress, + uint16_t captureCompareRegister); + +//***************************************************************************** +// +//! \brief Reads the current timer count value +//! +//! Reads the current count value of the timer. There is a majority vote system +//! in place to confirm an accurate value is returned. The TIMER_A_THRESHOLD +//! #define in the corresponding header file can be modified so that the votes +//! must be closer together for a consensus to occur. +//! +//! \param baseAddress is the base address of the TIMER_A module. +//! +//! \return Majority vote of timer count value +// +//***************************************************************************** +extern uint16_t Timer_A_getCounterValue(uint16_t baseAddress); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_TIMER_A_H__ diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/timer_b.c b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/timer_b.c new file mode 100644 index 000000000..70754817e --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/timer_b.c @@ -0,0 +1,401 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// timer_b.c - Driver for the timer_b Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup timer_b_api timer_b +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_TxB7__ +#include "timer_b.h" + +#include + +void Timer_B_startCounter(uint16_t baseAddress, + uint16_t timerMode) +{ + HWREG16(baseAddress + OFS_TBxCTL) |= timerMode; +} + +void Timer_B_initContinuousMode(uint16_t baseAddress, + Timer_B_initContinuousModeParam *param) +{ + HWREG16(baseAddress + + OFS_TBxCTL) &= ~(TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + + TIMER_B_UPDOWN_MODE + + TIMER_B_DO_CLEAR + + TIMER_B_TBIE_INTERRUPT_ENABLE + + CNTL_3 + + ID__8 + ); + HWREG16(baseAddress + OFS_TBxEX0) &= ~TBIDEX_7; + + HWREG16(baseAddress + OFS_TBxEX0) |= param->clockSourceDivider & 0x7; + + HWREG16(baseAddress + OFS_TBxCTL) |= (param->clockSource + + param->timerClear + + param->timerInterruptEnable_TBIE + + ((param->clockSourceDivider >> + 3) << 6)); + + if(param->startTimer) + { + HWREG16(baseAddress + OFS_TBxCTL) |= TIMER_B_CONTINUOUS_MODE; + } +} + +void Timer_B_initUpMode(uint16_t baseAddress, + Timer_B_initUpModeParam *param) +{ + HWREG16(baseAddress + OFS_TBxCTL) &= + ~(TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + + TIMER_B_UPDOWN_MODE + + TIMER_B_DO_CLEAR + + TIMER_B_TBIE_INTERRUPT_ENABLE + + CNTL_3 + ); + HWREG16(baseAddress + OFS_TBxEX0) &= ~TBIDEX_7; + + HWREG16(baseAddress + OFS_TBxEX0) |= param->clockSourceDivider & 0x7; + + HWREG16(baseAddress + OFS_TBxCTL) |= (param->clockSource + + param->timerClear + + param->timerInterruptEnable_TBIE + + ((param->clockSourceDivider >> + 3) << 6)); + + if(param->startTimer) + { + HWREG16(baseAddress + OFS_TBxCTL) |= TIMER_B_UP_MODE; + } + + if(TIMER_B_CCIE_CCR0_INTERRUPT_ENABLE == + param->captureCompareInterruptEnable_CCR0_CCIE) + { + HWREG16(baseAddress + + OFS_TBxCCTL0) |= TIMER_B_CCIE_CCR0_INTERRUPT_ENABLE; + } + else + { + HWREG16(baseAddress + + OFS_TBxCCTL0) &= ~TIMER_B_CCIE_CCR0_INTERRUPT_ENABLE; + } + + HWREG16(baseAddress + OFS_TBxCCR0) = param->timerPeriod; +} + +void Timer_B_initUpDownMode(uint16_t baseAddress, + Timer_B_initUpDownModeParam *param) +{ + HWREG16(baseAddress + OFS_TBxCTL) &= + ~(TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + + TIMER_B_UPDOWN_MODE + + TIMER_B_DO_CLEAR + + TIMER_B_TBIE_INTERRUPT_ENABLE + + CNTL_3 + ); + HWREG16(baseAddress + OFS_TBxEX0) &= ~TBIDEX_7; + + HWREG16(baseAddress + OFS_TBxEX0) |= param->clockSourceDivider & 0x7; + + HWREG16(baseAddress + OFS_TBxCTL) |= (param->clockSource + + TIMER_B_STOP_MODE + + param->timerClear + + param->timerInterruptEnable_TBIE + + ((param->clockSourceDivider >> + 3) << 6)); + + if(param->startTimer) + { + HWREG16(baseAddress + OFS_TBxCTL) |= TIMER_B_UPDOWN_MODE; + } + + if(TIMER_B_CCIE_CCR0_INTERRUPT_ENABLE == + param->captureCompareInterruptEnable_CCR0_CCIE) + { + HWREG16(baseAddress + + OFS_TBxCCTL0) |= TIMER_B_CCIE_CCR0_INTERRUPT_ENABLE; + } + else + { + HWREG16(baseAddress + + OFS_TBxCCTL0) &= ~TIMER_B_CCIE_CCR0_INTERRUPT_ENABLE; + } + + HWREG16(baseAddress + OFS_TBxCCR0) = param->timerPeriod; +} + +void Timer_B_initCaptureMode(uint16_t baseAddress, + Timer_B_initCaptureModeParam *param) +{ + HWREG16(baseAddress + param->captureRegister) |= CAP; + + HWREG16(baseAddress + param->captureRegister) &= + ~(TIMER_B_CAPTUREMODE_RISING_AND_FALLING_EDGE + + TIMER_B_CAPTURE_INPUTSELECT_Vcc + + TIMER_B_CAPTURE_SYNCHRONOUS + + TIMER_B_DO_CLEAR + + TIMER_B_TBIE_INTERRUPT_ENABLE + + CM_3 + ); + + HWREG16(baseAddress + param->captureRegister) |= (param->captureMode + + param->captureInputSelect + + + param-> + synchronizeCaptureSource + + param-> + captureInterruptEnable + + param->captureOutputMode + ); +} + +void Timer_B_initCompareMode(uint16_t baseAddress, + Timer_B_initCompareModeParam *param) +{ + HWREG16(baseAddress + param->compareRegister) &= ~CAP; + + HWREG16(baseAddress + param->compareRegister) &= + ~(TIMER_B_CAPTURECOMPARE_INTERRUPT_ENABLE + + TIMER_B_OUTPUTMODE_RESET_SET + ); + + HWREG16(baseAddress + + param->compareRegister) |= (param->compareInterruptEnable + + param->compareOutputMode + ); + + HWREG16(baseAddress + param->compareRegister + + OFS_TBxR) = param->compareValue; +} + +void Timer_B_enableInterrupt(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_TBxCTL) |= TBIE; +} + +void Timer_B_disableInterrupt(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_TBxCTL) &= ~TBIE; +} + +uint32_t Timer_B_getInterruptStatus(uint16_t baseAddress) +{ + return (HWREG16(baseAddress + OFS_TBxCTL) & TBIFG); +} + +void Timer_B_enableCaptureCompareInterrupt(uint16_t baseAddress, + uint16_t captureCompareRegister) +{ + HWREG16(baseAddress + captureCompareRegister) |= CCIE; +} + +void Timer_B_disableCaptureCompareInterrupt(uint16_t baseAddress, + uint16_t captureCompareRegister) +{ + HWREG16(baseAddress + captureCompareRegister) &= ~CCIE; +} + +uint32_t Timer_B_getCaptureCompareInterruptStatus(uint16_t baseAddress, + uint16_t captureCompareRegister, + uint16_t mask) +{ + return (HWREG16(baseAddress + captureCompareRegister) & mask); +} + +void Timer_B_clear(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_TBxCTL) |= TBCLR; +} + +uint8_t Timer_B_getSynchronizedCaptureCompareInput(uint16_t baseAddress, + uint16_t captureCompareRegister, + uint16_t synchronized) +{ + if(HWREG16(baseAddress + captureCompareRegister) & synchronized) + { + return (TIMER_B_CAPTURECOMPARE_INPUT_HIGH); + } + else + { + return (TIMER_B_CAPTURECOMPARE_INPUT_LOW); + } +} + +uint8_t Timer_B_getOutputForOutputModeOutBitValue(uint16_t baseAddress, + uint16_t captureCompareRegister) +{ + if(HWREG16(baseAddress + captureCompareRegister) & OUT) + { + return (TIMER_B_OUTPUTMODE_OUTBITVALUE_HIGH); + } + else + { + return (TIMER_B_OUTPUTMODE_OUTBITVALUE_LOW); + } +} + +uint16_t Timer_B_getCaptureCompareCount(uint16_t baseAddress, + uint16_t captureCompareRegister) +{ + return (HWREG16(baseAddress + OFS_TBxR + captureCompareRegister)); +} + +void Timer_B_setOutputForOutputModeOutBitValue(uint16_t baseAddress, + uint16_t captureCompareRegister, + uint8_t outputModeOutBitValue) +{ + HWREG16(baseAddress + captureCompareRegister) &= ~OUT; + HWREG16(baseAddress + captureCompareRegister) |= outputModeOutBitValue; +} + +void Timer_B_outputPWM(uint16_t baseAddress, + Timer_B_outputPWMParam *param) +{ + HWREG16(baseAddress + OFS_TBxCTL) &= + ~(TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + + TIMER_B_UPDOWN_MODE + TIMER_B_DO_CLEAR + + TIMER_B_TBIE_INTERRUPT_ENABLE + ); + HWREG16(baseAddress + OFS_TBxEX0) &= ~TBIDEX_7; + + HWREG16(baseAddress + OFS_TBxEX0) |= param->clockSourceDivider & 0x7; + + HWREG16(baseAddress + OFS_TBxCTL) |= (param->clockSource + + TIMER_B_UP_MODE + + TIMER_B_DO_CLEAR + + ((param->clockSourceDivider >> + 3) << 6)); + + HWREG16(baseAddress + OFS_TBxCCR0) = param->timerPeriod; + + HWREG16(baseAddress + OFS_TBxCCTL0) &= + ~(TIMER_B_CAPTURECOMPARE_INTERRUPT_ENABLE + + TIMER_B_OUTPUTMODE_RESET_SET + ); + + HWREG16(baseAddress + param->compareRegister) |= param->compareOutputMode; + + HWREG16(baseAddress + param->compareRegister + OFS_TBxR) = param->dutyCycle; +} + +void Timer_B_stop(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_TBxCTL) &= ~MC_3; +} + +void Timer_B_setCompareValue(uint16_t baseAddress, + uint16_t compareRegister, + uint16_t compareValue) +{ + HWREG16(baseAddress + compareRegister + OFS_TBxR) = compareValue; +} + +void Timer_B_clearTimerInterrupt(uint16_t baseAddress) +{ + HWREG16(baseAddress + OFS_TBxCTL) &= ~TBIFG; +} + +void Timer_B_clearCaptureCompareInterrupt(uint16_t baseAddress, + uint16_t captureCompareRegister) +{ + HWREG16(baseAddress + captureCompareRegister) &= ~CCIFG; +} + +void Timer_B_selectCounterLength(uint16_t baseAddress, + uint16_t counterLength) +{ + HWREG16(baseAddress + OFS_TBxCTL) &= ~CNTL_3; + HWREG16(baseAddress + OFS_TBxCTL) |= counterLength; +} + +void Timer_B_selectLatchingGroup(uint16_t baseAddress, + uint16_t groupLatch) +{ + HWREG16(baseAddress + OFS_TBxCTL) &= ~TBCLGRP_3; + HWREG16(baseAddress + OFS_TBxCTL) |= groupLatch; +} + +void Timer_B_initCompareLatchLoadEvent(uint16_t baseAddress, + uint16_t compareRegister, + uint16_t compareLatchLoadEvent) +{ + HWREG16(baseAddress + compareRegister) &= ~CLLD_3; + HWREG16(baseAddress + compareRegister) |= compareLatchLoadEvent; +} + +uint16_t Timer_B_getCounterValue(uint16_t baseAddress) +{ + uint16_t voteOne, voteTwo, res; + + voteTwo = HWREG16(baseAddress + OFS_TBxR); + + do + { + voteOne = voteTwo; + voteTwo = HWREG16(baseAddress + OFS_TBxR); + + if(voteTwo > voteOne) + { + res = voteTwo - voteOne; + } + else if(voteOne > voteTwo) + { + res = voteOne - voteTwo; + } + else + { + res = 0; + } + } + while(res > TIMER_B_THRESHOLD); + + return(voteTwo); +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for timer_b_api +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/timer_b.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/timer_b.h new file mode 100644 index 000000000..8caa17dc8 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/timer_b.h @@ -0,0 +1,1192 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// timer_b.h - Driver for the TIMER_B Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_TIMER_B_H__ +#define __MSP430WARE_TIMER_B_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_TxB7__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "inc/hw_regaccess.h" +//***************************************************************************** +// +// The following is a parameter used for Timer_B_getCounterValue that +// determines the maximum difference in counts of the TAxR register for a +// majority vote. +// +//***************************************************************************** +#define TIMER_B_THRESHOLD 50 + +//***************************************************************************** +// +//! \brief Used in the Timer_B_outputPWM() function as the param parameter. +// +//***************************************************************************** +typedef struct Timer_B_outputPWMParam +{ + //! Selects the clock source + //! \n Valid values are: + //! - \b TIMER_B_CLOCKSOURCE_EXTERNAL_TXCLK [Default] + //! - \b TIMER_B_CLOCKSOURCE_ACLK + //! - \b TIMER_B_CLOCKSOURCE_SMCLK + //! - \b TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + uint16_t clockSource; + //! Is the divider for Clock source. + //! \n Valid values are: + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_1 [Default] + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_2 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_3 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_4 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_5 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_6 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_7 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_8 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_10 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_12 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_14 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_16 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_20 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_24 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_28 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_32 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_40 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_48 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_56 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_64 + uint16_t clockSourceDivider; + //! Selects the desired Timer_B period + uint16_t timerPeriod; + //! Selects the compare register being used. Refer to datasheet to ensure + //! the device has the compare register being used. + //! \n Valid values are: + //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0 + //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1 + //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2 + //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3 + //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4 + //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5 + //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6 + uint16_t compareRegister; + //! Specifies the output mode. + //! \n Valid values are: + //! - \b TIMER_B_OUTPUTMODE_OUTBITVALUE [Default] + //! - \b TIMER_B_OUTPUTMODE_SET + //! - \b TIMER_B_OUTPUTMODE_TOGGLE_RESET + //! - \b TIMER_B_OUTPUTMODE_SET_RESET + //! - \b TIMER_B_OUTPUTMODE_TOGGLE + //! - \b TIMER_B_OUTPUTMODE_RESET + //! - \b TIMER_B_OUTPUTMODE_TOGGLE_SET + //! - \b TIMER_B_OUTPUTMODE_RESET_SET + uint16_t compareOutputMode; + //! Specifies the dutycycle for the generated waveform + uint16_t dutyCycle; +} Timer_B_outputPWMParam; + +//***************************************************************************** +// +//! \brief Used in the Timer_B_initUpMode() function as the param parameter. +// +//***************************************************************************** +typedef struct Timer_B_initUpModeParam +{ + //! Selects the clock source + //! \n Valid values are: + //! - \b TIMER_B_CLOCKSOURCE_EXTERNAL_TXCLK [Default] + //! - \b TIMER_B_CLOCKSOURCE_ACLK + //! - \b TIMER_B_CLOCKSOURCE_SMCLK + //! - \b TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + uint16_t clockSource; + //! Is the divider for Clock source. + //! \n Valid values are: + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_1 [Default] + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_2 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_3 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_4 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_5 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_6 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_7 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_8 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_10 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_12 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_14 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_16 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_20 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_24 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_28 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_32 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_40 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_48 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_56 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_64 + uint16_t clockSourceDivider; + //! Is the specified Timer_B period. This is the value that gets written + //! into the CCR0. Limited to 16 bits[uint16_t] + uint16_t timerPeriod; + //! Is to enable or disable Timer_B interrupt + //! \n Valid values are: + //! - \b TIMER_B_TBIE_INTERRUPT_ENABLE + //! - \b TIMER_B_TBIE_INTERRUPT_DISABLE [Default] + uint16_t timerInterruptEnable_TBIE; + //! Is to enable or disable Timer_B CCR0 capture compare interrupt. + //! \n Valid values are: + //! - \b TIMER_B_CCIE_CCR0_INTERRUPT_ENABLE + //! - \b TIMER_B_CCIE_CCR0_INTERRUPT_DISABLE [Default] + uint16_t captureCompareInterruptEnable_CCR0_CCIE; + //! Decides if Timer_B clock divider, count direction, count need to be + //! reset. + //! \n Valid values are: + //! - \b TIMER_B_DO_CLEAR + //! - \b TIMER_B_SKIP_CLEAR [Default] + uint16_t timerClear; + //! Whether to start the timer immediately + bool startTimer; +} Timer_B_initUpModeParam; + +//***************************************************************************** +// +//! \brief Used in the Timer_B_initCaptureMode() function as the param +//! parameter. +// +//***************************************************************************** +typedef struct Timer_B_initCaptureModeParam +{ + //! Selects the capture register being used. Refer to datasheet to ensure + //! the device has the capture register being used. + //! \n Valid values are: + //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0 + //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1 + //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2 + //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3 + //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4 + //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5 + //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6 + uint16_t captureRegister; + //! Is the capture mode selected. + //! \n Valid values are: + //! - \b TIMER_B_CAPTUREMODE_NO_CAPTURE [Default] + //! - \b TIMER_B_CAPTUREMODE_RISING_EDGE + //! - \b TIMER_B_CAPTUREMODE_FALLING_EDGE + //! - \b TIMER_B_CAPTUREMODE_RISING_AND_FALLING_EDGE + uint16_t captureMode; + //! Decides the Input Select + //! \n Valid values are: + //! - \b TIMER_B_CAPTURE_INPUTSELECT_CCIxA [Default] + //! - \b TIMER_B_CAPTURE_INPUTSELECT_CCIxB + //! - \b TIMER_B_CAPTURE_INPUTSELECT_GND + //! - \b TIMER_B_CAPTURE_INPUTSELECT_Vcc + uint16_t captureInputSelect; + //! Decides if capture source should be synchronized with Timer_B clock + //! \n Valid values are: + //! - \b TIMER_B_CAPTURE_ASYNCHRONOUS [Default] + //! - \b TIMER_B_CAPTURE_SYNCHRONOUS + uint16_t synchronizeCaptureSource; + //! Is to enable or disable Timer_B capture compare interrupt. + //! \n Valid values are: + //! - \b TIMER_B_CAPTURECOMPARE_INTERRUPT_DISABLE [Default] + //! - \b TIMER_B_CAPTURECOMPARE_INTERRUPT_ENABLE + uint16_t captureInterruptEnable; + //! Specifies the output mode. + //! \n Valid values are: + //! - \b TIMER_B_OUTPUTMODE_OUTBITVALUE [Default] + //! - \b TIMER_B_OUTPUTMODE_SET + //! - \b TIMER_B_OUTPUTMODE_TOGGLE_RESET + //! - \b TIMER_B_OUTPUTMODE_SET_RESET + //! - \b TIMER_B_OUTPUTMODE_TOGGLE + //! - \b TIMER_B_OUTPUTMODE_RESET + //! - \b TIMER_B_OUTPUTMODE_TOGGLE_SET + //! - \b TIMER_B_OUTPUTMODE_RESET_SET + uint16_t captureOutputMode; +} Timer_B_initCaptureModeParam; + +//***************************************************************************** +// +//! \brief Used in the Timer_B_initContinuousMode() function as the param +//! parameter. +// +//***************************************************************************** +typedef struct Timer_B_initContinuousModeParam +{ + //! Selects the clock source + //! \n Valid values are: + //! - \b TIMER_B_CLOCKSOURCE_EXTERNAL_TXCLK [Default] + //! - \b TIMER_B_CLOCKSOURCE_ACLK + //! - \b TIMER_B_CLOCKSOURCE_SMCLK + //! - \b TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + uint16_t clockSource; + //! Is the divider for Clock source. + //! \n Valid values are: + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_1 [Default] + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_2 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_3 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_4 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_5 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_6 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_7 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_8 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_10 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_12 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_14 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_16 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_20 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_24 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_28 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_32 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_40 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_48 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_56 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_64 + uint16_t clockSourceDivider; + //! Is to enable or disable Timer_B interrupt + //! \n Valid values are: + //! - \b TIMER_B_TBIE_INTERRUPT_ENABLE + //! - \b TIMER_B_TBIE_INTERRUPT_DISABLE [Default] + uint16_t timerInterruptEnable_TBIE; + //! Decides if Timer_B clock divider, count direction, count need to be + //! reset. + //! \n Valid values are: + //! - \b TIMER_B_DO_CLEAR + //! - \b TIMER_B_SKIP_CLEAR [Default] + uint16_t timerClear; + //! Whether to start the timer immediately + bool startTimer; +} Timer_B_initContinuousModeParam; + +//***************************************************************************** +// +//! \brief Used in the Timer_B_initUpDownMode() function as the param +//! parameter. +// +//***************************************************************************** +typedef struct Timer_B_initUpDownModeParam +{ + //! Selects the clock source + //! \n Valid values are: + //! - \b TIMER_B_CLOCKSOURCE_EXTERNAL_TXCLK [Default] + //! - \b TIMER_B_CLOCKSOURCE_ACLK + //! - \b TIMER_B_CLOCKSOURCE_SMCLK + //! - \b TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + uint16_t clockSource; + //! Is the divider for Clock source. + //! \n Valid values are: + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_1 [Default] + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_2 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_3 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_4 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_5 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_6 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_7 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_8 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_10 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_12 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_14 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_16 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_20 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_24 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_28 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_32 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_40 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_48 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_56 + //! - \b TIMER_B_CLOCKSOURCE_DIVIDER_64 + uint16_t clockSourceDivider; + //! Is the specified Timer_B period + uint16_t timerPeriod; + //! Is to enable or disable Timer_B interrupt + //! \n Valid values are: + //! - \b TIMER_B_TBIE_INTERRUPT_ENABLE + //! - \b TIMER_B_TBIE_INTERRUPT_DISABLE [Default] + uint16_t timerInterruptEnable_TBIE; + //! Is to enable or disable Timer_B CCR0 capture compare interrupt. + //! \n Valid values are: + //! - \b TIMER_B_CCIE_CCR0_INTERRUPT_ENABLE + //! - \b TIMER_B_CCIE_CCR0_INTERRUPT_DISABLE [Default] + uint16_t captureCompareInterruptEnable_CCR0_CCIE; + //! Decides if Timer_B clock divider, count direction, count need to be + //! reset. + //! \n Valid values are: + //! - \b TIMER_B_DO_CLEAR + //! - \b TIMER_B_SKIP_CLEAR [Default] + uint16_t timerClear; + //! Whether to start the timer immediately + bool startTimer; +} Timer_B_initUpDownModeParam; + +//***************************************************************************** +// +//! \brief Used in the Timer_B_initCompareMode() function as the param +//! parameter. +// +//***************************************************************************** +typedef struct Timer_B_initCompareModeParam +{ + //! Selects the compare register being used. Refer to datasheet to ensure + //! the device has the compare register being used. + //! \n Valid values are: + //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0 + //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1 + //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2 + //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3 + //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4 + //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5 + //! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6 + uint16_t compareRegister; + //! Is to enable or disable Timer_B capture compare interrupt. + //! \n Valid values are: + //! - \b TIMER_B_CAPTURECOMPARE_INTERRUPT_DISABLE [Default] + //! - \b TIMER_B_CAPTURECOMPARE_INTERRUPT_ENABLE + uint16_t compareInterruptEnable; + //! Specifies the output mode. + //! \n Valid values are: + //! - \b TIMER_B_OUTPUTMODE_OUTBITVALUE [Default] + //! - \b TIMER_B_OUTPUTMODE_SET + //! - \b TIMER_B_OUTPUTMODE_TOGGLE_RESET + //! - \b TIMER_B_OUTPUTMODE_SET_RESET + //! - \b TIMER_B_OUTPUTMODE_TOGGLE + //! - \b TIMER_B_OUTPUTMODE_RESET + //! - \b TIMER_B_OUTPUTMODE_TOGGLE_SET + //! - \b TIMER_B_OUTPUTMODE_RESET_SET + uint16_t compareOutputMode; + //! Is the count to be compared with in compare mode + uint16_t compareValue; +} Timer_B_initCompareModeParam; + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: Timer_B_initContinuousMode(), Timer_B_initUpMode(), +// Timer_B_initUpDownMode(), and Timer_B_outputPWM(). +// +//***************************************************************************** +#define TIMER_B_CLOCKSOURCE_DIVIDER_1 0x00 +#define TIMER_B_CLOCKSOURCE_DIVIDER_2 0x08 +#define TIMER_B_CLOCKSOURCE_DIVIDER_3 0x02 +#define TIMER_B_CLOCKSOURCE_DIVIDER_4 0x10 +#define TIMER_B_CLOCKSOURCE_DIVIDER_5 0x04 +#define TIMER_B_CLOCKSOURCE_DIVIDER_6 0x05 +#define TIMER_B_CLOCKSOURCE_DIVIDER_7 0x06 +#define TIMER_B_CLOCKSOURCE_DIVIDER_8 0x18 +#define TIMER_B_CLOCKSOURCE_DIVIDER_10 0x0C +#define TIMER_B_CLOCKSOURCE_DIVIDER_12 0x0D +#define TIMER_B_CLOCKSOURCE_DIVIDER_14 0x0E +#define TIMER_B_CLOCKSOURCE_DIVIDER_16 0x0F +#define TIMER_B_CLOCKSOURCE_DIVIDER_20 0x14 +#define TIMER_B_CLOCKSOURCE_DIVIDER_24 0x15 +#define TIMER_B_CLOCKSOURCE_DIVIDER_28 0x16 +#define TIMER_B_CLOCKSOURCE_DIVIDER_32 0x17 +#define TIMER_B_CLOCKSOURCE_DIVIDER_40 0x1C +#define TIMER_B_CLOCKSOURCE_DIVIDER_48 0x1D +#define TIMER_B_CLOCKSOURCE_DIVIDER_56 0x1E +#define TIMER_B_CLOCKSOURCE_DIVIDER_64 0x1F + +//***************************************************************************** +// +// The following are values that can be passed to the timerMode parameter for +// functions: Timer_B_startCounter(). +// +//***************************************************************************** +#define TIMER_B_STOP_MODE MC_0 +#define TIMER_B_UP_MODE MC_1 +#define TIMER_B_CONTINUOUS_MODE MC_2 +#define TIMER_B_UPDOWN_MODE MC_3 + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: Timer_B_initContinuousMode(), Timer_B_initUpMode(), and +// Timer_B_initUpDownMode(). +// +//***************************************************************************** +#define TIMER_B_DO_CLEAR TBCLR +#define TIMER_B_SKIP_CLEAR 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: Timer_B_initContinuousMode(), Timer_B_initUpMode(), +// Timer_B_initUpDownMode(), and Timer_B_outputPWM(). +// +//***************************************************************************** +#define TIMER_B_CLOCKSOURCE_EXTERNAL_TXCLK TBSSEL__TACLK +#define TIMER_B_CLOCKSOURCE_ACLK TBSSEL__ACLK +#define TIMER_B_CLOCKSOURCE_SMCLK TBSSEL__SMCLK +#define TIMER_B_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK TBSSEL__INCLK + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: Timer_B_initContinuousMode(), Timer_B_initUpMode(), and +// Timer_B_initUpDownMode(). +// +//***************************************************************************** +#define TIMER_B_TBIE_INTERRUPT_ENABLE TBIE +#define TIMER_B_TBIE_INTERRUPT_DISABLE 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: Timer_B_initUpMode(), and Timer_B_initUpDownMode(). +// +//***************************************************************************** +#define TIMER_B_CCIE_CCR0_INTERRUPT_ENABLE CCIE +#define TIMER_B_CCIE_CCR0_INTERRUPT_DISABLE 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: Timer_B_initCaptureMode(), and Timer_B_initCompareMode(). +// +//***************************************************************************** +#define TIMER_B_CAPTURECOMPARE_INTERRUPT_DISABLE 0x00 +#define TIMER_B_CAPTURECOMPARE_INTERRUPT_ENABLE CCIE + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: Timer_B_initCaptureMode(). +// +//***************************************************************************** +#define TIMER_B_CAPTURE_INPUTSELECT_CCIxA CCIS_0 +#define TIMER_B_CAPTURE_INPUTSELECT_CCIxB CCIS_1 +#define TIMER_B_CAPTURE_INPUTSELECT_GND CCIS_2 +#define TIMER_B_CAPTURE_INPUTSELECT_Vcc CCIS_3 + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: Timer_B_initCaptureMode(), Timer_B_initCompareMode(), and +// Timer_B_outputPWM(). +// +//***************************************************************************** +#define TIMER_B_OUTPUTMODE_OUTBITVALUE OUTMOD_0 +#define TIMER_B_OUTPUTMODE_SET OUTMOD_1 +#define TIMER_B_OUTPUTMODE_TOGGLE_RESET OUTMOD_2 +#define TIMER_B_OUTPUTMODE_SET_RESET OUTMOD_3 +#define TIMER_B_OUTPUTMODE_TOGGLE OUTMOD_4 +#define TIMER_B_OUTPUTMODE_RESET OUTMOD_5 +#define TIMER_B_OUTPUTMODE_TOGGLE_SET OUTMOD_6 +#define TIMER_B_OUTPUTMODE_RESET_SET OUTMOD_7 + +//***************************************************************************** +// +// The following are values that can be passed to the compareRegister parameter +// for functions: Timer_B_setCompareValue(), and +// Timer_B_initCompareLatchLoadEvent(); the captureCompareRegister parameter +// for functions: Timer_B_enableCaptureCompareInterrupt(), +// Timer_B_disableCaptureCompareInterrupt(), +// Timer_B_getCaptureCompareInterruptStatus(), +// Timer_B_getSynchronizedCaptureCompareInput(), +// Timer_B_getOutputForOutputModeOutBitValue(), +// Timer_B_getCaptureCompareCount(), +// Timer_B_setOutputForOutputModeOutBitValue(), and +// Timer_B_clearCaptureCompareInterrupt(); the param parameter for functions: +// Timer_B_initCaptureMode(), Timer_B_initCompareMode(), and +// Timer_B_outputPWM(). +// +//***************************************************************************** +#define TIMER_B_CAPTURECOMPARE_REGISTER_0 0x02 +#define TIMER_B_CAPTURECOMPARE_REGISTER_1 0x04 +#define TIMER_B_CAPTURECOMPARE_REGISTER_2 0x06 +#define TIMER_B_CAPTURECOMPARE_REGISTER_3 0x08 +#define TIMER_B_CAPTURECOMPARE_REGISTER_4 0x0A +#define TIMER_B_CAPTURECOMPARE_REGISTER_5 0x0C +#define TIMER_B_CAPTURECOMPARE_REGISTER_6 0x0E + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: Timer_B_initCaptureMode(). +// +//***************************************************************************** +#define TIMER_B_CAPTUREMODE_NO_CAPTURE CM_0 +#define TIMER_B_CAPTUREMODE_RISING_EDGE CM_1 +#define TIMER_B_CAPTUREMODE_FALLING_EDGE CM_2 +#define TIMER_B_CAPTUREMODE_RISING_AND_FALLING_EDGE CM_3 + +//***************************************************************************** +// +// The following are values that can be passed to the param parameter for +// functions: Timer_B_initCaptureMode(). +// +//***************************************************************************** +#define TIMER_B_CAPTURE_ASYNCHRONOUS 0x00 +#define TIMER_B_CAPTURE_SYNCHRONOUS SCS + +//***************************************************************************** +// +// The following are values that can be passed to the mask parameter for +// functions: Timer_B_getCaptureCompareInterruptStatus() as well as returned by +// the Timer_B_getCaptureCompareInterruptStatus() function. +// +//***************************************************************************** +#define TIMER_B_CAPTURE_OVERFLOW COV +#define TIMER_B_CAPTURECOMPARE_INTERRUPT_FLAG CCIFG + +//***************************************************************************** +// +// The following are values that can be passed to the synchronized parameter +// for functions: Timer_B_getSynchronizedCaptureCompareInput(). +// +//***************************************************************************** +#define TIMER_B_READ_SYNCHRONIZED_CAPTURECOMPAREINPUT SCCI +#define TIMER_B_READ_CAPTURE_COMPARE_INPUT CCI + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the Timer_B_getSynchronizedCaptureCompareInput() +// function. +// +//***************************************************************************** +#define TIMER_B_CAPTURECOMPARE_INPUT_HIGH 0x01 +#define TIMER_B_CAPTURECOMPARE_INPUT_LOW 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the outputModeOutBitValue +// parameter for functions: Timer_B_setOutputForOutputModeOutBitValue() as well +// as returned by the Timer_B_getOutputForOutputModeOutBitValue() function. +// +//***************************************************************************** +#define TIMER_B_OUTPUTMODE_OUTBITVALUE_HIGH OUT +#define TIMER_B_OUTPUTMODE_OUTBITVALUE_LOW 0x00 + +//***************************************************************************** +// +// The following are values that can be passed to the counterLength parameter +// for functions: Timer_B_selectCounterLength(). +// +//***************************************************************************** +#define TIMER_B_COUNTER_16BIT CNTL_3 +#define TIMER_B_COUNTER_12BIT CNTL_2 +#define TIMER_B_COUNTER_10BIT CNTL_1 +#define TIMER_B_COUNTER_8BIT CNTL_0 + +//***************************************************************************** +// +// The following are values that can be passed to the groupLatch parameter for +// functions: Timer_B_selectLatchingGroup(). +// +//***************************************************************************** +#define TIMER_B_GROUP_NONE TBCLGRP_0 +#define TIMER_B_GROUP_CL12_CL23_CL56 TBCLGRP_1 +#define TIMER_B_GROUP_CL123_CL456 TBCLGRP_2 +#define TIMER_B_GROUP_ALL TBCLGRP_3 + +//***************************************************************************** +// +// The following are values that can be passed to the compareLatchLoadEvent +// parameter for functions: Timer_B_initCompareLatchLoadEvent(). +// +//***************************************************************************** +#define TIMER_B_LATCH_ON_WRITE_TO_TBxCCRn_COMPARE_REGISTER CLLD_0 +#define TIMER_B_LATCH_WHEN_COUNTER_COUNTS_TO_0_IN_UP_OR_CONT_MODE CLLD_1 +#define TIMER_B_LATCH_WHEN_COUNTER_COUNTS_TO_0_IN_UPDOWN_MODE CLLD_2 +#define TIMER_B_LATCH_WHEN_COUNTER_COUNTS_TO_CURRENT_COMPARE_LATCH_VALUE CLLD_3 + +//***************************************************************************** +// +// The following are values that can be passed toThe following are values that +// can be returned by the Timer_B_getInterruptStatus() function. +// +//***************************************************************************** +#define TIMER_B_INTERRUPT_NOT_PENDING 0x00 +#define TIMER_B_INTERRUPT_PENDING 0x01 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Starts Timer_B counter +//! +//! This function assumes that the timer has been previously configured using +//! Timer_B_configureContinuousMode, Timer_B_configureUpMode or +//! Timer_B_configureUpDownMode. +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param timerMode selects the mode of the timer +//! Valid values are: +//! - \b TIMER_B_STOP_MODE +//! - \b TIMER_B_UP_MODE +//! - \b TIMER_B_CONTINUOUS_MODE [Default] +//! - \b TIMER_B_UPDOWN_MODE +//! +//! Modified bits of \b TBxCTL register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_B_startCounter(uint16_t baseAddress, + uint16_t timerMode); + +//***************************************************************************** +// +//! \brief Configures Timer_B in continuous mode. +//! +//! This API does not start the timer. Timer needs to be started when required +//! using the Timer_B_startCounter API. +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param param is the pointer to struct for continuous mode initialization. +//! +//! Modified bits of \b TBxCTL register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_B_initContinuousMode(uint16_t baseAddress, + Timer_B_initContinuousModeParam *param); + +//***************************************************************************** +// +//! \brief Configures Timer_B in up mode. +//! +//! This API does not start the timer. Timer needs to be started when required +//! using the Timer_B_startCounter API. +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param param is the pointer to struct for up mode initialization. +//! +//! Modified bits of \b TBxCTL register, bits of \b TBxCCTL0 register and bits +//! of \b TBxCCR0 register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_B_initUpMode(uint16_t baseAddress, + Timer_B_initUpModeParam *param); + +//***************************************************************************** +// +//! \brief Configures Timer_B in up down mode. +//! +//! This API does not start the timer. Timer needs to be started when required +//! using the Timer_B_startCounter API. +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param param is the pointer to struct for up-down mode initialization. +//! +//! Modified bits of \b TBxCTL register, bits of \b TBxCCTL0 register and bits +//! of \b TBxCCR0 register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_B_initUpDownMode(uint16_t baseAddress, + Timer_B_initUpDownModeParam *param); + +//***************************************************************************** +// +//! \brief Initializes Capture Mode +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param param is the pointer to struct for capture mode initialization. +//! +//! Modified bits of \b TBxCCTLn register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_B_initCaptureMode(uint16_t baseAddress, + Timer_B_initCaptureModeParam *param); + +//***************************************************************************** +// +//! \brief Initializes Compare Mode +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param param is the pointer to struct for compare mode initialization. +//! +//! Modified bits of \b TBxCCTLn register and bits of \b TBxCCRn register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_B_initCompareMode(uint16_t baseAddress, + Timer_B_initCompareModeParam *param); + +//***************************************************************************** +// +//! \brief Enable Timer_B interrupt +//! +//! Enables Timer_B interrupt. Does not clear interrupt flags. +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! +//! Modified bits of \b TBxCTL register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_B_enableInterrupt(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Disable Timer_B interrupt +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! +//! Modified bits of \b TBxCTL register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_B_disableInterrupt(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Get Timer_B interrupt status +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! +//! \return One of the following: +//! - \b Timer_B_INTERRUPT_NOT_PENDING +//! - \b Timer_B_INTERRUPT_PENDING +//! \n indicating the status of the Timer_B interrupt +// +//***************************************************************************** +extern uint32_t Timer_B_getInterruptStatus(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Enable capture compare interrupt +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param captureCompareRegister selects the capture compare register being +//! used. Refer to datasheet to ensure the device has the capture +//! compare register being used. +//! Valid values are: +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6 +//! +//! Modified bits of \b TBxCCTLn register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_B_enableCaptureCompareInterrupt(uint16_t baseAddress, + uint16_t captureCompareRegister); + +//***************************************************************************** +// +//! \brief Disable capture compare interrupt +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param captureCompareRegister selects the capture compare register being +//! used. Refer to datasheet to ensure the device has the capture +//! compare register being used. +//! Valid values are: +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6 +//! +//! Modified bits of \b TBxCCTLn register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_B_disableCaptureCompareInterrupt(uint16_t baseAddress, + uint16_t captureCompareRegister); + +//***************************************************************************** +// +//! \brief Return capture compare interrupt status +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param captureCompareRegister selects the capture compare register being +//! used. Refer to datasheet to ensure the device has the capture +//! compare register being used. +//! Valid values are: +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6 +//! \param mask is the mask for the interrupt status +//! Mask value is the logical OR of any of the following: +//! - \b TIMER_B_CAPTURE_OVERFLOW +//! - \b TIMER_B_CAPTURECOMPARE_INTERRUPT_FLAG +//! +//! \return Logical OR of any of the following: +//! - \b Timer_B_CAPTURE_OVERFLOW +//! - \b Timer_B_CAPTURECOMPARE_INTERRUPT_FLAG +//! \n indicating the status of the masked interrupts +// +//***************************************************************************** +extern uint32_t Timer_B_getCaptureCompareInterruptStatus(uint16_t baseAddress, + uint16_t captureCompareRegister, + uint16_t mask); + +//***************************************************************************** +// +//! \brief Reset/Clear the Timer_B clock divider, count direction, count +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! +//! Modified bits of \b TBxCTL register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_B_clear(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Get synchronized capturecompare input +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param captureCompareRegister selects the capture compare register being +//! used. Refer to datasheet to ensure the device has the capture +//! compare register being used. +//! Valid values are: +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6 +//! \param synchronized selects the type of capture compare input +//! Valid values are: +//! - \b TIMER_B_READ_SYNCHRONIZED_CAPTURECOMPAREINPUT +//! - \b TIMER_B_READ_CAPTURE_COMPARE_INPUT +//! +//! \return One of the following: +//! - \b Timer_B_CAPTURECOMPARE_INPUT_HIGH +//! - \b Timer_B_CAPTURECOMPARE_INPUT_LOW +// +//***************************************************************************** +extern uint8_t Timer_B_getSynchronizedCaptureCompareInput(uint16_t baseAddress, + uint16_t captureCompareRegister, + uint16_t synchronized); + +//***************************************************************************** +// +//! \brief Get output bit for output mode +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param captureCompareRegister selects the capture compare register being +//! used. Refer to datasheet to ensure the device has the capture +//! compare register being used. +//! Valid values are: +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6 +//! +//! \return One of the following: +//! - \b Timer_B_OUTPUTMODE_OUTBITVALUE_HIGH +//! - \b Timer_B_OUTPUTMODE_OUTBITVALUE_LOW +// +//***************************************************************************** +extern uint8_t Timer_B_getOutputForOutputModeOutBitValue(uint16_t baseAddress, + uint16_t captureCompareRegister); + +//***************************************************************************** +// +//! \brief Get current capturecompare count +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param captureCompareRegister selects the capture compare register being +//! used. Refer to datasheet to ensure the device has the capture +//! compare register being used. +//! Valid values are: +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6 +//! +//! \return Current count as uint16_t +// +//***************************************************************************** +extern uint16_t Timer_B_getCaptureCompareCount(uint16_t baseAddress, + uint16_t captureCompareRegister); + +//***************************************************************************** +// +//! \brief Set output bit for output mode +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param captureCompareRegister selects the capture compare register being +//! used. Refer to datasheet to ensure the device has the capture +//! compare register being used. +//! Valid values are: +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6 +//! \param outputModeOutBitValue the value to be set for out bit +//! Valid values are: +//! - \b TIMER_B_OUTPUTMODE_OUTBITVALUE_HIGH +//! - \b TIMER_B_OUTPUTMODE_OUTBITVALUE_LOW +//! +//! Modified bits of \b TBxCCTLn register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_B_setOutputForOutputModeOutBitValue(uint16_t baseAddress, + uint16_t captureCompareRegister, + uint8_t outputModeOutBitValue); + +//***************************************************************************** +// +//! \brief Generate a PWM with Timer_B running in up mode +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param param is the pointer to struct for PWM configuration. +//! +//! Modified bits of \b TBxCCTLn register, bits of \b TBxCTL register, bits of +//! \b TBxCCTL0 register and bits of \b TBxCCR0 register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_B_outputPWM(uint16_t baseAddress, + Timer_B_outputPWMParam *param); + +//***************************************************************************** +// +//! \brief Stops the Timer_B +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! +//! Modified bits of \b TBxCTL register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_B_stop(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Sets the value of the capture-compare register +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param compareRegister selects the compare register being used. Refer to +//! datasheet to ensure the device has the compare register being used. +//! Valid values are: +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6 +//! \param compareValue is the count to be compared with in compare mode +//! +//! Modified bits of \b TBxCCRn register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_B_setCompareValue(uint16_t baseAddress, + uint16_t compareRegister, + uint16_t compareValue); + +//***************************************************************************** +// +//! \brief Clears the Timer_B TBIFG interrupt flag +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! +//! Modified bits are \b TBIFG of \b TBxCTL register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_B_clearTimerInterrupt(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Clears the capture-compare interrupt flag +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param captureCompareRegister selects the capture compare register being +//! used. Refer to datasheet to ensure the device has the capture +//! compare register being used. +//! Valid values are: +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6 +//! +//! Modified bits are \b CCIFG of \b TBxCCTLn register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_B_clearCaptureCompareInterrupt(uint16_t baseAddress, + uint16_t captureCompareRegister); + +//***************************************************************************** +// +//! \brief Selects Timer_B counter length +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param counterLength selects the value of counter length. +//! Valid values are: +//! - \b TIMER_B_COUNTER_16BIT [Default] +//! - \b TIMER_B_COUNTER_12BIT +//! - \b TIMER_B_COUNTER_10BIT +//! - \b TIMER_B_COUNTER_8BIT +//! +//! Modified bits are \b CNTL of \b TBxCTL register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_B_selectCounterLength(uint16_t baseAddress, + uint16_t counterLength); + +//***************************************************************************** +// +//! \brief Selects Timer_B Latching Group +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param groupLatch selects the latching group. +//! Valid values are: +//! - \b TIMER_B_GROUP_NONE [Default] +//! - \b TIMER_B_GROUP_CL12_CL23_CL56 +//! - \b TIMER_B_GROUP_CL123_CL456 +//! - \b TIMER_B_GROUP_ALL +//! +//! Modified bits are \b TBCLGRP of \b TBxCTL register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_B_selectLatchingGroup(uint16_t baseAddress, + uint16_t groupLatch); + +//***************************************************************************** +// +//! \brief Selects Compare Latch Load Event +//! +//! \param baseAddress is the base address of the TIMER_B module. +//! \param compareRegister selects the compare register being used. Refer to +//! datasheet to ensure the device has the compare register being used. +//! Valid values are: +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_0 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_1 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_2 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_3 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_4 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_5 +//! - \b TIMER_B_CAPTURECOMPARE_REGISTER_6 +//! \param compareLatchLoadEvent selects the latch load event +//! Valid values are: +//! - \b TIMER_B_LATCH_ON_WRITE_TO_TBxCCRn_COMPARE_REGISTER [Default] +//! - \b TIMER_B_LATCH_WHEN_COUNTER_COUNTS_TO_0_IN_UP_OR_CONT_MODE +//! - \b TIMER_B_LATCH_WHEN_COUNTER_COUNTS_TO_0_IN_UPDOWN_MODE +//! - \b +//! TIMER_B_LATCH_WHEN_COUNTER_COUNTS_TO_CURRENT_COMPARE_LATCH_VALUE +//! +//! Modified bits are \b CLLD of \b TBxCCTLn register. +//! +//! \return None +// +//***************************************************************************** +extern void Timer_B_initCompareLatchLoadEvent(uint16_t baseAddress, + uint16_t compareRegister, + uint16_t compareLatchLoadEvent); + +//***************************************************************************** +// +//! \brief Reads the current timer count value +//! +//! Reads the current count value of the timer. There is a majority vote system +//! in place to confirm an accurate value is returned. The Timer_B_THRESHOLD +//! #define in the associated header file can be modified so that the votes +//! must be closer together for a consensus to occur. +//! +//! \param baseAddress is the base address of the Timer module. +//! +//! \return Majority vote of timer count value +// +//***************************************************************************** +extern uint16_t Timer_B_getCounterValue(uint16_t baseAddress); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_TIMER_B_H__ diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/tlv.c b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/tlv.c new file mode 100644 index 000000000..7ccf84a11 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/tlv.c @@ -0,0 +1,240 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// tlv.c - Driver for the tlv Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup tlv_api tlv +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_TLV__ +#include "tlv.h" + +#include + +void TLV_getInfo(uint8_t tag, + uint8_t instance, + uint8_t *length, + uint16_t **data_address) +{ + // TLV Structure Start Address + char *TLV_address = (char *)TLV_START; + + while((TLV_address < (char *)TLV_END) + && ((*TLV_address != tag) || instance) // check for tag and instance + && (*TLV_address != TLV_TAGEND)) // do range check first + { + if(*TLV_address == tag) + { + // repeat till requested instance is reached + instance--; + } + // add (Current TAG address + LENGTH) + 2 + TLV_address += *(TLV_address + 1) + 2; + } + + // Check if Tag match happened.. + if(*TLV_address == tag) + { + // Return length = Address + 1 + *length = *(TLV_address + 1); + // Return address of first data/value info = Address + 2 + *data_address = (uint16_t *)(TLV_address + 2); + } + // If there was no tag match and the end of TLV structure was reached.. + else + { + // Return 0 for TAG not found + *length = 0; + // Return 0 for TAG not found + *data_address = 0; + } +} + +uint16_t TLV_getDeviceType() +{ + uint16_t *pDeviceType = (uint16_t *)TLV_DEVICE_ID_0; + // Return Value from TLV Table + return(pDeviceType[0]); +} + +uint16_t TLV_getMemory(uint8_t instance) +{ + uint8_t *pPDTAG; + uint8_t bPDTAG_bytes; + uint16_t count; + + // set tag for word access comparison + instance *= 2; + + // TLV access Function Call + // Get Peripheral data pointer + TLV_getInfo(TLV_PDTAG, + 0, + &bPDTAG_bytes, + (uint16_t **)&pPDTAG + ); + + for(count = 0; count <= instance; count += 2) + { + if(pPDTAG[count] == 0) + { + // Return 0 if end reached + return(0); + } + if(count == instance) + { + return (pPDTAG[count] | pPDTAG[count + 1] << 8); + } + } + + // Return 0: not found + return(0); +} + +uint16_t TLV_getPeripheral(uint8_t tag, + uint8_t instance) +{ + uint8_t *pPDTAG; + uint8_t bPDTAG_bytes; + uint16_t count = 0; + uint16_t pcount = 0; + + // Get Peripheral data pointer + TLV_getInfo(TLV_PDTAG, + 0, + &bPDTAG_bytes, + (uint16_t **)&pPDTAG + ); + + // read memory configuration from TLV to get offset for Peripherals + while(TLV_getMemory(count)) + { + count++; + } + // get number of Peripheral entries + pcount = pPDTAG[count * 2 + 1]; + // inc count to first Periperal + count++; + // adjust point to first address of Peripheral + pPDTAG += count * 2; + // set counter back to 0 + count = 0; + // align pcount for work comparision + pcount *= 2; + + // TLV access Function Call + for(count = 0; count <= pcount; count += 2) + { + if(pPDTAG[count + 1] == tag) + { + // test if required Peripheral is found + if(instance > 0) + { + // test if required instance is found + instance--; + } + else + { + // Return found data + return (pPDTAG[count] | pPDTAG[count + 1] << 8); + } + } + } + + // Return 0: not found + return(0); +} + +uint8_t TLV_getInterrupt(uint8_t tag) +{ + uint8_t *pPDTAG; + uint8_t bPDTAG_bytes; + uint16_t count = 0; + uint16_t pcount = 0; + + // Get Peripheral data pointer + TLV_getInfo(TLV_PDTAG, + 0, + &bPDTAG_bytes, + (uint16_t **)&pPDTAG + ); + + // read memory configuration from TLV to get offset for Peripherals + while(TLV_getMemory(count)) + { + count++; + } + + pcount = pPDTAG[count * 2 + 1]; + // inc count to first Periperal + count++; + // adjust point to first address of Peripheral + pPDTAG += (pcount + count) * 2; + // set counter back to 0 + count = 0; + + // TLV access Function Call + for(count = 0; count <= tag; count += 2) + { + if(pPDTAG[count] == 0) + { + // Return 0: not found/end of table + return(0); + } + if(count == tag) + { + // Return found data + return (pPDTAG[count]); + } + } + + // Return 0: not found + return(0); +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for tlv_api +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/tlv.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/tlv.h new file mode 100644 index 000000000..5c84f6965 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/tlv.h @@ -0,0 +1,439 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// tlv.h - Driver for the TLV Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_TLV_H__ +#define __MSP430WARE_TLV_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_TLV__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "inc/hw_regaccess.h" +//****************************************************************************** +// +// TLV Data Types +// +//****************************************************************************** +struct s_TLV_Die_Record +{ + uint32_t wafer_id; + uint16_t die_x_position; + uint16_t die_y_position; + uint16_t test_results; +}; + +struct s_TLV_ADC_Cal_Data +{ + uint16_t adc_gain_factor; + int16_t adc_offset; + uint16_t adc_ref15_30_temp; + uint16_t adc_ref15_85_temp; + uint16_t adc_ref20_30_temp; + uint16_t adc_ref20_85_temp; + uint16_t adc_ref25_30_temp; + uint16_t adc_ref25_85_temp; +}; + +struct s_TLV_Timer_D_Cal_Data +{ + uint16_t TDH0CTL1_64; + uint16_t TDH0CTL1_128; + uint16_t TDH0CTL1_200; + uint16_t TDH0CTL1_256; +}; + +struct s_TLV_REF_Cal_Data +{ + uint16_t ref_ref15; + uint16_t ref_ref20; + uint16_t ref_ref25; +}; + +struct s_Peripheral_Memory_Data +{ + uint16_t memory_1; + uint16_t memory_2; + uint16_t memory_3; + uint16_t memory_4; +}; + +//***************************************************************************** +// +// The following are values that can be passed to the tag parameter for +// functions: TLV_getInfo(). +// +//***************************************************************************** +#define TLV_TAG_LDTAG TLV_LDTAG +#define TLV_TAG_PDTAG TLV_PDTAG +#define TLV_TAG_Reserved3 TLV_Reserved3 +#define TLV_TAG_Reserved4 TLV_Reserved4 +#define TLV_TAG_BLANK TLV_BLANK +#define TLV_TAG_Reserved6 TLV_Reserved6 +#define TLV_TAG_Reserved7 TLV_Reserved7 +#define TLV_TAG_TAGEND TLV_TAGEND +#define TLV_TAG_TAGEXT TLV_TAGEXT +#define TLV_TAG_TIMER_D_CAL TLV_TIMERDCAL +#define TLV_DEVICE_ID_0 0x1A04 +#define TLV_DEVICE_ID_1 0x1A05 +#define TLV_TAG_DIERECORD TLV_DIERECORD +#define TLV_TAG_ADCCAL TLV_ADCCAL +#define TLV_TAG_ADC12CAL TLV_ADC12CAL +#define TLV_TAG_ADC10CAL TLV_ADC10CAL +#define TLV_TAG_REFCAL TLV_REFCAL + +//***************************************************************************** +// +// The following are values that can be passed to the tag parameter for +// functions: TLV_getPeripheral(). +// +//***************************************************************************** +#define TLV_PID_NO_MODULE (0x00) +#define TLV_PID_PORTMAPPING (0x10) +#define TLV_PID_MSP430CPUXV2 (0x23) +#define TLV_PID_JTAG (0x09) +#define TLV_PID_SBW (0x0F) +#define TLV_PID_EEM_XS (0x02) +#define TLV_PID_EEM_S (0x03) +#define TLV_PID_EEM_M (0x04) +#define TLV_PID_EEM_L (0x05) +#define TLV_PID_PMM (0x30) +#define TLV_PID_PMM_FR (0x32) +#define TLV_PID_FCTL (0x39) +#define TLV_PID_CRC16 (0x3C) +#define TLV_PID_CRC16_RB (0x3D) +#define TLV_PID_WDT_A (0x40) +#define TLV_PID_SFR (0x41) +#define TLV_PID_SYS (0x42) +#define TLV_PID_RAMCTL (0x44) +#define TLV_PID_DMA_1 (0x46) +#define TLV_PID_DMA_3 (0x47) +#define TLV_PID_UCS (0x48) +#define TLV_PID_DMA_6 (0x4A) +#define TLV_PID_DMA_2 (0x4B) +#define TLV_PID_PORT1_2 (0x51) +#define TLV_PID_PORT3_4 (0x52) +#define TLV_PID_PORT5_6 (0x53) +#define TLV_PID_PORT7_8 (0x54) +#define TLV_PID_PORT9_10 (0x55) +#define TLV_PID_PORT11_12 (0x56) +#define TLV_PID_PORTU (0x5E) +#define TLV_PID_PORTJ (0x5F) +#define TLV_PID_TA2 (0x60) +#define TLV_PID_TA3 (0x61) +#define TLV_PID_TA5 (0x62) +#define TLV_PID_TA7 (0x63) +#define TLV_PID_TB3 (0x65) +#define TLV_PID_TB5 (0x66) +#define TLV_PID_TB7 (0x67) +#define TLV_PID_RTC (0x68) +#define TLV_PID_BT_RTC (0x69) +#define TLV_PID_BBS (0x6A) +#define TLV_PID_RTC_B (0x6B) +#define TLV_PID_TD2 (0x6C) +#define TLV_PID_TD3 (0x6D) +#define TLV_PID_TD5 (0x6E) +#define TLV_PID_TD7 (0x6F) +#define TLV_PID_TEC (0x70) +#define TLV_PID_RTC_C (0x71) +#define TLV_PID_AES (0x80) +#define TLV_PID_MPY16 (0x84) +#define TLV_PID_MPY32 (0x85) +#define TLV_PID_MPU (0x86) +#define TLV_PID_USCI_AB (0x90) +#define TLV_PID_USCI_A (0x91) +#define TLV_PID_USCI_B (0x92) +#define TLV_PID_EUSCI_A (0x94) +#define TLV_PID_EUSCI_B (0x95) +#define TLV_PID_REF (0xA0) +#define TLV_PID_COMP_B (0xA8) +#define TLV_PID_COMP_D (0xA9) +#define TLV_PID_USB (0x98) +#define TLV_PID_LCD_B (0xB1) +#define TLV_PID_LCD_C (0xB2) +#define TLV_PID_DAC12_A (0xC0) +#define TLV_PID_SD16_B_1 (0xC8) +#define TLV_PID_SD16_B_2 (0xC9) +#define TLV_PID_SD16_B_3 (0xCA) +#define TLV_PID_SD16_B_4 (0xCB) +#define TLV_PID_SD16_B_5 (0xCC) +#define TLV_PID_SD16_B_6 (0xCD) +#define TLV_PID_SD16_B_7 (0xCE) +#define TLV_PID_SD16_B_8 (0xCF) +#define TLV_PID_ADC12_A (0xD1) +#define TLV_PID_ADC10_A (0xD3) +#define TLV_PID_ADC10_B (0xD4) +#define TLV_PID_SD16_A (0xD8) +#define TLV_PID_TI_BSL (0xFC) + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Gets TLV Info +//! +//! The TLV structure uses a tag or base address to identify segments of the +//! table where information is stored. Some examples of TLV tags are Peripheral +//! Descriptor, Interrupts, Info Block and Die Record. This function retrieves +//! the value of a tag and the length of the tag. +//! +//! \param tag represents the tag for which the information needs to be +//! retrieved. +//! Valid values are: +//! - \b TLV_TAG_LDTAG +//! - \b TLV_TAG_PDTAG +//! - \b TLV_TAG_Reserved3 +//! - \b TLV_TAG_Reserved4 +//! - \b TLV_TAG_BLANK +//! - \b TLV_TAG_Reserved6 +//! - \b TLV_TAG_Reserved7 +//! - \b TLV_TAG_TAGEND +//! - \b TLV_TAG_TAGEXT +//! - \b TLV_TAG_TIMER_D_CAL +//! - \b TLV_DEVICE_ID_0 +//! - \b TLV_DEVICE_ID_1 +//! - \b TLV_TAG_DIERECORD +//! - \b TLV_TAG_ADCCAL +//! - \b TLV_TAG_ADC12CAL +//! - \b TLV_TAG_ADC10CAL +//! - \b TLV_TAG_REFCAL +//! \param instance In some cases a specific tag may have more than one +//! instance. For example there may be multiple instances of timer +//! calibration data present under a single Timer Cal tag. This variable +//! specifies the instance for which information is to be retrieved (0, +//! 1, etc.). When only one instance exists; 0 is passed. +//! \param length Acts as a return through indirect reference. The function +//! retrieves the value of the TLV tag length. This value is pointed to +//! by *length and can be used by the application level once the +//! function is called. If the specified tag is not found then the +//! pointer is null 0. +//! \param data_address acts as a return through indirect reference. Once the +//! function is called data_address points to the pointer that holds the +//! value retrieved from the specified TLV tag. If the specified tag is +//! not found then the pointer is null 0. +//! +//! \return None +// +//***************************************************************************** +extern void TLV_getInfo(uint8_t tag, + uint8_t instance, + uint8_t *length, + uint16_t **data_address); + +//***************************************************************************** +// +//! \brief Retrieves the unique device ID from the TLV structure. +//! +//! +//! \return The device ID is returned as type uint16_t. +// +//***************************************************************************** +extern uint16_t TLV_getDeviceType(void); + +//***************************************************************************** +// +//! \brief Gets memory information +//! +//! The Peripheral Descriptor tag is split into two portions a list of the +//! available flash memory blocks followed by a list of available peripherals. +//! This function is used to parse through the first portion and calculate the +//! total flash memory available in a device. The typical usage is to call the +//! TLV_getMemory which returns a non-zero value until the entire memory list +//! has been parsed. When a zero is returned, it indicates that all the memory +//! blocks have been counted and the next address holds the beginning of the +//! device peripheral list. +//! +//! \param instance In some cases a specific tag may have more than one +//! instance. This variable specifies the instance for which information +//! is to be retrieved (0, 1 etc). When only one instance exists; 0 is +//! passed. +//! +//! \return The returned value is zero if the end of the memory list is +//! reached. +// +//***************************************************************************** +extern uint16_t TLV_getMemory(uint8_t instance); + +//***************************************************************************** +// +//! \brief Gets peripheral information from the TLV +//! +//! he Peripheral Descriptor tag is split into two portions a list of the +//! available flash memory blocks followed by a list of available peripherals. +//! This function is used to parse through the second portion and can be used +//! to check if a specific peripheral is present in a device. The function +//! calls TLV_getPeripheral() recursively until the end of the memory list and +//! consequently the beginning of the peripheral list is reached. < +//! +//! \param tag represents represents the tag for a specific peripheral for +//! which the information needs to be retrieved. In the header file tlv. +//! h specific peripheral tags are pre-defined, for example USCIA_B and +//! TA0 are defined as TLV_PID_USCI_AB and TLV_PID_TA2 respectively. +//! Valid values are: +//! - \b TLV_PID_NO_MODULE - No Module +//! - \b TLV_PID_PORTMAPPING - Port Mapping +//! - \b TLV_PID_MSP430CPUXV2 - MSP430CPUXV2 +//! - \b TLV_PID_JTAG - JTAG +//! - \b TLV_PID_SBW - SBW +//! - \b TLV_PID_EEM_XS - EEM X-Small +//! - \b TLV_PID_EEM_S - EEM Small +//! - \b TLV_PID_EEM_M - EEM Medium +//! - \b TLV_PID_EEM_L - EEM Large +//! - \b TLV_PID_PMM - PMM +//! - \b TLV_PID_PMM_FR - PMM FRAM +//! - \b TLV_PID_FCTL - Flash +//! - \b TLV_PID_CRC16 - CRC16 +//! - \b TLV_PID_CRC16_RB - CRC16 Reverse +//! - \b TLV_PID_WDT_A - WDT_A +//! - \b TLV_PID_SFR - SFR +//! - \b TLV_PID_SYS - SYS +//! - \b TLV_PID_RAMCTL - RAMCTL +//! - \b TLV_PID_DMA_1 - DMA 1 +//! - \b TLV_PID_DMA_3 - DMA 3 +//! - \b TLV_PID_UCS - UCS +//! - \b TLV_PID_DMA_6 - DMA 6 +//! - \b TLV_PID_DMA_2 - DMA 2 +//! - \b TLV_PID_PORT1_2 - Port 1 + 2 / A +//! - \b TLV_PID_PORT3_4 - Port 3 + 4 / B +//! - \b TLV_PID_PORT5_6 - Port 5 + 6 / C +//! - \b TLV_PID_PORT7_8 - Port 7 + 8 / D +//! - \b TLV_PID_PORT9_10 - Port 9 + 10 / E +//! - \b TLV_PID_PORT11_12 - Port 11 + 12 / F +//! - \b TLV_PID_PORTU - Port U +//! - \b TLV_PID_PORTJ - Port J +//! - \b TLV_PID_TA2 - Timer A2 +//! - \b TLV_PID_TA3 - Timer A1 +//! - \b TLV_PID_TA5 - Timer A5 +//! - \b TLV_PID_TA7 - Timer A7 +//! - \b TLV_PID_TB3 - Timer B3 +//! - \b TLV_PID_TB5 - Timer B5 +//! - \b TLV_PID_TB7 - Timer B7 +//! - \b TLV_PID_RTC - RTC +//! - \b TLV_PID_BT_RTC - BT + RTC +//! - \b TLV_PID_BBS - Battery Backup Switch +//! - \b TLV_PID_RTC_B - RTC_B +//! - \b TLV_PID_TD2 - Timer D2 +//! - \b TLV_PID_TD3 - Timer D1 +//! - \b TLV_PID_TD5 - Timer D5 +//! - \b TLV_PID_TD7 - Timer D7 +//! - \b TLV_PID_TEC - Timer Event Control +//! - \b TLV_PID_RTC_C - RTC_C +//! - \b TLV_PID_AES - AES +//! - \b TLV_PID_MPY16 - MPY16 +//! - \b TLV_PID_MPY32 - MPY32 +//! - \b TLV_PID_MPU - MPU +//! - \b TLV_PID_USCI_AB - USCI_AB +//! - \b TLV_PID_USCI_A - USCI_A +//! - \b TLV_PID_USCI_B - USCI_B +//! - \b TLV_PID_EUSCI_A - eUSCI_A +//! - \b TLV_PID_EUSCI_B - eUSCI_B +//! - \b TLV_PID_REF - Shared Reference +//! - \b TLV_PID_COMP_B - COMP_B +//! - \b TLV_PID_COMP_D - COMP_D +//! - \b TLV_PID_USB - USB +//! - \b TLV_PID_LCD_B - LCD_B +//! - \b TLV_PID_LCD_C - LCD_C +//! - \b TLV_PID_DAC12_A - DAC12_A +//! - \b TLV_PID_SD16_B_1 - SD16_B 1 Channel +//! - \b TLV_PID_SD16_B_2 - SD16_B 2 Channel +//! - \b TLV_PID_SD16_B_3 - SD16_B 3 Channel +//! - \b TLV_PID_SD16_B_4 - SD16_B 4 Channel +//! - \b TLV_PID_SD16_B_5 - SD16_B 5 Channel +//! - \b TLV_PID_SD16_B_6 - SD16_B 6 Channel +//! - \b TLV_PID_SD16_B_7 - SD16_B 7 Channel +//! - \b TLV_PID_SD16_B_8 - SD16_B 8 Channel +//! - \b TLV_PID_ADC12_A - ADC12_A +//! - \b TLV_PID_ADC10_A - ADC10_A +//! - \b TLV_PID_ADC10_B - ADC10_B +//! - \b TLV_PID_SD16_A - SD16_A +//! - \b TLV_PID_TI_BSL - BSL +//! \param instance In some cases a specific tag may have more than one +//! instance. For example a device may have more than a single USCI +//! module, each of which is defined by an instance number 0, 1, 2, etc. +//! When only one instance exists; 0 is passed. +//! +//! \return The returned value is zero if the specified tag value (peripheral) +//! is not available in the device. +// +//***************************************************************************** +extern uint16_t TLV_getPeripheral(uint8_t tag, + uint8_t instance); + +//***************************************************************************** +// +//! \brief Get interrupt information from the TLV +//! +//! This function is used to retrieve information on available interrupt +//! vectors. It allows the user to check if a specific interrupt vector is +//! defined in a given device. +//! +//! \param tag represents the tag for the interrupt vector. Interrupt vector +//! tags number from 0 to N depending on the number of available +//! interrupts. Refer to the device datasheet for a list of available +//! interrupts. +//! +//! \return The returned value is zero is the specified interrupt vector is not +//! defined. +// +//***************************************************************************** +extern uint8_t TLV_getInterrupt(uint8_t tag); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_TLV_H__ diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/wdt_a.c b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/wdt_a.c new file mode 100644 index 000000000..bba45df8c --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/wdt_a.c @@ -0,0 +1,102 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// wdt_a.c - Driver for the wdt_a Module. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \addtogroup wdt_a_api wdt_a +//! @{ +// +//***************************************************************************** + +#include "inc/hw_regaccess.h" +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_WDT_A__ +#include "wdt_a.h" + +#include + +void WDT_A_hold(uint16_t baseAddress) +{ + // Set Hold bit + uint8_t newWDTStatus = + ((HWREG16(baseAddress + OFS_WDTCTL) & 0x00FF) | WDTHOLD); + + HWREG16(baseAddress + OFS_WDTCTL) = WDTPW + newWDTStatus; +} + +void WDT_A_start(uint16_t baseAddress) +{ + // Reset Hold bit + uint8_t newWDTStatus = + ((HWREG16(baseAddress + OFS_WDTCTL) & 0x00FF) & ~(WDTHOLD)); + + HWREG16(baseAddress + OFS_WDTCTL) = WDTPW + newWDTStatus; +} + +void WDT_A_resetTimer(uint16_t baseAddress) +{ + // Set Counter Clear bit + uint8_t newWDTStatus = + ((HWREG16(baseAddress + OFS_WDTCTL) & 0x00FF) | WDTCNTCL); + + HWREG16(baseAddress + OFS_WDTCTL) = WDTPW + newWDTStatus; +} + +void WDT_A_initWatchdogTimer(uint16_t baseAddress, + uint8_t clockSelect, + uint8_t clockDivider) +{ + HWREG16(baseAddress + OFS_WDTCTL) = + WDTPW + WDTCNTCL + WDTHOLD + clockSelect + clockDivider; +} + +void WDT_A_initIntervalTimer(uint16_t baseAddress, + uint8_t clockSelect, + uint8_t clockDivider) +{ + HWREG16(baseAddress + OFS_WDTCTL) = + WDTPW + WDTCNTCL + WDTHOLD + WDTTMSEL + clockSelect + clockDivider; +} + +#endif +//***************************************************************************** +// +//! Close the doxygen group for wdt_a_api +//! @} +// +//***************************************************************************** diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/wdt_a.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/wdt_a.h new file mode 100644 index 000000000..1400b0eb7 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/driverlib/MSP430FR5xx_6xx/wdt_a.h @@ -0,0 +1,210 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +//***************************************************************************** +// +// wdt_a.h - Driver for the WDT_A Module. +// +//***************************************************************************** + +#ifndef __MSP430WARE_WDT_A_H__ +#define __MSP430WARE_WDT_A_H__ + +#include "inc/hw_memmap.h" + +#ifdef __MSP430_HAS_WDT_A__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are values that can be passed to the clockSelect parameter for +// functions: WDT_A_initWatchdogTimer(), and WDT_A_initIntervalTimer(). +// +//***************************************************************************** +#define WDT_A_CLOCKSOURCE_SMCLK (WDTSSEL_0) +#define WDT_A_CLOCKSOURCE_ACLK (WDTSSEL_1) +#define WDT_A_CLOCKSOURCE_VLOCLK (WDTSSEL_2) +#define WDT_A_CLOCKSOURCE_XCLK (WDTSSEL_3) + +//***************************************************************************** +// +// The following are values that can be passed to the clockDivider parameter +// for functions: WDT_A_initWatchdogTimer(), and WDT_A_initIntervalTimer(). +// +//***************************************************************************** +#define WDT_A_CLOCKDIVIDER_2G (WDTIS_0) +#define WDT_A_CLOCKDIVIDER_128M (WDTIS_1) +#define WDT_A_CLOCKDIVIDER_8192K (WDTIS_2) +#define WDT_A_CLOCKDIVIDER_512K (WDTIS_3) +#define WDT_A_CLOCKDIVIDER_32K (WDTIS_4) +#define WDT_A_CLOCKDIVIDER_8192 (WDTIS_5) +#define WDT_A_CLOCKDIVIDER_512 (WDTIS_6) +#define WDT_A_CLOCKDIVIDER_64 (WDTIS_7) + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \brief Holds the Watchdog Timer. +//! +//! This function stops the watchdog timer from running, that way no interrupt +//! or PUC is asserted. +//! +//! \param baseAddress is the base address of the WDT_A module. +//! +//! \return None +// +//***************************************************************************** +extern void WDT_A_hold(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Starts the Watchdog Timer. +//! +//! This function starts the watchdog timer functionality to start counting +//! again. +//! +//! \param baseAddress is the base address of the WDT_A module. +//! +//! \return None +// +//***************************************************************************** +extern void WDT_A_start(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Resets the timer counter of the Watchdog Timer. +//! +//! This function resets the watchdog timer to 0x0000h. +//! +//! \param baseAddress is the base address of the WDT_A module. +//! +//! \return None +// +//***************************************************************************** +extern void WDT_A_resetTimer(uint16_t baseAddress); + +//***************************************************************************** +// +//! \brief Sets the clock source for the Watchdog Timer in watchdog mode. +//! +//! This function sets the watchdog timer in watchdog mode, which will cause a +//! PUC when the timer overflows. When in the mode, a PUC can be avoided with a +//! call to WDT_A_resetTimer() before the timer runs out. +//! +//! \param baseAddress is the base address of the WDT_A module. +//! \param clockSelect is the clock source that the watchdog timer will use. +//! Valid values are: +//! - \b WDT_A_CLOCKSOURCE_SMCLK [Default] +//! - \b WDT_A_CLOCKSOURCE_ACLK +//! - \b WDT_A_CLOCKSOURCE_VLOCLK +//! - \b WDT_A_CLOCKSOURCE_XCLK +//! \n Modified bits are \b WDTSSEL of \b WDTCTL register. +//! \param clockDivider is the divider of the clock source, in turn setting the +//! watchdog timer interval. +//! Valid values are: +//! - \b WDT_A_CLOCKDIVIDER_2G +//! - \b WDT_A_CLOCKDIVIDER_128M +//! - \b WDT_A_CLOCKDIVIDER_8192K +//! - \b WDT_A_CLOCKDIVIDER_512K +//! - \b WDT_A_CLOCKDIVIDER_32K [Default] +//! - \b WDT_A_CLOCKDIVIDER_8192 +//! - \b WDT_A_CLOCKDIVIDER_512 +//! - \b WDT_A_CLOCKDIVIDER_64 +//! \n Modified bits are \b WDTIS and \b WDTHOLD of \b WDTCTL register. +//! +//! \return None +// +//***************************************************************************** +extern void WDT_A_initWatchdogTimer(uint16_t baseAddress, + uint8_t clockSelect, + uint8_t clockDivider); + +//***************************************************************************** +// +//! \brief Sets the clock source for the Watchdog Timer in timer interval mode. +//! +//! This function sets the watchdog timer as timer interval mode, which will +//! assert an interrupt without causing a PUC. +//! +//! \param baseAddress is the base address of the WDT_A module. +//! \param clockSelect is the clock source that the watchdog timer will use. +//! Valid values are: +//! - \b WDT_A_CLOCKSOURCE_SMCLK [Default] +//! - \b WDT_A_CLOCKSOURCE_ACLK +//! - \b WDT_A_CLOCKSOURCE_VLOCLK +//! - \b WDT_A_CLOCKSOURCE_XCLK +//! \n Modified bits are \b WDTSSEL of \b WDTCTL register. +//! \param clockDivider is the divider of the clock source, in turn setting the +//! watchdog timer interval. +//! Valid values are: +//! - \b WDT_A_CLOCKDIVIDER_2G +//! - \b WDT_A_CLOCKDIVIDER_128M +//! - \b WDT_A_CLOCKDIVIDER_8192K +//! - \b WDT_A_CLOCKDIVIDER_512K +//! - \b WDT_A_CLOCKDIVIDER_32K [Default] +//! - \b WDT_A_CLOCKDIVIDER_8192 +//! - \b WDT_A_CLOCKDIVIDER_512 +//! - \b WDT_A_CLOCKDIVIDER_64 +//! \n Modified bits are \b WDTIS and \b WDTHOLD of \b WDTCTL register. +//! +//! \return None +// +//***************************************************************************** +extern void WDT_A_initIntervalTimer(uint16_t baseAddress, + uint8_t clockSelect, + uint8_t clockDivider); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif +#endif // __MSP430WARE_WDT_A_H__ diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/low_level_init_iar.c b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/low_level_init_iar.c new file mode 100644 index 000000000..45a2a8fc7 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/low_level_init_iar.c @@ -0,0 +1,67 @@ +/******************************************************************************* + * + + * This is a template for early application low-level initialization. + * + * The following license agreement applies to linker command files, + * example projects (unless another license is explicitly stated), the + * cstartup code, low_level_init.c, and some other low-level runtime + * library files. + * + * + * Copyright 2013, IAR Systems AB. + * + * This source code is the property of IAR Systems. The source code may only + * be used together with the IAR Embedded Workbench. Redistribution and use + * in source and binary forms, with or without modification, is permitted + * provided that the following conditions are met: + * + * - Redistributions of source code, in whole or in part, must retain the + * above copyright notice, this list of conditions and the disclaimer below. + * + * - IAR Systems name may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + ******************************************************************************/ + +/* + * The function __low_level_init it called by the start-up code before + * "main" is called, and before data segment initialization is + * performed. + * + * This is a template file, modify to perform any initialization that + * should take place early. + * + * The return value of this function controls if data segment + * initialization should take place. If 0 is returned, it is bypassed. + * + * For the MSP430 microcontroller family, please consider disabling + * the watchdog timer here, as it could time-out during the data + * segment initialization. + */ + +#include +#include "msp430.h" + +int __low_level_init(void) +{ + /* Insert your low-level initializations here */ + WDTCTL = WDTPW | WDTHOLD; + + /* + * Return value: + * + * 1 - Perform data segment initialization. + * 0 - Skip data segment initialization. + */ + + return 1; +} diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/main.c b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/main.c new file mode 100644 index 000000000..58561b16a --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/main.c @@ -0,0 +1,304 @@ +/* + FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * This project provides two demo applications. A simple blinky style project, + * and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to + * select between the two. The simply blinky demo is implemented and described + * in main_blinky.c. The more comprehensive test and demo application is + * implemented and described in main_full.c. + * + * This file implements the code that is not demo specific, including the + * hardware setup and standard FreeRTOS hook functions. + * + * ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON + * THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO + * APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT! + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Standard demo includes. */ +#include "TimerDemo.h" +#include "QueueOverwrite.h" +#include "EventGroupsDemo.h" +#include "IntSemTest.h" +#include "TaskNotify.h" +#include "ParTest.h" /* LEDs - a historic name for "Parallel Port". */ + +/* TI includes. */ +#include "driverlib.h" + +/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, +or 0 to run the more comprehensive test and demo application. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1 + +/*-----------------------------------------------------------*/ + +/* + * Configure the hardware as necessary to run this demo. + */ +static void prvSetupHardware( void ); + +/* + * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. + * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. + */ +#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + extern void main_blinky( void ); +#else + extern void main_full( void ); +#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */ + +/* Prototypes for the standard FreeRTOS callback/hook functions implemented +within this file. */ +void vApplicationMallocFailedHook( void ); +void vApplicationIdleHook( void ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationTickHook( void ); + +/* The heap is allocated here so the __persistent qualifier can be used. This +requires configAPPLICATION_ALLOCATED_HEAP to be set to 1 in FreeRTOSConfig.h. +See http://www.freertos.org/a00111.html for more information. */ +__persistent uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Configure the hardware ready to run the demo. */ + prvSetupHardware(); + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + of this file. */ + #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + { + main_blinky(); + } + #else + { + main_full(); + } + #endif + + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Set all GPIO pins to output and low. */ + GPIO_setOutputLowOnPin( GPIO_PORT_P1, GPIO_PIN0 | GPIO_PIN1 | GPIO_PIN2 | GPIO_PIN3 | GPIO_PIN4 | GPIO_PIN5 | GPIO_PIN6 | GPIO_PIN7 ); + GPIO_setOutputLowOnPin( GPIO_PORT_P2, GPIO_PIN0 | GPIO_PIN1 | GPIO_PIN2 | GPIO_PIN3 | GPIO_PIN4 | GPIO_PIN5 | GPIO_PIN6 | GPIO_PIN7 ); + GPIO_setOutputLowOnPin( GPIO_PORT_P3, GPIO_PIN0 | GPIO_PIN1 | GPIO_PIN2 | GPIO_PIN3 | GPIO_PIN4 | GPIO_PIN5 | GPIO_PIN6 | GPIO_PIN7 ); + GPIO_setOutputLowOnPin( GPIO_PORT_P4, GPIO_PIN0 | GPIO_PIN1 | GPIO_PIN2 | GPIO_PIN3 | GPIO_PIN4 | GPIO_PIN5 | GPIO_PIN6 | GPIO_PIN7 ); + GPIO_setOutputLowOnPin( GPIO_PORT_PJ, GPIO_PIN0 | GPIO_PIN1 | GPIO_PIN2 | GPIO_PIN3 | GPIO_PIN4 | GPIO_PIN5 | GPIO_PIN6 | GPIO_PIN7 | GPIO_PIN8 | GPIO_PIN9 | GPIO_PIN10 | GPIO_PIN11 | GPIO_PIN12 | GPIO_PIN13 | GPIO_PIN14 | GPIO_PIN15 ); + GPIO_setAsOutputPin( GPIO_PORT_P1, GPIO_PIN0 | GPIO_PIN1 | GPIO_PIN2 | GPIO_PIN3 | GPIO_PIN4 | GPIO_PIN5 | GPIO_PIN6 | GPIO_PIN7 ); + GPIO_setAsOutputPin( GPIO_PORT_P2, GPIO_PIN0 | GPIO_PIN1 | GPIO_PIN2 | GPIO_PIN3 | GPIO_PIN4 | GPIO_PIN5 | GPIO_PIN6 | GPIO_PIN7 ); + GPIO_setAsOutputPin( GPIO_PORT_P3, GPIO_PIN0 | GPIO_PIN1 | GPIO_PIN2 | GPIO_PIN3 | GPIO_PIN4 | GPIO_PIN5 | GPIO_PIN6 | GPIO_PIN7 ); + GPIO_setAsOutputPin( GPIO_PORT_P4, GPIO_PIN0 | GPIO_PIN1 | GPIO_PIN2 | GPIO_PIN3 | GPIO_PIN4 | GPIO_PIN5 | GPIO_PIN6 | GPIO_PIN7 ); + GPIO_setAsOutputPin( GPIO_PORT_PJ, GPIO_PIN0 | GPIO_PIN1 | GPIO_PIN2 | GPIO_PIN3 | GPIO_PIN4 | GPIO_PIN5 | GPIO_PIN6 | GPIO_PIN7 | GPIO_PIN8 | GPIO_PIN9 | GPIO_PIN10 | GPIO_PIN11 | GPIO_PIN12 | GPIO_PIN13 | GPIO_PIN14 | GPIO_PIN15 ); + + /* Configure P2.0 for UCA0TXD and P2.1 for UCA0RXD. */ + GPIO_setOutputLowOnPin( GPIO_PORT_P2, GPIO_PIN0 ); + GPIO_setAsOutputPin( GPIO_PORT_P2, GPIO_PIN0 ); + GPIO_setAsPeripheralModuleFunctionInputPin( GPIO_PORT_P2, GPIO_PIN1, GPIO_SECONDARY_MODULE_FUNCTION ); + + /* Set PJ.4 and PJ.5 for LFXT. */ + GPIO_setAsPeripheralModuleFunctionInputPin( GPIO_PORT_PJ, GPIO_PIN4 + GPIO_PIN5, GPIO_PRIMARY_MODULE_FUNCTION ); + + /* Set DCO frequency to 1 MHz. */ + CS_setDCOFreq( CS_DCORSEL_0, CS_DCOFSEL_6 ); + + /* Set external clock frequency to 32.768 KHz. */ + CS_setExternalClockSource( 32768, 0 ); + + /* Set ACLK = LFXT. */ + CS_initClockSignal( CS_ACLK, CS_LFXTCLK_SELECT, CS_CLOCK_DIVIDER_1 ); + + /* Set SMCLK = DCO with frequency divider of 1. */ + CS_initClockSignal( CS_SMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 ); + + /* Set MCLK = DCO with frequency divider of 1. */ + CS_initClockSignal( CS_MCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 ); + + /* Start XT1 with no time out. */ + CS_turnOnLFXT( CS_LFXT_DRIVE_0 ); + + /* Disable the GPIO power-on default high-impedance mode. */ + PMM_unlockLPM5(); +} +/*-----------------------------------------------------------*/ + +void vApplicationMallocFailedHook( void ) +{ + /* Called if a call to pvPortMalloc() fails because there is insufficient + free memory available in the FreeRTOS heap. pvPortMalloc() is called + internally by FreeRTOS API functions that create tasks, queues, software + timers, and semaphores. The size of the FreeRTOS heap is set by the + configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); +} +/*-----------------------------------------------------------*/ + +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +{ + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + function is called if a stack overflow is detected. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ +volatile size_t xFreeHeapSpace; + + /* This is just a trivial example of an idle hook. It is called on each + cycle of the idle task. It must *NOT* attempt to block. In this case the + idle task just queries the amount of FreeRTOS heap that remains. See the + memory management section on the http://www.FreeRTOS.org web site for memory + management options. If there is a lot of heap memory free then the + configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up + RAM. */ + xFreeHeapSpace = xPortGetFreeHeapSize(); + + /* Remove compiler warning about xFreeHeapSpace being set but never used. */ + ( void ) xFreeHeapSpace; +} +/*-----------------------------------------------------------*/ + +void vApplicationTickHook( void ) +{ + #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 + { + /* The full demo includes a software timer demo/test that requires + prodding periodically from the tick interrupt. */ + vTimerPeriodicISRTests(); + + /* Call the periodic queue overwrite from ISR demo. */ + vQueueOverwritePeriodicISRDemo(); + + /* Call the periodic event group from ISR demo. */ + vPeriodicEventGroupsProcessing(); + + /* Call the code that uses a mutex from an ISR. */ + vInterruptSemaphorePeriodicTest(); + + /* Call the code that 'gives' a task notification from an ISR. */ + xNotifyTaskFromISR(); + } + #endif +} +/*-----------------------------------------------------------*/ + +/* The MSP430X port uses this callback function to configure its tick interrupt. +This allows the application to choose the tick interrupt source. +configTICK_VECTOR must also be set in FreeRTOSConfig.h to the correct +interrupt vector for the chosen tick interrupt source. This implementation of +vApplicationSetupTimerInterrupt() generates the tick from timer A0, so in this +case configTICK_VECTOR is set to TIMER0_A0_VECTOR. */ +void vApplicationSetupTimerInterrupt( void ) +{ +const unsigned short usACLK_Frequency_Hz = 32768; + + /* Ensure the timer is stopped. */ + TA0CTL = 0; + + /* Run the timer from the ACLK. */ + TA0CTL = TASSEL_1; + + /* Clear everything to start with. */ + TA0CTL |= TACLR; + + /* Set the compare match value according to the tick rate we want. */ + TA0CCR0 = usACLK_Frequency_Hz / configTICK_RATE_HZ; + + /* Enable the interrupts. */ + TA0CCTL0 = CCIE; + + /* Start up clean. */ + TA0CTL |= TACLR; + + /* Up mode. */ + TA0CTL |= MC_1; +} +/*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/MSP430FR5969_LaunchPad/main.h b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/main.h new file mode 100644 index 000000000..9b4a38c44 --- /dev/null +++ b/FreeRTOS/Demo/MSP430FR5969_LaunchPad/main.h @@ -0,0 +1,64 @@ +/* --COPYRIGHT--,BSD + * Copyright (c) 2014, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * --/COPYRIGHT--*/ +/******************************************************************************* + * + * main.h + * + * Out of Box Demo for the MSP-EXP430FR5969 + * Main loop, initialization, and interrupt service routines + * + * June 2014 + * E. Chen + * + ******************************************************************************/ + +#ifndef OUTOFBOX_FR5969_NEWD_MAIN_H_ +#define OUTOFBOX_FR5969_NEWD_MAIN_H_ + +#define CAL_ADC_12T30_L *(int8_t *)(0x1A1E) // Temperature Sensor Calibration-30 C 2.0V ref +#define CAL_ADC_12T30_H *(int8_t *)(0x1A1F) +#define CAL_ADC_12T85_L *(int8_t *)(0x1A20) // Temperature Sensor Calibration-85 C 2.0V ref +#define CAL_ADC_12T85_H *(int8_t *)(0x1A21) + +extern int mode; +extern int pingHost; + +void Init_GPIO(void); +void Init_Clock(void); +void Init_UART(void); +void Init_RTC(void); +void sendCalibrationConstants(void); +void sendTimeStamp(void); +void sendAckToPC(void); +void enterLPM35(void); + +#endif /* OUTOFBOX_FR5969_NEWD_MAIN_H_ */