Ensure the PIC32 interrupt stack is 8 byte aligned for all values of configISR_STACK_SIZE.

pull/4/head
Richard Barry 8 years ago
parent 96db5a3600
commit 8ca40d80a9

@ -188,11 +188,11 @@ volatile UBaseType_t uxInterruptNesting = 0x01;
UBaseType_t uxSavedTaskStackPointer = 0;
/* The stack used by interrupt service routines that cause a context switch. */
StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
__attribute__ ((aligned(8))) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
/* The top of stack value ensures there is enough space to store 6 registers on
the callers stack, as some functions seem to want to do this. */
const StackType_t * const xISRStackTop = &( xISRStack[ configISR_STACK_SIZE - 7 ] );
const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE & ~portBYTE_ALIGNMENT_MASK ) - 8 ] );
/*-----------------------------------------------------------*/

@ -198,7 +198,7 @@ extern void vPortClearInterruptMaskFromISR( UBaseType_t );
/*-----------------------------------------------------------*/
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - _clz( ( uxReadyPriorities ) ) )
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - _clz( ( uxReadyPriorities ) ) )
#endif /* taskRECORD_READY_PRIORITY */

@ -1,5 +1,5 @@
/*
FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
FreeRTOS V9.0.1 - Copyright (C) 2017 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
@ -71,8 +71,12 @@
* Implementation of functions defined in portable.h for the PIC32MZ port.
*----------------------------------------------------------*/
/* Microchip specific headers. */
#include <xc.h>
/* Standard headers. */
#include <string.h>
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
@ -189,11 +193,13 @@ volatile UBaseType_t uxInterruptNesting = 0x01;
UBaseType_t uxSavedTaskStackPointer = 0;
/* The stack used by interrupt service routines that cause a context switch. */
StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
__attribute__ ((aligned(8))) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
/* The top of stack value ensures there is enough space to store 6 registers on
the callers stack, as some functions seem to want to do this. */
const StackType_t * const xISRStackTop = &( xISRStack[ configISR_STACK_SIZE - 7 ] );
the callers stack, as some functions seem to want to do this. 8 byte alignment
is required to allow double word floating point stack pushes generated by the
compiler. */
const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE & ~portBYTE_ALIGNMENT_MASK ) - 8 ] );
/* Saved as part of the task context. Set to pdFALSE if the task does not
require an FPU context. */

@ -209,7 +209,7 @@ extern void vPortClearInterruptMaskFromISR( UBaseType_t );
/*-----------------------------------------------------------*/
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - _clz( ( uxReadyPriorities ) ) )
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - _clz( ( uxReadyPriorities ) ) )
#endif /* taskRECORD_READY_PRIORITY */

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