Remove some large files from the repository that don't need to be there.
Richard Barry
14 years ago
parent
678396f61b
commit
731a01f8f4
@ -1,12 +0,0 @@
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<!DOCTYPE html PUBLIC "-//W3C//DTD SVG 1.0//EN" "http://www.w3.org/TR/SVG/DTD/svg10.dtd">
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<HTML>
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<HEAD>
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<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
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<TITLE>XPS Project Report</TITLE>
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</HEAD>
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<HEAD><TITLE>XPS Project Report</TITLE></HEAD>
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<FRAMESET COLS="20%,80%" BORDER="0" FRAMESPACING="0">
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<FRAME SRC="system_toc.html" MARGINWIDTH="0" MARINHEIGHT="0" FRAMEBORDER="NO" BORDER="NO" NAME="system_toc" SCROLLING="YES">
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<FRAME SRC="system_main.html" MARGINWIDTH="0" MARINHEIGHT="0" FRAMEBORDER="NO" BORDER="NO" NAME="system_main" SCROLLING="YES">
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</FRAMESET>
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</HTML>
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@ -1,563 +0,0 @@
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=========================================================================
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Time: Sat Aug 27 15:05:27 GMT Daylight Time 2011
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Running: run_batch_mode 96334104
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{COLLECTING: INSTANCE MCB_DDR3 }
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{COLLECTING: C_INTERCONNECT_S0_AXI_MASTERS microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM OPTIONAL string none microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM}
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{COLLECTING: C_INTERCONNECT_S0_AXI_IS_ACLK_ASYNC 0 OPTIONAL_UPDATE integer 0 }
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{COLLECTING: C_INTERCONNECT_S0_AXI_ACLK_RATIO 100000000 UPDATE integer 1 }
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{COLLECTING: C_INTERCONNECT_S0_AXI_SECURE 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S0_AXI_AW_REGISTER 1 OPTIONAL integer 0 1}
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{COLLECTING: C_INTERCONNECT_S0_AXI_AR_REGISTER 1 OPTIONAL integer 0 1}
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{COLLECTING: C_INTERCONNECT_S0_AXI_W_REGISTER 1 OPTIONAL integer 0 1}
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{COLLECTING: C_INTERCONNECT_S0_AXI_R_REGISTER 1 OPTIONAL integer 0 1}
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{COLLECTING: C_INTERCONNECT_S0_AXI_B_REGISTER 1 OPTIONAL integer 0 1}
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{COLLECTING: C_INTERCONNECT_S0_AXI_WRITE_FIFO_DEPTH 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S0_AXI_READ_FIFO_DEPTH 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE 4 OPTIONAL INTEGER 4 }
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{COLLECTING: C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE 4 OPTIONAL INTEGER 4 }
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{COLLECTING: C_S0_AXI_ADDED_AXI_PARAMS TRUE CONSTANT }
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{COLLECTING: C_S0_AXI_AXI_VER 1.02.a CONSTANT }
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{COLLECTING: C_INTERCONNECT_S1_AXI_MASTERS none OPTIONAL string none }
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{COLLECTING: C_INTERCONNECT_S1_AXI_IS_ACLK_ASYNC 0 OPTIONAL_UPDATE integer 0 }
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{COLLECTING: C_INTERCONNECT_S1_AXI_ACLK_RATIO 1 UPDATE integer 1 }
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{COLLECTING: C_INTERCONNECT_S1_AXI_SECURE 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S1_AXI_AW_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S1_AXI_AR_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S1_AXI_W_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S1_AXI_R_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S1_AXI_B_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S1_AXI_WRITE_FIFO_DEPTH 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S1_AXI_READ_FIFO_DEPTH 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S1_AXI_WRITE_ACCEPTANCE 4 OPTIONAL INTEGER 4 }
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{COLLECTING: C_INTERCONNECT_S1_AXI_READ_ACCEPTANCE 4 OPTIONAL INTEGER 4 }
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{COLLECTING: C_S1_AXI_ADDED_AXI_PARAMS TRUE CONSTANT }
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{COLLECTING: C_S1_AXI_AXI_VER 1.01.a CONSTANT }
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{COLLECTING: C_INTERCONNECT_S2_AXI_MASTERS none OPTIONAL string none }
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{COLLECTING: C_INTERCONNECT_S2_AXI_IS_ACLK_ASYNC 0 OPTIONAL_UPDATE integer 0 }
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{COLLECTING: C_INTERCONNECT_S2_AXI_ACLK_RATIO 1 UPDATE integer 1 }
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{COLLECTING: C_INTERCONNECT_S2_AXI_SECURE 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S2_AXI_AW_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S2_AXI_AR_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S2_AXI_W_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S2_AXI_R_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S2_AXI_B_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S2_AXI_WRITE_FIFO_DEPTH 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S2_AXI_READ_FIFO_DEPTH 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S2_AXI_WRITE_ACCEPTANCE 4 OPTIONAL INTEGER 4 }
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{COLLECTING: C_INTERCONNECT_S2_AXI_READ_ACCEPTANCE 4 OPTIONAL INTEGER 4 }
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{COLLECTING: C_S2_AXI_ADDED_AXI_PARAMS TRUE CONSTANT }
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{COLLECTING: C_S2_AXI_AXI_VER 1.01.a CONSTANT }
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{COLLECTING: C_INTERCONNECT_S3_AXI_MASTERS none OPTIONAL string none }
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{COLLECTING: C_INTERCONNECT_S3_AXI_IS_ACLK_ASYNC 0 OPTIONAL_UPDATE integer 0 }
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{COLLECTING: C_INTERCONNECT_S3_AXI_ACLK_RATIO 1 UPDATE integer 1 }
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{COLLECTING: C_INTERCONNECT_S3_AXI_SECURE 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S3_AXI_AW_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S3_AXI_AR_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S3_AXI_W_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S3_AXI_R_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S3_AXI_B_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S3_AXI_WRITE_FIFO_DEPTH 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S3_AXI_READ_FIFO_DEPTH 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S3_AXI_WRITE_ACCEPTANCE 4 OPTIONAL INTEGER 4 }
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{COLLECTING: C_INTERCONNECT_S3_AXI_READ_ACCEPTANCE 4 OPTIONAL INTEGER 4 }
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{COLLECTING: C_S3_AXI_ADDED_AXI_PARAMS TRUE CONSTANT }
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{COLLECTING: C_S3_AXI_AXI_VER 1.01.a CONSTANT }
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{COLLECTING: C_INTERCONNECT_S4_AXI_MASTERS none OPTIONAL string none }
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{COLLECTING: C_INTERCONNECT_S4_AXI_IS_ACLK_ASYNC 0 OPTIONAL_UPDATE integer 0 }
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{COLLECTING: C_INTERCONNECT_S4_AXI_ACLK_RATIO 1 UPDATE integer 1 }
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{COLLECTING: C_INTERCONNECT_S4_AXI_SECURE 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S4_AXI_AW_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S4_AXI_AR_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S4_AXI_W_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S4_AXI_R_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S4_AXI_B_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S4_AXI_WRITE_FIFO_DEPTH 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S4_AXI_READ_FIFO_DEPTH 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S4_AXI_WRITE_ACCEPTANCE 4 OPTIONAL INTEGER 4 }
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{COLLECTING: C_INTERCONNECT_S4_AXI_READ_ACCEPTANCE 4 OPTIONAL INTEGER 4 }
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{COLLECTING: C_S4_AXI_ADDED_AXI_PARAMS TRUE CONSTANT }
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{COLLECTING: C_S4_AXI_AXI_VER 1.01.a CONSTANT }
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{COLLECTING: C_INTERCONNECT_S5_AXI_MASTERS none OPTIONAL string none }
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{COLLECTING: C_INTERCONNECT_S5_AXI_IS_ACLK_ASYNC 0 OPTIONAL_UPDATE integer 0 }
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{COLLECTING: C_INTERCONNECT_S5_AXI_ACLK_RATIO 1 UPDATE integer 1 }
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{COLLECTING: C_INTERCONNECT_S5_AXI_SECURE 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S5_AXI_AW_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S5_AXI_AR_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S5_AXI_W_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S5_AXI_R_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S5_AXI_B_REGISTER 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S5_AXI_WRITE_FIFO_DEPTH 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S5_AXI_READ_FIFO_DEPTH 0 OPTIONAL integer 0 }
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{COLLECTING: C_INTERCONNECT_S5_AXI_WRITE_ACCEPTANCE 4 OPTIONAL INTEGER 4 }
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{COLLECTING: C_INTERCONNECT_S5_AXI_READ_ACCEPTANCE 4 OPTIONAL INTEGER 4 }
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{COLLECTING: C_S5_AXI_ADDED_AXI_PARAMS TRUE CONSTANT }
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{COLLECTING: C_S5_AXI_AXI_VER 1.01.a CONSTANT }
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{COLLECTING: C_MCB_LOC MEMC3 OPTIONAL MEMC3 }
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{COLLECTING: C_MCB_RZQ_LOC K7 OPTIONAL STRING NOT_SET K7}
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{COLLECTING: C_MCB_ZIO_LOC R7 OPTIONAL STRING NOT_SET R7}
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{COLLECTING: C_MCB_PERFORMANCE STANDARD OPTIONAL STRING STANDARD }
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{COLLECTING: C_BYPASS_CORE_UCF 0 OPTIONAL 0 }
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{COLLECTING: C_S0_AXI_BASEADDR 0x80000000 OPTIONAL STD_LOGIC_VECTOR 0xFFFFFFFF 0x80000000}
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{COLLECTING: C_S0_AXI_HIGHADDR 0x807FFFFF OPTIONAL STD_LOGIC_VECTOR 0x00000000 0x807FFFFF}
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{COLLECTING: C_S1_AXI_BASEADDR 0xFFFFFFFF OPTIONAL STD_LOGIC_VECTOR 0xFFFFFFFF }
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{COLLECTING: C_S1_AXI_HIGHADDR 0x00000000 OPTIONAL STD_LOGIC_VECTOR 0x00000000 }
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{COLLECTING: C_S2_AXI_BASEADDR 0xFFFFFFFF OPTIONAL STD_LOGIC_VECTOR 0xFFFFFFFF }
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{COLLECTING: C_S2_AXI_HIGHADDR 0x00000000 OPTIONAL STD_LOGIC_VECTOR 0x00000000 }
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{COLLECTING: C_S3_AXI_BASEADDR 0xFFFFFFFF OPTIONAL STD_LOGIC_VECTOR 0xFFFFFFFF }
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{COLLECTING: C_S3_AXI_HIGHADDR 0x00000000 OPTIONAL STD_LOGIC_VECTOR 0x00000000 }
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{COLLECTING: C_S4_AXI_BASEADDR 0xFFFFFFFF OPTIONAL STD_LOGIC_VECTOR 0xFFFFFFFF }
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{COLLECTING: C_S4_AXI_HIGHADDR 0x00000000 OPTIONAL STD_LOGIC_VECTOR 0x00000000 }
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{COLLECTING: C_S5_AXI_BASEADDR 0xFFFFFFFF OPTIONAL STD_LOGIC_VECTOR 0xFFFFFFFF }
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{COLLECTING: C_S5_AXI_HIGHADDR 0x00000000 OPTIONAL STD_LOGIC_VECTOR 0x00000000 }
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{COLLECTING: C_MEM_TYPE DDR3 OPTIONAL STRING DDR3 }
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{COLLECTING: C_MEM_PARTNO MT41J64M16XX-187E REQUIRE STRING NOT_SET MT41J64M16XX-187E}
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{COLLECTING: C_MEM_BASEPARTNO NOT_SET OPTIONAL STRING NOT_SET }
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{COLLECTING: C_NUM_DQ_PINS 16 OPTIONAL_UPDATE INTEGER 16 }
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{COLLECTING: C_MEM_ADDR_WIDTH 13 OPTIONAL_UPDATE INTEGER 13 }
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{COLLECTING: C_MEM_BANKADDR_WIDTH 3 OPTIONAL_UPDATE INTEGER 3 }
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{COLLECTING: C_MEM_NUM_COL_BITS 10 OPTIONAL_UPDATE INTEGER 10 }
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{COLLECTING: C_MEM_TRAS -1 OPTIONAL_UPDATE INTEGER -1 }
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{COLLECTING: C_MEM_TRCD -1 OPTIONAL_UPDATE INTEGER -1 }
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{COLLECTING: C_MEM_TREFI -1 OPTIONAL_UPDATE INTEGER -1 }
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{COLLECTING: C_MEM_TRFC -1 OPTIONAL_UPDATE INTEGER -1 }
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{COLLECTING: C_MEM_TRP -1 OPTIONAL_UPDATE INTEGER -1 }
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{COLLECTING: C_MEM_TWR -1 OPTIONAL_UPDATE INTEGER -1 }
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{COLLECTING: C_MEM_TRTP -1 OPTIONAL_UPDATE INTEGER -1 }
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{COLLECTING: C_MEM_TWTR -1 OPTIONAL_UPDATE INTEGER -1 }
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{COLLECTING: C_PORT_CONFIG B32_B32_B32_B32 OPTIONAL STRING B32_B32_B32_B32 }
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{COLLECTING: C_SKIP_IN_TERM_CAL 0 OPTIONAL INTEGER 0 }
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{COLLECTING: C_SKIP_IN_TERM_CAL_VALUE NONE OPTIONAL STRING NONE }
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{COLLECTING: C_MEMCLK_PERIOD 0 OPTIONAL_UPDATE INTEGER 0 }
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{COLLECTING: C_MEM_ADDR_ORDER ROW_BANK_COLUMN OPTIONAL STRING ROW_BANK_COLUMN }
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{COLLECTING: C_MEM_TZQINIT_MAXCNT 512 UPDATE INTEGER 512 }
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{COLLECTING: C_MEM_CAS_LATENCY 6 UPDATE INTEGER 6 }
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{COLLECTING: C_SIMULATION FALSE OPTIONAL STRING FALSE }
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{COLLECTING: C_MEM_DDR1_2_ODS FULL OPTIONAL STRING FULL }
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{COLLECTING: C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODS CLASS_II OPTIONAL STRING CLASS_II }
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{COLLECTING: C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODS CLASS_II OPTIONAL STRING CLASS_II }
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{COLLECTING: C_MEM_DDR2_RTT 150OHMS OPTIONAL STRING 150OHMS }
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{COLLECTING: C_MEM_DDR2_DIFF_DQS_EN YES OPTIONAL STRING YES }
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{COLLECTING: C_MEM_DDR2_3_PA_SR FULL OPTIONAL STRING FULL }
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{COLLECTING: C_MEM_DDR2_3_HIGH_TEMP_SR NORMAL OPTIONAL STRING NORMAL }
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{COLLECTING: C_MEM_DDR3_CAS_WR_LATENCY 5 UPDATE INTEGER 5 }
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{COLLECTING: C_MEM_DDR3_CAS_LATENCY 6 UPDATE INTEGER 6 }
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{COLLECTING: C_MEM_DDR3_ODS DIV6 OPTIONAL STRING DIV6 }
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{COLLECTING: C_MEM_DDR3_RTT DIV4 OPTIONAL STRING DIV4 }
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{COLLECTING: C_MEM_DDR3_AUTO_SR ENABLED OPTIONAL STRING ENABLED }
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{COLLECTING: C_MEM_MOBILE_PA_SR FULL OPTIONAL STRING FULL }
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{COLLECTING: C_MEM_MDDR_ODS FULL OPTIONAL STRING FULL }
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{COLLECTING: C_ARB_ALGORITHM 0 OPTIONAL INTEGER 0 }
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{COLLECTING: C_ARB_NUM_TIME_SLOTS 12 OPTIONAL INTEGER 12 }
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{COLLECTING: C_ARB_TIME_SLOT_0 0b000000000001010011 OPTIONAL STD_LOGIC_VECTOR 0b000000000001010011 }
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{COLLECTING: C_ARB_TIME_SLOT_1 0b000000001010011000 OPTIONAL STD_LOGIC_VECTOR 0b000000001010011000 }
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{COLLECTING: C_ARB_TIME_SLOT_2 0b000000010011000001 OPTIONAL STD_LOGIC_VECTOR 0b000000010011000001 }
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{COLLECTING: C_ARB_TIME_SLOT_3 0b000000011000001010 OPTIONAL STD_LOGIC_VECTOR 0b000000011000001010 }
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{COLLECTING: C_ARB_TIME_SLOT_4 0b000000000001010011 OPTIONAL STD_LOGIC_VECTOR 0b000000000001010011 }
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{COLLECTING: C_ARB_TIME_SLOT_5 0b000000001010011000 OPTIONAL STD_LOGIC_VECTOR 0b000000001010011000 }
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{COLLECTING: C_ARB_TIME_SLOT_6 0b000000010011000001 OPTIONAL STD_LOGIC_VECTOR 0b000000010011000001 }
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{COLLECTING: C_ARB_TIME_SLOT_7 0b000000011000001010 OPTIONAL STD_LOGIC_VECTOR 0b000000011000001010 }
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{COLLECTING: C_ARB_TIME_SLOT_8 0b000000000001010011 OPTIONAL STD_LOGIC_VECTOR 0b000000000001010011 }
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{COLLECTING: C_ARB_TIME_SLOT_9 0b000000001010011000 OPTIONAL STD_LOGIC_VECTOR 0b000000001010011000 }
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{COLLECTING: C_ARB_TIME_SLOT_10 0b000000010011000001 OPTIONAL STD_LOGIC_VECTOR 0b000000010011000001 }
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{COLLECTING: C_ARB_TIME_SLOT_11 0b000000011000001010 OPTIONAL STD_LOGIC_VECTOR 0b000000011000001010 }
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{COLLECTING: C_S0_AXI_ENABLE 1 OPTIONAL INTEGER 1 }
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{COLLECTING: C_S0_AXI_PROTOCOL AXI4 CONSTANT STRING AXI4 }
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{COLLECTING: C_S0_AXI_ID_WIDTH 3 UPDATE INTEGER 4 }
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{COLLECTING: C_S0_AXI_ADDR_WIDTH 32 CONSTANT INTEGER 32 }
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{COLLECTING: C_S0_AXI_DATA_WIDTH 32 OPTIONAL INTEGER 32 }
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{COLLECTING: C_S0_AXI_SUPPORTS_READ 1 OPTIONAL_UPDATE INTEGER 1 }
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{COLLECTING: C_S0_AXI_SUPPORTS_WRITE 1 OPTIONAL_UPDATE INTEGER 1 }
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{COLLECTING: C_S0_AXI_SUPPORTS_NARROW_BURST Auto OPTIONAL_UPDATE INTEGER 1 }
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{COLLECTING: C_S0_AXI_REG_EN0 0x00000 OPTIONAL_UPDATE STD_LOGIC_VECTOR 0x00000 }
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{COLLECTING: C_S0_AXI_REG_EN1 0x01000 OPTIONAL STD_LOGIC_VECTOR 0x01000 }
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{COLLECTING: C_S0_AXI_STRICT_COHERENCY 0 OPTIONAL_UPDATE INTEGER 1 0}
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{COLLECTING: C_S0_AXI_ENABLE_AP 0 OPTIONAL INTEGER 0 }
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{COLLECTING: C_S1_AXI_ENABLE 0 OPTIONAL INTEGER 0 }
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{COLLECTING: C_S1_AXI_PROTOCOL AXI4 CONSTANT STRING AXI4 }
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{COLLECTING: C_S1_AXI_ID_WIDTH 4 UPDATE INTEGER 4 }
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{COLLECTING: C_S1_AXI_ADDR_WIDTH 32 CONSTANT INTEGER 32 }
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{COLLECTING: C_S1_AXI_DATA_WIDTH 32 OPTIONAL INTEGER 32 }
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{COLLECTING: C_S1_AXI_SUPPORTS_READ 1 OPTIONAL_UPDATE INTEGER 1 }
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{COLLECTING: C_S1_AXI_SUPPORTS_WRITE 1 OPTIONAL_UPDATE INTEGER 1 }
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{COLLECTING: C_S1_AXI_SUPPORTS_NARROW_BURST Auto OPTIONAL_UPDATE INTEGER 1 }
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{COLLECTING: C_S1_AXI_REG_EN0 0x00000 OPTIONAL_UPDATE STD_LOGIC_VECTOR 0x00000 }
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{COLLECTING: C_S1_AXI_REG_EN1 0x01000 OPTIONAL STD_LOGIC_VECTOR 0x01000 }
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{COLLECTING: C_S1_AXI_STRICT_COHERENCY 1 OPTIONAL_UPDATE INTEGER 1 }
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{COLLECTING: C_S1_AXI_ENABLE_AP 0 OPTIONAL INTEGER 0 }
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{COLLECTING: C_S2_AXI_ENABLE 0 OPTIONAL INTEGER 0 }
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{COLLECTING: C_S2_AXI_PROTOCOL AXI4 CONSTANT STRING AXI4 }
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{COLLECTING: C_S2_AXI_ID_WIDTH 4 UPDATE INTEGER 4 }
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{COLLECTING: C_S2_AXI_ADDR_WIDTH 32 CONSTANT INTEGER 32 }
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{COLLECTING: C_S2_AXI_DATA_WIDTH 32 CONSTANT INTEGER 32 }
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{COLLECTING: C_S2_AXI_SUPPORTS_READ 1 OPTIONAL_UPDATE INTEGER 1 }
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{COLLECTING: C_S2_AXI_SUPPORTS_WRITE 1 OPTIONAL_UPDATE INTEGER 1 }
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{COLLECTING: C_S2_AXI_SUPPORTS_NARROW_BURST Auto OPTIONAL_UPDATE INTEGER 1 }
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{COLLECTING: C_S2_AXI_REG_EN0 0x00000 OPTIONAL_UPDATE STD_LOGIC_VECTOR 0x00000 }
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{COLLECTING: C_S2_AXI_REG_EN1 0x01000 OPTIONAL STD_LOGIC_VECTOR 0x01000 }
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{COLLECTING: C_S2_AXI_STRICT_COHERENCY 1 OPTIONAL_UPDATE INTEGER 1 }
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{COLLECTING: C_S2_AXI_ENABLE_AP 0 OPTIONAL INTEGER 0 }
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{COLLECTING: C_S3_AXI_ENABLE 0 OPTIONAL INTEGER 0 }
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{COLLECTING: C_S3_AXI_PROTOCOL AXI4 CONSTANT STRING AXI4 }
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{COLLECTING: C_S3_AXI_ID_WIDTH 4 UPDATE INTEGER 4 }
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{COLLECTING: C_S3_AXI_ADDR_WIDTH 32 CONSTANT INTEGER 32 }
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{COLLECTING: C_S3_AXI_DATA_WIDTH 32 CONSTANT INTEGER 32 }
|
||||
{COLLECTING: C_S3_AXI_SUPPORTS_READ 1 OPTIONAL_UPDATE INTEGER 1 }
|
||||
{COLLECTING: C_S3_AXI_SUPPORTS_WRITE 1 OPTIONAL_UPDATE INTEGER 1 }
|
||||
{COLLECTING: C_S3_AXI_SUPPORTS_NARROW_BURST Auto OPTIONAL_UPDATE INTEGER 1 }
|
||||
{COLLECTING: C_S3_AXI_REG_EN0 0x00000 OPTIONAL_UPDATE STD_LOGIC_VECTOR 0x00000 }
|
||||
{COLLECTING: C_S3_AXI_REG_EN1 0x01000 OPTIONAL STD_LOGIC_VECTOR 0x01000 }
|
||||
{COLLECTING: C_S3_AXI_STRICT_COHERENCY 1 OPTIONAL_UPDATE INTEGER 1 }
|
||||
{COLLECTING: C_S3_AXI_ENABLE_AP 0 OPTIONAL INTEGER 0 }
|
||||
{COLLECTING: C_S4_AXI_ENABLE 0 OPTIONAL INTEGER 0 }
|
||||
{COLLECTING: C_S4_AXI_PROTOCOL AXI4 CONSTANT STRING AXI4 }
|
||||
{COLLECTING: C_S4_AXI_ID_WIDTH 4 UPDATE INTEGER 4 }
|
||||
{COLLECTING: C_S4_AXI_ADDR_WIDTH 32 CONSTANT INTEGER 32 }
|
||||
{COLLECTING: C_S4_AXI_DATA_WIDTH 32 CONSTANT INTEGER 32 }
|
||||
{COLLECTING: C_S4_AXI_SUPPORTS_READ 1 OPTIONAL_UPDATE INTEGER 1 }
|
||||
{COLLECTING: C_S4_AXI_SUPPORTS_WRITE 1 OPTIONAL_UPDATE INTEGER 1 }
|
||||
{COLLECTING: C_S4_AXI_SUPPORTS_NARROW_BURST Auto OPTIONAL_UPDATE INTEGER 1 }
|
||||
{COLLECTING: C_S4_AXI_REG_EN0 0x00000 OPTIONAL_UPDATE STD_LOGIC_VECTOR 0x00000 }
|
||||
{COLLECTING: C_S4_AXI_REG_EN1 0x01000 OPTIONAL STD_LOGIC_VECTOR 0x01000 }
|
||||
{COLLECTING: C_S4_AXI_STRICT_COHERENCY 1 OPTIONAL_UPDATE INTEGER 1 }
|
||||
{COLLECTING: C_S4_AXI_ENABLE_AP 0 OPTIONAL INTEGER 0 }
|
||||
{COLLECTING: C_S5_AXI_ENABLE 0 OPTIONAL INTEGER 0 }
|
||||
{COLLECTING: C_S5_AXI_PROTOCOL AXI4 CONSTANT STRING AXI4 }
|
||||
{COLLECTING: C_S5_AXI_ID_WIDTH 4 UPDATE INTEGER 4 }
|
||||
{COLLECTING: C_S5_AXI_ADDR_WIDTH 32 CONSTANT INTEGER 32 }
|
||||
{COLLECTING: C_S5_AXI_DATA_WIDTH 32 CONSTANT INTEGER 32 }
|
||||
{COLLECTING: C_S5_AXI_SUPPORTS_READ 1 OPTIONAL_UPDATE INTEGER 1 }
|
||||
{COLLECTING: C_S5_AXI_SUPPORTS_WRITE 1 OPTIONAL_UPDATE INTEGER 1 }
|
||||
{COLLECTING: C_S5_AXI_SUPPORTS_NARROW_BURST Auto OPTIONAL_UPDATE INTEGER 1 }
|
||||
{COLLECTING: C_S5_AXI_REG_EN0 0x00000 OPTIONAL_UPDATE STD_LOGIC_VECTOR 0x00000 }
|
||||
{COLLECTING: C_S5_AXI_REG_EN1 0x01000 OPTIONAL STD_LOGIC_VECTOR 0x01000 }
|
||||
{COLLECTING: C_S5_AXI_STRICT_COHERENCY 1 OPTIONAL_UPDATE INTEGER 1 }
|
||||
{COLLECTING: C_S5_AXI_ENABLE_AP 0 OPTIONAL INTEGER 0 }
|
||||
{COLLECTING: C_MCB_USE_EXTERNAL_BUFPLL 0 OPTIONAL INTEGER 0 }
|
||||
{COLLECTING: C_SYS_RST_PRESENT 1 UPDATE INTEGER 0 }
|
||||
{COLLECTING: HW_VER 1.02.a }
|
||||
{SENDING PARAMETER: C_ARB_ALGORITHM : 0 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_ARB_NUM_TIME_SLOTS : 12 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_ARB_TIME_SLOT_0 : 0b000000000001010011 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_ARB_TIME_SLOT_1 : 0b000000001010011000 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_ARB_TIME_SLOT_2 : 0b000000010011000001 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_ARB_TIME_SLOT_3 : 0b000000011000001010 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_ARB_TIME_SLOT_4 : 0b000000000001010011 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_ARB_TIME_SLOT_5 : 0b000000001010011000 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_ARB_TIME_SLOT_6 : 0b000000010011000001 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_ARB_TIME_SLOT_7 : 0b000000011000001010 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_ARB_TIME_SLOT_8 : 0b000000000001010011 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_ARB_TIME_SLOT_9 : 0b000000001010011000 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_ARB_TIME_SLOT_10 : 0b000000010011000001 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_ARB_TIME_SLOT_11 : 0b000000011000001010 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_BYPASS_CORE_UCF : 0 {} OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_ACLK_RATIO : 100000000 integer UPDATE}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_AR_REGISTER : 1 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_AW_REGISTER : 1 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_B_REGISTER : 1 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_IS_ACLK_ASYNC : 0 integer OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_MASTERS : {microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM} string OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_R_REGISTER : 1 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE : 4 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_READ_FIFO_DEPTH : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_SECURE : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_W_REGISTER : 1 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE : 4 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S0_AXI_WRITE_FIFO_DEPTH : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_ACLK_RATIO : 1 integer UPDATE}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_AR_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_AW_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_B_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_IS_ACLK_ASYNC : 0 integer OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_MASTERS : none string OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_R_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_READ_ACCEPTANCE : 4 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_READ_FIFO_DEPTH : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_SECURE : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_W_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_WRITE_ACCEPTANCE : 4 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S1_AXI_WRITE_FIFO_DEPTH : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_ACLK_RATIO : 1 integer UPDATE}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_AR_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_AW_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_B_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_IS_ACLK_ASYNC : 0 integer OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_MASTERS : none string OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_R_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_READ_ACCEPTANCE : 4 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_READ_FIFO_DEPTH : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_SECURE : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_W_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_WRITE_ACCEPTANCE : 4 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S2_AXI_WRITE_FIFO_DEPTH : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_ACLK_RATIO : 1 integer UPDATE}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_AR_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_AW_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_B_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_IS_ACLK_ASYNC : 0 integer OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_MASTERS : none string OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_R_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_READ_ACCEPTANCE : 4 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_READ_FIFO_DEPTH : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_SECURE : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_W_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_WRITE_ACCEPTANCE : 4 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S3_AXI_WRITE_FIFO_DEPTH : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_ACLK_RATIO : 1 integer UPDATE}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_AR_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_AW_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_B_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_IS_ACLK_ASYNC : 0 integer OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_MASTERS : none string OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_R_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_READ_ACCEPTANCE : 4 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_READ_FIFO_DEPTH : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_SECURE : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_W_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_WRITE_ACCEPTANCE : 4 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S4_AXI_WRITE_FIFO_DEPTH : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_ACLK_RATIO : 1 integer UPDATE}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_AR_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_AW_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_B_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_IS_ACLK_ASYNC : 0 integer OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_MASTERS : none string OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_R_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_READ_ACCEPTANCE : 4 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_READ_FIFO_DEPTH : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_SECURE : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_W_REGISTER : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_WRITE_ACCEPTANCE : 4 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_INTERCONNECT_S5_AXI_WRITE_FIFO_DEPTH : 0 integer OPTIONAL}
|
||||
{SENDING PARAMETER: C_MCB_LOC : MEMC3 {} OPTIONAL}
|
||||
{SENDING PARAMETER: C_MCB_PERFORMANCE : STANDARD STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MCB_RZQ_LOC : K7 STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MCB_USE_EXTERNAL_BUFPLL : 0 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_MCB_ZIO_LOC : R7 STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MEM_ADDR_ORDER : ROW_BANK_COLUMN STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MEM_ADDR_WIDTH : 13 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_MEM_BANKADDR_WIDTH : 3 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_MEM_BASEPARTNO : NOT_SET STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MEM_CAS_LATENCY : 6 INTEGER UPDATE}
|
||||
{SENDING PARAMETER: C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODS : CLASS_II STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODS : CLASS_II STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MEM_DDR1_2_ODS : FULL STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MEM_DDR2_3_HIGH_TEMP_SR : NORMAL STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MEM_DDR2_3_PA_SR : FULL STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MEM_DDR2_DIFF_DQS_EN : YES STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MEM_DDR2_RTT : 150OHMS STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MEM_DDR3_AUTO_SR : ENABLED STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MEM_DDR3_CAS_LATENCY : 6 INTEGER UPDATE}
|
||||
{SENDING PARAMETER: C_MEM_DDR3_CAS_WR_LATENCY : 5 INTEGER UPDATE}
|
||||
{SENDING PARAMETER: C_MEM_DDR3_ODS : DIV6 STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MEM_DDR3_RTT : DIV4 STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MEM_MDDR_ODS : FULL STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MEM_MOBILE_PA_SR : FULL STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MEM_NUM_COL_BITS : 10 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_MEM_PARTNO : MT41J64M16XX-187E STRING REQUIRE}
|
||||
{SENDING PARAMETER: C_MEM_TRAS : -1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_MEM_TRCD : -1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_MEM_TREFI : -1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_MEM_TRFC : -1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_MEM_TRP : -1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_MEM_TRTP : -1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_MEM_TWR : -1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_MEM_TWTR : -1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_MEM_TYPE : DDR3 STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_MEM_TZQINIT_MAXCNT : 512 INTEGER UPDATE}
|
||||
{SENDING PARAMETER: C_MEMCLK_PERIOD : 0 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_NUM_DQ_PINS : 16 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_PORT_CONFIG : B32_B32_B32_B32 STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_S0_AXI_ADDED_AXI_PARAMS : TRUE {} CONSTANT}
|
||||
{SENDING PARAMETER: C_S0_AXI_ADDR_WIDTH : 32 INTEGER CONSTANT}
|
||||
{SENDING PARAMETER: C_S0_AXI_AXI_VER : 1.02.a {} CONSTANT}
|
||||
{SENDING PARAMETER: C_S0_AXI_BASEADDR : 0x80000000 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S0_AXI_DATA_WIDTH : 32 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_S0_AXI_ENABLE : 1 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_S0_AXI_ENABLE_AP : 0 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_S0_AXI_HIGHADDR : 0x807FFFFF STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S0_AXI_ID_WIDTH : 3 INTEGER UPDATE}
|
||||
{SENDING PARAMETER: C_S0_AXI_PROTOCOL : AXI4 STRING CONSTANT}
|
||||
{SENDING PARAMETER: C_S0_AXI_REG_EN0 : 0x00000 STD_LOGIC_VECTOR OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S0_AXI_REG_EN1 : 0x01000 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S0_AXI_STRICT_COHERENCY : 0 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S0_AXI_SUPPORTS_NARROW_BURST : Auto INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S0_AXI_SUPPORTS_READ : 1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S0_AXI_SUPPORTS_WRITE : 1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S1_AXI_ADDED_AXI_PARAMS : TRUE {} CONSTANT}
|
||||
{SENDING PARAMETER: C_S1_AXI_ADDR_WIDTH : 32 INTEGER CONSTANT}
|
||||
{SENDING PARAMETER: C_S1_AXI_AXI_VER : 1.01.a {} CONSTANT}
|
||||
{SENDING PARAMETER: C_S1_AXI_BASEADDR : 0xFFFFFFFF STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S1_AXI_DATA_WIDTH : 32 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_S1_AXI_ENABLE : 0 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_S1_AXI_ENABLE_AP : 0 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_S1_AXI_HIGHADDR : 0x00000000 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S1_AXI_ID_WIDTH : 4 INTEGER UPDATE}
|
||||
{SENDING PARAMETER: C_S1_AXI_PROTOCOL : AXI4 STRING CONSTANT}
|
||||
{SENDING PARAMETER: C_S1_AXI_REG_EN0 : 0x00000 STD_LOGIC_VECTOR OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S1_AXI_REG_EN1 : 0x01000 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S1_AXI_STRICT_COHERENCY : 1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S1_AXI_SUPPORTS_NARROW_BURST : Auto INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S1_AXI_SUPPORTS_READ : 1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S1_AXI_SUPPORTS_WRITE : 1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S2_AXI_ADDED_AXI_PARAMS : TRUE {} CONSTANT}
|
||||
{SENDING PARAMETER: C_S2_AXI_ADDR_WIDTH : 32 INTEGER CONSTANT}
|
||||
{SENDING PARAMETER: C_S2_AXI_AXI_VER : 1.01.a {} CONSTANT}
|
||||
{SENDING PARAMETER: C_S2_AXI_BASEADDR : 0xFFFFFFFF STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S2_AXI_DATA_WIDTH : 32 INTEGER CONSTANT}
|
||||
{SENDING PARAMETER: C_S2_AXI_ENABLE : 0 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_S2_AXI_ENABLE_AP : 0 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_S2_AXI_HIGHADDR : 0x00000000 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S2_AXI_ID_WIDTH : 4 INTEGER UPDATE}
|
||||
{SENDING PARAMETER: C_S2_AXI_PROTOCOL : AXI4 STRING CONSTANT}
|
||||
{SENDING PARAMETER: C_S2_AXI_REG_EN0 : 0x00000 STD_LOGIC_VECTOR OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S2_AXI_REG_EN1 : 0x01000 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S2_AXI_STRICT_COHERENCY : 1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S2_AXI_SUPPORTS_NARROW_BURST : Auto INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S2_AXI_SUPPORTS_READ : 1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S2_AXI_SUPPORTS_WRITE : 1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S3_AXI_ADDED_AXI_PARAMS : TRUE {} CONSTANT}
|
||||
{SENDING PARAMETER: C_S3_AXI_ADDR_WIDTH : 32 INTEGER CONSTANT}
|
||||
{SENDING PARAMETER: C_S3_AXI_AXI_VER : 1.01.a {} CONSTANT}
|
||||
{SENDING PARAMETER: C_S3_AXI_BASEADDR : 0xFFFFFFFF STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S3_AXI_DATA_WIDTH : 32 INTEGER CONSTANT}
|
||||
{SENDING PARAMETER: C_S3_AXI_ENABLE : 0 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_S3_AXI_ENABLE_AP : 0 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_S3_AXI_HIGHADDR : 0x00000000 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S3_AXI_ID_WIDTH : 4 INTEGER UPDATE}
|
||||
{SENDING PARAMETER: C_S3_AXI_PROTOCOL : AXI4 STRING CONSTANT}
|
||||
{SENDING PARAMETER: C_S3_AXI_REG_EN0 : 0x00000 STD_LOGIC_VECTOR OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S3_AXI_REG_EN1 : 0x01000 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S3_AXI_STRICT_COHERENCY : 1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S3_AXI_SUPPORTS_NARROW_BURST : Auto INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S3_AXI_SUPPORTS_READ : 1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S3_AXI_SUPPORTS_WRITE : 1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S4_AXI_ADDED_AXI_PARAMS : TRUE {} CONSTANT}
|
||||
{SENDING PARAMETER: C_S4_AXI_ADDR_WIDTH : 32 INTEGER CONSTANT}
|
||||
{SENDING PARAMETER: C_S4_AXI_AXI_VER : 1.01.a {} CONSTANT}
|
||||
{SENDING PARAMETER: C_S4_AXI_BASEADDR : 0xFFFFFFFF STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S4_AXI_DATA_WIDTH : 32 INTEGER CONSTANT}
|
||||
{SENDING PARAMETER: C_S4_AXI_ENABLE : 0 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_S4_AXI_ENABLE_AP : 0 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_S4_AXI_HIGHADDR : 0x00000000 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S4_AXI_ID_WIDTH : 4 INTEGER UPDATE}
|
||||
{SENDING PARAMETER: C_S4_AXI_PROTOCOL : AXI4 STRING CONSTANT}
|
||||
{SENDING PARAMETER: C_S4_AXI_REG_EN0 : 0x00000 STD_LOGIC_VECTOR OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S4_AXI_REG_EN1 : 0x01000 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S4_AXI_STRICT_COHERENCY : 1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S4_AXI_SUPPORTS_NARROW_BURST : Auto INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S4_AXI_SUPPORTS_READ : 1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S4_AXI_SUPPORTS_WRITE : 1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S5_AXI_ADDED_AXI_PARAMS : TRUE {} CONSTANT}
|
||||
{SENDING PARAMETER: C_S5_AXI_ADDR_WIDTH : 32 INTEGER CONSTANT}
|
||||
{SENDING PARAMETER: C_S5_AXI_AXI_VER : 1.01.a {} CONSTANT}
|
||||
{SENDING PARAMETER: C_S5_AXI_BASEADDR : 0xFFFFFFFF STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S5_AXI_DATA_WIDTH : 32 INTEGER CONSTANT}
|
||||
{SENDING PARAMETER: C_S5_AXI_ENABLE : 0 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_S5_AXI_ENABLE_AP : 0 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_S5_AXI_HIGHADDR : 0x00000000 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S5_AXI_ID_WIDTH : 4 INTEGER UPDATE}
|
||||
{SENDING PARAMETER: C_S5_AXI_PROTOCOL : AXI4 STRING CONSTANT}
|
||||
{SENDING PARAMETER: C_S5_AXI_REG_EN0 : 0x00000 STD_LOGIC_VECTOR OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S5_AXI_REG_EN1 : 0x01000 STD_LOGIC_VECTOR OPTIONAL}
|
||||
{SENDING PARAMETER: C_S5_AXI_STRICT_COHERENCY : 1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S5_AXI_SUPPORTS_NARROW_BURST : Auto INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S5_AXI_SUPPORTS_READ : 1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_S5_AXI_SUPPORTS_WRITE : 1 INTEGER OPTIONAL_UPDATE}
|
||||
{SENDING PARAMETER: C_SIMULATION : FALSE STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_SKIP_IN_TERM_CAL : 0 INTEGER OPTIONAL}
|
||||
{SENDING PARAMETER: C_SKIP_IN_TERM_CAL_VALUE : NONE STRING OPTIONAL}
|
||||
{SENDING PARAMETER: C_SYS_RST_PRESENT : 1 INTEGER UPDATE}
|
||||
{SENDING PARAMETER: HW_VER : 1.02.a {} {}}
|
||||
{SENDING PARAMETER: INSTANCE : MCB_DDR3 {} {}}
|
||||
{Executing C:/devtools/Xilinx/13.1/ISE_DS/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_v3_7/bin/nt/mig.exe -cg_exc_inp mig_input.txt -cg_exc_out mig_output.txt}
|
||||
{SET: IGNORE C_MCB_LOC = MEMC3 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_MEM_DDR3_ODS = DIV6 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_MCB_ZIO_LOC = R7 (BATCH:OPTIONAL::MHS:COMPVAL)}
|
||||
{SET: UPDATE C_S4_AXI_SUPPORTS_WRITE = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_S0_AXI_BASEADDR = 0x80000000 (BATCH:OPTIONAL::MHS:COMPVAL)}
|
||||
{SET: IGNORE C_MEM_MDDR_ODS = FULL (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_MEM_DDR2_DIFF_DQS_EN = YES (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_S2_AXI_ENABLE = 0 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_S0_AXI_DATA_WIDTH = 32 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: CHECK C_MEM_NUM_COL_BITS = 10 (BATCH:OPTIONAL_UPDATE:CHECK:MPD:MPDVAL)}
|
||||
{SET: IGNORE C_MEM_DDR3_RTT = DIV4 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: UPDREM C_MEM_CAS_LATENCY = 6 (BATCH:UPDATE::MPD:MPDVAL)}
|
||||
{SET: UPDATE C_MEM_TRFC = 160000 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_INTERCONNECT_S0_AXI_AR_REGISTER = 1 (BATCH:OPTIONAL::MHS:COMPVAL)}
|
||||
{SET: UPDATE C_S3_AXI_SUPPORTS_READ = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_S0_AXI_SUPPORTS_NARROW_BURST = Auto (BATCH:OPTIONAL_UPDATE::MPD:DEFVAL)}
|
||||
{SET: IGNORE C_S0_AXI_STRICT_COHERENCY = 0 (BATCH:OPTIONAL_UPDATE::MHS:COMPVAL)}
|
||||
{SET: IGNORE C_ARB_TIME_SLOT_10 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_INTERCONNECT_S0_AXI_SECURE = 0 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_ARB_TIME_SLOT_11 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_ARB_NUM_TIME_SLOTS = 12 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_S5_AXI_ENABLE = 0 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: UPDATE C_S2_AXI_SUPPORTS_WRITE = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: UPDATE C_MEM_TRTP = 7500 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: UPDATE C_MEM_TREFI = 7800000 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE = 4 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_INTERCONNECT_S0_AXI_READ_FIFO_DEPTH = 0 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_S0_AXI_ENABLE = 1 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_MEM_MOBILE_PA_SR = FULL (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_SKIP_IN_TERM_CAL = 0 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_MEM_DDR2_3_HIGH_TEMP_SR = NORMAL (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: UPDREM C_S0_AXI_SUPPORTS_READ = 1 (BATCH:OPTIONAL_UPDATE::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_S0_AXI_HIGHADDR = 0x807FFFFF (BATCH:OPTIONAL::MHS:COMPVAL)}
|
||||
{SET: IGNORE C_MEM_DDR1_2_ODS = FULL (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_MEM_TYPE = DDR3 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: CHECK C_MEM_ADDR_WIDTH = 13 (BATCH:OPTIONAL_UPDATE:CHECK:MPD:MPDVAL)}
|
||||
{SET: UPDATE C_S5_AXI_SUPPORTS_WRITE = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: UPDATE C_S4_AXI_SUPPORTS_READ = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_S0_AXI_ENABLE_AP = 0 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: UPDATE C_MEM_TWR = 15000 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_S3_AXI_ENABLE = 0 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: UPDREM C_S0_AXI_SUPPORTS_WRITE = 1 (BATCH:OPTIONAL_UPDATE::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_S0_AXI_ADDR_WIDTH = 32 (BATCH:CONSTANT::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_INTERCONNECT_S0_AXI_MASTERS = microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM (BATCH:OPTIONAL::MHS:COMPVAL)}
|
||||
{SET: IGNORE C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODS = CLASS_II (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE = 4 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: UPDREM C_MEM_DDR3_CAS_WR_LATENCY = 5 (BATCH:UPDATE::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_INTERCONNECT_S0_AXI_WRITE_FIFO_DEPTH = 0 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_INTERCONNECT_S0_AXI_W_REGISTER = 1 (BATCH:OPTIONAL::MHS:COMPVAL)}
|
||||
{SET: IGNORE C_MEM_DDR2_RTT = 150OHMS (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_MCB_PERFORMANCE = STANDARD (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: CHECK C_MEM_BANKADDR_WIDTH = 3 (BATCH:OPTIONAL_UPDATE:CHECK:MPD:MPDVAL)}
|
||||
{SET: IGNORE C_INTERCONNECT_S0_AXI_B_REGISTER = 1 (BATCH:OPTIONAL::MHS:COMPVAL)}
|
||||
{SET: IGNORE C_SIMULATION = FALSE (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: UPDATE C_S1_AXI_SUPPORTS_READ = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: UPDATE C_MEM_TWTR = 7500 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: UPDATE C_S3_AXI_SUPPORTS_WRITE = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: UPDATE C_MEM_TRAS = 37500 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: UPDREM C_MEM_DDR3_CAS_LATENCY = 6 (BATCH:UPDATE::MPD:MPDVAL)}
|
||||
{SET: UPDATE C_S5_AXI_SUPPORTS_READ = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_S1_AXI_ENABLE = 0 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: UPDATE C_MEM_TRCD = 13130 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_ARB_TIME_SLOT_0 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_ARB_ALGORITHM = 0 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: UPDATE C_MEM_TRP = 13130 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_ARB_TIME_SLOT_1 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODS = CLASS_II (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_ARB_TIME_SLOT_2 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_ARB_TIME_SLOT_3 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_MEM_DDR3_AUTO_SR = ENABLED (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_ARB_TIME_SLOT_4 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_ARB_TIME_SLOT_5 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_ARB_TIME_SLOT_6 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_INTERCONNECT_S0_AXI_AW_REGISTER = 1 (BATCH:OPTIONAL::MHS:COMPVAL)}
|
||||
{SET: IGNORE C_ARB_TIME_SLOT_7 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_MEMCLK_PERIOD = 0 (BATCH:OPTIONAL_UPDATE:SKIP_BATCH:MPD:MPDVAL)}
|
||||
{SET: IGNORE C_MCB_RZQ_LOC = K7 (BATCH:OPTIONAL::MHS:COMPVAL)}
|
||||
{SET: IGNORE C_ARB_TIME_SLOT_8 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_MEM_ADDR_ORDER = ROW_BANK_COLUMN (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_MCB_USE_EXTERNAL_BUFPLL = 0 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_INTERCONNECT_S0_AXI_R_REGISTER = 1 (BATCH:OPTIONAL::MHS:COMPVAL)}
|
||||
{SET: IGNORE C_ARB_TIME_SLOT_9 = 0b000000000000000000 (BATCH:OPTIONAL::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_S4_AXI_ENABLE = 0 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: UPDATE C_S1_AXI_SUPPORTS_WRITE = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_SKIP_IN_TERM_CAL_VALUE = NONE (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: UPDATE C_S2_AXI_SUPPORTS_READ = 0 (BATCH:OPTIONAL_UPDATE::MPD:COMPVAL)}
|
||||
{SET: IGNORE C_MEM_DDR2_3_PA_SR = FULL (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_PORT_CONFIG = B32_B32_B32_B32 (BATCH:OPTIONAL::MPD:MPDVAL)}
|
||||
{SET: IGNORE C_MEM_PARTNO = MT41J64M16XX-187E (BATCH:REQUIRE::MHS:COMPVAL)}
|
||||
{SET: CHECK C_NUM_DQ_PINS = 16 (BATCH:OPTIONAL_UPDATE:CHECK:MPD:MPDVAL)}
|
||||
RETURN: 0
|
||||
@ -1,565 +0,0 @@
|
||||
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
|
||||
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
|
||||
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>Project Status (08/27/2011 - 12:37:45)</B></TD></TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
|
||||
<TD>system.xmp</TD>
|
||||
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
|
||||
<TD>Programming File Generated</TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
|
||||
<TD>system</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
|
||||
<TD>
|
||||
No Errors</TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>EDK 13.1</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
|
||||
<TD ALIGN=LEFT><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject\implementation\_xmsgs/*.xmsgs?&DataKey=Warning'>238 Warnings (0 new)</A></TD>
|
||||
</TR>
|
||||
</TABLE>
|
||||
|
||||
|
||||
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>XPS Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=EDKReports"><B>[-]</B></a></TD></TR>
|
||||
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Generated</B></TD>
|
||||
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject\platgen.log'>Platgen Log File</A></TD><TD>Sat 27. Aug 12:17:02 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject\__xps/ise/_xmsgs/platgen.xmsgs?&DataKey=Warning'>19 Warnings (18 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject\__xps/ise/_xmsgs/platgen.xmsgs?&DataKey=Info'>34 Infos (32 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Libgen Log File</TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Simgen Log File</TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD>BitInit Log File</TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject\system.log'>System Log File</A></TD><TD>Sat 27. Aug 12:34:09 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
</TABLE>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>XPS Synthesis Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=EDKSynthesisSumary"><B>[-]</B></a></TD></TR>
|
||||
<TR BGCOLOR='#FFFF99'><TD><B>Report</B></TD><TD><B>Generated</B></TD><TD><B>Flip Flops Used</B></TD><TD><B>LUTs Used</B></TD><TD><B>BRAMS Used</B></TD><TD COLSPAN='2'><B>Errors</B></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/synthesis\system_xst.srp'>system</A></TD><TD>Sat 27. Aug 12:17:50 2011</TD><TD ALIGN=RIGHT>14696</TD><TD ALIGN=RIGHT>14247</TD><TD ALIGN=RIGHT>14</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/synthesis\mcb_ddr3_wrapper_xst.srp'>mcb_ddr3_wrapper</A></TD><TD>Sat 27. Aug 12:16:50 2011</TD><TD ALIGN=RIGHT>373</TD><TD ALIGN=RIGHT>690</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/synthesis\debug_module_wrapper_xst.srp'>debug_module_wrapper</A></TD><TD>Sat 27. Aug 12:16:27 2011</TD><TD ALIGN=RIGHT>131</TD><TD ALIGN=RIGHT>142</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/synthesis\clock_generator_0_wrapper_xst.srp'>clock_generator_0_wrapper</A></TD><TD>Sat 27. Aug 12:16:17 2011</TD><TD> </TD><TD ALIGN=RIGHT>1</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/synthesis\microblaze_0_bram_block_wrapper_xst.srp'>microblaze_0_bram_block_wrapper</A></TD><TD>Sat 27. Aug 12:16:12 2011</TD><TD> </TD><TD> </TD><TD ALIGN=RIGHT>4</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/synthesis\microblaze_0_d_bram_ctrl_wrapper_xst.srp'>microblaze_0_d_bram_ctrl_wrapper</A></TD><TD>Sat 27. Aug 12:16:06 2011</TD><TD ALIGN=RIGHT>2</TD><TD ALIGN=RIGHT>6</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/synthesis\microblaze_0_i_bram_ctrl_wrapper_xst.srp'>microblaze_0_i_bram_ctrl_wrapper</A></TD><TD>Sat 27. Aug 12:16:01 2011</TD><TD ALIGN=RIGHT>2</TD><TD ALIGN=RIGHT>6</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/synthesis\axi4lite_0_wrapper_xst.srp'>axi4lite_0_wrapper</A></TD><TD>Sat 27. Aug 12:15:55 2011</TD><TD ALIGN=RIGHT>2905</TD><TD ALIGN=RIGHT>1827</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/synthesis\axi_timer_0_wrapper_xst.srp'>axi_timer_0_wrapper</A></TD><TD>Fri 26. Aug 21:17:55 2011</TD><TD ALIGN=RIGHT>260</TD><TD ALIGN=RIGHT>272</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/synthesis\microblaze_0_intc_wrapper_xst.srp'>microblaze_0_intc_wrapper</A></TD><TD>Fri 26. Aug 21:17:45 2011</TD><TD ALIGN=RIGHT>86</TD><TD ALIGN=RIGHT>115</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/synthesis\ethernet_dma_wrapper_xst.srp'>ethernet_dma_wrapper</A></TD><TD>Fri 26. Aug 21:17:37 2011</TD><TD ALIGN=RIGHT>3728</TD><TD ALIGN=RIGHT>3798</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD>ethernet_dma_wrapper_fifo_generator_v8_1_6_fifo_generator_v8_1_xst_1</TD><TD>Fri 26. Aug 21:16:56 2011</TD><TD ALIGN=RIGHT>107</TD><TD ALIGN=RIGHT>109</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD>ethernet_dma_wrapper_fifo_generator_v8_1_7_fifo_generator_v8_1_xst_1</TD><TD>Fri 26. Aug 21:15:53 2011</TD><TD ALIGN=RIGHT>98</TD><TD ALIGN=RIGHT>100</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD>ethernet_dma_wrapper_fifo_generator_v8_1_2_fifo_generator_v8_1_xst_1</TD><TD>Fri 26. Aug 21:14:50 2011</TD><TD ALIGN=RIGHT>68</TD><TD ALIGN=RIGHT>49</TD><TD ALIGN=RIGHT>1</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD>ethernet_dma_wrapper_fifo_generator_v8_1_1_fifo_generator_v8_1_xst_1</TD><TD>Fri 26. Aug 21:13:47 2011</TD><TD ALIGN=RIGHT>74</TD><TD ALIGN=RIGHT>59</TD><TD ALIGN=RIGHT>1</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD>ethernet_dma_wrapper_fifo_generator_v8_1_5_fifo_generator_v8_1_xst_1</TD><TD>Fri 26. Aug 21:12:44 2011</TD><TD ALIGN=RIGHT>69</TD><TD ALIGN=RIGHT>49</TD><TD ALIGN=RIGHT>1</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD>ethernet_dma_wrapper_fifo_generator_v8_1_4_fifo_generator_v8_1_xst_1</TD><TD>Fri 26. Aug 21:11:41 2011</TD><TD ALIGN=RIGHT>99</TD><TD ALIGN=RIGHT>103</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD>ethernet_dma_wrapper_fifo_generator_v8_1_3_fifo_generator_v8_1_xst_1</TD><TD>Fri 26. Aug 21:10:39 2011</TD><TD ALIGN=RIGHT>97</TD><TD ALIGN=RIGHT>98</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/synthesis\ethernet_wrapper_xst.srp'>ethernet_wrapper</A></TD><TD>Fri 26. Aug 21:09:24 2011</TD><TD ALIGN=RIGHT>3166</TD><TD ALIGN=RIGHT>3264</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD>ethernet_wrapper_fifo_generator_v8_1_fifo_generator_v8_1_xst_1</TD><TD>Fri 26. Aug 21:08:27 2011</TD><TD ALIGN=RIGHT>104</TD><TD ALIGN=RIGHT>148</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD>ethernet_wrapper_blk_mem_gen_v5_2_2_blk_mem_gen_v5_2_xst_1</TD><TD>Fri 26. Aug 21:07:29 2011</TD><TD> </TD><TD> </TD><TD ALIGN=RIGHT>1</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD>ethernet_wrapper_blk_mem_gen_v5_2_1_blk_mem_gen_v5_2_xst_1</TD><TD>Fri 26. Aug 21:07:03 2011</TD><TD> </TD><TD> </TD><TD ALIGN=RIGHT>2</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD>ethernet_wrapper_blk_mem_gen_v5_2_4_blk_mem_gen_v5_2_xst_1</TD><TD>Fri 26. Aug 21:06:36 2011</TD><TD> </TD><TD> </TD><TD ALIGN=RIGHT>1</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD>ethernet_wrapper_blk_mem_gen_v5_2_3_blk_mem_gen_v5_2_xst_1</TD><TD>Fri 26. Aug 21:06:10 2011</TD><TD ALIGN=RIGHT>2</TD><TD ALIGN=RIGHT>49</TD><TD ALIGN=RIGHT>2</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/synthesis\push_buttons_4bits_wrapper_xst.srp'>push_buttons_4bits_wrapper</A></TD><TD>Fri 26. Aug 21:04:24 2011</TD><TD ALIGN=RIGHT>72</TD><TD ALIGN=RIGHT>85</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/synthesis\leds_4bits_wrapper_xst.srp'>leds_4bits_wrapper</A></TD><TD>Fri 26. Aug 21:04:14 2011</TD><TD ALIGN=RIGHT>33</TD><TD ALIGN=RIGHT>41</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/synthesis\rs232_uart_1_wrapper_xst.srp'>rs232_uart_1_wrapper</A></TD><TD>Fri 26. Aug 21:04:05 2011</TD><TD ALIGN=RIGHT>84</TD><TD ALIGN=RIGHT>102</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/synthesis\proc_sys_reset_0_wrapper_xst.srp'>proc_sys_reset_0_wrapper</A></TD><TD>Fri 26. Aug 21:03:43 2011</TD><TD ALIGN=RIGHT>69</TD><TD ALIGN=RIGHT>55</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/synthesis\microblaze_0_dlmb_wrapper_xst.srp'>microblaze_0_dlmb_wrapper</A></TD><TD>Fri 26. Aug 21:03:19 2011</TD><TD ALIGN=RIGHT>1</TD><TD ALIGN=RIGHT>1</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/synthesis\microblaze_0_ilmb_wrapper_xst.srp'>microblaze_0_ilmb_wrapper</A></TD><TD>Fri 26. Aug 21:03:15 2011</TD><TD ALIGN=RIGHT>1</TD><TD ALIGN=RIGHT>1</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/synthesis\microblaze_0_wrapper_xst.srp'>microblaze_0_wrapper</A></TD><TD>Fri 26. Aug 21:03:10 2011</TD><TD ALIGN=RIGHT>1301</TD><TD ALIGN=RIGHT>1703</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/synthesis\axi4_0_wrapper_xst.srp'>axi4_0_wrapper</A></TD><TD>Fri 26. Aug 21:02:14 2011</TD><TD ALIGN=RIGHT>1488</TD><TD ALIGN=RIGHT>1083</TD><TD> </TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD>axi4_0_wrapper_FIFO_GENERATOR_V8_1_2_fifo_generator_v8_1_xst_1</TD><TD>Fri 26. Aug 21:01:57 2011</TD><TD ALIGN=RIGHT>90</TD><TD ALIGN=RIGHT>97</TD><TD ALIGN=RIGHT>2</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD>axi4_0_wrapper_FIFO_GENERATOR_V8_1_1_fifo_generator_v8_1_xst_1</TD><TD>Fri 26. Aug 21:00:49 2011</TD><TD ALIGN=RIGHT>89</TD><TD ALIGN=RIGHT>96</TD><TD ALIGN=RIGHT>1</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
|
||||
</TABLE>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary (actual values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>
|
||||
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
|
||||
<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
|
||||
<TD ALIGN=RIGHT>12,060</TD>
|
||||
<TD ALIGN=RIGHT>54,576</TD>
|
||||
<TD ALIGN=RIGHT>22%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Flip Flops</TD>
|
||||
<TD ALIGN=RIGHT>12,052</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Latches</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Latch-thrus</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as AND/OR logics</TD>
|
||||
<TD ALIGN=RIGHT>8</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
|
||||
<TD ALIGN=RIGHT>10,940</TD>
|
||||
<TD ALIGN=RIGHT>27,288</TD>
|
||||
<TD ALIGN=RIGHT>40%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as logic</TD>
|
||||
<TD ALIGN=RIGHT>9,639</TD>
|
||||
<TD ALIGN=RIGHT>27,288</TD>
|
||||
<TD ALIGN=RIGHT>35%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O6 output only</TD>
|
||||
<TD ALIGN=RIGHT>6,889</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 output only</TD>
|
||||
<TD ALIGN=RIGHT>260</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 and O6</TD>
|
||||
<TD ALIGN=RIGHT>2,490</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as ROM</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Memory</TD>
|
||||
<TD ALIGN=RIGHT>693</TD>
|
||||
<TD ALIGN=RIGHT>6,408</TD>
|
||||
<TD ALIGN=RIGHT>10%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Dual Port RAM</TD>
|
||||
<TD ALIGN=RIGHT>250</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O6 output only</TD>
|
||||
<TD ALIGN=RIGHT>10</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 output only</TD>
|
||||
<TD ALIGN=RIGHT>4</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 and O6</TD>
|
||||
<TD ALIGN=RIGHT>236</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Single Port RAM</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O6 output only</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 output only</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 and O6</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Shift Register</TD>
|
||||
<TD ALIGN=RIGHT>442</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O6 output only</TD>
|
||||
<TD ALIGN=RIGHT>205</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 output only</TD>
|
||||
<TD ALIGN=RIGHT>7</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 and O6</TD>
|
||||
<TD ALIGN=RIGHT>230</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used exclusively as route-thrus</TD>
|
||||
<TD ALIGN=RIGHT>608</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with same-slice register load</TD>
|
||||
<TD ALIGN=RIGHT>566</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with same-slice carry load</TD>
|
||||
<TD ALIGN=RIGHT>37</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with other load</TD>
|
||||
<TD ALIGN=RIGHT>5</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
|
||||
<TD ALIGN=RIGHT>4,589</TD>
|
||||
<TD ALIGN=RIGHT>6,822</TD>
|
||||
<TD ALIGN=RIGHT>67%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
|
||||
<TD ALIGN=RIGHT>13,843</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused Flip Flop</TD>
|
||||
<TD ALIGN=RIGHT>3,765</TD>
|
||||
<TD ALIGN=RIGHT>13,843</TD>
|
||||
<TD ALIGN=RIGHT>27%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused LUT</TD>
|
||||
<TD ALIGN=RIGHT>2,903</TD>
|
||||
<TD ALIGN=RIGHT>13,843</TD>
|
||||
<TD ALIGN=RIGHT>20%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of fully used LUT-FF pairs</TD>
|
||||
<TD ALIGN=RIGHT>7,175</TD>
|
||||
<TD ALIGN=RIGHT>13,843</TD>
|
||||
<TD ALIGN=RIGHT>51%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of unique control sets</TD>
|
||||
<TD ALIGN=RIGHT>697</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of slice register sites lost<BR> to control set restrictions</TD>
|
||||
<TD ALIGN=RIGHT>2,541</TD>
|
||||
<TD ALIGN=RIGHT>54,576</TD>
|
||||
<TD ALIGN=RIGHT>4%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject\implementation\system_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
|
||||
<TD ALIGN=RIGHT>87</TD>
|
||||
<TD ALIGN=RIGHT>296</TD>
|
||||
<TD ALIGN=RIGHT>29%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of LOCed IOBs</TD>
|
||||
<TD ALIGN=RIGHT>87</TD>
|
||||
<TD ALIGN=RIGHT>87</TD>
|
||||
<TD ALIGN=RIGHT>100%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> IOB Flip Flops</TD>
|
||||
<TD ALIGN=RIGHT>27</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD>
|
||||
<TD ALIGN=RIGHT>12</TD>
|
||||
<TD ALIGN=RIGHT>116</TD>
|
||||
<TD ALIGN=RIGHT>10%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD>
|
||||
<TD ALIGN=RIGHT>4</TD>
|
||||
<TD ALIGN=RIGHT>232</TD>
|
||||
<TD ALIGN=RIGHT>1%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD>
|
||||
<TD ALIGN=RIGHT>3</TD>
|
||||
<TD ALIGN=RIGHT>32</TD>
|
||||
<TD ALIGN=RIGHT>9%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFIO2s</TD>
|
||||
<TD ALIGN=RIGHT>3</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFIO2_2CLKs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2FB/BUFIO2FB_2CLKs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>32</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD>
|
||||
<TD ALIGN=RIGHT>6</TD>
|
||||
<TD ALIGN=RIGHT>16</TD>
|
||||
<TD ALIGN=RIGHT>37%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFGs</TD>
|
||||
<TD ALIGN=RIGHT>5</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFGMUX</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCM/DCM_CLKGENs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>8</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGIC2/ISERDES2s</TD>
|
||||
<TD ALIGN=RIGHT>12</TD>
|
||||
<TD ALIGN=RIGHT>376</TD>
|
||||
<TD ALIGN=RIGHT>3%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as ILOGIC2s</TD>
|
||||
<TD ALIGN=RIGHT>12</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as ISERDES2s</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IODELAY2/IODRP2/IODRP2_MCBs</TD>
|
||||
<TD ALIGN=RIGHT>34</TD>
|
||||
<TD ALIGN=RIGHT>376</TD>
|
||||
<TD ALIGN=RIGHT>9%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as IODELAY2s</TD>
|
||||
<TD ALIGN=RIGHT>10</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as IODRP2s</TD>
|
||||
<TD ALIGN=RIGHT>2</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as IODRP2_MCBs</TD>
|
||||
<TD ALIGN=RIGHT>22</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OLOGIC2/OSERDES2s</TD>
|
||||
<TD ALIGN=RIGHT>60</TD>
|
||||
<TD ALIGN=RIGHT>376</TD>
|
||||
<TD ALIGN=RIGHT>15%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as OLOGIC2s</TD>
|
||||
<TD ALIGN=RIGHT>14</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as OSERDES2s</TD>
|
||||
<TD ALIGN=RIGHT>46</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BSCANs</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD ALIGN=RIGHT>4</TD>
|
||||
<TD ALIGN=RIGHT>25%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFHs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>256</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLLs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>8</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLL_MCBs</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD ALIGN=RIGHT>4</TD>
|
||||
<TD ALIGN=RIGHT>25%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DSP48A1s</TD>
|
||||
<TD ALIGN=RIGHT>3</TD>
|
||||
<TD ALIGN=RIGHT>58</TD>
|
||||
<TD ALIGN=RIGHT>5%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of GTPA1_DUALs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>2</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ICAPs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MCBs</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD ALIGN=RIGHT>2</TD>
|
||||
<TD ALIGN=RIGHT>50%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCIE_A1s</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCILOGICSEs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>2</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PLL_ADVs</TD>
|
||||
<TD ALIGN=RIGHT>2</TD>
|
||||
<TD ALIGN=RIGHT>4</TD>
|
||||
<TD ALIGN=RIGHT>50%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PMVs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of STARTUPs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of SUSPEND_SYNCs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
|
||||
<TD ALIGN=RIGHT>3.89</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
</TABLE>
|
||||
|
||||
|
||||
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
|
||||
<TD>0 (Setup: 0, Hold: 0, Component Switching Limit: 0)</TD>
|
||||
<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
|
||||
<TD COLSPAN='2'><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject\implementation\system_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
|
||||
<A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject\implementation\system.unroutes'>All Signals Completely Routed</A></TD>
|
||||
<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
|
||||
<TD COLSPAN='2'><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject\implementation\system_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
|
||||
<TD>
|
||||
<A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject\implementation\system.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
|
||||
<TD BGCOLOR='#FFFF99'><B> </B></TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TABLE>
|
||||
|
||||
|
||||
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
|
||||
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
|
||||
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject\implementation\system.bld'>Translation Report</A></TD><TD>Current</TD><TD>Sat 27. Aug 12:19:05 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject\implementation\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>87 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject\implementation\_xmsgs/ngdbuild.xmsgs?&DataKey=Info'>13 Infos (8 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject\implementation\system_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Sat 27. Aug 12:28:13 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject\implementation\_xmsgs/map.xmsgs?&DataKey=Warning'>50 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject\implementation\_xmsgs/map.xmsgs?&DataKey=Info'>1134 Infos (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject\implementation\system.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Sat 27. Aug 12:31:43 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject\implementation\_xmsgs/par.xmsgs?&DataKey=Warning'>51 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject\implementation\_xmsgs/par.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject\implementation\system.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Sat 27. Aug 12:32:50 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject\implementation\_xmsgs/trce.xmsgs?&DataKey=Warning'>3 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject\implementation\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject\implementation\system.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Sat 27. Aug 12:34:09 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject\implementation\_xmsgs/bitgen.xmsgs?&DataKey=Warning'>47 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
|
||||
</TABLE>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
|
||||
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject\implementation\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Sat 27. Aug 12:34:09 2011</TD></TR>
|
||||
</TABLE>
|
||||
|
||||
|
||||
<br><center><b>Date Generated:</b> 08/27/2011 - 12:37:46</center>
|
||||
</BODY></HTML>
|
||||
Loading…
Reference in New Issue