From 68ddb32b55be1bbe74977f79aedb8470a97b7542 Mon Sep 17 00:00:00 2001 From: Stephane Viau <84857962+sviaunxp@users.noreply.github.com> Date: Fri, 15 Oct 2021 18:21:56 +0200 Subject: [PATCH] Handle interrupt acknowledge register in Cortex-A53 SRE port (#392) Let the FreeRTOS IRQ handler properly store and restore the ICCIAR register value around the vApplicationIRQHandler() call. Signed-off-by: Stephane Viau Co-authored-by: Stephane Viau Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com> --- portable/GCC/ARM_CA53_64_BIT_SRE/portASM.S | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/portable/GCC/ARM_CA53_64_BIT_SRE/portASM.S b/portable/GCC/ARM_CA53_64_BIT_SRE/portASM.S index 79a5465b7..7df2b27e6 100644 --- a/portable/GCC/ARM_CA53_64_BIT_SRE/portASM.S +++ b/portable/GCC/ARM_CA53_64_BIT_SRE/portASM.S @@ -303,6 +303,13 @@ FreeRTOS_IRQ_Handler: /* Maintain the interrupt nesting information across the function call. */ STP X1, X5, [SP, #-0x10]! + /* Read value from the interrupt acknowledge register, which is stored in W0 + for future parameter and interrupt clearing use. */ + MRS X0, S3_0_C12_C12_0 /* read ICC_IAR1_EL1 and store ICCIAR in X0 as parameter */ + + /* Maintain the ICCIAR value across the function call. */ + STP X0, X1, [SP, #-0x10]! + /* Call the C handler. */ BL vApplicationIRQHandler @@ -311,6 +318,12 @@ FreeRTOS_IRQ_Handler: DSB SY ISB SY + /* Restore the ICCIAR value. */ + LDP X0, X1, [SP], #0x10 + + /* End IRQ processing by writing ICCIAR to the EOI register. */ + MSR S3_0_C12_C12_1, X0 /* ICC_EOIR1_EL1 */ + /* Restore the critical nesting count. */ LDP X1, X5, [SP], #0x10 STR X1, [X5]