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@ -1,6 +1,5 @@
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/******************************************************************
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***** *****
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***** Name: cs8900.c *****
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***** Ver.: 1.0 *****
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***** Date: 07/05/2001 *****
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***** Auth: Andreas Dannenberg *****
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@ -16,416 +15,451 @@
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******************************************************************/
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/* Adapted from file originally written by Andreas Dannenberg. Supplied with permission. */
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#include "FreeRTOS.h"
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#include "semphr.h"
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#include "semphr.h"
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#include "task.h"
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#include "emac.h"
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#include "LPC17xx_defs.h"
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#define configPINSEL2_VALUE 0x50150105
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#define configPINSEL2_VALUE 0x50150105
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/* The semaphore used to wake the uIP task when data arives. */
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xSemaphoreHandle xEMACSemaphore = NULL;
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static unsigned short *rptr;
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static unsigned short *tptr;
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xSemaphoreHandle xEMACSemaphore = NULL;
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// easyWEB internal function
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// help function to swap the byte order of a WORD
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static unsigned short *rptr;
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static unsigned short *tptr;
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static unsigned short SwapBytes(unsigned short Data)
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static unsigned short SwapBytes( unsigned short Data )
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{
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return (Data >> 8) | (Data << 8);
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return( Data >> 8 ) | ( Data << 8 );
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}
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// Keil: function added to write PHY
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void write_PHY (int PhyReg, int Value)
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int write_PHY( int PhyReg, int Value )
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{
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unsigned int tout;
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const unsigned int uiMaxTime = 10;
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MAC_MADR = DP83848C_DEF_ADR | PhyReg;
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MAC_MWTD = Value;
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/* Wait utill operation completed */
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tout = 0;
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for (tout = 0; tout < uiMaxTime; tout++) {
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if ((MAC_MIND & MIND_BUSY) == 0) {
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break;
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}
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vTaskDelay( 2 );
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}
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unsigned int tout;
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const unsigned int uiMaxTime = 10;
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MAC_MADR = DP83848C_DEF_ADR | PhyReg;
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MAC_MWTD = Value;
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/* Wait utill operation completed */
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tout = 0;
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for( tout = 0; tout < uiMaxTime; tout++ )
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{
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if( (MAC_MIND & MIND_BUSY) == 0 )
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{
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break;
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}
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vTaskDelay( 2 );
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}
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if( tout < uiMaxTime )
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{
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return pdPASS;
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}
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else
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{
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return pdFAIL;
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}
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}
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// Keil: function added to read PHY
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unsigned short read_PHY (unsigned char PhyReg)
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unsigned short read_PHY( unsigned char PhyReg, portBASE_TYPE *pxStatus )
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{
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unsigned int tout;
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const unsigned int uiMaxTime = 10;
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MAC_MADR = DP83848C_DEF_ADR | PhyReg;
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MAC_MCMD = MCMD_READ;
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/* Wait until operation completed */
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tout = 0;
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for (tout = 0; tout < uiMaxTime; tout++) {
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if ((MAC_MIND & MIND_BUSY) == 0) {
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break;
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}
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vTaskDelay( 2 );
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}
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MAC_MCMD = 0;
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return (MAC_MRDD);
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}
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unsigned int tout;
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const unsigned int uiMaxTime = 10;
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MAC_MADR = DP83848C_DEF_ADR | PhyReg;
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MAC_MCMD = MCMD_READ;
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/* Wait until operation completed */
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tout = 0;
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for( tout = 0; tout < uiMaxTime; tout++ )
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{
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if( (MAC_MIND & MIND_BUSY) == 0 )
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{
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break;
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}
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vTaskDelay( 2 );
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}
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MAC_MCMD = 0;
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if( tout >= uiMaxTime )
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{
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*pxStatus = pdFAIL;
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}
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return( MAC_MRDD );
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}
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// Keil: function added to initialize Rx Descriptors
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void rx_descr_init (void)
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void rx_descr_init( void )
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{
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unsigned int i;
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for (i = 0; i < NUM_RX_FRAG; i++) {
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RX_DESC_PACKET(i) = RX_BUF(i);
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RX_DESC_CTRL(i) = RCTRL_INT | (ETH_FRAG_SIZE-1);
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RX_STAT_INFO(i) = 0;
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RX_STAT_HASHCRC(i) = 0;
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}
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/* Set EMAC Receive Descriptor Registers. */
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MAC_RXDESCRIPTOR = RX_DESC_BASE;
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MAC_RXSTATUS = RX_STAT_BASE;
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MAC_RXDESCRIPTORNUM = NUM_RX_FRAG-1;
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/* Rx Descriptors Point to 0 */
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MAC_RXCONSUMEINDEX = 0;
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unsigned int i;
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for( i = 0; i < NUM_RX_FRAG; i++ )
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{
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RX_DESC_PACKET( i ) = RX_BUF( i );
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RX_DESC_CTRL( i ) = RCTRL_INT | ( ETH_FRAG_SIZE - 1 );
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RX_STAT_INFO( i ) = 0;
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RX_STAT_HASHCRC( i ) = 0;
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}
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/* Set EMAC Receive Descriptor Registers. */
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MAC_RXDESCRIPTOR = RX_DESC_BASE;
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MAC_RXSTATUS = RX_STAT_BASE;
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MAC_RXDESCRIPTORNUM = NUM_RX_FRAG - 1;
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/* Rx Descriptors Point to 0 */
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MAC_RXCONSUMEINDEX = 0;
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}
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// Keil: function added to initialize Tx Descriptors
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void tx_descr_init (void) {
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unsigned int i;
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for (i = 0; i < NUM_TX_FRAG; i++) {
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TX_DESC_PACKET(i) = TX_BUF(i);
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TX_DESC_CTRL(i) = 0;
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TX_STAT_INFO(i) = 0;
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}
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/* Set EMAC Transmit Descriptor Registers. */
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MAC_TXDESCRIPTOR = TX_DESC_BASE;
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MAC_TXSTATUS = TX_STAT_BASE;
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MAC_TXDESCRIPTORNUM = NUM_TX_FRAG-1;
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/* Tx Descriptors Point to 0 */
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MAC_TXPRODUCEINDEX = 0;
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void tx_descr_init( void )
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{
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unsigned int i;
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for( i = 0; i < NUM_TX_FRAG; i++ )
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{
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TX_DESC_PACKET( i ) = TX_BUF( i );
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TX_DESC_CTRL( i ) = 0;
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TX_STAT_INFO( i ) = 0;
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}
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/* Set EMAC Transmit Descriptor Registers. */
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MAC_TXDESCRIPTOR = TX_DESC_BASE;
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MAC_TXSTATUS = TX_STAT_BASE;
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MAC_TXDESCRIPTORNUM = NUM_TX_FRAG - 1;
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/* Tx Descriptors Point to 0 */
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MAC_TXPRODUCEINDEX = 0;
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}
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// configure port-pins for use with LAN-controller,
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// reset it and send the configuration-sequence
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portBASE_TYPE Init_EMAC(void)
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portBASE_TYPE Init_EMAC( void )
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{
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portBASE_TYPE xReturn = pdPASS;
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// Keil: function modified to access the EMAC
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// Initializes the EMAC ethernet controller
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volatile unsigned int regv,tout,id1,id2;
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/* Enable P1 Ethernet Pins. */
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PINSEL2 = configPINSEL2_VALUE;
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PINSEL3 = (PINSEL3 & ~0x0000000F) | 0x00000005;
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/* Power Up the EMAC controller. */
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PCONP |= PCONP_PCENET;
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vTaskDelay( 2 );
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/* Reset all EMAC internal modules. */
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MAC_MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
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MAC_COMMAND = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
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/* A short delay after reset. */
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vTaskDelay( 2 );
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/* Initialize MAC control registers. */
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MAC_MAC1 = MAC1_PASS_ALL;
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MAC_MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
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MAC_MAXF = ETH_MAX_FLEN;
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MAC_CLRT = CLRT_DEF;
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MAC_IPGR = IPGR_DEF;
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/* Enable Reduced MII interface. */
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MAC_COMMAND = CR_RMII | CR_PASS_RUNT_FRM;
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/* Reset Reduced MII Logic. */
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MAC_SUPP = SUPP_RES_RMII;
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vTaskDelay( 2 );
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MAC_SUPP = 0;
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/* Put the PHY in reset mode */
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write_PHY (PHY_REG_BMCR, 0x8000);
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write_PHY (PHY_REG_BMCR, 0x8000);
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/* Wait for hardware reset to end. */
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for (tout = 0; tout < 100; tout++) {
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vTaskDelay( 10 );
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regv = read_PHY (PHY_REG_BMCR);
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if (!(regv & 0x8000)) {
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/* Reset complete */
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break;
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}
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}
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/* Set the Ethernet MAC Address registers */
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MAC_SA0 = (emacETHADDR0 << 8) | emacETHADDR1;
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MAC_SA1 = (emacETHADDR2 << 8) | emacETHADDR3;
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MAC_SA2 = (emacETHADDR4 << 8) | emacETHADDR5;
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/* Initialize Tx and Rx DMA Descriptors */
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rx_descr_init ();
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tx_descr_init ();
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/* Receive Broadcast and Perfect Match Packets */
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MAC_RXFILTERCTRL = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
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/* Create the semaphore used ot wake the uIP task. */
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vSemaphoreCreateBinary( xEMACSemaphore );
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/* Check if this is a DP83848C PHY. */
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id1 = read_PHY (PHY_REG_IDR1);
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id2 = read_PHY (PHY_REG_IDR2);
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if (((id1 << 16) | (id2 & 0xFFF0)) == DP83848C_ID) {
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/* Configure the PHY device */
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/* Use autonegotiation about the link speed. */
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write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG);
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/* Wait to complete Auto_Negotiation. */
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for (tout = 0; tout < 10; tout++) {
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vTaskDelay( 100 );
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regv = read_PHY (PHY_REG_BMSR);
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if (regv & 0x0020) {
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/* Autonegotiation Complete. */
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break;
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}
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}
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}
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else
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{
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xReturn = pdFAIL;
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}
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/* Check the link status. */
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if( xReturn == pdPASS )
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{
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xReturn = pdFAIL;
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for (tout = 0; tout < 10; tout++) {
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vTaskDelay( 100 );
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regv = read_PHY (PHY_REG_STS);
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if (regv & 0x0001) {
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/* Link is on. */
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xReturn = pdPASS;
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break;
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}
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}
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}
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if( xReturn == pdPASS )
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{
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/* Configure Full/Half Duplex mode. */
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if (regv & 0x0004) {
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/* Full duplex is enabled. */
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MAC_MAC2 |= MAC2_FULL_DUP;
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MAC_COMMAND |= CR_FULL_DUP;
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MAC_IPGT = IPGT_FULL_DUP;
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}
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else {
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/* Half duplex mode. */
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MAC_IPGT = IPGT_HALF_DUP;
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}
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/* Configure 100MBit/10MBit mode. */
|
|
|
|
|
if (regv & 0x0002) {
|
|
|
|
|
/* 10MBit mode. */
|
|
|
|
|
MAC_SUPP = 0;
|
|
|
|
|
}
|
|
|
|
|
else {
|
|
|
|
|
/* 100MBit mode. */
|
|
|
|
|
MAC_SUPP = SUPP_SPEED;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Reset all interrupts */
|
|
|
|
|
MAC_INTCLEAR = 0xFFFF;
|
|
|
|
|
|
|
|
|
|
/* Enable receive and transmit mode of MAC Ethernet core */
|
|
|
|
|
MAC_COMMAND |= (CR_RX_EN | CR_TX_EN);
|
|
|
|
|
MAC_MAC1 |= MAC1_REC_EN;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return xReturn;
|
|
|
|
|
portBASE_TYPE xReturn = pdPASS;
|
|
|
|
|
|
|
|
|
|
// Keil: function modified to access the EMAC
|
|
|
|
|
// Initializes the EMAC ethernet controller
|
|
|
|
|
volatile unsigned int regv, tout, id1, id2;
|
|
|
|
|
|
|
|
|
|
/* Enable P1 Ethernet Pins. */
|
|
|
|
|
PINSEL2 = configPINSEL2_VALUE;
|
|
|
|
|
PINSEL3 = ( PINSEL3 &~0x0000000F ) | 0x00000005;
|
|
|
|
|
|
|
|
|
|
/* Power Up the EMAC controller. */
|
|
|
|
|
PCONP |= PCONP_PCENET;
|
|
|
|
|
vTaskDelay( 2 );
|
|
|
|
|
|
|
|
|
|
/* Reset all EMAC internal modules. */
|
|
|
|
|
MAC_MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
|
|
|
|
|
MAC_COMMAND = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
|
|
|
|
|
|
|
|
|
|
/* A short delay after reset. */
|
|
|
|
|
vTaskDelay( 2 );
|
|
|
|
|
|
|
|
|
|
/* Initialize MAC control registers. */
|
|
|
|
|
MAC_MAC1 = MAC1_PASS_ALL;
|
|
|
|
|
MAC_MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
|
|
|
|
|
MAC_MAXF = ETH_MAX_FLEN;
|
|
|
|
|
MAC_CLRT = CLRT_DEF;
|
|
|
|
|
MAC_IPGR = IPGR_DEF;
|
|
|
|
|
|
|
|
|
|
/* Enable Reduced MII interface. */
|
|
|
|
|
MAC_COMMAND = CR_RMII | CR_PASS_RUNT_FRM;
|
|
|
|
|
|
|
|
|
|
/* Reset Reduced MII Logic. */
|
|
|
|
|
MAC_SUPP = SUPP_RES_RMII;
|
|
|
|
|
vTaskDelay( 2 );
|
|
|
|
|
MAC_SUPP = 0;
|
|
|
|
|
|
|
|
|
|
/* Put the PHY in reset mode */
|
|
|
|
|
write_PHY( PHY_REG_BMCR, 0x8000 );
|
|
|
|
|
xReturn = write_PHY( PHY_REG_BMCR, 0x8000 );
|
|
|
|
|
|
|
|
|
|
/* Wait for hardware reset to end. */
|
|
|
|
|
for( tout = 0; tout < 100; tout++ )
|
|
|
|
|
{
|
|
|
|
|
vTaskDelay( 10 );
|
|
|
|
|
regv = read_PHY( PHY_REG_BMCR, &xReturn );
|
|
|
|
|
if( !(regv & 0x8000) )
|
|
|
|
|
{
|
|
|
|
|
/* Reset complete */
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Check if this is a DP83848C PHY. */
|
|
|
|
|
id1 = read_PHY( PHY_REG_IDR1, &xReturn );
|
|
|
|
|
id2 = read_PHY( PHY_REG_IDR2, &xReturn );
|
|
|
|
|
if( ((id1 << 16) | (id2 & 0xFFF0)) == DP83848C_ID )
|
|
|
|
|
{
|
|
|
|
|
/* Set the Ethernet MAC Address registers */
|
|
|
|
|
MAC_SA0 = ( emacETHADDR0 << 8 ) | emacETHADDR1;
|
|
|
|
|
MAC_SA1 = ( emacETHADDR2 << 8 ) | emacETHADDR3;
|
|
|
|
|
MAC_SA2 = ( emacETHADDR4 << 8 ) | emacETHADDR5;
|
|
|
|
|
|
|
|
|
|
/* Initialize Tx and Rx DMA Descriptors */
|
|
|
|
|
rx_descr_init();
|
|
|
|
|
tx_descr_init();
|
|
|
|
|
|
|
|
|
|
/* Receive Broadcast and Perfect Match Packets */
|
|
|
|
|
MAC_RXFILTERCTRL = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
|
|
|
|
|
|
|
|
|
|
/* Create the semaphore used ot wake the uIP task. */
|
|
|
|
|
vSemaphoreCreateBinary( xEMACSemaphore );
|
|
|
|
|
|
|
|
|
|
/* Configure the PHY device */
|
|
|
|
|
|
|
|
|
|
/* Use autonegotiation about the link speed. */
|
|
|
|
|
if( write_PHY(PHY_REG_BMCR, PHY_AUTO_NEG) )
|
|
|
|
|
{
|
|
|
|
|
/* Wait to complete Auto_Negotiation. */
|
|
|
|
|
for( tout = 0; tout < 10; tout++ )
|
|
|
|
|
{
|
|
|
|
|
vTaskDelay( 100 );
|
|
|
|
|
regv = read_PHY( PHY_REG_BMSR, &xReturn );
|
|
|
|
|
if( regv & 0x0020 )
|
|
|
|
|
{
|
|
|
|
|
/* Autonegotiation Complete. */
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
xReturn = pdFAIL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Check the link status. */
|
|
|
|
|
if( xReturn == pdPASS )
|
|
|
|
|
{
|
|
|
|
|
xReturn = pdFAIL;
|
|
|
|
|
for( tout = 0; tout < 10; tout++ )
|
|
|
|
|
{
|
|
|
|
|
vTaskDelay( 100 );
|
|
|
|
|
regv = read_PHY( PHY_REG_STS, &xReturn );
|
|
|
|
|
if( regv & 0x0001 )
|
|
|
|
|
{
|
|
|
|
|
/* Link is on. */
|
|
|
|
|
xReturn = pdPASS;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if( xReturn == pdPASS )
|
|
|
|
|
{
|
|
|
|
|
/* Configure Full/Half Duplex mode. */
|
|
|
|
|
if( regv & 0x0004 )
|
|
|
|
|
{
|
|
|
|
|
/* Full duplex is enabled. */
|
|
|
|
|
MAC_MAC2 |= MAC2_FULL_DUP;
|
|
|
|
|
MAC_COMMAND |= CR_FULL_DUP;
|
|
|
|
|
MAC_IPGT = IPGT_FULL_DUP;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
/* Half duplex mode. */
|
|
|
|
|
MAC_IPGT = IPGT_HALF_DUP;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Configure 100MBit/10MBit mode. */
|
|
|
|
|
if( regv & 0x0002 )
|
|
|
|
|
{
|
|
|
|
|
/* 10MBit mode. */
|
|
|
|
|
MAC_SUPP = 0;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
/* 100MBit mode. */
|
|
|
|
|
MAC_SUPP = SUPP_SPEED;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Reset all interrupts */
|
|
|
|
|
MAC_INTCLEAR = 0xFFFF;
|
|
|
|
|
|
|
|
|
|
/* Enable receive and transmit mode of MAC Ethernet core */
|
|
|
|
|
MAC_COMMAND |= ( CR_RX_EN | CR_TX_EN );
|
|
|
|
|
MAC_MAC1 |= MAC1_REC_EN;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return xReturn;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// reads a word in little-endian byte order from RX_BUFFER
|
|
|
|
|
|
|
|
|
|
unsigned short ReadFrame_EMAC(void)
|
|
|
|
|
unsigned short ReadFrame_EMAC( void )
|
|
|
|
|
{
|
|
|
|
|
return (*rptr++);
|
|
|
|
|
return( *rptr++ );
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// reads a word in big-endian byte order from RX_FRAME_PORT
|
|
|
|
|
// (useful to avoid permanent byte-swapping while reading
|
|
|
|
|
// TCP/IP-data)
|
|
|
|
|
|
|
|
|
|
unsigned short ReadFrameBE_EMAC(void)
|
|
|
|
|
unsigned short ReadFrameBE_EMAC( void )
|
|
|
|
|
{
|
|
|
|
|
unsigned short ReturnValue;
|
|
|
|
|
unsigned short ReturnValue;
|
|
|
|
|
|
|
|
|
|
ReturnValue = SwapBytes (*rptr++);
|
|
|
|
|
return (ReturnValue);
|
|
|
|
|
ReturnValue = SwapBytes( *rptr++ );
|
|
|
|
|
return( ReturnValue );
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// copies bytes from frame port to MCU-memory
|
|
|
|
|
// NOTES: * an odd number of byte may only be transfered
|
|
|
|
|
// if the frame is read to the end!
|
|
|
|
|
// * MCU-memory MUST start at word-boundary
|
|
|
|
|
|
|
|
|
|
void CopyFromFrame_EMAC(void *Dest, unsigned short Size)
|
|
|
|
|
void CopyFromFrame_EMAC( void *Dest, unsigned short Size )
|
|
|
|
|
{
|
|
|
|
|
unsigned short * piDest; // Keil: Pointer added to correct expression
|
|
|
|
|
|
|
|
|
|
piDest = Dest; // Keil: Line added
|
|
|
|
|
while (Size > 1) {
|
|
|
|
|
*piDest++ = ReadFrame_EMAC();
|
|
|
|
|
Size -= 2;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (Size) { // check for leftover byte...
|
|
|
|
|
*(unsigned char *)piDest = (char)ReadFrame_EMAC();// the LAN-Controller will return 0
|
|
|
|
|
} // for the highbyte
|
|
|
|
|
unsigned short *piDest; // Keil: Pointer added to correct expression
|
|
|
|
|
piDest = Dest; // Keil: Line added
|
|
|
|
|
while( Size > 1 )
|
|
|
|
|
{
|
|
|
|
|
*piDest++ = ReadFrame_EMAC();
|
|
|
|
|
Size -= 2;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if( Size )
|
|
|
|
|
{ // check for leftover byte...
|
|
|
|
|
*( unsigned char * ) piDest = ( char ) ReadFrame_EMAC(); // the LAN-Controller will return 0
|
|
|
|
|
} // for the highbyte
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// does a dummy read on frame-I/O-port
|
|
|
|
|
// NOTE: only an even number of bytes is read!
|
|
|
|
|
|
|
|
|
|
void DummyReadFrame_EMAC(unsigned short Size) // discards an EVEN number of bytes
|
|
|
|
|
{ // from RX-fifo
|
|
|
|
|
while (Size > 1) {
|
|
|
|
|
ReadFrame_EMAC();
|
|
|
|
|
Size -= 2;
|
|
|
|
|
}
|
|
|
|
|
void DummyReadFrame_EMAC( unsigned short Size ) // discards an EVEN number of bytes
|
|
|
|
|
{ // from RX-fifo
|
|
|
|
|
while( Size > 1 )
|
|
|
|
|
{
|
|
|
|
|
ReadFrame_EMAC();
|
|
|
|
|
Size -= 2;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Reads the length of the received ethernet frame and checks if the
|
|
|
|
|
// Reads the length of the received ethernet frame and checks if the
|
|
|
|
|
// destination address is a broadcast message or not
|
|
|
|
|
// returns the frame length
|
|
|
|
|
unsigned short StartReadFrame(void) {
|
|
|
|
|
unsigned short RxLen;
|
|
|
|
|
unsigned int idx;
|
|
|
|
|
|
|
|
|
|
idx = MAC_RXCONSUMEINDEX;
|
|
|
|
|
RxLen = (RX_STAT_INFO(idx) & RINFO_SIZE) - 3;
|
|
|
|
|
rptr = (unsigned short *)RX_DESC_PACKET(idx);
|
|
|
|
|
return(RxLen);
|
|
|
|
|
unsigned short StartReadFrame( void )
|
|
|
|
|
{
|
|
|
|
|
unsigned short RxLen;
|
|
|
|
|
unsigned int idx;
|
|
|
|
|
|
|
|
|
|
idx = MAC_RXCONSUMEINDEX;
|
|
|
|
|
RxLen = ( RX_STAT_INFO(idx) & RINFO_SIZE ) - 3;
|
|
|
|
|
rptr = ( unsigned short * ) RX_DESC_PACKET( idx );
|
|
|
|
|
return( RxLen );
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void EndReadFrame(void) {
|
|
|
|
|
unsigned int idx;
|
|
|
|
|
void EndReadFrame( void )
|
|
|
|
|
{
|
|
|
|
|
unsigned int idx;
|
|
|
|
|
|
|
|
|
|
/* DMA free packet. */
|
|
|
|
|
idx = MAC_RXCONSUMEINDEX;
|
|
|
|
|
/* DMA free packet. */
|
|
|
|
|
idx = MAC_RXCONSUMEINDEX;
|
|
|
|
|
|
|
|
|
|
if (++idx == NUM_RX_FRAG)
|
|
|
|
|
idx = 0;
|
|
|
|
|
if( ++idx == NUM_RX_FRAG )
|
|
|
|
|
{
|
|
|
|
|
idx = 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
MAC_RXCONSUMEINDEX = idx;
|
|
|
|
|
MAC_RXCONSUMEINDEX = idx;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
unsigned int CheckFrameReceived(void) { // Packet received ?
|
|
|
|
|
|
|
|
|
|
if (MAC_RXPRODUCEINDEX != MAC_RXCONSUMEINDEX) // more packets received ?
|
|
|
|
|
return(1);
|
|
|
|
|
else
|
|
|
|
|
return(0);
|
|
|
|
|
unsigned int CheckFrameReceived( void )
|
|
|
|
|
{
|
|
|
|
|
// Packet received ?
|
|
|
|
|
if( MAC_RXPRODUCEINDEX != MAC_RXCONSUMEINDEX )
|
|
|
|
|
{ // more packets received ?
|
|
|
|
|
return( 1 );
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
return( 0 );
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
unsigned int uiGetEMACRxData( unsigned char *ucBuffer )
|
|
|
|
|
{
|
|
|
|
|
unsigned int uiLen = 0;
|
|
|
|
|
unsigned int uiLen = 0;
|
|
|
|
|
|
|
|
|
|
if( MAC_RXPRODUCEINDEX != MAC_RXCONSUMEINDEX )
|
|
|
|
|
{
|
|
|
|
|
uiLen = StartReadFrame();
|
|
|
|
|
CopyFromFrame_EMAC( ucBuffer, uiLen );
|
|
|
|
|
EndReadFrame();
|
|
|
|
|
}
|
|
|
|
|
if( MAC_RXPRODUCEINDEX != MAC_RXCONSUMEINDEX )
|
|
|
|
|
{
|
|
|
|
|
uiLen = StartReadFrame();
|
|
|
|
|
CopyFromFrame_EMAC( ucBuffer, uiLen );
|
|
|
|
|
EndReadFrame();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return uiLen;
|
|
|
|
|
return uiLen;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// requests space in EMAC memory for storing an outgoing frame
|
|
|
|
|
|
|
|
|
|
void RequestSend(void)
|
|
|
|
|
void RequestSend( void )
|
|
|
|
|
{
|
|
|
|
|
unsigned int idx;
|
|
|
|
|
unsigned int idx;
|
|
|
|
|
|
|
|
|
|
idx = MAC_TXPRODUCEINDEX;
|
|
|
|
|
tptr = (unsigned short *)TX_DESC_PACKET(idx);
|
|
|
|
|
idx = MAC_TXPRODUCEINDEX;
|
|
|
|
|
tptr = ( unsigned short * ) TX_DESC_PACKET( idx );
|
|
|
|
|
}
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// check if ethernet controller is ready to accept the
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// frame we want to send
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unsigned int Rdy4Tx(void)
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unsigned int Rdy4Tx( void )
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{
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return (1); // the ethernet controller transmits much faster
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} // than the CPU can load its buffers
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return( 1 ); // the ethernet controller transmits much faster
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} // than the CPU can load its buffers
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// writes a word in little-endian byte order to TX_BUFFER
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void WriteFrame_EMAC(unsigned short Data)
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void WriteFrame_EMAC( unsigned short Data )
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{
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*tptr++ = Data;
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*tptr++ = Data;
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}
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// copies bytes from MCU-memory to frame port
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// NOTES: * an odd number of byte may only be transfered
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// if the frame is written to the end!
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// * MCU-memory MUST start at word-boundary
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void CopyToFrame_EMAC(void *Source, unsigned int Size)
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void CopyToFrame_EMAC( void *Source, unsigned int Size )
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{
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unsigned short * piSource;
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piSource = Source;
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Size = (Size + 1) & 0xFFFE; // round Size up to next even number
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while (Size > 0) {
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WriteFrame_EMAC(*piSource++);
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Size -= 2;
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}
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unsigned short *piSource;
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piSource = Source;
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Size = ( Size + 1 ) & 0xFFFE; // round Size up to next even number
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while( Size > 0 )
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{
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WriteFrame_EMAC( *piSource++ );
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Size -= 2;
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}
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}
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void DoSend_EMAC(unsigned short FrameSize)
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void DoSend_EMAC( unsigned short FrameSize )
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{
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unsigned int idx;
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unsigned int idx;
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idx = MAC_TXPRODUCEINDEX;
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TX_DESC_CTRL( idx ) = FrameSize | TCTRL_LAST;
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if( ++idx == NUM_TX_FRAG )
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{
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idx = 0;
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}
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idx = MAC_TXPRODUCEINDEX;
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TX_DESC_CTRL(idx) = FrameSize | TCTRL_LAST;
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if (++idx == NUM_TX_FRAG) idx = 0;
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|
MAC_TXPRODUCEINDEX = idx;
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MAC_TXPRODUCEINDEX = idx;
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}
|
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void vEMAC_ISR( void )
|
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|
|
{
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|
|
portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
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|
|
portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
|
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/* Clear the interrupt. */
|
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|
MAC_INTCLEAR = 0xffff;
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|
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/* Clear the interrupt. */
|
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|
MAC_INTCLEAR = 0xffff;
|
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|
|
/* Ensure the uIP task is not blocked as data has arrived. */
|
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|
|
xSemaphoreGiveFromISR( xEMACSemaphore, &xHigherPriorityTaskWoken );
|
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|
|
/* Ensure the uIP task is not blocked as data has arrived. */
|
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|
|
xSemaphoreGiveFromISR( xEMACSemaphore, &xHigherPriorityTaskWoken );
|
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|
portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
|
|
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|
|
portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
|
|
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|
|
}
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Richard Barry
16 years ago