diff --git a/Demo/NiosII_CycloneIII_DBC3C40_GCC/.sopc_builder/install.ptf b/Demo/NiosII_CycloneIII_DBC3C40_GCC/.sopc_builder/install.ptf
new file mode 100644
index 000000000..15a6e5959
--- /dev/null
+++ b/Demo/NiosII_CycloneIII_DBC3C40_GCC/.sopc_builder/install.ptf
@@ -0,0 +1,473 @@
+PACKAGE install
+{
+ version = "4.01:213";
+ COMPONENT altera_nios2
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/nios2_ip/altera_nios2";
+ }
+ }
+ COMPONENT altera_nios_custom_instruction
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/nios2_ip/altera_nios_custom_instruction";
+ }
+ }
+ COMPONENT altera_nios_custom_instr_bitswap
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/nios2_ip/altera_nios_custom_instr_bitswap";
+ }
+ }
+ COMPONENT altera_nios_custom_instr_endian_converter
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/nios2_ip/altera_nios_custom_instr_endian_converter";
+ }
+ }
+ COMPONENT altera_nios_custom_instr_floating_point
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/nios2_ip/altera_nios_custom_instr_floating_point";
+ }
+ }
+ COMPONENT altera_nios_custom_instr_interrupt_vector
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/nios2_ip/altera_nios_custom_instr_interrupt_vector";
+ }
+ }
+ COMPONENT altera_nios_dev_board_cyclone_1c20
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/nios2_ip/altera_nios_dev_board_cyclone_1c20";
+ }
+ }
+ COMPONENT altera_nios_dev_board_cyclone_2c35
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/nios2_ip/altera_nios_dev_board_cyclone_2c35";
+ }
+ }
+ COMPONENT altera_nios_dev_board_stratix_1s10
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/nios2_ip/altera_nios_dev_board_stratix_1s10";
+ }
+ }
+ COMPONENT altera_nios_dev_board_stratix_1s10_es
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/nios2_ip/altera_nios_dev_board_stratix_1s10_es";
+ }
+ }
+ COMPONENT altera_nios_dev_board_stratix_1s40
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/nios2_ip/altera_nios_dev_board_stratix_1s40";
+ }
+ }
+ COMPONENT altera_nios_dev_board_stratix_2s60
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/nios2_ip/altera_nios_dev_board_stratix_2s60";
+ }
+ }
+ COMPONENT altera_nios_dev_board_stratix_2s60_es
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/nios2_ip/altera_nios_dev_board_stratix_2s60_es";
+ }
+ }
+ COMPONENT altera_nios_dev_board_stratix_2s60_rohs
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/nios2_ip/altera_nios_dev_board_stratix_2s60_rohs";
+ }
+ }
+ COMPONENT altera_nios_dev_kit_stratix_edition_sram
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/nios2_ip/altera_nios_dev_kit_stratix_edition_sram";
+ }
+ }
+ COMPONENT altera_nios_dev_kit_stratix_edition_sram2
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/nios2_ip/altera_nios_dev_kit_stratix_edition_sram2";
+ }
+ }
+ COMPONENT altera_nios_multiply
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/nios2_ip/altera_nios_multiply";
+ }
+ }
+ COMPONENT altera_avalon_adapter_downstream_pipeline
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_adapter_downstream_pipeline";
+ }
+ }
+ COMPONENT altera_avalon_adapter_master_y
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_adapter_master_y";
+ }
+ }
+ COMPONENT altera_avalon_adapter_slave_y
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_adapter_slave_y";
+ }
+ }
+ COMPONENT altera_avalon_adapter_upstream_pipeline
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_adapter_upstream_pipeline";
+ }
+ }
+ COMPONENT altera_avalon_adapter_waitrequest_pipeline
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_adapter_waitrequest_pipeline";
+ }
+ }
+ COMPONENT altera_avalon_asmi
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_asmi";
+ }
+ }
+ COMPONENT altera_avalon_burst_adapter
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_burst_adapter";
+ }
+ }
+ COMPONENT altera_avalon_cf
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_cf";
+ }
+ }
+ COMPONENT altera_avalon_cfi_flash
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_cfi_flash";
+ }
+ }
+ COMPONENT altera_avalon_clock_adapter
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_clock_adapter";
+ }
+ }
+ COMPONENT altera_avalon_clock_crossing
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_clock_crossing";
+ }
+ }
+ COMPONENT altera_avalon_cs8900
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_cs8900";
+ }
+ }
+ COMPONENT altera_avalon_cy7c1380_ssram
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_cy7c1380_ssram";
+ }
+ }
+ COMPONENT altera_avalon_dma
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_dma";
+ }
+ }
+ COMPONENT altera_avalon_endian_adapter
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_endian_adapter";
+ }
+ }
+ COMPONENT altera_avalon_epcs_flash_controller
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_epcs_flash_controller";
+ }
+ }
+ COMPONENT altera_avalon_fifo
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_fifo";
+ }
+ }
+ COMPONENT altera_avalon_jtag_uart
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_jtag_uart";
+ }
+ }
+ COMPONENT altera_avalon_lan91c111
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_lan91c111";
+ }
+ }
+ COMPONENT altera_avalon_lcd_16207
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_lcd_16207";
+ }
+ }
+ COMPONENT altera_avalon_mailbox
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_mailbox";
+ }
+ }
+ COMPONENT altera_avalon_mutex
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_mutex";
+ }
+ }
+ COMPONENT altera_avalon_new_sdram_controller
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller";
+ }
+ }
+ COMPONENT altera_avalon_onchip_memory
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_onchip_memory";
+ }
+ }
+ COMPONENT altera_avalon_onchip_memory2
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2";
+ }
+ }
+ COMPONENT altera_avalon_performance_counter
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_performance_counter";
+ }
+ }
+ COMPONENT altera_avalon_pio
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_pio";
+ }
+ }
+ COMPONENT altera_avalon_pipeline_bridge
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_pipeline_bridge";
+ }
+ }
+ COMPONENT altera_avalon_pll
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_pll";
+ }
+ }
+ COMPONENT altera_avalon_sgdma
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_sgdma";
+ }
+ }
+ COMPONENT altera_avalon_spi
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_spi";
+ }
+ }
+ COMPONENT altera_avalon_sysid
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_sysid";
+ }
+ }
+ COMPONENT altera_avalon_timer
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_timer";
+ }
+ }
+ COMPONENT altera_avalon_tri_state_bridge
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_tri_state_bridge";
+ }
+ }
+ COMPONENT altera_avalon_uart
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_uart";
+ }
+ }
+ COMPONENT altera_avalon_user_defined_interface
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_user_defined_interface";
+ }
+ }
+ COMPONENT altera_sopc_builder
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_sopc_builder";
+ }
+ }
+ COMPONENT amd_avalon_am29lv065d_flash
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/amd_avalon_am29lv065d_flash";
+ }
+ }
+ COMPONENT amd_avalon_am29lv128m_flash
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/amd_avalon_am29lv128m_flash";
+ }
+ }
+ COMPONENT no_legacy_module
+ {
+ VERSION 7.080902
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/no_legacy_module";
+ }
+ }
+ COMPONENT triple_speed_ethernet
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/triple_speed_ethernet/lib/sopc_builder/altera_triple_speed_ethernet";
+ }
+ }
+ COMPONENT ddr2_sdram_component
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/ddr_ddr2_sdram/lib/sopc_builder/ddr2_sdram_component";
+ }
+ }
+ COMPONENT ddr_sdram_component
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/ddr_ddr2_sdram/lib/sopc_builder/ddr_sdram_component";
+ }
+ }
+ COMPONENT ddr3_high_perf
+ {
+ VERSION 8.1
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/ddr3_high_perf/lib/sopc_builder/ddr3_high_perf";
+ }
+ }
+ COMPONENT ddr2_high_perf
+ {
+ VERSION 8.1
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/ddr2_high_perf/lib/sopc_builder/ddr2_high_perf";
+ }
+ }
+ COMPONENT ddr_high_perf
+ {
+ VERSION 8.1
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/ddr_high_perf/lib/sopc_builder/ddr_high_perf";
+ }
+ }
+ COMPONENT altera_avalon_pcie_compiler
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/pci_express_compiler/lib/sopc_builder/altera_avalon_pcie_compiler";
+ }
+ }
+ COMPONENT altera_avalon_pcie_compiler_adapter
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/pci_express_compiler/lib/sopc_builder/altera_avalon_pcie_compiler_adapter";
+ }
+ }
+ COMPONENT altera_avalon_pci_compiler
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/pci_compiler/lib/sopc_builder/altera_avalon_pci_compiler";
+ }
+ }
+ COMPONENT altera_avalon_pci_compiler_adapter
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/pci_compiler/lib/sopc_builder/altera_avalon_pci_compiler_adapter";
+ }
+ }
+}
diff --git a/Demo/NiosII_CycloneIII_DBC3C40_GCC/.sopc_builder/install2.ptf b/Demo/NiosII_CycloneIII_DBC3C40_GCC/.sopc_builder/install2.ptf
new file mode 100644
index 000000000..c42d32774
--- /dev/null
+++ b/Demo/NiosII_CycloneIII_DBC3C40_GCC/.sopc_builder/install2.ptf
@@ -0,0 +1,250 @@
+PACKAGE install2
+{
+ # This file informs the Nios II IDE of non-legacy component paths.
+ # Generated 2009.08.05.16:22:08
+ COMPONENT alt_vip_clip
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/clipper/lib";
+ }
+ }
+ COMPONENT alt_vip_cpr
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/color_plane_sequencer/lib";
+ }
+ }
+ COMPONENT alt_vip_crs
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/chroma_resampler/lib";
+ }
+ }
+ COMPONENT alt_vip_csc
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/csc/lib";
+ }
+ }
+ COMPONENT alt_vip_dil
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/deinterlacer/lib";
+ }
+ }
+ COMPONENT alt_vip_fir
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/fir_filter_2d/lib";
+ }
+ }
+ COMPONENT alt_vip_gam
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/gamma_corrector/lib";
+ }
+ }
+ COMPONENT alt_vip_lbc
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/line_buffer_compiler/lib";
+ }
+ }
+ COMPONENT alt_vip_med
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/median_filter_2d/lib";
+ }
+ }
+ COMPONENT alt_vip_mix
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/alpha_blending_mixer/lib";
+ }
+ }
+ COMPONENT alt_vip_scl
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/scaler/lib";
+ }
+ }
+ COMPONENT alt_vip_tpg
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/test_pattern_generator/lib";
+ }
+ }
+ COMPONENT alt_vip_vfb
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/frame_buffer/lib";
+ }
+ }
+ COMPONENT altera_avalon_dc_fifo
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_dc_fifo";
+ }
+ }
+ COMPONENT altera_avalon_half_rate_bridge
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_half_rate_bridge";
+ }
+ }
+ COMPONENT altera_avalon_multi_channel_shared_fifo
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_multi_channel_shared_fifo";
+ }
+ }
+ COMPONENT altera_avalon_packets_to_master
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_packets_to_master";
+ }
+ }
+ COMPONENT altera_avalon_pixel_converter
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_pixel_converter";
+ }
+ }
+ COMPONENT altera_avalon_remote_update_cycloneiii
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_remote_update_cycloneiii";
+ }
+ }
+ COMPONENT altera_avalon_round_robin_scheduler
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_round_robin_scheduler";
+ }
+ }
+ COMPONENT altera_avalon_sc_fifo
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo";
+ }
+ }
+ COMPONENT altera_avalon_st_bytes_to_packets
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_st_bytes_to_packets";
+ }
+ }
+ COMPONENT altera_avalon_st_idle_inserter
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_st_idle_inserter";
+ }
+ }
+ COMPONENT altera_avalon_st_idle_remover
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_st_idle_remover";
+ }
+ }
+ COMPONENT altera_avalon_st_packets_to_bytes
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_st_packets_to_bytes";
+ }
+ }
+ COMPONENT altera_avalon_video_sync_generator
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_video_sync_generator";
+ }
+ }
+ COMPONENT altera_jtag_avalon_master
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_jtag_avalon_master";
+ }
+ }
+ COMPONENT altera_jtag_dc_streaming
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_jtag_phy";
+ }
+ }
+ COMPONENT altpll
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_altpll";
+ }
+ }
+ COMPONENT avalon_mm_master_bfm
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/verification/avalon_mm_bfm/avalon_mm_master_bfm";
+ }
+ }
+ COMPONENT avalon_mm_slave_bfm
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/verification/avalon_mm_bfm/avalon_mm_slave_bfm";
+ }
+ }
+ COMPONENT pci_lite
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_pci_lite";
+ }
+ }
+ COMPONENT sls_avalon_usb20hr
+ {
+ VERSION 2.2
+ {
+ local = "C:/devtools/altera/90sp2/ip/sls/usb20hr_ocp_eval_pack/hardware/component";
+ }
+ }
+ COMPONENT spi_slave_to_avalon_mm_master_bridge
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_spislave_to_avalonmm_bridge";
+ }
+ }
+ COMPONENT spislave
+ {
+ VERSION 9.0
+ {
+ local = "C:/devtools/altera/90sp2/ip/altera/sopc_builder_ip/altera_avalon_spi_phy_slave";
+ }
+ }
+}
diff --git a/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/.cdtbuild b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/.cdtbuild
new file mode 100644
index 000000000..6b6e7ee0f
--- /dev/null
+++ b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/.cdtbuild
@@ -0,0 +1,28 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 3.1.0?>
+
+<ManagedProjectBuildInfo>
+<project id="RTOSDemo.nios2.exec.1581235184" name="Nios II Executable" projectType="nios2.exec">
+<configuration artifactExtension="elf" artifactName="RTOSDemo" cleanCommand="rm -rf" description="" errorParsers="org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser" id="nios2.exec.debug.1446010332" name="Debug" parent="nios2.exec.debug">
+<toolChain id="com.altera.nj.ui.exe.Debug.241068812" name="com.altera.nj.ui.exe.Debug" superClass="com.altera.nj.ui.exe.Debug">
+<tool id="com.altera.nj.ui.tool.compiler.exe.debug.238740427" name="Nios II Compiler" superClass="com.altera.nj.ui.tool.compiler.exe.debug">
+<option id="nios2.compiler.general.include.paths.1954487624" superClass="nios2.compiler.general.include.paths" valueType="includePath">
+<listOptionValue builtIn="false" value=""${workspace_loc:/RTOSDemo/FreeRTOS/portable/GCC/Nios2}""/>
+<listOptionValue builtIn="false" value=""${workspace_loc:/RTOSDemo/Common_Demo_Tasks/include}""/>
+<listOptionValue builtIn="false" value=""${workspace_loc:/RTOSDemo/FreeRTOS/include}""/>
+<listOptionValue builtIn="false" value=""${workspace_loc:/RTOSDemo}""/>
+</option>
+</tool>
+<tool id="com.altera.nj.ui.tool.linker.exe.debug.2054232498" name="Linker" superClass="com.altera.nj.ui.tool.linker.exe.debug"/>
+<macros expandEnvironmentMacros="true"/>
+</toolChain>
+</configuration>
+<configuration artifactExtension="elf" artifactName="RTOSDemo" cleanCommand="rm -rf" description="" errorParsers="org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser" id="nios2.exec.release.654306637" name="Release" parent="nios2.exec.release">
+<toolChain id="com.altera.nj.ui.exe.Release.506996366" name="com.altera.nj.ui.exe.Release" superClass="com.altera.nj.ui.exe.Release">
+<tool id="com.altera.nj.ui.tool.compiler.exe.release.1487128363" name="Nios II Compiler" superClass="com.altera.nj.ui.tool.compiler.exe.release"/>
+<tool id="com.altera.nj.ui.tool.linker.exe.release.733767895" name="Linker" superClass="com.altera.nj.ui.tool.linker.exe.release"/>
+</toolChain>
+</configuration>
+<macros/>
+</project>
+</ManagedProjectBuildInfo>
diff --git a/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/.cdtproject b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/.cdtproject
new file mode 100644
index 000000000..4fe5dd236
--- /dev/null
+++ b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/.cdtproject
@@ -0,0 +1,65 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?eclipse-cdt version="2.0"?>
+
+<cdtproject id="org.eclipse.cdt.managedbuilder.core.managedMake">
+<extension id="org.eclipse.cdt.managedbuilder.core.ManagedBuildManager" point="org.eclipse.cdt.core.ScannerInfoProvider"/>
+<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser">
+<attribute key="addr2line" value="addr2line"/>
+<attribute key="c++filt" value="c++filt"/>
+</extension>
+<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser">
+<attribute key="addr2line" value="addr2line"/>
+<attribute key="c++filt" value="c++filt"/>
+</extension>
+<data>
+<item id="org.eclipse.cdt.core.pathentry">
+<pathentry kind="src" path=""/>
+<pathentry kind="out" path=""/>
+<pathentry kind="con" path="org.eclipse.cdt.managedbuilder.MANAGED_CONTAINER"/>
+<pathentry kind="con" path="org.eclipse.cdt.make.core.DISCOVERED_SCANNER_INFO"/>
+</item>
+<item id="scannerConfiguration">
+<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile"/>
+<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+<buildOutputProvider>
+<openAction enabled="true" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="specsFile">
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+<parser enabled="true"/>
+</scannerInfoProvider>
+</profile>
+<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+<buildOutputProvider>
+<openAction enabled="false" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="makefileGenerator">
+<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+<parser enabled="false"/>
+</scannerInfoProvider>
+</profile>
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+<buildOutputProvider>
+<openAction enabled="false" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="specsFile">
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+<parser enabled="false"/>
+</scannerInfoProvider>
+</profile>
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+<buildOutputProvider>
+<openAction enabled="false" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="specsFile">
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+<parser enabled="false"/>
+</scannerInfoProvider>
+</profile>
+</item>
+</data>
+</cdtproject>
diff --git a/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/.project b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/.project
new file mode 100644
index 000000000..f740744d5
--- /dev/null
+++ b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/.project
@@ -0,0 +1,90 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>RTOSDemo</name>
+ <comment></comment>
+ <projects>
+ <project>RTOSDemo_syslib</project>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.make.core.makeBuilder</name>
+ <triggers>clean,full,incremental,</triggers>
+ <arguments>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+ <value>false</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.append_environment</key>
+ <value>true</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.stopOnError</key>
+ <value>false</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.enabledIncrementalBuild</key>
+ <value>false</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.build.command</key>
+ <value>make</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.build.target.inc</key>
+ <value>all</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.build.arguments</key>
+ <value></value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+ <value>true</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.environment</key>
+ <value></value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.enableFullBuild</key>
+ <value>false</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.build.target.auto</key>
+ <value>all</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+ <value>false</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.build.target.clean</key>
+ <value>clean</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.core.errorOutputParser</key>
+ <value>org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.VCErrorParser;</value>
+ </dictionary>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>com.altera.ide.core.alterabuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>org.eclipse.cdt.make.core.ScannerConfigBuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>com.altera.ide.core.AlteraNios2Nature</nature>
+ <nature>com.altera.ide.core.AlteraApplicationNature</nature>
+ <nature>org.eclipse.cdt.make.core.makeNature</nature>
+ <nature>org.eclipse.cdt.make.core.ScannerConfigNature</nature>
+ </natures>
+</projectDescription>
diff --git a/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/.settings/org.eclipse.cdt.core.prefs b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/.settings/org.eclipse.cdt.core.prefs
new file mode 100644
index 000000000..726d3f5c0
--- /dev/null
+++ b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/.settings/org.eclipse.cdt.core.prefs
@@ -0,0 +1,3 @@
+#Tue Aug 04 21:28:00 BST 2009
+eclipse.preferences.version=1
+indexerId=org.eclipse.cdt.core.fastIndexer
diff --git a/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/.settings/org.eclipse.cdt.managedbuilder.core.prefs
new file mode 100644
index 000000000..312e4b72e
--- /dev/null
+++ b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/.settings/org.eclipse.cdt.managedbuilder.core.prefs
@@ -0,0 +1,6 @@
+#Tue Aug 04 21:27:58 BST 2009
+eclipse.preferences.version=1
+nios2.exec.debug.746546544/internalBuilder/enabled=false
+nios2.exec.debug.746546544/internalBuilder/ignoreErr=true
+nios2.exec.release.1419815778/internalBuilder/enabled=false
+nios2.exec.release.1419815778/internalBuilder/ignoreErr=true
diff --git a/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/.settings/org.eclipse.ltk.core.refactoring.prefs b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/.settings/org.eclipse.ltk.core.refactoring.prefs
new file mode 100644
index 000000000..2f316a605
--- /dev/null
+++ b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/.settings/org.eclipse.ltk.core.refactoring.prefs
@@ -0,0 +1,3 @@
+#Tue Aug 04 21:40:26 BST 2009
+eclipse.preferences.version=1
+org.eclipse.ltk.core.refactoring.enable.project.refactoring.history=false
diff --git a/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/FreeRTOSConfig.h b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/FreeRTOSConfig.h
new file mode 100644
index 000000000..3e914814a
--- /dev/null
+++ b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/FreeRTOSConfig.h
@@ -0,0 +1,107 @@
+/*
+ FreeRTOS V5.4.1 - Copyright (C) 2009 Real Time Engineers Ltd.
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation and modified by the FreeRTOS exception.
+ **NOTE** The exception to the GPL is included to allow you to distribute a
+ combined work that includes FreeRTOS without being obliged to provide the
+ source code for proprietary components outside of the FreeRTOS kernel.
+ Alternative commercial license and support terms are also available upon
+ request. See the licensing section of http://www.FreeRTOS.org for full
+ license details.
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details.
+
+ You should have received a copy of the GNU General Public License along
+ with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59
+ Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+
+
+ ***************************************************************************
+ * *
+ * Looking for a quick start? Then check out the FreeRTOS eBook! *
+ * See http://www.FreeRTOS.org/Documentation for details *
+ * *
+ ***************************************************************************
+
+ 1 tab == 4 spaces!
+
+ Please ensure to read the configuration and relevant port sections of the
+ online documentation.
+
+ http://www.FreeRTOS.org - Documentation, latest information, license and
+ contact details.
+
+ http://www.SafeRTOS.com - A version that is certified for use in safety
+ critical systems.
+
+ http://www.OpenRTOS.com - Commercial support, development, porting,
+ licensing and training services.
+*/
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+#include "system.h"
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION 1
+#define configUSE_IDLE_HOOK 0
+#define configUSE_TICK_HOOK 0
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) SYS_CLK_FREQ )
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )
+#define configMINIMAL_STACK_SIZE ( 1024 )
+#define configISR_STACK_SIZE configMINIMAL_STACK_SIZE
+#define configTOTAL_HEAP_SIZE ( ( size_t ) 8388608 )
+#define configMAX_TASK_NAME_LEN ( 8 )
+#define configUSE_TRACE_FACILITY 0
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 0
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configCHECK_FOR_STACK_OVERFLOW 2
+#define configQUEUE_REGISTRY_SIZE 0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskCleanUpResources 0
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 1
+
+/* The priority at which the tick interrupt runs. This should probably be
+kept at 1. */
+#define configKERNEL_INTERRUPT_PRIORITY 0x01
+
+/* The maximum interrupt priority from which FreeRTOS.org API functions can
+be called. Only API functions that end in ...FromISR() can be used within
+interrupts. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 0x03
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/ParTest/ParTest.c b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/ParTest/ParTest.c
new file mode 100644
index 000000000..8af0adf6c
--- /dev/null
+++ b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/ParTest/ParTest.c
@@ -0,0 +1,110 @@
+/*
+ FreeRTOS V5.4.1 - Copyright (C) 2009 Real Time Engineers Ltd.
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation and modified by the FreeRTOS exception.
+ **NOTE** The exception to the GPL is included to allow you to distribute a
+ combined work that includes FreeRTOS without being obliged to provide the
+ source code for proprietary components outside of the FreeRTOS kernel.
+ Alternative commercial license and support terms are also available upon
+ request. See the licensing section of http://www.FreeRTOS.org for full
+ license details.
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details.
+
+ You should have received a copy of the GNU General Public License along
+ with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59
+ Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+
+
+ ***************************************************************************
+ * *
+ * Looking for a quick start? Then check out the FreeRTOS eBook! *
+ * See http://www.FreeRTOS.org/Documentation for details *
+ * *
+ ***************************************************************************
+
+ 1 tab == 4 spaces!
+
+ Please ensure to read the configuration and relevant port sections of the
+ online documentation.
+
+ http://www.FreeRTOS.org - Documentation, latest information, license and
+ contact details.
+
+ http://www.SafeRTOS.com - A version that is certified for use in safety
+ critical systems.
+
+ http://www.OpenRTOS.com - Commercial support, development, porting,
+ licensing and training services.
+*/
+
+/*-----------------------------------------------------------
+ * Simple parallel port IO routines.
+ *-----------------------------------------------------------*/
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* Demo app includes. */
+#include "system.h"
+#include "altera_avalon_pio_regs.h"
+#include "partest.h"
+
+/*---------------------------------------------------------------------------*/
+
+#define partstNUM_LEDS ( 8 )
+
+/*---------------------------------------------------------------------------*/
+
+static unsigned portLONG ulLedStates;
+
+/*---------------------------------------------------------------------------*/
+
+void vParTestInitialise( void )
+{
+ IOWR_ALTERA_AVALON_PIO_DIRECTION( LED_PIO_BASE, ALTERA_AVALON_PIO_DIRECTION_OUTPUT );
+ ulLedStates = 0;
+}
+/*-----------------------------------------------------------*/
+
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
+{
+ if( uxLED < partstNUM_LEDS )
+ {
+ taskENTER_CRITICAL();
+ {
+ if ( xValue > 0 )
+ {
+ ulLedStates |= 1 << uxLED;
+ }
+ else
+ {
+ ulLedStates &= ~( 1 << uxLED );
+ }
+ IOWR_ALTERA_AVALON_PIO_DATA( LED_PIO_BASE, ulLedStates );
+ }
+ taskEXIT_CRITICAL();
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
+{
+ if( uxLED < partstNUM_LEDS )
+ {
+ taskENTER_CRITICAL();
+ {
+ vParTestSetLED( uxLED, !( ulLedStates & ( 1 << uxLED ) ) );
+ }
+ taskEXIT_CRITICAL();
+ }
+}
+/*-----------------------------------------------------------*/
diff --git a/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/application.stf b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/application.stf
new file mode 100644
index 000000000..1fc6df552
--- /dev/null
+++ b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/application.stf
@@ -0,0 +1,5 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<stf>
+ <project sdk="RTOSDemo_syslib" target="Nios II Application">
+ </project>
+</stf>
diff --git a/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/main.c b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/main.c
new file mode 100644
index 000000000..a1368ab2b
--- /dev/null
+++ b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/main.c
@@ -0,0 +1,552 @@
+/*
+ FreeRTOS V5.4.1 - Copyright (C) 2009 Real Time Engineers Ltd.
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation and modified by the FreeRTOS exception.
+ **NOTE** The exception to the GPL is included to allow you to distribute a
+ combined work that includes FreeRTOS without being obliged to provide the
+ source code for proprietary components outside of the FreeRTOS kernel.
+ Alternative commercial license and support terms are also available upon
+ request. See the licensing section of http://www.FreeRTOS.org for full
+ license details.
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details.
+
+ You should have received a copy of the GNU General Public License along
+ with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59
+ Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+
+
+ ***************************************************************************
+ * *
+ * Looking for a quick start? Then check out the FreeRTOS eBook! *
+ * See http://www.FreeRTOS.org/Documentation for details *
+ * *
+ ***************************************************************************
+
+ 1 tab == 4 spaces!
+
+ Please ensure to read the configuration and relevant port sections of the
+ online documentation.
+
+ http://www.FreeRTOS.org - Documentation, latest information, license and
+ contact details.
+
+ http://www.SafeRTOS.com - A version that is certified for use in safety
+ critical systems.
+
+ http://www.OpenRTOS.com - Commercial support, development, porting,
+ licensing and training services.
+*/
+
+/*
+ * Creates all the demo application tasks, then starts the scheduler.
+ * In addition to the standard demo tasks, the following tasks and tests are
+ * defined and/or created within this file:
+ *
+ * "Check" task - This only executes every five seconds but has the highest
+ * priority so is guaranteed to get processor time. Its main function is to
+ * check that all the standard demo tasks are still operational. The check
+ * task will write an error message to the console should an error be detected
+ * within any of the demo tasks. The check task also toggles the LED defined
+ * by mainCHECK_LED every 5 seconds while the system is error free, with the
+ * toggle rate increasing to every 500ms should an error occur.
+ *
+ * "Reg test" tasks - These fill the registers with known values, then check
+ * that each register still contains its expected value. Each task uses
+ * different values. The tasks run with very low priority so get preempted very
+ * frequently. A register containing an unexpected value is indicative of an
+ * error in the context switching mechanism.
+ *
+ * See the online documentation for this demo for more information on interrupt
+ * usage.
+ */
+
+/* Standard includes. */
+#include <stddef.h>
+#include <stdio.h>
+#include <string.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+/* Demo application includes. */
+#include "partest.h"
+#include "flash.h"
+#include "blocktim.h"
+#include "semtest.h"
+#include "serial.h"
+#include "comtest.h"
+#include "GenQTest.h"
+#include "QPeek.h"
+#include "integer.h"
+#include "PollQ.h"
+#include "BlockQ.h"
+#include "dynamic.h"
+#include "countsem.h"
+#include "recmutex.h"
+#include "death.h"
+
+/*-----------------------------------------------------------*/
+
+/* The rate at which the LED controlled by the 'check' task will toggle when no
+errors have been detected. */
+#define mainNO_ERROR_PERIOD ( 5000 )
+
+/* The rate at which the LED controlled by the 'check' task will toggle when an
+error has been detected. */
+#define mainERROR_PERIOD ( 500 )
+
+/* The LED toggled by the Check task. */
+#define mainCHECK_LED ( 7 )
+
+/* The first LED used by the ComTest tasks. One LED toggles each time a
+character is transmitted, and one each time a character is received and
+verified as being the expected character. */
+#define mainCOMTEST_LED ( 4 )
+
+/* Priority definitions for the tasks in the demo application. */
+#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 )
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )
+#define mainQUEUE_BLOCK_PRIORITY ( tskIDLE_PRIORITY + 3 )
+#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )
+#define mainSEMAPHORE_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
+#define mainGENERIC_QUEUE_PRIORITY ( tskIDLE_PRIORITY )
+#define mainREG_TEST_PRIORITY ( tskIDLE_PRIORITY )
+
+/* Misc. */
+#define mainDONT_WAIT ( 0 )
+
+/* The parameters passed to the reg test tasks. This is just done to check
+the parameter passing mechanism is working correctly. */
+#define mainREG_TEST_1_PARAMETER ( ( void * ) 0x12345678 )
+#define mainREG_TEST_2_PARAMETER ( ( void * ) 0x87654321 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the processor ready for the demo.
+ */
+static void prvSetupHardware( void );
+
+/*
+ * Execute all of the check functions to ensure the tests haven't failed.
+ */
+static void prvCheckTask( void *pvParameters );
+
+/*
+ * The register test (or RegTest) tasks as described at the top of this file.
+ */
+static void prvFirstRegTestTask( void *pvParameters );
+static void prvSecondRegTestTask( void *pvParameters );
+
+/*-----------------------------------------------------------*/
+
+/* Counters that are incremented on each iteration of the RegTest tasks
+so long as no errors have been detected. */
+volatile unsigned long ulRegTest1Counter = 0UL, ulRegTest2Counter = 0UL;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Create the demo tasks then start the scheduler.
+ */
+int main( void )
+{
+ /* Configure any hardware required for this demo. */
+ prvSetupHardware();
+
+ /* Create all the other standard demo tasks. These serve no purpose other
+ than to test the port and demonstrate the use of the FreeRTOS API. */
+ vStartLEDFlashTasks( tskIDLE_PRIORITY );
+ vStartIntegerMathTasks( mainGENERIC_QUEUE_PRIORITY );
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
+ vStartBlockingQueueTasks( mainQUEUE_BLOCK_PRIORITY );
+ vCreateBlockTimeTasks();
+ vStartSemaphoreTasks( mainSEMAPHORE_TASK_PRIORITY );
+ vStartDynamicPriorityTasks();
+ vStartQueuePeekTasks();
+ vStartGenericQueueTasks( mainGENERIC_QUEUE_PRIORITY );
+ vStartCountingSemaphoreTasks();
+ vStartRecursiveMutexTasks();
+ vAltStartComTestTasks( mainCOM_TEST_PRIORITY, 0, mainCOMTEST_LED );
+
+ /* prvCheckTask uses sprintf so requires more stack. */
+ xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
+
+ /* The RegTest tasks as described at the top of this file. */
+ xTaskCreate( prvFirstRegTestTask, "Rreg1", configMINIMAL_STACK_SIZE, mainREG_TEST_1_PARAMETER, mainREG_TEST_PRIORITY, NULL );
+ xTaskCreate( prvSecondRegTestTask, "Rreg2", configMINIMAL_STACK_SIZE, mainREG_TEST_2_PARAMETER, mainREG_TEST_PRIORITY, NULL );
+
+ /* This task has to be created last as it keeps account of the number of tasks
+ it expects to see running. */
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );
+
+ /* Finally start the scheduler. */
+ vTaskStartScheduler();
+
+ /* Will only reach here if there is insufficient heap available to start
+ the scheduler. */
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupHardware( void )
+{
+ /* Setup the digital IO for the LED's. */
+ vParTestInitialise();
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationStackOverflowHook( void )
+{
+ /* Look at pxCurrentTCB to see which task overflowed its stack. */
+ for( ;; )
+ {
+ asm( "break" );
+ }
+}
+/*-----------------------------------------------------------*/
+
+void _general_exception_handler( unsigned portLONG ulCause, unsigned portLONG ulStatus )
+{
+ /* This overrides the definition provided by the kernel. Other exceptions
+ should be handled here. */
+ for( ;; )
+ {
+ asm( "break" );
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckTask( void *pvParameters )
+{
+portTickType xLastExecutionTime, ulTicksToWait = mainNO_ERROR_PERIOD;
+unsigned long ulLastRegTest1 = 0UL, ulLastRegTest2 = 0UL;
+const portCHAR * pcMessage;
+
+ /* Initialise the variable used to control our iteration rate prior to
+ its first use. */
+ xLastExecutionTime = xTaskGetTickCount();
+
+ for( ;; )
+ {
+ /* Wait until it is time to run the tests again. */
+ vTaskDelayUntil( &xLastExecutionTime, ulTicksToWait );
+
+ /* Have any of the standard demo tasks detected an error in their
+ operation? */
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
+ {
+ ulTicksToWait = mainERROR_PERIOD;
+ pcMessage = "Error: Integer Maths.\n";
+ }
+ else if( xAreGenericQueueTasksStillRunning() != pdTRUE )
+ {
+ ulTicksToWait = mainERROR_PERIOD;
+ pcMessage = "Error: GenQ.\n";
+ }
+ else if( xAreBlockingQueuesStillRunning() != pdTRUE )
+ {
+ ulTicksToWait = mainERROR_PERIOD;
+ pcMessage = "Error: BlockQ.\n";
+ }
+ else if( xArePollingQueuesStillRunning() != pdTRUE )
+ {
+ ulTicksToWait = mainERROR_PERIOD;
+ pcMessage = "Error: PollQ.\n";
+ }
+ else if( xAreQueuePeekTasksStillRunning() != pdTRUE )
+ {
+ ulTicksToWait = mainERROR_PERIOD;
+ pcMessage = "Error: PeekQ.\n";
+ }
+ else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
+ {
+ ulTicksToWait = mainERROR_PERIOD;
+ pcMessage = "Error: Block Time.\n";
+ }
+ else if( xAreSemaphoreTasksStillRunning() != pdTRUE )
+ {
+ ulTicksToWait = mainERROR_PERIOD;
+ pcMessage = "Error: Semaphore Test.\n";
+ }
+ else if( xAreComTestTasksStillRunning() != pdTRUE )
+ {
+ ulTicksToWait = mainERROR_PERIOD;
+ pcMessage = "Error: Comm Test.\n";
+ }
+ else if( xIsCreateTaskStillRunning() != pdTRUE )
+ {
+ ulTicksToWait = mainERROR_PERIOD;
+ pcMessage = "Error: Suicidal Tasks.\n";
+ }
+ else if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
+ {
+ ulTicksToWait = mainERROR_PERIOD;
+ pcMessage = "Error: Dynamic Priority.\n";
+ }
+ else if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE )
+ {
+ ulTicksToWait = mainERROR_PERIOD;
+ pcMessage = "Error: Count Semaphore.\n";
+ }
+ else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
+ {
+ ulTicksToWait = mainERROR_PERIOD;
+ pcMessage = "Error: Recursive Mutex.\n";
+ }
+ else if( ulLastRegTest1 == ulRegTest1Counter )
+ {
+ /* ulRegTest1Counter is no longer being incremented, indicating
+ that an error has been discovered in prvFirstRegTestTask(). */
+ ulTicksToWait = mainERROR_PERIOD;
+ pcMessage = "Error: Reg Test1.\n";
+ }
+ else if( ulLastRegTest2 == ulRegTest2Counter )
+ {
+ /* ulRegTest2Counter is no longer being incremented, indicating
+ that an error has been discovered in prvSecondRegTestTask(). */
+ ulTicksToWait = mainERROR_PERIOD;
+ pcMessage = "Error: Reg Test2.\n";
+ }
+ else
+ {
+ pcMessage = NULL;
+ }
+
+ /* Remember the counter values this time around so a counter failing
+ to be incremented correctly can be spotted. */
+ ulLastRegTest1 = ulRegTest1Counter;
+ ulLastRegTest2 = ulRegTest2Counter;
+
+ /* Print out an error message if there is one. Mutual exclusion is
+ not used as this is the only task accessing stdout. */
+ if( pcMessage != NULL )
+ {
+ printf( pcMessage );
+ }
+
+ /* Provide visual feedback of the system status. If the LED is toggled
+ every 5 seconds then no errors have been found. If the LED is toggled
+ every 500ms then at least one error has been found. */
+ vParTestToggleLED( mainCHECK_LED );
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvFirstRegTestTask( void *pvParameters )
+{
+ /* Check the parameters are passed in as expected. */
+ if( pvParameters != mainREG_TEST_1_PARAMETER )
+ {
+ /* Don't execute any further so an error is recognised by the check
+ task. */
+ vTaskDelete( NULL );
+ }
+
+ /* Fill registers with known values, then check that each register still
+ contains its expected value. An incorrect value is indicative of an error
+ in the context switching process.
+
+ If no errors are found ulRegTest1Counter is incremented. The check task
+ will recognise an error if ulRegTest1Counter stops being incremented.
+ This task also performs a manual yield in the middle of its execution, just
+ to increase the test coverage. */
+ asm volatile (
+ " .extern ulRegTest1Counter \n" \
+ " \n" \
+ " addi r3, r0, 3 \n" \
+ " addi r4, r0, 4 \n" \
+ " addi r5, r0, 5 \n" \
+ " addi r6, r0, 6 \n" \
+ " addi r7, r0, 7 \n" \
+ " addi r8, r0, 8 \n" \
+ " addi r9, r0, 9 \n" \
+ " addi r10, r0, 10 \n" \
+ " addi r11, r0, 11 \n" \
+ " addi r12, r0, 12 \n" \
+ " addi r13, r0, 13 \n" \
+ " addi r14, r0, 14 \n" \
+ " addi r15, r0, 15 \n" \
+ " addi r16, r0, 16 \n" \
+ " addi r17, r0, 17 \n" \
+ " addi r18, r0, 18 \n" \
+ " addi r19, r0, 19 \n" \
+ " addi r20, r0, 20 \n" \
+ " addi r21, r0, 21 \n" \
+ " addi r22, r0, 22 \n" \
+ " addi r23, r0, 23 \n" \
+ " addi r28, r0, 28 \n" \
+ " addi r31, r0, 31 \n" \
+ "RegTest1: \n" \
+ " addi r2, r0, 0 \n" \
+ " trap \n" \
+ " bne r2, r0, RegTest1Error \n" \
+ " addi r2, r0, 3 \n" \
+ " bne r2, r3, RegTest1Error \n" \
+ " addi r2, r0, 4 \n" \
+ " bne r2, r4, RegTest1Error \n" \
+ " addi r2, r0, 5 \n" \
+ " bne r2, r5, RegTest1Error \n" \
+ " addi r2, r0, 6 \n" \
+ " bne r2, r6, RegTest1Error \n" \
+ " addi r2, r0, 7 \n" \
+ " bne r2, r7, RegTest1Error \n" \
+ " addi r2, r0, 8 \n" \
+ " bne r2, r8, RegTest1Error \n" \
+ " addi r2, r0, 9 \n" \
+ " bne r2, r9, RegTest1Error \n" \
+ " addi r2, r0, 10 \n" \
+ " bne r2, r10, RegTest1Error \n" \
+ " addi r2, r0, 11 \n" \
+ " bne r2, r11, RegTest1Error \n" \
+ " addi r2, r0, 12 \n" \
+ " bne r2, r12, RegTest1Error \n" \
+ " addi r2, r0, 13 \n" \
+ " bne r2, r13, RegTest1Error \n" \
+ " addi r2, r0, 14 \n" \
+ " bne r2, r14, RegTest1Error \n" \
+ " addi r2, r0, 15 \n" \
+ " bne r2, r15, RegTest1Error \n" \
+ " addi r2, r0, 16 \n" \
+ " bne r2, r16, RegTest1Error \n" \
+ " addi r2, r0, 17 \n" \
+ " bne r2, r17, RegTest1Error \n" \
+ " addi r2, r0, 18 \n" \
+ " bne r2, r18, RegTest1Error \n" \
+ " addi r2, r0, 19 \n" \
+ " bne r2, r19, RegTest1Error \n" \
+ " addi r2, r0, 20 \n" \
+ " bne r2, r20, RegTest1Error \n" \
+ " addi r2, r0, 21 \n" \
+ " bne r2, r21, RegTest1Error \n" \
+ " addi r2, r0, 22 \n" \
+ " bne r2, r22, RegTest1Error \n" \
+ " addi r2, r0, 23 \n" \
+ " bne r2, r23, RegTest1Error \n" \
+ " addi r2, r0, 28 \n" \
+ " bne r2, r28, RegTest1Error \n" \
+ " addi r2, r0, 31 \n" \
+ " bne r2, r31, RegTest1Error \n" \
+ " ldw r2, %gprel(ulRegTest1Counter)(gp) \n" \
+ " addi r2, r2, 1 \n" \
+ " stw r2, %gprel(ulRegTest1Counter)(gp) \n" \
+ " br RegTest1 \n" \
+ "RegTest1Error: \n" \
+ " br RegTest1Error \n"
+ );
+}
+/*-----------------------------------------------------------*/
+
+static void prvSecondRegTestTask( void *pvParameters )
+{
+ /* Check the parameters are passed in as expected. */
+ if( pvParameters != mainREG_TEST_2_PARAMETER )
+ {
+ /* Don't execute any further so an error is recognised by the check
+ task. */
+ vTaskDelete( NULL );
+ }
+
+ /* Fill registers with known values, then check that each register still
+ contains its expected value. An incorrect value is indicative of an error
+ in the context switching process.
+
+ If no errors are found ulRegTest2Counter is incremented. The check task
+ will recognise an error if ulRegTest2Counter stops being incremented. */
+ asm volatile (
+ " .extern ulRegTest2Counter \n" \
+ " \n" \
+ " addi r3, r0, 3 \n" \
+ " addi r4, r0, 4 \n" \
+ " addi r5, r0, 5 \n" \
+ " addi r6, r0, 6 \n" \
+ " addi r7, r0, 7 \n" \
+ " addi r8, r0, 8 \n" \
+ " addi r9, r0, 9 \n" \
+ " addi r10, r0, 10 \n" \
+ " addi r11, r0, 11 \n" \
+ " addi r12, r0, 12 \n" \
+ " addi r13, r0, 13 \n" \
+ " addi r14, r0, 14 \n" \
+ " addi r15, r0, 15 \n" \
+ " addi r16, r0, 16 \n" \
+ " addi r17, r0, 17 \n" \
+ " addi r18, r0, 18 \n" \
+ " addi r19, r0, 19 \n" \
+ " addi r20, r0, 20 \n" \
+ " addi r21, r0, 21 \n" \
+ " addi r22, r0, 22 \n" \
+ " addi r23, r0, 23 \n" \
+ " addi r28, r0, 28 \n" \
+ " addi r31, r0, 31 \n" \
+ "RegTest2: \n" \
+ " addi r2, r0, 0 \n" \
+ " bne r2, r0, RegTest2Error \n" \
+ " addi r2, r0, 3 \n" \
+ " bne r2, r3, RegTest2Error \n" \
+ " addi r2, r0, 4 \n" \
+ " bne r2, r4, RegTest2Error \n" \
+ " addi r2, r0, 5 \n" \
+ " bne r2, r5, RegTest2Error \n" \
+ " addi r2, r0, 6 \n" \
+ " bne r2, r6, RegTest2Error \n" \
+ " addi r2, r0, 7 \n" \
+ " bne r2, r7, RegTest2Error \n" \
+ " addi r2, r0, 8 \n" \
+ " bne r2, r8, RegTest2Error \n" \
+ " addi r2, r0, 9 \n" \
+ " bne r2, r9, RegTest2Error \n" \
+ " addi r2, r0, 10 \n" \
+ " bne r2, r10, RegTest2Error \n" \
+ " addi r2, r0, 11 \n" \
+ " bne r2, r11, RegTest2Error \n" \
+ " addi r2, r0, 12 \n" \
+ " bne r2, r12, RegTest2Error \n" \
+ " addi r2, r0, 13 \n" \
+ " bne r2, r13, RegTest2Error \n" \
+ " addi r2, r0, 14 \n" \
+ " bne r2, r14, RegTest2Error \n" \
+ " addi r2, r0, 15 \n" \
+ " bne r2, r15, RegTest2Error \n" \
+ " addi r2, r0, 16 \n" \
+ " bne r2, r16, RegTest2Error \n" \
+ " addi r2, r0, 17 \n" \
+ " bne r2, r17, RegTest2Error \n" \
+ " addi r2, r0, 18 \n" \
+ " bne r2, r18, RegTest2Error \n" \
+ " addi r2, r0, 19 \n" \
+ " bne r2, r19, RegTest2Error \n" \
+ " addi r2, r0, 20 \n" \
+ " bne r2, r20, RegTest2Error \n" \
+ " addi r2, r0, 21 \n" \
+ " bne r2, r21, RegTest2Error \n" \
+ " addi r2, r0, 22 \n" \
+ " bne r2, r22, RegTest2Error \n" \
+ " addi r2, r0, 23 \n" \
+ " bne r2, r23, RegTest2Error \n" \
+ " addi r2, r0, 28 \n" \
+ " bne r2, r28, RegTest2Error \n" \
+ " addi r2, r0, 31 \n" \
+ " bne r2, r31, RegTest2Error \n" \
+ " ldw r2, %gprel(ulRegTest2Counter)(gp) \n" \
+ " addi r2, r2, 1 \n" \
+ " stw r2, %gprel(ulRegTest2Counter)(gp) \n" \
+ " br RegTest2 \n" \
+ "RegTest2Error: \n" \
+ " br RegTest2Error \n"
+ );
+}
+/*-----------------------------------------------------------*/
+
diff --git a/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/serial.c b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/serial.c
new file mode 100644
index 000000000..1117e005a
--- /dev/null
+++ b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo/serial.c
@@ -0,0 +1,241 @@
+/*
+ FreeRTOS V5.4.1 - Copyright (C) 2009 Real Time Engineers Ltd.
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation and modified by the FreeRTOS exception.
+ **NOTE** The exception to the GPL is included to allow you to distribute a
+ combined work that includes FreeRTOS without being obliged to provide the
+ source code for proprietary components outside of the FreeRTOS kernel.
+ Alternative commercial license and support terms are also available upon
+ request. See the licensing section of http://www.FreeRTOS.org for full
+ license details.
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details.
+
+ You should have received a copy of the GNU General Public License along
+ with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59
+ Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+
+
+ ***************************************************************************
+ * *
+ * Looking for a quick start? Then check out the FreeRTOS eBook! *
+ * See http://www.FreeRTOS.org/Documentation for details *
+ * *
+ ***************************************************************************
+
+ 1 tab == 4 spaces!
+
+ Please ensure to read the configuration and relevant port sections of the
+ online documentation.
+
+ http://www.FreeRTOS.org - Documentation, latest information, license and
+ contact details.
+
+ http://www.SafeRTOS.com - A version that is certified for use in safety
+ critical systems.
+
+ http://www.OpenRTOS.com - Commercial support, development, porting,
+ licensing and training services.
+*/
+
+/* NOTE: This is just a test file and not intended to be a generic
+COM driver. */
+
+#include "altera_avalon_uart.h"
+#include "altera_avalon_uart_regs.h"
+#include "sys/alt_irq.h"
+
+#include "FreeRTOS.h"
+#include "queue.h"
+#include "system.h"
+#include "Serial.h"
+/*---------------------------------------------------------------------------*/
+
+#define serINVALID_QUEUE ( ( xQueueHandle ) 0 )
+#define serNO_BLOCK ( ( portTickType ) 0 )
+/*---------------------------------------------------------------------------*/
+
+static xQueueHandle xRxedChars;
+static xQueueHandle xCharsForTx;
+
+alt_u32 uartControl;
+/*---------------------------------------------------------------------------*/
+
+static void vUARTInterruptHandler( void* context, alt_u32 id );
+static void vUARTReceiveHandler( alt_u32 status );
+static void vUARTTransmitHandler( alt_u32 status );
+/*---------------------------------------------------------------------------*/
+
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
+{
+ /* Create the queues used to hold Rx and Tx characters. */
+ xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
+ xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
+
+ /* If the queues were created correctly then setup the serial port hardware. */
+ if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) )
+ {
+ portENTER_CRITICAL();
+ {
+ uartControl = ALTERA_AVALON_UART_CONTROL_RTS_MSK | ALTERA_AVALON_UART_CONTROL_RRDY_MSK | ALTERA_AVALON_UART_CONTROL_DCTS_MSK;
+ IOWR_ALTERA_AVALON_UART_CONTROL( UART_BASE, uartControl );
+
+ /* register the interrupt handler */
+ alt_irq_register ( UART_IRQ, NULL, vUARTInterruptHandler );
+ }
+ portEXIT_CRITICAL();
+ }
+ else
+ {
+ return ( xComPortHandle ) 0;
+ }
+ return ( xComPortHandle ) 1;
+}
+/*---------------------------------------------------------------------------*/
+
+void vSerialClose( xComPortHandle xPort )
+{
+ /* Never used. */
+}
+/*---------------------------------------------------------------------------*/
+
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )
+{
+ /* The port handle is not required as this driver only supports one port. */
+ ( void ) pxPort;
+
+
+ /* Get the next character from the buffer. Return false if no characters
+ are available, or arrive before xBlockTime expires. */
+ if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
+ {
+ return pdTRUE;
+ }
+ else
+ {
+ uartControl |= ALTERA_AVALON_UART_CONTROL_RRDY_MSK;
+ IOWR_ALTERA_AVALON_UART_CONTROL( UART_BASE, uartControl );
+ return pdFALSE;
+ }
+}
+/*---------------------------------------------------------------------------*/
+
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )
+{
+signed portBASE_TYPE lReturn = pdPASS;
+
+ /* Place the character in the queue of characters to be transmitted. */
+ if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) == pdPASS )
+ {
+ /*Triggers an interrupt on every character or (down) when queue is full. */
+ uartControl |= ALTERA_AVALON_UART_CONTROL_TRDY_MSK;
+ IOWR_ALTERA_AVALON_UART_CONTROL( UART_BASE, uartControl );
+ lReturn = pdPASS;
+ }
+ else
+ {
+ lReturn = pdFAIL;
+ }
+ return lReturn;
+}
+/*---------------------------------------------------------------------------*/
+
+void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength )
+{
+signed portCHAR *pxNext;
+
+ /* A couple of parameters that this port does not use. */
+ ( void ) usStringLength;
+ ( void ) pxPort;
+
+ /* NOTE: This implementation does not handle the queue being full as no block time is used! */
+
+ /* The port handle is not required as this driver only supports UART0. */
+ ( void ) pxPort;
+
+ /* Send each character in the string, one at a time. */
+ pxNext = ( signed portCHAR * ) pcString;
+ while( *pxNext )
+ {
+ xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );
+ pxNext++;
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void vUARTInterruptHandler( void* context, alt_u32 id )
+{
+ alt_u32 status;
+
+ /* Read the status register in order to determine the cause of the
+ interrupt. */
+ status = IORD_ALTERA_AVALON_UART_STATUS( UART_BASE );
+
+ /* Clear any error flags set at the device */
+ IOWR_ALTERA_AVALON_UART_STATUS( UART_BASE, 0 );
+
+ /* process a read irq */
+ if ( status & ALTERA_AVALON_UART_STATUS_RRDY_MSK )
+ {
+ vUARTReceiveHandler( status );
+ }
+
+ /* process a write irq */
+ if ( status & ( ALTERA_AVALON_UART_STATUS_TRDY_MSK ) )
+ {
+ vUARTTransmitHandler( status );
+ }
+}
+/*---------------------------------------------------------------------------*/
+
+static void vUARTReceiveHandler( alt_u32 status )
+{
+signed portCHAR cChar;
+portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
+
+ /* If there was an error, discard the data */
+ if ( status & ( ALTERA_AVALON_UART_STATUS_PE_MSK | ALTERA_AVALON_UART_STATUS_FE_MSK ) )
+ {
+ asm("break");
+ return;
+ }
+
+ /* Transfer data from the device to the circular buffer */
+ cChar = IORD_ALTERA_AVALON_UART_RXDATA( UART_BASE );
+ if ( pdTRUE != xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken ) )
+ {
+ /* If the circular buffer was full, disable interrupts. Interrupts will
+ be re-enabled when data is removed from the buffer. */
+ uartControl &= ~ALTERA_AVALON_UART_CONTROL_RRDY_MSK;
+ IOWR_ALTERA_AVALON_UART_CONTROL( UART_BASE, uartControl );
+ }
+
+ portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
+}
+/*---------------------------------------------------------------------------*/
+
+static void vUARTTransmitHandler( alt_u32 status )
+{
+signed portCHAR cChar;
+portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
+ /* Transfer data if there is some ready to be transferred */
+ if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE )
+ {
+ IOWR_ALTERA_AVALON_UART_TXDATA( UART_BASE, cChar );
+ }
+ else
+ {
+ uartControl &= ~ALTERA_AVALON_UART_CONTROL_TRDY_MSK;
+ }
+
+ IOWR_ALTERA_AVALON_UART_CONTROL( UART_BASE, uartControl );
+ portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
+}
+/*---------------------------------------------------------------------------*/
diff --git a/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo_syslib/.cdtbuild b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo_syslib/.cdtbuild
new file mode 100644
index 000000000..51b300907
--- /dev/null
+++ b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo_syslib/.cdtbuild
@@ -0,0 +1,19 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 3.1.0?>
+
+<ManagedProjectBuildInfo>
+<project id="RTOSDemo_syslib.nios2.lib.1122692399" name="Nios II Library" projectType="nios2.lib">
+<configuration artifactExtension="a" artifactName="RTOSDemo_syslib" cleanCommand="rm -rf" description="" errorParsers="org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser" id="nios2.lib.debug.1710955039" name="Debug" parent="nios2.lib.debug">
+<toolChain id="com.altera.nj.ui.lib.Debug.629598059" name="com.altera.nj.ui.lib.Debug" superClass="com.altera.nj.ui.lib.Debug">
+<tool id="com.altera.nj.ui.tool.compiler.lib.debug.2113232429" name="Nios II Compiler" superClass="com.altera.nj.ui.tool.compiler.lib.debug"/>
+<tool id="com.altera.nj.ui.tool.archiver.lib.debug.346993942" name="Archiver" superClass="com.altera.nj.ui.tool.archiver.lib.debug"/>
+</toolChain>
+</configuration>
+<configuration artifactExtension="a" artifactName="RTOSDemo_syslib" cleanCommand="rm -rf" description="" errorParsers="org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser" id="nios2.lib.release.872414519" name="Release" parent="nios2.lib.release">
+<toolChain id="com.altera.nj.ui.lib.Release.1045176498" name="com.altera.nj.ui.lib.Release" superClass="com.altera.nj.ui.lib.Release">
+<tool id="com.altera.nj.ui.tool.compiler.lib.release.1684787927" name="Nios II Compiler" superClass="com.altera.nj.ui.tool.compiler.lib.release"/>
+<tool id="com.altera.nj.ui.tool.archiver.lib.release.2019566308" name="Archiver" superClass="com.altera.nj.ui.tool.archiver.lib.release"/>
+</toolChain>
+</configuration>
+</project>
+</ManagedProjectBuildInfo>
diff --git a/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo_syslib/.cdtproject b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo_syslib/.cdtproject
new file mode 100644
index 000000000..1b8aa2e3c
--- /dev/null
+++ b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo_syslib/.cdtproject
@@ -0,0 +1,59 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?eclipse-cdt version="2.0"?>
+
+<cdtproject id="org.eclipse.cdt.managedbuilder.core.managedMake">
+<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+<extension id="org.eclipse.cdt.managedbuilder.core.ManagedBuildManager" point="org.eclipse.cdt.core.ScannerInfoProvider"/>
+<data>
+<item id="scannerConfiguration">
+<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile"/>
+<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+<buildOutputProvider>
+<openAction enabled="true" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="specsFile">
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+<parser enabled="true"/>
+</scannerInfoProvider>
+</profile>
+<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+<buildOutputProvider>
+<openAction enabled="false" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="makefileGenerator">
+<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+<parser enabled="false"/>
+</scannerInfoProvider>
+</profile>
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+<buildOutputProvider>
+<openAction enabled="false" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="specsFile">
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+<parser enabled="false"/>
+</scannerInfoProvider>
+</profile>
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+<buildOutputProvider>
+<openAction enabled="false" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="specsFile">
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+<parser enabled="false"/>
+</scannerInfoProvider>
+</profile>
+</item>
+<item id="org.eclipse.cdt.core.pathentry">
+<pathentry kind="src" path=""/>
+<pathentry kind="out" path=""/>
+<pathentry kind="con" path="org.eclipse.cdt.make.core.DISCOVERED_SCANNER_INFO"/>
+<pathentry kind="con" path="org.eclipse.cdt.managedbuilder.MANAGED_CONTAINER"/>
+</item>
+</data>
+</cdtproject>
diff --git a/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo_syslib/.project b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo_syslib/.project
new file mode 100644
index 000000000..7e6d03ef0
--- /dev/null
+++ b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo_syslib/.project
@@ -0,0 +1,89 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>RTOSDemo_syslib</name>
+ <comment></comment>
+ <projects>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.make.core.makeBuilder</name>
+ <triggers>clean,full,incremental,</triggers>
+ <arguments>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+ <value>false</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.append_environment</key>
+ <value>true</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.stopOnError</key>
+ <value>false</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.enabledIncrementalBuild</key>
+ <value>false</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.build.command</key>
+ <value>make</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.build.target.inc</key>
+ <value>all</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.build.arguments</key>
+ <value></value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+ <value>true</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.environment</key>
+ <value></value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.enableFullBuild</key>
+ <value>false</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.build.target.auto</key>
+ <value>all</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+ <value>false</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.build.target.clean</key>
+ <value>clean</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.core.errorOutputParser</key>
+ <value>org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.VCErrorParser;</value>
+ </dictionary>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>com.altera.ide.core.alterabuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>org.eclipse.cdt.make.core.ScannerConfigBuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>com.altera.ide.core.AlteraNios2Nature</nature>
+ <nature>com.altera.ide.core.AlteraSDKNature</nature>
+ <nature>org.eclipse.cdt.make.core.makeNature</nature>
+ <nature>org.eclipse.cdt.make.core.ScannerConfigNature</nature>
+ </natures>
+</projectDescription>
diff --git a/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo_syslib/.settings/org.eclipse.cdt.core.prefs b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo_syslib/.settings/org.eclipse.cdt.core.prefs
new file mode 100644
index 000000000..726d3f5c0
--- /dev/null
+++ b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo_syslib/.settings/org.eclipse.cdt.core.prefs
@@ -0,0 +1,3 @@
+#Tue Aug 04 21:28:00 BST 2009
+eclipse.preferences.version=1
+indexerId=org.eclipse.cdt.core.fastIndexer
diff --git a/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo_syslib/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo_syslib/.settings/org.eclipse.cdt.managedbuilder.core.prefs
new file mode 100644
index 000000000..645b38a21
--- /dev/null
+++ b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo_syslib/.settings/org.eclipse.cdt.managedbuilder.core.prefs
@@ -0,0 +1,6 @@
+#Tue Aug 04 21:27:57 BST 2009
+eclipse.preferences.version=1
+nios2.lib.debug.1710955039/internalBuilder/enabled=false
+nios2.lib.debug.1710955039/internalBuilder/ignoreErr=true
+nios2.lib.release.872414519/internalBuilder/enabled=false
+nios2.lib.release.872414519/internalBuilder/ignoreErr=true
diff --git a/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo_syslib/readme.txt b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo_syslib/readme.txt
new file mode 100644
index 000000000..18be4e2d5
--- /dev/null
+++ b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo_syslib/readme.txt
@@ -0,0 +1,20 @@
+/*******************************************************************************
+*
+* System Library Project
+* ======================
+*
+* This is the library project custom created for your hardware system.
+* It is built up from auto-generated files and component source files.
+*
+* The auto-generated system source files can be found in:
+* <configuration_folder>/system_description
+* e.g. Release/system_description/system.h *
+*
+* The component source files from the relevant sopc component folders
+* e.g. <sopc_kit_nios2>/components/altera_nios2
+*
+* To change the system library build properties, right click on the project
+* and select properties. This allows you to set options like timers,
+* memory sections and build options.
+* *
+*******************************************************************************/
diff --git a/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo_syslib/system.stf b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo_syslib/system.stf
new file mode 100644
index 000000000..6edcd69f0
--- /dev/null
+++ b/Demo/NiosII_CycloneIII_DBC3C40_GCC/RTOSDemo_syslib/system.stf
@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<stf>
+ <project ptf="C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\NiosII_CycloneIII_DBC3C40_GCC\cpu.ptf" target="Nios II System Library">
+ </project>
+ <cpu name="cpu_0">
+ </cpu>
+ <os_spec clean_exit="yes" direct_drivers="no" exception_stack="no" instruction_emulation="no" name="none (single-threaded)" no_c_plus_plus="no" no_exit="no" profiling="no" small_footprint="no" sopc_component_dir="altera_hal" stack_checking="no" stderr="jtag_uart_0" stdin="jtag_uart_0" stdout="jtag_uart_0">
+ <sys_defines>
+<define name="alt_max_fd" quote="no" value="32"/>
+<define name="alt_sys_clk" quote="no" value="SYS_CLK"/>
+<define name="alt_timestamp_clk" quote="no" value="none"/>
+</sys_defines>
+<make_macros>
+<macro name="alt_sim_optimize" quote="no" value="0"/>
+</make_macros>
+</os_spec>
+ <link_spec auto_gen_script="yes">
+ <script name="none">
+ <section memory="sdram" name=".text"/>
+<section memory="sdram" name=".rodata"/>
+<section memory="sdram" name=".rwdata"/>
+<section memory="sdram" name=".stack"/>
+<section memory="sdram" name=".heap"/>
+<section memory="sdram" name=".exceptionstack" size="0x400"/>
+</script>
+ </link_spec>
+</stf>
diff --git a/Demo/NiosII_CycloneIII_DBC3C40_GCC/cpu.ptf b/Demo/NiosII_CycloneIII_DBC3C40_GCC/cpu.ptf
new file mode 100644
index 000000000..d8959410c
--- /dev/null
+++ b/Demo/NiosII_CycloneIII_DBC3C40_GCC/cpu.ptf
@@ -0,0 +1,4855 @@
+SYSTEM cpu
+{
+ System_Wizard_Version = "8.00";
+ System_Wizard_Build = "215";
+ Builder_Application = "sopc_builder_ca";
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ hdl_language = "vhdl";
+ device_family = "CYCLONEIII";
+ device_family_id = "CYCLONEIII";
+ generate_sdk = "0";
+ do_build_sim = "0";
+ hardcopy_compatible = "0";
+ CLOCKS
+ {
+ CLOCK clk
+ {
+ frequency = "75000000";
+ source = "External";
+ Is_Clock_Source = "0";
+ display_name = "clk";
+ pipeline = "0";
+ clock_module_connection_point_for_c2h = "clk.clk";
+ }
+ }
+ clock_freq = "75000000";
+ clock_freq = "75000000";
+ board_class = "";
+ view_master_columns = "1";
+ view_master_priorities = "0";
+ generate_hdl = "";
+ bustype_column_width = "0";
+ clock_column_width = "80";
+ name_column_width = "75";
+ desc_column_width = "75";
+ base_column_width = "75";
+ end_column_width = "75";
+ BOARD_INFO
+ {
+ altera_avalon_epcs_flash_controller
+ {
+ reference_designators = "";
+ }
+ altera_avalon_cfi_flash
+ {
+ reference_designators = "";
+ }
+ }
+ do_log_history = "0";
+ }
+ MODULE cpu_0
+ {
+ MASTER instruction_master
+ {
+ PORT_WIRING
+ {
+ PORT clk
+ {
+ type = "clk";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT reset_n
+ {
+ type = "reset_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "0";
+ }
+ PORT i_address
+ {
+ type = "address";
+ width = "25";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT i_read
+ {
+ type = "read";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT i_readdata
+ {
+ type = "readdata";
+ width = "32";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT i_readdatavalid
+ {
+ type = "readdatavalid";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT i_waitrequest
+ {
+ type = "waitrequest";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon";
+ Is_Asynchronous = "0";
+ DBS_Big_Endian = "0";
+ Adapts_To = "";
+ Do_Stream_Reads = "0";
+ Do_Stream_Writes = "0";
+ Max_Address_Width = "32";
+ Data_Width = "32";
+ Address_Width = "25";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "0";
+ Register_Outgoing_Signals = "0";
+ Interleave_Bursts = "";
+ Linewrap_Bursts = "";
+ Burst_On_Burst_Boundaries_Only = "";
+ Always_Burst_Max_Burst = "";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ Is_Instruction_Master = "1";
+ Is_Readable = "1";
+ Is_Writeable = "0";
+ Address_Group = "0";
+ Has_IRQ = "0";
+ Irq_Scheme = "individual_requests";
+ Interrupt_Range = "0-0";
+ }
+ MEMORY_MAP
+ {
+ Entry cpu_0/jtag_debug_module
+ {
+ address = "0x00901800";
+ span = "0x00000800";
+ is_bridge = "0";
+ }
+ Entry onchip_memory/s1
+ {
+ address = "0x00904000";
+ span = "0x00002000";
+ is_bridge = "0";
+ }
+ Entry sdram/s1
+ {
+ address = "0x01000000";
+ span = "0x01000000";
+ is_bridge = "0";
+ }
+ Entry epcs_controller/epcs_control_port
+ {
+ address = "0x00906000";
+ span = "0x00000800";
+ is_bridge = "0";
+ }
+ Entry cfi_flash/s1
+ {
+ address = "0x00000000";
+ span = "0x00800000";
+ is_bridge = "0";
+ }
+ Entry DBC3C40_SRAM_inst/avalon_tristate_slave
+ {
+ address = "0x00800000";
+ span = "0x00100000";
+ is_bridge = "0";
+ }
+ }
+ }
+ MASTER custom_instruction_master
+ {
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "nios_custom_instruction";
+ Data_Width = "32";
+ Address_Width = "8";
+ Is_Custom_Instruction = "1";
+ Is_Enabled = "0";
+ Max_Address_Width = "8";
+ Base_Address = "N/A";
+ Is_Visible = "0";
+ }
+ PORT_WIRING
+ {
+ PORT dataa
+ {
+ type = "dataa";
+ width = "32";
+ direction = "output";
+ }
+ PORT datab
+ {
+ type = "datab";
+ width = "32";
+ direction = "output";
+ }
+ PORT result
+ {
+ type = "result";
+ width = "32";
+ direction = "input";
+ }
+ PORT clk_en
+ {
+ type = "clk_en";
+ width = "1";
+ direction = "output";
+ }
+ PORT reset
+ {
+ type = "reset";
+ width = "1";
+ direction = "output";
+ }
+ PORT start
+ {
+ type = "start";
+ width = "1";
+ direction = "output";
+ }
+ PORT done
+ {
+ type = "done";
+ width = "1";
+ direction = "input";
+ }
+ PORT n
+ {
+ type = "n";
+ width = "8";
+ direction = "output";
+ }
+ PORT a
+ {
+ type = "a";
+ width = "5";
+ direction = "output";
+ }
+ PORT b
+ {
+ type = "b";
+ width = "5";
+ direction = "output";
+ }
+ PORT c
+ {
+ type = "c";
+ width = "5";
+ direction = "output";
+ }
+ PORT readra
+ {
+ type = "readra";
+ width = "1";
+ direction = "output";
+ }
+ PORT readrb
+ {
+ type = "readrb";
+ width = "1";
+ direction = "output";
+ }
+ PORT writerc
+ {
+ type = "writerc";
+ width = "1";
+ direction = "output";
+ }
+ }
+ }
+ SLAVE jtag_debug_module
+ {
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon";
+ Write_Wait_States = "0cycles";
+ Read_Wait_States = "1cycles";
+ Hold_Time = "0cycles";
+ Setup_Time = "0cycles";
+ Is_Printable_Device = "0";
+ Address_Alignment = "dynamic";
+ Well_Behaved_Waitrequest = "0";
+ Is_Nonvolatile_Storage = "0";
+ Address_Span = "2048";
+ Read_Latency = "0";
+ Is_Memory_Device = "1";
+ Maximum_Pending_Read_Transactions = "0";
+ Minimum_Uninterrupted_Run_Length = "1";
+ Accepts_Internal_Connections = "1";
+ Write_Latency = "0";
+ Is_Flash = "0";
+ Data_Width = "32";
+ Address_Width = "9";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "0";
+ Register_Outgoing_Signals = "0";
+ Interleave_Bursts = "0";
+ Linewrap_Bursts = "0";
+ Burst_On_Burst_Boundaries_Only = "0";
+ Always_Burst_Max_Burst = "0";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ Accepts_External_Connections = "1";
+ Requires_Internal_Connections = "";
+ MASTERED_BY cpu_0/instruction_master
+ {
+ priority = "1";
+ Offset_Address = "0x00901800";
+ }
+ MASTERED_BY cpu_0/data_master
+ {
+ priority = "1";
+ Offset_Address = "0x00901800";
+ }
+ Base_Address = "0x00901800";
+ Is_Readable = "1";
+ Is_Writeable = "1";
+ Uses_Tri_State_Data_Bus = "0";
+ Has_IRQ = "0";
+ JTAG_Hub_Base_Id = "1118278";
+ JTAG_Hub_Instance_Id = "0";
+ Address_Group = "0";
+ IRQ_MASTER cpu_0/data_master
+ {
+ IRQ_Number = "NC";
+ }
+ }
+ PORT_WIRING
+ {
+ PORT jtag_debug_module_address
+ {
+ type = "address";
+ width = "9";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT jtag_debug_module_begintransfer
+ {
+ type = "begintransfer";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT jtag_debug_module_byteenable
+ {
+ type = "byteenable";
+ width = "4";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT jtag_debug_module_clk
+ {
+ type = "clk";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT jtag_debug_module_debugaccess
+ {
+ type = "debugaccess";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT jtag_debug_module_readdata
+ {
+ type = "readdata";
+ width = "32";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT jtag_debug_module_reset
+ {
+ type = "reset";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT jtag_debug_module_resetrequest
+ {
+ type = "resetrequest";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT jtag_debug_module_select
+ {
+ type = "chipselect";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT jtag_debug_module_write
+ {
+ type = "write";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT jtag_debug_module_writedata
+ {
+ type = "writedata";
+ width = "32";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT reset_n
+ {
+ Is_Enabled = "1";
+ direction = "input";
+ type = "reset_n";
+ width = "1";
+ }
+ }
+ }
+ MASTER data_master
+ {
+ SYSTEM_BUILDER_INFO
+ {
+ Has_IRQ = "1";
+ Irq_Scheme = "individual_requests";
+ Bus_Type = "avalon";
+ Is_Asynchronous = "0";
+ DBS_Big_Endian = "0";
+ Adapts_To = "";
+ Do_Stream_Reads = "0";
+ Do_Stream_Writes = "0";
+ Max_Address_Width = "32";
+ Data_Width = "32";
+ Address_Width = "25";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "1";
+ Register_Outgoing_Signals = "0";
+ Interleave_Bursts = "0";
+ Linewrap_Bursts = "0";
+ Burst_On_Burst_Boundaries_Only = "";
+ Always_Burst_Max_Burst = "0";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ Is_Data_Master = "1";
+ Address_Group = "0";
+ Is_Readable = "1";
+ Is_Writeable = "1";
+ Interrupt_Range = "0-31";
+ }
+ PORT_WIRING
+ {
+ PORT d_irq
+ {
+ type = "irq";
+ width = "32";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT d_address
+ {
+ type = "address";
+ width = "25";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT d_byteenable
+ {
+ type = "byteenable";
+ width = "4";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT d_read
+ {
+ type = "read";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT d_readdata
+ {
+ type = "readdata";
+ width = "32";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT d_readdatavalid
+ {
+ type = "readdatavalid";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "0";
+ }
+ PORT d_waitrequest
+ {
+ type = "waitrequest";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT d_write
+ {
+ type = "write";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT d_writedata
+ {
+ type = "writedata";
+ width = "32";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT jtag_debug_module_debugaccess_to_roms
+ {
+ type = "debugaccess";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ }
+ MEMORY_MAP
+ {
+ Entry cpu_0/jtag_debug_module
+ {
+ address = "0x00901800";
+ span = "0x00000800";
+ is_bridge = "0";
+ }
+ Entry onchip_memory/s1
+ {
+ address = "0x00904000";
+ span = "0x00002000";
+ is_bridge = "0";
+ }
+ Entry jtag_uart_0/avalon_jtag_slave
+ {
+ address = "0x009000d0";
+ span = "0x00000008";
+ is_bridge = "0";
+ }
+ Entry sdram/s1
+ {
+ address = "0x01000000";
+ span = "0x01000000";
+ is_bridge = "0";
+ }
+ Entry sysid/control_slave
+ {
+ address = "0x009000d8";
+ span = "0x00000008";
+ is_bridge = "0";
+ }
+ Entry LED_Pio/s1
+ {
+ address = "0x00900080";
+ span = "0x00000010";
+ is_bridge = "0";
+ }
+ Entry SG_Pio/s1
+ {
+ address = "0x00900090";
+ span = "0x00000010";
+ is_bridge = "0";
+ }
+ Entry IO_Pio/s1
+ {
+ address = "0x009000a0";
+ span = "0x00000010";
+ is_bridge = "0";
+ }
+ Entry Button_Pio/s1
+ {
+ address = "0x009000b0";
+ span = "0x00000010";
+ is_bridge = "0";
+ }
+ Entry uart/s1
+ {
+ address = "0x00900040";
+ span = "0x00000020";
+ is_bridge = "0";
+ }
+ Entry LM74_Pio/s1
+ {
+ address = "0x009000c0";
+ span = "0x00000010";
+ is_bridge = "0";
+ }
+ Entry epcs_controller/epcs_control_port
+ {
+ address = "0x00906000";
+ span = "0x00000800";
+ is_bridge = "0";
+ }
+ Entry cfi_flash/s1
+ {
+ address = "0x00000000";
+ span = "0x00800000";
+ is_bridge = "0";
+ }
+ Entry DBC3C40_SRAM_inst/avalon_tristate_slave
+ {
+ address = "0x00800000";
+ span = "0x00100000";
+ is_bridge = "0";
+ }
+ Entry sys_clk/s1
+ {
+ address = "0x00900060";
+ span = "0x00000020";
+ is_bridge = "0";
+ }
+ Entry nios_vga_inst/vga_regs
+ {
+ address = "0x00900000";
+ span = "0x00000040";
+ is_bridge = "0";
+ }
+ }
+ }
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ cache_has_dcache = "0";
+ cache_dcache_size = "0";
+ cache_dcache_line_size = "0";
+ cache_dcache_bursts = "0";
+ cache_dcache_ram_block_type = "AUTO";
+ num_tightly_coupled_data_masters = "0";
+ gui_num_tightly_coupled_data_masters = "0";
+ gui_include_tightly_coupled_data_masters = "0";
+ gui_omit_avalon_data_master = "0";
+ cache_has_icache = "1";
+ cache_icache_size = "16384";
+ cache_icache_line_size = "32";
+ cache_icache_ram_block_type = "AUTO";
+ cache_icache_bursts = "0";
+ num_tightly_coupled_instruction_masters = "0";
+ gui_num_tightly_coupled_instruction_masters = "0";
+ gui_include_tightly_coupled_instruction_masters = "0";
+ debug_level = "3";
+ include_oci = "1";
+ oci_sbi_enabled = "1";
+ oci_num_xbrk = "2";
+ oci_num_dbrk = "2";
+ oci_dbrk_trace = "0";
+ oci_dbrk_pairs = "1";
+ oci_onchip_trace = "0";
+ oci_offchip_trace = "0";
+ oci_data_trace = "0";
+ include_third_party_debug_port = "0";
+ oci_trace_addr_width = "7";
+ oci_trigger_arming = "1";
+ oci_debugreq_signals = "0";
+ oci_embedded_pll = "0";
+ oci_num_pm = "0";
+ oci_pm_width = "32";
+ performance_counters_present = "0";
+ performance_counters_width = "32";
+ always_encrypt = "1";
+ debug_simgen = "0";
+ activate_model_checker = "0";
+ activate_test_end_checker = "0";
+ activate_trace = "1";
+ activate_monitors = "1";
+ clear_x_bits_ld_non_bypass = "1";
+ bit_31_bypass_dcache = "1";
+ hdl_sim_caches_cleared = "1";
+ hbreak_test = "0";
+ allow_full_address_range = "0";
+ extra_exc_info = "0";
+ branch_prediction_type = "Static";
+ bht_ptr_sz = "8";
+ bht_index_pc_only = "0";
+ gui_branch_prediction_type = "Static";
+ full_waveform_signals = "0";
+ export_pcb = "0";
+ avalon_debug_port_present = "0";
+ illegal_instructions_trap = "0";
+ illegal_memory_access_detection = "0";
+ illegal_mem_exc = "0";
+ slave_access_error_exc = "0";
+ division_error_exc = "0";
+ advanced_exc = "0";
+ gui_mmu_present = "0";
+ mmu_present = "0";
+ process_id_num_bits = "8";
+ tlb_ptr_sz = "7";
+ tlb_num_ways = "16";
+ udtlb_num_entries = "6";
+ uitlb_num_entries = "4";
+ fast_tlb_miss_exc_slave = "";
+ fast_tlb_miss_exc_offset = "0x00000000";
+ mpu_present = "0";
+ mpu_num_data_regions = "8";
+ mpu_num_inst_regions = "8";
+ mpu_min_data_region_size_log2 = "12";
+ mpu_min_inst_region_size_log2 = "12";
+ mpu_use_limit = "0";
+ hardware_divide_present = "0";
+ gui_hardware_divide_setting = "0";
+ hardware_multiply_present = "1";
+ hardware_multiply_impl = "embedded_mul";
+ shift_rot_impl = "fast_le_shift";
+ gui_hardware_multiply_setting = "embedded_mul_fast_le_shift";
+ reset_slave = "cfi_flash/s1";
+ break_slave = "cpu_0/jtag_debug_module";
+ exc_slave = "sdram/s1";
+ reset_offset = "0x00000000";
+ break_offset = "0x00000020";
+ exc_offset = "0x00000020";
+ cpu_reset = "0";
+ CPU_Implementation = "small";
+ cpu_selection = "s";
+ device_family_id = "CYCLONEIII";
+ address_stall_present = "1";
+ dsp_block_supports_shift = "0";
+ mrams_present = "0";
+ do_generate = "1";
+ cpuid_value = "0";
+ cpuid_sz = "1";
+ dont_overwrite_cpuid = "1";
+ allow_legacy_sdk = "1";
+ legacy_sdk_support = "1";
+ inst_addr_width = "25";
+ data_addr_width = "25";
+ asp_debug = "0";
+ asp_core_debug = "0";
+ CPU_Architecture = "nios2";
+ cache_icache_burst_type = "none";
+ include_debug = "0";
+ include_trace = "0";
+ hardware_multiply_uses_les = "0";
+ hardware_multiply_omits_msw = "1";
+ big_endian = "0";
+ break_slave_override = "";
+ break_offset_override = "0x20";
+ altera_show_unreleased_features = "0";
+ altera_show_unpublished_features = "0";
+ altera_internal_test = "0";
+ alt_log_port_base = "";
+ alt_log_port_type = "";
+ gui_illegal_instructions_trap = "0";
+ atomic_mem_present = "0";
+ nmi_present = "0";
+ fast_intr_present = "0";
+ num_shadow_regs = "0";
+ gui_illegal_memory_access_detection = "0";
+ cache_omit_dcache = "0";
+ cache_omit_icache = "0";
+ omit_instruction_master = "0";
+ omit_data_master = "0";
+ ras_ptr_sz = "4";
+ jtb_ptr_sz = "5";
+ ibuf_ptr_sz = "4";
+ always_bypass_dcache = "0";
+ iss_trace_on = "0";
+ iss_trace_warning = "1";
+ iss_trace_info = "1";
+ iss_trace_disassembly = "0";
+ iss_trace_registers = "0";
+ iss_trace_instr_count = "0";
+ iss_software_debug = "0";
+ iss_software_debug_port = "9996";
+ iss_memory_dump_start = "";
+ iss_memory_dump_end = "";
+ Boot_Copier = "boot_loader_cfi.srec";
+ Boot_Copier_EPCS = "boot_loader_epcs.srec";
+ Boot_Copier_EPCS_SII_SIII_CIII = "boot_loader_epcs_sii_siii_ciii.srec";
+ Boot_Copier_BE = "boot_loader_cfi_be.srec";
+ Boot_Copier_EPCS_BE = "boot_loader_epcs_be.srec";
+ Boot_Copier_EPCS_SII_SIII_CIII_BE = "boot_loader_epcs_sii_siii_ciii_be.srec";
+ CONSTANTS
+ {
+ CONSTANT __nios_catch_irqs__
+ {
+ value = "1";
+ comment = "Include panic handler for all irqs (needs uart)";
+ }
+ CONSTANT __nios_use_constructors__
+ {
+ value = "1";
+ comment = "Call c++ static constructors";
+ }
+ CONSTANT __nios_use_small_printf__
+ {
+ value = "1";
+ comment = "Smaller non-ANSI printf, with no floating point";
+ }
+ CONSTANT nasys_has_icache
+ {
+ value = "1";
+ comment = "True if instruction cache present";
+ }
+ CONSTANT nasys_icache_size
+ {
+ value = "16384";
+ comment = "Size in bytes of instruction cache";
+ }
+ CONSTANT nasys_icache_line_size
+ {
+ value = "32";
+ comment = "Size in bytes of each icache line";
+ }
+ CONSTANT nasys_icache_line_size_log2
+ {
+ value = "5";
+ comment = "Log2 size in bytes of each icache line";
+ }
+ CONSTANT nasys_has_dcache
+ {
+ value = "0";
+ comment = "True if instruction cache present";
+ }
+ CONSTANT nasys_dcache_size
+ {
+ value = "0";
+ comment = "Size in bytes of data cache";
+ }
+ CONSTANT nasys_dcache_line_size
+ {
+ value = "0";
+ comment = "Size in bytes of each dcache line";
+ }
+ CONSTANT nasys_dcache_line_size_log2
+ {
+ value = "-Infinity";
+ comment = "Log2 size in bytes of each dcache line";
+ }
+ }
+ license_status = "encrypted";
+ mainmem_slave = "DBC3C40_SRAM_inst/avalon_tristate_slave";
+ datamem_slave = "DBC3C40_SRAM_inst/avalon_tristate_slave";
+ maincomm_slave = "uart/s1";
+ germs_monitor_id = "";
+ }
+ class = "altera_nios2";
+ class_version = "7.08";
+ SYSTEM_BUILDER_INFO
+ {
+ Is_Enabled = "1";
+ Clock_Source = "clk";
+ Has_Clock = "1";
+ Parameters_Signature = "";
+ Is_CPU = "1";
+ Instantiate_In_System_Module = "1";
+ Required_Device_Family = "STRATIX,STRATIXGX,STRATIXII,STRATIXIIGX,STRATIXIIGXLITE,STRATIXIII,STRATIXIV,CYCLONE,CYCLONEII,CYCLONEIII";
+ Default_Module_Name = "cpu";
+ Top_Level_Ports_Are_Enumerated = "1";
+ View
+ {
+ Settings_Summary = "Nios II/s
+ <br> 16-Kbyte Instruction Cache
+
+ <br> JTAG Debug Module
+ ";
+ MESSAGES
+ {
+ }
+ }
+ }
+ iss_model_name = "altera_nios2";
+ HDL_INFO
+ {
+ PLI_Files = "";
+ Precompiled_Simulation_Library_Files = "";
+ Simulation_HDL_Files = "";
+ Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/cpu_0_test_bench.vhd, __PROJECT_DIRECTORY__/cpu_0_mult_cell.vhd, __PROJECT_DIRECTORY__/cpu_0_jtag_debug_module_tck.vhd, __PROJECT_DIRECTORY__/cpu_0_jtag_debug_module_sysclk.vhd, __PROJECT_DIRECTORY__/cpu_0_jtag_debug_module_wrapper.vhd, __PROJECT_DIRECTORY__/cpu_0.vhd";
+ Synthesis_Only_Files = "";
+ }
+ MASTER tightly_coupled_instruction_master_0
+ {
+ PORT_WIRING
+ {
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Register_Incoming_Signals = "0";
+ Bus_Type = "avalon";
+ Data_Width = "32";
+ Max_Address_Width = "31";
+ Address_Width = "8";
+ Is_Instruction_Master = "1";
+ Has_IRQ = "0";
+ Is_Enabled = "0";
+ Is_Big_Endian = "0";
+ Connection_Limit = "1";
+ Is_Channel = "1";
+ }
+ }
+ MASTER tightly_coupled_instruction_master_1
+ {
+ PORT_WIRING
+ {
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Register_Incoming_Signals = "0";
+ Bus_Type = "avalon";
+ Data_Width = "32";
+ Max_Address_Width = "31";
+ Address_Width = "8";
+ Address_Group = "0";
+ Is_Instruction_Master = "1";
+ Is_Readable = "1";
+ Is_Writeable = "0";
+ Has_IRQ = "0";
+ Is_Enabled = "0";
+ Is_Big_Endian = "0";
+ Connection_Limit = "1";
+ Is_Channel = "1";
+ }
+ }
+ MASTER tightly_coupled_instruction_master_2
+ {
+ PORT_WIRING
+ {
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Register_Incoming_Signals = "0";
+ Bus_Type = "avalon";
+ Data_Width = "32";
+ Max_Address_Width = "31";
+ Address_Width = "8";
+ Address_Group = "0";
+ Is_Instruction_Master = "1";
+ Is_Readable = "1";
+ Is_Writeable = "0";
+ Has_IRQ = "0";
+ Is_Enabled = "0";
+ Is_Big_Endian = "0";
+ Connection_Limit = "1";
+ Is_Channel = "1";
+ }
+ }
+ MASTER tightly_coupled_instruction_master_3
+ {
+ PORT_WIRING
+ {
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Register_Incoming_Signals = "0";
+ Bus_Type = "avalon";
+ Data_Width = "32";
+ Max_Address_Width = "31";
+ Address_Width = "8";
+ Address_Group = "0";
+ Is_Instruction_Master = "1";
+ Is_Readable = "1";
+ Is_Writeable = "0";
+ Has_IRQ = "0";
+ Is_Enabled = "0";
+ Is_Big_Endian = "0";
+ Connection_Limit = "1";
+ Is_Channel = "1";
+ }
+ }
+ MASTER data_master2
+ {
+ PORT_WIRING
+ {
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Register_Incoming_Signals = "1";
+ Bus_Type = "avalon";
+ Data_Width = "32";
+ Max_Address_Width = "31";
+ Address_Width = "8";
+ Address_Group = "0";
+ Is_Data_Master = "1";
+ Is_Readable = "1";
+ Is_Writeable = "1";
+ Has_IRQ = "0";
+ Is_Enabled = "0";
+ Is_Big_Endian = "0";
+ }
+ }
+ MASTER tightly_coupled_data_master_0
+ {
+ PORT_WIRING
+ {
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Register_Incoming_Signals = "0";
+ Bus_Type = "avalon";
+ Data_Width = "32";
+ Max_Address_Width = "31";
+ Address_Width = "8";
+ Address_Group = "0";
+ Is_Data_Master = "1";
+ Is_Readable = "1";
+ Is_Writeable = "1";
+ Has_IRQ = "0";
+ Is_Enabled = "0";
+ Is_Big_Endian = "0";
+ Connection_Limit = "1";
+ Is_Channel = "1";
+ }
+ }
+ MASTER tightly_coupled_data_master_1
+ {
+ PORT_WIRING
+ {
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Register_Incoming_Signals = "0";
+ Bus_Type = "avalon";
+ Data_Width = "32";
+ Max_Address_Width = "31";
+ Address_Width = "8";
+ Address_Group = "0";
+ Is_Data_Master = "1";
+ Is_Readable = "1";
+ Is_Writeable = "1";
+ Has_IRQ = "0";
+ Is_Enabled = "0";
+ Is_Big_Endian = "0";
+ Connection_Limit = "1";
+ Is_Channel = "1";
+ }
+ }
+ MASTER tightly_coupled_data_master_2
+ {
+ PORT_WIRING
+ {
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Register_Incoming_Signals = "0";
+ Bus_Type = "avalon";
+ Data_Width = "32";
+ Max_Address_Width = "31";
+ Address_Width = "8";
+ Address_Group = "0";
+ Is_Data_Master = "1";
+ Is_Readable = "1";
+ Is_Writeable = "1";
+ Has_IRQ = "0";
+ Is_Enabled = "0";
+ Is_Big_Endian = "0";
+ Connection_Limit = "1";
+ Is_Channel = "1";
+ }
+ }
+ MASTER tightly_coupled_data_master_3
+ {
+ PORT_WIRING
+ {
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Register_Incoming_Signals = "0";
+ Bus_Type = "avalon";
+ Data_Width = "32";
+ Max_Address_Width = "31";
+ Address_Width = "8";
+ Address_Group = "0";
+ Is_Data_Master = "1";
+ Is_Readable = "1";
+ Is_Writeable = "1";
+ Has_IRQ = "0";
+ Is_Enabled = "0";
+ Is_Big_Endian = "0";
+ Connection_Limit = "1";
+ Is_Channel = "1";
+ }
+ }
+ PORT_WIRING
+ {
+ PORT jtag_debug_trigout
+ {
+ width = "1";
+ direction = "output";
+ Is_Enabled = "0";
+ }
+ PORT jtag_debug_offchip_trace_clk
+ {
+ width = "1";
+ direction = "output";
+ Is_Enabled = "0";
+ }
+ PORT jtag_debug_offchip_trace_data
+ {
+ width = "18";
+ direction = "output";
+ Is_Enabled = "0";
+ }
+ PORT clkx2
+ {
+ width = "1";
+ direction = "input";
+ Is_Enabled = "0";
+ visible = "0";
+ }
+ }
+ SIMULATION
+ {
+ DISPLAY
+ {
+ SIGNAL aaa
+ {
+ format = "Logic";
+ name = "i_readdata";
+ radix = "hexadecimal";
+ }
+ SIGNAL aab
+ {
+ format = "Logic";
+ name = "i_readdatavalid";
+ radix = "hexadecimal";
+ }
+ SIGNAL aac
+ {
+ format = "Logic";
+ name = "i_waitrequest";
+ radix = "hexadecimal";
+ }
+ SIGNAL aad
+ {
+ format = "Logic";
+ name = "i_address";
+ radix = "hexadecimal";
+ }
+ SIGNAL aae
+ {
+ format = "Logic";
+ name = "i_read";
+ radix = "hexadecimal";
+ }
+ SIGNAL aaf
+ {
+ format = "Logic";
+ name = "clk";
+ radix = "hexadecimal";
+ }
+ SIGNAL aag
+ {
+ format = "Logic";
+ name = "reset_n";
+ radix = "hexadecimal";
+ }
+ SIGNAL aah
+ {
+ format = "Logic";
+ name = "d_readdata";
+ radix = "hexadecimal";
+ }
+ SIGNAL aai
+ {
+ format = "Logic";
+ name = "d_waitrequest";
+ radix = "hexadecimal";
+ }
+ SIGNAL aaj
+ {
+ format = "Logic";
+ name = "d_irq";
+ radix = "hexadecimal";
+ }
+ SIGNAL aak
+ {
+ format = "Logic";
+ name = "d_address";
+ radix = "hexadecimal";
+ }
+ SIGNAL aal
+ {
+ format = "Logic";
+ name = "d_byteenable";
+ radix = "hexadecimal";
+ }
+ SIGNAL aam
+ {
+ format = "Logic";
+ name = "d_read";
+ radix = "hexadecimal";
+ }
+ SIGNAL aan
+ {
+ format = "Logic";
+ name = "d_write";
+ radix = "hexadecimal";
+ }
+ SIGNAL aao
+ {
+ format = "Logic";
+ name = "d_writedata";
+ radix = "hexadecimal";
+ }
+ SIGNAL aap
+ {
+ format = "Divider";
+ name = "base pipeline";
+ radix = "";
+ }
+ SIGNAL aaq
+ {
+ format = "Logic";
+ name = "clk";
+ radix = "hexadecimal";
+ }
+ SIGNAL aar
+ {
+ format = "Logic";
+ name = "reset_n";
+ radix = "hexadecimal";
+ }
+ SIGNAL aas
+ {
+ format = "Logic";
+ name = "M_stall";
+ radix = "hexadecimal";
+ }
+ SIGNAL aat
+ {
+ format = "Logic";
+ name = "F_pcb_nxt";
+ radix = "hexadecimal";
+ }
+ SIGNAL aau
+ {
+ format = "Logic";
+ name = "F_pcb";
+ radix = "hexadecimal";
+ }
+ SIGNAL aav
+ {
+ format = "Logic";
+ name = "D_pcb";
+ radix = "hexadecimal";
+ }
+ SIGNAL aaw
+ {
+ format = "Logic";
+ name = "E_pcb";
+ radix = "hexadecimal";
+ }
+ SIGNAL aax
+ {
+ format = "Logic";
+ name = "M_pcb";
+ radix = "hexadecimal";
+ }
+ SIGNAL aay
+ {
+ format = "Logic";
+ name = "W_pcb";
+ radix = "hexadecimal";
+ }
+ SIGNAL aaz
+ {
+ format = "Logic";
+ name = "F_vinst";
+ radix = "ascii";
+ }
+ SIGNAL aba
+ {
+ format = "Logic";
+ name = "D_vinst";
+ radix = "ascii";
+ }
+ SIGNAL abb
+ {
+ format = "Logic";
+ name = "E_vinst";
+ radix = "ascii";
+ }
+ SIGNAL abc
+ {
+ format = "Logic";
+ name = "M_vinst";
+ radix = "ascii";
+ }
+ SIGNAL abd
+ {
+ format = "Logic";
+ name = "W_vinst";
+ radix = "ascii";
+ }
+ SIGNAL abe
+ {
+ format = "Logic";
+ name = "F_inst_ram_hit";
+ radix = "hexadecimal";
+ }
+ SIGNAL abf
+ {
+ format = "Logic";
+ name = "F_issue";
+ radix = "hexadecimal";
+ }
+ SIGNAL abg
+ {
+ format = "Logic";
+ name = "F_kill";
+ radix = "hexadecimal";
+ }
+ SIGNAL abh
+ {
+ format = "Logic";
+ name = "D_kill";
+ radix = "hexadecimal";
+ }
+ SIGNAL abi
+ {
+ format = "Logic";
+ name = "D_refetch";
+ radix = "hexadecimal";
+ }
+ SIGNAL abj
+ {
+ format = "Logic";
+ name = "D_issue";
+ radix = "hexadecimal";
+ }
+ SIGNAL abk
+ {
+ format = "Logic";
+ name = "D_valid";
+ radix = "hexadecimal";
+ }
+ SIGNAL abl
+ {
+ format = "Logic";
+ name = "E_valid";
+ radix = "hexadecimal";
+ }
+ SIGNAL abm
+ {
+ format = "Logic";
+ name = "M_valid";
+ radix = "hexadecimal";
+ }
+ SIGNAL abn
+ {
+ format = "Logic";
+ name = "W_valid";
+ radix = "hexadecimal";
+ }
+ SIGNAL abo
+ {
+ format = "Logic";
+ name = "W_wr_dst_reg";
+ radix = "hexadecimal";
+ }
+ SIGNAL abp
+ {
+ format = "Logic";
+ name = "W_dst_regnum";
+ radix = "hexadecimal";
+ }
+ SIGNAL abq
+ {
+ format = "Logic";
+ name = "W_wr_data";
+ radix = "hexadecimal";
+ }
+ SIGNAL abr
+ {
+ format = "Logic";
+ name = "F_en";
+ radix = "hexadecimal";
+ }
+ SIGNAL abs
+ {
+ format = "Logic";
+ name = "D_en";
+ radix = "hexadecimal";
+ }
+ SIGNAL abt
+ {
+ format = "Logic";
+ name = "E_en";
+ radix = "hexadecimal";
+ }
+ SIGNAL abu
+ {
+ format = "Logic";
+ name = "M_en";
+ radix = "hexadecimal";
+ }
+ SIGNAL abv
+ {
+ format = "Logic";
+ name = "F_iw";
+ radix = "hexadecimal";
+ }
+ SIGNAL abw
+ {
+ format = "Logic";
+ name = "D_iw";
+ radix = "hexadecimal";
+ }
+ SIGNAL abx
+ {
+ format = "Logic";
+ name = "E_iw";
+ radix = "hexadecimal";
+ }
+ SIGNAL aby
+ {
+ format = "Logic";
+ name = "E_valid_prior_to_hbreak";
+ radix = "hexadecimal";
+ }
+ SIGNAL abz
+ {
+ format = "Logic";
+ name = "M_pipe_flush_nxt";
+ radix = "hexadecimal";
+ }
+ SIGNAL aca
+ {
+ format = "Logic";
+ name = "M_pipe_flush_baddr_nxt";
+ radix = "hexadecimal";
+ }
+ SIGNAL acb
+ {
+ format = "Logic";
+ name = "M_status_reg_pie";
+ radix = "hexadecimal";
+ }
+ SIGNAL acc
+ {
+ format = "Logic";
+ name = "M_ienable_reg";
+ radix = "hexadecimal";
+ }
+ SIGNAL acd
+ {
+ format = "Logic";
+ name = "intr_req";
+ radix = "hexadecimal";
+ }
+ }
+ }
+ }
+ MODULE onchip_memory
+ {
+ SLAVE s1
+ {
+ PORT_WIRING
+ {
+ PORT clk
+ {
+ type = "clk";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT reset_n
+ {
+ type = "reset_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "0";
+ }
+ PORT address
+ {
+ type = "address";
+ width = "11";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT chipselect
+ {
+ type = "chipselect";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT clken
+ {
+ type = "clken";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ default_value = "1'b1";
+ }
+ PORT read
+ {
+ type = "read";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "0";
+ }
+ PORT readdata
+ {
+ type = "readdata";
+ width = "32";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT write
+ {
+ type = "write";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT writedata
+ {
+ type = "writedata";
+ width = "32";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT debugaccess
+ {
+ type = "debugaccess";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "0";
+ }
+ PORT byteenable
+ {
+ type = "byteenable";
+ width = "4";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon";
+ Write_Wait_States = "0cycles";
+ Read_Wait_States = "0cycles";
+ Hold_Time = "0cycles";
+ Setup_Time = "0cycles";
+ Is_Printable_Device = "0";
+ Address_Alignment = "dynamic";
+ Well_Behaved_Waitrequest = "0";
+ Is_Nonvolatile_Storage = "0";
+ Address_Span = "8192";
+ Read_Latency = "1";
+ Is_Memory_Device = "1";
+ Maximum_Pending_Read_Transactions = "0";
+ Minimum_Uninterrupted_Run_Length = "1";
+ Accepts_Internal_Connections = "1";
+ Write_Latency = "0";
+ Is_Flash = "0";
+ Data_Width = "32";
+ Address_Width = "11";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "0";
+ Register_Outgoing_Signals = "0";
+ Interleave_Bursts = "0";
+ Linewrap_Bursts = "0";
+ Burst_On_Burst_Boundaries_Only = "0";
+ Always_Burst_Max_Burst = "0";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ MASTERED_BY cpu_0/instruction_master
+ {
+ priority = "1";
+ Offset_Address = "0x00904000";
+ }
+ MASTERED_BY cpu_0/data_master
+ {
+ priority = "1";
+ Offset_Address = "0x00904000";
+ }
+ Base_Address = "0x00904000";
+ Address_Group = "0";
+ Has_IRQ = "0";
+ Is_Channel = "1";
+ Is_Writable = "1";
+ IRQ_MASTER cpu_0/data_master
+ {
+ IRQ_Number = "NC";
+ }
+ }
+ }
+ iss_model_name = "altera_memory";
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ allow_mram_sim_contents_only_file = "0";
+ ram_block_type = "AUTO";
+ init_contents_file = "onchip_memory";
+ non_default_init_file_enabled = "0";
+ gui_ram_block_type = "Automatic";
+ Writeable = "1";
+ dual_port = "0";
+ Size_Value = "8192";
+ Size_Multiple = "1";
+ use_shallow_mem_blocks = "0";
+ init_mem_content = "1";
+ allow_in_system_memory_content_editor = "0";
+ instance_id = "NONE";
+ read_during_write_mode = "DONT_CARE";
+ ignore_auto_block_type_assignment = "1";
+ MAKE
+ {
+ TARGET delete_placeholder_warning
+ {
+ onchip_memory
+ {
+ Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
+ Is_Phony = "1";
+ Target_File = "do_delete_placeholder_warning";
+ }
+ }
+ TARGET hex
+ {
+ onchip_memory
+ {
+ Command1 = "@echo Post-processing to create $(notdir $@)";
+ Command2 = "elf2hex $(ELF) 0x00904000 0x905FFF --width=32 $(QUARTUS_PROJECT_DIR)/onchip_memory.hex --create-lanes=0 ";
+ Dependency = "$(ELF)";
+ Target_File = "$(QUARTUS_PROJECT_DIR)/onchip_memory.hex";
+ }
+ }
+ TARGET sim
+ {
+ onchip_memory
+ {
+ Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
+ Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
+ Command3 = "touch $(SIMDIR)/dummy_file";
+ Dependency = "$(ELF)";
+ Target_File = "$(SIMDIR)/dummy_file";
+ }
+ }
+ }
+ contents_info = "";
+ }
+ SIMULATION
+ {
+ DISPLAY
+ {
+ SIGNAL a
+ {
+ name = "chipselect";
+ conditional = "1";
+ }
+ SIGNAL c
+ {
+ name = "address";
+ radix = "hexadecimal";
+ }
+ SIGNAL d
+ {
+ name = "byteenable";
+ radix = "binary";
+ conditional = "1";
+ }
+ SIGNAL e
+ {
+ name = "readdata";
+ radix = "hexadecimal";
+ }
+ SIGNAL b
+ {
+ name = "write";
+ conditional = "1";
+ }
+ SIGNAL f
+ {
+ name = "writedata";
+ radix = "hexadecimal";
+ conditional = "1";
+ }
+ }
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Prohibited_Device_Family = "MERCURY, APEX20K, APEX20KE, APEX20KC, APEXII, ACEX1K, FLEX10KE, EXCALIBUR_ARM, MAXII";
+ Instantiate_In_System_Module = "1";
+ Is_Enabled = "1";
+ Default_Module_Name = "onchip_memory";
+ Top_Level_Ports_Are_Enumerated = "1";
+ Clock_Source = "clk";
+ Has_Clock = "1";
+ View
+ {
+ MESSAGES
+ {
+ }
+ }
+ }
+ class = "altera_avalon_onchip_memory2";
+ class_version = "7.08";
+ HDL_INFO
+ {
+ Precompiled_Simulation_Library_Files = "";
+ Simulation_HDL_Files = "";
+ Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/onchip_memory.vhd";
+ Synthesis_Only_Files = "";
+ }
+ SLAVE s2
+ {
+ PORT_WIRING
+ {
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon";
+ Is_Memory_Device = "1";
+ Address_Group = "0";
+ Address_Alignment = "dynamic";
+ Address_Width = "11";
+ Data_Width = "32";
+ Has_IRQ = "0";
+ Read_Wait_States = "0";
+ Write_Wait_States = "0";
+ Address_Span = "8192";
+ Read_Latency = "1";
+ Is_Channel = "1";
+ Is_Enabled = "0";
+ Is_Writable = "1";
+ }
+ }
+ PORT_WIRING
+ {
+ }
+ }
+ MODULE jtag_uart_0
+ {
+ SLAVE avalon_jtag_slave
+ {
+ PORT_WIRING
+ {
+ PORT clk
+ {
+ type = "clk";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT reset_n
+ {
+ type = "reset_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "0";
+ }
+ PORT av_irq
+ {
+ type = "irq";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT av_chipselect
+ {
+ type = "chipselect";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT av_address
+ {
+ type = "address";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT av_read_n
+ {
+ type = "read_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT av_readdata
+ {
+ type = "readdata";
+ width = "32";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT av_write_n
+ {
+ type = "write_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT av_writedata
+ {
+ type = "writedata";
+ width = "32";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT av_waitrequest
+ {
+ type = "waitrequest";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT dataavailable
+ {
+ type = "dataavailable";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT readyfordata
+ {
+ type = "readyfordata";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT rst_n
+ {
+ type = "reset_n";
+ direction = "input";
+ width = "1";
+ Is_Enabled = "1";
+ }
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Has_IRQ = "1";
+ Bus_Type = "avalon";
+ Read_Wait_States = "peripheral_controlled";
+ Write_Wait_States = "peripheral_controlled";
+ Hold_Time = "0cycles";
+ Setup_Time = "0cycles";
+ Is_Printable_Device = "1";
+ Address_Alignment = "native";
+ Well_Behaved_Waitrequest = "0";
+ Is_Nonvolatile_Storage = "0";
+ Read_Latency = "0";
+ Is_Memory_Device = "0";
+ Maximum_Pending_Read_Transactions = "0";
+ Minimum_Uninterrupted_Run_Length = "1";
+ Accepts_Internal_Connections = "1";
+ Write_Latency = "0";
+ Is_Flash = "0";
+ Data_Width = "32";
+ Address_Width = "1";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "0";
+ Register_Outgoing_Signals = "0";
+ Interleave_Bursts = "0";
+ Linewrap_Bursts = "0";
+ Burst_On_Burst_Boundaries_Only = "0";
+ Always_Burst_Max_Burst = "0";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ JTAG_Hub_Base_Id = "262254";
+ JTAG_Hub_Instance_Id = "0";
+ Connection_Limit = "1";
+ MASTERED_BY cpu_0/data_master
+ {
+ priority = "1";
+ Offset_Address = "0x009000d0";
+ }
+ IRQ_MASTER cpu_0/data_master
+ {
+ IRQ_Number = "1";
+ }
+ Base_Address = "0x009000d0";
+ Address_Group = "0";
+ }
+ }
+ class = "altera_avalon_jtag_uart";
+ class_version = "7.08";
+ iss_model_name = "altera_avalon_jtag_uart";
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ write_depth = "64";
+ read_depth = "64";
+ write_threshold = "8";
+ read_threshold = "8";
+ read_char_stream = "";
+ showascii = "1";
+ read_le = "0";
+ write_le = "0";
+ altera_show_unreleased_jtag_uart_features = "0";
+ }
+ SIMULATION
+ {
+ DISPLAY
+ {
+ SIGNAL av_chipselect
+ {
+ name = "av_chipselect";
+ }
+ SIGNAL av_address
+ {
+ name = "av_address";
+ radix = "hexadecimal";
+ }
+ SIGNAL av_read_n
+ {
+ name = "av_read_n";
+ }
+ SIGNAL av_readdata
+ {
+ name = "av_readdata";
+ radix = "hexadecimal";
+ }
+ SIGNAL av_write_n
+ {
+ name = "av_write_n";
+ }
+ SIGNAL av_writedata
+ {
+ name = "av_writedata";
+ radix = "hexadecimal";
+ }
+ SIGNAL av_waitrequest
+ {
+ name = "av_waitrequest";
+ }
+ SIGNAL dataavailable
+ {
+ name = "dataavailable";
+ }
+ SIGNAL readyfordata
+ {
+ name = "readyfordata";
+ }
+ SIGNAL av_irq
+ {
+ name = "av_irq";
+ }
+ }
+ INTERACTIVE_IN drive
+ {
+ enable = "0";
+ file = "_input_data_stream.dat";
+ mutex = "_input_data_mutex.dat";
+ log = "_in.log";
+ rate = "100";
+ signals = "temp,list";
+ exe = "nios2-terminal";
+ }
+ INTERACTIVE_OUT log
+ {
+ enable = "1";
+ exe = "perl -- atail-f.pl";
+ file = "_output_stream.dat";
+ radix = "ascii";
+ signals = "temp,list";
+ }
+ Fix_Me_Up = "";
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Is_Enabled = "1";
+ Clock_Source = "clk";
+ Has_Clock = "1";
+ Instantiate_In_System_Module = "1";
+ Iss_Launch_Telnet = "0";
+ Top_Level_Ports_Are_Enumerated = "1";
+ View
+ {
+ MESSAGES
+ {
+ }
+ Settings_Summary = "<br>Write Depth: 64; Write IRQ Threshold: 8
+ <br>Read Depth: 64; Read IRQ Threshold: 8";
+ }
+ }
+ HDL_INFO
+ {
+ Precompiled_Simulation_Library_Files = "";
+ Simulation_HDL_Files = "";
+ Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/jtag_uart_0.vhd";
+ Synthesis_Only_Files = "";
+ }
+ PORT_WIRING
+ {
+ }
+ }
+ MODULE sdram
+ {
+ SLAVE s1
+ {
+ PORT_WIRING
+ {
+ PORT clk
+ {
+ type = "clk";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT reset_n
+ {
+ type = "reset_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT az_addr
+ {
+ type = "address";
+ width = "22";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT az_be_n
+ {
+ type = "byteenable_n";
+ width = "4";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT az_cs
+ {
+ type = "chipselect";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT az_data
+ {
+ type = "writedata";
+ width = "32";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT az_rd_n
+ {
+ type = "read_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT az_wr_n
+ {
+ type = "write_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT za_data
+ {
+ type = "readdata";
+ width = "32";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT za_valid
+ {
+ type = "readdatavalid";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT za_waitrequest
+ {
+ type = "waitrequest";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT zs_addr
+ {
+ direction = "output";
+ width = "12";
+ Is_Enabled = "1";
+ }
+ PORT zs_ba
+ {
+ direction = "output";
+ width = "2";
+ Is_Enabled = "1";
+ }
+ PORT zs_cas_n
+ {
+ direction = "output";
+ width = "1";
+ Is_Enabled = "1";
+ }
+ PORT zs_cke
+ {
+ direction = "output";
+ width = "1";
+ Is_Enabled = "1";
+ }
+ PORT zs_cs_n
+ {
+ direction = "output";
+ width = "1";
+ Is_Enabled = "1";
+ }
+ PORT zs_dq
+ {
+ direction = "inout";
+ width = "32";
+ Is_Enabled = "1";
+ }
+ PORT zs_dqm
+ {
+ direction = "output";
+ width = "4";
+ Is_Enabled = "1";
+ }
+ PORT zs_ras_n
+ {
+ direction = "output";
+ width = "1";
+ Is_Enabled = "1";
+ }
+ PORT zs_we_n
+ {
+ direction = "output";
+ width = "1";
+ Is_Enabled = "1";
+ }
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon";
+ Read_Wait_States = "peripheral_controlled";
+ Write_Wait_States = "peripheral_controlled";
+ Hold_Time = "0cycles";
+ Setup_Time = "0cycles";
+ Is_Printable_Device = "0";
+ Address_Alignment = "dynamic";
+ Well_Behaved_Waitrequest = "0";
+ Is_Nonvolatile_Storage = "0";
+ Address_Span = "16777216";
+ Read_Latency = "0";
+ Is_Memory_Device = "1";
+ Maximum_Pending_Read_Transactions = "6";
+ Minimum_Uninterrupted_Run_Length = "1";
+ Accepts_Internal_Connections = "1";
+ Write_Latency = "0";
+ Is_Flash = "0";
+ Data_Width = "32";
+ Address_Width = "22";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "0";
+ Register_Outgoing_Signals = "0";
+ Interleave_Bursts = "0";
+ Linewrap_Bursts = "0";
+ Burst_On_Burst_Boundaries_Only = "0";
+ Always_Burst_Max_Burst = "0";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ MASTERED_BY cpu_0/instruction_master
+ {
+ priority = "1";
+ Offset_Address = "0x01000000";
+ }
+ MASTERED_BY cpu_0/data_master
+ {
+ priority = "1";
+ Offset_Address = "0x01000000";
+ }
+ Base_Address = "0x01000000";
+ Has_IRQ = "0";
+ Simulation_Num_Lanes = "1";
+ Address_Group = "0";
+ IRQ_MASTER cpu_0/data_master
+ {
+ IRQ_Number = "NC";
+ }
+ }
+ }
+ PORT_WIRING
+ {
+ PORT zs_addr
+ {
+ type = "export";
+ width = "12";
+ direction = "output";
+ Is_Enabled = "0";
+ }
+ PORT zs_ba
+ {
+ type = "export";
+ width = "2";
+ direction = "output";
+ Is_Enabled = "0";
+ }
+ PORT zs_cas_n
+ {
+ type = "export";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "0";
+ }
+ PORT zs_cke
+ {
+ type = "export";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "0";
+ }
+ PORT zs_cs_n
+ {
+ type = "export";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "0";
+ }
+ PORT zs_dq
+ {
+ type = "export";
+ width = "32";
+ direction = "output";
+ Is_Enabled = "0";
+ }
+ PORT zs_dqm
+ {
+ type = "export";
+ width = "4";
+ direction = "output";
+ Is_Enabled = "0";
+ }
+ PORT zs_ras_n
+ {
+ type = "export";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "0";
+ }
+ PORT zs_we_n
+ {
+ type = "export";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "0";
+ }
+ }
+ iss_model_name = "altera_memory";
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ register_data_in = "1";
+ sim_model_base = "0";
+ sdram_data_width = "32";
+ sdram_addr_width = "12";
+ sdram_row_width = "12";
+ sdram_col_width = "8";
+ sdram_num_chipselects = "1";
+ sdram_num_banks = "4";
+ refresh_period = "15.625";
+ powerup_delay = "100.0";
+ cas_latency = "2";
+ t_rfc = "70.0";
+ t_rp = "15.0";
+ t_mrd = "3";
+ t_rcd = "15.0";
+ t_ac = "6.0";
+ t_wr = "14.0";
+ init_refresh_commands = "2";
+ init_nop_delay = "0.0";
+ shared_data = "0";
+ sdram_bank_width = "2";
+ tristate_bridge_slave = "";
+ starvation_indicator = "0";
+ is_initialized = "1";
+ }
+ SIMULATION
+ {
+ DISPLAY
+ {
+ SIGNAL a
+ {
+ name = "az_addr";
+ radix = "hexadecimal";
+ }
+ SIGNAL b
+ {
+ name = "az_be_n";
+ radix = "hexadecimal";
+ }
+ SIGNAL c
+ {
+ name = "az_cs";
+ }
+ SIGNAL d
+ {
+ name = "az_data";
+ radix = "hexadecimal";
+ }
+ SIGNAL e
+ {
+ name = "az_rd_n";
+ }
+ SIGNAL f
+ {
+ name = "az_wr_n";
+ }
+ SIGNAL h
+ {
+ name = "za_data";
+ radix = "hexadecimal";
+ }
+ SIGNAL i
+ {
+ name = "za_valid";
+ }
+ SIGNAL j
+ {
+ name = "za_waitrequest";
+ }
+ SIGNAL l
+ {
+ name = "CODE";
+ radix = "ascii";
+ }
+ SIGNAL g
+ {
+ name = "clk";
+ }
+ SIGNAL k
+ {
+ name = "za_cannotrefresh";
+ suppress = "1";
+ }
+ SIGNAL m
+ {
+ name = "zs_addr";
+ radix = "hexadecimal";
+ suppress = "0";
+ }
+ SIGNAL n
+ {
+ name = "zs_ba";
+ radix = "hexadecimal";
+ suppress = "0";
+ }
+ SIGNAL o
+ {
+ name = "zs_cs_n";
+ radix = "hexadecimal";
+ suppress = "0";
+ }
+ SIGNAL p
+ {
+ name = "zs_ras_n";
+ suppress = "0";
+ }
+ SIGNAL q
+ {
+ name = "zs_cas_n";
+ suppress = "0";
+ }
+ SIGNAL r
+ {
+ name = "zs_we_n";
+ suppress = "0";
+ }
+ SIGNAL s
+ {
+ name = "zs_dq";
+ radix = "hexadecimal";
+ suppress = "0";
+ }
+ SIGNAL t
+ {
+ name = "zs_dqm";
+ radix = "hexadecimal";
+ suppress = "0";
+ }
+ SIGNAL u
+ {
+ name = "zt_addr";
+ radix = "hexadecimal";
+ suppress = "1";
+ }
+ SIGNAL v
+ {
+ name = "zt_ba";
+ radix = "hexadecimal";
+ suppress = "1";
+ }
+ SIGNAL w
+ {
+ name = "zt_oe";
+ suppress = "1";
+ }
+ SIGNAL x
+ {
+ name = "zt_cke";
+ suppress = "1";
+ }
+ SIGNAL y
+ {
+ name = "zt_chipselect";
+ suppress = "1";
+ }
+ SIGNAL z0
+ {
+ name = "zt_lock_n";
+ suppress = "1";
+ }
+ SIGNAL z1
+ {
+ name = "zt_ras_n";
+ suppress = "1";
+ }
+ SIGNAL z2
+ {
+ name = "zt_cas_n";
+ suppress = "1";
+ }
+ SIGNAL z3
+ {
+ name = "zt_we_n";
+ suppress = "1";
+ }
+ SIGNAL z4
+ {
+ name = "zt_cs_n";
+ radix = "hexadecimal";
+ suppress = "1";
+ }
+ SIGNAL z5
+ {
+ name = "zt_dqm";
+ radix = "hexadecimal";
+ suppress = "1";
+ }
+ SIGNAL z6
+ {
+ name = "zt_data";
+ radix = "hexadecimal";
+ suppress = "1";
+ }
+ SIGNAL z7
+ {
+ name = "tz_data";
+ radix = "hexadecimal";
+ suppress = "1";
+ }
+ SIGNAL z8
+ {
+ name = "tz_waitrequest";
+ suppress = "1";
+ }
+ }
+ Fix_Me_Up = "";
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Instantiate_In_System_Module = "1";
+ Is_Enabled = "1";
+ Default_Module_Name = "sdram";
+ Top_Level_Ports_Are_Enumerated = "1";
+ Clock_Source = "clk";
+ Has_Clock = "1";
+ Disable_Simulation_Port_Wiring = "0";
+ View
+ {
+ MESSAGES
+ {
+ }
+ Settings_Summary = "4194304 x 32<br>
+ Memory size: 16 MBytes<br>
+ 128 MBits
+ ";
+ }
+ }
+ class = "altera_avalon_new_sdram_controller";
+ class_version = "7.08";
+ HDL_INFO
+ {
+ Precompiled_Simulation_Library_Files = "";
+ Simulation_HDL_Files = "";
+ Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sdram.vhd";
+ Synthesis_Only_Files = "";
+ }
+ }
+ MODULE sysid
+ {
+ SLAVE control_slave
+ {
+ PORT_WIRING
+ {
+ PORT clock
+ {
+ type = "clk";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "0";
+ }
+ PORT reset_n
+ {
+ type = "reset_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "0";
+ }
+ PORT address
+ {
+ type = "address";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT readdata
+ {
+ type = "readdata";
+ width = "32";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon";
+ Write_Wait_States = "0cycles";
+ Read_Wait_States = "1cycles";
+ Hold_Time = "0cycles";
+ Setup_Time = "0cycles";
+ Is_Printable_Device = "0";
+ Address_Alignment = "native";
+ Well_Behaved_Waitrequest = "0";
+ Is_Nonvolatile_Storage = "0";
+ Read_Latency = "0";
+ Is_Memory_Device = "0";
+ Maximum_Pending_Read_Transactions = "0";
+ Minimum_Uninterrupted_Run_Length = "1";
+ Accepts_Internal_Connections = "1";
+ Write_Latency = "0";
+ Is_Flash = "0";
+ Data_Width = "32";
+ Address_Width = "1";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "0";
+ Register_Outgoing_Signals = "0";
+ Interleave_Bursts = "0";
+ Linewrap_Bursts = "0";
+ Burst_On_Burst_Boundaries_Only = "0";
+ Always_Burst_Max_Burst = "0";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ MASTERED_BY cpu_0/data_master
+ {
+ priority = "1";
+ Offset_Address = "0x009000d8";
+ }
+ Base_Address = "0x009000d8";
+ Has_IRQ = "0";
+ Address_Group = "0";
+ IRQ_MASTER cpu_0/data_master
+ {
+ IRQ_Number = "NC";
+ }
+ }
+ }
+ class = "altera_avalon_sysid";
+ class_version = "7.08";
+ SYSTEM_BUILDER_INFO
+ {
+ Date_Modified = "";
+ Is_Enabled = "1";
+ Instantiate_In_System_Module = "1";
+ Fixed_Module_Name = "sysid";
+ Top_Level_Ports_Are_Enumerated = "1";
+ Clock_Source = "clk";
+ Has_Clock = "1";
+ View
+ {
+ Settings_Summary = "System ID (at last Generate):<br> <b>2A1C5786</b> (unique ID tag) <br> <b>485BC1C0</b> (timestamp: Fri Jun 20, 2008 @4:42 PM)";
+ MESSAGES
+ {
+ }
+ }
+ }
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ id = "706500486u";
+ timestamp = "1213972928u";
+ regenerate_values = "0";
+ MAKE
+ {
+ TARGET verifysysid
+ {
+ verifysysid
+ {
+ All_Depends_On = "0";
+ Command = "nios2-download $(JTAG_CABLE) --sidp=0x009000d8 --id=706500486 --timestamp=1213972928";
+ Is_Phony = "1";
+ Target_File = "dummy_verifysysid_file";
+ }
+ }
+ }
+ }
+ HDL_INFO
+ {
+ Precompiled_Simulation_Library_Files = "";
+ Simulation_HDL_Files = "";
+ Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sysid.vhd";
+ Synthesis_Only_Files = "";
+ }
+ PORT_WIRING
+ {
+ }
+ }
+ MODULE LED_Pio
+ {
+ SLAVE s1
+ {
+ PORT_WIRING
+ {
+ PORT clk
+ {
+ type = "clk";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT reset_n
+ {
+ type = "reset_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT address
+ {
+ type = "address";
+ width = "2";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT write_n
+ {
+ type = "write_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT writedata
+ {
+ type = "writedata";
+ width = "8";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT chipselect
+ {
+ type = "chipselect";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon";
+ Write_Wait_States = "0cycles";
+ Read_Wait_States = "1cycles";
+ Hold_Time = "0cycles";
+ Setup_Time = "0cycles";
+ Is_Printable_Device = "0";
+ Address_Alignment = "native";
+ Well_Behaved_Waitrequest = "0";
+ Is_Nonvolatile_Storage = "0";
+ Read_Latency = "0";
+ Is_Memory_Device = "0";
+ Maximum_Pending_Read_Transactions = "0";
+ Minimum_Uninterrupted_Run_Length = "1";
+ Accepts_Internal_Connections = "1";
+ Write_Latency = "0";
+ Is_Flash = "0";
+ Data_Width = "8";
+ Address_Width = "2";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "0";
+ Register_Outgoing_Signals = "0";
+ Interleave_Bursts = "0";
+ Linewrap_Bursts = "0";
+ Burst_On_Burst_Boundaries_Only = "0";
+ Always_Burst_Max_Burst = "0";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ MASTERED_BY cpu_0/data_master
+ {
+ priority = "1";
+ Offset_Address = "0x00900080";
+ }
+ Base_Address = "0x00900080";
+ Has_IRQ = "0";
+ Address_Group = "0";
+ IRQ_MASTER cpu_0/data_master
+ {
+ IRQ_Number = "NC";
+ }
+ Is_Readable = "0";
+ Is_Writable = "1";
+ }
+ }
+ PORT_WIRING
+ {
+ PORT out_port
+ {
+ type = "export";
+ width = "8";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT in_port
+ {
+ direction = "input";
+ Is_Enabled = "0";
+ width = "8";
+ }
+ PORT bidir_port
+ {
+ direction = "inout";
+ Is_Enabled = "0";
+ width = "8";
+ }
+ }
+ class = "altera_avalon_pio";
+ class_version = "7.08";
+ SYSTEM_BUILDER_INFO
+ {
+ Is_Enabled = "1";
+ Instantiate_In_System_Module = "1";
+ Wire_Test_Bench_Values = "1";
+ Top_Level_Ports_Are_Enumerated = "1";
+ Clock_Source = "clk";
+ Has_Clock = "1";
+ Date_Modified = "";
+ View
+ {
+ MESSAGES
+ {
+ }
+ Settings_Summary = " 8-bit PIO using <br>
+
+
+ output pins";
+ }
+ }
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ Do_Test_Bench_Wiring = "0";
+ Driven_Sim_Value = "0";
+ has_tri = "0";
+ has_out = "1";
+ has_in = "0";
+ capture = "0";
+ Data_Width = "8";
+ reset_value = "0";
+ edge_type = "NONE";
+ irq_type = "NONE";
+ bit_clearing_edge_register = "0";
+ }
+ HDL_INFO
+ {
+ Precompiled_Simulation_Library_Files = "";
+ Simulation_HDL_Files = "";
+ Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/LED_Pio.vhd";
+ Synthesis_Only_Files = "";
+ }
+ }
+ MODULE SG_Pio
+ {
+ SLAVE s1
+ {
+ PORT_WIRING
+ {
+ PORT clk
+ {
+ type = "clk";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT reset_n
+ {
+ type = "reset_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT address
+ {
+ type = "address";
+ width = "2";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT write_n
+ {
+ type = "write_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT writedata
+ {
+ type = "writedata";
+ width = "14";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT chipselect
+ {
+ type = "chipselect";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon";
+ Write_Wait_States = "0cycles";
+ Read_Wait_States = "1cycles";
+ Hold_Time = "0cycles";
+ Setup_Time = "0cycles";
+ Is_Printable_Device = "0";
+ Address_Alignment = "native";
+ Well_Behaved_Waitrequest = "0";
+ Is_Nonvolatile_Storage = "0";
+ Read_Latency = "0";
+ Is_Memory_Device = "0";
+ Maximum_Pending_Read_Transactions = "0";
+ Minimum_Uninterrupted_Run_Length = "1";
+ Accepts_Internal_Connections = "1";
+ Write_Latency = "0";
+ Is_Flash = "0";
+ Data_Width = "14";
+ Address_Width = "2";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "0";
+ Register_Outgoing_Signals = "0";
+ Interleave_Bursts = "0";
+ Linewrap_Bursts = "0";
+ Burst_On_Burst_Boundaries_Only = "0";
+ Always_Burst_Max_Burst = "0";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ MASTERED_BY cpu_0/data_master
+ {
+ priority = "1";
+ Offset_Address = "0x00900090";
+ }
+ Base_Address = "0x00900090";
+ Has_IRQ = "0";
+ Address_Group = "0";
+ IRQ_MASTER cpu_0/data_master
+ {
+ IRQ_Number = "NC";
+ }
+ Is_Readable = "0";
+ Is_Writable = "1";
+ }
+ }
+ PORT_WIRING
+ {
+ PORT out_port
+ {
+ type = "export";
+ width = "14";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT in_port
+ {
+ direction = "input";
+ Is_Enabled = "0";
+ width = "14";
+ }
+ PORT bidir_port
+ {
+ direction = "inout";
+ Is_Enabled = "0";
+ width = "14";
+ }
+ }
+ class = "altera_avalon_pio";
+ class_version = "7.08";
+ SYSTEM_BUILDER_INFO
+ {
+ Is_Enabled = "1";
+ Instantiate_In_System_Module = "1";
+ Wire_Test_Bench_Values = "1";
+ Top_Level_Ports_Are_Enumerated = "1";
+ Clock_Source = "clk";
+ Has_Clock = "1";
+ Date_Modified = "";
+ View
+ {
+ MESSAGES
+ {
+ }
+ Settings_Summary = " 14-bit PIO using <br>
+
+
+ output pins";
+ }
+ }
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ Do_Test_Bench_Wiring = "0";
+ Driven_Sim_Value = "0";
+ has_tri = "0";
+ has_out = "1";
+ has_in = "0";
+ capture = "0";
+ Data_Width = "14";
+ reset_value = "0";
+ edge_type = "NONE";
+ irq_type = "NONE";
+ bit_clearing_edge_register = "0";
+ }
+ HDL_INFO
+ {
+ Precompiled_Simulation_Library_Files = "";
+ Simulation_HDL_Files = "";
+ Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/SG_Pio.vhd";
+ Synthesis_Only_Files = "";
+ }
+ }
+ MODULE IO_Pio
+ {
+ SLAVE s1
+ {
+ PORT_WIRING
+ {
+ PORT clk
+ {
+ type = "clk";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT reset_n
+ {
+ type = "reset_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT address
+ {
+ type = "address";
+ width = "2";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT write_n
+ {
+ type = "write_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT writedata
+ {
+ type = "writedata";
+ width = "32";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT chipselect
+ {
+ type = "chipselect";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT readdata
+ {
+ type = "readdata";
+ width = "32";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon";
+ Write_Wait_States = "0cycles";
+ Read_Wait_States = "1cycles";
+ Hold_Time = "0cycles";
+ Setup_Time = "0cycles";
+ Is_Printable_Device = "0";
+ Address_Alignment = "native";
+ Well_Behaved_Waitrequest = "0";
+ Is_Nonvolatile_Storage = "0";
+ Read_Latency = "0";
+ Is_Memory_Device = "0";
+ Maximum_Pending_Read_Transactions = "0";
+ Minimum_Uninterrupted_Run_Length = "1";
+ Accepts_Internal_Connections = "1";
+ Write_Latency = "0";
+ Is_Flash = "0";
+ Data_Width = "32";
+ Address_Width = "2";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "0";
+ Register_Outgoing_Signals = "0";
+ Interleave_Bursts = "0";
+ Linewrap_Bursts = "0";
+ Burst_On_Burst_Boundaries_Only = "0";
+ Always_Burst_Max_Burst = "0";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ MASTERED_BY cpu_0/data_master
+ {
+ priority = "1";
+ Offset_Address = "0x009000a0";
+ }
+ Base_Address = "0x009000a0";
+ Has_IRQ = "0";
+ Address_Group = "0";
+ IRQ_MASTER cpu_0/data_master
+ {
+ IRQ_Number = "NC";
+ }
+ Is_Readable = "1";
+ Is_Writable = "1";
+ }
+ }
+ PORT_WIRING
+ {
+ PORT bidir_port
+ {
+ type = "export";
+ width = "32";
+ direction = "inout";
+ Is_Enabled = "1";
+ }
+ PORT in_port
+ {
+ direction = "input";
+ Is_Enabled = "0";
+ width = "32";
+ }
+ PORT out_port
+ {
+ direction = "output";
+ Is_Enabled = "0";
+ width = "32";
+ }
+ }
+ class = "altera_avalon_pio";
+ class_version = "7.08";
+ SYSTEM_BUILDER_INFO
+ {
+ Is_Enabled = "1";
+ Instantiate_In_System_Module = "1";
+ Wire_Test_Bench_Values = "1";
+ Top_Level_Ports_Are_Enumerated = "1";
+ Clock_Source = "clk";
+ Has_Clock = "1";
+ Date_Modified = "";
+ View
+ {
+ MESSAGES
+ {
+ }
+ Settings_Summary = " 32-bit PIO using <br>
+ tri-state pins with edge type NONE and interrupt source NONE
+
+ ";
+ }
+ }
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ Do_Test_Bench_Wiring = "0";
+ Driven_Sim_Value = "0";
+ has_tri = "1";
+ has_out = "0";
+ has_in = "0";
+ capture = "0";
+ Data_Width = "32";
+ reset_value = "0";
+ edge_type = "NONE";
+ irq_type = "NONE";
+ bit_clearing_edge_register = "0";
+ }
+ HDL_INFO
+ {
+ Precompiled_Simulation_Library_Files = "";
+ Simulation_HDL_Files = "";
+ Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/IO_Pio.vhd";
+ Synthesis_Only_Files = "";
+ }
+ }
+ MODULE Button_Pio
+ {
+ SLAVE s1
+ {
+ PORT_WIRING
+ {
+ PORT clk
+ {
+ type = "clk";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT reset_n
+ {
+ type = "reset_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT address
+ {
+ type = "address";
+ width = "2";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT readdata
+ {
+ type = "readdata";
+ width = "9";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon";
+ Write_Wait_States = "0cycles";
+ Read_Wait_States = "1cycles";
+ Hold_Time = "0cycles";
+ Setup_Time = "0cycles";
+ Is_Printable_Device = "0";
+ Address_Alignment = "native";
+ Well_Behaved_Waitrequest = "0";
+ Is_Nonvolatile_Storage = "0";
+ Read_Latency = "0";
+ Is_Memory_Device = "0";
+ Maximum_Pending_Read_Transactions = "0";
+ Minimum_Uninterrupted_Run_Length = "1";
+ Accepts_Internal_Connections = "1";
+ Write_Latency = "0";
+ Is_Flash = "0";
+ Data_Width = "9";
+ Address_Width = "2";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "0";
+ Register_Outgoing_Signals = "0";
+ Interleave_Bursts = "0";
+ Linewrap_Bursts = "0";
+ Burst_On_Burst_Boundaries_Only = "0";
+ Always_Burst_Max_Burst = "0";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ MASTERED_BY cpu_0/data_master
+ {
+ priority = "1";
+ Offset_Address = "0x009000b0";
+ }
+ Base_Address = "0x009000b0";
+ Has_IRQ = "0";
+ Address_Group = "0";
+ IRQ_MASTER cpu_0/data_master
+ {
+ IRQ_Number = "NC";
+ }
+ Is_Readable = "1";
+ Is_Writable = "0";
+ }
+ }
+ PORT_WIRING
+ {
+ PORT in_port
+ {
+ type = "export";
+ width = "9";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT out_port
+ {
+ direction = "output";
+ Is_Enabled = "0";
+ width = "9";
+ }
+ PORT bidir_port
+ {
+ direction = "inout";
+ Is_Enabled = "0";
+ width = "9";
+ }
+ }
+ class = "altera_avalon_pio";
+ class_version = "7.08";
+ SYSTEM_BUILDER_INFO
+ {
+ Is_Enabled = "1";
+ Instantiate_In_System_Module = "1";
+ Wire_Test_Bench_Values = "1";
+ Top_Level_Ports_Are_Enumerated = "1";
+ Clock_Source = "clk";
+ Has_Clock = "1";
+ Date_Modified = "";
+ View
+ {
+ MESSAGES
+ {
+ }
+ Settings_Summary = " 9-bit PIO using <br>
+
+ input pins with edge type NONE and interrupt source NONE
+ ";
+ }
+ }
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ Do_Test_Bench_Wiring = "0";
+ Driven_Sim_Value = "0";
+ has_tri = "0";
+ has_out = "0";
+ has_in = "1";
+ capture = "0";
+ Data_Width = "9";
+ reset_value = "0";
+ edge_type = "NONE";
+ irq_type = "NONE";
+ bit_clearing_edge_register = "0";
+ }
+ HDL_INFO
+ {
+ Precompiled_Simulation_Library_Files = "";
+ Simulation_HDL_Files = "";
+ Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/Button_Pio.vhd";
+ Synthesis_Only_Files = "";
+ }
+ }
+ MODULE uart
+ {
+ SLAVE s1
+ {
+ PORT_WIRING
+ {
+ PORT clk
+ {
+ type = "clk";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT reset_n
+ {
+ type = "reset_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT irq
+ {
+ type = "irq";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT address
+ {
+ type = "address";
+ width = "3";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT begintransfer
+ {
+ type = "begintransfer";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT chipselect
+ {
+ type = "chipselect";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT read_n
+ {
+ type = "read_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT write_n
+ {
+ type = "write_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT writedata
+ {
+ type = "writedata";
+ width = "16";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT readdata
+ {
+ type = "readdata";
+ width = "16";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT dataavailable
+ {
+ type = "dataavailable";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT readyfordata
+ {
+ type = "readyfordata";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Has_IRQ = "1";
+ Bus_Type = "avalon";
+ Write_Wait_States = "1cycles";
+ Read_Wait_States = "1cycles";
+ Hold_Time = "0cycles";
+ Setup_Time = "0cycles";
+ Is_Printable_Device = "1";
+ Address_Alignment = "native";
+ Well_Behaved_Waitrequest = "0";
+ Is_Nonvolatile_Storage = "0";
+ Read_Latency = "0";
+ Is_Memory_Device = "0";
+ Maximum_Pending_Read_Transactions = "0";
+ Minimum_Uninterrupted_Run_Length = "1";
+ Accepts_Internal_Connections = "1";
+ Write_Latency = "0";
+ Is_Flash = "0";
+ Data_Width = "16";
+ Address_Width = "3";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "0";
+ Register_Outgoing_Signals = "0";
+ Interleave_Bursts = "0";
+ Linewrap_Bursts = "0";
+ Burst_On_Burst_Boundaries_Only = "0";
+ Always_Burst_Max_Burst = "0";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ MASTERED_BY cpu_0/data_master
+ {
+ priority = "1";
+ Offset_Address = "0x00900040";
+ }
+ IRQ_MASTER cpu_0/data_master
+ {
+ IRQ_Number = "0";
+ }
+ Base_Address = "0x00900040";
+ Address_Group = "0";
+ }
+ }
+ PORT_WIRING
+ {
+ PORT rxd
+ {
+ type = "export";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT txd
+ {
+ type = "export";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT cts_n
+ {
+ direction = "input";
+ width = "1";
+ Is_Enabled = "0";
+ }
+ PORT rts_n
+ {
+ direction = "output";
+ width = "1";
+ Is_Enabled = "0";
+ }
+ }
+ class = "altera_avalon_uart";
+ class_version = "7.08";
+ iss_model_name = "altera_avalon_uart";
+ SYSTEM_BUILDER_INFO
+ {
+ Instantiate_In_System_Module = "1";
+ Is_Enabled = "1";
+ Iss_Launch_Telnet = "0";
+ Top_Level_Ports_Are_Enumerated = "1";
+ View
+ {
+ Settings_Summary = "8-bit UART with 115200 baud, <br>
+ 1 stop bits and N parity";
+ Is_Collapsed = "1";
+ MESSAGES
+ {
+ }
+ }
+ Clock_Source = "clk";
+ Has_Clock = "1";
+ }
+ SIMULATION
+ {
+ DISPLAY
+ {
+ SIGNAL a
+ {
+ name = " Bus Interface";
+ format = "Divider";
+ }
+ SIGNAL b
+ {
+ name = "chipselect";
+ }
+ SIGNAL c
+ {
+ name = "address";
+ radix = "hexadecimal";
+ }
+ SIGNAL d
+ {
+ name = "writedata";
+ radix = "hexadecimal";
+ }
+ SIGNAL e
+ {
+ name = "readdata";
+ radix = "hexadecimal";
+ }
+ SIGNAL f
+ {
+ name = " Internals";
+ format = "Divider";
+ }
+ SIGNAL g
+ {
+ name = "tx_ready";
+ }
+ SIGNAL h
+ {
+ name = "tx_data";
+ radix = "ascii";
+ }
+ SIGNAL i
+ {
+ name = "rx_char_ready";
+ }
+ SIGNAL j
+ {
+ name = "rx_data";
+ radix = "ascii";
+ }
+ }
+ INTERACTIVE_OUT log
+ {
+ enable = "0";
+ file = "_log_module.txt";
+ radix = "ascii";
+ signals = "temp,list";
+ exe = "perl -- tail-f.pl";
+ }
+ INTERACTIVE_IN drive
+ {
+ enable = "0";
+ file = "_input_data_stream.dat";
+ mutex = "_input_data_mutex.dat";
+ log = "_in.log";
+ rate = "100";
+ signals = "temp,list";
+ exe = "perl -- uart.pl";
+ }
+ }
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ baud = "115200";
+ data_bits = "8";
+ fixed_baud = "1";
+ parity = "N";
+ stop_bits = "1";
+ use_cts_rts = "0";
+ use_eop_register = "0";
+ sim_true_baud = "0";
+ sim_char_stream = "";
+ }
+ HDL_INFO
+ {
+ Precompiled_Simulation_Library_Files = "";
+ Simulation_HDL_Files = "";
+ Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/uart.vhd";
+ Synthesis_Only_Files = "";
+ }
+ }
+ MODULE LM74_Pio
+ {
+ SLAVE s1
+ {
+ PORT_WIRING
+ {
+ PORT clk
+ {
+ type = "clk";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT reset_n
+ {
+ type = "reset_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT address
+ {
+ type = "address";
+ width = "2";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT write_n
+ {
+ type = "write_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT writedata
+ {
+ type = "writedata";
+ width = "3";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT chipselect
+ {
+ type = "chipselect";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT readdata
+ {
+ type = "readdata";
+ width = "3";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon";
+ Write_Wait_States = "0cycles";
+ Read_Wait_States = "1cycles";
+ Hold_Time = "0cycles";
+ Setup_Time = "0cycles";
+ Is_Printable_Device = "0";
+ Address_Alignment = "native";
+ Well_Behaved_Waitrequest = "0";
+ Is_Nonvolatile_Storage = "0";
+ Read_Latency = "0";
+ Is_Memory_Device = "0";
+ Maximum_Pending_Read_Transactions = "0";
+ Minimum_Uninterrupted_Run_Length = "1";
+ Accepts_Internal_Connections = "1";
+ Write_Latency = "0";
+ Is_Flash = "0";
+ Data_Width = "3";
+ Address_Width = "2";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "0";
+ Register_Outgoing_Signals = "0";
+ Interleave_Bursts = "0";
+ Linewrap_Bursts = "0";
+ Burst_On_Burst_Boundaries_Only = "0";
+ Always_Burst_Max_Burst = "0";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ MASTERED_BY cpu_0/data_master
+ {
+ priority = "1";
+ Offset_Address = "0x009000c0";
+ }
+ Base_Address = "0x009000c0";
+ Has_IRQ = "0";
+ Address_Group = "0";
+ IRQ_MASTER cpu_0/data_master
+ {
+ IRQ_Number = "NC";
+ }
+ Is_Readable = "1";
+ Is_Writable = "1";
+ }
+ }
+ PORT_WIRING
+ {
+ PORT bidir_port
+ {
+ type = "export";
+ width = "3";
+ direction = "inout";
+ Is_Enabled = "1";
+ }
+ PORT in_port
+ {
+ direction = "input";
+ Is_Enabled = "0";
+ width = "3";
+ }
+ PORT out_port
+ {
+ direction = "output";
+ Is_Enabled = "0";
+ width = "3";
+ }
+ }
+ class = "altera_avalon_pio";
+ class_version = "7.08";
+ SYSTEM_BUILDER_INFO
+ {
+ Is_Enabled = "1";
+ Instantiate_In_System_Module = "1";
+ Wire_Test_Bench_Values = "1";
+ Top_Level_Ports_Are_Enumerated = "1";
+ Clock_Source = "clk";
+ Has_Clock = "1";
+ Date_Modified = "";
+ View
+ {
+ MESSAGES
+ {
+ }
+ Settings_Summary = " 3-bit PIO using <br>
+ tri-state pins with edge type NONE and interrupt source NONE
+
+ ";
+ }
+ }
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ Do_Test_Bench_Wiring = "0";
+ Driven_Sim_Value = "0";
+ has_tri = "1";
+ has_out = "0";
+ has_in = "0";
+ capture = "0";
+ Data_Width = "3";
+ reset_value = "0";
+ edge_type = "NONE";
+ irq_type = "NONE";
+ bit_clearing_edge_register = "0";
+ }
+ HDL_INFO
+ {
+ Precompiled_Simulation_Library_Files = "";
+ Simulation_HDL_Files = "";
+ Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/LM74_Pio.vhd";
+ Synthesis_Only_Files = "";
+ }
+ }
+ MODULE epcs_controller
+ {
+ SLAVE epcs_control_port
+ {
+ PORT_WIRING
+ {
+ PORT clk
+ {
+ type = "clk";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT reset_n
+ {
+ type = "reset_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT irq
+ {
+ type = "irq";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT address
+ {
+ type = "address";
+ width = "9";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT chipselect
+ {
+ type = "chipselect";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT dataavailable
+ {
+ type = "dataavailable";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT endofpacket
+ {
+ type = "endofpacket";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT read_n
+ {
+ type = "read_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT readdata
+ {
+ type = "readdata";
+ width = "32";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT readyfordata
+ {
+ type = "readyfordata";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT write_n
+ {
+ type = "write_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT writedata
+ {
+ type = "writedata";
+ width = "32";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT data_from_cpu
+ {
+ Is_Enabled = "0";
+ direction = "input";
+ type = "writedata";
+ width = "16";
+ }
+ PORT data_to_cpu
+ {
+ Is_Enabled = "0";
+ direction = "output";
+ type = "readdata";
+ width = "16";
+ }
+ PORT epcs_select
+ {
+ Is_Enabled = "0";
+ direction = "input";
+ type = "chipselect";
+ width = "1";
+ }
+ PORT mem_addr
+ {
+ Is_Enabled = "0";
+ direction = "input";
+ type = "address";
+ width = "3";
+ }
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Has_IRQ = "1";
+ Bus_Type = "avalon";
+ Write_Wait_States = "1cycles";
+ Read_Wait_States = "1cycles";
+ Hold_Time = "0cycles";
+ Setup_Time = "0cycles";
+ Is_Printable_Device = "0";
+ Address_Alignment = "dynamic";
+ Well_Behaved_Waitrequest = "0";
+ Is_Nonvolatile_Storage = "1";
+ Address_Span = "2048";
+ Read_Latency = "0";
+ Is_Memory_Device = "1";
+ Maximum_Pending_Read_Transactions = "0";
+ Minimum_Uninterrupted_Run_Length = "1";
+ Accepts_Internal_Connections = "1";
+ Write_Latency = "0";
+ Is_Flash = "1";
+ Data_Width = "32";
+ Address_Width = "9";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "0";
+ Register_Outgoing_Signals = "0";
+ Interleave_Bursts = "0";
+ Linewrap_Bursts = "0";
+ Burst_On_Burst_Boundaries_Only = "0";
+ Always_Burst_Max_Burst = "0";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ MASTERED_BY cpu_0/instruction_master
+ {
+ priority = "1";
+ Offset_Address = "0x00906000";
+ }
+ MASTERED_BY cpu_0/data_master
+ {
+ priority = "1";
+ Offset_Address = "0x00906000";
+ }
+ IRQ_MASTER cpu_0/data_master
+ {
+ IRQ_Number = "2";
+ }
+ Base_Address = "0x00906000";
+ Address_Group = "0";
+ }
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ class = "altera_avalon_epcs_flash_controller";
+ flash_reference_designator = "";
+ }
+ }
+ PORT_WIRING
+ {
+ PORT dclk
+ {
+ type = "export";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT sce
+ {
+ type = "export";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT sdo
+ {
+ type = "export";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT data0
+ {
+ type = "export";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ }
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ databits = "8";
+ targetclock = "20";
+ clockunits = "MHz";
+ clockmult = "1000000";
+ numslaves = "1";
+ ismaster = "1";
+ clockpolarity = "0";
+ clockphase = "0";
+ lsbfirst = "0";
+ extradelay = "0";
+ targetssdelay = "100";
+ delayunits = "us";
+ delaymult = "1e-006";
+ prefix = "epcs_";
+ register_offset = "0x400";
+ use_asmi_atom = "0";
+ MAKE
+ {
+ MACRO
+ {
+ EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX = "$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_TMP1:0=)";
+ EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)";
+ }
+ MASTER cpu_0
+ {
+ MACRO
+ {
+ BOOTS_FROM_EPCS = "0";
+ BOOT_COPIER_EPCS = "boot_loader_epcs.srec";
+ CPU_CLASS = "altera_nios2";
+ CPU_RESET_ADDRESS = "0x0";
+ }
+ }
+ TARGET delete_placeholder_warning
+ {
+ epcs_controller
+ {
+ Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
+ Is_Phony = "1";
+ Target_File = "do_delete_placeholder_warning";
+ }
+ }
+ TARGET flashfiles
+ {
+ epcs_controller
+ {
+ Command1 = "@if [ $(BOOTS_FROM_EPCS) -eq 1 ]; then echo Post-processing to create $(notdir $@) ; elf2flash --input=$(ELF) --flash= --boot=$(DBL_QUOTE)$(shell $(DBL_QUOTE)$(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir$(DBL_QUOTE) $(CPU_CLASS) $(QUARTUS_PROJECT_DIR))/$(BOOT_COPIER_EPCS)$(DBL_QUOTE) --outfile=$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --epcs --base=0x0 --end=0x7FFFFFFF ; fi";
+ Dependency = "$(ELF)";
+ Target_File = "$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash";
+ }
+ }
+ TARGET sim
+ {
+ epcs_controller
+ {
+ Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
+ Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
+ Command3 = "touch $(SIMDIR)/dummy_file";
+ Dependency = "$(ELF)";
+ Target_File = "$(SIMDIR)/dummy_file";
+ }
+ }
+ }
+ clockunit = "kHz";
+ delayunit = "us";
+ }
+ class = "altera_avalon_epcs_flash_controller";
+ class_version = "7.08";
+ SYSTEM_BUILDER_INFO
+ {
+ Is_Enabled = "1";
+ Clock_Source = "clk";
+ Has_Clock = "1";
+ Instantiate_In_System_Module = "1";
+ Required_Device_Family = "STRATIX,CYCLONE,CYCLONEII,CYCLONEIII,STRATIXIII,STRATIXII,STRATIXIIGX,ARRIAGX,STRATIXIIGXLITE";
+ Fixed_Module_Name = "epcs_controller";
+ Top_Level_Ports_Are_Enumerated = "1";
+ View
+ {
+ MESSAGES
+ {
+ }
+ }
+ }
+ HDL_INFO
+ {
+ Precompiled_Simulation_Library_Files = "";
+ Simulation_HDL_Files = "";
+ Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/epcs_controller.vhd";
+ Synthesis_Only_Files = "";
+ }
+ }
+ MODULE tri_state_bridge_0
+ {
+ SLAVE avalon_slave
+ {
+ PORT_WIRING
+ {
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon";
+ Write_Wait_States = "0cycles";
+ Read_Wait_States = "1cycles";
+ Hold_Time = "0cycles";
+ Setup_Time = "0cycles";
+ Is_Printable_Device = "0";
+ Address_Alignment = "dynamic";
+ Well_Behaved_Waitrequest = "0";
+ Is_Nonvolatile_Storage = "0";
+ Address_Span = "1";
+ Read_Latency = "0";
+ Is_Memory_Device = "0";
+ Maximum_Pending_Read_Transactions = "0";
+ Minimum_Uninterrupted_Run_Length = "1";
+ Accepts_Internal_Connections = "1";
+ Write_Latency = "0";
+ Is_Flash = "0";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "1";
+ Register_Outgoing_Signals = "1";
+ Interleave_Bursts = "0";
+ Linewrap_Bursts = "0";
+ Burst_On_Burst_Boundaries_Only = "0";
+ Always_Burst_Max_Burst = "0";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ MASTERED_BY cpu_0/data_master
+ {
+ priority = "1";
+ Offset_Address = "0x00000000";
+ }
+ MASTERED_BY cpu_0/instruction_master
+ {
+ priority = "1";
+ Offset_Address = "0x00000000";
+ }
+ MASTERED_BY nios_vga_inst/vga_dma
+ {
+ priority = "1";
+ Offset_Address = "0x00000000";
+ }
+ Bridges_To = "tristate_master";
+ Base_Address = "N/A";
+ Has_IRQ = "0";
+ IRQ = "N/A";
+ Address_Group = "0";
+ IRQ_MASTER cpu_0/data_master
+ {
+ IRQ_Number = "NC";
+ }
+ }
+ }
+ MASTER tristate_master
+ {
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon_tristate";
+ Is_Asynchronous = "0";
+ DBS_Big_Endian = "0";
+ Adapts_To = "";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "0";
+ Register_Outgoing_Signals = "0";
+ Interleave_Bursts = "0";
+ Linewrap_Bursts = "0";
+ Burst_On_Burst_Boundaries_Only = "0";
+ Always_Burst_Max_Burst = "0";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ Bridges_To = "avalon_slave";
+ }
+ PORT_WIRING
+ {
+ }
+ MEMORY_MAP
+ {
+ Entry cfi_flash/s1
+ {
+ address = "0x00000000";
+ span = "0x00800000";
+ is_bridge = "0";
+ }
+ Entry DBC3C40_SRAM_inst/avalon_tristate_slave
+ {
+ address = "0x00800000";
+ span = "0x00100000";
+ is_bridge = "0";
+ }
+ }
+ }
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ }
+ class = "altera_avalon_tri_state_bridge";
+ class_version = "7.08";
+ SYSTEM_BUILDER_INFO
+ {
+ Is_Enabled = "1";
+ Clock_Source = "clk";
+ Has_Clock = "1";
+ Instantiate_In_System_Module = "1";
+ Is_Bridge = "1";
+ Top_Level_Ports_Are_Enumerated = "1";
+ View
+ {
+ MESSAGES
+ {
+ }
+ }
+ }
+ }
+ MODULE sys_clk
+ {
+ SLAVE s1
+ {
+ PORT_WIRING
+ {
+ PORT clk
+ {
+ type = "clk";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT reset_n
+ {
+ type = "reset_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT irq
+ {
+ type = "irq";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT address
+ {
+ type = "address";
+ width = "3";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT writedata
+ {
+ type = "writedata";
+ width = "16";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT readdata
+ {
+ type = "readdata";
+ width = "16";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT chipselect
+ {
+ type = "chipselect";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT write_n
+ {
+ type = "write_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Has_IRQ = "1";
+ Bus_Type = "avalon";
+ Write_Wait_States = "0cycles";
+ Read_Wait_States = "1cycles";
+ Hold_Time = "0cycles";
+ Setup_Time = "0cycles";
+ Is_Printable_Device = "0";
+ Address_Alignment = "native";
+ Well_Behaved_Waitrequest = "0";
+ Is_Nonvolatile_Storage = "0";
+ Read_Latency = "0";
+ Is_Memory_Device = "0";
+ Maximum_Pending_Read_Transactions = "0";
+ Minimum_Uninterrupted_Run_Length = "1";
+ Accepts_Internal_Connections = "1";
+ Write_Latency = "0";
+ Is_Flash = "0";
+ Data_Width = "16";
+ Address_Width = "3";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "0";
+ Register_Outgoing_Signals = "0";
+ Interleave_Bursts = "0";
+ Linewrap_Bursts = "0";
+ Burst_On_Burst_Boundaries_Only = "0";
+ Always_Burst_Max_Burst = "0";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ MASTERED_BY cpu_0/data_master
+ {
+ priority = "1";
+ Offset_Address = "0x00900060";
+ }
+ IRQ_MASTER cpu_0/data_master
+ {
+ IRQ_Number = "3";
+ }
+ Base_Address = "0x00900060";
+ Address_Group = "0";
+ }
+ }
+ class = "altera_avalon_timer";
+ class_version = "7.08";
+ iss_model_name = "altera_avalon_timer";
+ SYSTEM_BUILDER_INFO
+ {
+ Instantiate_In_System_Module = "1";
+ Is_Enabled = "1";
+ Top_Level_Ports_Are_Enumerated = "1";
+ View
+ {
+ Settings_Summary = "Timer with 1 ms timeout period.";
+ Is_Collapsed = "1";
+ MESSAGES
+ {
+ }
+ }
+ Clock_Source = "clk";
+ Has_Clock = "1";
+ }
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ always_run = "0";
+ fixed_period = "0";
+ snapshot = "1";
+ period = "1.0";
+ period_units = "ms";
+ reset_output = "0";
+ timeout_pulse_output = "0";
+ load_value = "74999";
+ counter_size = "32";
+ mult = "0.0010";
+ ticks_per_sec = "1000";
+ }
+ HDL_INFO
+ {
+ Precompiled_Simulation_Library_Files = "";
+ Simulation_HDL_Files = "";
+ Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sys_clk.vhd";
+ Synthesis_Only_Files = "";
+ }
+ PORT_WIRING
+ {
+ }
+ }
+ MODULE cfi_flash
+ {
+ SLAVE s1
+ {
+ PORT_WIRING
+ {
+ PORT data
+ {
+ type = "data";
+ width = "16";
+ direction = "inout";
+ Is_Enabled = "1";
+ is_shared = "1";
+ }
+ PORT address
+ {
+ type = "address";
+ width = "22";
+ direction = "input";
+ Is_Enabled = "1";
+ is_shared = "1";
+ }
+ PORT read_n
+ {
+ type = "read_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ is_shared = "1";
+ }
+ PORT write_n
+ {
+ type = "write_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ is_shared = "1";
+ }
+ PORT select_n
+ {
+ type = "chipselect_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ is_shared = "0";
+ }
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon_tristate";
+ Write_Wait_States = "100ns";
+ Read_Wait_States = "100ns";
+ Hold_Time = "20ns";
+ Setup_Time = "20ns";
+ Is_Printable_Device = "0";
+ Address_Alignment = "dynamic";
+ Well_Behaved_Waitrequest = "0";
+ Is_Nonvolatile_Storage = "1";
+ Address_Span = "8388608";
+ Read_Latency = "0";
+ Is_Memory_Device = "1";
+ Maximum_Pending_Read_Transactions = "0";
+ Minimum_Uninterrupted_Run_Length = "1";
+ Accepts_Internal_Connections = "1";
+ Write_Latency = "0";
+ Is_Flash = "1";
+ Active_CS_Through_Read_Latency = "0";
+ Data_Width = "16";
+ Address_Width = "22";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "0";
+ Register_Outgoing_Signals = "0";
+ Interleave_Bursts = "0";
+ Linewrap_Bursts = "0";
+ Burst_On_Burst_Boundaries_Only = "0";
+ Always_Burst_Max_Burst = "0";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ MASTERED_BY tri_state_bridge_0/tristate_master
+ {
+ priority = "1";
+ Offset_Address = "0x00000000";
+ }
+ Base_Address = "0x00000000";
+ Has_IRQ = "0";
+ Simulation_Num_Lanes = "1";
+ Convert_Xs_To_0 = "1";
+ Address_Group = "0";
+ IRQ_MASTER cpu_0/data_master
+ {
+ IRQ_Number = "NC";
+ }
+ }
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ class = "altera_avalon_cfi_flash";
+ Supports_Flash_File_System = "1";
+ flash_reference_designator = "";
+ }
+ }
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ Setup_Value = "20";
+ Wait_Value = "100";
+ Hold_Value = "20";
+ Timing_Units = "ns";
+ Unit_Multiplier = "1";
+ Size = "8388608";
+ MAKE
+ {
+ MACRO
+ {
+ CFI_FLASH_FLASHTARGET_ALT_SIM_PREFIX = "$(CFI_FLASH_FLASHTARGET_TMP1:0=)";
+ CFI_FLASH_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)";
+ }
+ MASTER cpu_0
+ {
+ MACRO
+ {
+ BOOT_COPIER = "boot_loader_cfi.srec";
+ CPU_CLASS = "altera_nios2";
+ CPU_RESET_ADDRESS = "0x0";
+ }
+ }
+ TARGET delete_placeholder_warning
+ {
+ cfi_flash
+ {
+ Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
+ Is_Phony = "1";
+ Target_File = "do_delete_placeholder_warning";
+ }
+ }
+ TARGET flashfiles
+ {
+ cfi_flash
+ {
+ Command1 = "@echo Post-processing to create $(notdir $@)";
+ Command2 = "elf2flash --input=$(ELF) --flash= --boot=$(DBL_QUOTE)$(shell $(DBL_QUOTE)$(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir$(DBL_QUOTE) $(CPU_CLASS) $(QUARTUS_PROJECT_DIR))/$(BOOT_COPIER)$(DBL_QUOTE) --outfile=$(CFI_FLASH_FLASHTARGET_ALT_SIM_PREFIX)cfi_flash.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --base=0x0 --end=0x7FFFFF --reset=$(CPU_RESET_ADDRESS) ";
+ Dependency = "$(ELF)";
+ Target_File = "$(CFI_FLASH_FLASHTARGET_ALT_SIM_PREFIX)cfi_flash.flash";
+ }
+ }
+ TARGET sim
+ {
+ cfi_flash
+ {
+ Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
+ Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
+ Command3 = "touch $(SIMDIR)/dummy_file";
+ Dependency = "$(ELF)";
+ Target_File = "$(SIMDIR)/dummy_file";
+ }
+ }
+ }
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Simulation_Num_Lanes = "2";
+ Is_Enabled = "1";
+ Clock_Source = "clk";
+ Has_Clock = "1";
+ Make_Memory_Model = "1";
+ Instantiate_In_System_Module = "0";
+ Top_Level_Ports_Are_Enumerated = "1";
+ View
+ {
+ MESSAGES
+ {
+ }
+ }
+ }
+ class = "altera_avalon_cfi_flash";
+ class_version = "7.08";
+ iss_model_name = "altera_avalon_flash";
+ HDL_INFO
+ {
+ }
+ }
+ MODULE nios_vga_inst
+ {
+ MASTER vga_dma
+ {
+ PORT_WIRING
+ {
+ PORT cpu_clk
+ {
+ type = "clk";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT rst_n
+ {
+ type = "reset_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT ram_in
+ {
+ type = "readdata";
+ width = "32";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT wait_st
+ {
+ type = "waitrequest";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT ram_cs
+ {
+ type = "chipselect";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT ram_wr
+ {
+ type = "write";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT ram_rd
+ {
+ type = "read";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT ram_addr
+ {
+ type = "address";
+ width = "26";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT ram_out
+ {
+ type = "writedata";
+ width = "32";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ }
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon";
+ Is_Asynchronous = "0";
+ DBS_Big_Endian = "0";
+ Adapts_To = "";
+ Do_Stream_Reads = "0";
+ Do_Stream_Writes = "0";
+ Max_Address_Width = "32";
+ Data_Width = "32";
+ Address_Width = "26";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "0";
+ Register_Outgoing_Signals = "0";
+ Interleave_Bursts = "0";
+ Linewrap_Bursts = "0";
+ Burst_On_Burst_Boundaries_Only = "0";
+ Always_Burst_Max_Burst = "0";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ }
+ MEMORY_MAP
+ {
+ Entry cfi_flash/s1
+ {
+ address = "0x00000000";
+ span = "0x00800000";
+ is_bridge = "0";
+ }
+ Entry DBC3C40_SRAM_inst/avalon_tristate_slave
+ {
+ address = "0x00800000";
+ span = "0x00100000";
+ is_bridge = "0";
+ }
+ }
+ }
+ SLAVE vga_regs
+ {
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon";
+ Write_Wait_States = "1cycles";
+ Read_Wait_States = "1cycles";
+ Hold_Time = "0cycles";
+ Setup_Time = "0cycles";
+ Is_Printable_Device = "0";
+ Address_Alignment = "native";
+ Well_Behaved_Waitrequest = "0";
+ Is_Nonvolatile_Storage = "0";
+ Read_Latency = "0";
+ Is_Memory_Device = "0";
+ Maximum_Pending_Read_Transactions = "0";
+ Minimum_Uninterrupted_Run_Length = "1";
+ Accepts_Internal_Connections = "1";
+ Write_Latency = "0";
+ Is_Flash = "0";
+ Data_Width = "32";
+ Address_Width = "4";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "0";
+ Register_Outgoing_Signals = "0";
+ Interleave_Bursts = "0";
+ Linewrap_Bursts = "0";
+ Burst_On_Burst_Boundaries_Only = "0";
+ Always_Burst_Max_Burst = "0";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ MASTERED_BY cpu_0/data_master
+ {
+ priority = "1";
+ Offset_Address = "0x00900000";
+ }
+ Base_Address = "0x00900000";
+ Address_Group = "0";
+ IRQ_MASTER cpu_0/data_master
+ {
+ IRQ_Number = "NC";
+ }
+ }
+ PORT_WIRING
+ {
+ PORT cpu_cs
+ {
+ type = "chipselect";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT cpu_wr
+ {
+ type = "write";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT cpu_addr
+ {
+ type = "address";
+ width = "4";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT cpu_in
+ {
+ type = "writedata";
+ width = "32";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ PORT cpu_out
+ {
+ type = "readdata";
+ width = "32";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ }
+ }
+ PORT_WIRING
+ {
+ PORT r
+ {
+ type = "export";
+ width = "8";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT g
+ {
+ type = "export";
+ width = "8";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT b
+ {
+ type = "export";
+ width = "8";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT hs
+ {
+ type = "export";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT vs
+ {
+ type = "export";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT m1
+ {
+ type = "export";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT m2
+ {
+ type = "export";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT blank_n
+ {
+ type = "export";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT sync_n
+ {
+ type = "export";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT sync_t
+ {
+ type = "export";
+ width = "1";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT lcd_reg
+ {
+ type = "export";
+ width = "3";
+ direction = "output";
+ Is_Enabled = "1";
+ }
+ PORT video_clk
+ {
+ type = "export";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ }
+ }
+ class = "no_legacy_module";
+ class_version = "7.08";
+ gtf_class_name = "nios_vga";
+ gtf_class_version = "1.0.1";
+ SYSTEM_BUILDER_INFO
+ {
+ Do_Not_Generate = "1";
+ Instantiate_In_System_Module = "1";
+ Is_Enabled = "1";
+ Clock_Source = "clk";
+ Has_Clock = "1";
+ View
+ {
+ MESSAGES
+ {
+ }
+ }
+ }
+ HDL_INFO
+ {
+ Simulation_HDL_Files = "__PROJECT_DIRECTORY__/nios_vga_inst.vhd";
+ }
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ terminated_ports
+ {
+ }
+ }
+ }
+ MODULE DBC3C40_SRAM_inst
+ {
+ SLAVE avalon_tristate_slave
+ {
+ SYSTEM_BUILDER_INFO
+ {
+ Bus_Type = "avalon_tristate";
+ Write_Wait_States = "1cycles";
+ Read_Wait_States = "1cycles";
+ Hold_Time = "1cycles";
+ Setup_Time = "0cycles";
+ Is_Printable_Device = "0";
+ Address_Alignment = "dynamic";
+ Well_Behaved_Waitrequest = "0";
+ Is_Nonvolatile_Storage = "0";
+ Address_Span = "1048576";
+ Read_Latency = "0";
+ Is_Memory_Device = "1";
+ Maximum_Pending_Read_Transactions = "0";
+ Minimum_Uninterrupted_Run_Length = "1";
+ Accepts_Internal_Connections = "1";
+ Write_Latency = "0";
+ Is_Flash = "0";
+ Active_CS_Through_Read_Latency = "0";
+ Data_Width = "16";
+ Address_Width = "19";
+ Maximum_Burst_Size = "1";
+ Register_Incoming_Signals = "0";
+ Register_Outgoing_Signals = "0";
+ Interleave_Bursts = "0";
+ Linewrap_Bursts = "0";
+ Burst_On_Burst_Boundaries_Only = "0";
+ Always_Burst_Max_Burst = "0";
+ Is_Big_Endian = "0";
+ Is_Enabled = "1";
+ MASTERED_BY tri_state_bridge_0/tristate_master
+ {
+ priority = "1";
+ Offset_Address = "0x00800000";
+ }
+ Base_Address = "0x00800000";
+ Address_Group = "0";
+ IRQ_MASTER cpu_0/data_master
+ {
+ IRQ_Number = "NC";
+ }
+ }
+ PORT_WIRING
+ {
+ PORT addr
+ {
+ type = "address";
+ width = "19";
+ direction = "input";
+ Is_Enabled = "1";
+ is_shared = "1";
+ }
+ PORT data
+ {
+ type = "data";
+ width = "16";
+ direction = "inout";
+ Is_Enabled = "1";
+ is_shared = "1";
+ }
+ PORT ncs
+ {
+ type = "chipselect_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ is_shared = "0";
+ }
+ PORT wrn
+ {
+ type = "write_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ is_shared = "1";
+ }
+ PORT rdn
+ {
+ type = "read_n";
+ width = "1";
+ direction = "input";
+ Is_Enabled = "1";
+ is_shared = "1";
+ }
+ PORT ben
+ {
+ type = "byteenable_n";
+ width = "2";
+ direction = "input";
+ Is_Enabled = "1";
+ is_shared = "1";
+ }
+ }
+ }
+ class = "no_legacy_module";
+ class_version = "7.08";
+ gtf_class_name = "DBC3C40_SRAM";
+ gtf_class_version = "1.0";
+ SYSTEM_BUILDER_INFO
+ {
+ Do_Not_Generate = "1";
+ Instantiate_In_System_Module = "0";
+ Is_Enabled = "1";
+ Clock_Source = "clk";
+ View
+ {
+ MESSAGES
+ {
+ }
+ }
+ }
+ HDL_INFO
+ {
+ Simulation_HDL_Files = "";
+ }
+ WIZARD_SCRIPT_ARGUMENTS
+ {
+ terminated_ports
+ {
+ }
+ }
+ }
+}
diff --git a/Demo/NiosII_CycloneIII_DBC3C40_GCC/cpu_sim/dummy_file b/Demo/NiosII_CycloneIII_DBC3C40_GCC/cpu_sim/dummy_file
new file mode 100644
index 000000000..e69de29bb
diff --git a/Demo/NiosII_CycloneIII_DBC3C40_GCC/onchip_memory.hex b/Demo/NiosII_CycloneIII_DBC3C40_GCC/onchip_memory.hex
new file mode 100644
index 000000000..e35303dc4
--- /dev/null
+++ b/Demo/NiosII_CycloneIII_DBC3C40_GCC/onchip_memory.hex
@@ -0,0 +1,258 @@
+:020000020000FC
+:200000000000000000000000000000000000000000000000000000000000000000000000E0
+:200008000000000000000000000000000000000000000000000000000000000000000000D8
+:200010000000000000000000000000000000000000000000000000000000000000000000D0
+:200018000000000000000000000000000000000000000000000000000000000000000000C8
+:200020000000000000000000000000000000000000000000000000000000000000000000C0
+:200028000000000000000000000000000000000000000000000000000000000000000000B8
+:200030000000000000000000000000000000000000000000000000000000000000000000B0
+:200038000000000000000000000000000000000000000000000000000000000000000000A8
+:200040000000000000000000000000000000000000000000000000000000000000000000A0
+:20004800000000000000000000000000000000000000000000000000000000000000000098
+:20005000000000000000000000000000000000000000000000000000000000000000000090
+:20005800000000000000000000000000000000000000000000000000000000000000000088
+:20006000000000000000000000000000000000000000000000000000000000000000000080
+:20006800000000000000000000000000000000000000000000000000000000000000000078
+:20007000000000000000000000000000000000000000000000000000000000000000000070
+:20007800000000000000000000000000000000000000000000000000000000000000000068
+:20008000000000000000000000000000000000000000000000000000000000000000000060
+:20008800000000000000000000000000000000000000000000000000000000000000000058
+:20009000000000000000000000000000000000000000000000000000000000000000000050
+:20009800000000000000000000000000000000000000000000000000000000000000000048
+:2000A000000000000000000000000000000000000000000000000000000000000000000040
+:2000A800000000000000000000000000000000000000000000000000000000000000000038
+:2000B000000000000000000000000000000000000000000000000000000000000000000030
+:2000B800000000000000000000000000000000000000000000000000000000000000000028
+:2000C000000000000000000000000000000000000000000000000000000000000000000020
+:2000C800000000000000000000000000000000000000000000000000000000000000000018
+:2000D000000000000000000000000000000000000000000000000000000000000000000010
+:2000D800000000000000000000000000000000000000000000000000000000000000000008
+:2000E000000000000000000000000000000000000000000000000000000000000000000000
+:2000E8000000000000000000000000000000000000000000000000000000000000000000F8
+:2000F0000000000000000000000000000000000000000000000000000000000000000000F0
+:2000F8000000000000000000000000000000000000000000000000000000000000000000E8
+:200100000000000000000000000000000000000000000000000000000000000000000000DF
+:200108000000000000000000000000000000000000000000000000000000000000000000D7
+:200110000000000000000000000000000000000000000000000000000000000000000000CF
+:200118000000000000000000000000000000000000000000000000000000000000000000C7
+:200120000000000000000000000000000000000000000000000000000000000000000000BF
+:200128000000000000000000000000000000000000000000000000000000000000000000B7
+:200130000000000000000000000000000000000000000000000000000000000000000000AF
+:200138000000000000000000000000000000000000000000000000000000000000000000A7
+:2001400000000000000000000000000000000000000000000000000000000000000000009F
+:20014800000000000000000000000000000000000000000000000000000000000000000097
+:2001500000000000000000000000000000000000000000000000000000000000000000008F
+:20015800000000000000000000000000000000000000000000000000000000000000000087
+:2001600000000000000000000000000000000000000000000000000000000000000000007F
+:20016800000000000000000000000000000000000000000000000000000000000000000077
+:2001700000000000000000000000000000000000000000000000000000000000000000006F
+:20017800000000000000000000000000000000000000000000000000000000000000000067
+:2001800000000000000000000000000000000000000000000000000000000000000000005F
+:20018800000000000000000000000000000000000000000000000000000000000000000057
+:2001900000000000000000000000000000000000000000000000000000000000000000004F
+:20019800000000000000000000000000000000000000000000000000000000000000000047
+:2001A00000000000000000000000000000000000000000000000000000000000000000003F
+:2001A800000000000000000000000000000000000000000000000000000000000000000037
+:2001B00000000000000000000000000000000000000000000000000000000000000000002F
+:2001B800000000000000000000000000000000000000000000000000000000000000000027
+:2001C00000000000000000000000000000000000000000000000000000000000000000001F
+:2001C800000000000000000000000000000000000000000000000000000000000000000017
+:2001D00000000000000000000000000000000000000000000000000000000000000000000F
+:2001D800000000000000000000000000000000000000000000000000000000000000000007
+:2001E0000000000000000000000000000000000000000000000000000000000000000000FF
+:2001E8000000000000000000000000000000000000000000000000000000000000000000F7
+:2001F0000000000000000000000000000000000000000000000000000000000000000000EF
+:2001F8000000000000000000000000000000000000000000000000000000000000000000E7
+:200200000000000000000000000000000000000000000000000000000000000000000000DE
+:200208000000000000000000000000000000000000000000000000000000000000000000D6
+:200210000000000000000000000000000000000000000000000000000000000000000000CE
+:200218000000000000000000000000000000000000000000000000000000000000000000C6
+:200220000000000000000000000000000000000000000000000000000000000000000000BE
+:200228000000000000000000000000000000000000000000000000000000000000000000B6
+:200230000000000000000000000000000000000000000000000000000000000000000000AE
+:200238000000000000000000000000000000000000000000000000000000000000000000A6
+:2002400000000000000000000000000000000000000000000000000000000000000000009E
+:20024800000000000000000000000000000000000000000000000000000000000000000096
+:2002500000000000000000000000000000000000000000000000000000000000000000008E
+:20025800000000000000000000000000000000000000000000000000000000000000000086
+:2002600000000000000000000000000000000000000000000000000000000000000000007E
+:20026800000000000000000000000000000000000000000000000000000000000000000076
+:2002700000000000000000000000000000000000000000000000000000000000000000006E
+:20027800000000000000000000000000000000000000000000000000000000000000000066
+:2002800000000000000000000000000000000000000000000000000000000000000000005E
+:20028800000000000000000000000000000000000000000000000000000000000000000056
+:2002900000000000000000000000000000000000000000000000000000000000000000004E
+:20029800000000000000000000000000000000000000000000000000000000000000000046
+:2002A00000000000000000000000000000000000000000000000000000000000000000003E
+:2002A800000000000000000000000000000000000000000000000000000000000000000036
+:2002B00000000000000000000000000000000000000000000000000000000000000000002E
+:2002B800000000000000000000000000000000000000000000000000000000000000000026
+:2002C00000000000000000000000000000000000000000000000000000000000000000001E
+:2002C800000000000000000000000000000000000000000000000000000000000000000016
+:2002D00000000000000000000000000000000000000000000000000000000000000000000E
+:2002D800000000000000000000000000000000000000000000000000000000000000000006
+:2002E0000000000000000000000000000000000000000000000000000000000000000000FE
+:2002E8000000000000000000000000000000000000000000000000000000000000000000F6
+:2002F0000000000000000000000000000000000000000000000000000000000000000000EE
+:2002F8000000000000000000000000000000000000000000000000000000000000000000E6
+:200300000000000000000000000000000000000000000000000000000000000000000000DD
+:200308000000000000000000000000000000000000000000000000000000000000000000D5
+:200310000000000000000000000000000000000000000000000000000000000000000000CD
+:200318000000000000000000000000000000000000000000000000000000000000000000C5
+:200320000000000000000000000000000000000000000000000000000000000000000000BD
+:200328000000000000000000000000000000000000000000000000000000000000000000B5
+:200330000000000000000000000000000000000000000000000000000000000000000000AD
+:200338000000000000000000000000000000000000000000000000000000000000000000A5
+:2003400000000000000000000000000000000000000000000000000000000000000000009D
+:20034800000000000000000000000000000000000000000000000000000000000000000095
+:2003500000000000000000000000000000000000000000000000000000000000000000008D
+:20035800000000000000000000000000000000000000000000000000000000000000000085
+:2003600000000000000000000000000000000000000000000000000000000000000000007D
+:20036800000000000000000000000000000000000000000000000000000000000000000075
+:2003700000000000000000000000000000000000000000000000000000000000000000006D
+:20037800000000000000000000000000000000000000000000000000000000000000000065
+:2003800000000000000000000000000000000000000000000000000000000000000000005D
+:20038800000000000000000000000000000000000000000000000000000000000000000055
+:2003900000000000000000000000000000000000000000000000000000000000000000004D
+:20039800000000000000000000000000000000000000000000000000000000000000000045
+:2003A00000000000000000000000000000000000000000000000000000000000000000003D
+:2003A800000000000000000000000000000000000000000000000000000000000000000035
+:2003B00000000000000000000000000000000000000000000000000000000000000000002D
+:2003B800000000000000000000000000000000000000000000000000000000000000000025
+:2003C00000000000000000000000000000000000000000000000000000000000000000001D
+:2003C800000000000000000000000000000000000000000000000000000000000000000015
+:2003D00000000000000000000000000000000000000000000000000000000000000000000D
+:2003D800000000000000000000000000000000000000000000000000000000000000000005
+:2003E0000000000000000000000000000000000000000000000000000000000000000000FD
+:2003E8000000000000000000000000000000000000000000000000000000000000000000F5
+:2003F0000000000000000000000000000000000000000000000000000000000000000000ED
+:2003F8000000000000000000000000000000000000000000000000000000000000000000E5
+:200400000000000000000000000000000000000000000000000000000000000000000000DC
+:200408000000000000000000000000000000000000000000000000000000000000000000D4
+:200410000000000000000000000000000000000000000000000000000000000000000000CC
+:200418000000000000000000000000000000000000000000000000000000000000000000C4
+:200420000000000000000000000000000000000000000000000000000000000000000000BC
+:200428000000000000000000000000000000000000000000000000000000000000000000B4
+:200430000000000000000000000000000000000000000000000000000000000000000000AC
+:200438000000000000000000000000000000000000000000000000000000000000000000A4
+:2004400000000000000000000000000000000000000000000000000000000000000000009C
+:20044800000000000000000000000000000000000000000000000000000000000000000094
+:2004500000000000000000000000000000000000000000000000000000000000000000008C
+:20045800000000000000000000000000000000000000000000000000000000000000000084
+:2004600000000000000000000000000000000000000000000000000000000000000000007C
+:20046800000000000000000000000000000000000000000000000000000000000000000074
+:2004700000000000000000000000000000000000000000000000000000000000000000006C
+:20047800000000000000000000000000000000000000000000000000000000000000000064
+:2004800000000000000000000000000000000000000000000000000000000000000000005C
+:20048800000000000000000000000000000000000000000000000000000000000000000054
+:2004900000000000000000000000000000000000000000000000000000000000000000004C
+:20049800000000000000000000000000000000000000000000000000000000000000000044
+:2004A00000000000000000000000000000000000000000000000000000000000000000003C
+:2004A800000000000000000000000000000000000000000000000000000000000000000034
+:2004B00000000000000000000000000000000000000000000000000000000000000000002C
+:2004B800000000000000000000000000000000000000000000000000000000000000000024
+:2004C00000000000000000000000000000000000000000000000000000000000000000001C
+:2004C800000000000000000000000000000000000000000000000000000000000000000014
+:2004D00000000000000000000000000000000000000000000000000000000000000000000C
+:2004D800000000000000000000000000000000000000000000000000000000000000000004
+:2004E0000000000000000000000000000000000000000000000000000000000000000000FC
+:2004E8000000000000000000000000000000000000000000000000000000000000000000F4
+:2004F0000000000000000000000000000000000000000000000000000000000000000000EC
+:2004F8000000000000000000000000000000000000000000000000000000000000000000E4
+:200500000000000000000000000000000000000000000000000000000000000000000000DB
+:200508000000000000000000000000000000000000000000000000000000000000000000D3
+:200510000000000000000000000000000000000000000000000000000000000000000000CB
+:200518000000000000000000000000000000000000000000000000000000000000000000C3
+:200520000000000000000000000000000000000000000000000000000000000000000000BB
+:200528000000000000000000000000000000000000000000000000000000000000000000B3
+:200530000000000000000000000000000000000000000000000000000000000000000000AB
+:200538000000000000000000000000000000000000000000000000000000000000000000A3
+:2005400000000000000000000000000000000000000000000000000000000000000000009B
+:20054800000000000000000000000000000000000000000000000000000000000000000093
+:2005500000000000000000000000000000000000000000000000000000000000000000008B
+:20055800000000000000000000000000000000000000000000000000000000000000000083
+:2005600000000000000000000000000000000000000000000000000000000000000000007B
+:20056800000000000000000000000000000000000000000000000000000000000000000073
+:2005700000000000000000000000000000000000000000000000000000000000000000006B
+:20057800000000000000000000000000000000000000000000000000000000000000000063
+:2005800000000000000000000000000000000000000000000000000000000000000000005B
+:20058800000000000000000000000000000000000000000000000000000000000000000053
+:2005900000000000000000000000000000000000000000000000000000000000000000004B
+:20059800000000000000000000000000000000000000000000000000000000000000000043
+:2005A00000000000000000000000000000000000000000000000000000000000000000003B
+:2005A800000000000000000000000000000000000000000000000000000000000000000033
+:2005B00000000000000000000000000000000000000000000000000000000000000000002B
+:2005B800000000000000000000000000000000000000000000000000000000000000000023
+:2005C00000000000000000000000000000000000000000000000000000000000000000001B
+:2005C800000000000000000000000000000000000000000000000000000000000000000013
+:2005D00000000000000000000000000000000000000000000000000000000000000000000B
+:2005D800000000000000000000000000000000000000000000000000000000000000000003
+:2005E0000000000000000000000000000000000000000000000000000000000000000000FB
+:2005E8000000000000000000000000000000000000000000000000000000000000000000F3
+:2005F0000000000000000000000000000000000000000000000000000000000000000000EB
+:2005F8000000000000000000000000000000000000000000000000000000000000000000E3
+:200600000000000000000000000000000000000000000000000000000000000000000000DA
+:200608000000000000000000000000000000000000000000000000000000000000000000D2
+:200610000000000000000000000000000000000000000000000000000000000000000000CA
+:200618000000000000000000000000000000000000000000000000000000000000000000C2
+:200620000000000000000000000000000000000000000000000000000000000000000000BA
+:200628000000000000000000000000000000000000000000000000000000000000000000B2
+:200630000000000000000000000000000000000000000000000000000000000000000000AA
+:200638000000000000000000000000000000000000000000000000000000000000000000A2
+:2006400000000000000000000000000000000000000000000000000000000000000000009A
+:20064800000000000000000000000000000000000000000000000000000000000000000092
+:2006500000000000000000000000000000000000000000000000000000000000000000008A
+:20065800000000000000000000000000000000000000000000000000000000000000000082
+:2006600000000000000000000000000000000000000000000000000000000000000000007A
+:20066800000000000000000000000000000000000000000000000000000000000000000072
+:2006700000000000000000000000000000000000000000000000000000000000000000006A
+:20067800000000000000000000000000000000000000000000000000000000000000000062
+:2006800000000000000000000000000000000000000000000000000000000000000000005A
+:20068800000000000000000000000000000000000000000000000000000000000000000052
+:2006900000000000000000000000000000000000000000000000000000000000000000004A
+:20069800000000000000000000000000000000000000000000000000000000000000000042
+:2006A00000000000000000000000000000000000000000000000000000000000000000003A
+:2006A800000000000000000000000000000000000000000000000000000000000000000032
+:2006B00000000000000000000000000000000000000000000000000000000000000000002A
+:2006B800000000000000000000000000000000000000000000000000000000000000000022
+:2006C00000000000000000000000000000000000000000000000000000000000000000001A
+:2006C800000000000000000000000000000000000000000000000000000000000000000012
+:2006D00000000000000000000000000000000000000000000000000000000000000000000A
+:2006D800000000000000000000000000000000000000000000000000000000000000000002
+:2006E0000000000000000000000000000000000000000000000000000000000000000000FA
+:2006E8000000000000000000000000000000000000000000000000000000000000000000F2
+:2006F0000000000000000000000000000000000000000000000000000000000000000000EA
+:2006F8000000000000000000000000000000000000000000000000000000000000000000E2
+:200700000000000000000000000000000000000000000000000000000000000000000000D9
+:200708000000000000000000000000000000000000000000000000000000000000000000D1
+:200710000000000000000000000000000000000000000000000000000000000000000000C9
+:200718000000000000000000000000000000000000000000000000000000000000000000C1
+:200720000000000000000000000000000000000000000000000000000000000000000000B9
+:200728000000000000000000000000000000000000000000000000000000000000000000B1
+:200730000000000000000000000000000000000000000000000000000000000000000000A9
+:200738000000000000000000000000000000000000000000000000000000000000000000A1
+:20074000000000000000000000000000000000000000000000000000000000000000000099
+:20074800000000000000000000000000000000000000000000000000000000000000000091
+:20075000000000000000000000000000000000000000000000000000000000000000000089
+:20075800000000000000000000000000000000000000000000000000000000000000000081
+:20076000000000000000000000000000000000000000000000000000000000000000000079
+:20076800000000000000000000000000000000000000000000000000000000000000000071
+:20077000000000000000000000000000000000000000000000000000000000000000000069
+:20077800000000000000000000000000000000000000000000000000000000000000000061
+:20078000000000000000000000000000000000000000000000000000000000000000000059
+:20078800000000000000000000000000000000000000000000000000000000000000000051
+:20079000000000000000000000000000000000000000000000000000000000000000000049
+:20079800000000000000000000000000000000000000000000000000000000000000000041
+:2007A000000000000000000000000000000000000000000000000000000000000000000039
+:2007A800000000000000000000000000000000000000000000000000000000000000000031
+:2007B000000000000000000000000000000000000000000000000000000000000000000029
+:2007B800000000000000000000000000000000000000000000000000000000000000000021
+:2007C000000000000000000000000000000000000000000000000000000000000000000019
+:2007C800000000000000000000000000000000000000000000000000000000000000000011
+:2007D000000000000000000000000000000000000000000000000000000000000000000009
+:2007D800000000000000000000000000000000000000000000000000000000000000000001
+:2007E0000000000000000000000000000000000000000000000000000000000000000000F9
+:2007E8000000000000000000000000000000000000000000000000000000000000000000F1
+:2007F0000000000000000000000000000000000000000000000000000000000000000000E9
+:2007F8000000000000000000000000000000000000000000000000000000000000000000E1
+:00000001FF
diff --git a/Demo/NiosII_CycloneIII_DBC3C40_GCC/sopc_builder_log.txt b/Demo/NiosII_CycloneIII_DBC3C40_GCC/sopc_builder_log.txt
new file mode 100644
index 000000000..7720757e4
--- /dev/null
+++ b/Demo/NiosII_CycloneIII_DBC3C40_GCC/sopc_builder_log.txt
@@ -0,0 +1 @@
+"c:/devtools/altera/90sp2/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/devtools/altera/90sp2/quartus/sopc_builder/bin/sopc_builder.jar;c:/devtools/altera/90sp2/quartus/sopc_builder/bin/PinAssigner.jar;c:/devtools/altera/90sp2/quartus/sopc_builder/bin/sopc_wizard.jar;c:/devtools/altera/90sp2/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/devtools/altera/90sp2/quartus/sopc_builder" -notalkback=1 -projectname -projectpathC:/E/Dev/FreeRTOS/WorkingCopy3/Demo/NiosII_CycloneIII_DBC3C40_GCC --no_splash --update_classes_and_exit --quartus_dir="c:/devtools/altera/90sp2/quartus" --sopc_perl="c:/devtools/altera/90sp2/quartus/bin/perl" --sopc_lib_path="c:\E\Dev\FreeRTOS\WorkingCopy3\Demo\NiosII_CycloneIII_DBC3C40_GCC+C:\devtools\altera\90\nios2eds\bin;+C:\devtools\altera\90sp2\ip\altera\asi\lib\ip_toolbench+C:\devtools\altera\90sp2\quartus\common\librarian\factories+Q:\quartus\cusp\bin+Q:\quartus\dsp_builder\bin+Q:\quartus\dsp_builder\bin\extlibs+C:\devtools\altera\90sp2\ip\altera\clipper\lib+C:\tools\altera\9.0\132\linux32\quartus\cusp\include+C:\tools\altera\9.0\132\linux32\quartus\cusp\include\cusp+C:\tools\altera\9.0\132\linux32\quartus\cusp\include\cusp\fuLib+C:\tools\altera\9.0\132\linux32\quartus\cusp\include\cusp\simlib+C:\tools\altera\9.0\132\linux32\quartus\cusp\synthinclude+C:\tools\altera\9.0\132\linux32\quartus\cusp\synthinclude\stlport+C:\tools\altera\9.0\132\linux32\quartus\cusp\synthinclude\stlport\config+C:\tools\altera\9.0\132\linux32\quartus\cusp\synthinclude\stlport\stl+C:\tools\altera\9.0\132\linux32\quartus\cusp\synthinclude\stlport\using+C:\tools\altera\9.0\132\linux32\quartus\cusp\synthinclude\stlport\wrap_std+C:\tools\altera\9.0\132\linux32\quartus\cusp\systemc\include\sysc\communication+C:\tools\altera\9.0\132\linux32\quartus\cusp\systemc\include\sysc\datatypes\bit+C:\tools\altera\9.0\132\linux32\quartus\cusp\systemc\include\sysc\datatypes\fx+C:\tools\altera\9.0\132\linux32\quartus\cusp\systemc\include\sysc\datatypes\int+C:\tools\altera\9.0\132\linux32\quartus\cusp\systemc\include\sysc\datatypes\misc+C:\tools\altera\9.0\132\linux32\quartus\cusp\systemc\include\sysc\kernel+C:\tools\altera\9.0\132\linux32\quartus\cusp\systemc\include\sysc\tracing+C:\tools\altera\9.0\132\linux32\quartus\cusp\systemc\include\sysc\utils+C:\tools\altera\9.0\132\linux32\quartus\cusp\systemc\include+C:\devtools\altera\90sp2\ip\altera\clipper\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\color_plane_sequencer\lib+C:\devtools\altera\90sp2\ip\altera\color_plane_sequencer\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\chroma_resampler\lib+C:\devtools\altera\90sp2\ip\altera\chroma_resampler\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\csc\lib+C:\devtools\altera\90sp2\ip\altera\csc\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\clocked_video_input\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\deinterlacer\lib+C:\devtools\altera\90sp2\ip\altera\deinterlacer\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\fir_filter_2d\lib+C:\devtools\altera\90sp2\ip\altera\fir_filter_2d\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\gamma_corrector\lib+C:\devtools\altera\90sp2\ip\altera\gamma_corrector\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\clocked_video_output\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\line_buffer_compiler\lib+C:\devtools\altera\90sp2\ip\altera\line_buffer_compiler\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\median_filter_2d\lib+C:\devtools\altera\90sp2\ip\altera\median_filter_2d\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\alpha_blending_mixer\lib+C:\devtools\altera\90sp2\ip\altera\alpha_blending_mixer\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\scaler\lib+C:\devtools\altera\90sp2\ip\altera\scaler\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\test_pattern_generator\lib+C:\devtools\altera\90sp2\ip\altera\test_pattern_generator\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\frame_buffer\lib+C:\devtools\altera\90sp2\ip\altera\frame_buffer\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip+C:\devtools\altera\90sp2\quartus\sopc_builder\model\lib+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_cf+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_cfi_flash+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_dc_fifo+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_dma+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_epcs_flash_controller+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_fifo+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_half_rate_bridge+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_jtag_uart+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_lan91c111+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_lcd_16207+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_mailbox+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_multi_channel_shared_fifo+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_mutex+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_packets_to_master+C:\devtools\altera\90sp2\ip\altera\pci_compiler\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\pci_compiler\lib\sopc_builder+C:\devtools\altera\90sp2\ip\altera\pci_express_compiler\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\pci_express_compiler\lib\sopc_builder+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_performance_counter+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_pio+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_pixel_converter+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_remote_update_cycloneiii+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_round_robin_scheduler+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_sc_fifo+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_sgdma+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_spi+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_st_bytes_to_packets+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_st_idle_inserter+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_st_idle_remover+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_st_packets_to_bytes+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_sysid+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_timer+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_uart+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_video_sync_generator+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_jtag_avalon_master+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_jtag_phy+C:\devtools\altera\90sp2\ip\altera\nios2_ip\altera_nios2+C:\devtools\altera\90sp2\ip\altera\nios2_ip+C:\devtools\altera\90sp2\ip\altera\ddr_high_perf\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\ddr_high_perf\lib\sopc_builder+C:\devtools\altera\90sp2\ip\altera\ddr2_high_perf\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\ddr2_high_perf\lib\sopc_builder+C:\devtools\altera\90sp2\ip\altera\ddr3_high_perf\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\ddr3_high_perf\lib\sopc_builder+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_altpll+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\verification\avalon_mm_bfm\avalon_mm_master_bfm+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\verification\avalon_mm_bfm\avalon_mm_slave_bfm+C:\devtools\altera\90sp2\ip\altera\crc_compiler\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_data_sink+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_data_source+C:\devtools\altera\90sp2\ip\altera\ddr_ddr2_sdram\lib\sopc_builder+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_pci_lite+C:\devtools\altera\90sp2\ip\altera\rapidio\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\sdi\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\sls\usb20hr_ocp_eval_pack\hardware\component+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_spislave_to_avalonmm_bridge+C:\devtools\altera\90sp2\ip\altera\sopc_builder_ip\altera_avalon_spi_phy_slave+C:\devtools\altera\90sp2\ip\altera\triple_speed_ethernet\lib\ip_toolbench+C:\devtools\altera\90sp2\ip\altera\triple_speed_ethernet\lib\sopc_builder+C:\devtools\altera\90sp2\ip\altera\triple_speed_ethernet\lib\sopc_builder\altera_triple_speed_ethernet++c:/devtools/altera/90sp2/quartus/../ip/altera/sopc_builder_ip+c:/devtools/altera/90sp2/quartus/../ip/altera/nios2_ip"