From 4d9cd906d3f7c339ee3d6d64a00c416d58a8b003 Mon Sep 17 00:00:00 2001 From: Jonathan Cubides <92931721+cubidesj@users.noreply.github.com> Date: Thu, 6 Mar 2025 19:34:48 +0100 Subject: [PATCH] RISCV Add FPU context save (#1250) * port: riscv: Split the number of registers and the size of the context * port: riscv: Create some macros for the FPU context * port: riscv: Add a couple of macros that store fpu context * port: riscv: Update the stack init function to include the fpu context size * port: riscv: Add a chip_specific_extensions file that includes the F extension * Update dictionary to include some risc-v instructions * port: riscv: Fix a few typos * port: riscv: Apply @aggarg's sugestions --- .github/.cSpellWords.txt | 3 + ...freertos_risc_v_chip_specific_extensions.h | 24 +- portable/GCC/RISC-V/portASM.S | 96 +++--- portable/GCC/RISC-V/portContext.h | 287 +++++++++++++----- 4 files changed, 287 insertions(+), 123 deletions(-) diff --git a/.github/.cSpellWords.txt b/.github/.cSpellWords.txt index 3582741e3..27fb0fc33 100644 --- a/.github/.cSpellWords.txt +++ b/.github/.cSpellWords.txt @@ -23,6 +23,7 @@ AIRCR ALMIEN ALMV ANDC +andi ANDCCR APIC APROCFREQ @@ -47,6 +48,7 @@ bcpc BCPC beevt BEEVT +beqz BERR bfextu Biagioni @@ -298,6 +300,7 @@ FADD FCMD fcolor FCSE +fcsr fdiagnostics fdiv FDIV diff --git a/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h b/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h index 4d8a5fb53..c10869eb4 100644 --- a/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h +++ b/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h @@ -80,22 +80,22 @@ csrr t2, lpcount0 csrr t3, lpstart1 csrr t4, lpend1 csrr t5, lpcount1 -sw t0, 1 * portWORD_SIZE( sp ) -sw t1, 2 * portWORD_SIZE( sp ) -sw t2, 3 * portWORD_SIZE( sp ) -sw t3, 4 * portWORD_SIZE( sp ) -sw t4, 5 * portWORD_SIZE( sp ) -sw t5, 6 * portWORD_SIZE( sp ) +sw t0, 2 * portWORD_SIZE( sp ) +sw t1, 3 * portWORD_SIZE( sp ) +sw t2, 4 * portWORD_SIZE( sp ) +sw t3, 5 * portWORD_SIZE( sp ) +sw t4, 6 * portWORD_SIZE( sp ) +sw t5, 7 * portWORD_SIZE( sp ) .endm /* Restore the additional registers found on the Pulpino. */ .macro portasmRESTORE_ADDITIONAL_REGISTERS -lw t0, 1 * portWORD_SIZE( sp ) /* Load additional registers into accessible temporary registers. */ -lw t1, 2 * portWORD_SIZE( sp ) -lw t2, 3 * portWORD_SIZE( sp ) -lw t3, 4 * portWORD_SIZE( sp ) -lw t4, 5 * portWORD_SIZE( sp ) -lw t5, 6 * portWORD_SIZE( sp ) +lw t0, 2 * portWORD_SIZE( sp ) /* Load additional registers into accessible temporary registers. */ +lw t1, 3 * portWORD_SIZE( sp ) +lw t2, 4 * portWORD_SIZE( sp ) +lw t3, 5 * portWORD_SIZE( sp ) +lw t4, 6 * portWORD_SIZE( sp ) +lw t5, 7 * portWORD_SIZE( sp ) csrw lpstart0, t0 csrw lpend0, t1 csrw lpcount0, t2 diff --git a/portable/GCC/RISC-V/portASM.S b/portable/GCC/RISC-V/portASM.S index 99613ada6..1fe50f67c 100644 --- a/portable/GCC/RISC-V/portASM.S +++ b/portable/GCC/RISC-V/portASM.S @@ -162,7 +162,6 @@ definitions. */ * where the global and thread pointers are currently assumed to be constant so * are not saved: * - * mstatus * xCriticalNesting * x31 * x30 @@ -192,18 +191,12 @@ definitions. */ * x6 * x5 * portTASK_RETURN_ADDRESS + * [FPU registers (when enabled/available) go here] * [chip specific registers go here] + * mstatus * pxCode */ pxPortInitialiseStack: - csrr t0, mstatus /* Obtain current mstatus value. */ - andi t0, t0, ~0x8 /* Ensure interrupts are disabled when the stack is restored within an ISR. Required when a task is created after the schedulre has been started, otherwise interrupts would be disabled anyway. */ - addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */ - slli t1, t1, 4 - or t0, t0, t1 /* Set MPIE and MPP bits in mstatus value. */ - - addi a0, a0, -portWORD_SIZE - store_x t0, 0(a0) /* mstatus onto the stack. */ addi a0, a0, -portWORD_SIZE /* Space for critical nesting count. */ store_x x0, 0(a0) /* Critical nesting count starts at 0 for every task. */ @@ -212,10 +205,12 @@ pxPortInitialiseStack: #else addi a0, a0, -(22 * portWORD_SIZE) /* Space for registers x10-x31. */ #endif - store_x a2, 0(a0) /* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */ - addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9 + taskReturnAddress. */ + store_x a2, 0(a0) /* Task parameters (pvParameters parameter) goes into register x10/a0 on the stack. */ + + addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9 + taskReturnAddress (register x1). */ load_x t0, xTaskReturnAddress store_x t0, 0(a0) /* Return address onto the stack. */ + addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */ chip_specific_stack_frame: /* First add any chip specific registers to the stack frame being created. */ beq t0, x0, 1f /* No more chip specific registers to save. */ @@ -224,6 +219,23 @@ chip_specific_stack_frame: /* First add any chip specific registers addi t0, t0, -1 /* Decrement the count of chip specific registers remaining. */ j chip_specific_stack_frame /* Until no more chip specific registers. */ 1: + csrr t0, mstatus /* Obtain current mstatus value. */ + andi t0, t0, ~0x8 /* Ensure interrupts are disabled when the stack is restored within an ISR. Required when a task is created after the scheduler has been started, otherwise interrupts would be disabled anyway. */ + addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE=1 and MPP=M_Mode in mstatus. */ + slli t1, t1, 4 + or t0, t0, t1 /* Set MPIE and MPP bits in mstatus value. */ + +#if( configENABLE_FPU == 1 ) + /* Mark the FPU as clean in the mstatus value. */ + li t1, ~MSTATUS_FS_MASK + and t0, t0, t1 + li t1, MSTATUS_FS_CLEAN + or t0, t0, t1 +#endif + + addi a0, a0, -portWORD_SIZE + store_x t0, 0(a0) /* mstatus onto the stack. */ + addi a0, a0, -portWORD_SIZE store_x a1, 0(a0) /* mret value (pxCode parameter) onto the stack. */ ret @@ -235,46 +247,46 @@ xPortStartFirstTask: load_x x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */ + load_x x5, 1 * portWORD_SIZE( sp ) /* Initial mstatus into x5 (t0). */ + addi x5, x5, 0x08 /* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */ + csrw mstatus, x5 /* Interrupts enabled from here! */ + portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */ - load_x x7, 4 * portWORD_SIZE( sp ) /* t2 */ - load_x x8, 5 * portWORD_SIZE( sp ) /* s0/fp */ - load_x x9, 6 * portWORD_SIZE( sp ) /* s1 */ - load_x x10, 7 * portWORD_SIZE( sp ) /* a0 */ - load_x x11, 8 * portWORD_SIZE( sp ) /* a1 */ - load_x x12, 9 * portWORD_SIZE( sp ) /* a2 */ - load_x x13, 10 * portWORD_SIZE( sp ) /* a3 */ - load_x x14, 11 * portWORD_SIZE( sp ) /* a4 */ - load_x x15, 12 * portWORD_SIZE( sp ) /* a5 */ + load_x x7, 5 * portWORD_SIZE( sp ) /* t2 */ + load_x x8, 6 * portWORD_SIZE( sp ) /* s0/fp */ + load_x x9, 7 * portWORD_SIZE( sp ) /* s1 */ + load_x x10, 8 * portWORD_SIZE( sp ) /* a0 */ + load_x x11, 9 * portWORD_SIZE( sp ) /* a1 */ + load_x x12, 10 * portWORD_SIZE( sp ) /* a2 */ + load_x x13, 11 * portWORD_SIZE( sp ) /* a3 */ + load_x x14, 12 * portWORD_SIZE( sp ) /* a4 */ + load_x x15, 13 * portWORD_SIZE( sp ) /* a5 */ #ifndef __riscv_32e - load_x x16, 13 * portWORD_SIZE( sp ) /* a6 */ - load_x x17, 14 * portWORD_SIZE( sp ) /* a7 */ - load_x x18, 15 * portWORD_SIZE( sp ) /* s2 */ - load_x x19, 16 * portWORD_SIZE( sp ) /* s3 */ - load_x x20, 17 * portWORD_SIZE( sp ) /* s4 */ - load_x x21, 18 * portWORD_SIZE( sp ) /* s5 */ - load_x x22, 19 * portWORD_SIZE( sp ) /* s6 */ - load_x x23, 20 * portWORD_SIZE( sp ) /* s7 */ - load_x x24, 21 * portWORD_SIZE( sp ) /* s8 */ - load_x x25, 22 * portWORD_SIZE( sp ) /* s9 */ - load_x x26, 23 * portWORD_SIZE( sp ) /* s10 */ - load_x x27, 24 * portWORD_SIZE( sp ) /* s11 */ - load_x x28, 25 * portWORD_SIZE( sp ) /* t3 */ - load_x x29, 26 * portWORD_SIZE( sp ) /* t4 */ - load_x x30, 27 * portWORD_SIZE( sp ) /* t5 */ - load_x x31, 28 * portWORD_SIZE( sp ) /* t6 */ + load_x x16, 14 * portWORD_SIZE( sp ) /* a6 */ + load_x x17, 15 * portWORD_SIZE( sp ) /* a7 */ + load_x x18, 16 * portWORD_SIZE( sp ) /* s2 */ + load_x x19, 17 * portWORD_SIZE( sp ) /* s3 */ + load_x x20, 18 * portWORD_SIZE( sp ) /* s4 */ + load_x x21, 19 * portWORD_SIZE( sp ) /* s5 */ + load_x x22, 20 * portWORD_SIZE( sp ) /* s6 */ + load_x x23, 21 * portWORD_SIZE( sp ) /* s7 */ + load_x x24, 22 * portWORD_SIZE( sp ) /* s8 */ + load_x x25, 23 * portWORD_SIZE( sp ) /* s9 */ + load_x x26, 24 * portWORD_SIZE( sp ) /* s10 */ + load_x x27, 25 * portWORD_SIZE( sp ) /* s11 */ + load_x x28, 26 * portWORD_SIZE( sp ) /* t3 */ + load_x x29, 27 * portWORD_SIZE( sp ) /* t4 */ + load_x x30, 28 * portWORD_SIZE( sp ) /* t5 */ + load_x x31, 29 * portWORD_SIZE( sp ) /* t6 */ #endif load_x x5, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */ load_x x6, pxCriticalNesting /* Load the address of xCriticalNesting into x6. */ store_x x5, 0( x6 ) /* Restore the critical nesting value for this task. */ - load_x x5, portMSTATUS_OFFSET * portWORD_SIZE( sp ) /* Initial mstatus into x5 (t0). */ - addi x5, x5, 0x08 /* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */ - csrrw x0, mstatus, x5 /* Interrupts enabled from here! */ - - load_x x5, 2 * portWORD_SIZE( sp ) /* Initial x5 (t0) value. */ - load_x x6, 3 * portWORD_SIZE( sp ) /* Initial x6 (t1) value. */ + load_x x5, 3 * portWORD_SIZE( sp ) /* Initial x5 (t0) value. */ + load_x x6, 4 * portWORD_SIZE( sp ) /* Initial x6 (t1) value. */ addi sp, sp, portCONTEXT_SIZE ret diff --git a/portable/GCC/RISC-V/portContext.h b/portable/GCC/RISC-V/portContext.h index 6baae753d..9afe6eef3 100644 --- a/portable/GCC/RISC-V/portContext.h +++ b/portable/GCC/RISC-V/portContext.h @@ -29,6 +29,10 @@ #ifndef PORTCONTEXT_H #define PORTCONTEXT_H +#ifndef configENABLE_FPU + #define configENABLE_FPU 0 +#endif + #if __riscv_xlen == 64 #define portWORD_SIZE 8 #define store_x sd @@ -50,65 +54,199 @@ * notes at the top of portASM.S file. */ #ifdef __riscv_32e #define portCONTEXT_SIZE ( 15 * portWORD_SIZE ) - #define portCRITICAL_NESTING_OFFSET 13 - #define portMSTATUS_OFFSET 14 + #define portCRITICAL_NESTING_OFFSET 14 #else #define portCONTEXT_SIZE ( 31 * portWORD_SIZE ) - #define portCRITICAL_NESTING_OFFSET 29 - #define portMSTATUS_OFFSET 30 + #define portCRITICAL_NESTING_OFFSET 30 #endif +#if ( configENABLE_FPU == 1 ) + /* Bit [14:13] in the mstatus encode the status of FPU state which is one of + * the following values: + * 1. Value: 0, Meaning: Off. + * 2. Value: 1, Meaning: Initial. + * 3. Value: 2, Meaning: Clean. + * 4. Value: 3, Meaning: Dirty. + */ + #define MSTATUS_FS_MASK 0x6000 + #define MSTATUS_FS_INITIAL 0x2000 + #define MSTATUS_FS_CLEAN 0x4000 + #define MSTATUS_FS_DIRTY 0x6000 + #define MSTATUS_FS_OFFSET 13 + + #ifdef __riscv_fdiv + #if __riscv_flen == 32 + #define load_f flw + #define store_f fsw + #elif __riscv_flen == 64 + #define load_f fld + #define store_f fsd + #else + #error Assembler did not define __riscv_flen + #endif + + #define portFPU_REG_SIZE ( __riscv_flen / 8 ) + #define portFPU_REG_COUNT 33 /* 32 Floating point registers plus one CSR. */ + #define portFPU_CONTEXT_SIZE ( portFPU_REG_SIZE * portFPU_REG_COUNT ) + #else + #error configENABLE_FPU must not be set to 1 if the hardwar does not have FPU + #endif +#endif /*-----------------------------------------------------------*/ .extern pxCurrentTCB - .extern xISRStackTop - .extern xCriticalNesting - .extern pxCriticalNesting +.extern xISRStackTop +.extern xCriticalNesting +.extern pxCriticalNesting +/*-----------------------------------------------------------*/ + + .macro portcontexSAVE_FPU_CONTEXT +addi sp, sp, -( portFPU_CONTEXT_SIZE ) +/* Store the FPU registers. */ +store_f f0, 2 * portWORD_SIZE( sp ) +store_f f1, 3 * portWORD_SIZE( sp ) +store_f f2, 4 * portWORD_SIZE( sp ) +store_f f3, 5 * portWORD_SIZE( sp ) +store_f f4, 6 * portWORD_SIZE( sp ) +store_f f5, 7 * portWORD_SIZE( sp ) +store_f f6, 8 * portWORD_SIZE( sp ) +store_f f7, 9 * portWORD_SIZE( sp ) +store_f f8, 10 * portWORD_SIZE( sp ) +store_f f9, 11 * portWORD_SIZE( sp ) +store_f f10, 12 * portWORD_SIZE( sp ) +store_f f11, 13 * portWORD_SIZE( sp ) +store_f f12, 14 * portWORD_SIZE( sp ) +store_f f13, 15 * portWORD_SIZE( sp ) +store_f f14, 16 * portWORD_SIZE( sp ) +store_f f15, 17 * portWORD_SIZE( sp ) +store_f f16, 18 * portWORD_SIZE( sp ) +store_f f17, 19 * portWORD_SIZE( sp ) +store_f f18, 20 * portWORD_SIZE( sp ) +store_f f19, 21 * portWORD_SIZE( sp ) +store_f f20, 22 * portWORD_SIZE( sp ) +store_f f21, 23 * portWORD_SIZE( sp ) +store_f f22, 24 * portWORD_SIZE( sp ) +store_f f23, 25 * portWORD_SIZE( sp ) +store_f f24, 26 * portWORD_SIZE( sp ) +store_f f25, 27 * portWORD_SIZE( sp ) +store_f f26, 28 * portWORD_SIZE( sp ) +store_f f27, 29 * portWORD_SIZE( sp ) +store_f f28, 30 * portWORD_SIZE( sp ) +store_f f29, 31 * portWORD_SIZE( sp ) +store_f f30, 32 * portWORD_SIZE( sp ) +store_f f31, 33 * portWORD_SIZE( sp ) +csrr t0, fcsr +store_x t0, 34 * portWORD_SIZE( sp ) + .endm +/*-----------------------------------------------------------*/ + + .macro portcontextRESTORE_FPU_CONTEXT +/* Restore the FPU registers. */ +load_f f0, 2 * portWORD_SIZE( sp ) +load_f f1, 3 * portWORD_SIZE( sp ) +load_f f2, 4 * portWORD_SIZE( sp ) +load_f f3, 5 * portWORD_SIZE( sp ) +load_f f4, 6 * portWORD_SIZE( sp ) +load_f f5, 7 * portWORD_SIZE( sp ) +load_f f6, 8 * portWORD_SIZE( sp ) +load_f f7, 9 * portWORD_SIZE( sp ) +load_f f8, 10 * portWORD_SIZE( sp ) +load_f f9, 11 * portWORD_SIZE( sp ) +load_f f10, 12 * portWORD_SIZE( sp ) +load_f f11, 13 * portWORD_SIZE( sp ) +load_f f12, 14 * portWORD_SIZE( sp ) +load_f f13, 15 * portWORD_SIZE( sp ) +load_f f14, 16 * portWORD_SIZE( sp ) +load_f f15, 17 * portWORD_SIZE( sp ) +load_f f16, 18 * portWORD_SIZE( sp ) +load_f f17, 19 * portWORD_SIZE( sp ) +load_f f18, 20 * portWORD_SIZE( sp ) +load_f f19, 21 * portWORD_SIZE( sp ) +load_f f20, 22 * portWORD_SIZE( sp ) +load_f f21, 23 * portWORD_SIZE( sp ) +load_f f22, 24 * portWORD_SIZE( sp ) +load_f f23, 25 * portWORD_SIZE( sp ) +load_f f24, 26 * portWORD_SIZE( sp ) +load_f f25, 27 * portWORD_SIZE( sp ) +load_f f26, 28 * portWORD_SIZE( sp ) +load_f f27, 29 * portWORD_SIZE( sp ) +load_f f28, 30 * portWORD_SIZE( sp ) +load_f f29, 31 * portWORD_SIZE( sp ) +load_f f30, 32 * portWORD_SIZE( sp ) +load_f f31, 33 * portWORD_SIZE( sp ) +load_x t0, 34 * portWORD_SIZE( sp ) +csrw fcsr, t0 +addi sp, sp, ( portFPU_CONTEXT_SIZE ) + .endm /*-----------------------------------------------------------*/ .macro portcontextSAVE_CONTEXT_INTERNAL addi sp, sp, -portCONTEXT_SIZE -store_x x1, 1 * portWORD_SIZE( sp ) -store_x x5, 2 * portWORD_SIZE( sp ) -store_x x6, 3 * portWORD_SIZE( sp ) -store_x x7, 4 * portWORD_SIZE( sp ) -store_x x8, 5 * portWORD_SIZE( sp ) -store_x x9, 6 * portWORD_SIZE( sp ) -store_x x10, 7 * portWORD_SIZE( sp ) -store_x x11, 8 * portWORD_SIZE( sp ) -store_x x12, 9 * portWORD_SIZE( sp ) -store_x x13, 10 * portWORD_SIZE( sp ) -store_x x14, 11 * portWORD_SIZE( sp ) -store_x x15, 12 * portWORD_SIZE( sp ) +store_x x1, 2 * portWORD_SIZE( sp ) +store_x x5, 3 * portWORD_SIZE( sp ) +store_x x6, 4 * portWORD_SIZE( sp ) +store_x x7, 5 * portWORD_SIZE( sp ) +store_x x8, 6 * portWORD_SIZE( sp ) +store_x x9, 7 * portWORD_SIZE( sp ) +store_x x10, 8 * portWORD_SIZE( sp ) +store_x x11, 9 * portWORD_SIZE( sp ) +store_x x12, 10 * portWORD_SIZE( sp ) +store_x x13, 11 * portWORD_SIZE( sp ) +store_x x14, 12 * portWORD_SIZE( sp ) +store_x x15, 13 * portWORD_SIZE( sp ) #ifndef __riscv_32e - store_x x16, 13 * portWORD_SIZE( sp ) - store_x x17, 14 * portWORD_SIZE( sp ) - store_x x18, 15 * portWORD_SIZE( sp ) - store_x x19, 16 * portWORD_SIZE( sp ) - store_x x20, 17 * portWORD_SIZE( sp ) - store_x x21, 18 * portWORD_SIZE( sp ) - store_x x22, 19 * portWORD_SIZE( sp ) - store_x x23, 20 * portWORD_SIZE( sp ) - store_x x24, 21 * portWORD_SIZE( sp ) - store_x x25, 22 * portWORD_SIZE( sp ) - store_x x26, 23 * portWORD_SIZE( sp ) - store_x x27, 24 * portWORD_SIZE( sp ) - store_x x28, 25 * portWORD_SIZE( sp ) - store_x x29, 26 * portWORD_SIZE( sp ) - store_x x30, 27 * portWORD_SIZE( sp ) - store_x x31, 28 * portWORD_SIZE( sp ) + store_x x16, 14 * portWORD_SIZE( sp ) + store_x x17, 15 * portWORD_SIZE( sp ) + store_x x18, 16 * portWORD_SIZE( sp ) + store_x x19, 17 * portWORD_SIZE( sp ) + store_x x20, 18 * portWORD_SIZE( sp ) + store_x x21, 19 * portWORD_SIZE( sp ) + store_x x22, 20 * portWORD_SIZE( sp ) + store_x x23, 21 * portWORD_SIZE( sp ) + store_x x24, 22 * portWORD_SIZE( sp ) + store_x x25, 23 * portWORD_SIZE( sp ) + store_x x26, 24 * portWORD_SIZE( sp ) + store_x x27, 25 * portWORD_SIZE( sp ) + store_x x28, 26 * portWORD_SIZE( sp ) + store_x x29, 27 * portWORD_SIZE( sp ) + store_x x30, 28 * portWORD_SIZE( sp ) + store_x x31, 29 * portWORD_SIZE( sp ) #endif /* ifndef __riscv_32e */ load_x t0, xCriticalNesting /* Load the value of xCriticalNesting into t0. */ store_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Store the critical nesting value to the stack. */ +#if( configENABLE_FPU == 1 ) + csrr t0, mstatus + srl t1, t0, MSTATUS_FS_OFFSET + andi t1, t1, 3 + addi t2, x0, 3 + bne t1, t2, 1f /* If FPU status is not dirty, do not save FPU registers. */ -csrr t0, mstatus /* Required for MPIE bit. */ -store_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp ) - + portcontexSAVE_FPU_CONTEXT +1: +#endif portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */ +csrr t0, mstatus +store_x t0, 1 * portWORD_SIZE( sp ) + +#if( configENABLE_FPU == 1 ) + /* Mark the FPU as clean, if it was dirty and we saved FPU registers. */ + srl t1, t0, MSTATUS_FS_OFFSET + andi t1, t1, 3 + addi t2, x0, 3 + bne t1, t2, 2f + + li t1, ~MSTATUS_FS_MASK + and t0, t0, t1 + li t1, MSTATUS_FS_CLEAN + or t0, t0, t1 + csrw mstatus, t0 +2: +#endif + load_x t0, pxCurrentTCB /* Load pxCurrentTCB. */ store_x sp, 0 ( t0 ) /* Write sp to first TCB member. */ @@ -142,46 +280,57 @@ load_x sp, 0 ( t1 ) /* Read sp from first TCB member. */ load_x t0, 0 ( sp ) csrw mepc, t0 +/* Restore mstatus register. */ +load_x t0, 1 * portWORD_SIZE( sp ) +csrw mstatus, t0 + /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */ portasmRESTORE_ADDITIONAL_REGISTERS -/* Load mstatus with the interrupt enable bits used by the task. */ -load_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp ) -csrw mstatus, t0 /* Required for MPIE bit. */ +#if( configENABLE_FPU == 1 ) + csrr t0, mstatus + srl t1, t0, MSTATUS_FS_OFFSET + andi t1, t1, 3 + addi t2, x0, 3 + bne t1, t2, 3f /* If FPU status is not dirty, do not restore FPU registers. */ + + portcontextRESTORE_FPU_CONTEXT +3: +#endif /* ifdef portasmSTORE_FPU_CONTEXT */ load_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */ load_x t1, pxCriticalNesting /* Load the address of xCriticalNesting into t1. */ store_x t0, 0 ( t1 ) /* Restore the critical nesting value for this task. */ -load_x x1, 1 * portWORD_SIZE( sp ) -load_x x5, 2 * portWORD_SIZE( sp ) -load_x x6, 3 * portWORD_SIZE( sp ) -load_x x7, 4 * portWORD_SIZE( sp ) -load_x x8, 5 * portWORD_SIZE( sp ) -load_x x9, 6 * portWORD_SIZE( sp ) -load_x x10, 7 * portWORD_SIZE( sp ) -load_x x11, 8 * portWORD_SIZE( sp ) -load_x x12, 9 * portWORD_SIZE( sp ) -load_x x13, 10 * portWORD_SIZE( sp ) -load_x x14, 11 * portWORD_SIZE( sp ) -load_x x15, 12 * portWORD_SIZE( sp ) +load_x x1, 2 * portWORD_SIZE( sp ) +load_x x5, 3 * portWORD_SIZE( sp ) +load_x x6, 4 * portWORD_SIZE( sp ) +load_x x7, 5 * portWORD_SIZE( sp ) +load_x x8, 6 * portWORD_SIZE( sp ) +load_x x9, 7 * portWORD_SIZE( sp ) +load_x x10, 8 * portWORD_SIZE( sp ) +load_x x11, 9 * portWORD_SIZE( sp ) +load_x x12, 10 * portWORD_SIZE( sp ) +load_x x13, 11 * portWORD_SIZE( sp ) +load_x x14, 12 * portWORD_SIZE( sp ) +load_x x15, 13 * portWORD_SIZE( sp ) #ifndef __riscv_32e - load_x x16, 13 * portWORD_SIZE( sp ) - load_x x17, 14 * portWORD_SIZE( sp ) - load_x x18, 15 * portWORD_SIZE( sp ) - load_x x19, 16 * portWORD_SIZE( sp ) - load_x x20, 17 * portWORD_SIZE( sp ) - load_x x21, 18 * portWORD_SIZE( sp ) - load_x x22, 19 * portWORD_SIZE( sp ) - load_x x23, 20 * portWORD_SIZE( sp ) - load_x x24, 21 * portWORD_SIZE( sp ) - load_x x25, 22 * portWORD_SIZE( sp ) - load_x x26, 23 * portWORD_SIZE( sp ) - load_x x27, 24 * portWORD_SIZE( sp ) - load_x x28, 25 * portWORD_SIZE( sp ) - load_x x29, 26 * portWORD_SIZE( sp ) - load_x x30, 27 * portWORD_SIZE( sp ) - load_x x31, 28 * portWORD_SIZE( sp ) + load_x x16, 14 * portWORD_SIZE( sp ) + load_x x17, 15 * portWORD_SIZE( sp ) + load_x x18, 16 * portWORD_SIZE( sp ) + load_x x19, 17 * portWORD_SIZE( sp ) + load_x x20, 18 * portWORD_SIZE( sp ) + load_x x21, 19 * portWORD_SIZE( sp ) + load_x x22, 20 * portWORD_SIZE( sp ) + load_x x23, 21 * portWORD_SIZE( sp ) + load_x x24, 22 * portWORD_SIZE( sp ) + load_x x25, 23 * portWORD_SIZE( sp ) + load_x x26, 24 * portWORD_SIZE( sp ) + load_x x27, 25 * portWORD_SIZE( sp ) + load_x x28, 26 * portWORD_SIZE( sp ) + load_x x29, 27 * portWORD_SIZE( sp ) + load_x x30, 28 * portWORD_SIZE( sp ) + load_x x31, 29 * portWORD_SIZE( sp ) #endif /* ifndef __riscv_32e */ addi sp, sp, portCONTEXT_SIZE