Kernel source code:
+ Added xPortIsInsideInterrupt() to RVDS ARM CM4F port - the same will get added to other ports in time. Demo application code: + Added first pass Microchip CEC1302 demo for Keil. + Harden the new StaticAllocation.c standard demo tasks against integer promotion rules causing problems on 16-bit architectures.pull/4/head
Richard Barry
9 years ago
parent
732778a971
commit
42e73b9b8f
@ -0,0 +1,734 @@
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/**************************************************************************//**
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* @file cmsis_armcc.h
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* @brief CMSIS Cortex-M Core Function/Instruction Header File
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* @version V4.30
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* @date 20. October 2015
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******************************************************************************/
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/* Copyright (c) 2009 - 2015 ARM LIMITED
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name of ARM nor the names of its contributors may be used
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to endorse or promote products derived from this software without
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specific prior written permission.
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*
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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---------------------------------------------------------------------------*/
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#ifndef __CMSIS_ARMCC_H
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#define __CMSIS_ARMCC_H
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#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
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#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
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#endif
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/* ########################### Core Function Access ########################### */
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/** \ingroup CMSIS_Core_FunctionInterface
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\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
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@{
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*/
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/* intrinsic void __enable_irq(); */
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/* intrinsic void __disable_irq(); */
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/**
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\brief Get Control Register
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\details Returns the content of the Control Register.
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\return Control Register value
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*/
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__STATIC_INLINE uint32_t __get_CONTROL(void)
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{
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register uint32_t __regControl __ASM("control");
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return(__regControl);
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}
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/**
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\brief Set Control Register
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\details Writes the given value to the Control Register.
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\param [in] control Control Register value to set
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*/
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__STATIC_INLINE void __set_CONTROL(uint32_t control)
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{
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register uint32_t __regControl __ASM("control");
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__regControl = control;
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}
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/**
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\brief Get IPSR Register
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\details Returns the content of the IPSR Register.
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\return IPSR Register value
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*/
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__STATIC_INLINE uint32_t __get_IPSR(void)
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{
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register uint32_t __regIPSR __ASM("ipsr");
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return(__regIPSR);
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}
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/**
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\brief Get APSR Register
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\details Returns the content of the APSR Register.
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\return APSR Register value
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*/
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__STATIC_INLINE uint32_t __get_APSR(void)
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{
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register uint32_t __regAPSR __ASM("apsr");
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return(__regAPSR);
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}
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/**
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\brief Get xPSR Register
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\details Returns the content of the xPSR Register.
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\return xPSR Register value
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*/
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__STATIC_INLINE uint32_t __get_xPSR(void)
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{
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register uint32_t __regXPSR __ASM("xpsr");
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return(__regXPSR);
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}
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/**
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\brief Get Process Stack Pointer
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\details Returns the current value of the Process Stack Pointer (PSP).
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\return PSP Register value
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*/
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__STATIC_INLINE uint32_t __get_PSP(void)
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{
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register uint32_t __regProcessStackPointer __ASM("psp");
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return(__regProcessStackPointer);
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}
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/**
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\brief Set Process Stack Pointer
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\details Assigns the given value to the Process Stack Pointer (PSP).
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\param [in] topOfProcStack Process Stack Pointer value to set
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*/
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__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
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{
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register uint32_t __regProcessStackPointer __ASM("psp");
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__regProcessStackPointer = topOfProcStack;
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}
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/**
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\brief Get Main Stack Pointer
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\details Returns the current value of the Main Stack Pointer (MSP).
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\return MSP Register value
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*/
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__STATIC_INLINE uint32_t __get_MSP(void)
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{
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register uint32_t __regMainStackPointer __ASM("msp");
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return(__regMainStackPointer);
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}
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/**
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\brief Set Main Stack Pointer
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\details Assigns the given value to the Main Stack Pointer (MSP).
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\param [in] topOfMainStack Main Stack Pointer value to set
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*/
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__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
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{
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register uint32_t __regMainStackPointer __ASM("msp");
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__regMainStackPointer = topOfMainStack;
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}
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/**
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\brief Get Priority Mask
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\details Returns the current state of the priority mask bit from the Priority Mask Register.
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\return Priority Mask value
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*/
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__STATIC_INLINE uint32_t __get_PRIMASK(void)
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{
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register uint32_t __regPriMask __ASM("primask");
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return(__regPriMask);
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}
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/**
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\brief Set Priority Mask
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\details Assigns the given value to the Priority Mask Register.
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\param [in] priMask Priority Mask
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*/
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__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
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{
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register uint32_t __regPriMask __ASM("primask");
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__regPriMask = (priMask);
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}
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#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
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/**
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\brief Enable FIQ
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\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
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Can only be executed in Privileged modes.
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*/
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#define __enable_fault_irq __enable_fiq
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/**
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\brief Disable FIQ
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\details Disables FIQ interrupts by setting the F-bit in the CPSR.
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Can only be executed in Privileged modes.
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*/
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#define __disable_fault_irq __disable_fiq
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/**
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\brief Get Base Priority
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\details Returns the current value of the Base Priority register.
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\return Base Priority register value
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*/
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__STATIC_INLINE uint32_t __get_BASEPRI(void)
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{
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register uint32_t __regBasePri __ASM("basepri");
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return(__regBasePri);
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}
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/**
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\brief Set Base Priority
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\details Assigns the given value to the Base Priority register.
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\param [in] basePri Base Priority value to set
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*/
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__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
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{
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register uint32_t __regBasePri __ASM("basepri");
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__regBasePri = (basePri & 0xFFU);
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}
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/**
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\brief Set Base Priority with condition
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\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
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or the new value increases the BASEPRI priority level.
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\param [in] basePri Base Priority value to set
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*/
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__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
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{
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register uint32_t __regBasePriMax __ASM("basepri_max");
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__regBasePriMax = (basePri & 0xFFU);
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}
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/**
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\brief Get Fault Mask
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\details Returns the current value of the Fault Mask register.
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\return Fault Mask register value
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*/
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__STATIC_INLINE uint32_t __get_FAULTMASK(void)
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{
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register uint32_t __regFaultMask __ASM("faultmask");
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return(__regFaultMask);
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}
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/**
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\brief Set Fault Mask
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\details Assigns the given value to the Fault Mask register.
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\param [in] faultMask Fault Mask value to set
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*/
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__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
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{
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register uint32_t __regFaultMask __ASM("faultmask");
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__regFaultMask = (faultMask & (uint32_t)1);
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}
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#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
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#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
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/**
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\brief Get FPSCR
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\details Returns the current value of the Floating Point Status/Control register.
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\return Floating Point Status/Control register value
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*/
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__STATIC_INLINE uint32_t __get_FPSCR(void)
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{
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#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
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register uint32_t __regfpscr __ASM("fpscr");
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return(__regfpscr);
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#else
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return(0U);
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#endif
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}
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/**
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\brief Set FPSCR
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\details Assigns the given value to the Floating Point Status/Control register.
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\param [in] fpscr Floating Point Status/Control value to set
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*/
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__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
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{
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#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
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register uint32_t __regfpscr __ASM("fpscr");
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__regfpscr = (fpscr);
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#endif
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}
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#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
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/*@} end of CMSIS_Core_RegAccFunctions */
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/* ########################## Core Instruction Access ######################### */
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/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
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Access to dedicated instructions
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@{
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*/
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/**
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\brief No Operation
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\details No Operation does nothing. This instruction can be used for code alignment purposes.
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*/
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#define __NOP __nop
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/**
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\brief Wait For Interrupt
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\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
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*/
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#define __WFI __wfi
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/**
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\brief Wait For Event
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\details Wait For Event is a hint instruction that permits the processor to enter
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a low-power state until one of a number of events occurs.
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*/
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#define __WFE __wfe
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/**
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\brief Send Event
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\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
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*/
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#define __SEV __sev
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/**
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\brief Instruction Synchronization Barrier
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\details Instruction Synchronization Barrier flushes the pipeline in the processor,
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so that all instructions following the ISB are fetched from cache or memory,
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after the instruction has been completed.
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*/
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#define __ISB() do {\
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__schedule_barrier();\
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__isb(0xF);\
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__schedule_barrier();\
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} while (0U)
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/**
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\brief Data Synchronization Barrier
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\details Acts as a special kind of Data Memory Barrier.
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It completes when all explicit memory accesses before this instruction complete.
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*/
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#define __DSB() do {\
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__schedule_barrier();\
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__dsb(0xF);\
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__schedule_barrier();\
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} while (0U)
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/**
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\brief Data Memory Barrier
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\details Ensures the apparent order of the explicit memory operations before
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and after the instruction, without ensuring their completion.
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*/
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#define __DMB() do {\
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__schedule_barrier();\
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__dmb(0xF);\
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__schedule_barrier();\
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} while (0U)
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/**
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\brief Reverse byte order (32 bit)
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\details Reverses the byte order in integer value.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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#define __REV __rev
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/**
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\brief Reverse byte order (16 bit)
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\details Reverses the byte order in two unsigned short values.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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#ifndef __NO_EMBEDDED_ASM
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__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
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{
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rev16 r0, r0
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bx lr
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}
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#endif
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/**
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\brief Reverse byte order in signed short value
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\details Reverses the byte order in a signed short value with sign extension to integer.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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#ifndef __NO_EMBEDDED_ASM
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__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
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{
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revsh r0, r0
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bx lr
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}
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#endif
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/**
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\brief Rotate Right in unsigned value (32 bit)
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\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
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\param [in] value Value to rotate
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\param [in] value Number of Bits to rotate
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\return Rotated value
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*/
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#define __ROR __ror
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/**
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\brief Breakpoint
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\details Causes the processor to enter Debug state.
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Debug tools can use this to investigate system state when the instruction at a particular address is reached.
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\param [in] value is ignored by the processor.
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If required, a debugger can use it to store additional information about the breakpoint.
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*/
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#define __BKPT(value) __breakpoint(value)
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/**
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\brief Reverse bit order of value
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\details Reverses the bit order of the given value.
|
||||
\param [in] value Value to reverse
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||||
\return Reversed value
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||||
*/
|
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#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
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#define __RBIT __rbit
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#else
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__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
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uint32_t result;
|
||||
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
|
||||
|
||||
result = value; /* r will be reversed bits of v; first get LSB of v */
|
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for (value >>= 1U; value; value >>= 1U)
|
||||
{
|
||||
result <<= 1U;
|
||||
result |= value & 1U;
|
||||
s--;
|
||||
}
|
||||
result <<= s; /* shift when v's highest bits are zero */
|
||||
return(result);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Count leading zeros
|
||||
\details Counts the number of leading zeros of a data value.
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
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||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (8 bit)
|
||||
\details Executes a exclusive LDR instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
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||||
#else
|
||||
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (16 bit)
|
||||
\details Executes a exclusive LDR instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (32 bit)
|
||||
\details Executes a exclusive LDR instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (8 bit)
|
||||
\details Executes a exclusive STR instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (16 bit)
|
||||
\details Executes a exclusive STR instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (32 bit)
|
||||
\details Executes a exclusive STR instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Remove the exclusive lock
|
||||
\details Removes the exclusive lock which is created by LDREX.
|
||||
*/
|
||||
#define __CLREX __clrex
|
||||
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __ssat
|
||||
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __usat
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right with Extend (32 bit)
|
||||
\details Moves each bit of a bitstring right by one bit.
|
||||
The carry input is shifted in at the left end of the bitstring.
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
rrx r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRBT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRHT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRT(value, ptr) __strt(value, ptr)
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
|
||||
|
||||
#define __SADD8 __sadd8
|
||||
#define __QADD8 __qadd8
|
||||
#define __SHADD8 __shadd8
|
||||
#define __UADD8 __uadd8
|
||||
#define __UQADD8 __uqadd8
|
||||
#define __UHADD8 __uhadd8
|
||||
#define __SSUB8 __ssub8
|
||||
#define __QSUB8 __qsub8
|
||||
#define __SHSUB8 __shsub8
|
||||
#define __USUB8 __usub8
|
||||
#define __UQSUB8 __uqsub8
|
||||
#define __UHSUB8 __uhsub8
|
||||
#define __SADD16 __sadd16
|
||||
#define __QADD16 __qadd16
|
||||
#define __SHADD16 __shadd16
|
||||
#define __UADD16 __uadd16
|
||||
#define __UQADD16 __uqadd16
|
||||
#define __UHADD16 __uhadd16
|
||||
#define __SSUB16 __ssub16
|
||||
#define __QSUB16 __qsub16
|
||||
#define __SHSUB16 __shsub16
|
||||
#define __USUB16 __usub16
|
||||
#define __UQSUB16 __uqsub16
|
||||
#define __UHSUB16 __uhsub16
|
||||
#define __SASX __sasx
|
||||
#define __QASX __qasx
|
||||
#define __SHASX __shasx
|
||||
#define __UASX __uasx
|
||||
#define __UQASX __uqasx
|
||||
#define __UHASX __uhasx
|
||||
#define __SSAX __ssax
|
||||
#define __QSAX __qsax
|
||||
#define __SHSAX __shsax
|
||||
#define __USAX __usax
|
||||
#define __UQSAX __uqsax
|
||||
#define __UHSAX __uhsax
|
||||
#define __USAD8 __usad8
|
||||
#define __USADA8 __usada8
|
||||
#define __SSAT16 __ssat16
|
||||
#define __USAT16 __usat16
|
||||
#define __UXTB16 __uxtb16
|
||||
#define __UXTAB16 __uxtab16
|
||||
#define __SXTB16 __sxtb16
|
||||
#define __SXTAB16 __sxtab16
|
||||
#define __SMUAD __smuad
|
||||
#define __SMUADX __smuadx
|
||||
#define __SMLAD __smlad
|
||||
#define __SMLADX __smladx
|
||||
#define __SMLALD __smlald
|
||||
#define __SMLALDX __smlaldx
|
||||
#define __SMUSD __smusd
|
||||
#define __SMUSDX __smusdx
|
||||
#define __SMLSD __smlsd
|
||||
#define __SMLSDX __smlsdx
|
||||
#define __SMLSLD __smlsld
|
||||
#define __SMLSLDX __smlsldx
|
||||
#define __SEL __sel
|
||||
#define __QADD __qadd
|
||||
#define __QSUB __qsub
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||
|
||||
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||
((int64_t)(ARG3) << 32U) ) >> 32U))
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x04) */
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#endif /* __CMSIS_ARMCC_H */
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,87 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cmFunc.h
|
||||
* @brief CMSIS Cortex-M Core Function Access Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CMFUNC_H
|
||||
#define __CORE_CMFUNC_H
|
||||
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/*------------------ RealView Compiler -----------------*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
/*------------------ ARM Compiler V6 -------------------*/
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armcc_V6.h"
|
||||
|
||||
/*------------------ GNU Compiler ----------------------*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
/*------------------ ICC Compiler ----------------------*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/
|
||||
#elif defined ( __TMS470__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
/*------------------ TASKING Compiler ------------------*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
#endif /* __CORE_CMFUNC_H */
|
||||
@ -0,0 +1,87 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cmInstr.h
|
||||
* @brief CMSIS Cortex-M Core Instruction Access Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CMINSTR_H
|
||||
#define __CORE_CMINSTR_H
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/*------------------ RealView Compiler -----------------*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
/*------------------ ARM Compiler V6 -------------------*/
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armcc_V6.h"
|
||||
|
||||
/*------------------ GNU Compiler ----------------------*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
/*------------------ ICC Compiler ----------------------*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/
|
||||
#elif defined ( __TMS470__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
/*------------------ TASKING Compiler ------------------*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
#endif /* __CORE_CMINSTR_H */
|
||||
@ -0,0 +1,96 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cmSimd.h
|
||||
* @brief CMSIS Cortex-M SIMD Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CMSIMD_H
|
||||
#define __CORE_CMSIMD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/*------------------ RealView Compiler -----------------*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
/*------------------ ARM Compiler V6 -------------------*/
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armcc_V6.h"
|
||||
|
||||
/*------------------ GNU Compiler ----------------------*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
/*------------------ ICC Compiler ----------------------*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/
|
||||
#elif defined ( __TMS470__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
/*------------------ TASKING Compiler ------------------*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CMSIMD_H */
|
||||
@ -0,0 +1,224 @@
|
||||
/*
|
||||
FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
|
||||
All rights reserved
|
||||
|
||||
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
|
||||
|
||||
***************************************************************************
|
||||
>>! NOTE: The modification to the GPL is included to allow you to !<<
|
||||
>>! distribute a combined work that includes FreeRTOS without being !<<
|
||||
>>! obliged to provide the source code for proprietary components !<<
|
||||
>>! outside of the FreeRTOS kernel. !<<
|
||||
***************************************************************************
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
|
||||
FOR A PARTICULAR PURPOSE. Full license text is available on the following
|
||||
link: http://www.freertos.org/a00114.html
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS provides completely free yet professionally developed, *
|
||||
* robust, strictly quality controlled, supported, and cross *
|
||||
* platform software that is more than just the market leader, it *
|
||||
* is the industry's de facto standard. *
|
||||
* *
|
||||
* Help yourself get started quickly while simultaneously helping *
|
||||
* to support the FreeRTOS project by purchasing a FreeRTOS *
|
||||
* tutorial book, reference manual, or both: *
|
||||
* http://www.FreeRTOS.org/Documentation *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
|
||||
the FAQ page "My application does not run, what could be wrong?". Have you
|
||||
defined configASSERT()?
|
||||
|
||||
http://www.FreeRTOS.org/support - In return for receiving this top quality
|
||||
embedded software for free we request you assist our global community by
|
||||
participating in the support forum.
|
||||
|
||||
http://www.FreeRTOS.org/training - Investing in training allows your team to
|
||||
be as productive as possible as early as possible. Now you can receive
|
||||
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
|
||||
Ltd, and the world's leading authority on the world's leading RTOS.
|
||||
|
||||
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
|
||||
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
|
||||
compatible FAT file system, and our tiny thread aware UDP/IP stack.
|
||||
|
||||
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
|
||||
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
|
||||
|
||||
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
|
||||
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
|
||||
licenses offer ticketed support, indemnification and commercial middleware.
|
||||
|
||||
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
|
||||
engineered and independently SIL3 certified version for use in safety and
|
||||
mission critical applications that require provable dependability.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
|
||||
#ifndef FREERTOS_CONFIG_H
|
||||
#define FREERTOS_CONFIG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Application specific definitions.
|
||||
*
|
||||
* These definitions should be adjusted for your particular hardware and
|
||||
* application requirements.
|
||||
*
|
||||
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
|
||||
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
|
||||
*
|
||||
* See http://www.freertos.org/a00110.html.
|
||||
*----------------------------------------------------------*/
|
||||
|
||||
|
||||
/* Set configCREATE_LOW_POWER_DEMO to one to run the simple blinky demo low power
|
||||
example, or 1 to run the more comprehensive test and demo application. See
|
||||
the comments at the top of main.c for more information. */
|
||||
#define configCREATE_LOW_POWER_DEMO 1
|
||||
|
||||
/* Some configuration is dependent on the demo being built. */
|
||||
#if( configCREATE_LOW_POWER_DEMO == 1 )
|
||||
|
||||
/* The low power demo uses a slow low power clock, so the SysTick clock,
|
||||
which is used by default by Cortex-M ports, is not used to generate the
|
||||
tick interrupt. */
|
||||
#define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 1
|
||||
|
||||
/* The slow clock used to generate the tick interrupt in the low power demo
|
||||
runs at 32768Hz. Ensure the clock is a multiple of the tick rate. */
|
||||
#define configTICK_RATE_HZ ( 128 )
|
||||
|
||||
/* The low power demo uses the tickless idle feature. */
|
||||
#define configUSE_TICKLESS_IDLE 1
|
||||
|
||||
#else
|
||||
|
||||
/* Some of the standard demo test tasks assume a tick rate of 1KHz, even
|
||||
though that is faster than would normally be warranted by a real
|
||||
application. */
|
||||
#define configTICK_RATE_HZ ( 1000 )
|
||||
|
||||
/* The full demo always has tasks to run so the tick will never be turned
|
||||
off. The blinky demo will use the default tickless idle implementation to
|
||||
turn the tick off. */
|
||||
#define configUSE_TICKLESS_IDLE 0
|
||||
|
||||
#endif
|
||||
|
||||
#define configUSE_PREEMPTION 1
|
||||
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
|
||||
#define configUSE_QUEUE_SETS 1
|
||||
#define configUSE_IDLE_HOOK 0
|
||||
#define configUSE_TICK_HOOK 1
|
||||
#define configCPU_CLOCK_HZ 48000000
|
||||
#define configMAX_PRIORITIES ( 5 )
|
||||
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 120 )
|
||||
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 40 * 1024 ) )
|
||||
#define configMAX_TASK_NAME_LEN ( 10 )
|
||||
#define configUSE_TRACE_FACILITY 0
|
||||
#define configUSE_16_BIT_TICKS 0
|
||||
#define configIDLE_SHOULD_YIELD 1
|
||||
#define configUSE_MUTEXES 1
|
||||
#define configQUEUE_REGISTRY_SIZE 0
|
||||
#define configCHECK_FOR_STACK_OVERFLOW 2
|
||||
#define configUSE_RECURSIVE_MUTEXES 1
|
||||
#define configUSE_MALLOC_FAILED_HOOK 1
|
||||
#define configUSE_APPLICATION_TASK_TAG 0
|
||||
#define configUSE_COUNTING_SEMAPHORES 1
|
||||
#define configSUPPORT_STATIC_ALLOCATION 1
|
||||
|
||||
/* Run time stats gathering definitions. */
|
||||
#define configGENERATE_RUN_TIME_STATS 0
|
||||
#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()
|
||||
#define portGET_RUN_TIME_COUNTER_VALUE()
|
||||
|
||||
/* This demo makes use of one or more example stats formatting functions. These
|
||||
format the raw data provided by the uxTaskGetSystemState() function in to human
|
||||
readable ASCII form. See the notes in the implementation of vTaskList() within
|
||||
FreeRTOS/Source/tasks.c for limitations. */
|
||||
#define configUSE_STATS_FORMATTING_FUNCTIONS 0
|
||||
|
||||
/* Co-routine definitions. */
|
||||
#define configUSE_CO_ROUTINES 0
|
||||
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
|
||||
|
||||
/* Software timer definitions. */
|
||||
#define configUSE_TIMERS 1
|
||||
#define configTIMER_TASK_PRIORITY ( 2 )
|
||||
#define configTIMER_QUEUE_LENGTH 5
|
||||
#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )
|
||||
|
||||
/* Set the following definitions to 1 to include the API function, or zero
|
||||
to exclude the API function. */
|
||||
#define INCLUDE_vTaskPrioritySet 1
|
||||
#define INCLUDE_uxTaskPriorityGet 1
|
||||
#define INCLUDE_vTaskDelete 1
|
||||
#define INCLUDE_vTaskCleanUpResources 1
|
||||
#define INCLUDE_vTaskSuspend 1
|
||||
#define INCLUDE_vTaskDelayUntil 1
|
||||
#define INCLUDE_vTaskDelay 1
|
||||
#define INCLUDE_eTaskGetState 1
|
||||
#define INCLUDE_xTimerPendFunctionCall 1
|
||||
|
||||
/* Cortex-M specific definitions. */
|
||||
#ifdef __NVIC_PRIO_BITS
|
||||
/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
|
||||
#define configPRIO_BITS __NVIC_PRIO_BITS
|
||||
#else
|
||||
#define configPRIO_BITS 4 /* 15 priority levels */
|
||||
#endif
|
||||
|
||||
/* The lowest interrupt priority that can be used in a call to a "set priority"
|
||||
function. */
|
||||
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0xf
|
||||
|
||||
/* The highest interrupt priority that can be used by any interrupt service
|
||||
routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
|
||||
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
|
||||
PRIORITY THAN THIS! (higher priorities are lower numeric values. */
|
||||
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
|
||||
|
||||
/* Interrupt priorities used by the kernel port layer itself. These are generic
|
||||
to all Cortex-M ports, and do not rely on any particular library functions. */
|
||||
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
|
||||
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
|
||||
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
|
||||
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
|
||||
|
||||
|
||||
/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
|
||||
standard names. */
|
||||
#define xPortPendSVHandler PendSV_Handler
|
||||
#define vPortSVCHandler SVC_Handler
|
||||
#define xPortSysTickHandler SysTick_Handler
|
||||
|
||||
/* Normal assert() semantics without relying on the provision of an assert.h
|
||||
header file. */
|
||||
#define configASSERT( x ) if( ( x ) == 0UL ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
|
||||
|
||||
/* LED not used at present, so just increment a variable to keep a count of the
|
||||
number of times the LED would otherwise have been toggled. */
|
||||
#define mainTOGGLE_LED() ulLED++
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* FREERTOS_CONFIG_H */
|
||||
@ -0,0 +1,492 @@
|
||||
|
||||
T220C 000:298 SEGGER J-Link V4.98e Log File (0000ms, 0270ms total)
|
||||
T220C 000:298 DLL Compiled: May 5 2015 11:00:52 (0000ms, 0270ms total)
|
||||
T220C 000:298 Logging started @ 2016-01-08 12:24 (0000ms, 0270ms total)
|
||||
T220C 000:298 JLINK_SetWarnOutHandler(...) (0000ms, 0270ms total)
|
||||
T220C 000:298 JLINK_OpenEx(...)
|
||||
Firmware: J-Link V9 compiled Oct 9 2015 20:34:47
|
||||
Hardware: V9.10
|
||||
S/N: 59101789
|
||||
Feature(s): GDB, JFlash returns O.K. (0266ms, 0536ms total)
|
||||
T220C 000:564 JLINK_SetErrorOutHandler(...) (0000ms, 0536ms total)
|
||||
T220C 000:564 JLINK_ExecCommand("ProjectFile = "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M4F_CEC1302_Clicker_2\Keil_Specific\JLinkSettings.ini"", ...)Device "UNSPECIFIED" selected. returns 0x00 (0002ms, 0538ms total)
|
||||
T220C 000:566 JLINK_ExecCommand("Device = ARMCM4_FP", ...)Device "UNSPECIFIED" selected. returns 0x00 (0000ms, 0538ms total)
|
||||
T220C 000:566 JLINK_ExecCommand("DisableConnectionTimeout", ...) returns 0x01 (0000ms, 0538ms total)
|
||||
T220C 000:566 JLINK_GetHardwareVersion() returns 0x16378 (0000ms, 0538ms total)
|
||||
T220C 000:566 JLINK_GetDLLVersion() returns 49805 (0000ms, 0538ms total)
|
||||
T220C 000:566 JLINK_GetFirmwareString(...) (0000ms, 0538ms total)
|
||||
T220C 000:566 JLINK_GetDLLVersion() returns 49805 (0000ms, 0538ms total)
|
||||
T220C 000:566 JLINK_GetCompileDateTime() (0000ms, 0538ms total)
|
||||
T220C 000:566 JLINK_GetFirmwareString(...) (0000ms, 0538ms total)
|
||||
T220C 000:566 JLINK_GetHardwareVersion() returns 0x16378 (0001ms, 0539ms total)
|
||||
T220C 000:567 JLINK_TIF_Select(JLINKARM_TIF_JTAG) returns 0x00 (0003ms, 0542ms total)
|
||||
T220C 000:570 JLINK_SetSpeed(5000) (0000ms, 0542ms total)
|
||||
T220C 000:570 JLINK_GetIdData(...) >0x2F8 JTAG>TotalIRLen = 4, IRPrint = 0x01 >0x30 JTAG> >0x210 JTAG> >0x70 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x48 JTAG> >0x78 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG>Found Cortex-M4 r0p1, Little endian. -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE0002000)FPUnit: 6 code (BP) slots and 2 literal slots -- CPU_ReadMem(4 bytes @ 0xE000EDFC)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0001000) -- CPU_ReadMem(4 bytes @ 0xE000ED88) -- CPU_WriteMem(4 bytes @ 0xE000ED88) -- CPU_ReadMem(4 bytes @ 0xE000ED88) -- CPU_WriteMem(4 bytes @ 0xE000ED88)CoreSight components:ROMTbl 0 @ E00FF000 -- CPU_ReadMem(16 bytes @ 0xE00FF000) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) -- CPU_ReadMem(16 bytes @ 0xE000EFE0)ROMTbl 0 [0]: FFF0F000, CID: B105E00D, PID: 000BB00C SCS -- CPU_ReadMem(16 bytes @ 0xE0001FF0)
|
||||
-- CPU_ReadMem(16 bytes @ 0xE0001FE0)ROMTbl 0 [1]: FFF02000, CID: B105E00D, PID: 003BB002 DWT -- CPU_ReadMem(16 bytes @ 0xE0002FF0) -- CPU_ReadMem(16 bytes @ 0xE0002FE0)ROMTbl 0 [2]: FFF03000, CID: B105E00D, PID: 002BB003 FPB -- CPU_ReadMem(16 bytes @ 0xE0000FF0) -- CPU_ReadMem(16 bytes @ 0xE0000FE0)ROMTbl 0 [3]: FFF01000, CID: B105E00D, PID: 003BB001 ITM -- CPU_ReadMem(16 bytes @ 0xE00FF010) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) -- CPU_ReadMem(16 bytes @ 0xE0040FE0)
|
||||
ROMTbl 0 [4]: FFF41000, CID: B105900D, PID: 000BB9A1 TPIU -- CPU_ReadMem(16 bytes @ 0xE0041FF0) -- CPU_ReadMem(16 bytes @ 0xE0041FE0)ROMTbl 0 [5]: FFF42000, CID: B105900D, PID: 000BB925 ETM ScanLen=4 NumDevices=1 aId[0]=0x4BA00477 aIrRead[0]=0 aScanLen[0]=0 aScanRead[0]=0 (0026ms, 0568ms total)
|
||||
T220C 000:596 JLINK_JTAG_GetDeviceID(DeviceIndex = 0) returns 0x4BA00477 (0000ms, 0568ms total)
|
||||
T220C 000:596 JLINK_JTAG_GetDeviceInfo(DeviceIndex = 0) returns 0x00 (0000ms, 0568ms total)
|
||||
T220C 000:596 JLINK_GetDLLVersion() returns 49805 (0000ms, 0568ms total)
|
||||
T220C 000:596 JLINK_CORE_GetFound() returns 0xE0000FF (0000ms, 0568ms total)
|
||||
T220C 000:596 JLINK_GetDebugInfo(0x100) -- Value=0xE00FF003 returns 0x00 (0000ms, 0568ms total)
|
||||
T220C 000:596 JLINK_ReadMem (0xE00FF000, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF 03 20 F0 FF 03 30 F0 FF 03 10 F0 FF ... returns 0x00 (0001ms, 0569ms total)
|
||||
T220C 000:597 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0570ms total)
|
||||
T220C 000:598 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0571ms total)
|
||||
T220C 000:599 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0000ms, 0571ms total)
|
||||
T220C 000:599 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0572ms total)
|
||||
T220C 000:600 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0573ms total)
|
||||
T220C 000:601 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0000ms, 0573ms total)
|
||||
T220C 000:601 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0574ms total)
|
||||
T220C 000:602 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0000ms, 0574ms total)
|
||||
T220C 000:602 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 0575ms total)
|
||||
T220C 000:603 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0576ms total)
|
||||
T220C 000:604 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0000ms, 0576ms total)
|
||||
T220C 000:604 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0577ms total)
|
||||
T220C 000:605 JLINK_ReadMemU32(0xE000EF40, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EF40) - Data: 21 00 11 10 returns 0x01 (0001ms, 0578ms total)
|
||||
T220C 000:606 JLINK_ReadMemU32(0xE000EF44, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EF44) - Data: 11 00 00 11 returns 0x01 (0000ms, 0578ms total)
|
||||
T220C 000:606 JLINK_ReadMemU32(0xE000ED00, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000ED00) - Data: 41 C2 0F 41 returns 0x01 (0001ms, 0579ms total)
|
||||
T220C 000:607 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 0579ms total)
|
||||
T220C 000:607 JLINK_Reset() -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048)
|
||||
-- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0646ms, 1225ms total)
|
||||
T220C 001:253 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 1225ms total)
|
||||
T220C 001:253 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 1225ms total)
|
||||
T220C 001:253 JLINK_Halt() returns 0x00 (0000ms, 1225ms total)
|
||||
T220C 001:253 JLINK_IsHalted() returns TRUE (0000ms, 1225ms total)
|
||||
T220C 001:253 JLINK_ReadMemU32(0xE000EDF0, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - Data: 03 00 03 00 returns 0x01 (0001ms, 1226ms total)
|
||||
T220C 001:254 JLINK_WriteU32(0xE000EDF0, 0xA05F0003) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) returns 0x00 (0000ms, 1226ms total)
|
||||
T220C 001:254 JLINK_WriteU32(0xE000EDFC, 0x01000000) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x00 (0001ms, 1227ms total)
|
||||
T220C 001:255 JLINK_GetHWStatus(...) returns 0x00 (0000ms, 1227ms total)
|
||||
T220C 001:256 JLINK_GetNumBPUnits(Type = 0xFFFFFF00) returns 0x06 (0000ms, 1227ms total)
|
||||
T220C 001:256 JLINK_GetNumBPUnits(Type = 0xF0) returns 0x2000 (0000ms, 1227ms total)
|
||||
T220C 001:256 JLINK_GetNumWPUnits() returns 0x04 (0000ms, 1227ms total)
|
||||
T220C 001:256 JLINK_GetSpeed() returns 0x1388 (0000ms, 1227ms total)
|
||||
T220C 001:256 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 02 00 00 00 returns 0x01 (0000ms, 1227ms total)
|
||||
T220C 001:256 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 02 00 00 00 returns 0x01 (0001ms, 1228ms total)
|
||||
T220C 001:257 JLINK_WriteMem(0xE0001000, 0x001C Bytes, ...) - Data: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... -- CPU_WriteMem(28 bytes @ 0xE0001000) returns 0x1C (0001ms, 1229ms total)
|
||||
T220C 001:258 JLINK_ReadMem (0xE0001000, 0x001C Bytes, ...) -- CPU_ReadMem(28 bytes @ 0xE0001000) - Data: 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 1230ms total)
|
||||
T220C 001:259 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 1230ms total)
|
||||
T220C 001:259 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 1230ms total)
|
||||
T220C 001:270 JLINK_WriteMem(0x00100000, 0x02AC Bytes, ...) - Data: 08 88 11 00 C1 01 10 00 DD 01 10 00 E3 01 10 00 ... -- CPU_WriteMem(684 bytes @ 0x00100000) returns 0x2AC (0003ms, 1233ms total)
|
||||
T220C 001:273 JLINK_ReadMem (0x00100000, 0x02AC Bytes, ...) -- CPU_ReadMem(684 bytes @ 0x00100000) - Data: 08 88 11 00 C1 01 10 00 DD 01 10 00 E3 01 10 00 ... returns 0x00 (0003ms, 1236ms total)
|
||||
T220C 001:330 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 1236ms total)
|
||||
T220C 001:330 JLINK_Reset() -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0646ms, 1882ms total)
|
||||
T220C 001:977 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 1882ms total)
|
||||
T220C 001:977 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 1882ms total)
|
||||
T220C 001:977 JLINK_ReadMem (0x00118000, 0x003C Bytes, ...) -- CPU_ReadMem(60 bytes @ 0x00118000) - Data: FE E7 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... returns 0x00 (0001ms, 1883ms total)
|
||||
T220C 002:517 JLINK_ReadMem (0x001001DA, 0x0002 Bytes, ...) -- CPU_ReadMem(2 bytes @ 0x001001DA) - Data: 00 47 returns 0x00 (0001ms, 1884ms total)
|
||||
T220C 002:518 JLINK_ReadMem (0x001001DC, 0x003C Bytes, ...) -- CPU_ReadMem(60 bytes @ 0x001001DC) - Data: 4F F0 01 07 FE E7 4F F0 02 07 FE E7 4F F0 03 07 ... returns 0x00 (0001ms, 1885ms total)
|
||||
T220C 002:601 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 1885ms total)
|
||||
T220C 002:601 JLINK_Reset() -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x48 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)
|
||||
-- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0)Could not set S_RESET_ST -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0646ms, 2531ms total)
|
||||
T220C 003:248 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2531ms total)
|
||||
T220C 003:249 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2531ms total)
|
||||
T220C 003:249 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 00 00 00 00 returns 0x01 (0000ms, 2531ms total)
|
||||
T1854 003:277 JLINK_Step() -- CPU_ReadMem(2 bytes @ 0x00118000) -- Simulated returns 0x00 (0001ms, 2532ms total)
|
||||
T1854 003:278 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2532ms total)
|
||||
T1854 003:278 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2532ms total)
|
||||
T1854 003:278 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 2532ms total)
|
||||
T1854 003:278 JLINK_ReadReg(R1) returns 0x00100000 (0000ms, 2532ms total)
|
||||
T1854 003:278 JLINK_ReadReg(R2) returns 0x000002AC (0000ms, 2532ms total)
|
||||
T1854 003:278 JLINK_ReadReg(R3) returns 0x04C11DB7 (0000ms, 2532ms total)
|
||||
T1854 003:278 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 2532ms total)
|
||||
T1854 003:278 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 2532ms total)
|
||||
T1854 003:278 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 2532ms total)
|
||||
T1854 003:278 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 2532ms total)
|
||||
T1854 003:278 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 2532ms total)
|
||||
T1854 003:278 JLINK_ReadReg(R9) returns 0x0011804C (0000ms, 2532ms total)
|
||||
T1854 003:278 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 2532ms total)
|
||||
T1854 003:278 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 2532ms total)
|
||||
T1854 003:278 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 2532ms total)
|
||||
T1854 003:278 JLINK_ReadReg(R13 (SP)) returns 0x00118800 (0000ms, 2532ms total)
|
||||
T1854 003:278 JLINK_ReadReg(R14) returns 0x00118001 (0000ms, 2532ms total)
|
||||
T1854 003:278 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2532ms total)
|
||||
T1854 003:278 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2532ms total)
|
||||
T1854 003:278 JLINK_ReadReg(MSP) returns 0x00118800 (0000ms, 2532ms total)
|
||||
T1854 003:278 JLINK_ReadReg(PSP) returns 0x00118800 (0000ms, 2532ms total)
|
||||
T1854 003:278 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 2532ms total)
|
||||
T1854 003:278 JLINK_ReadReg(FPSCR) returns 0x00000000 (0005ms, 2537ms total)
|
||||
T1854 003:283 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:283 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:283 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:283 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:283 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:283 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:283 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:283 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:283 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:283 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:283 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:283 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:283 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:283 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:283 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:283 JLINK_ReadReg(FPS15) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:283 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:284 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:284 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:284 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:284 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:284 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:284 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:284 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:284 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:284 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:284 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:284 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:284 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:284 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:284 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:284 JLINK_ReadReg(FPS31) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:292 JLINK_Step() -- CPU_ReadMem(2 bytes @ 0x00118000) -- Simulated returns 0x00 (0000ms, 2537ms total)
|
||||
T1854 003:292 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2537ms total)
|
||||
T1854 003:292 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2537ms total)
|
||||
T1854 003:293 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:293 JLINK_ReadReg(R1) returns 0x00100000 (0000ms, 2537ms total)
|
||||
T1854 003:293 JLINK_ReadReg(R2) returns 0x000002AC (0000ms, 2537ms total)
|
||||
T1854 003:293 JLINK_ReadReg(R3) returns 0x04C11DB7 (0000ms, 2537ms total)
|
||||
T1854 003:293 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:293 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:293 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:293 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:293 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:293 JLINK_ReadReg(R9) returns 0x0011804C (0000ms, 2537ms total)
|
||||
T1854 003:293 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:293 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:293 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:293 JLINK_ReadReg(R13 (SP)) returns 0x00118800 (0000ms, 2537ms total)
|
||||
T1854 003:293 JLINK_ReadReg(R14) returns 0x00118001 (0000ms, 2537ms total)
|
||||
T1854 003:293 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2537ms total)
|
||||
T1854 003:293 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2537ms total)
|
||||
T1854 003:293 JLINK_ReadReg(MSP) returns 0x00118800 (0000ms, 2537ms total)
|
||||
T1854 003:293 JLINK_ReadReg(PSP) returns 0x00118800 (0000ms, 2537ms total)
|
||||
T1854 003:293 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:293 JLINK_ReadReg(FPSCR) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:293 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:293 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:293 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:293 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:293 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:293 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:293 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:293 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 2537ms total)
|
||||
T1854 003:293 JLINK_ReadReg(FPS8) returns 0x00000000 (0001ms, 2538ms total)
|
||||
T1854 003:294 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 2538ms total)
|
||||
T1854 003:294 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 2538ms total)
|
||||
T1854 003:294 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 2538ms total)
|
||||
T1854 003:294 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 2538ms total)
|
||||
T1854 003:294 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 2538ms total)
|
||||
T1854 003:294 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 2538ms total)
|
||||
T1854 003:294 JLINK_ReadReg(FPS15) returns 0x00000000 (0000ms, 2538ms total)
|
||||
T1854 003:294 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 2538ms total)
|
||||
T1854 003:294 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 2538ms total)
|
||||
T1854 003:294 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 2538ms total)
|
||||
T1854 003:294 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 2538ms total)
|
||||
T1854 003:294 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 2538ms total)
|
||||
T1854 003:294 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 2538ms total)
|
||||
T1854 003:294 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 2538ms total)
|
||||
T1854 003:294 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 2538ms total)
|
||||
T1854 003:294 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 2538ms total)
|
||||
T1854 003:294 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 2538ms total)
|
||||
T1854 003:294 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 2538ms total)
|
||||
T1854 003:294 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 2538ms total)
|
||||
T1854 003:294 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 2538ms total)
|
||||
T1854 003:294 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 2538ms total)
|
||||
T1854 003:294 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 2538ms total)
|
||||
T1854 003:294 JLINK_ReadReg(FPS31) returns 0x00000000 (0000ms, 2538ms total)
|
||||
T1854 003:297 JLINK_Step() -- CPU_ReadMem(2 bytes @ 0x00118000) -- Simulated returns 0x00 (0000ms, 2538ms total)
|
||||
T1854 003:297 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2538ms total)
|
||||
T1854 003:297 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2538ms total)
|
||||
T1854 003:297 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 2538ms total)
|
||||
T1854 003:297 JLINK_ReadReg(R1) returns 0x00100000 (0000ms, 2538ms total)
|
||||
T1854 003:297 JLINK_ReadReg(R2) returns 0x000002AC (0000ms, 2538ms total)
|
||||
T1854 003:297 JLINK_ReadReg(R3) returns 0x04C11DB7 (0000ms, 2538ms total)
|
||||
T1854 003:297 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 2538ms total)
|
||||
T1854 003:297 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 2538ms total)
|
||||
T1854 003:297 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 2538ms total)
|
||||
T1854 003:297 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 2538ms total)
|
||||
T1854 003:297 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 2538ms total)
|
||||
T1854 003:297 JLINK_ReadReg(R9) returns 0x0011804C (0000ms, 2538ms total)
|
||||
T1854 003:297 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 2538ms total)
|
||||
T1854 003:297 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 2538ms total)
|
||||
T1854 003:297 JLINK_ReadReg(R12) returns 0x00000000 (0001ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(R13 (SP)) returns 0x00118800 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(R14) returns 0x00118001 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(R15 (PC)) returns 0x00118000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(XPSR) returns 0x41000000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(MSP) returns 0x00118800 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(PSP) returns 0x00118800 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(CFBP) returns 0x00000000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(FPSCR) returns 0x00000000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(FPS15) returns 0x00000000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 2539ms total)
|
||||
T1854 003:298 JLINK_ReadReg(FPS31) returns 0x00000000 (0000ms, 2539ms total)
|
||||
T220C 003:312 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) - Data: 00 00 00 00 returns 0x01 (0000ms, 2539ms total)
|
||||
T220C 027:508 JLINK_Close() -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0001004) >0x78 JTAG> >0x08 JTAG> (0005ms, 2544ms total)
|
||||
T220C 027:508 (0005ms, 2544ms total)
|
||||
T220C 027:508 Closed (0005ms, 2544ms total)
|
||||
@ -0,0 +1,35 @@
|
||||
[BREAKPOINTS]
|
||||
ForceImpTypeAny = 0
|
||||
ShowInfoWin = 1
|
||||
EnableFlashBP = 2
|
||||
BPDuringExecution = 0
|
||||
[CFI]
|
||||
CFISize = 0x00
|
||||
CFIAddr = 0x00
|
||||
[CPU]
|
||||
OverrideMemMap = 0
|
||||
AllowSimulation = 1
|
||||
ScriptFile=""
|
||||
[FLASH]
|
||||
CacheExcludeSize = 0x00
|
||||
CacheExcludeAddr = 0x00
|
||||
MinNumBytesFlashDL = 0
|
||||
SkipProgOnCRCMatch = 1
|
||||
VerifyDownload = 1
|
||||
AllowCaching = 1
|
||||
EnableFlashDL = 2
|
||||
Override = 1
|
||||
Device="Unspecified"
|
||||
[GENERAL]
|
||||
WorkRAMSize = 0x00
|
||||
WorkRAMAddr = 0x00
|
||||
RAMUsageLimit = 0x00
|
||||
[SWO]
|
||||
SWOLogFile=""
|
||||
[MEM]
|
||||
RdOverrideOrMask = 0x00
|
||||
RdOverrideAndMask = 0xFFFFFFFF
|
||||
RdOverrideAddr = 0xFFFFFFFF
|
||||
WrOverrideOrMask = 0x00
|
||||
WrOverrideAndMask = 0xFFFFFFFF
|
||||
WrOverrideAddr = 0xFFFFFFFF
|
||||
@ -0,0 +1,28 @@
|
||||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
|
||||
LR_IROM1 0x00100000 0x00020000 { ; load region size_region
|
||||
ER_IROM1 0x00000000 0x00000000 { ; load address = execution address
|
||||
}
|
||||
RW_IRAM1 0x00100000 0x00020000 { ; RW data
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
;LR_IROM1 0x00100000 0x00018000 { ; load region size_region
|
||||
; ER_IROM1 0x00100000 0x00018000 { ; load address = execution address
|
||||
; *.o (RESET, +First)
|
||||
; *(InRoot$$Sections)
|
||||
; .ANY (+RO)
|
||||
; }
|
||||
; RW_IRAM1 0x00118000 0x00008000 { ; RW data
|
||||
; .ANY (+RW +ZI)
|
||||
; }
|
||||
;}
|
||||
|
||||
@ -0,0 +1,682 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>RTOSDemo</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>48000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\Listings\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>7</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<nTsel>1</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile>init_app.ini</tIfile>
|
||||
<pMon>BIN\UL2CM3.DLL</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGDARM</Key>
|
||||
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGUARM</Key>
|
||||
<Name>(105=-1,-1,-1,-1,0)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ARMRTXEVENTFLAGS</Key>
|
||||
<Name>-L70 -Z18 -C0 -M0 -T1</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGTARM</Key>
|
||||
<Name>(1010=1231,224,1641,767,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ARMDBGFLAGS</Key>
|
||||
<Name>-T0</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2CM3</Key>
|
||||
<Name>-UV1115SAE -O2983 -S0 -C0 -P00 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO11 -FD118000 -FC8000 -FN1 -FF0NEW_DEVICE.FLM -FS0100000 -FL018000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<WatchWindow1>
|
||||
<Ww>
|
||||
<count>0</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>ulLED,0x0A</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>1</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>xTickCount,0x0A</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>2</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>ulErrorFound</ItemText>
|
||||
</Ww>
|
||||
<Ww>
|
||||
<count>3</count>
|
||||
<WinNumber>1</WinNumber>
|
||||
<ItemText>ulMaxRecordedNestingDepth</ItemText>
|
||||
</Ww>
|
||||
</WatchWindow1>
|
||||
<MemoryWindow1>
|
||||
<Mm>
|
||||
<WinNumber>1</WinNumber>
|
||||
<SubType>2</SubType>
|
||||
<ItemText>0xe000e284</ItemText>
|
||||
<AccSizeX>4</AccSizeX>
|
||||
</Mm>
|
||||
</MemoryWindow1>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>1</periodic>
|
||||
<aLwin>0</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>1</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
<Group>
|
||||
<GroupName>System</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>1</FileNumber>
|
||||
<FileType>2</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\startup_CEC1302.s</PathWithFileName>
|
||||
<FilenameWithoutPath>startup_CEC1302.s</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>2</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\system.c</PathWithFileName>
|
||||
<FilenameWithoutPath>system.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>main_and_config</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>2</GroupNumber>
|
||||
<FileNumber>3</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\main.c</PathWithFileName>
|
||||
<FilenameWithoutPath>main.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>2</GroupNumber>
|
||||
<FileNumber>4</FileNumber>
|
||||
<FileType>5</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\FreeRTOSConfig.h</PathWithFileName>
|
||||
<FilenameWithoutPath>FreeRTOSConfig.h</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>FreeRTOS_Source</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>3</GroupNumber>
|
||||
<FileNumber>5</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\Source\event_groups.c</PathWithFileName>
|
||||
<FilenameWithoutPath>event_groups.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>3</GroupNumber>
|
||||
<FileNumber>6</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\Source\list.c</PathWithFileName>
|
||||
<FilenameWithoutPath>list.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>3</GroupNumber>
|
||||
<FileNumber>7</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\Source\queue.c</PathWithFileName>
|
||||
<FilenameWithoutPath>queue.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>3</GroupNumber>
|
||||
<FileNumber>8</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\Source\tasks.c</PathWithFileName>
|
||||
<FilenameWithoutPath>tasks.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>3</GroupNumber>
|
||||
<FileNumber>9</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\Source\timers.c</PathWithFileName>
|
||||
<FilenameWithoutPath>timers.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>3</GroupNumber>
|
||||
<FileNumber>10</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\Source\portable\MemMang\heap_4.c</PathWithFileName>
|
||||
<FilenameWithoutPath>heap_4.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>3</GroupNumber>
|
||||
<FileNumber>11</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\Source\portable\RVDS\ARM_CM4F\port.c</PathWithFileName>
|
||||
<FilenameWithoutPath>port.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>main_low_power</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>4</GroupNumber>
|
||||
<FileNumber>12</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\main_low_power\main_low_power.c</PathWithFileName>
|
||||
<FilenameWithoutPath>main_low_power.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>4</GroupNumber>
|
||||
<FileNumber>13</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\main_low_power\low_power_tick_config.c</PathWithFileName>
|
||||
<FilenameWithoutPath>low_power_tick_config.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>main_full</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>5</GroupNumber>
|
||||
<FileNumber>14</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\main_full\main_full.c</PathWithFileName>
|
||||
<FilenameWithoutPath>main_full.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>5</GroupNumber>
|
||||
<FileNumber>15</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\RegTest.c</PathWithFileName>
|
||||
<FilenameWithoutPath>RegTest.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>5</GroupNumber>
|
||||
<FileNumber>16</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\Common\Minimal\flop.c</PathWithFileName>
|
||||
<FilenameWithoutPath>flop.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>5</GroupNumber>
|
||||
<FileNumber>17</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\Common\Minimal\EventGroupsDemo.c</PathWithFileName>
|
||||
<FilenameWithoutPath>EventGroupsDemo.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>5</GroupNumber>
|
||||
<FileNumber>18</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\Common\Minimal\TaskNotify.c</PathWithFileName>
|
||||
<FilenameWithoutPath>TaskNotify.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>5</GroupNumber>
|
||||
<FileNumber>19</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\Common\Minimal\blocktim.c</PathWithFileName>
|
||||
<FilenameWithoutPath>blocktim.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>5</GroupNumber>
|
||||
<FileNumber>20</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\Common\Minimal\dynamic.c</PathWithFileName>
|
||||
<FilenameWithoutPath>dynamic.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>5</GroupNumber>
|
||||
<FileNumber>21</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\Common\Minimal\GenQTest.c</PathWithFileName>
|
||||
<FilenameWithoutPath>GenQTest.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>5</GroupNumber>
|
||||
<FileNumber>22</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\Common\Minimal\TimerDemo.c</PathWithFileName>
|
||||
<FilenameWithoutPath>TimerDemo.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>5</GroupNumber>
|
||||
<FileNumber>23</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\Common\Minimal\IntQueue.c</PathWithFileName>
|
||||
<FilenameWithoutPath>IntQueue.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>5</GroupNumber>
|
||||
<FileNumber>24</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\main_full\IntQueueTimer.c</PathWithFileName>
|
||||
<FilenameWithoutPath>IntQueueTimer.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>5</GroupNumber>
|
||||
<FileNumber>25</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\Common\Minimal\BlockQ.c</PathWithFileName>
|
||||
<FilenameWithoutPath>BlockQ.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>5</GroupNumber>
|
||||
<FileNumber>26</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\Common\Minimal\countsem.c</PathWithFileName>
|
||||
<FilenameWithoutPath>countsem.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>5</GroupNumber>
|
||||
<FileNumber>27</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\Common\Minimal\recmutex.c</PathWithFileName>
|
||||
<FilenameWithoutPath>recmutex.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>5</GroupNumber>
|
||||
<FileNumber>28</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\Common\Minimal\semtest.c</PathWithFileName>
|
||||
<FilenameWithoutPath>semtest.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>5</GroupNumber>
|
||||
<FileNumber>29</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\Common\Minimal\death.c</PathWithFileName>
|
||||
<FilenameWithoutPath>death.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>peripheral_library</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>6</GroupNumber>
|
||||
<FileNumber>30</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\peripheral_library\basic_timer\btimer_api.c</PathWithFileName>
|
||||
<FilenameWithoutPath>btimer_api.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>6</GroupNumber>
|
||||
<FileNumber>31</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\peripheral_library\basic_timer\btimer_perphl.c</PathWithFileName>
|
||||
<FilenameWithoutPath>btimer_perphl.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>6</GroupNumber>
|
||||
<FileNumber>32</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\peripheral_library\pcr\pcr_api.c</PathWithFileName>
|
||||
<FilenameWithoutPath>pcr_api.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>6</GroupNumber>
|
||||
<FileNumber>33</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\peripheral_library\pcr\pcr_perphl.c</PathWithFileName>
|
||||
<FilenameWithoutPath>pcr_perphl.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>6</GroupNumber>
|
||||
<FileNumber>34</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\peripheral_library\htimer\htimer_api.c</PathWithFileName>
|
||||
<FilenameWithoutPath>htimer_api.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>6</GroupNumber>
|
||||
<FileNumber>35</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\peripheral_library\htimer\htimer_perphl.c</PathWithFileName>
|
||||
<FilenameWithoutPath>htimer_perphl.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
</ProjectOpt>
|
||||
@ -0,0 +1,689 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
||||
|
||||
<SchemaVersion>2.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>RTOSDemo</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<pCCUsed>5060061::V5.06 update 1 (build 61)::ARMCC</pCCUsed>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>ARMCM4_FP</Device>
|
||||
<Vendor>ARM</Vendor>
|
||||
<PackID>ARM.CMSIS.4.5.0</PackID>
|
||||
<PackURL>http://www.keil.com/pack/</PackURL>
|
||||
<Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM))</FlashDriverDll>
|
||||
<DeviceId>0</DeviceId>
|
||||
<RegisterFile>$$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>$$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd</SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath></RegisterFilePath>
|
||||
<DBRegisterFilePath></DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\Objects\</OutputDirectory>
|
||||
<OutputName>RTOSDemo</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>1</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\Listings\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments> -MPU</SimDllArguments>
|
||||
<SimDlgDll>DCM.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments> -MPU</TargetDllArguments>
|
||||
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
<Simulator>
|
||||
<UseSimulator>0</UseSimulator>
|
||||
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||
<RunToMain>1</RunToMain>
|
||||
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||
<RestoreFunctions>1</RestoreFunctions>
|
||||
<RestoreToolbox>1</RestoreToolbox>
|
||||
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
|
||||
<RestoreSysVw>1</RestoreSysVw>
|
||||
</Simulator>
|
||||
<Target>
|
||||
<UseTarget>1</UseTarget>
|
||||
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||
<RunToMain>1</RunToMain>
|
||||
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||
<RestoreFunctions>0</RestoreFunctions>
|
||||
<RestoreToolbox>1</RestoreToolbox>
|
||||
<RestoreTracepoints>1</RestoreTracepoints>
|
||||
<RestoreSysVw>1</RestoreSysVw>
|
||||
</Target>
|
||||
<RunDebugAfterBuild>0</RunDebugAfterBuild>
|
||||
<TargetSelection>1</TargetSelection>
|
||||
<SimDlls>
|
||||
<CpuDll></CpuDll>
|
||||
<CpuDllArguments></CpuDllArguments>
|
||||
<PeripheralDll></PeripheralDll>
|
||||
<PeripheralDllArguments></PeripheralDllArguments>
|
||||
<InitializationFile></InitializationFile>
|
||||
</SimDlls>
|
||||
<TargetDlls>
|
||||
<CpuDll></CpuDll>
|
||||
<CpuDllArguments></CpuDllArguments>
|
||||
<PeripheralDll></PeripheralDll>
|
||||
<PeripheralDllArguments></PeripheralDllArguments>
|
||||
<InitializationFile>init_app.ini</InitializationFile>
|
||||
<Driver>BIN\UL2CM3.DLL</Driver>
|
||||
</TargetDlls>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>4096</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||
<Flash3>"" ()</Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>1</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M4"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>2</RvdsVP>
|
||||
<hadIRAM2>0</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>1</useUlib>
|
||||
<EndSel>1</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>3</RoSelD>
|
||||
<RwSelD>3</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>1</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x80000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x100000</StartAddress>
|
||||
<Size>0x18000</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x118000</StartAddress>
|
||||
<Size>0x8000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>1</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>1</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>2</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>0</uC99>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>0</v6Lang>
|
||||
<v6LangP>0</v6LangP>
|
||||
<vShortEn>0</vShortEn>
|
||||
<vShortWch>0</vShortWch>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath>..;..\..\..\Source\include;..\..\..\Source\portable\RVDS\ARM_CM4F;..\..\Common\include;..\peripheral_library;..\CMSIS;..\main_full</IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>0</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x00000000</TextAddressRange>
|
||||
<DataAddressRange>0x20000000</DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile>RTOSDemo.sct</ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc></Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
<Group>
|
||||
<GroupName>System</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>startup_CEC1302.s</FileName>
|
||||
<FileType>2</FileType>
|
||||
<FilePath>.\startup_CEC1302.s</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>system.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\system.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>main_and_config</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>main.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\main.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>FreeRTOSConfig.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>..\FreeRTOSConfig.h</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>FreeRTOS_Source</GroupName>
|
||||
<GroupOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>2</AlwaysBuild>
|
||||
<GenerateAssemblyFile>2</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>2</AssembleAssemblyFile>
|
||||
<PublicsOnly>2</PublicsOnly>
|
||||
<StopOnExitCode>11</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<GroupArmAds>
|
||||
<Cads>
|
||||
<interw>2</interw>
|
||||
<Optim>0</Optim>
|
||||
<oTime>2</oTime>
|
||||
<SplitLS>2</SplitLS>
|
||||
<OneElfS>2</OneElfS>
|
||||
<Strict>2</Strict>
|
||||
<EnumInt>2</EnumInt>
|
||||
<PlainCh>2</PlainCh>
|
||||
<Ropi>2</Ropi>
|
||||
<Rwpi>2</Rwpi>
|
||||
<wLevel>2</wLevel>
|
||||
<uThumb>2</uThumb>
|
||||
<uSurpInc>2</uSurpInc>
|
||||
<uC99>2</uC99>
|
||||
<useXO>2</useXO>
|
||||
<v6Lang>0</v6Lang>
|
||||
<v6LangP>0</v6LangP>
|
||||
<vShortEn>0</vShortEn>
|
||||
<vShortWch>0</vShortWch>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>2</interw>
|
||||
<Ropi>2</Ropi>
|
||||
<Rwpi>2</Rwpi>
|
||||
<thumb>2</thumb>
|
||||
<SplitLS>2</SplitLS>
|
||||
<SwStkChk>2</SwStkChk>
|
||||
<NoWarn>2</NoWarn>
|
||||
<uSurpInc>2</uSurpInc>
|
||||
<useXO>2</useXO>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
</GroupArmAds>
|
||||
</GroupOption>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>event_groups.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Source\event_groups.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>list.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Source\list.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>queue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Source\queue.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tasks.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Source\tasks.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>timers.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Source\timers.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>heap_4.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Source\portable\MemMang\heap_4.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>port.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\Source\portable\RVDS\ARM_CM4F\port.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>main_low_power</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>main_low_power.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\main_low_power\main_low_power.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>low_power_tick_config.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\main_low_power\low_power_tick_config.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>main_full</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>main_full.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\main_full\main_full.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>RegTest.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\RegTest.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>flop.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Common\Minimal\flop.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>EventGroupsDemo.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Common\Minimal\EventGroupsDemo.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>TaskNotify.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Common\Minimal\TaskNotify.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>blocktim.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Common\Minimal\blocktim.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>dynamic.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Common\Minimal\dynamic.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>GenQTest.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Common\Minimal\GenQTest.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>TimerDemo.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Common\Minimal\TimerDemo.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>IntQueue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Common\Minimal\IntQueue.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>IntQueueTimer.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\main_full\IntQueueTimer.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>BlockQ.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Common\Minimal\BlockQ.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>countsem.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Common\Minimal\countsem.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>recmutex.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Common\Minimal\recmutex.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>semtest.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Common\Minimal\semtest.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>death.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Common\Minimal\death.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>peripheral_library</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>btimer_api.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\peripheral_library\basic_timer\btimer_api.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>btimer_perphl.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\peripheral_library\basic_timer\btimer_perphl.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>pcr_api.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\peripheral_library\pcr\pcr_api.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>pcr_perphl.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\peripheral_library\pcr\pcr_perphl.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>htimer_api.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\peripheral_library\htimer\htimer_api.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>htimer_perphl.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\peripheral_library\htimer\htimer_perphl.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
</Project>
|
||||
@ -0,0 +1,454 @@
|
||||
/*
|
||||
FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
|
||||
All rights reserved
|
||||
|
||||
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
|
||||
|
||||
***************************************************************************
|
||||
>>! NOTE: The modification to the GPL is included to allow you to !<<
|
||||
>>! distribute a combined work that includes FreeRTOS without being !<<
|
||||
>>! obliged to provide the source code for proprietary components !<<
|
||||
>>! outside of the FreeRTOS kernel. !<<
|
||||
***************************************************************************
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
|
||||
FOR A PARTICULAR PURPOSE. Full license text is available on the following
|
||||
link: http://www.freertos.org/a00114.html
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS provides completely free yet professionally developed, *
|
||||
* robust, strictly quality controlled, supported, and cross *
|
||||
* platform software that is more than just the market leader, it *
|
||||
* is the industry's de facto standard. *
|
||||
* *
|
||||
* Help yourself get started quickly while simultaneously helping *
|
||||
* to support the FreeRTOS project by purchasing a FreeRTOS *
|
||||
* tutorial book, reference manual, or both: *
|
||||
* http://www.FreeRTOS.org/Documentation *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
|
||||
the FAQ page "My application does not run, what could be wrong?". Have you
|
||||
defined configASSERT()?
|
||||
|
||||
http://www.FreeRTOS.org/support - In return for receiving this top quality
|
||||
embedded software for free we request you assist our global community by
|
||||
participating in the support forum.
|
||||
|
||||
http://www.FreeRTOS.org/training - Investing in training allows your team to
|
||||
be as productive as possible as early as possible. Now you can receive
|
||||
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
|
||||
Ltd, and the world's leading authority on the world's leading RTOS.
|
||||
|
||||
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
|
||||
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
|
||||
compatible FAT file system, and our tiny thread aware UDP/IP stack.
|
||||
|
||||
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
|
||||
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
|
||||
|
||||
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
|
||||
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
|
||||
licenses offer ticketed support, indemnification and commercial middleware.
|
||||
|
||||
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
|
||||
engineered and independently SIL3 certified version for use in safety and
|
||||
mission critical applications that require provable dependability.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
/*
|
||||
* "Reg test" tasks - These fill the registers with known values, then check
|
||||
* that each register maintains its expected value for the lifetime of the
|
||||
* task. Each task uses a different set of values. The reg test tasks execute
|
||||
* with a very low priority, so get preempted very frequently. A register
|
||||
* containing an unexpected value is indicative of an error in the context
|
||||
* switching mechanism.
|
||||
*/
|
||||
|
||||
|
||||
__asm void vRegTest1Implementation( void )
|
||||
{
|
||||
PRESERVE8
|
||||
IMPORT ulRegTest1LoopCounter
|
||||
|
||||
/* Fill the core registers with known values. */
|
||||
mov r0, #100
|
||||
mov r1, #101
|
||||
mov r2, #102
|
||||
mov r3, #103
|
||||
mov r4, #104
|
||||
mov r5, #105
|
||||
mov r6, #106
|
||||
mov r7, #107
|
||||
mov r8, #108
|
||||
mov r9, #109
|
||||
mov r10, #110
|
||||
mov r11, #111
|
||||
mov r12, #112
|
||||
|
||||
/* Fill the VFP registers with known values. */
|
||||
vmov d0, r0, r1
|
||||
vmov d1, r2, r3
|
||||
vmov d2, r4, r5
|
||||
vmov d3, r6, r7
|
||||
vmov d4, r8, r9
|
||||
vmov d5, r10, r11
|
||||
vmov d6, r0, r1
|
||||
vmov d7, r2, r3
|
||||
vmov d8, r4, r5
|
||||
vmov d9, r6, r7
|
||||
vmov d10, r8, r9
|
||||
vmov d11, r10, r11
|
||||
vmov d12, r0, r1
|
||||
vmov d13, r2, r3
|
||||
vmov d14, r4, r5
|
||||
vmov d15, r6, r7
|
||||
|
||||
reg1_loop
|
||||
/* Check all the VFP registers still contain the values set above.
|
||||
First save registers that are clobbered by the test. */
|
||||
push { r0-r1 }
|
||||
|
||||
vmov r0, r1, d0
|
||||
cmp r0, #100
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #101
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d1
|
||||
cmp r0, #102
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #103
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d2
|
||||
cmp r0, #104
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #105
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d3
|
||||
cmp r0, #106
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #107
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d4
|
||||
cmp r0, #108
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #109
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d5
|
||||
cmp r0, #110
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #111
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d6
|
||||
cmp r0, #100
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #101
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d7
|
||||
cmp r0, #102
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #103
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d8
|
||||
cmp r0, #104
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #105
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d9
|
||||
cmp r0, #106
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #107
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d10
|
||||
cmp r0, #108
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #109
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d11
|
||||
cmp r0, #110
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #111
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d12
|
||||
cmp r0, #100
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #101
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d13
|
||||
cmp r0, #102
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #103
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d14
|
||||
cmp r0, #104
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #105
|
||||
bne reg1_error_loopf
|
||||
vmov r0, r1, d15
|
||||
cmp r0, #106
|
||||
bne reg1_error_loopf
|
||||
cmp r1, #107
|
||||
bne reg1_error_loopf
|
||||
|
||||
/* Restore the registers that were clobbered by the test. */
|
||||
pop {r0-r1}
|
||||
|
||||
/* VFP register test passed. Jump to the core register test. */
|
||||
b reg1_loopf_pass
|
||||
|
||||
reg1_error_loopf
|
||||
/* If this line is hit then a VFP register value was found to be
|
||||
incorrect. */
|
||||
b reg1_error_loopf
|
||||
|
||||
reg1_loopf_pass
|
||||
|
||||
cmp r0, #100
|
||||
bne reg1_error_loop
|
||||
cmp r1, #101
|
||||
bne reg1_error_loop
|
||||
cmp r2, #102
|
||||
bne reg1_error_loop
|
||||
cmp r3, #103
|
||||
bne reg1_error_loop
|
||||
cmp r4, #104
|
||||
bne reg1_error_loop
|
||||
cmp r5, #105
|
||||
bne reg1_error_loop
|
||||
cmp r6, #106
|
||||
bne reg1_error_loop
|
||||
cmp r7, #107
|
||||
bne reg1_error_loop
|
||||
cmp r8, #108
|
||||
bne reg1_error_loop
|
||||
cmp r9, #109
|
||||
bne reg1_error_loop
|
||||
cmp r10, #110
|
||||
bne reg1_error_loop
|
||||
cmp r11, #111
|
||||
bne reg1_error_loop
|
||||
cmp r12, #112
|
||||
bne reg1_error_loop
|
||||
|
||||
/* Everything passed, increment the loop counter. */
|
||||
push { r0-r1 }
|
||||
ldr r0, =ulRegTest1LoopCounter
|
||||
ldr r1, [r0]
|
||||
adds r1, r1, #1
|
||||
str r1, [r0]
|
||||
pop { r0-r1 }
|
||||
|
||||
/* Start again. */
|
||||
b reg1_loop
|
||||
|
||||
reg1_error_loop
|
||||
/* If this line is hit then there was an error in a core register value.
|
||||
The loop ensures the loop counter stops incrementing. */
|
||||
b reg1_error_loop
|
||||
nop
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
__asm void vRegTest2Implementation( void )
|
||||
{
|
||||
PRESERVE8
|
||||
IMPORT ulRegTest2LoopCounter
|
||||
|
||||
/* Set all the core registers to known values. */
|
||||
mov r0, #-1
|
||||
mov r1, #1
|
||||
mov r2, #2
|
||||
mov r3, #3
|
||||
mov r4, #4
|
||||
mov r5, #5
|
||||
mov r6, #6
|
||||
mov r7, #7
|
||||
mov r8, #8
|
||||
mov r9, #9
|
||||
mov r10, #10
|
||||
mov r11, #11
|
||||
mov r12, #12
|
||||
|
||||
/* Set all the VFP to known values. */
|
||||
vmov d0, r0, r1
|
||||
vmov d1, r2, r3
|
||||
vmov d2, r4, r5
|
||||
vmov d3, r6, r7
|
||||
vmov d4, r8, r9
|
||||
vmov d5, r10, r11
|
||||
vmov d6, r0, r1
|
||||
vmov d7, r2, r3
|
||||
vmov d8, r4, r5
|
||||
vmov d9, r6, r7
|
||||
vmov d10, r8, r9
|
||||
vmov d11, r10, r11
|
||||
vmov d12, r0, r1
|
||||
vmov d13, r2, r3
|
||||
vmov d14, r4, r5
|
||||
vmov d15, r6, r7
|
||||
|
||||
reg2_loop
|
||||
|
||||
/* Check all the VFP registers still contain the values set above.
|
||||
First save registers that are clobbered by the test. */
|
||||
push { r0-r1 }
|
||||
|
||||
vmov r0, r1, d0
|
||||
cmp r0, #-1
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #1
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d1
|
||||
cmp r0, #2
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #3
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d2
|
||||
cmp r0, #4
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #5
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d3
|
||||
cmp r0, #6
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #7
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d4
|
||||
cmp r0, #8
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #9
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d5
|
||||
cmp r0, #10
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #11
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d6
|
||||
cmp r0, #-1
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #1
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d7
|
||||
cmp r0, #2
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #3
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d8
|
||||
cmp r0, #4
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #5
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d9
|
||||
cmp r0, #6
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #7
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d10
|
||||
cmp r0, #8
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #9
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d11
|
||||
cmp r0, #10
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #11
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d12
|
||||
cmp r0, #-1
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #1
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d13
|
||||
cmp r0, #2
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #3
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d14
|
||||
cmp r0, #4
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #5
|
||||
bne reg2_error_loopf
|
||||
vmov r0, r1, d15
|
||||
cmp r0, #6
|
||||
bne reg2_error_loopf
|
||||
cmp r1, #7
|
||||
bne reg2_error_loopf
|
||||
|
||||
/* Restore the registers that were clobbered by the test. */
|
||||
pop {r0-r1}
|
||||
|
||||
/* VFP register test passed. Jump to the core register test. */
|
||||
b reg2_loopf_pass
|
||||
|
||||
reg2_error_loopf
|
||||
/* If this line is hit then a VFP register value was found to be
|
||||
incorrect. */
|
||||
b reg2_error_loopf
|
||||
|
||||
reg2_loopf_pass
|
||||
|
||||
cmp r0, #-1
|
||||
bne reg2_error_loop
|
||||
cmp r1, #1
|
||||
bne reg2_error_loop
|
||||
cmp r2, #2
|
||||
bne reg2_error_loop
|
||||
cmp r3, #3
|
||||
bne reg2_error_loop
|
||||
cmp r4, #4
|
||||
bne reg2_error_loop
|
||||
cmp r5, #5
|
||||
bne reg2_error_loop
|
||||
cmp r6, #6
|
||||
bne reg2_error_loop
|
||||
cmp r7, #7
|
||||
bne reg2_error_loop
|
||||
cmp r8, #8
|
||||
bne reg2_error_loop
|
||||
cmp r9, #9
|
||||
bne reg2_error_loop
|
||||
cmp r10, #10
|
||||
bne reg2_error_loop
|
||||
cmp r11, #11
|
||||
bne reg2_error_loop
|
||||
cmp r12, #12
|
||||
bne reg2_error_loop
|
||||
|
||||
/* Increment the loop counter to indicate this test is still functioning
|
||||
correctly. */
|
||||
push { r0-r1 }
|
||||
ldr r0, =ulRegTest2LoopCounter
|
||||
ldr r1, [r0]
|
||||
adds r1, r1, #1
|
||||
str r1, [r0]
|
||||
|
||||
/* Yield to increase test coverage. */
|
||||
movs r0, #0x01
|
||||
ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */
|
||||
lsl r0, r0, #28 /* Shift to PendSV bit */
|
||||
str r0, [r1]
|
||||
dsb
|
||||
|
||||
pop { r0-r1 }
|
||||
|
||||
/* Start again. */
|
||||
b reg2_loop
|
||||
|
||||
reg2_error_loop
|
||||
/* If this line is hit then there was an error in a core register value.
|
||||
This loop ensures the loop counter variable stops incrementing. */
|
||||
b reg2_error_loop
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
@ -0,0 +1,7 @@
|
||||
//Initialization file for the application code
|
||||
RESET
|
||||
T
|
||||
T
|
||||
T
|
||||
eval PC = *(&(__Vectors) + 1) ; // startup code loc to the Jump routine
|
||||
T
|
||||
@ -0,0 +1,496 @@
|
||||
;/*
|
||||
;******************************************************************************
|
||||
;* © 2013 Microchip Technology Inc. and its subsidiaries.
|
||||
;* You may use this software and any derivatives exclusively with
|
||||
;* Microchip products.
|
||||
;* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
;* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
;* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
;* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
;* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
;* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
;* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
;* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
;* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
;* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
;* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
;* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
;* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
;* OF THESE TERMS.
|
||||
;******************************************************************************
|
||||
; */
|
||||
;/** @file startup_MEC1322.s
|
||||
; *MEC1322 API Test: startup and vector table
|
||||
; */
|
||||
;/** @defgroup startup_MEC1322
|
||||
; * @{
|
||||
; */
|
||||
|
||||
IMPORT __main
|
||||
IMPORT |Image$$RW_IRAM1$$Base|
|
||||
IMPORT |Image$$RW_IRAM1$$Limit|
|
||||
IMPORT |Image$$RW_IRAM1$$Length|
|
||||
IMPORT |Image$$RW_IRAM1$$ZI$$Base|
|
||||
IMPORT |Image$$RW_IRAM1$$ZI$$Limit|
|
||||
IMPORT |Image$$ER_IROM1$$Base|
|
||||
IMPORT |Image$$ER_IROM1$$Limit|
|
||||
IMPORT main
|
||||
IMPORT system_set_ec_clock
|
||||
|
||||
EXPORT Reset_Handler
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000800
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
EXPORT __stack_bottom
|
||||
__stack_bottom
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __tx_vectors
|
||||
__tx_vectors
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; MEC1322 External Interrupts
|
||||
DCD NVIC_Handler_I2C0 ; 40h: 0, I2C/SMBus 0
|
||||
DCD NVIC_Handler_I2C1 ; 44h: 1, I2C/SMBus 1
|
||||
DCD NVIC_Handler_I2C2 ; 48h: 2, I2C/SMBus 2
|
||||
DCD NVIC_Handler_I2C3 ; 4Ch: 3, I2C/SMBus 3
|
||||
DCD NVIC_Handler_DMA0 ; 50h: 4, DMA Channel 0
|
||||
DCD NVIC_Handler_DMA1 ; 54h: 5, DMA Channel 1
|
||||
DCD NVIC_Handler_DMA2 ; 58h: 6, DMA Channel 2
|
||||
DCD NVIC_Handler_DMA3 ; 5Ch: 7, DMA Channel 3
|
||||
DCD NVIC_Handler_DMA4 ; 60h: 8, DMA Channel 4
|
||||
DCD NVIC_Handler_DMA5 ; 64h: 9, DMA Channel 5
|
||||
DCD NVIC_Handler_DMA6 ; 68h: 10, DMA Channel 6
|
||||
DCD NVIC_Handler_DMA7 ; 6Ch: 11, DMA Channel 7
|
||||
DCD NVIC_Handler_LPCBERR ; 70h: 12, LPC Bus Error
|
||||
DCD NVIC_Handler_UART0 ; 74h: 13, UART0
|
||||
DCD NVIC_Handler_IMAP0 ; 78h: 14, IMAP0
|
||||
DCD NVIC_Handler_EC0_IBF ; 7Ch: 15, ACPI_EC0_IBF
|
||||
DCD NVIC_Handler_EC0_OBF ; 80h: 16, ACPI_EC0_OBF
|
||||
DCD NVIC_Handler_EC1_IBF ; 84h: 17, ACPI_EC1_IBF
|
||||
DCD NVIC_Handler_EC1_OBF ; 88h: 18, ACPI_EC1_OBF
|
||||
DCD NVIC_Handler_PM1_CTL ; 8Ch: 19, ACPI_PM1_CTL
|
||||
DCD NVIC_Handler_PM1_EN ; 90h: 20, ACPI_PM1_EN
|
||||
DCD NVIC_Handler_PM1_STS ; 94h: 21, ACPI_PM1_STS
|
||||
DCD NVIC_Handler_MIF8042_OBF ; 98h: 22, MIF8042_OBF
|
||||
DCD NVIC_Handler_MIF8042_IBF ; 9Ch: 23, MIF8042_IBF
|
||||
DCD NVIC_Handler_MAILBOX ; A0h: 24, Mailbox
|
||||
DCD NVIC_Handler_PECI ; A4h: 25, PECI
|
||||
DCD NVIC_Handler_TACH0 ; A8h: 26, TACH0
|
||||
DCD NVIC_Handler_TACH1 ; ACh: 27, TACH1
|
||||
DCD NVIC_Handler_ADC_SNGL ; B0h: 28, ADC_SNGL
|
||||
DCD NVIC_Handler_ADC_RPT ; B4h: 29, ADC_RPT
|
||||
DCD NVIC_Handler_V2P_INT0 ; B8h: 30, V2P_INT0
|
||||
DCD NVIC_Handler_V2P_INT1 ; BCh: 31, V2P_INT1
|
||||
DCD NVIC_Handler_PS2_CH0 ; C0h: 32, PS2_0
|
||||
DCD NVIC_Handler_PS2_CH1 ; C4h: 33, PS2_1
|
||||
DCD NVIC_Handler_PS2_CH2 ; C8h: 34, PS2_2
|
||||
DCD NVIC_Handler_PS2_CH3 ; CCh: 35, PS2_3
|
||||
DCD NVIC_Handler_SPI0_TX ; D0h: 36, SPI0_TX
|
||||
DCD NVIC_Handler_SPI0_RX ; D4h: 37, SPI0_RX
|
||||
DCD NVIC_Handler_HIB_TMR ; D8h: 38, HIB_TMR
|
||||
DCD NVIC_Handler_KEY_INT ; DCh: 39, KEY_INT
|
||||
DCD NVIC_Handler_KEY_WAKE ; E0h: 40, KEY_WAKE
|
||||
DCD NVIC_Handler_RPM_STALL ; E4h: 41, RPM_STALL
|
||||
DCD NVIC_Handler_RPM_SPIN ; E8h: 42, RPM_SPIN
|
||||
DCD NVIC_Handler_VBAT ; ECh: 43, VBAT
|
||||
DCD NVIC_Handler_LED0 ; F0h: 44, LED0
|
||||
DCD NVIC_Handler_LED1 ; F4h: 45, LED1
|
||||
DCD NVIC_Handler_LED2 ; F8h: 46, LED2
|
||||
DCD NVIC_Handler_MBC_ERR ; FCh: 47, MBC_ERR
|
||||
DCD NVIC_Handler_MBC_BUSY ; 100h: 48, MBC_BUSY
|
||||
DCD NVIC_Handler_TMR0 ; 104h: 49, TMR0
|
||||
DCD NVIC_Handler_TMR1 ; 108h: 50, TMR1
|
||||
DCD NVIC_Handler_TMR2 ; 10Ch: 51, TMR2
|
||||
DCD NVIC_Handler_TMR3 ; 110h: 52, TMR3
|
||||
DCD NVIC_Handler_TMR4 ; 114h: 53, TMR4
|
||||
DCD NVIC_Handler_TMR5 ; 118h: 54, TMR5
|
||||
DCD NVIC_Handler_SPI1_TX ; 11Ch: 55, SPI1_TX
|
||||
DCD NVIC_Handler_SPI1_RX ; 120h: 56, SPI1_RX
|
||||
DCD NVIC_Handler_GIRQ08 ; 124h: 57, GIRQ08
|
||||
DCD NVIC_Handler_GIRQ09 ; 128h: 58, GIRQ09
|
||||
DCD NVIC_Handler_GIRQ10 ; 12Ch: 59, GIRQ10
|
||||
DCD NVIC_Handler_GIRQ11 ; 130h: 60, GIRQ11
|
||||
DCD NVIC_Handler_GIRQ12 ; 134h: 61, GIRQ12
|
||||
DCD NVIC_Handler_GIRQ13 ; 138h: 62, GIRQ13
|
||||
DCD NVIC_Handler_GIRQ14 ; 13Ch: 63, GIRQ14
|
||||
DCD NVIC_Handler_GIRQ15 ; 140h: 64, GIRQ15
|
||||
DCD NVIC_Handler_GIRQ16 ; 144h: 65, GIRQ16
|
||||
DCD NVIC_Handler_GIRQ17 ; 148h: 66, GIRQ17
|
||||
DCD NVIC_Handler_GIRQ18 ; 14Ch: 67, GIRQ18
|
||||
DCD NVIC_Handler_GIRQ19 ; 150h: 68, GIRQ19
|
||||
DCD NVIC_Handler_GIRQ20 ; 154h: 69, GIRQ20
|
||||
DCD NVIC_Handler_GIRQ21 ; 158h: 70, GIRQ21
|
||||
DCD NVIC_Handler_GIRQ22 ; 15Ch: 71, GIRQ22
|
||||
DCD NVIC_Handler_GIRQ23 ; 160h: 72, GIRQ23
|
||||
DCD NVIC_Handler_073 ; 164h: 73, unknown
|
||||
DCD NVIC_Handler_074 ; 168h: 74, unknown
|
||||
DCD NVIC_Handler_075 ; 16Ch: 75, unknown
|
||||
DCD NVIC_Handler_076 ; 170h: 76, unknown
|
||||
DCD NVIC_Handler_077 ; 174h: 77, unknown
|
||||
DCD NVIC_Handler_078 ; 178h: 78, unknown
|
||||
DCD NVIC_Handler_079 ; 17Ch: 79, unknown
|
||||
DCD NVIC_Handler_080 ; 180h: 80, unknown
|
||||
DCD NVIC_Handler_DMA8 ; 184h: 81, DMA CH8
|
||||
DCD NVIC_Handler_DMA9 ; 188h: 82, DMA CH9
|
||||
DCD NVIC_Handler_DMA10 ; 18Ch: 83, DMA CH10
|
||||
DCD NVIC_Handler_DMA11 ; 190h: 84, DMA CH11
|
||||
DCD NVIC_Handler_LED3 ; 194h: 85, LED3
|
||||
DCD NVIC_Handler_PKE_ERR ; 198h: 86, PKE Error
|
||||
DCD NVIC_Handler_PKE_END ; 19Ch: 87, PKE End
|
||||
DCD NVIC_Handler_TRNG ; 1A0h: 88, TRandom Num Gen
|
||||
DCD NVIC_Handler_AES ; 1A4h: 89, AES
|
||||
DCD NVIC_Handler_HASH ; 1A8h: 90, HASH
|
||||
|
||||
|
||||
AREA ROMTABLE, CODE, READONLY
|
||||
THUMB
|
||||
; ---------- ROM API ----------
|
||||
; Jump table to ROM API C functions
|
||||
;
|
||||
;
|
||||
; ---------- ROM API End ------
|
||||
; Reset Handler
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
THUMB
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
|
||||
CPSID i
|
||||
|
||||
; support code is loaded from ROM loader
|
||||
LDR SP, =__initial_sp
|
||||
; configure CPU speed
|
||||
LDR R0, =system_set_ec_clock
|
||||
BLX R0
|
||||
|
||||
LDR SP, =__initial_sp
|
||||
|
||||
; support FPU
|
||||
IF {CPU} = "Cortex-M4.fp"
|
||||
LDR R0, =0xE000ED88 ; Enable CP10,CP11
|
||||
LDR R1,[R0]
|
||||
ORR R1,R1,#(0xF << 20)
|
||||
STR R1,[R0]
|
||||
ENDIF
|
||||
|
||||
; Enter Keil startup code which calls our main
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
MOV R7,#1
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
MOV R7,#2
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
MOV R7,#3
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
MOV R7,#4
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
MOV R7,#5
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
MOV R7,#6
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
MOV R7,#7
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
MOV R7,#8
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
MOV R7,#9
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
; External MEC1322 NVIC Interrupt Inputs
|
||||
EXPORT NVIC_Handler_I2C0 [WEAK]
|
||||
EXPORT NVIC_Handler_I2C1 [WEAK]
|
||||
EXPORT NVIC_Handler_I2C2 [WEAK]
|
||||
EXPORT NVIC_Handler_I2C3 [WEAK]
|
||||
EXPORT NVIC_Handler_DMA0 [WEAK]
|
||||
EXPORT NVIC_Handler_DMA1 [WEAK]
|
||||
EXPORT NVIC_Handler_DMA2 [WEAK]
|
||||
EXPORT NVIC_Handler_DMA3 [WEAK]
|
||||
EXPORT NVIC_Handler_DMA4 [WEAK]
|
||||
EXPORT NVIC_Handler_DMA5 [WEAK]
|
||||
EXPORT NVIC_Handler_DMA6 [WEAK]
|
||||
EXPORT NVIC_Handler_DMA7 [WEAK]
|
||||
EXPORT NVIC_Handler_LPCBERR [WEAK]
|
||||
EXPORT NVIC_Handler_UART0 [WEAK]
|
||||
EXPORT NVIC_Handler_IMAP0 [WEAK]
|
||||
EXPORT NVIC_Handler_EC0_IBF [WEAK]
|
||||
EXPORT NVIC_Handler_EC0_OBF [WEAK]
|
||||
EXPORT NVIC_Handler_EC1_IBF [WEAK]
|
||||
EXPORT NVIC_Handler_EC1_OBF [WEAK]
|
||||
EXPORT NVIC_Handler_PM1_CTL [WEAK]
|
||||
EXPORT NVIC_Handler_PM1_EN [WEAK]
|
||||
EXPORT NVIC_Handler_PM1_STS [WEAK]
|
||||
EXPORT NVIC_Handler_MIF8042_OBF [WEAK]
|
||||
EXPORT NVIC_Handler_MIF8042_IBF [WEAK]
|
||||
EXPORT NVIC_Handler_MAILBOX [WEAK]
|
||||
EXPORT NVIC_Handler_PECI [WEAK]
|
||||
EXPORT NVIC_Handler_TACH0 [WEAK]
|
||||
EXPORT NVIC_Handler_TACH1 [WEAK]
|
||||
EXPORT NVIC_Handler_ADC_SNGL [WEAK]
|
||||
EXPORT NVIC_Handler_ADC_RPT [WEAK]
|
||||
EXPORT NVIC_Handler_V2P_INT0 [WEAK]
|
||||
EXPORT NVIC_Handler_V2P_INT1 [WEAK]
|
||||
EXPORT NVIC_Handler_PS2_CH0 [WEAK]
|
||||
EXPORT NVIC_Handler_PS2_CH1 [WEAK]
|
||||
EXPORT NVIC_Handler_PS2_CH2 [WEAK]
|
||||
EXPORT NVIC_Handler_PS2_CH3 [WEAK]
|
||||
EXPORT NVIC_Handler_SPI0_TX [WEAK]
|
||||
EXPORT NVIC_Handler_SPI0_RX [WEAK]
|
||||
EXPORT NVIC_Handler_HIB_TMR [WEAK]
|
||||
EXPORT NVIC_Handler_KEY_INT [WEAK]
|
||||
EXPORT NVIC_Handler_KEY_WAKE [WEAK]
|
||||
EXPORT NVIC_Handler_RPM_STALL [WEAK]
|
||||
EXPORT NVIC_Handler_RPM_SPIN [WEAK]
|
||||
EXPORT NVIC_Handler_VBAT [WEAK]
|
||||
EXPORT NVIC_Handler_LED0 [WEAK]
|
||||
EXPORT NVIC_Handler_LED1 [WEAK]
|
||||
EXPORT NVIC_Handler_LED2 [WEAK]
|
||||
EXPORT NVIC_Handler_MBC_ERR [WEAK]
|
||||
EXPORT NVIC_Handler_MBC_BUSY [WEAK]
|
||||
EXPORT NVIC_Handler_TMR0 [WEAK]
|
||||
EXPORT NVIC_Handler_TMR1 [WEAK]
|
||||
EXPORT NVIC_Handler_TMR2 [WEAK]
|
||||
EXPORT NVIC_Handler_TMR3 [WEAK]
|
||||
EXPORT NVIC_Handler_TMR4 [WEAK]
|
||||
EXPORT NVIC_Handler_TMR5 [WEAK]
|
||||
EXPORT NVIC_Handler_SPI1_TX [WEAK]
|
||||
EXPORT NVIC_Handler_SPI1_RX [WEAK]
|
||||
EXPORT NVIC_Handler_GIRQ08 [WEAK]
|
||||
EXPORT NVIC_Handler_GIRQ09 [WEAK]
|
||||
EXPORT NVIC_Handler_GIRQ10 [WEAK]
|
||||
EXPORT NVIC_Handler_GIRQ11 [WEAK]
|
||||
EXPORT NVIC_Handler_GIRQ12 [WEAK]
|
||||
EXPORT NVIC_Handler_GIRQ13 [WEAK]
|
||||
EXPORT NVIC_Handler_GIRQ14 [WEAK]
|
||||
EXPORT NVIC_Handler_GIRQ15 [WEAK]
|
||||
EXPORT NVIC_Handler_GIRQ16 [WEAK]
|
||||
EXPORT NVIC_Handler_GIRQ17 [WEAK]
|
||||
EXPORT NVIC_Handler_GIRQ18 [WEAK]
|
||||
EXPORT NVIC_Handler_GIRQ19 [WEAK]
|
||||
EXPORT NVIC_Handler_GIRQ20 [WEAK]
|
||||
EXPORT NVIC_Handler_GIRQ21 [WEAK]
|
||||
EXPORT NVIC_Handler_GIRQ22 [WEAK]
|
||||
EXPORT NVIC_Handler_GIRQ23 [WEAK]
|
||||
EXPORT NVIC_Handler_073 [WEAK]
|
||||
EXPORT NVIC_Handler_074 [WEAK]
|
||||
EXPORT NVIC_Handler_075 [WEAK]
|
||||
EXPORT NVIC_Handler_076 [WEAK]
|
||||
EXPORT NVIC_Handler_077 [WEAK]
|
||||
EXPORT NVIC_Handler_078 [WEAK]
|
||||
EXPORT NVIC_Handler_079 [WEAK]
|
||||
EXPORT NVIC_Handler_080 [WEAK]
|
||||
EXPORT NVIC_Handler_DMA8 [WEAK]
|
||||
EXPORT NVIC_Handler_DMA9 [WEAK]
|
||||
EXPORT NVIC_Handler_DMA10 [WEAK]
|
||||
EXPORT NVIC_Handler_DMA11 [WEAK]
|
||||
EXPORT NVIC_Handler_LED3 [WEAK]
|
||||
EXPORT NVIC_Handler_PKE_ERR [WEAK]
|
||||
EXPORT NVIC_Handler_PKE_END [WEAK]
|
||||
EXPORT NVIC_Handler_TRNG [WEAK]
|
||||
EXPORT NVIC_Handler_AES [WEAK]
|
||||
EXPORT NVIC_Handler_HASH [WEAK]
|
||||
|
||||
NVIC_Handler_I2C0
|
||||
NVIC_Handler_I2C1
|
||||
NVIC_Handler_I2C2
|
||||
NVIC_Handler_I2C3
|
||||
NVIC_Handler_DMA0
|
||||
NVIC_Handler_DMA1
|
||||
NVIC_Handler_DMA2
|
||||
NVIC_Handler_DMA3
|
||||
NVIC_Handler_DMA4
|
||||
NVIC_Handler_DMA5
|
||||
NVIC_Handler_DMA6
|
||||
NVIC_Handler_DMA7
|
||||
NVIC_Handler_LPCBERR
|
||||
NVIC_Handler_UART0
|
||||
NVIC_Handler_IMAP0
|
||||
NVIC_Handler_EC0_IBF
|
||||
NVIC_Handler_EC0_OBF
|
||||
NVIC_Handler_EC1_IBF
|
||||
NVIC_Handler_EC1_OBF
|
||||
NVIC_Handler_PM1_CTL
|
||||
NVIC_Handler_PM1_EN
|
||||
NVIC_Handler_PM1_STS
|
||||
NVIC_Handler_MIF8042_OBF
|
||||
NVIC_Handler_MIF8042_IBF
|
||||
NVIC_Handler_MAILBOX
|
||||
NVIC_Handler_PECI
|
||||
NVIC_Handler_TACH0
|
||||
NVIC_Handler_TACH1
|
||||
NVIC_Handler_ADC_SNGL
|
||||
NVIC_Handler_ADC_RPT
|
||||
NVIC_Handler_V2P_INT0
|
||||
NVIC_Handler_V2P_INT1
|
||||
NVIC_Handler_PS2_CH0
|
||||
NVIC_Handler_PS2_CH1
|
||||
NVIC_Handler_PS2_CH2
|
||||
NVIC_Handler_PS2_CH3
|
||||
NVIC_Handler_SPI0_TX
|
||||
NVIC_Handler_SPI0_RX
|
||||
NVIC_Handler_HIB_TMR
|
||||
NVIC_Handler_KEY_INT
|
||||
NVIC_Handler_KEY_WAKE
|
||||
NVIC_Handler_RPM_STALL
|
||||
NVIC_Handler_RPM_SPIN
|
||||
NVIC_Handler_VBAT
|
||||
NVIC_Handler_LED0
|
||||
NVIC_Handler_LED1
|
||||
NVIC_Handler_LED2
|
||||
NVIC_Handler_MBC_ERR
|
||||
NVIC_Handler_MBC_BUSY
|
||||
NVIC_Handler_TMR0
|
||||
NVIC_Handler_TMR1
|
||||
NVIC_Handler_TMR2
|
||||
NVIC_Handler_TMR3
|
||||
NVIC_Handler_TMR4
|
||||
NVIC_Handler_TMR5
|
||||
NVIC_Handler_SPI1_TX
|
||||
NVIC_Handler_SPI1_RX
|
||||
NVIC_Handler_GIRQ08
|
||||
NVIC_Handler_GIRQ09
|
||||
NVIC_Handler_GIRQ10
|
||||
NVIC_Handler_GIRQ11
|
||||
NVIC_Handler_GIRQ12
|
||||
NVIC_Handler_GIRQ13
|
||||
NVIC_Handler_GIRQ14
|
||||
NVIC_Handler_GIRQ15
|
||||
NVIC_Handler_GIRQ16
|
||||
NVIC_Handler_GIRQ17
|
||||
NVIC_Handler_GIRQ18
|
||||
NVIC_Handler_GIRQ19
|
||||
NVIC_Handler_GIRQ20
|
||||
NVIC_Handler_GIRQ21
|
||||
NVIC_Handler_GIRQ22
|
||||
NVIC_Handler_GIRQ23
|
||||
NVIC_Handler_073
|
||||
NVIC_Handler_074
|
||||
NVIC_Handler_075
|
||||
NVIC_Handler_076
|
||||
NVIC_Handler_077
|
||||
NVIC_Handler_078
|
||||
NVIC_Handler_079
|
||||
NVIC_Handler_080
|
||||
NVIC_Handler_DMA8
|
||||
NVIC_Handler_DMA9
|
||||
NVIC_Handler_DMA10
|
||||
NVIC_Handler_DMA11
|
||||
NVIC_Handler_LED3
|
||||
NVIC_Handler_PKE_ERR
|
||||
NVIC_Handler_PKE_END
|
||||
NVIC_Handler_TRNG
|
||||
NVIC_Handler_AES
|
||||
NVIC_Handler_HASH
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
EXPORT __stack_bottom
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
||||
;/** @}
|
||||
; */
|
||||
@ -0,0 +1,73 @@
|
||||
/****************************************************************************
|
||||
* © 2013 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*/
|
||||
|
||||
/** @defgroup pwm pwm_c_wrapper
|
||||
* @{
|
||||
*/
|
||||
/** @file pwm_c_wrapper.cpp
|
||||
\brief the pwm component C wrapper
|
||||
This program is designed to allow the other C programs to be able to use this component
|
||||
|
||||
There are entry points for all C wrapper API implementation
|
||||
|
||||
<b>Platform:</b> This is ARC-based component
|
||||
|
||||
<b>Toolset:</b> Metaware IDE(8.5.1)
|
||||
<b>Reference:</b> smsc_reusable_fw_requirement.doc */
|
||||
|
||||
/*******************************************************************************
|
||||
* SMSC version control information (Perforce):
|
||||
*
|
||||
* FILE: $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/system/system.c $
|
||||
* REVISION: $Revision: #1 $
|
||||
* DATETIME: $DateTime: 2015/12/23 15:37:58 $
|
||||
* AUTHOR: $Author: akrishnan $
|
||||
*
|
||||
* Revision history (latest first):
|
||||
* #3 2011/05/09 martin_y update to Metaware IDE(8.5.1)
|
||||
* #2 2011/03/25 martin_y support FPGA build 058 apps
|
||||
* #1 2011/03/23 martin_y branch from MEC1618 sample code: MEC1618_evb_sample_code_build_0200
|
||||
***********************************************************************************
|
||||
*/
|
||||
/* Imported Header File */
|
||||
//#include "common.h"
|
||||
//#include "build.h"
|
||||
#include <stdint.h>
|
||||
|
||||
#define ADDR_PCR_PROCESSOR_CLOCK_CONTROL 0x40080120
|
||||
#define MMCR_PCR_PROCESSOR_CLOCK_CONTROL (*(uint32_t *)(ADDR_PCR_PROCESSOR_CLOCK_CONTROL))
|
||||
#define CPU_CLOCK_DIVIDER 1
|
||||
|
||||
/******************************************************************************/
|
||||
/** system_set_ec_clock
|
||||
* Set CPU speed
|
||||
* @param void
|
||||
* @return void
|
||||
*******************************************************************************/
|
||||
|
||||
void system_set_ec_clock(void)
|
||||
{
|
||||
|
||||
/* Set ARC CPU Clock Divider to determine the CPU speed */
|
||||
/* Set divider to 8 for 8MHz operation, MCLK in silicon chip is 64MHz, CPU=MCLK/Divider */
|
||||
MMCR_PCR_PROCESSOR_CLOCK_CONTROL = CPU_CLOCK_DIVIDER;
|
||||
|
||||
} /* End system_set_ec_clock() */
|
||||
|
||||
@ -0,0 +1,271 @@
|
||||
/*
|
||||
FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
|
||||
All rights reserved
|
||||
|
||||
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
|
||||
|
||||
***************************************************************************
|
||||
>>! NOTE: The modification to the GPL is included to allow you to !<<
|
||||
>>! distribute a combined work that includes FreeRTOS without being !<<
|
||||
>>! obliged to provide the source code for proprietary components !<<
|
||||
>>! outside of the FreeRTOS kernel. !<<
|
||||
***************************************************************************
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
|
||||
FOR A PARTICULAR PURPOSE. Full license text is available on the following
|
||||
link: http://www.freertos.org/a00114.html
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS provides completely free yet professionally developed, *
|
||||
* robust, strictly quality controlled, supported, and cross *
|
||||
* platform software that is more than just the market leader, it *
|
||||
* is the industry's de facto standard. *
|
||||
* *
|
||||
* Help yourself get started quickly while simultaneously helping *
|
||||
* to support the FreeRTOS project by purchasing a FreeRTOS *
|
||||
* tutorial book, reference manual, or both: *
|
||||
* http://www.FreeRTOS.org/Documentation *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
|
||||
the FAQ page "My application does not run, what could be wrong?". Have you
|
||||
defined configASSERT()?
|
||||
|
||||
http://www.FreeRTOS.org/support - In return for receiving this top quality
|
||||
embedded software for free we request you assist our global community by
|
||||
participating in the support forum.
|
||||
|
||||
http://www.FreeRTOS.org/training - Investing in training allows your team to
|
||||
be as productive as possible as early as possible. Now you can receive
|
||||
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
|
||||
Ltd, and the world's leading authority on the world's leading RTOS.
|
||||
|
||||
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
|
||||
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
|
||||
compatible FAT file system, and our tiny thread aware UDP/IP stack.
|
||||
|
||||
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
|
||||
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
|
||||
|
||||
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
|
||||
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
|
||||
licenses offer ticketed support, indemnification and commercial middleware.
|
||||
|
||||
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
|
||||
engineered and independently SIL3 certified version for use in safety and
|
||||
mission critical applications that require provable dependability.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* This project provides two demo applications. A simple blinky style project
|
||||
* that demonstrates low power tickless functionality, and a more comprehensive
|
||||
* test and demo application. The configCREATE_LOW_POWER_DEMO setting, which is
|
||||
* defined in FreeRTOSConfig.h, is used to select between the two. The simply
|
||||
* blinky low power demo is implemented and described in main_low_power.c. The
|
||||
* more comprehensive test and demo application is implemented and described in
|
||||
* main_full.c.
|
||||
*
|
||||
* This file implements the code that is not demo specific, including the
|
||||
* hardware setup and standard FreeRTOS hook functions.
|
||||
*
|
||||
* ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON
|
||||
* THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO
|
||||
* APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT!
|
||||
*
|
||||
*/
|
||||
|
||||
/* Scheduler include files. */
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
|
||||
/* Hardware register addresses. */
|
||||
#define mainVTOR ( * ( uint32_t * ) 0xE000ED08 )
|
||||
#define mainNVIC_AUX_ACTLR ( * ( uint32_t * ) 0xE000E008 )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* Configure the hardware as necessary to run this demo.
|
||||
*/
|
||||
static void prvSetupHardware( void );
|
||||
|
||||
/*
|
||||
* main_low_power() is used when configCREATE_LOW_POWER_DEMO is set to 1.
|
||||
* main_full() is used when configCREATE_LOW_POWER_DEMO is set to 0.
|
||||
*/
|
||||
#if( configCREATE_LOW_POWER_DEMO == 1 )
|
||||
|
||||
extern void main_low_power( void );
|
||||
|
||||
#else
|
||||
|
||||
extern void main_full( void );
|
||||
|
||||
/* Some of the tests and examples executed as part of the full demo make use
|
||||
of the tick hook to call API functions from an interrupt context. */
|
||||
extern void vFullDemoTickHook( void );
|
||||
|
||||
#endif /* #if configCREATE_LOW_POWER_DEMO == 1 */
|
||||
|
||||
/* Prototypes for the standard FreeRTOS callback/hook functions implemented
|
||||
within this file. */
|
||||
void vApplicationMallocFailedHook( void );
|
||||
void vApplicationIdleHook( void );
|
||||
void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName );
|
||||
void vApplicationTickHook( void );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* The variable that is incremented to represent each LED toggle. On the
|
||||
clicker hardware the LED state is set to the value of the least significant bit
|
||||
of this variable. On other hardware, where an LED is not used, the LED just
|
||||
keeps a count of the number of times the LED would otherwise have been toggled.
|
||||
See the comments in main_low_power.c and main_full.c for information on the
|
||||
expected LED toggle rate). */
|
||||
volatile uint32_t ulLED = 0;
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
int main( void )
|
||||
{
|
||||
/* Configure the hardware ready to run the demo. */
|
||||
prvSetupHardware();
|
||||
|
||||
/* The configCREATE_LOW_POWER_DEMO setting is described at the top
|
||||
of this file. */
|
||||
#if( configCREATE_LOW_POWER_DEMO == 1 )
|
||||
{
|
||||
main_low_power();
|
||||
}
|
||||
#else
|
||||
{
|
||||
main_full();
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Should not get here. */
|
||||
return 0;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvSetupHardware( void )
|
||||
{
|
||||
/* Disable M4 write buffer: fix MEC1322 hardware bug. */
|
||||
mainNVIC_AUX_ACTLR |= 0x07;
|
||||
|
||||
#ifdef __CC_ARM
|
||||
{
|
||||
/* Assuming downloading code via the debugger - so ensure the hardware
|
||||
is using the vector table downloaded with the application. */
|
||||
extern unsigned long __Vectors[];
|
||||
mainVTOR = ( uint32_t ) __Vectors;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vApplicationMallocFailedHook( void )
|
||||
{
|
||||
/* Called if a call to pvPortMalloc() fails because there is insufficient
|
||||
free memory available in the FreeRTOS heap. pvPortMalloc() is called
|
||||
internally by FreeRTOS API functions that create tasks, queues, software
|
||||
timers, and semaphores. The size of the FreeRTOS heap is set by the
|
||||
configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */
|
||||
|
||||
/* Force an assert. */
|
||||
configASSERT( ( volatile void * ) NULL );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )
|
||||
{
|
||||
( void ) pcTaskName;
|
||||
( void ) pxTask;
|
||||
|
||||
/* Run time stack overflow checking is performed if
|
||||
configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
|
||||
function is called if a stack overflow is detected. */
|
||||
|
||||
/* Force an assert. */
|
||||
configASSERT( ( volatile void * ) NULL );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vApplicationIdleHook( void )
|
||||
{
|
||||
volatile size_t xFreeHeapSpace;
|
||||
|
||||
/* This is just a trivial example of an idle hook. It is called on each
|
||||
cycle of the idle task. It must *NOT* attempt to block. In this case the
|
||||
idle task just queries the amount of FreeRTOS heap that remains. See the
|
||||
memory management section on the http://www.FreeRTOS.org web site for memory
|
||||
management options. If there is a lot of heap memory free then the
|
||||
configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up
|
||||
RAM. */
|
||||
xFreeHeapSpace = xPortGetFreeHeapSize();
|
||||
|
||||
/* Remove compiler warning about xFreeHeapSpace being set but never used. */
|
||||
( void ) xFreeHeapSpace;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vApplicationTickHook( void )
|
||||
{
|
||||
/* The full demo includes tests that run from the tick hook. */
|
||||
#if( configCREATE_LOW_POWER_DEMO == 0 )
|
||||
{
|
||||
/* Some of the tests and demo tasks executed by the full demo include
|
||||
interaction from an interrupt - for which the tick interrupt is used
|
||||
via the tick hook function. */
|
||||
vFullDemoTickHook();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint16_t *pusIdleTaskStackSize )
|
||||
{
|
||||
/* configUSE_STATIC_ALLOCATION is set to 1, so the application has the
|
||||
opportunity to supply the buffers that will be used by the Idle task as its
|
||||
stack and to hold its TCB. If these are set to NULL then the buffers will
|
||||
be allocated dynamically, just as if xTaskCreate() had been called. */
|
||||
*ppxIdleTaskTCBBuffer = NULL;
|
||||
*ppxIdleTaskStackBuffer = NULL;
|
||||
*pusIdleTaskStackSize = configMINIMAL_STACK_SIZE; /* In words. NOT in bytes! */
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint16_t *pusTimerTaskStackSize )
|
||||
{
|
||||
/* configUSE_STATIC_ALLOCATION is set to 1, so the application has the
|
||||
opportunity to supply the buffers that will be used by the Timer/RTOS daemon
|
||||
task as its stack and to hold its TCB. If these are set to NULL then the
|
||||
buffers will be allocated dynamically, just as if xTaskCreate() had been
|
||||
called. */
|
||||
*ppxTimerTaskTCBBuffer = NULL;
|
||||
*ppxTimerTaskStackBuffer = NULL;
|
||||
*pusTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; /* In words. NOT in bytes! */
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@ -0,0 +1,208 @@
|
||||
/*
|
||||
FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
|
||||
All rights reserved
|
||||
|
||||
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
|
||||
|
||||
***************************************************************************
|
||||
>>! NOTE: The modification to the GPL is included to allow you to !<<
|
||||
>>! distribute a combined work that includes FreeRTOS without being !<<
|
||||
>>! obliged to provide the source code for proprietary components !<<
|
||||
>>! outside of the FreeRTOS kernel. !<<
|
||||
***************************************************************************
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
|
||||
FOR A PARTICULAR PURPOSE. Full license text is available on the following
|
||||
link: http://www.freertos.org/a00114.html
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS provides completely free yet professionally developed, *
|
||||
* robust, strictly quality controlled, supported, and cross *
|
||||
* platform software that is more than just the market leader, it *
|
||||
* is the industry's de facto standard. *
|
||||
* *
|
||||
* Help yourself get started quickly while simultaneously helping *
|
||||
* to support the FreeRTOS project by purchasing a FreeRTOS *
|
||||
* tutorial book, reference manual, or both: *
|
||||
* http://www.FreeRTOS.org/Documentation *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
|
||||
the FAQ page "My application does not run, what could be wrong?". Have you
|
||||
defined configASSERT()?
|
||||
|
||||
http://www.FreeRTOS.org/support - In return for receiving this top quality
|
||||
embedded software for free we request you assist our global community by
|
||||
participating in the support forum.
|
||||
|
||||
http://www.FreeRTOS.org/training - Investing in training allows your team to
|
||||
be as productive as possible as early as possible. Now you can receive
|
||||
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
|
||||
Ltd, and the world's leading authority on the world's leading RTOS.
|
||||
|
||||
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
|
||||
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
|
||||
compatible FAT file system, and our tiny thread aware UDP/IP stack.
|
||||
|
||||
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
|
||||
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
|
||||
|
||||
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
|
||||
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
|
||||
licenses offer ticketed support, indemnification and commercial middleware.
|
||||
|
||||
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
|
||||
engineered and independently SIL3 certified version for use in safety and
|
||||
mission critical applications that require provable dependability.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file initialises three timers as follows:
|
||||
*
|
||||
* Basic timer channels 0 and 1 provide the interrupts that are used with the
|
||||
* IntQ standard demo tasks, which test interrupt nesting and using queues from
|
||||
* interrupts. The interrupts use slightly different frequencies so will
|
||||
* occasionally nest.
|
||||
*
|
||||
* Basic timer channel 2 provides a much higher frequency timer that tests the
|
||||
* nesting of interrupts that don't use the FreeRTOS API.
|
||||
*
|
||||
* All the timers can nest with the tick interrupt - creating a maximum
|
||||
* interrupt nesting depth of 4 (which is shown as a max nest count of 3 as the
|
||||
* tick interrupt does not increment the nesting count variable).
|
||||
*
|
||||
*/
|
||||
|
||||
/* Scheduler includes. */
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
|
||||
/* Demo includes. */
|
||||
#include "IntQueueTimer.h"
|
||||
#include "IntQueue.h"
|
||||
|
||||
/* Library includes. */
|
||||
#include "common_lib.h"
|
||||
#include "peripheral_library/interrupt/interrupt.h"
|
||||
#include "peripheral_library/basic_timer/btimer.h"
|
||||
|
||||
/* The frequencies at which the first two timers expire are slightly offset to
|
||||
ensure they don't remain synchronised. The frequency of the highest priority
|
||||
interrupt is 20 times faster so really hammers the interrupt entry and exit
|
||||
code. */
|
||||
#define tmrTIMER_0_FREQUENCY ( 2000UL )
|
||||
#define tmrTIMER_1_FREQUENCY ( 2003UL )
|
||||
#define tmrTIMER_2_FREQUENCY ( 20000UL )
|
||||
|
||||
/* The basic timer channels used for generating the three interrupts. */
|
||||
#define tmrTIMER_CHANNEL_0 0 /* At tmrTIMER_0_FREQUENCY */
|
||||
#define tmrTIMER_CHANNEL_1 1 /* At tmrTIMER_1_FREQUENCY */
|
||||
#define tmrTIMER_CHANNEL_2 2 /* At tmrTIMER_2_FREQUENCY */
|
||||
|
||||
/* The high frequency interrupt is given a priority above the maximum at which
|
||||
interrupt safe FreeRTOS calls can be made. The priority of the lower frequency
|
||||
timers must still be above the tick interrupt priority. */
|
||||
#define tmrLOWER_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 1 )
|
||||
#define tmrMEDIUM_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 0 )
|
||||
#define tmrHIGHER_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY - 1 )
|
||||
|
||||
#define tmrRECORD_NESTING_DEPTH() \
|
||||
ulNestingDepth++; \
|
||||
if( ulNestingDepth > ulMaxRecordedNestingDepth ) \
|
||||
{ \
|
||||
ulMaxRecordedNestingDepth = ulNestingDepth; \
|
||||
}
|
||||
|
||||
/* Used to count the nesting depth, and record the maximum nesting depth. */
|
||||
volatile uint32_t ulNestingDepth = 0, ulMaxRecordedNestingDepth = 0;
|
||||
|
||||
#define GIRQ23_ENABLE_SET ( * ( uint32_t * ) 0x4000C130 )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vInitialiseTimerForIntQueueTest( void )
|
||||
{
|
||||
const uint32_t ulTimer0Count = configCPU_CLOCK_HZ / tmrTIMER_0_FREQUENCY;
|
||||
const uint32_t ulTimer1Count = configCPU_CLOCK_HZ / tmrTIMER_1_FREQUENCY;
|
||||
const uint32_t ulTimer2Count = configCPU_CLOCK_HZ / tmrTIMER_2_FREQUENCY;
|
||||
|
||||
GIRQ23_ENABLE_SET = 0x03;
|
||||
*(unsigned int*)0x4000FC18 = 1;
|
||||
|
||||
/* Initialise the three timers as described at the top of this file, and
|
||||
enable their interrupts in the NVIC. */
|
||||
btimer_init( tmrTIMER_CHANNEL_0, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer0Count, ulTimer0Count );
|
||||
btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_0 );
|
||||
enable_timer0_irq();
|
||||
NVIC_SetPriority( TIMER0_IRQn, tmrLOWER_PRIORITY );
|
||||
NVIC_ClearPendingIRQ( TIMER0_IRQn );
|
||||
NVIC_EnableIRQ( TIMER0_IRQn );
|
||||
btimer_start( tmrTIMER_CHANNEL_0 );
|
||||
|
||||
btimer_init( tmrTIMER_CHANNEL_1, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer1Count, ulTimer1Count );
|
||||
btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_1 );
|
||||
enable_timer1_irq();
|
||||
NVIC_SetPriority( TIMER1_IRQn, tmrMEDIUM_PRIORITY );
|
||||
NVIC_ClearPendingIRQ( TIMER1_IRQn );
|
||||
NVIC_EnableIRQ( TIMER1_IRQn );
|
||||
btimer_start( tmrTIMER_CHANNEL_1 );
|
||||
|
||||
btimer_init( tmrTIMER_CHANNEL_2, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer2Count, ulTimer2Count );
|
||||
btimer_interrupt_status_get_clr( tmrTIMER_CHANNEL_2 );
|
||||
enable_timer2_irq();
|
||||
NVIC_SetPriority( TIMER2_IRQn, tmrHIGHER_PRIORITY );
|
||||
NVIC_ClearPendingIRQ( TIMER2_IRQn );
|
||||
NVIC_EnableIRQ( TIMER2_IRQn );
|
||||
btimer_start( tmrTIMER_CHANNEL_2 );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* The TMR0 interrupt is used for different purposes by the low power and full
|
||||
demos respectively. */
|
||||
#if( configCREATE_LOW_POWER_DEMO == 0 )
|
||||
|
||||
void NVIC_Handler_TMR0( void )
|
||||
{
|
||||
tmrRECORD_NESTING_DEPTH();
|
||||
|
||||
/* Call the IntQ test function for this channel. */
|
||||
portYIELD_FROM_ISR( xFirstTimerHandler() );
|
||||
|
||||
ulNestingDepth--;
|
||||
}
|
||||
|
||||
#endif /* configCREATE_LOW_POWER_DEMO */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void NVIC_Handler_TMR1( void )
|
||||
{
|
||||
tmrRECORD_NESTING_DEPTH();
|
||||
|
||||
/* Just testing the xPortIsInsideInterrupt() functionality. */
|
||||
configASSERT( xPortIsInsideInterrupt() == pdTRUE );
|
||||
|
||||
/* Call the IntQ test function for this channel. */
|
||||
portYIELD_FROM_ISR( xSecondTimerHandler() );
|
||||
|
||||
ulNestingDepth--;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void NVIC_Handler_TMR2( void )
|
||||
{
|
||||
tmrRECORD_NESTING_DEPTH();
|
||||
ulNestingDepth--;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
@ -0,0 +1,78 @@
|
||||
/*
|
||||
FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
|
||||
All rights reserved
|
||||
|
||||
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
|
||||
|
||||
***************************************************************************
|
||||
>>! NOTE: The modification to the GPL is included to allow you to !<<
|
||||
>>! distribute a combined work that includes FreeRTOS without being !<<
|
||||
>>! obliged to provide the source code for proprietary components !<<
|
||||
>>! outside of the FreeRTOS kernel. !<<
|
||||
***************************************************************************
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
|
||||
FOR A PARTICULAR PURPOSE. Full license text is available on the following
|
||||
link: http://www.freertos.org/a00114.html
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS provides completely free yet professionally developed, *
|
||||
* robust, strictly quality controlled, supported, and cross *
|
||||
* platform software that is more than just the market leader, it *
|
||||
* is the industry's de facto standard. *
|
||||
* *
|
||||
* Help yourself get started quickly while simultaneously helping *
|
||||
* to support the FreeRTOS project by purchasing a FreeRTOS *
|
||||
* tutorial book, reference manual, or both: *
|
||||
* http://www.FreeRTOS.org/Documentation *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
|
||||
the FAQ page "My application does not run, what could be wrong?". Have you
|
||||
defined configASSERT()?
|
||||
|
||||
http://www.FreeRTOS.org/support - In return for receiving this top quality
|
||||
embedded software for free we request you assist our global community by
|
||||
participating in the support forum.
|
||||
|
||||
http://www.FreeRTOS.org/training - Investing in training allows your team to
|
||||
be as productive as possible as early as possible. Now you can receive
|
||||
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
|
||||
Ltd, and the world's leading authority on the world's leading RTOS.
|
||||
|
||||
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
|
||||
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
|
||||
compatible FAT file system, and our tiny thread aware UDP/IP stack.
|
||||
|
||||
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
|
||||
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
|
||||
|
||||
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
|
||||
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
|
||||
licenses offer ticketed support, indemnification and commercial middleware.
|
||||
|
||||
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
|
||||
engineered and independently SIL3 certified version for use in safety and
|
||||
mission critical applications that require provable dependability.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifndef INT_QUEUE_TIMER_H
|
||||
#define INT_QUEUE_TIMER_H
|
||||
|
||||
void vInitialiseTimerForIntQueueTest( void );
|
||||
BaseType_t xTimer0Handler( void );
|
||||
BaseType_t xTimer1Handler( void );
|
||||
|
||||
#endif
|
||||
|
||||
@ -0,0 +1,436 @@
|
||||
/*
|
||||
FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
|
||||
All rights reserved
|
||||
|
||||
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
|
||||
|
||||
***************************************************************************
|
||||
>>! NOTE: The modification to the GPL is included to allow you to !<<
|
||||
>>! distribute a combined work that includes FreeRTOS without being !<<
|
||||
>>! obliged to provide the source code for proprietary components !<<
|
||||
>>! outside of the FreeRTOS kernel. !<<
|
||||
***************************************************************************
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
|
||||
FOR A PARTICULAR PURPOSE. Full license text is available on the following
|
||||
link: http://www.freertos.org/a00114.html
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS provides completely free yet professionally developed, *
|
||||
* robust, strictly quality controlled, supported, and cross *
|
||||
* platform software that is more than just the market leader, it *
|
||||
* is the industry's de facto standard. *
|
||||
* *
|
||||
* Help yourself get started quickly while simultaneously helping *
|
||||
* to support the FreeRTOS project by purchasing a FreeRTOS *
|
||||
* tutorial book, reference manual, or both: *
|
||||
* http://www.FreeRTOS.org/Documentation *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
|
||||
the FAQ page "My application does not run, what could be wrong?". Have you
|
||||
defined configASSERT()?
|
||||
|
||||
http://www.FreeRTOS.org/support - In return for receiving this top quality
|
||||
embedded software for free we request you assist our global community by
|
||||
participating in the support forum.
|
||||
|
||||
http://www.FreeRTOS.org/training - Investing in training allows your team to
|
||||
be as productive as possible as early as possible. Now you can receive
|
||||
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
|
||||
Ltd, and the world's leading authority on the world's leading RTOS.
|
||||
|
||||
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
|
||||
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
|
||||
compatible FAT file system, and our tiny thread aware UDP/IP stack.
|
||||
|
||||
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
|
||||
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
|
||||
|
||||
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
|
||||
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
|
||||
licenses offer ticketed support, indemnification and commercial middleware.
|
||||
|
||||
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
|
||||
engineered and independently SIL3 certified version for use in safety and
|
||||
mission critical applications that require provable dependability.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* NOTE 1: This project provides two demo applications. A simple blinky style
|
||||
* project that demonstrates the tickless low power features of FreeRTOS, and a
|
||||
* more comprehensive test and demo application. The configCREATE_LOW_POWER_DEMO
|
||||
* setting in FreeRTOSConifg.h is used to select between the two. See the notes
|
||||
* on using conifgCREATE_LOW_POWER_DEMO in main.c. This file implements the
|
||||
* comprehensive test and demo version.
|
||||
*
|
||||
* NOTE 2: This file only contains the source code that is specific to the
|
||||
* full demo. Generic functions, such FreeRTOS hook functions, and functions
|
||||
* required to configure the hardware, are defined in main.c.
|
||||
*
|
||||
******************************************************************************
|
||||
*
|
||||
* main_full() creates all the demo application tasks and software timers, then
|
||||
* starts the scheduler. The web documentation provides more details of the
|
||||
* standard demo application tasks, which provide no particular functionality,
|
||||
* but do provide a good example of how to use the FreeRTOS API.
|
||||
*
|
||||
* In addition to the standard demo tasks, the following tasks and tests are
|
||||
* defined and/or created within this file:
|
||||
*
|
||||
* "Reg test" tasks - These fill both the core and floating point registers with
|
||||
* known values, then check that each register maintains its expected value for
|
||||
* the lifetime of the task. Each task uses a different set of values. The reg
|
||||
* test tasks execute with a very low priority, so get preempted very
|
||||
* frequently. A register containing an unexpected value is indicative of an
|
||||
* error in the context switching mechanism.
|
||||
*
|
||||
* "Check" task - The check task period is initially set to three seconds. The
|
||||
* task checks that all the standard demo tasks, and the register check tasks,
|
||||
* are not only still executing, but are executing without reporting any errors.
|
||||
* If the check task discovers that a task has either stalled, or reported an
|
||||
* error, then it changes its own execution period from the initial three
|
||||
* seconds, to just 200ms. The check task also toggles an LED each time it is
|
||||
* called. This provides a visual indication of the system status: If the LED
|
||||
* toggles every three seconds, then no issues have been discovered. If the LED
|
||||
* toggles every 200ms, then an issue has been discovered with at least one
|
||||
* task.
|
||||
*/
|
||||
|
||||
/* Standard includes. */
|
||||
#include <stdio.h>
|
||||
|
||||
/* Kernel includes. */
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
#include "timers.h"
|
||||
#include "semphr.h"
|
||||
|
||||
/* Standard demo application includes. */
|
||||
#include "flop.h"
|
||||
#include "semtest.h"
|
||||
#include "dynamic.h"
|
||||
#include "BlockQ.h"
|
||||
#include "blocktim.h"
|
||||
#include "countsem.h"
|
||||
#include "GenQTest.h"
|
||||
#include "recmutex.h"
|
||||
#include "death.h"
|
||||
#include "TimerDemo.h"
|
||||
#include "IntQueue.h"
|
||||
#include "EventGroupsDemo.h"
|
||||
#include "TaskNotify.h"
|
||||
|
||||
/* Priorities for the demo application tasks. */
|
||||
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )
|
||||
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )
|
||||
#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )
|
||||
#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )
|
||||
#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
|
||||
|
||||
/* A block time of zero simply means "don't block". */
|
||||
#define mainDONT_BLOCK ( 0UL )
|
||||
|
||||
/* The period after which the check timer will expire, in ms, provided no errors
|
||||
have been reported by any of the standard demo tasks. ms are converted to the
|
||||
equivalent in ticks using the portTICK_PERIOD_MS constant. */
|
||||
#define mainNO_ERROR_CHECK_TASK_PERIOD ( 3000UL / portTICK_PERIOD_MS )
|
||||
|
||||
/* The period at which the check timer will expire, in ms, if an error has been
|
||||
reported in one of the standard demo tasks. ms are converted to the equivalent
|
||||
in ticks using the portTICK_PERIOD_MS constant. */
|
||||
#define mainERROR_CHECK_TASK_PERIOD ( 200UL / portTICK_PERIOD_MS )
|
||||
|
||||
/* Parameters that are passed into the register check tasks solely for the
|
||||
purpose of ensuring parameters are passed into tasks correctly. */
|
||||
#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 )
|
||||
#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 )
|
||||
|
||||
/* The base period used by the timer test tasks. */
|
||||
#define mainTIMER_TEST_PERIOD ( 50 )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* Called by main() to run the full demo (as opposed to the blinky demo) when
|
||||
* configCREATE_LOW_POWER_DEMO is set to 0.
|
||||
*/
|
||||
void main_full( void );
|
||||
|
||||
/*
|
||||
* The check task, as described at the top of this file.
|
||||
*/
|
||||
static void prvCheckTask( void *pvParameters );
|
||||
|
||||
/*
|
||||
* Some of the tests and demo tasks executed by the full demo include
|
||||
* interaction from an interrupt - for which the tick interrupt is used via the
|
||||
* tick hook function.
|
||||
*/
|
||||
void vFullDemoTickHook( void );
|
||||
|
||||
/*
|
||||
* Register check tasks, and the tasks used to write over and check the contents
|
||||
* of the FPU registers, as described at the top of this file. The nature of
|
||||
* these files necessitates that they are written in an assembly file, but the
|
||||
* entry points are kept in the C file for the convenience of checking the task
|
||||
* parameter.
|
||||
*/
|
||||
static void prvRegTestTaskEntry1( void *pvParameters );
|
||||
extern void vRegTest1Implementation( void );
|
||||
static void prvRegTestTaskEntry2( void *pvParameters );
|
||||
extern void vRegTest2Implementation( void );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* The following two variables are used to communicate the status of the
|
||||
register check tasks to the check task. If the variables keep incrementing,
|
||||
then the register check tasks have not discovered any errors. If a variable
|
||||
stops incrementing, then an error has been found. */
|
||||
volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;
|
||||
|
||||
/* The variable that is incremented to represent each LED toggle. On the
|
||||
clicker hardware the LED state is set to the value of the least significant bit
|
||||
of this variable. On other hardware, where an LED is not used, the LED just
|
||||
keeps a count of the number of times the LED would otherwise have been toggled.
|
||||
See the comments at the top of this file for information on the expected LED
|
||||
toggle rate. */
|
||||
extern volatile uint32_t ulLED;
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void main_full( void )
|
||||
{
|
||||
/* Start all the other standard demo/test tasks. They have no particular
|
||||
functionality, but do demonstrate how to use the FreeRTOS API and test the
|
||||
kernel port. */
|
||||
vStartDynamicPriorityTasks();
|
||||
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
|
||||
vCreateBlockTimeTasks();
|
||||
vStartCountingSemaphoreTasks();
|
||||
vStartGenericQueueTasks( tskIDLE_PRIORITY );
|
||||
vStartRecursiveMutexTasks();
|
||||
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
|
||||
vStartMathTasks( mainFLOP_TASK_PRIORITY );
|
||||
vStartTimerDemoTask( mainTIMER_TEST_PERIOD );
|
||||
vStartEventGroupTasks();
|
||||
vStartTaskNotifyTask();
|
||||
vStartInterruptQueueTasks();
|
||||
|
||||
/* Create the register check tasks, as described at the top of this file */
|
||||
xTaskCreate( prvRegTestTaskEntry1, "Reg1", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_1_PARAMETER, tskIDLE_PRIORITY, NULL );
|
||||
xTaskCreate( prvRegTestTaskEntry2, "Reg2", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL );
|
||||
|
||||
/* Create the task that performs the 'check' functionality, as described at
|
||||
the top of this file. */
|
||||
xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
|
||||
|
||||
/* The set of tasks created by the following function call have to be
|
||||
created last as they keep account of the number of tasks they expect to see
|
||||
running. */
|
||||
vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );
|
||||
|
||||
/* Start the scheduler. */
|
||||
vTaskStartScheduler();
|
||||
|
||||
/* If all is well, the scheduler will now be running, and the following
|
||||
line will never be reached. If the following line does execute, then
|
||||
there was insufficient FreeRTOS heap memory available for the Idle and/or
|
||||
timer tasks to be created. See the memory management section on the
|
||||
FreeRTOS web site for more details on the FreeRTOS heap
|
||||
http://www.freertos.org/a00111.html. */
|
||||
for( ;; );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvCheckTask( void *pvParameters )
|
||||
{
|
||||
TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD;
|
||||
TickType_t xLastExecutionTime;
|
||||
static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;
|
||||
unsigned long ulErrorFound = pdFALSE;
|
||||
|
||||
/* Just to stop compiler warnings. */
|
||||
( void ) pvParameters;
|
||||
|
||||
/* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()
|
||||
works correctly. */
|
||||
xLastExecutionTime = xTaskGetTickCount();
|
||||
|
||||
/* Cycle for ever, delaying then checking all the other tasks are still
|
||||
operating without error. The onboard LED is toggled on each iteration.
|
||||
If an error is detected then the delay period is decreased from
|
||||
mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the
|
||||
effect of increasing the rate at which the onboard LED toggles, and in so
|
||||
doing gives visual feedback of the system status. */
|
||||
for( ;; )
|
||||
{
|
||||
/* Delay until it is time to execute again. */
|
||||
vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod );
|
||||
|
||||
/* Check all the demo tasks (other than the flash tasks) to ensure
|
||||
that they are all still running, and that none have detected an error. */
|
||||
if( xAreIntQueueTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
ulErrorFound = 1UL << 0UL;
|
||||
}
|
||||
|
||||
if( xAreMathsTaskStillRunning() != pdTRUE )
|
||||
{
|
||||
ulErrorFound = 1UL << 1UL;
|
||||
}
|
||||
|
||||
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
ulErrorFound = 1UL << 2UL;
|
||||
}
|
||||
|
||||
if( xAreBlockingQueuesStillRunning() != pdTRUE )
|
||||
{
|
||||
ulErrorFound = 1UL << 3UL;
|
||||
}
|
||||
|
||||
if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
ulErrorFound = 1UL << 4UL;
|
||||
}
|
||||
|
||||
if( xAreGenericQueueTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
ulErrorFound = 1UL << 5UL;
|
||||
}
|
||||
|
||||
if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
ulErrorFound = 1UL << 6UL;
|
||||
}
|
||||
|
||||
if( xIsCreateTaskStillRunning() != pdTRUE )
|
||||
{
|
||||
ulErrorFound = 1UL << 7UL;
|
||||
}
|
||||
|
||||
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
ulErrorFound = 1UL << 8UL;
|
||||
}
|
||||
|
||||
if( xAreTimerDemoTasksStillRunning( ( TickType_t ) xDelayPeriod ) != pdPASS )
|
||||
{
|
||||
ulErrorFound = 1UL << 9UL;
|
||||
}
|
||||
|
||||
if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
ulErrorFound = 1UL << 10UL;
|
||||
}
|
||||
|
||||
if( xAreEventGroupTasksStillRunning() != pdPASS )
|
||||
{
|
||||
ulErrorFound = 1UL << 12UL;
|
||||
}
|
||||
|
||||
if( xAreTaskNotificationTasksStillRunning() != pdPASS )
|
||||
{
|
||||
ulErrorFound = 1UL << 14UL;
|
||||
}
|
||||
|
||||
/* Check that the register test 1 task is still running. */
|
||||
if( ulLastRegTest1Value == ulRegTest1LoopCounter )
|
||||
{
|
||||
ulErrorFound = 1UL << 15UL;
|
||||
}
|
||||
ulLastRegTest1Value = ulRegTest1LoopCounter;
|
||||
|
||||
/* Check that the register test 2 task is still running. */
|
||||
if( ulLastRegTest2Value == ulRegTest2LoopCounter )
|
||||
{
|
||||
ulErrorFound = 1UL << 16UL;
|
||||
}
|
||||
ulLastRegTest2Value = ulRegTest2LoopCounter;
|
||||
|
||||
/* Toggle the check LED to give an indication of the system status. If
|
||||
the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then
|
||||
everything is ok. A faster toggle indicates an error. */
|
||||
mainTOGGLE_LED();
|
||||
|
||||
if( ulErrorFound != pdFALSE )
|
||||
{
|
||||
/* An error has been detected in one of the tasks - flash the LED
|
||||
at a higher frequency to give visible feedback that something has
|
||||
gone wrong (it might just be that the loop back connector required
|
||||
by the comtest tasks has not been fitted). */
|
||||
xDelayPeriod = mainERROR_CHECK_TASK_PERIOD;
|
||||
}
|
||||
|
||||
configASSERT( ulErrorFound == pdFALSE );
|
||||
|
||||
/* Just testing the xPortIsInsideInterrupt() functionality. */
|
||||
configASSERT( xPortIsInsideInterrupt() == pdFALSE );
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvRegTestTaskEntry1( void *pvParameters )
|
||||
{
|
||||
/* Although the regtest task is written in assembler, its entry point is
|
||||
written in C for convenience of checking the task parameter is being passed
|
||||
in correctly. */
|
||||
if( pvParameters == mainREG_TEST_TASK_1_PARAMETER )
|
||||
{
|
||||
/* Start the part of the test that is written in assembler. */
|
||||
vRegTest1Implementation();
|
||||
}
|
||||
|
||||
/* The following line will only execute if the task parameter is found to
|
||||
be incorrect. The check timer will detect that the regtest loop counter is
|
||||
not being incremented and flag an error. */
|
||||
vTaskDelete( NULL );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvRegTestTaskEntry2( void *pvParameters )
|
||||
{
|
||||
/* Although the regtest task is written in assembler, its entry point is
|
||||
written in C for convenience of checking the task parameter is being passed
|
||||
in correctly. */
|
||||
if( pvParameters == mainREG_TEST_TASK_2_PARAMETER )
|
||||
{
|
||||
/* Start the part of the test that is written in assembler. */
|
||||
vRegTest2Implementation();
|
||||
}
|
||||
|
||||
/* The following line will only execute if the task parameter is found to
|
||||
be incorrect. The check timer will detect that the regtest loop counter is
|
||||
not being incremented and flag an error. */
|
||||
vTaskDelete( NULL );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vFullDemoTickHook( void )
|
||||
{
|
||||
/* Some of the tests and demo tasks executed by the full demo include
|
||||
interaction from an interrupt - for which the tick interrupt is used via
|
||||
the tick hook function. */
|
||||
|
||||
/* The full demo includes a software timer demo/test that requires
|
||||
prodding periodically from the tick interrupt. */
|
||||
vTimerPeriodicISRTests();
|
||||
|
||||
/* Call the periodic event group from ISR demo. */
|
||||
vPeriodicEventGroupsProcessing();
|
||||
|
||||
/* Call the code that 'gives' a task notification from an ISR. */
|
||||
xNotifyTaskFromISR();
|
||||
}
|
||||
@ -0,0 +1,422 @@
|
||||
/*
|
||||
FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
|
||||
All rights reserved
|
||||
|
||||
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
|
||||
|
||||
***************************************************************************
|
||||
>>! NOTE: The modification to the GPL is included to allow you to !<<
|
||||
>>! distribute a combined work that includes FreeRTOS without being !<<
|
||||
>>! obliged to provide the source code for proprietary components !<<
|
||||
>>! outside of the FreeRTOS kernel. !<<
|
||||
***************************************************************************
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
|
||||
FOR A PARTICULAR PURPOSE. Full license text is available on the following
|
||||
link: http://www.freertos.org/a00114.html
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS provides completely free yet professionally developed, *
|
||||
* robust, strictly quality controlled, supported, and cross *
|
||||
* platform software that is more than just the market leader, it *
|
||||
* is the industry's de facto standard. *
|
||||
* *
|
||||
* Help yourself get started quickly while simultaneously helping *
|
||||
* to support the FreeRTOS project by purchasing a FreeRTOS *
|
||||
* tutorial book, reference manual, or both: *
|
||||
* http://www.FreeRTOS.org/Documentation *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
|
||||
the FAQ page "My application does not run, what could be wrong?". Have you
|
||||
defined configASSERT()?
|
||||
|
||||
http://www.FreeRTOS.org/support - In return for receiving this top quality
|
||||
embedded software for free we request you assist our global community by
|
||||
participating in the support forum.
|
||||
|
||||
http://www.FreeRTOS.org/training - Investing in training allows your team to
|
||||
be as productive as possible as early as possible. Now you can receive
|
||||
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
|
||||
Ltd, and the world's leading authority on the world's leading RTOS.
|
||||
|
||||
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
|
||||
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
|
||||
compatible FAT file system, and our tiny thread aware UDP/IP stack.
|
||||
|
||||
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
|
||||
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
|
||||
|
||||
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
|
||||
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
|
||||
licenses offer ticketed support, indemnification and commercial middleware.
|
||||
|
||||
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
|
||||
engineered and independently SIL3 certified version for use in safety and
|
||||
mission critical applications that require provable dependability.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
/* Standard includes. */
|
||||
#include <limits.h>
|
||||
|
||||
/* FreeRTOS includes. */
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
|
||||
/* Library includes. */
|
||||
#include "common_lib.h"
|
||||
|
||||
#define prvDisableInterrupts() __asm volatile ( "cpsid i" ); \
|
||||
__dsb( portSY_FULL_READ_WRITE ); \
|
||||
__isb( portSY_FULL_READ_WRITE );
|
||||
|
||||
#define prvSleep() __dsb( portSY_FULL_READ_WRITE ); \
|
||||
__wfi(); \
|
||||
__isb( portSY_FULL_READ_WRITE );
|
||||
|
||||
#define prvEnableInterrupts() __asm volatile ( "cpsie i" ); \
|
||||
__dsb( portSY_FULL_READ_WRITE ); \
|
||||
__isb( portSY_FULL_READ_WRITE );
|
||||
|
||||
/* This file contains functions that will override the default implementations
|
||||
in the RTOS port layer. Therefore only build this file if the low power demo
|
||||
is being built. */
|
||||
#if( configCREATE_LOW_POWER_DEMO == 1 )
|
||||
|
||||
/* ID of the hibernation timer used to generate the tick. */
|
||||
#define mainTICK_HTIMER_ID 0
|
||||
|
||||
/* Written to the hibernation timer control register to configure the timer for
|
||||
its higher resolution. */
|
||||
#define mainHTIMER_HIGH_RESOLUTION 0
|
||||
|
||||
/* The frequency of the hibernation timer when it is running at its higher
|
||||
resolution and low resolution respectively. */
|
||||
#define mainHIGHER_RESOLUTION_TIMER_HZ ( 32787UL ) /* (1000000us / 30.5us) as each LSB is 30.5us. */
|
||||
#define mainLOW_RESOLUTION_TIMER_HZ ( 8UL ) /* ( 1000ms / 125ms ) as each LSB is 0.125s. */
|
||||
|
||||
/* When lpINCLUDE_TEST_TIMER is set to 1 a basic timer is used to generate
|
||||
interrupts at a low frequency. The purpose being to bring the CPU out of its
|
||||
sleep mode by an interrupt other than the tick interrupt, and therefore
|
||||
allowing an additional past through the code to be tested. */
|
||||
#define lpINCLUDE_TEST_TIMER 0
|
||||
|
||||
/* Some registers are accessed directly as the library is not compatible with
|
||||
all the compilers used. */
|
||||
#define lpHTIMER_PRELOAD_REGISTER ( * ( uint16_t * ) 0x40009800 )
|
||||
#define lpHTIMER_CONTROL_REGISTER ( * ( uint16_t * ) 0x40009804 )
|
||||
#define lpHTIMER_COUNT_REGISTER ( * ( uint16_t * ) 0x40009808 )
|
||||
#define lpEC_GIRQ17_ENABLE_SET ( * ( uint32_t * ) 0x4000C0B8 )
|
||||
#define lpHTIMER_INTERRUPT_CONTROL_BIT ( 1UL << 20UL )
|
||||
|
||||
/*
|
||||
* The low power demo does not use the SysTick, so override the
|
||||
* vPortSetupTickInterrupt() function with an implementation that configures
|
||||
* the low power clock. NOTE: This function name must not be changed as it
|
||||
* is called from the RTOS portable layer.
|
||||
*/
|
||||
void vPortSetupTimerInterrupt( void );
|
||||
|
||||
/*
|
||||
* To fully test the low power tick processing it is necessary to sometimes
|
||||
* bring the MCU out of its sleep state by a method other than the tick
|
||||
* interrupt. Interrupts generated from a basic timer are used for this
|
||||
* purpose.
|
||||
*/
|
||||
#if( lpINCLUDE_TEST_TIMER == 1 )
|
||||
static void prvSetupBasicTimer( void );
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* The reload value to use in the timer to generate the tick interrupt -
|
||||
assumes the timer is running at its higher resolution. */
|
||||
static const uint32_t ulHighResolutionReloadValue = ( mainHIGHER_RESOLUTION_TIMER_HZ / configTICK_RATE_HZ );
|
||||
|
||||
/* Calculate how many clock increments make up a single tick period. */
|
||||
static const uint32_t ulReloadValueForOneHighResolutionTick = ( mainHIGHER_RESOLUTION_TIMER_HZ / configTICK_RATE_HZ );
|
||||
//static const uint32_t usReloadValueForOneLowResolutionTick = ( mainLOW_RESOLUTION_TIMER_HZ / configTICK_RATE_HZ );
|
||||
|
||||
/* Calculate the maximum number of ticks that can be suppressed when using the
|
||||
high resolution clock and low resolution clock respectively. */
|
||||
static uint32_t ulMaximumPossibleSuppressedHighResolutionTicks = 0;
|
||||
//static const uint16_t usMaximumPossibleSuppressedLowResolutionTicks = USHRT_MAX / usReloadValueForOneLowResolutionTick;
|
||||
|
||||
/* As the clock is only 2KHz, it is likely a value of 1 will be too much, so
|
||||
use zero - but leave the value here to assist porting to different clock
|
||||
speeds. */
|
||||
static const uint32_t ulStoppedTimerCompensation = 0UL;
|
||||
|
||||
/* Flag set from the tick interrupt to allow the sleep processing to know if
|
||||
sleep mode was exited because of an timer interrupt or a different interrupt. */
|
||||
static volatile uint32_t ulTickFlag = pdFALSE;
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void NVIC_Handler_HIB_TMR( void )
|
||||
{
|
||||
lpHTIMER_PRELOAD_REGISTER = ulHighResolutionReloadValue;
|
||||
|
||||
/* Increment the RTOS tick. */
|
||||
if( xTaskIncrementTick() != pdFALSE )
|
||||
{
|
||||
/* A context switch is required. Context switching is performed in
|
||||
the PendSV interrupt. Pend the PendSV interrupt. */
|
||||
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
|
||||
}
|
||||
|
||||
/* The CPU woke because of a tick. */
|
||||
ulTickFlag = pdTRUE;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if( lpINCLUDE_TEST_TIMER == 1 )
|
||||
|
||||
#define GIRQ23_ENABLE_SET ( * ( uint32_t * ) 0x4000C130 )
|
||||
|
||||
static void prvSetupBasicTimer( void )
|
||||
{
|
||||
const uint8_t ucTimerChannel = 0;
|
||||
const uint32_t ulTimer0Count = configCPU_CLOCK_HZ / 10;
|
||||
|
||||
GIRQ23_ENABLE_SET = 0x03;
|
||||
*(unsigned int*)0x4000FC18 = 1;
|
||||
|
||||
/* To fully test the low power tick processing it is necessary to sometimes
|
||||
bring the MCU out of its sleep state by a method other than the tick
|
||||
interrupt. Interrupts generated from a basic timer are used for this
|
||||
purpose. */
|
||||
btimer_init( ucTimerChannel, BTIMER_AUTO_RESTART | BTIMER_COUNT_DOWN | BTIMER_INT_EN, 0, ulTimer0Count, ulTimer0Count );
|
||||
btimer_interrupt_status_get_clr( ucTimerChannel );
|
||||
enable_timer0_irq();
|
||||
NVIC_SetPriority( TIMER0_IRQn, ucTimerChannel );
|
||||
NVIC_ClearPendingIRQ( TIMER0_IRQn );
|
||||
NVIC_EnableIRQ( TIMER0_IRQn );
|
||||
btimer_start( ucTimerChannel );
|
||||
}
|
||||
|
||||
#endif /* lpINCLUDE_TEST_TIMER */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortSetupTimerInterrupt( void )
|
||||
{
|
||||
ulMaximumPossibleSuppressedHighResolutionTicks = ( ( uint32_t ) USHRT_MAX ) / ulReloadValueForOneHighResolutionTick;
|
||||
|
||||
/* Set up the hibernation timer to start at the value required by the
|
||||
tick interrupt. Equivalent to the following libarary call. The library
|
||||
is not used as it is not compatible with all the compilers used:
|
||||
htimer_enable( mainTICK_HTIMER_ID, ulHighResolutionReloadValue, mainHTIMER_HIGH_RESOLUTION ); */
|
||||
lpHTIMER_PRELOAD_REGISTER = ulHighResolutionReloadValue;
|
||||
lpHTIMER_CONTROL_REGISTER = mainHTIMER_HIGH_RESOLUTION;
|
||||
|
||||
/* Enable the HTIMER interrupt. Equivalent to enable_htimer0_irq(); */
|
||||
lpEC_GIRQ17_ENABLE_SET |= lpHTIMER_INTERRUPT_CONTROL_BIT;
|
||||
|
||||
/* The hibernation timer is not an auto-reload timer, so gets reset
|
||||
from within the ISR itself. For that reason it's interrupt is set
|
||||
to the highest possible priority to ensure clock slippage is minimised. */
|
||||
NVIC_SetPriority( HTIMER_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
|
||||
NVIC_ClearPendingIRQ( HTIMER_IRQn );
|
||||
NVIC_EnableIRQ( HTIMER_IRQn );
|
||||
|
||||
/* A basic timer is also started, purely for test purposes. Its only
|
||||
purpose is to bring the CPU out of its sleep mode by an interrupt other
|
||||
than the tick interrupt in order to get more code test coverage. */
|
||||
#if( lpINCLUDE_TEST_TIMER == 1 )
|
||||
{
|
||||
prvSetupBasicTimer();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Override the default definition of vPortSuppressTicksAndSleep() that is
|
||||
weakly defined in the FreeRTOS Cortex-M port layer with a version that manages
|
||||
the hibernation timer, as the tick is generated from the low power hibernation
|
||||
timer and not the SysTick as would normally be the case on a Cortex-M. */
|
||||
void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
|
||||
{
|
||||
uint32_t ulCompleteTickPeriods, ulReloadValue, ulCompletedTimerDecrements, ulCountAfterSleep, ulCountBeforeSleep;
|
||||
eSleepModeStatus eSleepAction;
|
||||
TickType_t xModifiableIdleTime;
|
||||
|
||||
/* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
|
||||
|
||||
/* Make sure the hibernation timer reload value does not overflow the
|
||||
counter. */
|
||||
if( xExpectedIdleTime > ( TickType_t ) ulMaximumPossibleSuppressedHighResolutionTicks )
|
||||
{
|
||||
xExpectedIdleTime = ( TickType_t ) ulMaximumPossibleSuppressedHighResolutionTicks;
|
||||
}
|
||||
|
||||
/* Stop the timer momentarily. The time the timer is stopped for is
|
||||
accounted for as best it can be, but using the tickless mode will
|
||||
inevitably result in some tiny drift of the time maintained by the kernel
|
||||
with respect to calendar time. Take the count value first as clearing
|
||||
the preload value also seems to clear the count. */
|
||||
ulCountBeforeSleep = ( uint32_t ) lpHTIMER_COUNT_REGISTER;
|
||||
lpHTIMER_PRELOAD_REGISTER = 0;
|
||||
|
||||
/* Calculate the reload value required to wait xExpectedIdleTime tick
|
||||
periods. -1 is used as the current time slice will already be part way
|
||||
through, the part value coming from the current timer count value. */
|
||||
ulReloadValue = ulCountBeforeSleep + ( ulReloadValueForOneHighResolutionTick * ( xExpectedIdleTime - 1UL ) );
|
||||
|
||||
if( ulReloadValue > ulStoppedTimerCompensation )
|
||||
{
|
||||
/* Compensate for the fact that the timer is going to be stopped
|
||||
momentarily. */
|
||||
ulReloadValue -= ulStoppedTimerCompensation;
|
||||
}
|
||||
|
||||
/* Enter a critical section but don't use the taskENTER_CRITICAL() method as
|
||||
that will mask interrupts that should exit sleep mode. */
|
||||
prvDisableInterrupts();
|
||||
|
||||
/* The tick flag is set to false before sleeping. If it is true when sleep
|
||||
mode is exited then sleep mode was probably exited because the tick was
|
||||
suppressed for the entire xExpectedIdleTime period. */
|
||||
ulTickFlag = pdFALSE;
|
||||
|
||||
/* If a context switch is pending then abandon the low power entry as
|
||||
the context switch might have been pended by an external interrupt that
|
||||
requires processing. */
|
||||
eSleepAction = eTaskConfirmSleepModeStatus();
|
||||
if( eSleepAction == eAbortSleep )
|
||||
{
|
||||
/* Resetart the timer from whatever remains in the counter register,
|
||||
but 0 is not a valid value. */
|
||||
ulReloadValue = ulCountBeforeSleep - ulStoppedTimerCompensation;
|
||||
|
||||
if( ulReloadValue == 0 )
|
||||
{
|
||||
ulReloadValue = ulReloadValueForOneHighResolutionTick;
|
||||
ulCompleteTickPeriods = 1UL;
|
||||
}
|
||||
else
|
||||
{
|
||||
ulCompleteTickPeriods = 0UL;
|
||||
}
|
||||
|
||||
lpHTIMER_PRELOAD_REGISTER = ( uint16_t ) ulReloadValue;
|
||||
|
||||
/* Re-enable interrupts - see comments above the cpsid instruction()
|
||||
above. */
|
||||
prvEnableInterrupts();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Write the calculated reload value, which will also start the
|
||||
timer. */
|
||||
lpHTIMER_PRELOAD_REGISTER = ( uint16_t ) ulReloadValue;
|
||||
|
||||
/* Allow the application to define some pre-sleep processing. */
|
||||
xModifiableIdleTime = xExpectedIdleTime;
|
||||
configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
|
||||
|
||||
/* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
|
||||
means the application defined code has already executed the sleep
|
||||
instructions. */
|
||||
if( xModifiableIdleTime > 0 )
|
||||
{
|
||||
prvSleep();
|
||||
}
|
||||
|
||||
/* Allow the application to define some post sleep processing. */
|
||||
configPOST_SLEEP_PROCESSING( xModifiableIdleTime );
|
||||
|
||||
/* Stop the hibernation timer. Again, the time the tiemr is stopped
|
||||
for is accounted for as best it can be, but using the tickless mode
|
||||
will inevitably result in some tiny drift of the time maintained by the
|
||||
kernel with respect to calendar time. Take the count value first as
|
||||
setting the preload to zero also seems to clear the count. */
|
||||
ulCountAfterSleep = lpHTIMER_COUNT_REGISTER;
|
||||
lpHTIMER_PRELOAD_REGISTER = 0;
|
||||
|
||||
/* Re-enable interrupts - see comments above the cpsid instruction()
|
||||
above. */
|
||||
prvEnableInterrupts();
|
||||
|
||||
if( ulTickFlag != pdFALSE )
|
||||
{
|
||||
/* The tick interrupt has already executed, although because this
|
||||
function is called with the scheduler suspended the actual tick
|
||||
processing will not occur until after this function has exited.
|
||||
The timer has already been reloaded to count in ticks, and can just
|
||||
continue counting down from its current value. */
|
||||
ulReloadValue = ulCountAfterSleep;
|
||||
|
||||
/* Sanity check that the timer's reload value has indeed been
|
||||
reset. */
|
||||
configASSERT( ( uint32_t ) lpHTIMER_PRELOAD_REGISTER == ulReloadValueForOneHighResolutionTick );
|
||||
|
||||
/* The tick interrupt handler will already have pended the tick
|
||||
processing in the kernel. As the pending tick will be processed as
|
||||
soon as this function exits, the tick value maintained by the tick
|
||||
is stepped forward by one less than the time spent sleeping. The
|
||||
actual stepping of the tick appears later in this function. */
|
||||
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Something other than the tick interrupt ended the sleep. How
|
||||
many complete tick periods passed while the processor was
|
||||
sleeping? */
|
||||
ulCompletedTimerDecrements = ulReloadValue - ulCountAfterSleep;
|
||||
|
||||
/* Undo the adjustment that was made to the reload value to account
|
||||
for the fact that a time slice was part way through when this
|
||||
function was called before working out how many complete tick
|
||||
periods this represents. (could have used [ulExpectedIdleTime *
|
||||
ulReloadValueForOneHighResolutionTick] instead of ulReloadValue on
|
||||
the previous line, but this way avoids the multiplication). */
|
||||
ulCompletedTimerDecrements += ( ulReloadValueForOneHighResolutionTick - ulCountBeforeSleep );
|
||||
ulCompleteTickPeriods = ulCompletedTimerDecrements / ulReloadValueForOneHighResolutionTick;
|
||||
|
||||
/* The reload value is set to whatever fraction of a single tick
|
||||
period remains. */
|
||||
ulReloadValue = ( ( ulCompleteTickPeriods + 1UL ) * ulReloadValueForOneHighResolutionTick ) - ulCompletedTimerDecrements;
|
||||
}
|
||||
|
||||
/* Cannot use a reload value of 0 - it will not start the timer. */
|
||||
if( ulReloadValue == 0 )
|
||||
{
|
||||
/* There is no fraction remaining. */
|
||||
ulReloadValue = ulReloadValueForOneHighResolutionTick;
|
||||
ulCompleteTickPeriods++;
|
||||
}
|
||||
|
||||
/* Restart the timer so it runs down from the reload value. The reload
|
||||
value will get set to the value required to generate exactly one tick
|
||||
period the next time the tick interrupt executes. */
|
||||
lpHTIMER_PRELOAD_REGISTER = ( uint16_t ) ulReloadValue;
|
||||
}
|
||||
|
||||
/* Wind the tick forward by the number of tick periods that the CPU
|
||||
remained in a low power state. */
|
||||
vTaskStepTick( ulCompleteTickPeriods );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void NVIC_Handler_TMR0( void )
|
||||
{
|
||||
/* This timer is used for test purposes. Its only function is to
|
||||
generate interrupts while the MCU is sleeping, so the MCU is sometimes
|
||||
brought out of sleep by a means other than the tick interrupt. */
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
||||
#endif /* configCREATE_LOW_POWER_DEMO */
|
||||
|
||||
@ -0,0 +1,237 @@
|
||||
/*
|
||||
FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
|
||||
All rights reserved
|
||||
|
||||
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
|
||||
|
||||
***************************************************************************
|
||||
>>! NOTE: The modification to the GPL is included to allow you to !<<
|
||||
>>! distribute a combined work that includes FreeRTOS without being !<<
|
||||
>>! obliged to provide the source code for proprietary components !<<
|
||||
>>! outside of the FreeRTOS kernel. !<<
|
||||
***************************************************************************
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
|
||||
FOR A PARTICULAR PURPOSE. Full license text is available on the following
|
||||
link: http://www.freertos.org/a00114.html
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS provides completely free yet professionally developed, *
|
||||
* robust, strictly quality controlled, supported, and cross *
|
||||
* platform software that is more than just the market leader, it *
|
||||
* is the industry's de facto standard. *
|
||||
* *
|
||||
* Help yourself get started quickly while simultaneously helping *
|
||||
* to support the FreeRTOS project by purchasing a FreeRTOS *
|
||||
* tutorial book, reference manual, or both: *
|
||||
* http://www.FreeRTOS.org/Documentation *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
|
||||
the FAQ page "My application does not run, what could be wrong?". Have you
|
||||
defined configASSERT()?
|
||||
|
||||
http://www.FreeRTOS.org/support - In return for receiving this top quality
|
||||
embedded software for free we request you assist our global community by
|
||||
participating in the support forum.
|
||||
|
||||
http://www.FreeRTOS.org/training - Investing in training allows your team to
|
||||
be as productive as possible as early as possible. Now you can receive
|
||||
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
|
||||
Ltd, and the world's leading authority on the world's leading RTOS.
|
||||
|
||||
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
|
||||
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
|
||||
compatible FAT file system, and our tiny thread aware UDP/IP stack.
|
||||
|
||||
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
|
||||
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
|
||||
|
||||
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
|
||||
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
|
||||
licenses offer ticketed support, indemnification and commercial middleware.
|
||||
|
||||
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
|
||||
engineered and independently SIL3 certified version for use in safety and
|
||||
mission critical applications that require provable dependability.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* NOTE 1: This project provides two demo applications. A simple blinky demo
|
||||
* that demonstrates tickless low power operation, and a more comprehensive
|
||||
* test and demo application. The configCREATE_LOW_POWER_DEMO setting in
|
||||
* FreeRTOSConfig.h is used to select between the two. See the notes on using
|
||||
* configCREATE_LOW_POWER_DEMO in main.c. This file implements the low power
|
||||
* version.
|
||||
*
|
||||
* NOTE 2: This file only contains the source code that is specific to the
|
||||
* low power demo. Generic functions, such FreeRTOS hook functions, and
|
||||
* functions required to configure the hardware are defined in main.c.
|
||||
******************************************************************************
|
||||
*
|
||||
* main_low_power() creates one queue, and two tasks. It then starts the
|
||||
* scheduler.
|
||||
*
|
||||
* The Queue Send Task:
|
||||
* The queue send task is implemented by the prvQueueSendTask() function in
|
||||
* this file. It sends the value 100 to the queue every second.
|
||||
*
|
||||
* The Queue Receive Task:
|
||||
* The queue receive task is implemented by the prvQueueReceiveTask() function
|
||||
* in this file. prvQueueReceiveTask() blocks on the queue, blipping (quickly
|
||||
* turn on then off again) the LED each time it received the value 100 from the
|
||||
* queue send task. The queue send task writes to the queue every second, so
|
||||
* the LED will blip once a second.
|
||||
*
|
||||
* The RTOS tick is turned off when the queue send task and queue receive task
|
||||
* are both in the Blocked state.
|
||||
*
|
||||
*/
|
||||
|
||||
/* Kernel includes. */
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
#include "semphr.h"
|
||||
|
||||
/* Priorities at which the tasks are created. */
|
||||
#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
|
||||
#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
|
||||
|
||||
/* The rate at which data is sent to the queue. The 200ms value is converted
|
||||
to ticks using the portTICK_PERIOD_MS constant. */
|
||||
#define mainQUEUE_SEND_FREQUENCY_MS pdMS_TO_TICKS( 1000 )
|
||||
|
||||
/* The number of items the queue can hold. This is 1 as the receive task
|
||||
will remove items as they are added, meaning the send task should always find
|
||||
the queue empty. */
|
||||
#define mainQUEUE_LENGTH ( 1 )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* Called by main when configCREATE_LOW_POWER_DEMO is set to 1 in
|
||||
* main.c.
|
||||
*/
|
||||
void main_low_power( void );
|
||||
|
||||
/*
|
||||
* The tasks as described in the comments at the top of this file.
|
||||
*/
|
||||
static void prvQueueReceiveTask( void *pvParameters );
|
||||
static void prvQueueSendTask( void *pvParameters );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* The queue used by both tasks. */
|
||||
static QueueHandle_t xQueue = NULL;
|
||||
|
||||
/* The variable that is incremented to represent each LED toggle. On the
|
||||
clicker hardware the LED state is set to the value of the least significant bit
|
||||
of this variable. On other hardware, where an LED is not used, the LED just
|
||||
keeps a count of the number of times the LED would otherwise have been toggled.
|
||||
See the comments at the top of this file for information on the expected LED
|
||||
toggle rate. */
|
||||
extern volatile uint32_t ulLED;
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void main_low_power( void )
|
||||
{
|
||||
/* Create the queue. */
|
||||
xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) );
|
||||
|
||||
if( xQueue != NULL )
|
||||
{
|
||||
/* Start the two tasks as described in the comments at the top of this
|
||||
file. */
|
||||
xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */
|
||||
"Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */
|
||||
configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */
|
||||
NULL, /* The parameter passed to the task - not used in this case. */
|
||||
mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */
|
||||
NULL ); /* The task handle is not required, so NULL is passed. */
|
||||
|
||||
xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );
|
||||
|
||||
/* Start the tasks and timer running. */
|
||||
vTaskStartScheduler();
|
||||
}
|
||||
|
||||
/* If all is well, the scheduler will now be running, and the following
|
||||
line will never be reached. If the following line does execute, then
|
||||
there was insufficient FreeRTOS heap memory available for the Idle and/or
|
||||
timer tasks to be created. See the memory management section on the
|
||||
FreeRTOS web site for more details on the FreeRTOS heap
|
||||
http://www.freertos.org/a00111.html. */
|
||||
for( ;; );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvQueueSendTask( void *pvParameters )
|
||||
{
|
||||
TickType_t xNextWakeTime;
|
||||
const uint32_t ulValueToSend = 100UL;
|
||||
|
||||
/* Remove compiler warning about unused parameter. */
|
||||
( void ) pvParameters;
|
||||
|
||||
/* Initialise xNextWakeTime - this only needs to be done once. */
|
||||
xNextWakeTime = xTaskGetTickCount();
|
||||
|
||||
for( ;; )
|
||||
{
|
||||
/* Place this task in the blocked state until it is time to run again. */
|
||||
vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );
|
||||
|
||||
/* Send to the queue - causing the queue receive task to unblock and
|
||||
toggle the LED. 0 is used as the block time so the sending operation
|
||||
will not block - it shouldn't need to block as the queue should always
|
||||
be empty at this point in the code. */
|
||||
xQueueSend( xQueue, &ulValueToSend, 0U );
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvQueueReceiveTask( void *pvParameters )
|
||||
{
|
||||
uint32_t ulReceivedValue;
|
||||
const uint32_t ulExpectedValue = 100UL;
|
||||
const TickType_t xShortDelay = pdMS_TO_TICKS( 10 );
|
||||
|
||||
/* Remove compiler warning about unused parameter. */
|
||||
( void ) pvParameters;
|
||||
|
||||
for( ;; )
|
||||
{
|
||||
/* Wait until something arrives in the queue - this task will block
|
||||
indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
|
||||
FreeRTOSConfig.h. */
|
||||
xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
|
||||
|
||||
/* To get here something must have been received from the queue, but
|
||||
is it the expected value? If it is, toggle the LED. */
|
||||
if( ulReceivedValue == ulExpectedValue )
|
||||
{
|
||||
/* Blip the LED briefly to show the demo is running, but without
|
||||
leaving the LED on too long as energy is being conserved. */
|
||||
mainTOGGLE_LED();
|
||||
vTaskDelay( xShortDelay );
|
||||
mainTOGGLE_LED();
|
||||
|
||||
ulReceivedValue = 0U;
|
||||
}
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
@ -0,0 +1,194 @@
|
||||
/*
|
||||
**********************************************************************************
|
||||
* © 2013 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
**********************************************************************************
|
||||
* ARM_REG.h
|
||||
* This is the header to define Cortex-M3 system control & status registers
|
||||
**********************************************************************************
|
||||
* SMSC version control information (Perforce):
|
||||
*
|
||||
* FILE: $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/ARM_REG.h $
|
||||
* REVISION: $Revision: #1 $
|
||||
* DATETIME: $DateTime: 2015/12/23 15:37:58 $
|
||||
* AUTHOR: $Author: akrishnan $
|
||||
*
|
||||
* Revision history (latest first):
|
||||
* #xx
|
||||
***********************************************************************************
|
||||
*/
|
||||
|
||||
/******************************************************************************/
|
||||
/** @defgroup ARM_REG ARM_REG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @file ARM_REG.h
|
||||
* \brief ARM Cortex-M3 registers header file
|
||||
* \author KBCEC Team
|
||||
*
|
||||
* This file contains ARM Cortex-M3 system control & status registers.
|
||||
******************************************************************************/
|
||||
#ifndef ARM_REG_H_
|
||||
#define ARM_REG_H_
|
||||
|
||||
#define REG8(x) (*((volatile unsigned char *)(x)))
|
||||
#define REG16(x) (*((volatile unsigned short *)(x)))
|
||||
#define REG32(x) (*((volatile unsigned long *)(x)))
|
||||
|
||||
/* NVIC Registers */
|
||||
#define NVIC_INT_TYPE REG32(0xE000E004)
|
||||
#define NVIC_AUX_ACTLR REG32(0xE000E008)
|
||||
#define WR_BUF_DISABLE (1 << 1)
|
||||
#define NVIC_ST_CTRL REG32(0xE000E010)
|
||||
#define ST_ENABLE (1 << 0)
|
||||
#define ST_TICKINT (1 << 1)
|
||||
#define ST_CLKSOURCE (1 << 2)
|
||||
#define ST_COUNTFLAG (1 << 3)
|
||||
#define NVIC_ST_RELOAD REG32(0xE000E014)
|
||||
#define NVIC_ST_CURRENT REG32(0xE000E018)
|
||||
#define NVIC_ST_CALIB REG32(0xE000E01C)
|
||||
#define NVIC_ENABLE0 REG32(0xE000E100)
|
||||
#define NVIC_ENABLE1 REG32(0xE000E104)
|
||||
#define NVIC_ENABLE2 REG32(0xE000E108)
|
||||
#define NVIC_ENABLE3 REG32(0xE000E10C)
|
||||
#define NVIC_ENABLE4 REG32(0xE000E110)
|
||||
#define NVIC_ENABLE5 REG32(0xE000E114)
|
||||
#define NVIC_ENABLE6 REG32(0xE000E118)
|
||||
#define NVIC_ENABLE7 REG32(0xE000E11C)
|
||||
#define NVIC_DISABLE0 REG32(0xE000E180)
|
||||
#define NVIC_DISABLE1 REG32(0xE000E184)
|
||||
#define NVIC_DISABLE2 REG32(0xE000E188)
|
||||
#define NVIC_DISABLE3 REG32(0xE000E18C)
|
||||
#define NVIC_DISABLE4 REG32(0xE000E190)
|
||||
#define NVIC_DISABLE5 REG32(0xE000E194)
|
||||
#define NVIC_DISABLE6 REG32(0xE000E198)
|
||||
#define NVIC_DISABLE7 REG32(0xE000E19C)
|
||||
#define NVIC_PEND0 REG32(0xE000E200)
|
||||
#define NVIC_PEND1 REG32(0xE000E204)
|
||||
#define NVIC_PEND2 REG32(0xE000E208)
|
||||
#define NVIC_PEND3 REG32(0xE000E20C)
|
||||
#define NVIC_PEND4 REG32(0xE000E210)
|
||||
#define NVIC_PEND5 REG32(0xE000E214)
|
||||
#define NVIC_PEND6 REG32(0xE000E218)
|
||||
#define NVIC_PEND7 REG32(0xE000E21C)
|
||||
#define NVIC_UNPEND0 REG32(0xE000E280)
|
||||
#define NVIC_UNPEND1 REG32(0xE000E284)
|
||||
#define NVIC_UNPEND2 REG32(0xE000E288)
|
||||
#define NVIC_UNPEND3 REG32(0xE000E28C)
|
||||
#define NVIC_UNPEND4 REG32(0xE000E290)
|
||||
#define NVIC_UNPEND5 REG32(0xE000E294)
|
||||
#define NVIC_UNPEND6 REG32(0xE000E298)
|
||||
#define NVIC_UNPEND7 REG32(0xE000E29C)
|
||||
#define NVIC_ACTIVE0 REG32(0xE000E300)
|
||||
#define NVIC_ACTIVE1 REG32(0xE000E304)
|
||||
#define NVIC_ACTIVE2 REG32(0xE000E308)
|
||||
#define NVIC_ACTIVE3 REG32(0xE000E30C)
|
||||
#define NVIC_ACTIVE4 REG32(0xE000E310)
|
||||
#define NVIC_ACTIVE5 REG32(0xE000E314)
|
||||
#define NVIC_ACTIVE6 REG32(0xE000E318)
|
||||
#define NVIC_ACTIVE7 REG32(0xE000E31C)
|
||||
#define NVIC_PRI0 REG32(0xE000E400)
|
||||
#define NVIC_PRI1 REG32(0xE000E404)
|
||||
#define NVIC_PRI2 REG32(0xE000E408)
|
||||
#define NVIC_PRI3 REG32(0xE000E40C)
|
||||
#define NVIC_PRI4 REG32(0xE000E410)
|
||||
#define NVIC_PRI5 REG32(0xE000E414)
|
||||
#define NVIC_PRI6 REG32(0xE000E418)
|
||||
#define NVIC_PRI7 REG32(0xE000E41C)
|
||||
#define NVIC_PRI8 REG32(0xE000E420)
|
||||
#define NVIC_PRI9 REG32(0xE000E424)
|
||||
#define NVIC_PRI10 REG32(0xE000E428)
|
||||
#define NVIC_PRI11 REG32(0xE000E42C)
|
||||
#define NVIC_PRI12 REG32(0xE000E430)
|
||||
#define NVIC_PRI13 REG32(0xE000E434)
|
||||
#define NVIC_PRI14 REG32(0xE000E438)
|
||||
#define NVIC_PRI15 REG32(0xE000E43C)
|
||||
#define NVIC_PRI16 REG32(0xE000E440)
|
||||
#define NVIC_PRI17 REG32(0xE000E444)
|
||||
#define NVIC_PRI18 REG32(0xE000E448)
|
||||
#define NVIC_PRI19 REG32(0xE000E44C)
|
||||
#define NVIC_PRI20 REG32(0xE000E450)
|
||||
#define NVIC_PRI21 REG32(0xE000E454)
|
||||
#define NVIC_PRI22 REG32(0xE000E458)
|
||||
#define NVIC_PRI23 REG32(0xE000E45C)
|
||||
#define NVIC_PRI24 REG32(0xE000E460)
|
||||
#define NVIC_PRI25 REG32(0xE000E464)
|
||||
#define NVIC_PRI26 REG32(0xE000E468)
|
||||
#define NVIC_PRI27 REG32(0xE000E46C)
|
||||
#define NVIC_PRI28 REG32(0xE000E470)
|
||||
#define NVIC_PRI29 REG32(0xE000E474)
|
||||
#define NVIC_PRI30 REG32(0xE000E478)
|
||||
#define NVIC_PRI31 REG32(0xE000E47C)
|
||||
#define NVIC_PRI32 REG32(0xE000E480)
|
||||
#define NVIC_PRI33 REG32(0xE000E484)
|
||||
#define NVIC_PRI34 REG32(0xE000E488)
|
||||
#define NVIC_PRI35 REG32(0xE000E48C)
|
||||
#define NVIC_PRI36 REG32(0xE000E490)
|
||||
#define NVIC_PRI37 REG32(0xE000E494)
|
||||
#define NVIC_PRI38 REG32(0xE000E498)
|
||||
#define NVIC_PRI39 REG32(0xE000E49C)
|
||||
#define NVIC_PRI40 REG32(0xE000E4A0)
|
||||
#define NVIC_PRI41 REG32(0xE000E4A4)
|
||||
#define NVIC_PRI42 REG32(0xE000E4A8)
|
||||
#define NVIC_PRI43 REG32(0xE000E4AC)
|
||||
#define NVIC_PRI44 REG32(0xE000E4B0)
|
||||
#define NVIC_PRI45 REG32(0xE000E4B4)
|
||||
#define NVIC_PRI46 REG32(0xE000E4B8)
|
||||
#define NVIC_PRI47 REG32(0xE000E4BC)
|
||||
#define NVIC_PRI48 REG32(0xE000E4C0)
|
||||
#define NVIC_PRI49 REG32(0xE000E4C4)
|
||||
#define NVIC_PRI50 REG32(0xE000E4C8)
|
||||
#define NVIC_PRI51 REG32(0xE000E4CC)
|
||||
#define NVIC_PRI52 REG32(0xE000E4D0)
|
||||
#define NVIC_PRI53 REG32(0xE000E4D4)
|
||||
#define NVIC_PRI54 REG32(0xE000E4D8)
|
||||
#define NVIC_PRI55 REG32(0xE000E4DC)
|
||||
#define NVIC_PRI56 REG32(0xE000E4E0)
|
||||
#define NVIC_PRI57 REG32(0xE000E4E4)
|
||||
#define NVIC_PRI58 REG32(0xE000E4E8)
|
||||
#define NVIC_PRI59 REG32(0xE000E4EC)
|
||||
#define NVIC_CPUID REG32(0xE000ED00)
|
||||
#define NVIC_INT_CTRL REG32(0xE000ED04)
|
||||
#define NVIC_VECT_TABLE REG32(0xE000ED08)
|
||||
#define NVIC_AP_INT_RST REG32(0xE000ED0C)
|
||||
#define NVIC_SYS_CTRL REG32(0xE000ED10)
|
||||
#define NVIC_CFG_CTRL REG32(0xE000ED14)
|
||||
#define NVIC_SYS_H_PRI1 REG32(0xE000ED18)
|
||||
#define NVIC_SYS_H_PRI2 REG32(0xE000ED1C)
|
||||
#define NVIC_SYS_H_PRI3 REG32(0xE000ED20)
|
||||
#define NVIC_SYS_H_CTRL REG32(0xE000ED24)
|
||||
#define NVIC_FAULT_STA REG32(0xE000ED28)
|
||||
#define NVIC_HARD_F_STA REG32(0xE000ED2C)
|
||||
#define NVIC_DBG_F_STA REG32(0xE000ED30)
|
||||
#define NVIC_MM_F_ADR REG32(0xE000ED34)
|
||||
#define NVIC_BUS_F_ADR REG32(0xE000ED38)
|
||||
#define NVIC_SW_TRIG REG32(0xE000EF00)
|
||||
|
||||
/* MPU Registers */
|
||||
#define MPU_TYPE REG32(0xE000ED90)
|
||||
#define MPU_CTRL REG32(0xE000ED94)
|
||||
#define MPU_RG_NUM REG32(0xE000ED98)
|
||||
#define MPU_RG_ADDR REG32(0xE000ED9C)
|
||||
#define MPU_RG_AT_SZ REG32(0xE000EDA0)
|
||||
|
||||
|
||||
#endif /* #ifndef ARM_REG_H_ */
|
||||
|
||||
/** @}
|
||||
*/
|
||||
@ -0,0 +1,691 @@
|
||||
/*****************************************************************************
|
||||
* © 2015 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
|
||||
#ifndef INCLUDE_CEC1302_CRYPTO_API_H_
|
||||
#define INCLUDE_CEC1302_CRYPTO_API_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Misc. */
|
||||
|
||||
/* RNG */
|
||||
/**
|
||||
* \rng_power
|
||||
*
|
||||
* \param [in] pwr_on Power On?
|
||||
* \return none
|
||||
*
|
||||
* \details Gate clocks on/off to NDRNG block
|
||||
*/
|
||||
extern void
|
||||
rng_power(bool pwr_on);
|
||||
|
||||
|
||||
/**
|
||||
* \rng_reset
|
||||
*
|
||||
* \return Reset NDRNG block
|
||||
*
|
||||
* \details
|
||||
*/
|
||||
extern void
|
||||
rng_reset(void);
|
||||
|
||||
|
||||
/**
|
||||
* \rng_mode
|
||||
*
|
||||
* \param [in] mode tmode_pseudo 0(asynchronous/true random mode),
|
||||
* Non-zero(pseudo-random mode)
|
||||
* \return None
|
||||
*
|
||||
* \details Set NDRNG random number generation mode
|
||||
*/
|
||||
extern void
|
||||
rng_mode(uint8_t mode);
|
||||
|
||||
|
||||
/**
|
||||
* \rng_is_on
|
||||
*
|
||||
* \return is NDRNG Block powered on? True if yes, false otherwise
|
||||
*
|
||||
* \details Check if NDRNG block is powered on.
|
||||
*/
|
||||
extern bool
|
||||
rng_is_on(void);
|
||||
|
||||
|
||||
/**
|
||||
* \rng_start
|
||||
*
|
||||
* \return None
|
||||
*
|
||||
* \details Start NDRNG engine
|
||||
*/
|
||||
extern void
|
||||
rng_start(void);
|
||||
|
||||
/**
|
||||
* \rng_stop
|
||||
*
|
||||
* \return Void
|
||||
*
|
||||
* \details Stop NDRNG engine
|
||||
*/
|
||||
extern void
|
||||
rng_stop(void);
|
||||
|
||||
|
||||
/**
|
||||
* \rng_get_fifo_level
|
||||
*
|
||||
* \return actual number of 32-bit words in the NDRNG FIFO.
|
||||
*
|
||||
* \details return the number of 32-bit words of random data
|
||||
* currently in the FIFO.
|
||||
*/
|
||||
extern uint32_t
|
||||
rng_get_fifo_level(void);
|
||||
|
||||
|
||||
/**
|
||||
* \rng_get_bytes
|
||||
*
|
||||
* \param [in] pbuff Output Buffer
|
||||
* \param [in] nbytes Number of bytes to be read
|
||||
* \return Number of bytes retrieved
|
||||
*
|
||||
* \details read bytes from the NDRNG FIFO
|
||||
*/
|
||||
extern uint32_t
|
||||
rng_get_bytes(uint8_t* pbuff, uint32_t nbytes);
|
||||
|
||||
|
||||
/**
|
||||
* \rng_get_words
|
||||
*
|
||||
* \param [in] pwords Pointer to output buffer
|
||||
* \param [in] nwords Number of words to read
|
||||
* \return actual number of words read
|
||||
*
|
||||
* \details Details
|
||||
*/
|
||||
extern uint32_t
|
||||
rng_get_words(uint32_t* pwords, uint32_t nwords);
|
||||
|
||||
|
||||
/* AES */
|
||||
/**
|
||||
* \aes_hash_power
|
||||
*
|
||||
* \param [in] pwr_on Gate/Ungate clocks to block
|
||||
* \return None
|
||||
*
|
||||
* \details Enable/Disable AES and HASH H/W Block
|
||||
*/
|
||||
extern void
|
||||
aes_hash_power(uint8_t pwr_on);
|
||||
|
||||
/**
|
||||
* \aes_hash_reset
|
||||
*
|
||||
* \return None
|
||||
*
|
||||
* \details Stop AES and HASH
|
||||
*/
|
||||
extern void
|
||||
aes_hash_reset(void);
|
||||
|
||||
/**
|
||||
* \aes_busy
|
||||
*
|
||||
* \return Is AES Block Running? True if yes, false Otherwise.
|
||||
*
|
||||
* \details Is AES Block Running?
|
||||
*/
|
||||
extern bool
|
||||
aes_busy(void);
|
||||
|
||||
|
||||
/**
|
||||
* \aes_status
|
||||
*
|
||||
* \return Status of AES Block
|
||||
*
|
||||
* \details Returns the Status of AES Block
|
||||
*/
|
||||
extern uint32_t
|
||||
aes_status(void);
|
||||
|
||||
/**
|
||||
* \aes_done_status
|
||||
*
|
||||
* \param [in] hw_status Pointer to where the status value will be updated
|
||||
* \return True if done, false otherwise
|
||||
*
|
||||
* \details Returns the done status of AES block
|
||||
*/
|
||||
extern bool
|
||||
aes_done_status(uint32_t* hw_status);
|
||||
|
||||
/**
|
||||
* \aes_stop
|
||||
*
|
||||
* \return Return aes_busy() Status
|
||||
*
|
||||
* \details Stop AES Operations
|
||||
*/
|
||||
extern bool
|
||||
aes_stop(void);
|
||||
|
||||
/**
|
||||
* \aes_start
|
||||
*
|
||||
* \param [in] ien Enable interrupts?
|
||||
* \return None
|
||||
*
|
||||
* \details Start AES block with or without interrupts
|
||||
*/
|
||||
extern void
|
||||
aes_start(bool ien);
|
||||
|
||||
/**
|
||||
* \aes_iclr
|
||||
*
|
||||
* \return Status of the AES Block
|
||||
*
|
||||
* \details Clears AES Hash Interrupts
|
||||
*/
|
||||
extern uint32_t
|
||||
aes_iclr(void);
|
||||
|
||||
|
||||
/**
|
||||
* \brief Brief
|
||||
*
|
||||
* \param [in] pkey Aligned buffer with AES Key
|
||||
* \param [in] piv Aligned buffer with AES initialization
|
||||
* \param [in] key_len AES_KEYLEN_128, AES_KEYLEN_192, AES_KEYLEN_256
|
||||
* \param [in] msbf Most Significant Byte order first?
|
||||
* \return AES_ERR_BAD_POINTER, AES_ERR_BAD_KEY_LEN, AES_OK
|
||||
*
|
||||
* \details Load AES Accelerator with key and optional Initialization vector
|
||||
*/
|
||||
extern uint8_t
|
||||
aes_set_key(const uint32_t* pkey,
|
||||
const uint32_t* piv,
|
||||
uint8_t key_len, bool msbf);
|
||||
|
||||
/**
|
||||
* \aes_crypt
|
||||
*
|
||||
* \param [in] data_in Aligned input data Buffer
|
||||
* \param [in] data_out Aligned output data buffer
|
||||
* \param [in] num_128bit_blocks Size of input in 16-byte blocks
|
||||
* \param [in] mode AES Encryption/Decryption Mode
|
||||
* \return AES_OK, AES_ERR_BAD_POINTER,
|
||||
*
|
||||
* \details Program specified AES Operation using currently programmed key
|
||||
*/
|
||||
extern uint8_t
|
||||
aes_crypt(const uint32_t* data_in,
|
||||
uint32_t* data_out,
|
||||
uint32_t num_128bit_blocks, uint8_t mode);
|
||||
|
||||
|
||||
/* SHA */
|
||||
#define SHA1_BLEN (20u)
|
||||
#define SHA1_WLEN (5u)
|
||||
#define SHA2_BLEN (32u)
|
||||
#define SHA2_WLEN (8u)
|
||||
#define SHA12_BLOCK_BLEN (64u)
|
||||
#define SHA12_BLOCK_WLEN (16u)
|
||||
#define SHA3_BLEN (48u)
|
||||
#define SHA3_WLEN (12u)
|
||||
#define SHA5_BLEN (64u)
|
||||
#define SHA5_WLEN (16u)
|
||||
|
||||
/* return values */
|
||||
#define SHA_RET_OK (0) /* OK */
|
||||
#define SHA_RET_START (1) /* OK, SHA Engine started */
|
||||
#define SHA_RET_ERROR (0x80) /* b[7]==1 indicates an error */
|
||||
#define SHA_RET_ERR_BUSY (0x80)
|
||||
#define SHA_RET_ERR_BAD_ADDR (0x81)
|
||||
#define SHA_RET_ERR_TIMEOUT (0x82)
|
||||
#define SHA_RET_ERR_MAX_LEN (0x83)
|
||||
#define SHA_RET_ERR_UNSUPPORTED (0x84)
|
||||
|
||||
#define SHA_MODE_MD5 (0) // Not supported by HW
|
||||
#define SHA_MODE_1 (1)
|
||||
#define SHA_MODE_224 (2) // Not supported by HW
|
||||
#define SHA_MODE_256 (3)
|
||||
#define SHA_MODE_384 (4) // Not supported by HW
|
||||
#define SHA_MODE_512 (5) // Not supported by HW
|
||||
|
||||
#define HASH_START_IEN (1u)
|
||||
#define HASH_START_NOIEN (0u)
|
||||
|
||||
typedef union {
|
||||
uint32_t w[SHA2_WLEN];
|
||||
uint8_t b[SHA2_BLEN];
|
||||
} SHA12_DIGEST_U;
|
||||
|
||||
|
||||
/*
|
||||
* !!! SHA-1 & SHA-256
|
||||
* HW Engine requires alignment >= 4-byte boundary !!!
|
||||
*/
|
||||
typedef struct sha12_context_s SHA12_CONTEXT_T;
|
||||
struct sha12_context_s {
|
||||
SHA12_DIGEST_U hash;
|
||||
union {
|
||||
uint32_t w[(SHA12_BLOCK_WLEN) * 2];
|
||||
uint8_t b[(SHA12_BLOCK_BLEN) * 2];
|
||||
} block;
|
||||
uint8_t mode;
|
||||
uint8_t block_len;
|
||||
uint8_t rsvd[2];
|
||||
uint32_t total_msg_len;
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
* \hash_busy
|
||||
*
|
||||
* \return is busy? True if yes, Flase other wise
|
||||
*
|
||||
* \details returns the busy status of Hash Block
|
||||
*/
|
||||
extern bool hash_busy(void);
|
||||
|
||||
/**
|
||||
* \hash_start
|
||||
*
|
||||
* \param [in] ien enable/disable interrupts
|
||||
* \return None
|
||||
*
|
||||
* \details start hash block
|
||||
*/
|
||||
extern void
|
||||
hash_start(bool ien);
|
||||
|
||||
/**
|
||||
* \hash_done_status
|
||||
*
|
||||
* \param [in] hw_status Hash Status Register Value
|
||||
* \return true if done, false otherwise
|
||||
*
|
||||
* \details reflects the done status of HASH black and updates
|
||||
* status regsiter value into the input variable
|
||||
*/
|
||||
extern bool
|
||||
hash_done_status(uint32_t* hw_status);
|
||||
|
||||
/**
|
||||
* \sha12_init
|
||||
*
|
||||
* \param [in] psha12_ctx Data Structure for Input data and Output Digest
|
||||
* \param [in] mode SHA_MODE_1 or SHA_MODE_256
|
||||
* \return SHA_RET_ERR_BAD_ADDR, SHA_RET_ERR_UNSPPORTED ,SHA_RET_OK
|
||||
*
|
||||
* \details Initializes the Data structure provided
|
||||
*/
|
||||
extern uint8_t
|
||||
sha12_init(SHA12_CONTEXT_T* psha12_ctx, uint8_t mode);
|
||||
|
||||
/**
|
||||
* \sha12_update
|
||||
*
|
||||
* \param [in] psha12_ctx Data Structure for Input data and Output Digest
|
||||
* \param [in] pdata Input Data to Hash Block
|
||||
* \param [in] num_bytes Byte length of input data
|
||||
* \return SHA_RET_ERR_BAD_ADDR, SHA_RET_ERR_BUSY, SHA_RET_ERR_MAX_LEN, SHA_RET_OK
|
||||
*
|
||||
* \details Run hash block on data and if data greater than block size, put remaining bytes back into the data structure
|
||||
*/
|
||||
extern uint8_t
|
||||
sha12_update(SHA12_CONTEXT_T* psha12_ctx,
|
||||
const uint32_t* pdata, uint32_t num_bytes);
|
||||
|
||||
/**
|
||||
* \sha12_finalize
|
||||
*
|
||||
* \param [in] psha12_ctx Data Structure for Input data and Output Digest
|
||||
* \return SHA_RET_ERR_BAD_ADDR, SHA_RET_ERR_BUSY ,SHA_RET_START
|
||||
*
|
||||
* \details Apply FIPS padding to SHA256 and perform final hash calculation.
|
||||
*/
|
||||
extern uint8_t
|
||||
sha12_finalize(SHA12_CONTEXT_T* psha12_ctx);
|
||||
|
||||
/**
|
||||
* \sha256_pad_fill
|
||||
*
|
||||
* \param [in] pblock64 Aligned Memory buffer of atleast 64 bytes
|
||||
* \param [in] msg_byte_len Length of Message in bytes
|
||||
* \return None
|
||||
*
|
||||
* \details Zero and fill a 64-byte SHA256 pad block with FIP padding values
|
||||
*/
|
||||
extern void
|
||||
sha256_pad_fill(uint32_t* pblock64, uint32_t msg_byte_len);
|
||||
|
||||
|
||||
/**
|
||||
* \sha256_raw
|
||||
*
|
||||
* \param [in] pdata Input Message
|
||||
* \param [in] pdigest Pointer to biffer where digest will be written
|
||||
* \param [in] num64byte_blocks size of input data in blocks
|
||||
* \return SHA_RET_ERR_BAD_ADDR, SHA_RET_ERR_BUSY ,SHA_RET_START
|
||||
*
|
||||
* \details Calculate SHA256 on data
|
||||
*/
|
||||
extern uint8_t
|
||||
sha256_raw(uint32_t* pdata, uint32_t* pdigest, uint32_t num64byte_blocks);
|
||||
|
||||
/**
|
||||
* \sha256_raw_init
|
||||
*
|
||||
* \param [in] psha256_digest Pointer to buffer where digest will be written
|
||||
* \return None
|
||||
*
|
||||
* \details Initialize the SHA256 Digest data block
|
||||
*/
|
||||
extern void
|
||||
sha256_raw_init(uint32_t* psha256_digest);
|
||||
|
||||
/**
|
||||
* \sha256_raw_update
|
||||
*
|
||||
* \param [in] pdata Message on which HASH block is to be called
|
||||
* \param [in] pdigest Pointer to where the digest will be stored
|
||||
* \param [in] num64byte_blocks size of input data in blocks
|
||||
* \return SHA_RET_ERR_BAD_ADDR, SHA_RET_ERR_BUSY ,SHA_RET_START
|
||||
*
|
||||
* \details run Hash block on data
|
||||
*/
|
||||
extern uint8_t
|
||||
sha256_raw_update(uint32_t* pdata,
|
||||
uint32_t* pdigest, uint32_t num64byte_blocks);
|
||||
|
||||
/**
|
||||
* \hash_iclr
|
||||
*
|
||||
* \return Hash Block status
|
||||
*
|
||||
* \details Clear Hash Interrupt
|
||||
*/
|
||||
extern uint32_t
|
||||
hash_iclr(void);
|
||||
|
||||
|
||||
/**
|
||||
* \sha_init
|
||||
*
|
||||
* \param [in] mode SHA_MODE_1, SHA_MODE_256, SHA_MODE_512
|
||||
* \param [in] pdigest Address where digest will be stored
|
||||
* \return * 0 = Success
|
||||
* 1 = Hash Engine busy
|
||||
* 2 = Unsupported SHA operation
|
||||
* 3 = Bad digest pointer, NULL or mis-aligned.
|
||||
* \details Initialize Hash engine for SHA operation.
|
||||
* Programs supported SHA operation's initial value, digest address,
|
||||
* and operation
|
||||
*/
|
||||
extern uint8_t
|
||||
sha_init(uint8_t mode, uint32_t* pdigest);
|
||||
|
||||
|
||||
/**
|
||||
* \sha_update
|
||||
*
|
||||
* \param [in] pdata Input Data
|
||||
* \param [in] nblocks Size in blocks
|
||||
* \param [in] flags bit(0) - Clear Status?, bit(1) - Enable Interrupts?, bit(2) - Start?
|
||||
* \return 0 - OK, 1 - Hash Busy, 2 - bad address for data, 3 - Buffer not aligned
|
||||
*
|
||||
* \details Run Hash block on data
|
||||
*/
|
||||
extern uint8_t
|
||||
sha_update(uint32_t* pdata, uint16_t nblocks, uint8_t flags);
|
||||
|
||||
|
||||
/**
|
||||
* \sha_final
|
||||
*
|
||||
* \param [in] padbuf Buffer for padding (Twice block size)
|
||||
* \param [in] total_msg_len Message length in bytes
|
||||
* \param [in] prem Parameter_Description
|
||||
* \param [in] flags bit(0) - Clear Status?, bit(1) - Enable Interrupts?, bit(2) - Start?
|
||||
* \return 0 - OK, 1 - Hash Busy, 2 - bad address for data, 3 - Buffer not aligned
|
||||
*
|
||||
* \details Run final SHA Calculations and add padding
|
||||
*/
|
||||
extern uint8_t
|
||||
sha_final(uint32_t* padbuf, uint32_t total_msg_len,
|
||||
const uint8_t* prem, uint8_t flags);
|
||||
|
||||
|
||||
/* PKE Miscellaneous */
|
||||
|
||||
#define PKE_RET_STARTED (0)
|
||||
#define PKE_RET_OK (0)
|
||||
#define PKE_RET_ERR_BUSY (1)
|
||||
#define PKE_RET_ERR_BAD_PARAM (2)
|
||||
#define PKE_RET_ERR_BAD_ADDR (3)
|
||||
#define PKE_RET_ERR_UNKNOWN_OP (4)
|
||||
#define PKE_RET_ERR_INVALID_BIT_LENGTH (5)
|
||||
#define PKE_RET_ERR_INVALID_MSG_LENGTH (6)
|
||||
|
||||
|
||||
/**
|
||||
* \pke_power
|
||||
*
|
||||
* \param [in] pwr_on power on?
|
||||
* \return None
|
||||
*
|
||||
* \details Gate or Ungate power to PKE block
|
||||
*/
|
||||
extern void
|
||||
pke_power(bool pwr_on);
|
||||
|
||||
|
||||
/**
|
||||
* \brief pke_reset
|
||||
*
|
||||
* \return None
|
||||
*
|
||||
* \details Reset PKE Block
|
||||
*/
|
||||
extern void
|
||||
pke_reset(void);
|
||||
|
||||
/**
|
||||
* \pke_status
|
||||
*
|
||||
* \return Return PKE Status register value
|
||||
*
|
||||
* \details Details
|
||||
*/
|
||||
extern uint32_t
|
||||
pke_status(void);
|
||||
|
||||
/**
|
||||
* \pke_done_status
|
||||
*
|
||||
* \param [in] hw_status POinter where PKE Status is updated
|
||||
* \return True if done, false otherwise
|
||||
*
|
||||
* \details Returns the done status of PKE block
|
||||
*/
|
||||
extern bool
|
||||
pke_done_status(uint32_t* hw_status);
|
||||
|
||||
/**
|
||||
* \pke_start
|
||||
*
|
||||
* \param [in] ien Interrupt Enable?
|
||||
* \return None
|
||||
*
|
||||
* \details Start PKE Block
|
||||
*/
|
||||
extern void
|
||||
pke_start(bool ien);
|
||||
|
||||
|
||||
/**
|
||||
* \pke_busy
|
||||
*
|
||||
* \return Busy? True if busy, false otherwise
|
||||
*
|
||||
* \details Details
|
||||
*/
|
||||
extern bool
|
||||
pke_busy(void);
|
||||
|
||||
|
||||
/**
|
||||
* \pke_clear_scm
|
||||
*
|
||||
* \return None
|
||||
*
|
||||
* \details Clear the Shared Crypto memory
|
||||
*/
|
||||
extern void
|
||||
pke_clear_scm(void);
|
||||
|
||||
/**
|
||||
* \pke_scm_clear_slot
|
||||
*
|
||||
* \param [in] slot_num Slot number in Shared Crypto Memory
|
||||
* \return None
|
||||
*
|
||||
* \details Clear the specified slot in Shared Crypto Memory
|
||||
*/
|
||||
extern void
|
||||
pke_scm_clear_slot(uint8_t slot_num);
|
||||
|
||||
/**
|
||||
* \pke_read_scm
|
||||
*
|
||||
* \param [in] dest Pointer to where the data is to be read
|
||||
* \param [in] nbytes Number of bytes to be read
|
||||
* \param [in] slot_num Slot number from which data is to be read
|
||||
* \param [in] reverse_byte_order Reverse Byte order? True if yes, false otherwise
|
||||
* \return Number of bytes Read
|
||||
*
|
||||
* \details Read data from specified slot number in Shared Crypto memory
|
||||
*/
|
||||
extern uint16_t
|
||||
pke_read_scm(uint8_t* dest, uint16_t nbytes,
|
||||
uint8_t slot_num, bool reverse_byte_order);
|
||||
|
||||
|
||||
/**
|
||||
* \pke_write_scm
|
||||
*
|
||||
* \param [in] pdata Data to be written
|
||||
* \param [in] num_bytes Number of bytes to be written
|
||||
* \param [in] slot_num Slot number to which data ought to be written
|
||||
* \param [in] reverse_byte_order Reverse Byte order? True if yes, false otherwise
|
||||
* \return None
|
||||
*
|
||||
* \details Write data provided to specified slot in Shared Crypto Memory
|
||||
*/
|
||||
extern void
|
||||
pke_write_scm(const void* pdata, uint16_t num_bytes,
|
||||
uint8_t slot_num, uint8_t reverse_byte_order);
|
||||
|
||||
/* PKE RSA */
|
||||
|
||||
/**
|
||||
* \ rsa_load_key
|
||||
*
|
||||
* \param [in] rsa_bit_len 1024, 2048
|
||||
* \param [in] private_exponent Pointer to private exponent
|
||||
* \param [in] public_modulus Pointer to Public modulus
|
||||
* \param [in] public_exponent Pointer to Public Exponent
|
||||
* \param [in] public_exponent_byte_len Length in bytes of Public Exponent
|
||||
* \param [in] msbf Reverse Byte order? True if yes, false otherwise
|
||||
* \return PKE_RET_ERR_BUSY, PKE_RET_ERR_INVALID_BIT_LENGTH, PKE_RET_OK
|
||||
*
|
||||
* \details Load RSA keys into Crypto memory
|
||||
*/
|
||||
extern uint8_t
|
||||
rsa_load_key(uint16_t rsa_bit_len,
|
||||
const uint8_t* private_exponent,
|
||||
const uint8_t* public_modulus,
|
||||
const uint8_t* public_exponent,
|
||||
uint16_t public_exponent_byte_len,
|
||||
bool msbf);
|
||||
|
||||
|
||||
/**
|
||||
* \ rsa_encrypt
|
||||
*
|
||||
* \param [in] rsa_bit_len 1024, 2048
|
||||
* \param [in] mesg Message to be encrypted
|
||||
* \param [in] mlen length of message
|
||||
* \param [in] flags bit[0]=0(do not start), 1(start after programming), bit[4] = byte order: 0 = Least significant byte first, 1 = Most significant byte first, bit[1]=0(do not enable interrupt), 1(enable interrupt before starting)
|
||||
* \return PKE_RET_ERR_BAD_ADDR, PKE_RET_ERR_BUSY, PKE_RET_ERR_INVALID_MSG_LENGTH, PKE_RET_ERR_INVALID_BIT_LENGTH, PKE_RET_OK
|
||||
*
|
||||
* \details Encrypt provided message. Load Keys before this function is called
|
||||
*/
|
||||
extern uint8_t
|
||||
rsa_encrypt(uint16_t rsa_bit_len,
|
||||
const uint8_t* mesg,
|
||||
uint16_t mlen,
|
||||
uint8_t flags);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* \ rsa_decrypt
|
||||
*
|
||||
* \param [in] rsa_bit_len 1024, 2048
|
||||
* \param [in] encrypted_mesg Encrypted data
|
||||
* \param [in] mlen length of encrypted message
|
||||
* \param [in] flags flags bit[0]=0(do not start), 1(start after programming), bit[4] = byte order: 0 = Least significant byte first, 1 = Most significant byte first, bit[1]=0(do not enable interrupt), 1(enable interrupt before starting)
|
||||
* \return PKE_RET_ERR_BAD_ADDR, PKE_RET_ERR_BUSY, PKE_RET_ERR_INVALID_MSG_LENGTH, PKE_RET_ERR_INVALID_BIT_LENGTH, PKE_RET_OK
|
||||
*
|
||||
* \details Perform decryption on provided encrypted message. load keys before calling this function
|
||||
*/
|
||||
extern uint8_t
|
||||
rsa_decrypt(uint16_t rsa_bit_len,
|
||||
const uint8_t* encrypted_mesg,
|
||||
uint16_t mlen,
|
||||
uint8_t flags);
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* INCLUDE_CEC1302_CRYPTO_API_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,9 @@
|
||||
#ifndef _COMMON_LIB_H_
|
||||
#define _COMMON_LIB_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include "./MCHP_CEC1302.h"
|
||||
#include "./basic_timer/btimer.h"
|
||||
|
||||
#endif /* _COMMON_LIB_H_ */
|
||||
|
||||
@ -0,0 +1,409 @@
|
||||
/*****************************************************************************
|
||||
* © 2015 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
******************************************************************************
|
||||
|
||||
Version Control Information (Perforce)
|
||||
******************************************************************************
|
||||
$Revision: #1 $
|
||||
$DateTime: 2015/11/22 06:01:28 $
|
||||
$Author: amohandas $
|
||||
Last Change: Updated with unit testing feedbacks
|
||||
******************************************************************************/
|
||||
/** @file btimer.h
|
||||
* \brief Basic Timer Peripheral Header file
|
||||
* \author jvasanth
|
||||
*
|
||||
* This file is the header file for Basic Timer Peripheral
|
||||
******************************************************************************/
|
||||
|
||||
/** @defgroup Basic_Timer
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _BTIMER_H
|
||||
#define _BTIMER_H
|
||||
|
||||
/******************************************************************************/
|
||||
/** Logical Timer ID for APIs.
|
||||
* This is the timer IDs passed to Basic Timer API function calls
|
||||
*******************************************************************************/
|
||||
enum _PID_BTIMER_
|
||||
{
|
||||
PID_BTIMER_0,
|
||||
PID_BTIMER_1,
|
||||
PID_BTIMER_2,
|
||||
PID_BTIMER_3,
|
||||
PID_BTIMER_4,
|
||||
PID_BTIMER_5,
|
||||
PID_BTIMER_MAX
|
||||
};
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* Logical flags for Timer Control */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
//This is for tmr_cntl parameter in btimer_init function
|
||||
#define BTIMER_AUTO_RESTART (0x08u)
|
||||
#define BTIMER_ONE_SHOT (0u)
|
||||
#define BTIMER_COUNT_UP (0x04u)
|
||||
#define BTIMER_COUNT_DOWN (0u)
|
||||
#define BTIMER_INT_EN (0x01u)
|
||||
#define BTIMER_NO_INT (0u)
|
||||
/* ---------------------------------------------------------------------- */
|
||||
|
||||
|
||||
//Timer Block Hardware Bits and Masks
|
||||
#define BTIMER_CNTL_HALT (0x80UL)
|
||||
#define BTIMER_CNTL_RELOAD (0x40UL)
|
||||
#define BTIMER_CNTL_START (0x20UL)
|
||||
#define BTIMER_CNTL_SOFT_RESET (0x10UL)
|
||||
#define BTIMER_CNTL_AUTO_RESTART (0x08UL)
|
||||
#define BTIMER_CNTL_COUNT_UP (0x04UL)
|
||||
#define BTIMER_CNTL_ENABLE (0x01UL)
|
||||
|
||||
#define BTIMER_CNTL_HALT_BIT (7U)
|
||||
#define BTIMER_CNTL_RELOAD_BIT (6U)
|
||||
#define BTIMER_CNTL_START_BIT (5U)
|
||||
#define BTIMER_CNTRL_SOFT_RESET_BIT (4U)
|
||||
#define BTIMER_CNTL_AUTO_RESTART_BIT (3U)
|
||||
#define BTIMER_CNTL_COUNT_DIR_BIT (2U)
|
||||
#define BTIMER_CNTL_ENABLE_BIT (0U)
|
||||
|
||||
#define BTIMER_GIRQ MEC_GIRQ23_ID
|
||||
#define BTIMER_MAX_INSTANCE PID_BTIMER_MAX
|
||||
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* API - Basic Timer Intitialization function */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
|
||||
/** Initialize specified timer
|
||||
* @param btimer_id Basic Timer ID
|
||||
* @param tmr_cntl Logical flags for Timer Control
|
||||
* @param initial_count Initial Count
|
||||
* @param preload_count Preload Count
|
||||
* @note Performs a soft reset of the timer before configuration
|
||||
*/
|
||||
void btimer_init(uint8_t btimer_id,
|
||||
uint16_t tmr_cntl,
|
||||
uint16_t prescaler,
|
||||
uint32_t initial_count,
|
||||
uint32_t preload_count);
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* API - Functions to program and read the Basic Timer Counter */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/** Program timer's counter register.
|
||||
* @param btimer_id Basic Timer ID
|
||||
* @param count new counter value
|
||||
* @note Timer hardware may implement a 16-bit or 32-bit
|
||||
* hardware counter. If the timer is 16-bit only the lower
|
||||
* 16-bits of the count paramter are used.
|
||||
*/
|
||||
void btimer_count_set(uint8_t btimer_id, uint32_t count);
|
||||
|
||||
/** Return current value of timer's count register.
|
||||
* @param btimer_id Basic Timer ID.
|
||||
* @return uint32_t timer count may be 32 or 16 bits depending
|
||||
* upon the hardware. Timers 0-3 are 16-bit
|
||||
* and Timers 4-5 are 32-bit.
|
||||
*/
|
||||
uint32_t btimer_count_get(uint8_t btimer_id);
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* API - Function to reload counter from Preload Register */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/** Force timer to reload counter from preload
|
||||
* register.
|
||||
* @param btimer_id Basic Timer ID.
|
||||
* @note Hardware will only reload counter if timer is running.
|
||||
*/
|
||||
void btimer_reload(uint8_t btimer_id);
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* API - Functions for stopping and starting the basic Timer */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/** Start timer counting.
|
||||
* @param btimer_id Basic Timer ID.
|
||||
*/
|
||||
void btimer_start(uint8_t btimer_id);
|
||||
|
||||
/** Stop timer.
|
||||
* @param btimer_id Basic Timer ID.
|
||||
* @note When a stopped timer is started again it will reload
|
||||
* the count register from preload value.
|
||||
*/
|
||||
void btimer_stop(uint8_t btimer_id);
|
||||
|
||||
/** Return state of timer's START bit.
|
||||
* @param btimer_id Basic Timer ID.
|
||||
* @return uint8_t 0(timer not started), 1 (timer started)
|
||||
*/
|
||||
uint8_t btimer_is_started(uint8_t btimer_id);
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* API - Function to perform basic timer soft reset */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/** Peform soft reset of specified timer.
|
||||
* @param btimer_id Basic Timer ID
|
||||
* @note Soft reset set all registers to POR values.
|
||||
* Spins 256 times waiting on hardware to clear reset bit.
|
||||
*/
|
||||
void btimer_reset(uint8_t btimer_id);
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* API - Functions to halt/unhalt the timer counting */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/** Halt timer counting with no reload on unhalt.
|
||||
* @param btimer_id Basic Timer ID.
|
||||
* @note A halted timer will not reload the count register when
|
||||
* unhalted, it will continue counting from the current
|
||||
* count value.
|
||||
*/
|
||||
void btimer_halt(uint8_t btimer_id);
|
||||
|
||||
/** Unhalt timer counting.
|
||||
* @param btimer_id Basic Timer ID.
|
||||
*/
|
||||
void btimer_unhalt(uint8_t btimer_id);
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* API - Functions for Basic Timer interrupt */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/** Enable specified timer's interrupt from the block.
|
||||
* @param btimer_id Basic Timer ID.
|
||||
* @param ien Non-zero enable interrupt in timer block, 0
|
||||
* disable.
|
||||
*/
|
||||
void btimer_interrupt_enable(uint8_t btimer_id, uint8_t ien);
|
||||
|
||||
/** Read Timer interrupt status and clear if set
|
||||
* @param btimer_id Basic Timer ID.
|
||||
* @return uint8_t 1 (Timer interrupt status set) else 0.
|
||||
* @note If timer interrupt status is set then clear it before
|
||||
* returning.
|
||||
*/
|
||||
uint8_t btimer_interrupt_status_get_clr(uint8_t btimer_id);
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* API - Functions for Basic Timer GIRQ */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/** Enables GIRQ enable bit for the timer
|
||||
* @param btimer_id Basic Timer ID.
|
||||
*/
|
||||
void btimer_girq_enable_set(uint8_t btimer_id);
|
||||
|
||||
/** Clears GIRQ enable bit for the timer
|
||||
* @param btimer_id Basic Timer ID.
|
||||
*/
|
||||
void btimer_girq_enable_clr(uint8_t btimer_id);
|
||||
|
||||
/** Returns GIRQ source bit for the timer
|
||||
* @param btimer_id Basic Timer ID.
|
||||
* @return uint8_t 0(src bit not set), Non-zero (src bit set)
|
||||
*/
|
||||
uint8_t btimer_girq_src_get(uint8_t btimer_id);
|
||||
|
||||
/** Clears GIRQ source bit for the timer
|
||||
* @param btimer_id Basic Timer ID.
|
||||
*/
|
||||
void btimer_girq_src_clr(uint8_t btimer_id);
|
||||
|
||||
/** Returns GIRQ result bit for the timer
|
||||
* @param btimer_id Basic Timer ID.
|
||||
* @return uint8_t 0(result bit not set), Non-zero (result bit set)
|
||||
*/
|
||||
uint8_t btimer_girq_result_get(uint8_t btimer_id);
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* API - Functions for Basic Timer Sleep */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/** Enable/Disable clock gating on idle of a timer
|
||||
* @param btimer_id Basic Timer ID.
|
||||
* @param sleep_en 1 = Sleep enable, 0 = Sleep disable
|
||||
*/
|
||||
void btimer_sleep(uint8_t btimer_id, uint8_t sleep_en);
|
||||
|
||||
/** Returns clk required status for the timer block
|
||||
* @param btimer_id Basic Timer ID.
|
||||
* @return Non-zero if clk required, else 0
|
||||
*/
|
||||
uint32_t btimer_clk_reqd_sts_get(uint8_t btimer_id);
|
||||
|
||||
/** Enable/Disable reset on sleep for the timer block
|
||||
* @param btimer_id Basic Timer ID.
|
||||
* @param reset_en 1 to enable, 0 to disable
|
||||
*/
|
||||
void btimer_reset_on_sleep(uint8_t btimer_id, uint8_t reset_en);
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* Peripheral Function - Functions to set and read Timer Counter Register */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/** Sets timer counter
|
||||
* @param btimer_id Basic Timer ID
|
||||
* @param count - 32-bit counter
|
||||
*/
|
||||
void p_btimer_count_set(uint8_t btimer_id, uint32_t count);
|
||||
|
||||
/** Read the timer counter
|
||||
* @param btimer_id Basic Timer ID
|
||||
* @return count - 32-bit counter
|
||||
*/
|
||||
uint32_t p_btimer_count_get(uint8_t btimer_id);
|
||||
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* Peripheral Function - Function to program the Preload */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/** Sets preload for the counter
|
||||
* @param btimer_id Basic Timer ID
|
||||
* @param preload_count - 32-bit pre-load value
|
||||
*/
|
||||
void p_btimer_preload_set(uint8_t btimer_id, uint32_t preload_count);
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* Peripheral Functions - Functions for basic timer interrupts */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/** Reads the interrupt status bit in the timer block
|
||||
* @param btimer_id Basic Timer ID
|
||||
* @return status - 1 if interrupt status set, else 0
|
||||
*/
|
||||
uint8_t p_btimer_int_status_get(uint8_t btimer_id);
|
||||
|
||||
/** Clears interrupt status bit in the timer block
|
||||
* @param btimer_id Basic Timer ID
|
||||
*/
|
||||
void p_btimer_int_status_clr(uint8_t btimer_id);
|
||||
|
||||
/** Sets interrupt enable bit in the timer block
|
||||
* @param btimer_id Basic Timer ID
|
||||
*/
|
||||
void p_btimer_int_enable_set(uint8_t btimer_id);
|
||||
|
||||
/** Clears interrupt enable bit for the timer block
|
||||
* @param btimer_id Basic Timer ID
|
||||
*/
|
||||
void p_btimer_int_enable_clr(uint8_t btimer_id);
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* Peripheral Functions - Functions for Control Register */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/** Writes the control register 32-bits
|
||||
* @param btimer_id Basic Timer ID
|
||||
* @param value - 32-bit value to program
|
||||
*/
|
||||
void p_btimer_ctrl_write(uint8_t btimer_id, uint32_t value);
|
||||
|
||||
/** Reads the control register
|
||||
* @param btimer_id Basic Timer ID
|
||||
* @return uint32_t - 32-bit value
|
||||
*/
|
||||
uint32_t p_btimer_ctrl_read(uint8_t btimer_id);
|
||||
|
||||
/** Clears enable bit in the control register
|
||||
* @param btimer_id Basic Timer ID
|
||||
*/
|
||||
void p_btimer_ctrl_enable_set(uint8_t btimer_id);
|
||||
|
||||
/** Clears enable bit in the control register
|
||||
* @param btimer_id Basic Timer ID
|
||||
*/
|
||||
void p_btimer_ctrl_enable_clr(uint8_t btimer_id);
|
||||
|
||||
/** Sets counter direction bit in the control register
|
||||
* @param btimer_id Basic Timer ID
|
||||
*/
|
||||
void p_btimer_ctrl_counter_dir_set(uint8_t btimer_id);
|
||||
|
||||
/** Clears counter direction bit in the control register
|
||||
* @param btimer_id Basic Timer ID
|
||||
*/
|
||||
void p_btimer_ctrl_counter_dir_clr(uint8_t btimer_id);
|
||||
|
||||
/** Sets auto restart bit in the control register
|
||||
* @param btimer_id Basic Timer ID
|
||||
*/
|
||||
void p_btimer_ctrl_auto_restart_set(uint8_t btimer_id);
|
||||
|
||||
/** Clears auto resetart bit in the control register
|
||||
* @param btimer_id Basic Timer ID
|
||||
*/
|
||||
void p_btimer_ctrl_auto_restart_clr(uint8_t btimer_id);
|
||||
|
||||
/** Sets soft reset bit in the control register
|
||||
* @param btimer_id Basic Timer ID
|
||||
*/
|
||||
void p_btimer_ctrl_soft_reset_set(uint8_t btimer_id);
|
||||
|
||||
/** Read Soft Reset bit
|
||||
* @param btimer_id Basic Timer ID
|
||||
* @return 0 if soft reset status bit cleared; else non-zero value
|
||||
*/
|
||||
uint8_t p_btimer_ctrl_soft_reset_sts_get(uint8_t btimer_id);
|
||||
|
||||
/** Sets start bit in the control register
|
||||
* @param btimer_id Basic Timer ID
|
||||
*/
|
||||
void p_btimer_ctrl_start_set(uint8_t btimer_id);
|
||||
|
||||
/** Read start bit in the control register
|
||||
* @param btimer_id Basic Timer ID
|
||||
* @return 0 if start bit not set; else non-zero value
|
||||
*/
|
||||
uint8_t p_btimer_ctrl_start_get(uint8_t btimer_id);
|
||||
|
||||
/** Clears start bit in the control register
|
||||
* @param btimer_id Basic Timer ID
|
||||
*/
|
||||
void p_btimer_ctrl_start_clr(uint8_t btimer_id);
|
||||
|
||||
/** Sets reload bit in the control register
|
||||
* @param btimer_id Basic Timer ID
|
||||
*/
|
||||
void p_btimer_ctrl_reload_set(uint8_t btimer_id);
|
||||
|
||||
/** Clears reload bit in the control register
|
||||
* @param btimer_id Basic Timer ID
|
||||
*/
|
||||
void p_btimer_ctrl_reload_clr(uint8_t btimer_id);
|
||||
|
||||
/** Sets halt bit in the control register
|
||||
* @param btimer_id Basic Timer ID
|
||||
*/
|
||||
void p_btimer_ctrl_halt_set(uint8_t btimer_id);
|
||||
|
||||
/** Clears halt bit in the control register
|
||||
* @param btimer_id Basic Timer ID
|
||||
*/
|
||||
|
||||
void p_btimer_ctrl_halt_clr(uint8_t btimer_id);
|
||||
|
||||
/** Sets prescale value
|
||||
* @param btimer_id Basic Timer ID
|
||||
* @param prescaler - 16-bit pre-scale value
|
||||
*/
|
||||
void p_btimer_ctrl_prescale_set(uint8_t btimer_id, uint16_t prescaler);
|
||||
|
||||
|
||||
#endif // #ifndef _BTIMER_H
|
||||
|
||||
/* end btimer_perphl.c */
|
||||
|
||||
/** @} //Peripherals Basic_Timer
|
||||
*/
|
||||
|
||||
@ -0,0 +1,474 @@
|
||||
/*****************************************************************************
|
||||
* © 2015 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
******************************************************************************
|
||||
|
||||
Version Control Information (Perforce)
|
||||
******************************************************************************
|
||||
$Revision: #2 $
|
||||
$DateTime: 2015/11/24 06:27:00 $
|
||||
$Author: amohandas $
|
||||
Last Change: Updated for tabs
|
||||
******************************************************************************/
|
||||
/** @file btimer_api.c
|
||||
* \brief Basic Timer APIs Source file
|
||||
* \author jvasanth
|
||||
*
|
||||
* This file implements the Basic Timer API functions
|
||||
******************************************************************************/
|
||||
|
||||
/** @defgroup Basic_Timer
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "common_lib.h"
|
||||
#include "btimer.h"
|
||||
#include "..\pcr\pcr.h"
|
||||
//#include "..\interrupt\ecia.h"
|
||||
|
||||
/** Basic Timer Sleep Registers & Bit Positions */
|
||||
static const uint32_t btmr_pcr_id[BTIMER_MAX_INSTANCE] = {
|
||||
PCR_BTIMER0,
|
||||
PCR_BTIMER1,
|
||||
PCR_BTIMER2,
|
||||
PCR_BTIMER3,
|
||||
PCR_BTIMER4,
|
||||
PCR_BTIMER5
|
||||
};
|
||||
|
||||
#ifdef PLIB_BTIMER_CHECK_ID
|
||||
|
||||
/** Local helper that checks if logical Timer ID is valid.
|
||||
* @param btimer_id Basic Timer ID
|
||||
* @return uint8_t Non-zero(VALID), 0(Invalid)
|
||||
*/
|
||||
static uint8_t btmr_valid(uint8_t btimer_id)
|
||||
{
|
||||
if ( btimer_id < (PID_BTIMER_MAX ) ) {
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
|
||||
/** This version of tmr_valid skips checking always returning 1.
|
||||
* Compiler may optimize it out.
|
||||
* @param btimer_id Basic Timer ID
|
||||
* @return uint8_t 1(VALID)
|
||||
*/
|
||||
static uint8_t btmr_valid(uint8_t btimer_id) { return 1; }
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* Basic Timer Intitialization function */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
|
||||
/** Initialize specified timer
|
||||
* @param btimer_id Basic Timer ID
|
||||
* @param tmr_cntl Logical flags for Timer Control
|
||||
* @param initial_count Initial Count
|
||||
* @param preload_count Preload Count
|
||||
* @note Performs a soft reset of the timer before configuration
|
||||
*/
|
||||
void btimer_init(uint8_t btimer_id,
|
||||
uint16_t tmr_cntl,
|
||||
uint16_t prescaler,
|
||||
uint32_t initial_count,
|
||||
uint32_t preload_count)
|
||||
{
|
||||
uint32_t value;
|
||||
|
||||
if (btmr_valid(btimer_id)) {
|
||||
|
||||
btimer_reset(btimer_id);
|
||||
|
||||
// Ungate timer clocks and program prescale
|
||||
value = ((uint32_t)prescaler << 16) + (BTIMER_CNTL_ENABLE);
|
||||
p_btimer_ctrl_write(btimer_id, value);
|
||||
|
||||
// Program Preload & initial counter value
|
||||
p_btimer_preload_set(btimer_id, preload_count);
|
||||
p_btimer_count_set(btimer_id, initial_count);
|
||||
|
||||
// Program control register, interrupt enable, and clear status
|
||||
if (tmr_cntl & BTIMER_COUNT_UP) {
|
||||
p_btimer_ctrl_counter_dir_set(btimer_id);
|
||||
}
|
||||
if (tmr_cntl & BTIMER_AUTO_RESTART) {
|
||||
p_btimer_ctrl_auto_restart_set(btimer_id);
|
||||
}
|
||||
if (tmr_cntl & BTIMER_INT_EN) {
|
||||
p_btimer_int_enable_set(btimer_id); // enable first
|
||||
p_btimer_int_status_clr(btimer_id); // clear status
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* Functions to program and read the Basic Timer Counter */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
|
||||
/** Program timer's counter register.
|
||||
* @param btimer_id Basic Timer ID
|
||||
* @param count new counter value
|
||||
* @note Timer hardware may implement a 16-bit or 32-bit
|
||||
* hardware counter. If the timer is 16-bit only the lower
|
||||
* 16-bits of the count paramter are used.
|
||||
*/
|
||||
void btimer_count_set(uint8_t btimer_id, uint32_t count)
|
||||
{
|
||||
if ( btmr_valid(btimer_id) ) {
|
||||
|
||||
p_btimer_count_set(btimer_id, count);
|
||||
}
|
||||
}
|
||||
|
||||
/** Return current value of timer's count register.
|
||||
* @param btimer_id Basic Timer ID.
|
||||
* @return uint32_t timer count may be 32 or 16 bits depending
|
||||
* upon the hardware. Timers 0-3 are 16-bit
|
||||
* and Timers 4-5 are 32-bit.
|
||||
*/
|
||||
uint32_t btimer_count_get(uint8_t btimer_id)
|
||||
{
|
||||
uint32_t cnt;
|
||||
|
||||
cnt = 0ul;
|
||||
if ( btmr_valid(btimer_id) ) {
|
||||
|
||||
cnt = p_btimer_count_get(btimer_id);
|
||||
}
|
||||
|
||||
return cnt;
|
||||
}
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* Function to reload counter from Preload Register */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
|
||||
/** Force timer to reload counter from preload
|
||||
* register.
|
||||
* @param btimer_id Basic Timer ID.
|
||||
* @note Hardware will only reload counter if timer is running.
|
||||
*/
|
||||
void btimer_reload(uint8_t btimer_id)
|
||||
{
|
||||
if ( btmr_valid(btimer_id) ) {
|
||||
|
||||
if (p_btimer_ctrl_start_get(btimer_id)) //Check if timer is running
|
||||
{
|
||||
p_btimer_ctrl_reload_set(btimer_id);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* Functions for stopping and starting the basic Timer */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
|
||||
/** Start timer counting.
|
||||
* @param btimer_id Basic Timer ID.
|
||||
*/
|
||||
void btimer_start(uint8_t btimer_id)
|
||||
{
|
||||
if ( btmr_valid(btimer_id) ) {
|
||||
|
||||
p_btimer_ctrl_start_set(btimer_id);
|
||||
}
|
||||
}
|
||||
|
||||
/** Stop timer.
|
||||
* @param btimer_id Basic Timer ID.
|
||||
* @note When a stopped timer is started again it will reload
|
||||
* the count register from preload value.
|
||||
*/
|
||||
void btimer_stop(uint8_t btimer_id)
|
||||
{
|
||||
if ( btmr_valid(btimer_id) ) {
|
||||
|
||||
p_btimer_ctrl_start_clr(btimer_id);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
/** Return state of timer's START bit.
|
||||
* @param btimer_id Basic Timer ID.
|
||||
* @return uint8_t 0(timer not started), 1 (timer started)
|
||||
*/
|
||||
uint8_t btimer_is_started(uint8_t btimer_id)
|
||||
{
|
||||
uint8_t sts;
|
||||
|
||||
sts = 0;
|
||||
if ( btmr_valid(btimer_id) ) {
|
||||
|
||||
if (p_btimer_ctrl_start_get(btimer_id))
|
||||
{
|
||||
sts = 1;
|
||||
}
|
||||
}
|
||||
return sts;
|
||||
}
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* Function to perform basic timer soft reset */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
|
||||
/** Peform soft reset of specified timer.
|
||||
* @param btimer_id Basic Timer ID
|
||||
* @note Soft reset set all registers to POR values.
|
||||
* Spins 256 times waiting on hardware to clear reset bit.
|
||||
*/
|
||||
void btimer_reset(uint8_t btimer_id)
|
||||
{
|
||||
uint32_t wait_cnt;
|
||||
uint8_t soft_reset_sts;
|
||||
|
||||
if (btmr_valid(btimer_id)) {
|
||||
|
||||
p_btimer_ctrl_soft_reset_set(btimer_id);
|
||||
|
||||
wait_cnt = 256ul;
|
||||
do {
|
||||
soft_reset_sts = p_btimer_ctrl_soft_reset_sts_get(btimer_id);
|
||||
|
||||
if (0 == soft_reset_sts){
|
||||
break;
|
||||
}
|
||||
}
|
||||
while ( wait_cnt-- );
|
||||
}
|
||||
}
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* Functions to halt/unhalt the timer counting */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
|
||||
/** Halt timer counting with no reload on unhalt.
|
||||
* @param btimer_id Basic Timer ID.
|
||||
* @note A halted timer will not reload the count register when
|
||||
* unhalted, it will continue counting from the current
|
||||
* count value.
|
||||
*/
|
||||
void btimer_halt(uint8_t btimer_id)
|
||||
{
|
||||
if ( btmr_valid(btimer_id) ) {
|
||||
|
||||
p_btimer_ctrl_halt_set(btimer_id);
|
||||
}
|
||||
}
|
||||
|
||||
/** Unhalt timer counting.
|
||||
* @param btimer_id Basic Timer ID.
|
||||
*/
|
||||
void btimer_unhalt(uint8_t btimer_id)
|
||||
{
|
||||
if ( btmr_valid(btimer_id) ) {
|
||||
|
||||
p_btimer_ctrl_halt_clr(btimer_id);
|
||||
}
|
||||
}
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* Functions for Basic Timer interrupt */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
|
||||
/** Enable specified timer's interrupt from the block.
|
||||
* @param btimer_id Basic Timer ID.
|
||||
* @param ien Non-zero enable interrupt in timer block, 0
|
||||
* disable.
|
||||
*/
|
||||
void btimer_interrupt_enable(uint8_t btimer_id, uint8_t ien)
|
||||
{
|
||||
if (btmr_valid(btimer_id)) {
|
||||
|
||||
p_btimer_int_enable_set(btimer_id);
|
||||
|
||||
if (ien) {
|
||||
p_btimer_int_enable_set(btimer_id);
|
||||
} else {
|
||||
p_btimer_int_enable_clr(btimer_id);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/** Read Timer interrupt status and clear if set
|
||||
* @param btimer_id Basic Timer ID.
|
||||
* @return uint8_t 1 (Timer interrupt status set) else 0.
|
||||
* @note If timer interrupt status is set then clear it before
|
||||
* returning.
|
||||
*/
|
||||
uint8_t btimer_interrupt_status_get_clr(uint8_t btimer_id)
|
||||
{
|
||||
uint8_t sts;
|
||||
|
||||
sts = 0;
|
||||
if (btmr_valid(btimer_id)) {
|
||||
|
||||
sts = p_btimer_int_status_get(btimer_id);
|
||||
if (sts) {
|
||||
p_btimer_int_status_clr(btimer_id);
|
||||
}
|
||||
}
|
||||
return sts;
|
||||
}
|
||||
|
||||
#if 0 //Temporary disable until interrupt module
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* Functions for Basic Timer GIRQ */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
|
||||
/** Enables GIRQ enable bit for the timer
|
||||
* @param btimer_id Basic Timer ID.
|
||||
*/
|
||||
void btimer_girq_enable_set(uint8_t btimer_id)
|
||||
{
|
||||
if (btmr_valid(btimer_id))
|
||||
{
|
||||
//Note: Bit Position is same as Timer ID
|
||||
p_ecia_girq_enable_set(BTIMER_GIRQ, btimer_id);
|
||||
}
|
||||
}
|
||||
|
||||
/** Clears GIRQ enable bit for the timer
|
||||
* @param btimer_id Basic Timer ID.
|
||||
*/
|
||||
void btimer_girq_enable_clr(uint8_t btimer_id)
|
||||
{
|
||||
if (btmr_valid(btimer_id))
|
||||
{
|
||||
//Note: Bit Position is same as Timer ID
|
||||
p_ecia_girq_enable_clr(BTIMER_GIRQ, btimer_id);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/** Returns GIRQ source bit for the timer
|
||||
* @param btimer_id Basic Timer ID.
|
||||
* @return uint8_t 0(src bit not set), Non-zero (src bit set)
|
||||
*/
|
||||
uint8_t btimer_girq_src_get(uint8_t btimer_id)
|
||||
{
|
||||
uint8_t retVal;
|
||||
|
||||
retVal = 0;
|
||||
if (btmr_valid(btimer_id))
|
||||
{
|
||||
//Note: Bit Position is same as Timer ID
|
||||
retVal = p_ecia_girq_source_get(BTIMER_GIRQ, btimer_id);
|
||||
}
|
||||
|
||||
return retVal;
|
||||
}
|
||||
|
||||
/** Clears GIRQ source bit for the timer
|
||||
* @param btimer_id Basic Timer ID.
|
||||
*/
|
||||
void btimer_girq_src_clr(uint8_t btimer_id)
|
||||
{
|
||||
if (btmr_valid(btimer_id))
|
||||
{
|
||||
//Note: Bit Position is same as Timer ID
|
||||
p_ecia_girq_source_clr(BTIMER_GIRQ, btimer_id);
|
||||
}
|
||||
}
|
||||
|
||||
/** Returns GIRQ result bit for the timer
|
||||
* @param btimer_id Basic Timer ID.
|
||||
* @return uint8_t 0(result bit not set), Non-zero (result bit set)
|
||||
*/
|
||||
uint8_t btimer_girq_result_get(uint8_t btimer_id)
|
||||
{
|
||||
uint8_t retVal;
|
||||
|
||||
retVal = 0;
|
||||
if (btmr_valid(btimer_id))
|
||||
{
|
||||
//Note: Bit Position is same as Timer ID
|
||||
retVal = p_ecia_girq_result_get(BTIMER_GIRQ, btimer_id);
|
||||
}
|
||||
|
||||
return retVal;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* Functions for Basic Timer Sleep */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
|
||||
/** Enable/Disable clock gating on idle of a timer
|
||||
* @param btimer_id Basic Timer ID.
|
||||
* @param sleep_en 1 = Sleep enable, 0 = Sleep disable
|
||||
*/
|
||||
void btimer_sleep(uint8_t btimer_id, uint8_t sleep_en)
|
||||
{
|
||||
uint32_t pcr_blk_id;
|
||||
|
||||
if ( btmr_valid(btimer_id) )
|
||||
{
|
||||
pcr_blk_id = btmr_pcr_id[btimer_id];
|
||||
|
||||
pcr_sleep_enable(pcr_blk_id, sleep_en);
|
||||
}
|
||||
}
|
||||
|
||||
/** Returns clk required status for the timer block
|
||||
* @param btimer_id Basic Timer ID.
|
||||
* @return Non-zero if clk required, else 0
|
||||
*/
|
||||
uint32_t btimer_clk_reqd_sts_get(uint8_t btimer_id)
|
||||
{
|
||||
uint32_t retVal;
|
||||
uint32_t pcr_blk_id;
|
||||
|
||||
retVal = 0ul;
|
||||
if ( btmr_valid(btimer_id) )
|
||||
{
|
||||
pcr_blk_id = btmr_pcr_id[btimer_id];
|
||||
|
||||
retVal = pcr_clock_reqd_status_get(pcr_blk_id);
|
||||
}
|
||||
|
||||
return retVal;
|
||||
}
|
||||
|
||||
/** Enable/Disable reset on sleep for the timer block
|
||||
* @param btimer_id Basic Timer ID.
|
||||
* @param reset_en 1 to enable, 0 to disable
|
||||
*/
|
||||
void btimer_reset_on_sleep(uint8_t btimer_id, uint8_t reset_en)
|
||||
{
|
||||
uint32_t pcr_blk_id;
|
||||
|
||||
if ( btmr_valid(btimer_id) )
|
||||
{
|
||||
pcr_blk_id = btmr_pcr_id[btimer_id];
|
||||
|
||||
pcr_reset_enable(pcr_blk_id, reset_en);
|
||||
}
|
||||
}
|
||||
|
||||
/* end btimer_api.c */
|
||||
|
||||
/** @} //Peripheral Basic_Timer
|
||||
*/
|
||||
@ -0,0 +1,287 @@
|
||||
/*****************************************************************************
|
||||
* © 2015 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
******************************************************************************
|
||||
|
||||
Version Control Information (Perforce)
|
||||
******************************************************************************
|
||||
$Revision: #2 $
|
||||
$DateTime: 2015/11/24 06:27:00 $
|
||||
$Author: amohandas $
|
||||
Last Change: Updated for tabs
|
||||
******************************************************************************/
|
||||
/** @file btimer_perphl.c
|
||||
* \brief Basic Timer Peripheral Source file
|
||||
* \author jvasanth
|
||||
*
|
||||
* This file implements the Basic Timer Peripheral functions
|
||||
******************************************************************************/
|
||||
|
||||
/** @defgroup Basic_Timer
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "common_lib.h"
|
||||
#include "btimer.h"
|
||||
|
||||
/** Basic Timer Instance base addresses */
|
||||
static TIMER_16_0_Type * const btmr_inst[BTIMER_MAX_INSTANCE] = {
|
||||
CEC1302_TIMER_16_0,
|
||||
CEC1302_TIMER_16_1,
|
||||
CEC1302_TIMER_16_2,
|
||||
CEC1302_TIMER_16_3,
|
||||
CEC1302_TIMER_32_0,
|
||||
CEC1302_TIMER_32_1
|
||||
};
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* Functions to set and read Timer Counter Register */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
|
||||
/** Sets timer counter
|
||||
* @param btimer_id Basic Timer ID
|
||||
* @param count - 32-bit counter
|
||||
*/
|
||||
void p_btimer_count_set(uint8_t btimer_id, uint32_t count)
|
||||
{
|
||||
btmr_inst[btimer_id]->COUNT = count;
|
||||
}
|
||||
|
||||
/** Read the timer counter
|
||||
* @param btimer_id Basic Timer ID
|
||||
* @return count - 32-bit counter
|
||||
*/
|
||||
uint32_t p_btimer_count_get(uint8_t btimer_id)
|
||||
{
|
||||
return btmr_inst[btimer_id]->COUNT;
|
||||
}
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* Function to program the Preload */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
|
||||
/** Sets preload for the counter
|
||||
* @param btimer_id Basic Timer ID
|
||||
* @param preload_count - 32-bit pre-load value
|
||||
*/
|
||||
void p_btimer_preload_set(uint8_t btimer_id, uint32_t preload_count)
|
||||
{
|
||||
btmr_inst[btimer_id]->PRE_LOAD = preload_count;
|
||||
}
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* Functions for basic timer interrupts */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
|
||||
/** Reads the interrupt status bit in the timer block
|
||||
* @param btimer_id Basic Timer ID
|
||||
* @return status - 1 if interrupt status set, else 0
|
||||
*/
|
||||
uint8_t p_btimer_int_status_get(uint8_t btimer_id)
|
||||
{
|
||||
return (uint8_t)(btmr_inst[btimer_id]->INTERRUPT_STATUS);
|
||||
}
|
||||
|
||||
/** Clears interrupt status bit in the timer block
|
||||
* @param btimer_id Basic Timer ID
|
||||
*/
|
||||
void p_btimer_int_status_clr(uint8_t btimer_id)
|
||||
{
|
||||
// Write 1 to clear
|
||||
btmr_inst[btimer_id]->INTERRUPT_STATUS = 1;
|
||||
}
|
||||
|
||||
/** Sets interrupt enable bit in the timer block
|
||||
* @param btimer_id Basic Timer ID
|
||||
*/
|
||||
void p_btimer_int_enable_set(uint8_t btimer_id)
|
||||
{
|
||||
btmr_inst[btimer_id]->INTERRUPT_ENABLE = 1;
|
||||
}
|
||||
|
||||
/** Clears interrupt enable bit for the timer block
|
||||
* @param btimer_id Basic Timer ID
|
||||
*/
|
||||
void p_btimer_int_enable_clr(uint8_t btimer_id)
|
||||
{
|
||||
btmr_inst[btimer_id]->INTERRUPT_ENABLE = 0;
|
||||
}
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* Functions for Control Register */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
|
||||
/** Writes the control register 32-bits
|
||||
* @param btimer_id Basic Timer ID
|
||||
* @param value - 32-bit value to program
|
||||
*/
|
||||
void p_btimer_ctrl_write(uint8_t btimer_id, uint32_t value)
|
||||
{
|
||||
btmr_inst[btimer_id]->CONTROL.w = value;
|
||||
}
|
||||
|
||||
/** Reads the control register
|
||||
* @param btimer_id Basic Timer ID
|
||||
* @return uint32_t - 32-bit value
|
||||
*/
|
||||
uint32_t p_btimer_ctrl_read(uint8_t btimer_id)
|
||||
{
|
||||
uint32_t retVal;
|
||||
|
||||
retVal = btmr_inst[btimer_id]->CONTROL.w;
|
||||
|
||||
return retVal;
|
||||
}
|
||||
|
||||
/** Sets enable bit in the control register
|
||||
* @param btimer_id Basic Timer ID
|
||||
*/
|
||||
void p_btimer_ctrl_enable_set(uint8_t btimer_id)
|
||||
{
|
||||
btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_ENABLE;
|
||||
}
|
||||
|
||||
/** Clears enable bit in the control register
|
||||
* @param btimer_id Basic Timer ID
|
||||
*/
|
||||
void p_btimer_ctrl_enable_clr(uint8_t btimer_id)
|
||||
{
|
||||
btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_ENABLE;
|
||||
}
|
||||
|
||||
/** Sets counter direction bit in the control register
|
||||
* @param btimer_id Basic Timer ID
|
||||
*/
|
||||
void p_btimer_ctrl_counter_dir_set(uint8_t btimer_id)
|
||||
{
|
||||
btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_COUNT_UP;
|
||||
}
|
||||
|
||||
/** Clears counter direction bit in the control register
|
||||
* @param btimer_id Basic Timer ID
|
||||
*/
|
||||
void p_btimer_ctrl_counter_dir_clr(uint8_t btimer_id)
|
||||
{
|
||||
btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_COUNT_UP;
|
||||
}
|
||||
|
||||
/** Sets auto restart bit in the control register
|
||||
* @param btimer_id Basic Timer ID
|
||||
*/
|
||||
void p_btimer_ctrl_auto_restart_set(uint8_t btimer_id)
|
||||
{
|
||||
btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_AUTO_RESTART;
|
||||
}
|
||||
|
||||
/** Clears auto resetart bit in the control register
|
||||
* @param btimer_id Basic Timer ID
|
||||
*/
|
||||
void p_btimer_ctrl_auto_restart_clr(uint8_t btimer_id)
|
||||
{
|
||||
btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_AUTO_RESTART;
|
||||
}
|
||||
|
||||
/** Sets soft reset bit in the control register
|
||||
* @param btimer_id Basic Timer ID
|
||||
*/
|
||||
void p_btimer_ctrl_soft_reset_set(uint8_t btimer_id)
|
||||
{
|
||||
btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_SOFT_RESET;
|
||||
}
|
||||
|
||||
/** Read Soft Reset bit
|
||||
* @param btimer_id Basic Timer ID
|
||||
* @return 0 if soft reset status bit cleared; else non-zero value
|
||||
*/
|
||||
uint8_t p_btimer_ctrl_soft_reset_sts_get(uint8_t btimer_id)
|
||||
{
|
||||
return (btmr_inst[btimer_id]->CONTROL.b[0] & BTIMER_CNTL_SOFT_RESET);
|
||||
}
|
||||
|
||||
/** Sets start bit in the control register
|
||||
* @param btimer_id Basic Timer ID
|
||||
*/
|
||||
void p_btimer_ctrl_start_set(uint8_t btimer_id)
|
||||
{
|
||||
btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_START;
|
||||
}
|
||||
|
||||
/** Read start bit in the control register
|
||||
* @param btimer_id Basic Timer ID
|
||||
* @return 0 if start bit not set; else non-zero value
|
||||
*/
|
||||
uint8_t p_btimer_ctrl_start_get(uint8_t btimer_id)
|
||||
{
|
||||
return (btmr_inst[btimer_id]->CONTROL.b[0] & BTIMER_CNTL_START);
|
||||
}
|
||||
|
||||
/** Clears start bit in the control register
|
||||
* @param btimer_id Basic Timer ID
|
||||
*/
|
||||
void p_btimer_ctrl_start_clr(uint8_t btimer_id)
|
||||
{
|
||||
btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_START;
|
||||
}
|
||||
|
||||
/** Sets reload bit in the control register
|
||||
* @param btimer_id Basic Timer ID
|
||||
*/
|
||||
void p_btimer_ctrl_reload_set(uint8_t btimer_id)
|
||||
{
|
||||
btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_RELOAD;
|
||||
}
|
||||
|
||||
/** Clears reload bit in the control register
|
||||
* @param btimer_id Basic Timer ID
|
||||
*/
|
||||
void p_btimer_ctrl_reload_clr(uint8_t btimer_id)
|
||||
{
|
||||
btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_RELOAD;
|
||||
}
|
||||
|
||||
/** Sets halt bit in the control register
|
||||
* @param btimer_id Basic Timer ID
|
||||
*/
|
||||
void p_btimer_ctrl_halt_set(uint8_t btimer_id)
|
||||
{
|
||||
btmr_inst[btimer_id]->CONTROL.b[0] |= BTIMER_CNTL_HALT;
|
||||
}
|
||||
|
||||
/** Clears halt bit in the control register
|
||||
* @param btimer_id Basic Timer ID
|
||||
*/
|
||||
void p_btimer_ctrl_halt_clr(uint8_t btimer_id)
|
||||
{
|
||||
btmr_inst[btimer_id]->CONTROL.b[0] &= ~BTIMER_CNTL_HALT;
|
||||
}
|
||||
|
||||
/** Sets prescale value
|
||||
* @param btimer_id Basic Timer ID
|
||||
* @param prescaler - 16-bit pre-scale value
|
||||
*/
|
||||
void p_btimer_ctrl_prescale_set(uint8_t btimer_id, uint16_t prescaler)
|
||||
{
|
||||
btmr_inst[btimer_id]->CONTROL.h[1] = prescaler;
|
||||
}
|
||||
|
||||
|
||||
/* end btimer_perphl.c */
|
||||
|
||||
/** @} //Peripheral Basic_Timer
|
||||
*/
|
||||
|
||||
@ -0,0 +1,327 @@
|
||||
/****************************************************************************
|
||||
* © 2013 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*/
|
||||
|
||||
/** @defgroup pwm pwm_c_wrapper
|
||||
* @{
|
||||
*/
|
||||
/** @file pwm_c_wrapper.cpp
|
||||
\brief the pwm component C wrapper
|
||||
This program is designed to allow the other C programs to be able to use this component
|
||||
|
||||
There are entry points for all C wrapper API implementation
|
||||
|
||||
<b>Platform:</b> This is ARC-based component
|
||||
|
||||
<b>Toolset:</b> Metaware IDE(8.5.1)
|
||||
<b>Reference:</b> smsc_reusable_fw_requirement.doc */
|
||||
|
||||
/*******************************************************************************
|
||||
* SMSC version control information (Perforce):
|
||||
*
|
||||
* FILE: $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/cfg.h $
|
||||
* REVISION: $Revision: #1 $
|
||||
* DATETIME: $DateTime: 2015/12/23 15:37:58 $
|
||||
* AUTHOR: $Author: akrishnan $
|
||||
*
|
||||
* Revision history (latest first):
|
||||
* #1 Branched from //depotAE/projects/Sensor_Fusion/maincodeline/sf01_evb
|
||||
* #2 Updated tasks for smbus driver and smbus application
|
||||
* #3 Added feature, algo and fusion task
|
||||
* #4 Removed smbapp task
|
||||
***********************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef _CFG_H_
|
||||
#define _CFG_H_
|
||||
|
||||
|
||||
/*
|
||||
* TOOLSET : defines the build tools used
|
||||
* TOOLKEIL - For KEIL Toolset
|
||||
* TOOLPC - For PC Toolset, ex: MSVC++ 6.0,Borland C..etc.
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
#define INTERACTIVE_UART 0
|
||||
|
||||
/*
|
||||
* TASK_XX : defines the Kernel Task Assignements to Different Application Specific Tasks
|
||||
* : Always TASK_00 is High Priority
|
||||
* : Ex1: To Assign timer task to TASK_00
|
||||
* : #define TASK_00 timer
|
||||
* : Ex2: To Assign pwm task to TASK_03
|
||||
* : #define TASK_03 pwm
|
||||
* : Each Task should have Following Function Definitions
|
||||
* : (void) Tasxx_Init_task(void);
|
||||
* : (void) Taskxx_Main_task(enum EVENT_TYPE event);
|
||||
* : Please refer kernel.h for enum EVENT_TYPE
|
||||
* : Ex: If Application needs "tach" task should be added to kernel,
|
||||
* : tach.c should contain following public calls:
|
||||
* : (void)tach_init_task(void);
|
||||
* : (void)tach_main_task(enum EVENT_TYPE event);
|
||||
* :
|
||||
* : Each Task's event ie. EVENT TASK & EVENT TIMEOUT could be assigned the
|
||||
* : priority level. if it is assigned HIGH, then Task's event will belong to
|
||||
* : HIGH priority group.
|
||||
* : ex: define TASK_04 as pwm and pwm tasks event with following priority list
|
||||
* : PRIORITY_TASK_04_EVENTTASK LOW - This means, the pwm task (which is TASK_04) Event Task will be assigned to low priority group
|
||||
* : PRIORITY_TASK_04_EVENTTIMEOUT HIGH - This means, the pwm task Event Timeout will be assigned Hihg priority group
|
||||
*
|
||||
*/
|
||||
#define LOW 0
|
||||
#define HIGH !LOW
|
||||
|
||||
#define INTR_ON 1
|
||||
#define INTR_OFF 0
|
||||
|
||||
#define TASK_SCHED_LO 1
|
||||
#define TASK_SCHED_HI 2
|
||||
|
||||
#define MAX_NUM_TASKS 31 // Bits 0 - 30
|
||||
|
||||
// !!!! CRITICAL !!!
|
||||
// You MUST define the following values correctly
|
||||
//
|
||||
#define NUMBER_OF_TASKS 18 /* Total No: of Enabled Tasks */
|
||||
|
||||
#define TASK_00 timer /* TASK_00=timer */
|
||||
#define PRIORITY_TASK_00_EVENTTASK HIGH /* Timer Event Task HIGH priority */
|
||||
#define PRIORITY_TASK_00_EVENTTIMEOUT HIGH /* Timer Event Timeout HIGH priority */
|
||||
#define ENABLE_TASK_00_EVENTINTR 1 /* Enable EventTypeInterrupt scheduling */
|
||||
#define ENABLE_TASK_00_EVENTTASK 0
|
||||
#define ENABLE_TASK_00_EVENTTIMER 0
|
||||
|
||||
#define TASK_01 spi /* Task_01=spi - for spi */
|
||||
#define PRIORITY_TASK_01_EVENTTASK LOW /* Event Task HIGH priority */
|
||||
#define PRIORITY_TASK_01_EVENTTIMEOUT LOW /* Event Timeout LOW priority */
|
||||
#define ENABLE_TASK_01_EVENTINTR 0 /* Enable EventTypeInterrupt scheduling */
|
||||
#define ENABLE_TASK_01_EVENTTASK 0
|
||||
#define ENABLE_TASK_01_EVENTTIMER 1
|
||||
|
||||
#define TASK_02 smbus /* Task_02=smbus */
|
||||
#define PRIORITY_TASK_02_EVENTTASK HIGH /* temp Event Task HIGH priority */
|
||||
#define PRIORITY_TASK_02_EVENTTIMEOUT HIGH /* temp Event Timeout LOW priority */
|
||||
#define ENABLE_TASK_02_EVENTINTR 1 /* Enable EventTypeInterrupt scheduling */
|
||||
#define ENABLE_TASK_02_EVENTTASK 1
|
||||
#define ENABLE_TASK_02_EVENTTIMER 1
|
||||
|
||||
#define TASK_03 smbus_app /* TASK_03=smbus_app */
|
||||
#define PRIORITY_TASK_03_EVENTTASK HIGH /* Event Task HIGH priority */
|
||||
#define PRIORITY_TASK_03_EVENTTIMEOUT HIGH /* Event Timeout HIGH priority */
|
||||
#define ENABLE_TASK_03_EVENTINTR 0 /* Enable EventTypeInterrupt scheduling */
|
||||
#define ENABLE_TASK_03_EVENTTASK 1
|
||||
#define ENABLE_TASK_03_EVENTTIMER 1
|
||||
|
||||
#define TASK_04 pwm /* Task_04=pwm */
|
||||
#define PRIORITY_TASK_04_EVENTTASK LOW /* Event Task LOW priority */
|
||||
#define PRIORITY_TASK_04_EVENTTIMEOUT LOW /* Event Timeout LOW priority */
|
||||
#define ENABLE_TASK_04_EVENTINTR 0 /* Enable EventTypeInterrupt scheduling */
|
||||
#define ENABLE_TASK_04_EVENTTASK 0
|
||||
#define ENABLE_TASK_04_EVENTTIMER 1
|
||||
|
||||
#define TASK_05 adc /* TASK_05=adc */
|
||||
#define PRIORITY_TASK_05_EVENTTASK LOW /* Dflt Event Task LOW priority */
|
||||
#define PRIORITY_TASK_05_EVENTTIMEOUT LOW /* Dflt Event Timeout LOW priority */
|
||||
#define ENABLE_TASK_05_EVENTINTR 0 /* Enable EventTypeInterrupt scheduling */
|
||||
#define ENABLE_TASK_05_EVENTTASK 0
|
||||
#define ENABLE_TASK_05_EVENTTIMER 1
|
||||
|
||||
#define TASK_06 gpio /* TASK_06=gpio */
|
||||
#define PRIORITY_TASK_06_EVENTTASK LOW /* Dflt Event Task LOW priority */
|
||||
#define PRIORITY_TASK_06_EVENTTIMEOUT HIGH /* Dflt Event Timeout LOW priority */
|
||||
#define ENABLE_TASK_06_EVENTINTR 0 /* Enable EventTypeInterrupt scheduling */
|
||||
#define ENABLE_TASK_06_EVENTTASK 0
|
||||
#define ENABLE_TASK_06_EVENTTIMER 1
|
||||
|
||||
#define TASK_07 btimer /* Task_07=btimer */
|
||||
#define PRIORITY_TASK_07_EVENTTASK LOW /* Dflt Event Task LOW priority */
|
||||
#define PRIORITY_TASK_07_EVENTTIMEOUT LOW /* Dflt Event Timeout LOW priority */
|
||||
#define ENABLE_TASK_07_EVENTINTR 0 /* Enable EventTypeInterrupt scheduling */
|
||||
#define ENABLE_TASK_07_EVENTTASK 0
|
||||
#define ENABLE_TASK_07_EVENTTIMER 1
|
||||
|
||||
#define TASK_08 led /* Task_08=led */
|
||||
#define PRIORITY_TASK_08_EVENTTASK LOW /* Dflt Event Task LOW priority */
|
||||
#define PRIORITY_TASK_08_EVENTTIMEOUT LOW /* Dflt Event Timeout LOW priority */
|
||||
#define ENABLE_TASK_08_EVENTINTR 0 /* Enable EventTypeInterrupt scheduling */
|
||||
#define ENABLE_TASK_08_EVENTTASK 0
|
||||
#define ENABLE_TASK_08_EVENTTIMER 1
|
||||
|
||||
#define TASK_09 wdt /* Task_09=wdt */
|
||||
#define PRIORITY_TASK_09_EVENTTASK LOW /* Dflt Event Task LOW priority */
|
||||
#define PRIORITY_TASK_09_EVENTTIMEOUT LOW /* Dflt Event Timeout LOW priority */
|
||||
#define ENABLE_TASK_09_EVENTINTR 1 /* Enable EventTypeInterrupt scheduling */
|
||||
#define ENABLE_TASK_09_EVENTTASK 1
|
||||
#define ENABLE_TASK_09_EVENTTIMER 1
|
||||
|
||||
#define TASK_10 aes /* Task_10=aes */
|
||||
#define PRIORITY_TASK_10_EVENTTASK LOW /* phot Event Task LOW priority */
|
||||
#define PRIORITY_TASK_10_EVENTTIMEOUT LOW /* phot Event Timeout LOW priority */
|
||||
#define ENABLE_TASK_10_EVENTINTR 0 /* Enable EventTypeInterrupt scheduling */
|
||||
#define ENABLE_TASK_10_EVENTTASK 0
|
||||
#define ENABLE_TASK_10_EVENTTIMER 1
|
||||
|
||||
#define TASK_11 rnd /* Task_11=rnd */
|
||||
#define PRIORITY_TASK_11_EVENTTASK LOW /* Dflt Event Task LOW priority */
|
||||
#define PRIORITY_TASK_11_EVENTTIMEOUT LOW /* Dflt Event Timeout LOW priority */
|
||||
#define ENABLE_TASK_11_EVENTINTR 0 /* Enable EventTypeInterrupt scheduling */
|
||||
#define ENABLE_TASK_11_EVENTTASK 0
|
||||
#define ENABLE_TASK_11_EVENTTIMER 1
|
||||
|
||||
#define TASK_12 sha /* Task_12=sha */
|
||||
#define PRIORITY_TASK_12_EVENTTASK LOW /* Dflt Event Task LOW priority */
|
||||
#define PRIORITY_TASK_12_EVENTTIMEOUT LOW /* Dflt Event Timeout LOW priority */
|
||||
#define ENABLE_TASK_12_EVENTINTR 0 /* Enable EventTypeInterrupt scheduling */
|
||||
#define ENABLE_TASK_12_EVENTTASK 0
|
||||
#define ENABLE_TASK_12_EVENTTIMER 1
|
||||
|
||||
#define TASK_13 pke /* Task_13=pke */
|
||||
#define PRIORITY_TASK_13_EVENTTASK LOW /* Dflt Event Task LOW priority */
|
||||
#define PRIORITY_TASK_13_EVENTTIMEOUT LOW /* Dflt Event Timeout LOW priority */
|
||||
#define ENABLE_TASK_13_EVENTINTR 0 /* Enable EventTypeInterrupt scheduling */
|
||||
#define ENABLE_TASK_13_EVENTTASK 0
|
||||
#define ENABLE_TASK_13_EVENTTIMER 1
|
||||
|
||||
#define TASK_14 tach /* Task_14=tach */
|
||||
#define PRIORITY_TASK_14_EVENTTASK LOW /* Dflt Event Task LOW priority */
|
||||
#define PRIORITY_TASK_14_EVENTTIMEOUT LOW /* Dflt Event Timeout LOW priority */
|
||||
#define ENABLE_TASK_14_EVENTINTR 0 /* Enable EventTypeInterrupt scheduling */
|
||||
#define ENABLE_TASK_14_EVENTTASK 0
|
||||
#define ENABLE_TASK_14_EVENTTIMER 1
|
||||
|
||||
#define TASK_15 rtc /* Task_15=rtc */
|
||||
#define PRIORITY_TASK_15_EVENTTASK LOW /* Dflt Event Task LOW priority */
|
||||
#define PRIORITY_TASK_15_EVENTTIMEOUT LOW /* Dflt Event Timeout LOW priority */
|
||||
#define ENABLE_TASK_15_EVENTINTR 1 /* Enable EventTypeInterrupt scheduling */
|
||||
#define ENABLE_TASK_15_EVENTTASK 0
|
||||
#define ENABLE_TASK_15_EVENTTIMER 1
|
||||
|
||||
#define TASK_16 htimer /* TASK_06=htimer */
|
||||
#define PRIORITY_TASK_16_EVENTTASK LOW /* Dflt Event Task LOW priority */
|
||||
#define PRIORITY_TASK_16_EVENTTIMEOUT LOW /* Dflt Event Timeout LOW priority */
|
||||
#define ENABLE_TASK_16_EVENTINTR 0 /* Enable EventTypeInterrupt scheduling */
|
||||
#define ENABLE_TASK_16_EVENTTASK 0
|
||||
#define ENABLE_TASK_16_EVENTTIMER 1
|
||||
|
||||
#define TASK_17 uart /* Task_17=uart */
|
||||
#define PRIORITY_TASK_17_EVENTTASK LOW /* Dflt Event Task LOW priority */
|
||||
#define PRIORITY_TASK_17_EVENTTIMEOUT HIGH /* Dflt Event Timeout LOW priority */
|
||||
#define ENABLE_TASK_17_EVENTINTR 0 /* Enable EventTypeInterrupt scheduling */
|
||||
#define ENABLE_TASK_17_EVENTTASK 0
|
||||
#define ENABLE_TASK_17_EVENTTIMER 1
|
||||
|
||||
#define TASK_18 dflt /* Task_18=dflt */
|
||||
#define PRIORITY_TASK_18_EVENTTASK LOW /* Dflt Event Task LOW priority */
|
||||
#define PRIORITY_TASK_18_EVENTTIMEOUT LOW /* Dflt Event Timeout LOW priority */
|
||||
#define ENABLE_TASK_18_EVENTINTR 1 /* Enable EventTypeInterrupt scheduling */
|
||||
#define ENABLE_TASK_18_EVENTTASK 1
|
||||
#define ENABLE_TASK_18_EVENTTIMER 1
|
||||
|
||||
//#define TASK_19 dflt /* Task_19=dflt */
|
||||
//#define PRIORITY_TASK_19_EVENTTASK LOW /* Dflt Event Task LOW priority */
|
||||
//#define PRIORITY_TASK_19_EVENTTIMEOUT LOW /* Dflt Event Timeout LOW priority */
|
||||
//#define ENABLE_TASK_19_EVENTINTR 0 /* Enable EventTypeInterrupt scheduling */
|
||||
//#define ENABLE_TASK_19_EVENTTASK 0
|
||||
//#define ENABLE_TASK_19_EVENTTIMER 0
|
||||
|
||||
//#define TASK_20 dflt /* Task_20=dflt */
|
||||
//#define PRIORITY_TASK_20_EVENTTASK LOW /* Dflt Event Task LOW priority */
|
||||
//#define PRIORITY_TASK_20_EVENTTIMEOUT LOW /* Dflt Event Timeout LOW priority */
|
||||
//#define ENABLE_TASK_20_EVENTINTR 0 /* Enable EventTypeInterrupt scheduling */
|
||||
//#define ENABLE_TASK_20_EVENTTASK 0
|
||||
//#define ENABLE_TASK_20_EVENTTIMER 0
|
||||
|
||||
//#define TASK_21 dflt /* Task_21=dflt */
|
||||
//#define PRIORITY_TASK_21_EVENTTASK LOW /* Dflt Event Task LOW priority */
|
||||
//#define PRIORITY_TASK_21_EVENTTIMEOUT LOW /* Dflt Event Timeout LOW priority */
|
||||
//#define ENABLE_TASK_21_EVENTINTR 0 /* Enable EventTypeInterrupt scheduling */
|
||||
//#define ENABLE_TASK_21_EVENTTASK 0
|
||||
//#define ENABLE_TASK_21_EVENTTIMER 0
|
||||
|
||||
//#define TASK_22 dflt /* Task_22=dflt */
|
||||
//#define PRIORITY_TASK_22_EVENTTASK LOW /* Dflt Event Task LOW priority */
|
||||
//#define PRIORITY_TASK_22_EVENTTIMEOUT LOW /* Dflt Event Timeout LOW priority */
|
||||
//#define ENABLE_TASK_22_EVENTINTR 0 /* Enable EventTypeInterrupt scheduling */
|
||||
//#define ENABLE_TASK_22_EVENTTASK 0
|
||||
//#define ENABLE_TASK_22_EVENTTIMER 0
|
||||
|
||||
//#define TASK_23 dflt /* Task_23=dflt */
|
||||
//#define PRIORITY_TASK_23_EVENTTASK LOW /* Dflt Event Task LOW priority */
|
||||
//#define PRIORITY_TASK_23_EVENTTIMEOUT LOW /* Dflt Event Timeout LOW priority */
|
||||
//#define ENABLE_TASK_23_EVENTINTR 0 /* Enable EventTypeInterrupt scheduling */
|
||||
//#define ENABLE_TASK_23_EVENTTASK 0
|
||||
//#define ENABLE_TASK_23_EVENTTIMER 0
|
||||
|
||||
//#define TASK_24 dflt /* Task_24=dflt */
|
||||
//#define PRIORITY_TASK_24_EVENTTASK LOW /* Dflt Event Task LOW priority */
|
||||
//#define PRIORITY_TASK_24_EVENTTIMEOUT LOW /* Dflt Event Timeout LOW priority */
|
||||
//#define ENABLE_TASK_24_EVENTINTR 0 /* Enable EventTypeInterrupt scheduling */
|
||||
//#define ENABLE_TASK_24_EVENTTASK 0
|
||||
//#define ENABLE_TASK_24_EVENTTIMER 0
|
||||
|
||||
//#define TASK_25 dflt /* Task_25=dflt */
|
||||
//#define PRIORITY_TASK_25_EVENTTASK LOW /* Dflt Event Task LOW priority */
|
||||
//#define PRIORITY_TASK_25_EVENTTIMEOUT LOW /* Dflt Event Timeout LOW priority */
|
||||
//#define ENABLE_TASK_25_EVENTINTR 0 /* Enable EventTypeInterrupt scheduling */
|
||||
//#define ENABLE_TASK_25_EVENTTASK 0
|
||||
//#define ENABLE_TASK_25_EVENTTIMER 0
|
||||
|
||||
//#define TASK_26 dflt /* Task_26=dflt */
|
||||
//#define PRIORITY_TASK_26_EVENTTASK LOW /* Dflt Event Task LOW priority */
|
||||
//#define PRIORITY_TASK_26_EVENTTIMEOUT LOW /* Dflt Event Timeout LOW priority */
|
||||
//#define ENABLE_TASK_26_EVENTINTR 0 /* Enable EventTypeInterrupt scheduling */
|
||||
//#define ENABLE_TASK_26_EVENTTASK 0
|
||||
//#define ENABLE_TASK_26_EVENTTIMER 0
|
||||
|
||||
//#define TASK_27 dflt /* Task_27=dflt */
|
||||
//#define PRIORITY_TASK_27_EVENTTASK LOW /* Dflt Event Task LOW priority */
|
||||
//#define PRIORITY_TASK_27_EVENTTIMEOUT LOW /* Dflt Event Timeout LOW priority */
|
||||
//#define ENABLE_TASK_27_EVENTINTR 0 /* Enable EventTypeInterrupt scheduling */
|
||||
//#define ENABLE_TASK_27_EVENTTASK 0
|
||||
//#define ENABLE_TASK_27_EVENTTIMER 0
|
||||
|
||||
//#define TASK_28 dflt /* Task_28=dflt */
|
||||
//#define PRIORITY_TASK_28_EVENTTASK LOW /* Dflt Event Task LOW priority */
|
||||
//#define PRIORITY_TASK_28_EVENTTIMEOUT LOW /* Dflt Event Timeout LOW priority */
|
||||
//#define ENABLE_TASK_28_EVENTINTR 0 /* Enable EventTypeInterrupt scheduling */
|
||||
//#define ENABLE_TASK_28_EVENTTASK 0
|
||||
//#define ENABLE_TASK_28_EVENTTIMER 0
|
||||
|
||||
//#define TASK_29 dflt /* Task_29=dflt */
|
||||
//#define PRIORITY_TASK_29_EVENTTASK LOW /* Dflt Event Task LOW priority */
|
||||
//#define PRIORITY_TASK_29_EVENTTIMEOUT LOW /* Dflt Event Timeout LOW priority */
|
||||
//#define ENABLE_TASK_29_EVENTINTR 0 /* Enable EventTypeInterrupt scheduling */
|
||||
//#define ENABLE_TASK_29_EVENTTASK 0
|
||||
//#define ENABLE_TASK_29_EVENTTIMER 0
|
||||
|
||||
//#define TASK_30 dflt /* Task_30=dflt */
|
||||
//#define PRIORITY_TASK_30_EVENTTASK LOW /* Dflt Event Task LOW priority */
|
||||
//#define PRIORITY_TASK_30_EVENTTIMEOUT LOW /* Dflt Event Timeout LOW priority */
|
||||
//#define ENABLE_TASK_30_EVENTINTR 0 /* Enable EventTypeInterrupt scheduling */
|
||||
//#define ENABLE_TASK_30_EVENTTASK 0
|
||||
//#define ENABLE_TASK_30_EVENTTIMER 0
|
||||
|
||||
|
||||
#endif /*_CFG_H_*/
|
||||
|
||||
/** @}
|
||||
*/
|
||||
|
||||
@ -0,0 +1,71 @@
|
||||
/*
|
||||
**********************************************************************************
|
||||
* © 2013 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
**********************************************************************************
|
||||
* common.h
|
||||
* This is the header file including common headers from various modules
|
||||
**********************************************************************************
|
||||
* $Revision: #1 $ $DateTime: 2015/12/23 15:37:58 $ $ $
|
||||
* Description: added ict module
|
||||
**********************************************************************************
|
||||
* #xx
|
||||
**********************************************************************************
|
||||
* $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/common.h $
|
||||
*/
|
||||
|
||||
/*********************************************************************************/
|
||||
/** @defgroup common common
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @file common.h
|
||||
* \brief header file including common headers from various modules
|
||||
* \author App Firmware Team
|
||||
*
|
||||
**********************************************************************************/
|
||||
#ifndef _COMMON_H_
|
||||
#define _COMMON_H_
|
||||
|
||||
// Include common headers from various modules
|
||||
// !!! The include order is important !!!
|
||||
#include "cfg.h"
|
||||
#include "platform.h"
|
||||
#include "MCHP_CEC1302.h"
|
||||
#include "ARM_REG.h"
|
||||
/* Cortex-M4 processor and core peripherals */
|
||||
#include "core_cm4.h"
|
||||
#include "MEC1322.h"
|
||||
|
||||
#include "defs.h"
|
||||
#include "string.h"
|
||||
|
||||
#include "kernel.h"
|
||||
#include "..\system\system.h"
|
||||
#include "..\debug\trace.h"
|
||||
#include "..\interrupt\interrupt.h"
|
||||
#include "..\timer\timer_app.h"
|
||||
|
||||
#include "cec1302_crypto_api.h"
|
||||
|
||||
#endif /*_COMMON_H_*/
|
||||
|
||||
/** @}
|
||||
*/
|
||||
|
||||
|
||||
@ -0,0 +1,64 @@
|
||||
/*
|
||||
**********************************************************************************
|
||||
* © 2013 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
**********************************************************************************
|
||||
* common.h
|
||||
* This is the header file including common headers from various modules
|
||||
**********************************************************************************
|
||||
* $Revision: #1 $ $DateTime: 2015/12/23 15:37:58 $ $ $
|
||||
* Description: added ict module
|
||||
**********************************************************************************
|
||||
* #xx
|
||||
**********************************************************************************
|
||||
* $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/common_lib.h $
|
||||
*/
|
||||
|
||||
/*********************************************************************************/
|
||||
/** @defgroup common common
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @file common.h
|
||||
* \brief header file including common headers from various modules
|
||||
* \author App Firmware Team
|
||||
*
|
||||
**********************************************************************************/
|
||||
#ifndef _COMMON_LIB_H_
|
||||
#define _COMMON_LIB_H_
|
||||
|
||||
// Include common headers from various modules
|
||||
// !!! The include order is important !!!
|
||||
#include "platform.h"
|
||||
#include "ARM_REG.h"
|
||||
#include "MCHP_CEC1302.h"
|
||||
/* Cortex-M4 processor and core peripherals */
|
||||
#include "core_cm4.h"
|
||||
#include "MEC1322.h"
|
||||
#include "defs.h"
|
||||
#include "string.h"
|
||||
//_RB_#include "build.h"
|
||||
//_RB_#include "..\system\system.h"
|
||||
//_RB_#include "..\debug\trace.h"
|
||||
#include <stdbool.h>
|
||||
#endif /*_COMMON_LIB_H_*/
|
||||
|
||||
/** @}
|
||||
*/
|
||||
|
||||
|
||||
@ -0,0 +1,54 @@
|
||||
/*
|
||||
**********************************************************************************
|
||||
* © 2013 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
**********************************************************************************
|
||||
* defs.h
|
||||
* This is the definition header file for generic usages
|
||||
**********************************************************************************
|
||||
* #xx
|
||||
**********************************************************************************
|
||||
* $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/defs.h $
|
||||
*/
|
||||
|
||||
|
||||
/*********************************************************************************/
|
||||
/** @defgroup defs defs
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @file defs.h
|
||||
* \brief definition header file for generic usages
|
||||
* \author App Firmware Team
|
||||
*
|
||||
**********************************************************************************/
|
||||
#ifndef _DEFS_H_
|
||||
#define _DEFS_H_
|
||||
|
||||
/* bit operation MACRO, xvar could be byte, word or dword */
|
||||
#define mSET_BIT(x, xvar) ( xvar |= x )
|
||||
#define mCLR_BIT(x, xvar) ( xvar &= ~x )
|
||||
#define mGET_BIT(x, xvar) ( xvar & x )
|
||||
#define mCLR_SRC_BIT(x, xvar) ( xvar = x )
|
||||
#define mTOGGLE_BIT(x, xvar) {if(mGET_BIT(x, xvar)){mCLR_BIT(x, xvar);}else{mSET_BIT(x, xvar);}}
|
||||
|
||||
#endif /*_DEFS_H_*/
|
||||
|
||||
/** @}
|
||||
*/
|
||||
|
||||
@ -0,0 +1,111 @@
|
||||
/*****************************************************************************
|
||||
* © 2015 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
******************************************************************************
|
||||
|
||||
Version Control Information (Perforce)
|
||||
******************************************************************************
|
||||
$Revision: #1 $
|
||||
$DateTime: 2015/12/17 01:09:00 $
|
||||
$Author: snakka $
|
||||
Last Change: Updated for peripheral functions prefix p_
|
||||
******************************************************************************/
|
||||
/** @file btimer.h
|
||||
* \brief Hibernation Timer Peripheral Header file
|
||||
* \author jvasanth
|
||||
*
|
||||
* This file is the header file for Hibernation Timer Peripheral
|
||||
******************************************************************************/
|
||||
|
||||
/** @defgroup Hibernation_Timer
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _HTIMER_H
|
||||
#define _HTIMER_H
|
||||
|
||||
/******************************************************************************/
|
||||
/** Logical Timer ID for APIs.
|
||||
* This is the timer IDs passed to Hibernation Timer function calls
|
||||
*******************************************************************************/
|
||||
enum _PID_HTIMER_
|
||||
{
|
||||
PID_HTIMER_0,
|
||||
PID_HTIMER_MAX
|
||||
};
|
||||
|
||||
#define HTIMER_MAX_INSTANCE PID_HTIMER_MAX
|
||||
|
||||
/* -------------------------------------------------------------------- */
|
||||
/* Hibernation Timer APIs */
|
||||
/* -------------------------------------------------------------------- */
|
||||
/** Enables hibernation timer
|
||||
* @param htimer_id Hibernation Timer ID
|
||||
* @param preload_value - 16-bit preload value
|
||||
* @param resolution_mode 0 - resolution of 30.5us per LSB,
|
||||
* 1 - resolution of 0.125s per LSB
|
||||
*/
|
||||
void htimer_enable(uint8_t htimer_id, uint16_t preload_value, uint8_t resolution_mode);
|
||||
|
||||
/** Disables the hibernation timer by programming the prelaod value as 0
|
||||
* @param htimer_id Hibernation Timer ID
|
||||
*/
|
||||
void htimer_disable(uint8_t htimer_id);
|
||||
|
||||
|
||||
/** Reloads new preload value for the hibernation timer
|
||||
* @param htimer_id Hibernation Timer ID
|
||||
* @param reload_value - 16-bit preload value
|
||||
*/
|
||||
void htimer_reload(uint8_t htimer_id, uint16_t reload_value);
|
||||
|
||||
|
||||
/* -------------------------------------------------------------------- */
|
||||
/* Hibernation Timer Peripheral Functions */
|
||||
/* -------------------------------------------------------------------- */
|
||||
/** Sets hibernation timer preload value
|
||||
* @param htimer_id Hibernation Timer ID
|
||||
* @param preload_value - 16-bit preload value
|
||||
*/
|
||||
void p_htimer_preload_set(uint8_t htimer_id, uint16_t preload_value);
|
||||
|
||||
/*_RB_ Added by RB. */
|
||||
uint16_t p_htimer_preload_get(uint8_t htimer_id);
|
||||
|
||||
/** Sets hibernation timer resolution
|
||||
* @param htimer_id Hibernation Timer ID
|
||||
* @param resolution_mode 0 - resolution of 30.5us per LSB,
|
||||
* 1 - resolution of 0.125s per LSB
|
||||
*/
|
||||
void p_htimer_resolution_set(uint8_t htimer_id, uint8_t resolution_mode);
|
||||
|
||||
|
||||
/** Returns the Hibernation Timer current count value
|
||||
* @param htimer_id Hibernation Timer ID
|
||||
* @return 16-bit count value
|
||||
*/
|
||||
uint16_t p_htimer_count_get(uint8_t htimer_id);
|
||||
|
||||
|
||||
#endif // #ifndef _HTIMER_H
|
||||
|
||||
/* end htimer.h */
|
||||
|
||||
/** @} //Peripherals Hibernation_Timer
|
||||
*/
|
||||
|
||||
@ -0,0 +1,112 @@
|
||||
/*****************************************************************************
|
||||
* © 2015 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
******************************************************************************
|
||||
|
||||
Version Control Information (Perforce)
|
||||
******************************************************************************
|
||||
$Revision: #1 $
|
||||
$DateTime: 2015/12/17 01:09:00 $
|
||||
$Author: snakka $
|
||||
Last Change: Updated for peripheral functions prefix p_
|
||||
******************************************************************************/
|
||||
/** @file btimer_perphl.c
|
||||
* \brief Hibernation Timer API Source file
|
||||
* \author jvasanth
|
||||
*
|
||||
* This file implements Hibernation Timer APIs
|
||||
******************************************************************************/
|
||||
|
||||
/** @defgroup Hibernation_Timer
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "common_lib.h"
|
||||
#include "htimer.h"
|
||||
|
||||
#ifdef PLIB_HTIMER_CHECK_ID
|
||||
|
||||
/** Local helper that checks if logical Timer ID is valid.
|
||||
* @param htimer_id Hibernation Timer ID
|
||||
* @return uint8_t Non-zero(VALID), 0(Invalid)
|
||||
*/
|
||||
static uint8_t htmr_valid(uint8_t htimer_id)
|
||||
{
|
||||
if ( htimer_id < (PID_HTIMER_MAX ) ) {
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
|
||||
/** This version of tmr_valid skips checking always returning 1.
|
||||
* Compiler may optimize it out.
|
||||
* @param htimer_id Hibernation Timer ID
|
||||
* @return uint8_t 1(VALID)
|
||||
*/
|
||||
static uint8_t htmr_valid(uint8_t htimer_id) { return 1; }
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/** Enables hibernation timer
|
||||
* @param htimer_id Hibernation Timer ID
|
||||
* @param preload_value - 16-bit preload value
|
||||
* @param resolution_mode 0 - resolution of 30.5us per LSB,
|
||||
* 1 - resolution of 0.125s per LSB
|
||||
*/
|
||||
void htimer_enable(uint8_t htimer_id, uint16_t preload_value, uint8_t resolution_mode)
|
||||
{
|
||||
if (htmr_valid(htimer_id))
|
||||
{
|
||||
p_htimer_preload_set(htimer_id, preload_value);
|
||||
|
||||
p_htimer_resolution_set(htimer_id, resolution_mode);
|
||||
}
|
||||
}
|
||||
|
||||
/** Disables the hibernation timer by programming the prelaod value as 0
|
||||
* @param htimer_id Hibernation Timer ID
|
||||
*/
|
||||
void htimer_disable(uint8_t htimer_id)
|
||||
{
|
||||
if (htmr_valid(htimer_id))
|
||||
{
|
||||
p_htimer_preload_set(htimer_id, 0);
|
||||
}
|
||||
}
|
||||
|
||||
/** Reloads new preload value for the hibernation timer
|
||||
* @param htimer_id Hibernation Timer ID
|
||||
* @param reload_value - 16-bit preload value
|
||||
*/
|
||||
void htimer_reload(uint8_t htimer_id, uint16_t reload_value)
|
||||
{
|
||||
if ( htmr_valid(htimer_id))
|
||||
{
|
||||
p_htimer_preload_set(htimer_id, reload_value);
|
||||
}
|
||||
}
|
||||
|
||||
/* end htimer_api.c */
|
||||
|
||||
/** @} //APIs Hibernation_Timer
|
||||
*/
|
||||
|
||||
@ -0,0 +1,93 @@
|
||||
/*****************************************************************************
|
||||
* © 2015 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
******************************************************************************
|
||||
|
||||
Version Control Information (Perforce)
|
||||
******************************************************************************
|
||||
$Revision: #1 $
|
||||
$DateTime: 2015/12/17 01:09:00 $
|
||||
$Author: snakka $
|
||||
Last Change: Updated for peripheral functions prefix p_
|
||||
******************************************************************************/
|
||||
/** @file btimer_perphl.c
|
||||
* \brief Hibernation Timer Peripheral Source file
|
||||
* \author jvasanth
|
||||
*
|
||||
* This file implements Hibernation Timer Peripheral functions
|
||||
******************************************************************************/
|
||||
|
||||
/** @defgroup Hibernation_Timer
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "common_lib.h"
|
||||
#include "htimer.h"
|
||||
|
||||
/** Hibernation Timer Instance base addresses */
|
||||
static HTM_Type * const htmr_inst[HTIMER_MAX_INSTANCE] = {
|
||||
CEC1302_HTM
|
||||
};
|
||||
|
||||
/** Sets hibernation timer preload value
|
||||
* @param htimer_id Hibernation Timer ID
|
||||
* @param preload_value - 16-bit preload value
|
||||
* @note Setting the preload with a non-zero value starts
|
||||
* the hibernation timer to down count. Setting the preload
|
||||
* to 0 disables the hibernation counter
|
||||
*/
|
||||
void p_htimer_preload_set(uint8_t htimer_id, uint16_t preload_value)
|
||||
{
|
||||
htmr_inst[htimer_id]->PRELOAD = preload_value;
|
||||
}
|
||||
|
||||
/** Sets hibernation timer resolution
|
||||
* @param htimer_id Hibernation Timer ID
|
||||
* @param resolution_mode 0 - resolution of 30.5us per LSB,
|
||||
* 1 - resolution of 0.125s per LSB
|
||||
*/
|
||||
void p_htimer_resolution_set(uint8_t htimer_id, uint8_t resolution_mode)
|
||||
{
|
||||
htmr_inst[htimer_id]->CONTROL = resolution_mode;
|
||||
}
|
||||
|
||||
/** Returns the Hibernation Timer current count value
|
||||
* @param htimer_id Hibernation Timer ID
|
||||
* @return 16-bit count value
|
||||
*/
|
||||
uint16_t p_htimer_count_get(uint8_t htimer_id)
|
||||
{
|
||||
uint16_t htimer_count;
|
||||
|
||||
htimer_count = htmr_inst[htimer_id]->COUNT;
|
||||
|
||||
return htimer_count;
|
||||
}
|
||||
|
||||
/*_RB_ Added by RB. */
|
||||
uint16_t p_htimer_preload_get(uint8_t htimer_id)
|
||||
{
|
||||
return htmr_inst[htimer_id]->PRELOAD;
|
||||
}
|
||||
|
||||
|
||||
/* end htimer_perphl.c */
|
||||
|
||||
/** @} //Peripheral Hibernation_Timer
|
||||
*/
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,462 @@
|
||||
/*****************************************************************************
|
||||
* © 2015 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
******************************************************************************
|
||||
|
||||
Version Control Information (Perforce)
|
||||
******************************************************************************
|
||||
$Revision: #1 $
|
||||
$DateTime: 2015/11/24 06:28:28 $
|
||||
$Author: amohandas $
|
||||
Last Change: Updated for tabs
|
||||
******************************************************************************/
|
||||
/** @file pcr.h
|
||||
* \brief Power, Clocks, and Resets Header file
|
||||
* \author jvasanth
|
||||
*
|
||||
* This file is the PCR header file
|
||||
******************************************************************************/
|
||||
|
||||
/** @defgroup PCR
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _PCR_H
|
||||
#define _PCR_H
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/** PCR Register IDS
|
||||
*******************************************************************************/
|
||||
enum _PCR_REGSET_ID_
|
||||
{
|
||||
PCR_REG_CHIP_SLEEP_ENABLE =0,
|
||||
PCR_REG_CHIP_CLK_REQD_STS,
|
||||
PCR_REG_EC_SLEEP_ENABLE,
|
||||
PCR_REG_EC_CLK_REQD_STS,
|
||||
PCR_REG_HOST_SLEEP_ENABLE,
|
||||
PCR_REG_HOST_CLK_REQD_STS,
|
||||
PCR_REG_SYSTEM_SLEEP_CTRL,
|
||||
PCR_REG_PROCESSOR_CLK_CTRL = 8,
|
||||
PCR_REG_EC_SLEEP_ENABLE_2,
|
||||
PCR_REG_EC_CLK_REQD_STS_2,
|
||||
PCR_REG_SLOW_CLK_CTRL,
|
||||
PCR_REG_OSCILLATOR_ID,
|
||||
PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS,
|
||||
PCR_REG_CHIP_RESET_ENABLE,
|
||||
PCR_REG_HOST_RESET_ENABLE,
|
||||
PCR_REG_EC_RESET_ENABLE,
|
||||
PCR_REG_EC_RESET_ENABLE_2,
|
||||
PCR_REG_PWR_RESET_CTRL
|
||||
};
|
||||
/* ---------------------------------------------------------------------- */
|
||||
|
||||
// Encode the Register ids for Sleep Enable, Clock Required, Reset Enable
|
||||
//PCR register group 0 - CHIP
|
||||
#define PCR0_REGS_CHIP (((uint32_t)(PCR_REG_CHIP_SLEEP_ENABLE) & 0xFF) + \
|
||||
(((uint32_t)(PCR_REG_CHIP_CLK_REQD_STS) & 0xFF)<<8u) + \
|
||||
(((uint32_t)(PCR_REG_CHIP_RESET_ENABLE) & 0xFF)<<16u))
|
||||
|
||||
//PCR register group 1 - EC
|
||||
#define PCR1_REGS_EC (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE) & 0xFF) + \
|
||||
(((uint32_t)(PCR_REG_EC_CLK_REQD_STS) & 0xFF)<<8u) + \
|
||||
(((uint32_t)(PCR_REG_EC_RESET_ENABLE) & 0xFF)<<16u))
|
||||
|
||||
//PCR register group 2 - HOST
|
||||
#define PCR2_REGS_HOST (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE) & 0xFF) + \
|
||||
(((uint32_t)(PCR_REG_EC_CLK_REQD_STS) & 0xFF)<<8u) + \
|
||||
(((uint32_t)(PCR_REG_EC_RESET_ENABLE) & 0xFF)<<16u))
|
||||
|
||||
//PCR register group 3 - EC 2
|
||||
#define PCR3_REGS_EC2 (((uint32_t)(PCR_REG_EC_SLEEP_ENABLE_2) & 0xFF) + \
|
||||
(((uint32_t)(PCR_REG_EC_CLK_REQD_STS_2) & 0xFF)<<8u) + \
|
||||
(((uint32_t)(PCR_REG_EC_RESET_ENABLE_2) & 0xFF)<<16u))
|
||||
|
||||
|
||||
//PCR1_EC -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions
|
||||
#define PCR1_EC_INT_BITPOS (0u)
|
||||
#define PCR1_EC_PECI_BITPOS (1u)
|
||||
#define PCR1_EC_TACH0_BITPOS (2u)
|
||||
#define PCR1_EC_PWM0_BITPOS (4u)
|
||||
#define PCR1_EC_PMC_BITPOS (5u)
|
||||
#define PCR1_EC_DMA_BITPOS (6u)
|
||||
#define PCR1_EC_TFDP_BITPOS (7u)
|
||||
#define PCR1_EC_CPU_BITPOS (8u)
|
||||
#define PCR1_EC_WDT_BITPOS (9u)
|
||||
#define PCR1_EC_SMB0_BITPOS (10u)
|
||||
#define PCR1_EC_TACH1_BITPOS (11u)
|
||||
#define PCR1_EC_PWM1_BITPOS (20u)
|
||||
#define PCR1_EC_PWM2_BITPOS (21u)
|
||||
#define PCR1_EC_PWM3_BITPOS (22u)
|
||||
#define PCR1_EC_REG_BITPOS (29u)
|
||||
#define PCR1_EC_BTIMER0_BITPOS (30u)
|
||||
#define PCR1_EC_BTIMER1_BITPOS (31u)
|
||||
|
||||
//PCR2_HOST -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions
|
||||
#define PCR2_HOST_LPC_BITPOS (0u)
|
||||
#define PCR2_HOST_UART0_BITPOS (1u)
|
||||
#define PCR2_HOST_GLBL_CFG_BITPOS (12u)
|
||||
#define PCR2_HOST_ACPI_EC0_BITPOS (13u)
|
||||
#define PCR2_HOST_ACPI_EC1_BITPOS (14u)
|
||||
#define PCR2_HOST_ACPI_PM1_BITPOS (15u)
|
||||
#define PCR2_HOST_8042EM_BITPOS (16u)
|
||||
#define PCR2_HOST_RTC_BITPOS (18u)
|
||||
|
||||
//PCR3_EC2 -> SLEEP_ENABLE, CLK REQD STS, RESET_ENABLE Bit Positions
|
||||
#define PCR3_EC2_ADC_BITPOS (3u)
|
||||
#define PCR3_EC2_PS2_0_BITPOS (5u)
|
||||
#define PCR3_EC2_PS2_1_BITPOS (6u)
|
||||
#define PCR3_EC2_PS2_2_BITPOS (7u)
|
||||
#define PCR3_EC2_PS2_3_BITPOS (8u)
|
||||
#define PCR3_EC2_SPI0_BITPOS (9u)
|
||||
#define PCR3_EC2_HTIMER_BITPOS (10u)
|
||||
#define PCR3_EC2_KEYSCAN_BITPOS (11u)
|
||||
#define PCR3_EC2_RPM_PWM_BITPOS (12u)
|
||||
#define PCR3_EC2_SMB1_BITPOS (13u)
|
||||
#define PCR3_EC2_SMB2_BITPOS (14u)
|
||||
#define PCR3_EC2_SMB3_BITPOS (15u)
|
||||
#define PCR3_EC2_LED0_BITPOS (16u)
|
||||
#define PCR3_EC2_LED1_BITPOS (17u)
|
||||
#define PCR3_EC2_LED2_BITPOS (18u)
|
||||
#define PCR3_EC2_BCM_BITPOS (19u)
|
||||
#define PCR3_EC2_SPI1_BITPOS (20u)
|
||||
#define PCR3_EC2_BTIMER2_BITPOS (21u)
|
||||
#define PCR3_EC2_BTIMER3_BITPOS (22u)
|
||||
#define PCR3_EC2_BTIMER4_BITPOS (23u)
|
||||
#define PCR3_EC2_BTIMER5_BITPOS (24u)
|
||||
#define PCR3_EC2_LED3_BITPOS (25u)
|
||||
|
||||
/*
|
||||
* n = b[7:0] = PCR Reg Bit Position
|
||||
* m = b[31:8] = PCRx Regs IDs
|
||||
*/
|
||||
//#define PCRx_REGS_BIT(m,n) ((((uint32_t)(m)&0xFFFFFFul)<<8u) + ((uint32_t)(n)&0xFFul))
|
||||
|
||||
//PCRx_REGS_BIT positions
|
||||
#define PCRx_REGS_POS_SLEEP_ENABLE (8u)
|
||||
#define PCRx_REGS_POS_CLK_REQD_STS (16u)
|
||||
#define PCRx_REGS_POS_RESET_ENABLE (24u)
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/** PCR Block IDS.
|
||||
* These IDs are used to directly refer to a block
|
||||
*******************************************************************************/
|
||||
typedef enum {
|
||||
PCR_INT = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_INT_BITPOS & 0xFFu)),
|
||||
PCR_PECI = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PECI_BITPOS & 0xFFu)),
|
||||
PCR_TACH0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TACH0_BITPOS & 0xFFu)),
|
||||
PCR_PWM0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM0_BITPOS & 0xFFu)),
|
||||
PCR_PMC = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PMC_BITPOS & 0xFFu)),
|
||||
PCR_DMA = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_DMA_BITPOS & 0xFFu)),
|
||||
PCR_TFDP = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TFDP_BITPOS & 0xFFu)),
|
||||
PCR_CPU = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_CPU_BITPOS & 0xFFu)),
|
||||
PCR_WDT = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_WDT_BITPOS & 0xFFu)),
|
||||
PCR_SMB0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_SMB0_BITPOS & 0xFFu)),
|
||||
PCR_TACH1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_TACH1_BITPOS & 0xFFu)),
|
||||
PCR_PWM1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM1_BITPOS & 0xFFu)),
|
||||
PCR_PWM2 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM2_BITPOS & 0xFFu)),
|
||||
PCR_PWM3 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_PWM3_BITPOS & 0xFFu)),
|
||||
PCR_REG = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_REG_BITPOS & 0xFFu)),
|
||||
PCR_BTIMER0 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_BTIMER0_BITPOS & 0xFFu)),
|
||||
PCR_BTIMER1 = (((uint32_t)(PCR1_REGS_EC) << 8) + (uint32_t)(PCR1_EC_BTIMER1_BITPOS & 0xFFu)),
|
||||
PCR_LPC = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_LPC_BITPOS & 0xFFu)),
|
||||
PCR_UART0 = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_UART0_BITPOS & 0xFFu)),
|
||||
PCR_GLBL_CFG = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_GLBL_CFG_BITPOS & 0xFFu)),
|
||||
PCR_ACPI_EC0 = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_ACPI_EC0_BITPOS & 0xFFu)),
|
||||
PCR_ACPI_EC1 = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_ACPI_EC1_BITPOS & 0xFFu)),
|
||||
PCR_ACPI_PM1 = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_ACPI_PM1_BITPOS & 0xFFu)),
|
||||
PCR_8042EM = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_8042EM_BITPOS & 0xFFu)),
|
||||
PCR_RTC = (((uint32_t)(PCR2_REGS_HOST) << 8) + (uint32_t)(PCR2_HOST_RTC_BITPOS & 0xFFu)),
|
||||
PCR_ADC = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_ADC_BITPOS & 0xFFu)),
|
||||
PCR_PS2_0 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_0_BITPOS & 0xFFu)),
|
||||
PCR_PS2_1 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_1_BITPOS & 0xFFu)),
|
||||
PCR_PS2_2 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_2_BITPOS & 0xFFu)),
|
||||
PCR_PS2_3 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_PS2_3_BITPOS & 0xFFu)),
|
||||
PCR_SPI0 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SPI0_BITPOS & 0xFFu)),
|
||||
PCR_HTIMER = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_HTIMER_BITPOS & 0xFFu)),
|
||||
PCR_KEYSCAN = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_KEYSCAN_BITPOS & 0xFFu)),
|
||||
PCR_RPM_PWM = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_RPM_PWM_BITPOS & 0xFFu)),
|
||||
PCR_SMB1 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SMB1_BITPOS & 0xFFu)),
|
||||
PCR_SMB2 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SMB2_BITPOS & 0xFFu)),
|
||||
PCR_SMB3 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SMB3_BITPOS & 0xFFu)),
|
||||
PCR_LED0 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED0_BITPOS & 0xFFu)),
|
||||
PCR_LED1 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED1_BITPOS & 0xFFu)),
|
||||
PCR_LED2 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED2_BITPOS & 0xFFu)),
|
||||
PCR_BCM = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BCM_BITPOS & 0xFFu)),
|
||||
PCR_SPI1 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_SPI1_BITPOS & 0xFFu)),
|
||||
PCR_BTIMER2 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER2_BITPOS & 0xFFu)),
|
||||
PCR_BTIMER3 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER3_BITPOS & 0xFFu)),
|
||||
PCR_BTIMER4 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER4_BITPOS & 0xFFu)),
|
||||
PCR_BTIMER5 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_BTIMER5_BITPOS & 0xFFu)),
|
||||
PCR_LED3 = (((uint32_t)(PCR3_REGS_EC2) << 8) + (uint32_t)(PCR3_EC2_LED3_BITPOS & 0xFFu)),
|
||||
} PCR_BLK_ID;
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/** PCR Processor ClK Divide Values
|
||||
*******************************************************************************/
|
||||
enum PROCESSOR_CLK_DIVIDE_VALUE
|
||||
{
|
||||
PCR_CPU_CLK_DIVIDE_1 = 1,
|
||||
PCR_CPU_CLK_DIVIDE_4 = 4,
|
||||
PCR_CPU_CLK_DIVIDE_16 = 16,
|
||||
PCR_CPU_CLK_DIVIDE_48 = 48
|
||||
};
|
||||
|
||||
/******************************************************************************/
|
||||
/** System Sleep Modes
|
||||
*******************************************************************************/
|
||||
enum SYSTEM_SLEEP_MODES
|
||||
{
|
||||
SYSTEM_HEAVY_SLEEP_1 = 0,
|
||||
SYSTEM_HEAVY_SLEEP_3 = 1,
|
||||
SYSTEM_HEAVY_SLEEP_2 = 2,
|
||||
SYSTEM_DEEPEST_SLEEP = 5
|
||||
};
|
||||
|
||||
/* Bitmask for System Sleep Control Register */
|
||||
#define PCR_SYS_SLP_CTRL_RING_OSC_PWR_DOWN_BITMASK (1UL<<0)
|
||||
#define PCR_SYS_SLP_CTRL_RING_OSC_OUTPUT_GATE_BITMASK (1UL<<1)
|
||||
#define PCR_SYS_SLP_CTRL_CORE_REGLTOR_STDBY_BITMASK (1UL<<2)
|
||||
|
||||
/* Bitmask for Chip Sub-system Power Reset Status Register */
|
||||
#define PCR_CHIP_SUBSYSTEM_VCC_RESET_STS_BITMASK (1UL<<2)
|
||||
#define PCR_CHIP_SUBSYSTEM_SIO_RESET_STS_BITMASK (1UL<<3)
|
||||
#define PCR_CHIP_SUBSYSTEM_VBAT_RESET_STS_BITMASK (1UL<<5)
|
||||
#define PCR_CHIP_SUBSYSTEM_VCC1_RESET_STS_BITMASK (1UL<<6)
|
||||
#define PCR_CHIP_SUBSYSTEM_32K_ACTIVE_STS_BITMASK (1UL<<10)
|
||||
#define PCR_CHIP_SUBSYSTEM_PCICLK_ACTIVE_STS_BITMASK (1UL<<11)
|
||||
|
||||
/* Bitmask for Processor Clock Control Register */
|
||||
#define PCR_OSCILLATOR_LOCK_STATUS_BITMASK (1UL<<8)
|
||||
|
||||
/* Bitmask for Power Reset Control Register */
|
||||
#define PCR_iRESET_OUT_BITMASK (1UL<<0)
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* API - Functions to program Sleep Enable, CLK Reqd Status, *
|
||||
* Reset Enable for a block *
|
||||
* ---------------------------------------------------------------------- */
|
||||
/** Sets or Clears block specific bit in PCR Sleep Enable Register
|
||||
* @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT
|
||||
* @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Sleep Enable Register
|
||||
*/
|
||||
void pcr_sleep_enable(uint32_t pcr_block_id, uint8_t set_clr_flag);
|
||||
|
||||
/** Get Clock Required Status for the block
|
||||
* @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT
|
||||
* @return uint8_t - 1 if Clock Required Status set, else 0
|
||||
*/
|
||||
uint8_t pcr_clock_reqd_status_get(uint32_t pcr_block_id);
|
||||
|
||||
/** Sets or Clears Reset Enable register bit for the block
|
||||
* @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT
|
||||
* @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Reset Enable Register
|
||||
*/
|
||||
void pcr_reset_enable(uint32_t pcr_block_id, uint8_t set_clr_flag);
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* API - Functions for entering low power modes */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/** Instructs all blocks to sleep by setting the Sleep Enable bits */
|
||||
void pcr_all_blocks_sleep(void);
|
||||
|
||||
/** Clears the Sleep Enable bits for all blocks */
|
||||
void pcr_all_blocks_wake(void);
|
||||
|
||||
/** Programs required sleep mode in System Sleep Control Register
|
||||
* @param sleep_mode - see enum SYSTEM_SLEEP_MODES
|
||||
*/
|
||||
void pcr_system_sleep(uint8_t sleep_mode);
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* Peripheral Function - Functions to program and read 32-bit values *
|
||||
* from PCR Registers *
|
||||
* ---------------------------------------------------------------------- */
|
||||
/** Write 32-bit value in the PCR Register
|
||||
* @param pcr_reg_id - pcr register id
|
||||
* @param value - 32-bit value
|
||||
*/
|
||||
void p_pcr_reg_write(uint8_t pcr_reg_id, uint32_t value);
|
||||
|
||||
/** Reads 32-bit value from the PCR Register
|
||||
* @param pcr_reg_id - pcr register id
|
||||
* @return value - 32-bit value
|
||||
*/
|
||||
uint32_t p_pcr_reg_read(uint8_t pcr_reg_id);
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* Peripheral Function - Functions to set, clr and get bits in *
|
||||
* PCR Registers *
|
||||
* ---------------------------------------------------------------------- */
|
||||
/** Sets bits in a PCR Register
|
||||
* @param pcr_reg_id - pcr register id
|
||||
* @param bit_mask - Bit mask of bits to set
|
||||
*/
|
||||
void p_pcr_reg_set(uint8_t pcr_reg_id, uint32_t bit_mask);
|
||||
|
||||
/** Clears bits in a PCR Register
|
||||
* @param pcr_reg_id - pcr register id
|
||||
* @param bit_mask - Bit mask of bits to clear
|
||||
*/
|
||||
void p_pcr_reg_clr(uint8_t pcr_reg_id, uint32_t bit_mask);
|
||||
|
||||
/** Read bits in a PCR Register
|
||||
* @param pcr_reg_id - pcr register id
|
||||
* @param bit_mask - Bit mask of bits to read
|
||||
* @return value - 32-bit value
|
||||
*/
|
||||
uint32_t p_pcr_reg_get(uint8_t pcr_reg_id, uint32_t bit_mask);
|
||||
|
||||
/** Sets or Clears bits in a PCR Register - Helper Function
|
||||
* @param pcr_reg_id - pcr register id
|
||||
* @param bit_mask - Bit mask of bits to set or clear
|
||||
* @param set_clr_flag - Flag to set (1) or clear (0) bits in the PCR Register
|
||||
*/
|
||||
void p_pcr_reg_update(uint8_t pcr_reg_id, uint32_t bit_mask, uint8_t set_clr_flag);
|
||||
|
||||
//Functions to operate on System Sleep Control Register
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* Peripheral Function - Functions to operate on System Sleep Control *
|
||||
* Register *
|
||||
* ---------------------------------------------------------------------- */
|
||||
/** Sets/Clears the Ring oscillator power down bit
|
||||
* in System Sleep Control Register
|
||||
* @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit
|
||||
*/
|
||||
void p_pcr_system_sleep_ctrl_ring_osc_power_down(uint8_t set_clr_flag);
|
||||
|
||||
/** Sets/Clears the Ring oscillator output gate bit
|
||||
* in System Sleep Control Register
|
||||
* @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit
|
||||
*/
|
||||
void p_pcr_system_sleep_ctrl_ring_osc_output_gate(uint8_t set_clr_flag);
|
||||
|
||||
/** Sets/Clears the Core regulator standby bit
|
||||
* in System Sleep Control Register
|
||||
* @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit
|
||||
*/
|
||||
void p_pcr_system_sleep_ctrl_core_regulator_stdby(uint8_t set_clr_flag);
|
||||
|
||||
/** Writes required sleep mode in System Sleep Control Register
|
||||
* @param sleep_value - System Sleep control value - [D2, D1, D0]
|
||||
*/
|
||||
void p_pcr_system_sleep_ctrl_write(uint8_t sleep_value);
|
||||
|
||||
/** Reads the System Sleep Control PCR Register
|
||||
* @return value - byte 0 of the system sleep control PCR register
|
||||
*/
|
||||
uint8_t p_pcr_system_sleep_ctrl_read(void);
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* Peripheral Function - Function to program to CLK Divide Value *
|
||||
* ---------------------------------------------------------------------- */
|
||||
/** Writes the clock divide value in the Processor Clock Control Register
|
||||
* @param clk_divide_value - clk divide values, valid values in enum PROCESSOR_CLK_DIVIDE_VALUE
|
||||
*/
|
||||
void p_pcr_processor_clk_ctrl_write(uint8_t clk_divide_value);
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* Peripheral Function - Function to program the Slow Clock Control *
|
||||
* Register *
|
||||
* ---------------------------------------------------------------------- */
|
||||
/** Write the slow clock divide value in the Slow Clock Control Register
|
||||
* @param slow_clk_divide_value - slow clk divide value
|
||||
*/
|
||||
void p_pcr_slow_clk_ctrl_write(uint8_t slow_clk_divide_value);
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* Peripheral Function - Function to read the Oscillator Lock Status */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/** Reads the Oscillator Lock status bit in the Oscillator ID Register
|
||||
* @return 1 if Oscillator Lock Status bit is set, else 0
|
||||
*/
|
||||
uint8_t p_pcr_oscillator_lock_sts_get(void);
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* Peripheral Function - Functions to read various power status in *
|
||||
* Chip Sub-System register *
|
||||
* ---------------------------------------------------------------------- */
|
||||
/** Reads the VCC Reset Status bit
|
||||
* in the Chip Subsystem Power Reset Status Register
|
||||
* @return 1 if VCC Reset Status bit is set, else 0
|
||||
*/
|
||||
uint8_t p_pcr_chip_subsystem_vcc_reset_sts_get(void);
|
||||
|
||||
/** Reads the SIO Reset Status bit
|
||||
* in the Chip Subsystem Power Reset Status Register
|
||||
* @return 1 if SIO Reset Status bit is set, else 0
|
||||
*/
|
||||
uint8_t p_pcr_chip_subsystem_sio_reset_sts_get(void);
|
||||
|
||||
/** Reads the VBAT Reset Status bit
|
||||
* in the Chip Subsystem Power Reset Status Register
|
||||
* @return 1 if VBAT Reset Status bit is set, else 0
|
||||
*/
|
||||
uint8_t p_pcr_chip_subsystem_vbat_reset_sts_get(void);
|
||||
|
||||
/** Clears the VBAT Reset Status bit
|
||||
* in the Chip Subsystem Power Reset Status Register
|
||||
*/
|
||||
void p_pcr_chip_subsystem_vbat_reset_sts_clr(void);
|
||||
|
||||
/** Reads the VCC1 Reset Status bit
|
||||
* in the Chip Subsystem Power Reset Status Register
|
||||
* @return 1 if VCC1 Reset Status bit is set, else 0
|
||||
*/
|
||||
uint8_t p_pcr_chip_subsystem_vcc1_reset_sts_get(void);
|
||||
|
||||
/** Clears the VCC1 Reset Status bit
|
||||
* in the Chip Subsystem Power Reset Status Register
|
||||
*/
|
||||
void p_pcr_chip_subsystem_vcc1_reset_sts_clr(void);
|
||||
|
||||
/** Reads the 32K_ACTIVE status bit
|
||||
* in the Chip Subsystem Power Reset Status Register
|
||||
* @return 1 if 32_ACTIVE bit is set, else 0
|
||||
*/
|
||||
uint8_t p_pcr_chip_subsystem_32K_active_sts_get(void);
|
||||
|
||||
/** Reads the PCICLK_ACTIVE status bit
|
||||
* in the Chip Subsystem Power Reset Status Register
|
||||
* @return 1 if CICLK_ACTIVE bit is set, else 0
|
||||
*/
|
||||
uint8_t p_pcr_chip_subsystem_pciclk_active_sts_get(void);
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* Peripheral Function - Functions for Power Reset Control Register */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/** Reads the iRESET_OUT bit in the Power Reset Control Register
|
||||
* @return 1 if iRESET_OUT bit is set, else 0
|
||||
*/
|
||||
uint8_t p_pcr_iReset_Out_get(void);
|
||||
|
||||
/** Sets/Clears the iRESET_OUT bit in the Power Reset Control Register
|
||||
* @param 1 Set iRESET_OUT bit; 0 - Clear the bit
|
||||
*/
|
||||
void p_pcr_iReset_Out(uint8_t set_clr_flag);
|
||||
|
||||
#endif // #ifndef _PCR_H
|
||||
/* end pcr.h */
|
||||
/** @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
@ -0,0 +1,133 @@
|
||||
/*****************************************************************************
|
||||
* © 2015 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
******************************************************************************
|
||||
|
||||
Version Control Information (Perforce)
|
||||
******************************************************************************
|
||||
$Revision: #1 $
|
||||
$DateTime: 2015/11/24 06:28:28 $
|
||||
$Author: amohandas $
|
||||
Last Change: Updated for tabs
|
||||
******************************************************************************/
|
||||
/** @file pcr_api.c
|
||||
* \brief Power, Clocks, and Resets API Source file
|
||||
* \author jvasanth
|
||||
*
|
||||
* This file implements the PCR APIs
|
||||
******************************************************************************/
|
||||
|
||||
/** @defgroup PCR
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "common_lib.h"
|
||||
#include "pcr.h"
|
||||
|
||||
|
||||
/* ------------------------------------------------------------------------------- */
|
||||
/* Functions to program Sleep Enable, CLK Reqd Status, Reset Enable for a block */
|
||||
/* ------------------------------------------------------------------------------- */
|
||||
|
||||
/** Sets or Clears block specific bit in PCR Sleep Enable Register
|
||||
* @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT
|
||||
* @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Sleep Enable Register
|
||||
*/
|
||||
void pcr_sleep_enable(uint32_t pcr_block_id, uint8_t set_clr_flag)
|
||||
{
|
||||
uint32_t bit_mask;
|
||||
uint8_t pcr_reg_id;
|
||||
|
||||
bit_mask = 1UL<<(pcr_block_id & 0xFFu);
|
||||
pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_SLEEP_ENABLE) & 0xFFu);
|
||||
|
||||
p_pcr_reg_update(pcr_reg_id, bit_mask, set_clr_flag);
|
||||
}
|
||||
|
||||
|
||||
/** Get Clock Required Status for the block
|
||||
* @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT
|
||||
* @return uint8_t - 1 if Clock Required Status set, else 0
|
||||
*/
|
||||
uint8_t pcr_clock_reqd_status_get(uint32_t pcr_block_id)
|
||||
{
|
||||
uint32_t bit_mask;
|
||||
uint8_t pcr_reg_id, retVal;
|
||||
|
||||
bit_mask = 1UL<<(pcr_block_id & 0xFFu);
|
||||
pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_CLK_REQD_STS) & 0xFFu);
|
||||
|
||||
retVal = 0;
|
||||
if (p_pcr_reg_get(pcr_reg_id, bit_mask))
|
||||
{
|
||||
retVal = 1;
|
||||
}
|
||||
|
||||
return retVal;
|
||||
}
|
||||
|
||||
/** Sets or Clears Reset Enable register bit for the block
|
||||
* @param pcr_block_id - pcr block id encoded using PCRx_REGS_BIT
|
||||
* @param set_clr_flag - Flag to set (1) or clear (0) bit in the PCR Reset Enable Register
|
||||
*/
|
||||
void pcr_reset_enable(uint32_t pcr_block_id, uint8_t set_clr_flag)
|
||||
{
|
||||
uint32_t bit_mask;
|
||||
uint8_t pcr_reg_id;
|
||||
|
||||
bit_mask = 1UL<<(pcr_block_id & 0xFFu);
|
||||
pcr_reg_id = (uint8_t)((pcr_block_id >> PCRx_REGS_POS_RESET_ENABLE) & 0xFFu);
|
||||
|
||||
p_pcr_reg_update(pcr_reg_id, bit_mask, set_clr_flag);
|
||||
}
|
||||
|
||||
|
||||
/* ------------------------------------------------------------------------------- */
|
||||
/* Functions for entering low power modes */
|
||||
/* ------------------------------------------------------------------------------- */
|
||||
|
||||
/** Instructs all blocks to sleep by setting the Sleep Enable bits */
|
||||
void pcr_all_blocks_sleep(void)
|
||||
{
|
||||
p_pcr_reg_write(PCR_REG_CHIP_SLEEP_ENABLE, 0xFFFFFFFF);
|
||||
p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE, 0xFFFFFFFF);
|
||||
p_pcr_reg_write(PCR_REG_HOST_SLEEP_ENABLE, 0xFFFFFFFF);
|
||||
p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_2, 0xFFFFFFFF);
|
||||
}
|
||||
|
||||
/** Clears the Sleep Enable bits for all blocks */
|
||||
void pcr_all_blocks_wake(void)
|
||||
{
|
||||
p_pcr_reg_write(PCR_REG_CHIP_SLEEP_ENABLE, 0);
|
||||
p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE, 0);
|
||||
p_pcr_reg_write(PCR_REG_HOST_SLEEP_ENABLE, 0);
|
||||
p_pcr_reg_write(PCR_REG_EC_SLEEP_ENABLE_2, 0);
|
||||
}
|
||||
|
||||
/** Programs required sleep mode in System Sleep Control Register
|
||||
* @param sleep_mode - see enum SYSTEM_SLEEP_MODES
|
||||
*/
|
||||
void pcr_system_sleep(uint8_t sleep_mode)
|
||||
{
|
||||
p_pcr_system_sleep_ctrl_write(sleep_mode);
|
||||
}
|
||||
|
||||
|
||||
/* end pcr_api.c */
|
||||
/** @}
|
||||
*/
|
||||
@ -0,0 +1,490 @@
|
||||
/*****************************************************************************
|
||||
* © 2015 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
******************************************************************************
|
||||
|
||||
Version Control Information (Perforce)
|
||||
******************************************************************************
|
||||
$Revision: #1 $
|
||||
$DateTime: 2015/11/24 06:28:28 $
|
||||
$Author: amohandas $
|
||||
Last Change: Updated for tabs
|
||||
******************************************************************************/
|
||||
/** @file pcr_perphl.c
|
||||
* \brief Power, Clocks, and Resets Peripheral Source file
|
||||
* \author jvasanth
|
||||
*
|
||||
* This file implements the PCR Peripheral functions
|
||||
******************************************************************************/
|
||||
|
||||
/** @defgroup PCR
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "common_lib.h"
|
||||
#include "pcr.h"
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* Generic functions to program and read 32-bit values from PCR Registers */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/** Writes 32-bit value in the PCR Register
|
||||
* @param pcr_reg_id - pcr register id
|
||||
* @param value - 32-bit value
|
||||
*/
|
||||
void p_pcr_reg_write(uint8_t pcr_reg_id, uint32_t value)
|
||||
{
|
||||
__IO uint32_t *pPCR_Reg;
|
||||
|
||||
pPCR_Reg = (uint32_t *)(PCR_BASE);
|
||||
|
||||
pPCR_Reg += pcr_reg_id;
|
||||
|
||||
*pPCR_Reg = value;
|
||||
}
|
||||
|
||||
/** Reads 32-bit value from the PCR Register
|
||||
* @param pcr_reg_id - pcr register id
|
||||
* @return value - 32-bit value
|
||||
*/
|
||||
uint32_t p_pcr_reg_read(uint8_t pcr_reg_id)
|
||||
{
|
||||
__IO uint32_t *pPCR_Reg;
|
||||
uint32_t retVal;
|
||||
|
||||
pPCR_Reg = (uint32_t *)(PCR_BASE);
|
||||
|
||||
pPCR_Reg += pcr_reg_id;
|
||||
|
||||
retVal = *pPCR_Reg;
|
||||
|
||||
return retVal;
|
||||
}
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* Functions to set, clr and get bits in PCR Registers */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
|
||||
/** Sets bits in a PCR Register
|
||||
* @param pcr_reg_id - pcr register id
|
||||
* @param bit_mask - Bit mask of bits to set
|
||||
*/
|
||||
void p_pcr_reg_set(uint8_t pcr_reg_id, uint32_t bit_mask)
|
||||
{
|
||||
__IO uint32_t *pPCR_Reg;
|
||||
|
||||
pPCR_Reg = (uint32_t *)(PCR_BASE);
|
||||
|
||||
pPCR_Reg += pcr_reg_id;
|
||||
|
||||
*pPCR_Reg |= bit_mask;
|
||||
}
|
||||
|
||||
/** Clears bits in a PCR Register
|
||||
* @param pcr_reg_id - pcr register id
|
||||
* @param bit_mask - Bit mask of bits to clear
|
||||
*/
|
||||
void p_pcr_reg_clr(uint8_t pcr_reg_id, uint32_t bit_mask)
|
||||
{
|
||||
__IO uint32_t *pPCR_Reg;
|
||||
|
||||
pPCR_Reg = (uint32_t *)(PCR_BASE);
|
||||
|
||||
pPCR_Reg += pcr_reg_id;
|
||||
|
||||
*pPCR_Reg &= ~bit_mask;
|
||||
}
|
||||
|
||||
/** Read bits in a PCR Register
|
||||
* @param pcr_reg_id - pcr register id
|
||||
* @param bit_mask - Bit mask of bits to read
|
||||
* @return value - 32-bit value
|
||||
*/
|
||||
uint32_t p_pcr_reg_get(uint8_t pcr_reg_id, uint32_t bit_mask)
|
||||
{
|
||||
__IO uint32_t *pPCR_Reg;
|
||||
uint32_t retVal;
|
||||
|
||||
pPCR_Reg = (uint32_t *)(PCR_BASE);
|
||||
|
||||
pPCR_Reg += pcr_reg_id;
|
||||
|
||||
retVal = (*pPCR_Reg) & bit_mask;
|
||||
|
||||
return retVal;
|
||||
}
|
||||
|
||||
/** Sets or Clears bits in a PCR Register - Helper Function
|
||||
* @param pcr_reg_id - pcr register id
|
||||
* @param bit_mask - Bit mask of bits to set or clear
|
||||
* @param set_clr_flag - Flag to set (1) or clear (0) bits in the PCR Register
|
||||
*/
|
||||
void p_pcr_reg_update(uint8_t pcr_reg_id, uint32_t bit_mask, uint8_t set_clr_flag)
|
||||
{
|
||||
if (set_clr_flag)
|
||||
{
|
||||
p_pcr_reg_set(pcr_reg_id, bit_mask);
|
||||
}
|
||||
else
|
||||
{
|
||||
p_pcr_reg_clr(pcr_reg_id, bit_mask);
|
||||
}
|
||||
}
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* Functions to operate on System Sleep Control Register */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
|
||||
/**
|
||||
* Sets/Clears the Ring oscillator power down bit
|
||||
* in System Sleep Control Register
|
||||
* @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit
|
||||
*/
|
||||
void p_pcr_system_sleep_ctrl_ring_osc_power_down(uint8_t set_clr_flag)
|
||||
{
|
||||
__IO uint32_t *pPCR_Reg;
|
||||
|
||||
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL;
|
||||
|
||||
if (set_clr_flag)
|
||||
{
|
||||
*pPCR_Reg |= PCR_SYS_SLP_CTRL_RING_OSC_PWR_DOWN_BITMASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
*pPCR_Reg &= ~PCR_SYS_SLP_CTRL_RING_OSC_PWR_DOWN_BITMASK;
|
||||
}
|
||||
}
|
||||
|
||||
/** Sets/Clears the Ring oscillator output gate bit
|
||||
* in System Sleep Control Register
|
||||
* @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit
|
||||
*/
|
||||
void p_pcr_system_sleep_ctrl_ring_osc_output_gate(uint8_t set_clr_flag)
|
||||
{
|
||||
__IO uint32_t *pPCR_Reg;
|
||||
|
||||
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL;
|
||||
|
||||
if (set_clr_flag)
|
||||
{
|
||||
*pPCR_Reg |= PCR_SYS_SLP_CTRL_RING_OSC_OUTPUT_GATE_BITMASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
*pPCR_Reg &= ~PCR_SYS_SLP_CTRL_RING_OSC_OUTPUT_GATE_BITMASK;
|
||||
}
|
||||
}
|
||||
|
||||
/** Sets/Clears the Core regulator standby bit
|
||||
* in System Sleep Control Register
|
||||
* @param set_clr_flag - 1 - Sets the bit, 0 - clears the bit
|
||||
*/
|
||||
void p_pcr_system_sleep_ctrl_core_regulator_stdby(uint8_t set_clr_flag)
|
||||
{
|
||||
__IO uint32_t *pPCR_Reg;
|
||||
|
||||
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL;
|
||||
|
||||
if (set_clr_flag)
|
||||
{
|
||||
*pPCR_Reg |= PCR_SYS_SLP_CTRL_CORE_REGLTOR_STDBY_BITMASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
*pPCR_Reg &= ~PCR_SYS_SLP_CTRL_CORE_REGLTOR_STDBY_BITMASK;
|
||||
}
|
||||
}
|
||||
|
||||
/** Writes required sleep mode in System Sleep Control Register
|
||||
* @param sleep_value - System Sleep control value - [D2, D1, D0]
|
||||
*/
|
||||
void p_pcr_system_sleep_ctrl_write(uint8_t sleep_value)
|
||||
{
|
||||
__IO uint32_t *pPCR_Reg;
|
||||
|
||||
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL;
|
||||
|
||||
*pPCR_Reg = (sleep_value & 0x7);
|
||||
}
|
||||
|
||||
/** Reads the System Sleep Control PCR Register
|
||||
* @return value - byte 0 of the system sleep control PCR register
|
||||
*/
|
||||
uint8_t p_pcr_system_sleep_ctrl_read(void)
|
||||
{
|
||||
__IO uint32_t *pPCR_Reg;
|
||||
uint8_t retVal;
|
||||
|
||||
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SYSTEM_SLEEP_CTRL;
|
||||
|
||||
retVal = (uint8_t)((*pPCR_Reg) & 0xFF);
|
||||
|
||||
return retVal;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* Function to program to CLK Divide Value */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
|
||||
/** Writes the clock divide value in the Processor Clock Control Register
|
||||
* @param clk_divide_value - clk divide values, valid values in enum PROCESSOR_CLK_DIVIDE_VALUE
|
||||
*/
|
||||
void p_pcr_processor_clk_ctrl_write(uint8_t clk_divide_value)
|
||||
{
|
||||
__IO uint32_t *pPCR_Reg;
|
||||
|
||||
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PROCESSOR_CLK_CTRL;
|
||||
|
||||
*pPCR_Reg = (clk_divide_value & 0xFF);
|
||||
|
||||
}
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* Function to program the slow clock divide value */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
|
||||
/** Write the slow clock divide value in the Slow Clock Control Register
|
||||
* @param slow_clk_divide_value - slow clk divide value
|
||||
*/
|
||||
void p_pcr_slow_clk_ctrl_write(uint8_t slow_clk_divide_value)
|
||||
{
|
||||
__IO uint32_t *pPCR_Reg;
|
||||
|
||||
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_SLOW_CLK_CTRL;
|
||||
|
||||
*pPCR_Reg = (slow_clk_divide_value & 0x3FF);
|
||||
|
||||
}
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* Function to read the Oscillator Lock Status */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
|
||||
/** Reads the Oscillator Lock status bit in the Oscillator ID Register
|
||||
* @return 1 if Oscillator Lock Status bit is set, else 0
|
||||
*/
|
||||
uint8_t p_pcr_oscillator_lock_sts_get(void)
|
||||
{
|
||||
__IO uint32_t *pPCR_Reg;
|
||||
uint8_t retVal;
|
||||
|
||||
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_OSCILLATOR_ID;
|
||||
|
||||
retVal = 0;
|
||||
if (*pPCR_Reg & PCR_OSCILLATOR_LOCK_STATUS_BITMASK)
|
||||
{
|
||||
retVal = 1;
|
||||
}
|
||||
|
||||
return retVal;
|
||||
|
||||
}
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* Functions to read various power status in Chip Sub-System register */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
|
||||
/** Reads the VCC Reset Status bit
|
||||
* in the Chip Subsystem Power Reset Status Register
|
||||
* @return 1 if VCC Reset Status bit is set, else 0
|
||||
*/
|
||||
uint8_t p_pcr_chip_subsystem_vcc_reset_sts_get(void)
|
||||
{
|
||||
__IO uint32_t *pPCR_Reg;
|
||||
uint8_t retVal;
|
||||
|
||||
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;
|
||||
|
||||
retVal = 0;
|
||||
if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_VCC_RESET_STS_BITMASK)
|
||||
{
|
||||
retVal = 1;
|
||||
}
|
||||
|
||||
return retVal;
|
||||
}
|
||||
|
||||
/** Reads the SIO Reset Status bit
|
||||
* in the Chip Subsystem Power Reset Status Register
|
||||
* @return 1 if SIO Reset Status bit is set, else 0
|
||||
*/
|
||||
uint8_t p_pcr_chip_subsystem_sio_reset_sts_get(void)
|
||||
{
|
||||
__IO uint32_t *pPCR_Reg;
|
||||
uint8_t retVal;
|
||||
|
||||
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;
|
||||
|
||||
retVal = 0;
|
||||
if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_SIO_RESET_STS_BITMASK)
|
||||
{
|
||||
retVal = 1;
|
||||
}
|
||||
|
||||
return retVal;
|
||||
}
|
||||
|
||||
/** Reads the VBAT Reset Status bit
|
||||
* in the Chip Subsystem Power Reset Status Register
|
||||
* @return 1 if VBAT Reset Status bit is set, else 0
|
||||
*/
|
||||
uint8_t p_pcr_chip_subsystem_vbat_reset_sts_get(void)
|
||||
{
|
||||
__IO uint32_t *pPCR_Reg;
|
||||
uint8_t retVal;
|
||||
|
||||
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;
|
||||
|
||||
retVal = 0;
|
||||
if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_VBAT_RESET_STS_BITMASK)
|
||||
{
|
||||
retVal = 1;
|
||||
}
|
||||
|
||||
return retVal;
|
||||
}
|
||||
|
||||
/** Clears the VBAT Reset Status bit
|
||||
* in the Chip Subsystem Power Reset Status Register
|
||||
*/
|
||||
void p_pcr_chip_subsystem_vbat_reset_sts_clr(void)
|
||||
{
|
||||
__IO uint32_t *pPCR_Reg;
|
||||
|
||||
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;
|
||||
|
||||
// Write to clear
|
||||
*pPCR_Reg = PCR_CHIP_SUBSYSTEM_VBAT_RESET_STS_BITMASK;
|
||||
|
||||
}
|
||||
|
||||
/** Reads the VCC1 Reset Status bit
|
||||
* in the Chip Subsystem Power Reset Status Register
|
||||
* @return 1 if VCC1 Reset Status bit is set, else 0
|
||||
*/
|
||||
uint8_t p_pcr_chip_subsystem_vcc1_reset_sts_get(void)
|
||||
{
|
||||
__IO uint32_t *pPCR_Reg;
|
||||
uint8_t retVal;
|
||||
|
||||
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;
|
||||
|
||||
retVal = 0;
|
||||
if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_VCC1_RESET_STS_BITMASK)
|
||||
{
|
||||
retVal = 1;
|
||||
}
|
||||
|
||||
return retVal;
|
||||
}
|
||||
|
||||
/** Clears the VCC1 Reset Status bit
|
||||
* in the Chip Subsystem Power Reset Status Register
|
||||
*/
|
||||
void p_pcr_chip_subsystem_vcc1_reset_sts_clr(void)
|
||||
{
|
||||
__IO uint32_t *pPCR_Reg;
|
||||
|
||||
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;
|
||||
|
||||
// Write to clear
|
||||
*pPCR_Reg = PCR_CHIP_SUBSYSTEM_VCC1_RESET_STS_BITMASK;
|
||||
|
||||
}
|
||||
|
||||
/** Reads the 32K_ACTIVE status bit
|
||||
* in the Chip Subsystem Power Reset Status Register
|
||||
* @return 1 if 32_ACTIVE bit is set, else 0
|
||||
*/
|
||||
uint8_t p_pcr_chip_subsystem_32K_active_sts_get(void)
|
||||
{
|
||||
__IO uint32_t *pPCR_Reg;
|
||||
uint8_t retVal;
|
||||
|
||||
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;
|
||||
|
||||
retVal = 0;
|
||||
if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_32K_ACTIVE_STS_BITMASK)
|
||||
{
|
||||
retVal = 1;
|
||||
}
|
||||
|
||||
return retVal;
|
||||
}
|
||||
|
||||
/** Reads the PCICLK_ACTIVE status bit
|
||||
* in the Chip Subsystem Power Reset Status Register
|
||||
* @return 1 if CICLK_ACTIVE bit is set, else 0
|
||||
*/
|
||||
uint8_t p_pcr_chip_subsystem_pciclk_active_sts_get(void)
|
||||
{
|
||||
__IO uint32_t *pPCR_Reg;
|
||||
uint8_t retVal;
|
||||
|
||||
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_CHIP_SUBSYSTEM_PWR_RESET_STS;
|
||||
|
||||
retVal = 0;
|
||||
if (*pPCR_Reg & PCR_CHIP_SUBSYSTEM_PCICLK_ACTIVE_STS_BITMASK)
|
||||
{
|
||||
retVal = 1;
|
||||
}
|
||||
return retVal;
|
||||
}
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
/* Functions for Power Reset Control Register */
|
||||
/* ---------------------------------------------------------------------- */
|
||||
|
||||
/** Reads the iRESET_OUT bit in the Power Reset Control Register
|
||||
* @return 1 if iRESET_OUT bit is set, else 0
|
||||
*/
|
||||
uint8_t p_pcr_iReset_Out_get(void)
|
||||
{
|
||||
__IO uint32_t *pPCR_Reg;
|
||||
uint8_t retVal;
|
||||
|
||||
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_CTRL;
|
||||
|
||||
retVal = 0;
|
||||
if (*pPCR_Reg & PCR_iRESET_OUT_BITMASK)
|
||||
{
|
||||
retVal = 1;
|
||||
}
|
||||
|
||||
return retVal;
|
||||
|
||||
}
|
||||
|
||||
/** Sets/Clears the iRESET_OUT bit in the Power Reset Control Register
|
||||
* @param 1 Set iRESET_OUT bit; 0 - Clear the bit
|
||||
*/
|
||||
void p_pcr_iReset_Out(uint8_t set_clr_flag)
|
||||
{
|
||||
__IO uint32_t *pPCR_Reg;
|
||||
|
||||
pPCR_Reg = (uint32_t *)(PCR_BASE) + PCR_REG_PWR_RESET_CTRL;
|
||||
|
||||
*pPCR_Reg = (set_clr_flag & 0x1);
|
||||
}
|
||||
|
||||
|
||||
/* end pcr_perphl.c */
|
||||
/** @}
|
||||
*/
|
||||
@ -0,0 +1,390 @@
|
||||
/****************************************************************************
|
||||
* © 2013 Microchip Technology Inc. and its subsidiaries.
|
||||
* You may use this software and any derivatives exclusively with
|
||||
* Microchip products.
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
|
||||
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
|
||||
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
|
||||
* PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
|
||||
* TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
|
||||
* CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
|
||||
* FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
|
||||
* OF THESE TERMS.
|
||||
*/
|
||||
|
||||
/** @defgroup pwm pwm_c_wrapper
|
||||
* @{
|
||||
*/
|
||||
/** @file pwm_c_wrapper.cpp
|
||||
\brief the pwm component C wrapper
|
||||
This program is designed to allow the other C programs to be able to use this component
|
||||
|
||||
There are entry points for all C wrapper API implementation
|
||||
|
||||
<b>Platform:</b> This is ARC-based component
|
||||
|
||||
<b>Toolset:</b> Metaware IDE(8.5.1)
|
||||
<b>Reference:</b> smsc_reusable_fw_requirement.doc */
|
||||
|
||||
/*******************************************************************************
|
||||
* SMSC version control information (Perforce):
|
||||
*
|
||||
* FILE: $File: //depot_pcs/FWEng/Release/projects/CEC1302_CLIB/release2/Source/hw_blks/common/include/platform.h $
|
||||
* REVISION: $Revision: #1 $
|
||||
* DATETIME: $DateTime: 2015/12/23 15:37:58 $
|
||||
* AUTHOR: $Author: akrishnan $
|
||||
*
|
||||
* Revision history (latest first):
|
||||
* #xx
|
||||
***********************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef _PLATFORM_H_
|
||||
#define _PLATFORM_H_
|
||||
#include <stdint.h>
|
||||
/* Platform Configuration PreProcessor Conditions */
|
||||
#define TOOLKEIL 1
|
||||
#define TOOLPC 2
|
||||
#define TOOLMW 3
|
||||
#define TOOLMDK 4
|
||||
|
||||
#define PCLINT 9 //added to satisfy PC Lint's need for a value here
|
||||
|
||||
#ifdef __CC_ARM // Keil ARM MDK
|
||||
#define TOOLSET TOOLMDK
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
#ifdef _WIN32 //always defined by visual c++
|
||||
#define TOOLSET TOOLPC
|
||||
#endif
|
||||
|
||||
#ifdef __WIN32__ //always defined by borland
|
||||
#define TOOLSET TOOLPC
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef _ARC
|
||||
#define TOOLSET TOOLMW // ARC Metaware
|
||||
#endif
|
||||
|
||||
#ifndef TOOLSET
|
||||
#error "ERROR: cfg.h TOOLSET not defined!"
|
||||
#endif
|
||||
|
||||
#if TOOLSET == TOOLMDK
|
||||
#define _KEIL_ARM_ 1 /* Make 1 for Keil MDK Compiler */
|
||||
#define _KEIL_ 0 /* Make 1 for Keil Compiler */
|
||||
#define _PC_ 0
|
||||
#define _ARC_CORE_ 0
|
||||
#endif
|
||||
|
||||
#if TOOLSET == TOOLKEIL
|
||||
#define _KEIL_ARM_ 0
|
||||
#define _KEIL_ 1 /* Make 1 for Keil Compiler */
|
||||
#define _PC_ 0
|
||||
#define _ARC_CORE_ 0
|
||||
#endif
|
||||
|
||||
#if TOOLSET == TOOLPC
|
||||
#define _KEIL_ARM_ 0
|
||||
#define _KEIL_ 0
|
||||
#define _PC_ 1 /* Make 1 for PC Environment */
|
||||
#define _ARC_CORE_ 0
|
||||
#endif
|
||||
|
||||
#if TOOLSET == TOOLMW
|
||||
#define _KEIL_ARM_ 0
|
||||
#define _KEIL_ 0
|
||||
#define _PC_ 0
|
||||
#define _ARC_CORE_ 1
|
||||
#endif
|
||||
|
||||
/* Short form for Standard Data Types */
|
||||
typedef unsigned char UINT8;
|
||||
typedef unsigned short UINT16;
|
||||
typedef unsigned long UINT32;
|
||||
|
||||
typedef volatile unsigned char REG8;
|
||||
|
||||
typedef unsigned char BYTE;
|
||||
typedef unsigned short WORD;
|
||||
typedef unsigned long DWORD;
|
||||
|
||||
typedef unsigned char UCHAR;
|
||||
typedef unsigned short USHORT;
|
||||
typedef unsigned long ULONG;
|
||||
|
||||
typedef unsigned char BOOL;
|
||||
typedef unsigned int UINT;
|
||||
|
||||
/* signed types */
|
||||
typedef signed char INT8;
|
||||
typedef signed short INT16;
|
||||
typedef signed long INT32;
|
||||
|
||||
typedef void VOID;
|
||||
|
||||
/* union types */
|
||||
typedef union _BITS_8
|
||||
{
|
||||
UINT8 byte;
|
||||
struct
|
||||
{
|
||||
UINT8 bit0: 1;
|
||||
UINT8 bit1: 1;
|
||||
UINT8 bit2: 1;
|
||||
UINT8 bit3: 1;
|
||||
UINT8 bit4: 1;
|
||||
UINT8 bit5: 1;
|
||||
UINT8 bit6: 1;
|
||||
UINT8 bit7: 1;
|
||||
}bit;
|
||||
}BITS_8;
|
||||
|
||||
|
||||
/* MACROS FOR Platform Portability */
|
||||
|
||||
/* macro for defining MMCR register */
|
||||
/* add MMCRARRAY() & EXTERNMMCRARRAY() */
|
||||
#if _KEIL_
|
||||
#define MMCR(name,address) volatile unsigned char xdata name _at_ address
|
||||
#define MMCRARRAY(name,length,address) volatile unsigned char xdata name[length] _at_ address
|
||||
#define MMCRTYPE(name,dtype,address) volatile dtype xdata name _at_ address
|
||||
#define EXTERNMMCR(name) extern volatile unsigned char xdata name
|
||||
#define EXTERNMMCRARRAY(name) extern volatile unsigned char xdata name[]
|
||||
#define EXTERNMMCRTYPE(name,dtype) extern volatile dtype xdata name
|
||||
#define SFR(name,address) sfr name = address
|
||||
#define SFRBIT(name,address) sbit name = address
|
||||
#define EXTERNSFR(name)
|
||||
#define BITADDRESSTYPE(name) bit name
|
||||
#define XDATA xdata
|
||||
#define CODE code
|
||||
#define DATA data
|
||||
#define IDATA idata
|
||||
#define INTERRUPT(x) interrupt x
|
||||
#define SET_GLOBAL_INTR_ENABLE() (sfrIE_EAbit = TRUE;)
|
||||
#define CLR_GLOBAL_INTR_ENABLE() (sfrIE_EAbit = FALSE;)
|
||||
#define NULLPTR (char *)(0)
|
||||
#define PLATFORM_TRIM_OSC() // TODO
|
||||
#define PNOP()
|
||||
#define DISABLE_INTERRUPTS() sfrIE_EAbit=0
|
||||
#define ENABLE_INTERRUPTS() sfrIE_EAbit=1
|
||||
#define SAVE_DIS_INTERRUPTS(x) { x=sfrIE_EAbit; sfrIE_EAbit=0; }
|
||||
#define RESTORE_INTERRUPTS(x) { sfrIE_EAbit=x; }
|
||||
#define ATOMIC_CPU_SLEEP()
|
||||
#define NUM_IRQ_VECTORS 12 // DW-8051
|
||||
#define IRQ_VECTOR_SIZE 8
|
||||
#define USE_INLINE_PATCHER 1
|
||||
#define IRQ_VECTABLE_IN_RAM 0
|
||||
#define PLAT_ROM_IRQ_VECTOR_BASE 0x03 // ROM start
|
||||
#define PLAT_IRQ_VECTOR_BASE 0x1003 // RAM start
|
||||
#define FUNC_NEVER_RETURNS
|
||||
#define BEGIN_SMALL_DATA_BLOCK(x)
|
||||
#define END_SMALL_DATA_BLOCK()
|
||||
UINT32 soft_norm(UINT32 val);
|
||||
#define NORM(x) soft_norm(x)
|
||||
//
|
||||
#define USE_FUNC_REPLACEMENT 0
|
||||
#endif
|
||||
|
||||
#if _PC_
|
||||
#define MMCR(name,address) volatile unsigned char name
|
||||
#define MMCRARRAY(name,length,address) volatile unsigned char name[length]
|
||||
#define MMCRTYPE(name,dtype,address) volatile dtype name
|
||||
#define EXTERNMMCR(name) extern volatile unsigned char name
|
||||
#define EXTERNMMCRARRAY(name) extern volatile unsigned char name[]
|
||||
#define EXTERNMMCRTYPE(name,dtype) extern volatile dtype name
|
||||
#define SFR(name,address) volatile unsigned char name
|
||||
#define SFRBIT(name,address) volatile unsigned char name
|
||||
#define EXTERNSFR(name) extern volatile unsigned char name
|
||||
#define BITADDRESSTYPE(name) volatile unsigned char name
|
||||
#define XDATA
|
||||
#define CODE
|
||||
#define DATA
|
||||
#define IDATA
|
||||
#define INTERRUPT(x)
|
||||
#define SET_GLOBAL_INTR_ENABLE() (sfrIE_EAbit = TRUE;)
|
||||
#define CLR_GLOBAL_INTR_ENABLE() (sfrIE_EAbit = FALSE;)
|
||||
#define NULLPTR (char *)(0)
|
||||
#define PLATFORM_TRIM_OSC() // TODO
|
||||
#define PNOP()
|
||||
#define DISABLE_INTERRUPTS()
|
||||
#define ENABLE_INTERRUPTS()
|
||||
#define SAVE_DIS_INTERRUPTS(x)
|
||||
#define RESTORE_INTERRUPTS(x)
|
||||
#define ATOMIC_CPU_SLEEP()
|
||||
#define NUM_IRQ_VECTORS 24
|
||||
#define IRQ_VECTOR_SIZE 8
|
||||
#define USE_INLINE_PATCHER 1
|
||||
#define IRQ_VECTABLE_IN_RAM 0
|
||||
#define FUNC_NEVER_RETURNS
|
||||
#define BEGIN_SMALL_DATA_BLOCK(x)
|
||||
#define END_SMALL_DATA_BLOCK()
|
||||
UINT32 soft_norm(UINT32 val);
|
||||
#define NORM(x) soft_norm(x)
|
||||
//
|
||||
#define USE_FUNC_REPLACEMENT 0
|
||||
#endif
|
||||
|
||||
#if _ARC_CORE_
|
||||
// ARC C has no equivalent operator to specify address of a variable
|
||||
// ARC MMCR's are 32-bit registers
|
||||
#define MMCR(name,address) volatile unsigned char name
|
||||
#define MMCRARRAY(name,length,address) volatile unsigned char name[length]
|
||||
#define MMCRTYPE(name,dtype,address) volatile dtype name
|
||||
#define EXTERNMMCR(name) extern volatile unsigned char name
|
||||
#define EXTERNMMCRARRAY(name) extern volatile unsigned char name[]
|
||||
#define EXTERNMMCRTYPE(name,dtype) extern volatile dtype name
|
||||
#define SFR(name,address) volatile unsigned char name
|
||||
#define SFRBIT(name,address) volatile unsigned char name
|
||||
#define EXTERNSFR(name) extern volatile unsigned char name
|
||||
#define BITADDRESSTYPE(name)
|
||||
#define XDATA
|
||||
#define CODE
|
||||
#define DATA
|
||||
#define IDATA
|
||||
#define INTERRUPT(x)
|
||||
#define SET_GLOBAL_INTR_ENABLE() (_enable())
|
||||
#define CLR_GLOBAL_INTR_ENABLE() (_disable())
|
||||
#define NULLPTR (char *)(0)
|
||||
#define NULLVOIDPTR (void *)(0)
|
||||
#define NULLFPTR (void (*)(void))0
|
||||
#define PLATFORM_TRIM_OSC() // TODO
|
||||
#define PNOP() _nop()
|
||||
#define DISABLE_INTERRUPTS() _disable()
|
||||
#define ENABLE_INTERRUPTS() _enable()
|
||||
#define SAVE_DIS_INTERRUPTS(x) { x=_lr(REG_STATUS32);_flag(x & ~(REG_STATUS32_E1_BIT | REG_STATUS32_E2_BIT));_nop(); }
|
||||
#define RESTORE_INTERRUPTS(x) { _flag((_lr(REG_STATUS32) | (x & (REG_STATUS32_E1_BIT | REG_STATUS32_E2_BIT))));_nop(); }
|
||||
#define ATOMIC_CPU_SLEEP() _flag(6);_sleep();_nop();_nop();
|
||||
#define NUM_IRQ_VECTORS 24
|
||||
#define IRQ_VECTOR_SIZE 8
|
||||
#define USE_INLINE_PATCHER 0
|
||||
#define DCCM_CODE_ALIAS_ADDR 0x00060000
|
||||
#define PLAT_ROM_IRQ_VECTOR_BASE 0
|
||||
#define PLAT_IRQ_VECTOR_BASE (DCCM_CODE_ALIAS_ADDR)
|
||||
/// y #define IRQ_VECTABLE_IN_RAM 1
|
||||
#define IRQ_VECTABLE_IN_RAM 0
|
||||
#define FUNC_NEVER_RETURNS _CC(_NEVER_RETURNS)
|
||||
#define BEGIN_SMALL_DATA_BLOCK(x) #pragma Push_small_data(x)
|
||||
#define END_SMALL_DATA_BLOCK() #pragma Pop_small_data()
|
||||
#define NORM(x) _norm(x)
|
||||
|
||||
#define INLINE_FUNCTION(x) #pragma On_inline(x)
|
||||
|
||||
//
|
||||
#define USE_FUNC_REPLACEMENT 0
|
||||
#endif
|
||||
|
||||
#if _KEIL_ARM_
|
||||
// For ARM MDK compiler
|
||||
// ARM MMCR's are 32-bit registers
|
||||
#define MMCR(name,address) volatile unsigned char name
|
||||
#define MMCRARRAY(name,length,address) volatile unsigned char name[length]
|
||||
#define MMCRTYPE(name,dtype,address) volatile dtype name
|
||||
#define EXTERNMMCR(name) extern volatile unsigned char name
|
||||
#define EXTERNMMCRARRAY(name) extern volatile unsigned char name[]
|
||||
#define EXTERNMMCRTYPE(name,dtype) extern volatile dtype name
|
||||
#define SFR(name,address) volatile unsigned char name
|
||||
#define SFRBIT(name,address) volatile unsigned char name
|
||||
#define EXTERNSFR(name) extern volatile unsigned char name
|
||||
#define BITADDRESSTYPE(name)
|
||||
#define XDATA
|
||||
#define CODE
|
||||
#define DATA
|
||||
#define IDATA
|
||||
#define INTERRUPT(x)
|
||||
#define SET_GLOBAL_INTR_ENABLE() (__enable_irq())
|
||||
#define CLR_GLOBAL_INTR_ENABLE() (__disable_irq())
|
||||
#define NULLPTR (char *)(0)
|
||||
#define NULLVOIDPTR (void *)(0)
|
||||
#define NULLFPTR (void (*)(void))0
|
||||
#define PLATFORM_TRIM_OSC() // TODO
|
||||
#define PNOP() __NOP()
|
||||
#define DISABLE_INTERRUPTS() __disable_irq()
|
||||
#define ENABLE_INTERRUPTS() __enable_irq()
|
||||
#define ATOMIC_CPU_SLEEP() __wfi();__nop();__nop();
|
||||
|
||||
#if 0 /* need further efforts if needed */
|
||||
#define SAVE_DIS_INTERRUPTS(x) { x=_lr(REG_STATUS32);_flag(x & ~(REG_STATUS32_E1_BIT | REG_STATUS32_E2_BIT));_nop(); }
|
||||
#define RESTORE_INTERRUPTS(x) { _flag((_lr(REG_STATUS32) | (x & (REG_STATUS32_E1_BIT | REG_STATUS32_E2_BIT))));_nop(); }
|
||||
#define NUM_IRQ_VECTORS 24
|
||||
#define IRQ_VECTOR_SIZE 8
|
||||
#define USE_INLINE_PATCHER 0
|
||||
#define DCCM_CODE_ALIAS_ADDR 0x00060000
|
||||
#define PLAT_ROM_IRQ_VECTOR_BASE 0
|
||||
#define PLAT_IRQ_VECTOR_BASE (DCCM_CODE_ALIAS_ADDR)
|
||||
/// y #define IRQ_VECTABLE_IN_RAM 1
|
||||
#define IRQ_VECTABLE_IN_RAM 0
|
||||
#define BEGIN_SMALL_DATA_BLOCK(x) #pragma Push_small_data(x)
|
||||
#define END_SMALL_DATA_BLOCK() #pragma Pop_small_data()
|
||||
#define INLINE_FUNCTION(x) #pragma On_inline(x)
|
||||
#define USE_FUNC_REPLACEMENT 0
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
#define FUNC_NEVER_RETURNS _CC(_NEVER_RETURNS)
|
||||
#define NORM(x) _norm(x)
|
||||
#else
|
||||
/* for ARM MDK */
|
||||
#define FUNC_NEVER_RETURNS
|
||||
UINT32 soft_norm(UINT32 val);
|
||||
#define NORM(x) soft_norm(x)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* General Constants */
|
||||
#define FALSE 0x00
|
||||
#define TRUE !FALSE
|
||||
|
||||
#define BIT_n_MASK(n) (1U << (n))
|
||||
#define BIT_0_MASK (1<<0)
|
||||
#define BIT_1_MASK (1<<1)
|
||||
#define BIT_2_MASK (1<<2)
|
||||
#define BIT_3_MASK (1<<3)
|
||||
#define BIT_4_MASK (1<<4)
|
||||
#define BIT_5_MASK (1<<5)
|
||||
#define BIT_6_MASK (1<<6)
|
||||
#define BIT_7_MASK (1<<7)
|
||||
#define BIT_8_MASK ((UINT16)1<<8)
|
||||
#define BIT_9_MASK ((UINT16)1<<9)
|
||||
#define BIT_10_MASK ((UINT16)1<<10)
|
||||
#define BIT_11_MASK ((UINT16)1<<11)
|
||||
#define BIT_12_MASK ((UINT16)1<<12)
|
||||
#define BIT_13_MASK ((UINT16)1<<13)
|
||||
#define BIT_14_MASK ((UINT16)1<<14)
|
||||
#define BIT_15_MASK ((UINT16)1<<15)
|
||||
#define BIT_16_MASK ((UINT32)1<<16)
|
||||
#define BIT_17_MASK ((UINT32)1<<17)
|
||||
#define BIT_18_MASK ((UINT32)1<<18)
|
||||
#define BIT_19_MASK ((UINT32)1<<19)
|
||||
#define BIT_20_MASK ((UINT32)1<<20)
|
||||
#define BIT_21_MASK ((UINT32)1<<21)
|
||||
#define BIT_22_MASK ((UINT32)1<<22)
|
||||
#define BIT_23_MASK ((UINT32)1<<23)
|
||||
#define BIT_24_MASK ((UINT32)1<<24)
|
||||
#define BIT_25_MASK ((UINT32)1<<25)
|
||||
#define BIT_26_MASK ((UINT32)1<<26)
|
||||
#define BIT_27_MASK ((UINT32)1<<27)
|
||||
#define BIT_28_MASK ((UINT32)1<<28)
|
||||
#define BIT_29_MASK ((UINT32)1<<29)
|
||||
#define BIT_30_MASK ((UINT32)1<<30)
|
||||
#define BIT_31_MASK ((UINT32)1<<31)
|
||||
|
||||
|
||||
/* For CEC application */
|
||||
#define ON 1
|
||||
#define OFF 0
|
||||
|
||||
#endif /*_PLATFORM_H_*/
|
||||
|
||||
/** @}
|
||||
*/
|
||||
|
||||
Loading…
Reference in New Issue