Removed file/folder
Richard Barry
19 years ago
parent
f3bfa0b050
commit
416c6b9791
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/*
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********************************************************************************
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* TERN, Inc.
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* (c) Copyright 2005, http://www.tern.com
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*
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* - Created to support i2chip module on a variety of TERN hardware platforms.
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********************************************************************************
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*/
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#include <embedded.h>
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#include "i2chip_hw.h"
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#ifdef I2CHIP_MMC
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#include "mmc.h"
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#endif
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void i2chip_init(void)
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{
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#ifdef TERN_586
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/*
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poke(MMCR,_BOOTCSCTL_,peek(MMCR,_BOOTCSCTL_)&0xffc9); // ROM 1 wait
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poke(MMCR,_ROMCS2CTL_,peek(MMCR,_ROMCS2CTL_)&0xffc8); // SRAM 0 wait
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pokeb(MMCR, _GPCSRT_, 24); // set the GP CS recovery time, 12 works
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pokeb(MMCR, _GPCSPW_, 128); // set the GP CS width, 64 works
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pokeb(MMCR, _GPCSOFF_, 16); // set the GP CS offset, 8 works
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pokeb(MMCR, _GPRDW_, 80); // set the GP RD pulse width, 50 works
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pokeb(MMCR, _GPRDOFF_, 30); // set the GP RD offset, 15 works
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pokeb(MMCR, _GPWRW_, 80); // set the GP WR pulse width, 50
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pokeb(MMCR, _GPWROFF_, 30); // set the GP WR offset, 15
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*/
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#ifdef TERN_5E
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pokeb(MMCR, _GPCSDW_, peekb(MMCR, _GPCSDW_)&0xf7); // set /CS3-/CSM Data Width=8
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pokeb(MMCR, _CSPFS_, peekb(MMCR, _CSPFS_)|0x08); // set the GP CS3 PIN Function
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poke(MMCR, _PAR15_, 0x2000); // set CS3 I/O region
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poke(MMCR, _PAR15_+2, 0x2dff); // set CS3 I/O region, 512 bytes
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pokeb(MMCR, _GPCSDW_, peekb(MMCR, _GPCSDW_)&0x7f); // CS7=J4.3 Data Width=8, /CSI
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// pokeb(MMCR, _GPCSDW_, peekb(MMCR, _GPCSDW_)|0x80); // CS7=J4.3 Data Width=16
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pokeb(MMCR, _CSPFS_, peekb(MMCR, _CSPFS_)|0x80); // set the GP CS7 PIN Function
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poke(MMCR, _PAR7_, 0x4000); // set CS7 I/O region
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poke(MMCR, _PAR7_+2, 0x3dff); // set CS7 I/O region, 512 bytes
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#else
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// If it's not 5E, then it must be 5P... in which case, we use PCS0 and
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// PCS1 as the chip-selects.
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pokeb(MMCR, _GPCSDW_, peekb(MMCR, _GPCSDW_)&0xfe); // CS0 Data Width=8
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poke(MMCR, _PIOPFS31_16_, peek(MMCR,_PIOPFS31_16_)|0x0800); // P27=/CS0
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poke(MMCR, _PAR13_, 0x1800); // CS0 I/O region
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poke(MMCR, _PAR13_+2, 0x21ff); // CS0 I/O RW, 512 bytes, start 0x1800
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#endif
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a HLPRsetvect(0x47, (void far *) spu_m_isr);
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HLPRsetvect(0x4f, (void far *) spu_1_isr);
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HLPRsetvect(0x57, (void far *) spu_2_isr);
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#endif // 186, or RE
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#ifdef TERN_186
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pio_init(18, 0); // P18=CTS1 for /PCS2
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#ifdef TERN_16_BIT
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outport(0xfff2, 2); // AUXCON, MCS, Bus 16-bit
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#endif
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#ifdef I2CHIP_MCS_DIRECT
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outport(0xffa0,0xc0bf); // UMCS, 256K ROM, disable AD15-0
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outport(0xfff0,inport(0xfff0)|0x4000 ); // SYSCON, MCS0 0x80000-0xbffff
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outport(0xffa8,0xa0bf ); // MPCS, MCS0=P14, 64KB, PCS I/O,
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outport(0xffa6,0x81ff); // MMCS, base 0x80000,
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outport(0xffa2,0x7fbf); // 512K RAM,
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outport(0xffa4,0x007d); // PACS, base 0,
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#else
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outport( 0xffa0,0xc0bf); // UMCS, 256K ROM, 3 wait, disable AD15-0
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outport( 0xfff0,inport(0xfff0)|0x4000 ); // SYSCON, MCS0 0x80000-0xbffff
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// outport( 0xffa8,0xa0bc ); // MPCS, MCS0=P14, 64KB, PCS I/O 0 wait
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// outport( 0xffa8,0xa0bd ); // MPCS, MCS0=P14, 64KB, PCS I/O 1 wait
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outport( 0xffa8,0xa0bf ); // MPCS, MCS0=P14, 64KB, PCS I/O 1 wait
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#endif // I2CHIP_MCS_DIRECT
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#ifndef TERN_RE // 80 MHz R- boards can't tolerate zero wait state.
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outport( 0xffa6,0x81ff ); // MMCS, base 0x80000
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outport(0xffa2,0x7fbe); // 512K RAM, 0 wait states
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outport(0xffa4,0x007d); // PACS, base 0, 0 wait
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#endif
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pio_init(14,0); // Enable /MCS0
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#endif // TERN_186
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#ifdef I2CHIP_WINDOW
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#ifdef I2CHIP_SHIFTED_ADDRESS
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pio_init(12, 2); // Configure P12 as A7, an output we'll be using.
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pio_wr(12, 0); // Set A7 low, initially.
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#endif
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WINDOW_RESTORE_BASE; // Equivalent to calling mmc_window(7, 0);
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#endif
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}
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#ifdef I2CHIP_WINDOW
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void i2chip_set_page(u_int page)
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{
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u_int new_page = page;
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#ifdef I2CHIP_SHIFTED_ADDRESS
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if (page & 0x01) // ... we're checking the right-most bit in the page.
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outport(0xff74, inport(0xff74) | 0x1000 ); // Using P12 as A7...
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else
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outport(0xff74, inport(0xff74) & 0xefff );
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new_page = page >> 1;
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#endif
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#ifdef I2CHIP_MMC
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mmc_window(7, new_page); // See mmc.c
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#endif
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#ifdef I2CHIP_P51
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p51_window(new_page);
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#endif
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}
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static u_int s_addr = 0xffff;
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u_char far* i2chip_mkptr(u_int addr)
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{
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if ((s_addr & 0xff00) == (addr & 0xff00)) // No point... no point...
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return MK_FP(WINDOW_BASE_SEGM, addr & 0xff);
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s_addr = addr ;
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// So the argument to this function is... what again?
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// I think it should be the highest 16-bits... or, in other words,
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// FP_SEG of a huge ptr.
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// Ok, and the *return* value should be a UINT value for the new
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// segment address to be used, if it's at all needed. TODO
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I2CHIP_SET_PAGE(s_addr >> 8); // Portable version
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// outportb(0x00, addr>>8); // quicker version
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return MK_FP(WINDOW_BASE_SEGM, addr & 0xff);
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}
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void i2chip_set_window(u_int window_addr)
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{
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s_addr = window_addr;
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I2CHIP_SET_PAGE(s_addr >> 8);
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}
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// Still inside #define I2CHIP_WINDOW ...
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u_int i2chip_get_window(void)
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{
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return s_addr & 0xff00;
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}
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void i2chip_push_window(u_int addr)
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{
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I2CHIP_SET_PAGE(addr>>8);
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}
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void i2chip_pop_window(void)
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{
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I2CHIP_SET_PAGE(s_addr >> 8);
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}
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#ifdef I2CHIP_WINDOW_IO
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u_char io_read_value(u_char far* addr)
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{
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// return value ... we assume the page is already set. So, instead,
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// we just go ahead and output valeu.
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return inportb(I2CHIP_BASE_SEG + (FP_OFF(addr) & 0xff));
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}
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void io_write_value(u_char far* addr, u_char value)
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{
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// Get the last whatever bytes... and write value.
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outportb(I2CHIP_BASE_SEG + (FP_OFF(addr) & 0xff), value);
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}
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#endif // I2CHIP_WINDOW_IO
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#ifdef I2CHIP_P51
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void p51_window(unsigned int page)
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{
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asm xor ax, ax
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asm mov ax, page
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#ifdef I2CHIP_WINDOW_IO
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asm mov dx, 1040h
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asm out dx, al
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#else
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asm out 040h, al
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#endif
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// use J1.19=/CS6
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}
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#endif // I2CHIP_P51
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#endif // I2CHIP_WINDOW
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#ifdef TERN_586
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/*
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// Function: spu_m_isr
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// P22=Master PIC IR7, interrupt vector=0x47, /INTA
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*/
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void interrupt far spu_m_isr(void)
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{
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disable();
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// Issue the EOI to interrupt controller
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outportb(_MPICOCW2_IO,0x67); // Specific EQI for master IR7
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enable();
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}
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/*
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// Function: spu_1_isr
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// P10=slave1 PIC IR7, Master IR2, interrupt vector=0x4f, /INTC
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*/
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void interrupt far spu_1_isr(void)
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{
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disable();
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// Issue the EOI to interrupt controller
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outportb(_S1PICOCW2_IO,0x67); // Specific EOI for slave 1 IR7
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outportb(_MPICOCW2_IO,0x62); // Specific EQI for master IR2
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enable();
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}
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/*
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// Function: spu_2_isr
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// P20=Slave2 PIC IR7, Master IR5, interrupt vector=0x57, GPIRQ7=PIO16 GP timer1
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*/
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void interrupt far spu_2_isr(void)
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{
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disable();
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// Issue the EOI to interrupt controller
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outportb(_S2PICOCW2_IO,0x67); // Specific EOI for slave 1 IR7
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outportb(_MPICOCW2_IO,0x65); // Specific EQI for master IR5
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enable();
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}
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#endif
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