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Update to V4.0.4. Add in STR912 port and demo.

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pull/4/head
Richard Barry 19 years ago
parent 05023971cb
commit 3dcbed5763
445 changed files with 30007 additions and 331 deletions
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2
Demo/ARM7_AT91FR40008_GCC/FreeRTOSConfig.h
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/*
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/ARM7_AT91FR40008_GCC/Makefile
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# FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
# FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
#
# This file is part of the FreeRTOS.org distribution.
#

2
Demo/ARM7_AT91FR40008_GCC/ParTest/ParTest.c
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/*
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/ARM7_AT91FR40008_GCC/main.c
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/*
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/ARM7_AT91FR40008_GCC/serial/serial.c
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/*
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/ARM7_AT91FR40008_GCC/serial/serialISR.c
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/*
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/ARM7_AT91SAM7S64_IAR/FreeRTOSConfig.h
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/*
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/ARM7_AT91SAM7S64_IAR/ParTest/ParTest.c
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/*
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/ARM7_AT91SAM7S64_IAR/USB/USBSample.c
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/*
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/ARM7_AT91SAM7S64_IAR/main.c
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/*
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/ARM7_AT91SAM7S64_IAR/serial/serial.c
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/*
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/ARM7_LPC2106_GCC/FreeRTOSConfig.h
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/*
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/ARM7_LPC2106_GCC/Makefile
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# FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
# FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
#
# This file is part of the FreeRTOS.org distribution.
#

2
Demo/ARM7_LPC2106_GCC/ParTest/ParTest.c
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/*
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/ARM7_LPC2106_GCC/main.c
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/*
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/ARM7_LPC2106_GCC/serial/serial.c
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/*
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/ARM7_LPC2106_GCC/serial/serialISR.c
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/*
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/ARM7_LPC2129_IAR/FreeRTOSConfig.h
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/*
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/ARM7_LPC2129_IAR/ParTest/ParTest.c
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/*
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/ARM7_LPC2129_IAR/main.c
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/*
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/ARM7_LPC2129_IAR/serial/serial.c
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/*
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/ARM7_LPC2129_Keil/FreeRTOSConfig.h
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/*
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/ARM7_LPC2129_Keil/ParTest/ParTest.c
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/*
FreeRTOS.org V4.0.3 - copyright (C) 2003-2006 Richard Barry.
FreeRTOS.org V4.0.4 - copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/ARM7_LPC2129_Keil/main.c
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/*
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/ARM7_LPC2129_Keil/serial/serial.c
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/*
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/ARM7_LPC2129_Keil/serial/serialISR.c
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/*
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/ARM7_STR71x_IAR/FreeRTOSConfig.h
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/*
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/ARM7_STR71x_IAR/ParTest/ParTest.c
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/*
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/ARM7_STR71x_IAR/main.c
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/*
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/ARM7_STR71x_IAR/serial/serial.c
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/*
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.

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Demo/ARM9_STR91X_IAR/91x_init_IAR.s
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;******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
;* File Name : 91x_init.s
;* Author : MCD Application Team
;* Date First Issued : 05/18/2006 : Version 1.0
;* Description : This module performs:
;* - FLASH/RAM initialization,
;* - Stack pointer initialization for each mode ,
;* - Branches to ?main in the C library (which eventually
;* calls main()).
;*
;* On reset, the ARM core starts up in Supervisor (SVC) mode,
;* in ARM state,with IRQ and FIQ disabled.
;*******************************************************************************
; History:
; 05/24/2006 : Version 1.1
; 05/18/2006 : Version 1.0
;*******************************************************************************
;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
;* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
;* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
;* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
;* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
;* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;******************************************************************************/
; Depending in Your Application, Disable or Enable the following Define
; #define BUFFERED_Mode ; Work on Buffered mode, when enabling this define
; just enable the Buffered define on 91x_conf.h
; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs
Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UND EQU 0x1B
Mode_SYS EQU 0x1F ; available on ARM Arch 4 and later
I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
;--- BASE ADDRESSES
; System memory locations
SRAM_Base EQU 0x04000000
SRAM_Limit EQU 0x04018000 ; at the top of 96 KB SRAM
SVC_Stack DEFINE SRAM_Limit ; 512 byte SVC stack at
; top of memory - used by kernel.
IRQ_Stack DEFINE SVC_Stack-512 ; followed by IRQ stack
USR_Stack DEFINE IRQ_Stack-512 ; followed by USR stack. Tasks run in
; system mode but task stacks are allocated
; when the task is created.
FIQ_Stack DEFINE USR_Stack-8 ; followed by FIQ stack
ABT_Stack DEFINE FIQ_Stack-8 ; followed by ABT stack
UND_Stack DEFINE ABT_Stack-8 ; followed by UNDEF stack
EXTERN main
; STR9X register specific definition
FMI_BBSR_AHB_UB EQU 0x54000000
FMI_BBADR_AHB_UB EQU 0x5400000C
FMI_NBBSR_AHB_UB EQU 0x54000004
FMI_NBBADR_AHB_UB EQU 0x54000010
SCU_SCRO_APB1_UB EQU 0x4C002034
SCRO_AHB_UNB EQU 0x5C002034
;---------------------------------------------------------------
; ?program_start
;---------------------------------------------------------------
MODULE ?program_start
RSEG ICODE:CODE(2)
IMPORT LINK
PUBLIC __program_start
EXTERN ?main
CODE32
__program_start:
LDR pc, =NextInst
NextInst
NOP ; execute some instructions to access CPU registers after wake
NOP ; up from Reset, while waiting for OSC stabilization
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ldr r0,=LINK ; to include the vector table inside the final executable.
; --- Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000,
; when the bank 0 is the boot bank, then enable the Bank 1.
LDR R6, =0x54000000
LDR R7, =0x4
STR R7, [R6]
LDR R6, =0x54000004
LDR R7, =0x3
STR R7, [R6]
LDR R6, =0x5400000C
LDR R7, =0x0
STR R7, [R6]
LDR R6, =0x54000010
LDR R7, =0x20000
STR R7, [R6]
LDR R6, =0x54000018
LDR R7, =0x18
STR R7, [R6]
; --- Enable 96K RAM
LDR R0, = SCRO_AHB_UNB
LDR R1, = 0x0196
STR R1, [R0]
/* Setup a stack for each mode - note that this only sets up a usable stack
for system/user, SWI and IRQ modes. Also each mode is setup with
interrupts initially disabled. */
MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit ; No interrupts
LDR SP, =FIQ_Stack
MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit ; No interrupts
LDR SP, =IRQ_Stack
MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit ; No interrupts
LDR SP, =ABT_Stack
MSR CPSR_c, #Mode_UND|I_Bit|F_Bit ; No interrupts
LDR SP, =UND_Stack
MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit ; No interrupts
LDR SP, =SVC_Stack
MSR CPSR_c, #Mode_SYS|I_Bit|F_Bit ; No interrupts
LDR SP, =USR_Stack
/* We want to start in supervisor mode. Operation will switch to system
mode when the first task starts. */
MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit
; --- Set bits 17-18 of the Core Configuration Control Register
MOV r0, #0x60000
MCR p15,0x1,r0,c15,c1,0
; --- Now enter the C code
B ?main ; Note : use B not BL, because an application will
; never return this way
LTORG
END
;******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****

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Demo/ARM9_STR91X_IAR/91x_vect_IAR.s
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;******************** (C) COPYRIGHT 2005 STMicroelectronics ********************
;* File Name : 91x_vect.s
;* Author : MCD Application Team
;* Date First Issued : 10/25/2005 : Beta Version V0.1
;* Description : This File used to initialize the exception and IRQ
;* vectors, and to enter/return to/from exceptions
;* handlers.
;*******************************************************************************
; History:
; 10/25/2005 : Beta Version V0.1
;*******************************************************************************
; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
; CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
; A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
; OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
; OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
; CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;******************************************************************************/
#include "FreeRTOSConfig.h"
#include "ISR_Support.h"
MODULE ?RESET
COMMON INTVEC:CODE(2)
CODE32
EXPORT LINK
VectorAddress EQU 0xFFFFF030 ; VIC Vector address register address.
VectorAddressDaisy EQU 0xFC000030 ; Daisy VIC Vector address register
; address.
LINK EQU 0x0
I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
;*******************************************************************************
; MACRO
;*******************************************************************************
;*******************************************************************************
; Import the __program_start address from 91x_init.s
;*******************************************************************************
IMPORT __program_start
;*******************************************************************************
; Import exception handlers
;*******************************************************************************
IMPORT vPortYieldProcessor ; FreeRTOS SWI handler
;*******************************************************************************
; Export Peripherals IRQ handlers table address
;*******************************************************************************
;*******************************************************************************
; Exception vectors
;*******************************************************************************
LDR PC, Reset_Addr
LDR PC, Undefined_Addr
LDR PC, SWI_Addr
LDR PC, Prefetch_Addr
LDR PC, Abort_Addr
NOP ; Reserved vector
LDR PC, IRQ_Addr
LDR PC, FIQ_Addr
;*******************************************************************************
; Exception handlers address table
;*******************************************************************************
Reset_Addr DCD __program_start
Undefined_Addr DCD UndefinedHandler
SWI_Addr DCD vPortYieldProcessor
Prefetch_Addr DCD PrefetchAbortHandler
Abort_Addr DCD DataAbortHandler
DCD 0 ; Reserved vector
IRQ_Addr DCD IRQHandler
FIQ_Addr DCD FIQHandler
;*******************************************************************************
; Exception Handlers
;*******************************************************************************
; - NOTE -
; The IRQ and SWI handlers are the only managed exception.
UndefinedHandler
b UndefinedHandler
PrefetchAbortHandler
b PrefetchAbortHandler
DataAbortHandler
b DataAbortHandler
FIQHandler
b FIQHandler
DefaultISR
b DefaultISR
;*******************************************************************************
;* Function Name : IRQHandler
;* Description : This function called when IRQ exception is entered.
;* Input : none
;* Output : none
;*******************************************************************************
IRQHandler
portSAVE_CONTEXT ; Save the context of the current task.
LDR r0, = VectorAddress
LDR r0, [r0] ; Read the routine address
LDR r1, = VectorAddressDaisy
LDR r1, [r1]
MOV lr, pc
bx r0
LDR r0, = VectorAddress ; Write to the VectorAddress to clear the
STR r0, [r0] ; respective interrupt in the internal interrupt
LDR r1, = VectorAddressDaisy ; Write to the VectorAddressDaisy to clear the
STR r1,[r1] ; respective interrupt in the internal interrupt
portRESTORE_CONTEXT ; Restore the context of the selected task.
LTORG
END
;******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****

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Demo/ARM9_STR91X_IAR/FreeRTOSConfig.h
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/*
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 96000000 )
#define configCPU_PERIPH_HZ ( ( unsigned portLONG ) 96000000 )
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )
#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 180 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) 50000 )
#define configMAX_TASK_NAME_LEN ( 16 )
#define configUSE_TRACE_FACILITY 1
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#endif /* FREERTOS_CONFIG_H */

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Demo/ARM9_STR91X_IAR/Library/include/91x_ahbapb.h
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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_ahbapb.h
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : This file contains all the functions prototypes for the
* AHBAPB software library.
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _91x_AHBAPB_H
#define _91x_AHBAPB_H
#include "91x_map.h"
#define AHBAPB_Split_Enable 0x01000000
#define AHBAPB_Split_Disable 0xFEFFFFFF
#define AHBAPB_Error_Enable 0x0000100
#define AHBAPB_Error_Disable 0xFFFFEFF
/*FLAG*/
#define AHBAPB_FLAG_ERROR 0x01 /* error flag*/
#define AHBAPB_FLAG_OUTM 0x10 /* Out of Memory flag */
#define AHBAPB_FLAG_APBT 0x20 /* APB Time-out flag */
#define AHBAPB_FLAG_RW 0x40 /*Access type flag*/
/* Includes ------------------------------------------------------------------*/
/* AHBAPB Init structure definition */
typedef struct
{
u32 AHBAPB_SetTimeOut;
u32 AHBAPB_Error;
u32 AHBAPB_Split;
u8 AHBAPB_SplitCounter;
}AHBAPB_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
void AHBAPB_DeInit(AHBAPB_TypeDef* AHBAPBx);
void AHBAPB_Init(AHBAPB_TypeDef* AHBAPBx, AHBAPB_InitTypeDef* AHBAPB_InitStruct);
void AHBAPB_StructInit(AHBAPB_InitTypeDef* AHBAPB_InitStruct);
FlagStatus AHBAPB_GetFlagStatus(AHBAPB_TypeDef* AHBAPBx, u8 AHBAPB_FLAG);
void AHBAPB_ClearFlag(AHBAPB_TypeDef* AHBAPBx, u8 AHBAPB_FLAG);
u32 AHBAPB_GetPeriphAddrError(AHBAPB_TypeDef* AHBAPBx);
#endif /* _91x_AHBAPB_H */
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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Demo/ARM9_STR91X_IAR/Library/include/91x_conf.h
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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_conf.h
* Author : MCD Application Team
* Date First Issued : 03/31/2006 : Beta Version V0.1
* Description : Library configuration.
********************************************************************************
* History:
* 03/31/2006 : Beta Version V0.1
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#ifndef __91x_CONF_H
#define __91x_CONF_H
/* To work in buffered mode just decomment the following line */
//#define Buffered
/* Comment the line below to put the library in release mode */
//#ifndef inline
// #define inline inline
//#endif
/************************* AHBAPB *************************/
#define _AHBAPB
#define _AHBAPB0
#define _AHBAPB1
/************************* VIC *************************/
#define _VIC
#define _VIC0
#define _VIC1
/************************* DMA *************************/
//#define _DMA
//#define _DMA_Channel0
//#define _DMA_Channel1
//#define _DMA_Channel2
//#define _DMA_Channel3
//#define _DMA_Channel4
//#define _DMA_Channel5
//#define _DMA_Channel6
//#define _DMA_Channel7
/************************* EMI *************************/
//#define _EMI
//#define _EMI_Bank0
//#define _EMI_Bank1
//#define _EMI_Bank2
//#define _EMI_Bank3
/************************* FMI *************************/
#define _FMI
/************************* WIU *************************/
//#define _WIU
/************************* TIM *************************/
//#define _TIM
//#define _TIM0
//#define _TIM1
//#define _TIM2
//#define _TIM3
/************************* GPIO ************************/
#define _GPIO
#define _GPIO0
#define _GPIO1
#define _GPIO2
#define _GPIO3
#define _GPIO4
#define _GPIO5
#define _GPIO6
#define _GPIO7
#define _GPIO8
#define _GPIO9
/************************* RTC *************************/
//#define _RTC
/************************* SCU *************************/
#define _SCU
/************************* MC **************************/
//#define _MC
/************************* UART ************************/
#define _UART
//#define _UART0
#define _UART1
//#define _UART2
/************************* SSP *************************/
//#define _SSP
//#define _SSP0
//#define _SSP1
/************************* CAN *************************/
//#define _CAN
/************************* ADC *************************/
//#define _ADC
/************************* WDG *************************/
#define _WDG
/************************* I2C *************************/
//#define _I2C
//#define _I2C0
//#define _I2C1
/************************ ENET *************************/
#define _ENET
/************************ DENET ************************/
//#define _DENET
/*---------------------------- _Main_Crystal frequency value (KHz)------------*/
#ifndef _Main_Crystal
#define _Main_Crystal 25000
#endif
/*------------------------------------------------------------------------------*/
#endif /* __91x_CONF_H */
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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Demo/ARM9_STR91X_IAR/Library/include/91x_dma.h
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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : template.h
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : provide a short description of the source file indicating
* its purpose.
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __91x_DMA_H
#define __91x_DMA_H
/* Includes ------------------------------------------------------------------*/
#include"91x_map.h"
/* Exported types ------------------------------------------------------------*/
typedef struct
{
u32 DMA_Channel_SrcAdd; /* The current source address (byte-aligned) of the data to be transferred.*/
u32 DMA_Channel_DesAdd; /* The current destination address (byte-aligned) of the data to be transferred.*/
u32 DMA_Channel_LLstItm; /* The word- aligned address for the next Linked List Item. */
u32 DMA_Channel_DesWidth; /* Destination transfer width. */
u32 DMA_Channel_SrcWidth; /* Source transfer width. */
u32 DMA_Channel_DesBstSize; /* The destination burst size which indicates the number of transfers that make up a destination burst transfer request.*/
u32 DMA_Channel_SrcBstSize; /* The source burst size.Indicates the number of transfers that make up a source burst */
u32 DMA_Channel_TrsfSize; /* Transfer size which indicates the size of the transfer when the DMA controller is the flow controller*/
u32 DMA_Channel_FlowCntrl; /* Flow control and transfer type. */
u32 DMA_Channel_Src; /* Source peripheral: selects the DMA source request peripheral. */
u32 DMA_Channel_Des; /* Destination peripheral:selects the DMA destination request peripheral. */
} DMA_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/* Interrupts masks */
#define DMA_ITMask_IE 0x4000 /* Interrupt error mask. */
#define DMA_ITMask_ITC 0x8000 /* Terminal count interrupt mask.*/
#define DMA_ITMask_ALL 0xC000 /* All DMA_Channelx interrupts enable/disable mask*/
/* Sources Request (used as masks) */
#define DMA_USB_RX_Mask 0x0001
#define DMA_USB_TX_Mask 0x0002
#define DMA_TIM0_Mask 0x0004
#define DMA_TIM1_Mask 0x0008
#define DMA_UART0_RX_Mask 0x0010
#define DMA_UART0_TX_Mask 0x0020
#define DMA_UART1_RX_Mask 0x0040
#define DMA_UART1_TX_Mask 0x0080
#define DMA_External_Req0_Mask 0x0100
#define DMA_External_Req1_Mask 0x0200
#define DMA_I2C0_Mask 0x0400
#define DMA_I2C1_Mask 0x0800
#define DMA_SSP0_RX_Mask 0x1000
#define DMA_SSP0_TX_Mask 0x2000
#define DMA_SSP1_RX_Mask 0x4000
#define DMA_SSP1_TX_Mask 0x8000
/* Previleged Mode and user mode */
#define DMA_PrevilegedMode 0x10000000
#define DMA_UserMode 0xEFFFFFFF
/* Error and Terminal Count interrupts Status, after and before"raw" masking */
#define DMA_IS 0x01
#define DMA_TCS 0x02
#define DMA_ES 0x03
#define DMA_TCRS 0x04
#define DMA_ERS 0x05
/* interrupt clear: Terminal Count flag Clear and Error flag clear*/
#define DMA_TCC 0x01
#define DMA_EC 0x02
/* channel index "0...7"*/
#define Channel0 0
#define Channel1 1
#define Channel2 2
#define Channel3 3
#define Channel4 4
#define Channel5 5
#define Channel6 6
#define Channel7 7
/* Destination request selection: selects the DMA Destination request peripheral */
#define DMA_DES_USB_RX 0x00
#define DMA_DES_USB_TX 0x40
#define DMA_DES_TIM1 0x80
#define DMA_DES_TIM2 0xC0
#define DMA_DES_UART0_RX 0x100
#define DMA_DES_UART0_TX 0x140
#define DMA_DES_UART1_RX 0x180
#define DMA_DES_UART1_TX 0x1C0
#define DMA_DES_External_Req0 0x200
#define DMA_DES_External_Req1 0x240
#define DMA_DES_I2C0 0x280
#define DMA_DES_I2C1 0x2C0
#define DMA_DES_SSP0_RX 0x300
#define DMA_DES_SSP0_TX 0x340
#define DMA_DES_SSP1_RX 0x380
#define DMA_DES_SSP1_TX 0x3C0
/* Source request selection: selects the DMA Source request peripheral */
#define DMA_SRC_USB_RX 0x00
#define DMA_SRC_USB_TX 0x02
#define DMA_SRC_TIM1 0x04
#define DMA_SRC_TIM2 0x06
#define DMA_SRC_UART0_RX 0x08
#define DMA_SRC_UART0_TX 0x0A
#define DMA_SRC_UART1_RX 0x0C
#define DMA_SRC_UART1_TX 0x0E
#define DMA_SRC_External_Req0 0x10
#define DMA_SRC_External_Req1 0x12
#define DMA_SRC_I2C0 0x14
#define DMA_SRC_I2C1 0x16
#define DMA_SRC_SSP0_RX 0x18
#define DMA_SRC_SSP0_TX 0x1A
#define DMA_SRC_SSP1_RX 0x1C
#define DMA_SRC_SSP1_TX 0x1E
#define DMA_FlowCntrlt0_DMA 0x00000000 /* transfer type :Memory-to-memory, flow controller:DMA */
#define DMA_FlowCntrl1_DMA 0x00000800 /* transfer type :Memory-to-peripheral, flow controller:DMA */
#define DMA_FlowCntrl2_DMA 0x00001000 /* transfer type :Peripheral-to-memory, flow controller:DMA */
#define DMA_FlowCntrl3_DMA 0x00001800 /* transfer type :Source peripheral-to-destination peripheral, flow controller:DMA */
#define DMA_FlowCntrl_DestPerip 0x00002000 /* transfer type :Source peripheral-to-destination peripheral, flow controller:Destination peripheral */
#define DMA_FlowCntrl_Perip1 0x00002800 /* transfer type :Memory-to-peripheral, flow controller:peripheral */
#define DMA_FlowCntrl_Perip2 0x00003000 /* transfer type : Peripheral-to-memory, flow controller:peripheral */
#define DMA_FlowCntrl_SrcPerip 0x00003800 /* transfer type :Source peripheral-to-destination peripheral, flow controller:Source peripheral */
#define DMA_SrcBst_1Data 0x00000000 /* Source Burst transfer request IS 1 Data ( DATA = Source transfer width ) */
#define DMA_SrcBst_4Data 0x00001000 /* Source Burst transfer request IS 4 Data */
#define DMA_SrcBst_8Data 0x00002000 /* Source Burst transfer request IS 8 Data */
#define DMA_SrcBst_16Data 0x00003000 /* Source Burst transfer request IS 16 Data */
#define DMA_SrcBst_32Data 0x00004000 /* Source Burst transfer request IS 32 Data */
#define DMA_SrcBst_64Data 0x00005000 /* Source Burst transfer request IS 64Data */
#define DMA_SrcBst_128Data 0x00006000 /* Source Burst transfer request IS 128 Data */
#define DMA_SrcBst_256Data 0x00007000 /* Source Burst transfer request IS 256 Data */
#define DMA_DesBst_1Data 0x00000000 /*Destination Burst transfer request IS 1Data ( DATA = destination transfer width ) */
#define DMA_DesBst_4Data 0x00008000 /*Destination Burst transfer request IS 1 Data */
#define DMA_DesBst_8Data 0x00010000 /*Destination Burst transfer request IS 4 Data */
#define DMA_DesBst_16Data 0x00018000 /*Destination Burst transfer request IS 8 Data */
#define DMA_DesBst_32Data 0x00020000 /*Destination Burst transfer request IS 16 Data */
#define DMA_DesBst_64Data 0x00028000 /*Destination Burst transfer request IS 32 Data */
#define DMA_DesBst_128Data 0x00030000 /*Destination Burst transfer request IS 128 Data */
#define DMA_DesBst_256Data 0x00038000 /*Destination Burst transfer request IS 256 Data */
#define DMA_SrcWidth_Byte 0x00000000 /* source Width is one Byte */
#define DMA_SrcWidth_HalfWord 0x00040000 /* source Width is one HalfWord */
#define DMA_SrcWidth_Word 0x00080000 /* source Width is one Word */
#define DMA_DesWidth_Byte 0x00000000 /* Destination Width is one Byte */
#define DMA_DesWidth_HalfWord 0x00200000 /* Destination Width is one HalfWord */
#define DMA_DesWidth_Word 0x00400000 /* Destination Width is one Word */
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void DMA_DeInit(void);
void DMA_Init(DMA_Channel_TypeDef * DMA_Channelx, DMA_InitTypeDef * DMA_InitStruct);
void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct);
void DMA_Cmd(FunctionalState NewState);
void DMA_ITMaskConfig(DMA_Channel_TypeDef * DMA_Channelx, u16 DMA_ITMask, FunctionalState NewState);
void DMA_ITConfig(DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState);
FlagStatus DMA_GetChannelStatus(u8 ChannelIndx );
ITStatus DMA_GetITStatus(u8 ChannelIndx,u8 DMA_ITReq);
void DMA_ClearIT(u8 ChannelIndx,u8 DMA_ITClr);
void DMA_SyncConfig(u16 DMA_SrcReq, FunctionalState NewState);
FlagStatus DMA_GetSReq(u16 DMA_SrcReq);
FlagStatus DMA_GetLSReq(u16 DMA_SrcReq);
FlagStatus DMA_GetBReq(u16 DMA_SrcReq);
FlagStatus DMA_GetLBReq(u16 DMA_SrcReq);
FlagStatus DMA_GetChannelActiveStatus( DMA_Channel_TypeDef * DMA_Channelx);
void DMA_SetSReq(u16 DMA_SrcReq);
void DMA_SetLSReq(u16 DMA_SrcReq);
void DMA_SetBReq(u16 DMA_SrcReq);
void DMA_SetLBReq(u16 DMA_SrcReq);
void DMA_ChannelCmd (DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState);
void DMA_ChannelHalt (DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState);
void DMA_ChannelBuffering (DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState);
void DMA_ChannelLockTrsf(DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState);
void DMA_ChannelCache(DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState);
void DMA_ChannelProt0Mode(DMA_Channel_TypeDef * DMA_Channelx,u32 Prot0Mode);
void DMA_ChannelSRCIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState);
void DMA_ChannelDESIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState);
#endif /* __91x_DMA_H */
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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Demo/ARM9_STR91X_IAR/Library/include/91x_enet.h
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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_enet.h
* Author : MCD Application Team
* Date First Issued : May 2006
* Description : ENET driver defines & function prototypes
********************************************************************************
* History:
* May 2006: v1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#ifndef _ENET_H_
#define _ENET_H_
#include <91x_lib.h>
#define ENET_BUFFER_SIZE 1520
/*Structures typedef----------------------------------------------------------*/
/*Struct containing the DMA Descriptor data */
typedef struct {
volatile u32 dmaStatCntl; /* DMA Status and Control Register */
volatile u32 dmaAddr; /* DMA Start Address Register */
volatile u32 dmaNext; /* DMA Next Descriptor Register */
volatile u32 dmaPackStatus; /* DMA Packet Status and Control Register */
} ENET_DMADSCRBase;
/* ENET_MACConfig Struct*/
typedef struct {
FunctionalState ReceiveALL; /* Receive All frames: no address rule filtering */
u32 MIIPrescaler; /* MII Clock Prescaler value */
FunctionalState LoopbackMode; /* MAC Loopback mode */
u32 AddressFilteringMode; /* Address Filtering Mode */
u32 VLANFilteringMode; /* VLAN Filtering Mode */
FunctionalState PassWrongFrame; /* Pass wrong frame (CRC, overlength, runt..)*/
FunctionalState LateCollision; /* Retransmit frame when late collision*/
FunctionalState BroadcastFrameReception; /* Accept broardcast frame */
FunctionalState PacketRetry; /* Retransmit frame in case of collision */
FunctionalState RxFrameFiltering; /* Filter early runt frame and address filter fail frames*/
FunctionalState AutomaticPadRemoval; /* Automatic Padding removal */
FunctionalState DeferralCheck; /* Excessive Defferal check */
} ENET_MACConfig;
/* ENET_TxStatus Struct*/
typedef struct {
FlagStatus PacketRetry;
u8 ByteCount;
u8 collisionCount;
FlagStatus LateCollisionObserved;
FlagStatus Deffered;
FlagStatus UnderRun;
FlagStatus ExcessiveCollision;
FlagStatus LateCollision;
FlagStatus ExcessiveDefferal;
FlagStatus LossOfCarrier;
FlagStatus NoCarrier;
FlagStatus FrameAborted;
} ENET_TxStatus;
/* ENET_RxStatus Struct*/
typedef struct {
FlagStatus FrameAborted;
FlagStatus PacketFilter;
FlagStatus FilteringFail;
FlagStatus BroadCastFrame;
FlagStatus MulticastFrame;
FlagStatus UnsupportedControFrame;
FlagStatus ControlFrame;
FlagStatus LengthError;
FlagStatus Vlan2Tag;
FlagStatus Vlan1Tag;
FlagStatus CRCError;
FlagStatus ExtraBit;
FlagStatus MIIError;
FlagStatus FrameType;
FlagStatus LateCollision;
FlagStatus OverLength;
FlagStatus RuntFrame;
FlagStatus WatchDogTimout;
FlagStatus FalseCarrierIndication;
u16 FrameLength;
} ENET_RxStatus;
/*Constants-------------------------------------------------------------------*/
/* AddressFilteringMode */
#define MAC_Perfect_Multicast_Perfect 0x0
#define MAC_Perfect_Muticast_Hash 0x1<<17
#define MAC_Hash_Multicast_Hash 0x3<<17
#define Inverse 0x4<<17
#define Promiscuous 0x5<<17
#define MAC_Hash_Muticast_All 0x6<<17
/* VLANFilteringMode */
#define VLANFilter_VLTAG_VLID 1
#define VLANfilter_VLTAG 0
/* MIIPrescaler */
#define MIIPrescaler_1 0 /* Prescaler for MDC clock when HCLK < 50 MHz */
#define MIIPrescaler_2 1 /* Precaler for MDC when HCLK > = 50 MHz */
/* MAC Address*/
#define MAC_ADDR0 0x0D
#define MAC_ADDR1 0x0A
#define MAC_ADDR2 0x08
#define MAC_ADDR3 0x04
#define MAC_ADDR4 0x02
#define MAC_ADDR5 0x01
/* Multicast Address */
#define MCAST_ADDR0 0xFF
#define MCAST_ADDR1 0x00
#define MCAST_ADDR2 0xFF
#define MCAST_ADDR3 0x00
#define MCAST_ADDR4 0xFF
#define MCAST_ADDR5 0x00
#define ENET_MAX_PACKET_SIZE 1520
#define ENET_NEXT_ENABLE 0x4000
/*ENET_OperatingMode*/
/* Set the full/half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_100M 0x2100
#define PHY_HALFDUPLEX_100M 0x2000
/* Set the full/half-duplex mode at 10 Mb/s */
#define PHY_FULLDUPLEX_10M 0x0100
#define PHY_HALFDUPLEX_10M 0x0000
/*----------------------------functions----------------------------------------*/
void ENET_MACControlConfig(ENET_MACConfig *MAC_Config);
void ENET_GetRxStatus(ENET_RxStatus * RxStatus);
void ENET_GetTxStatus(ENET_TxStatus * TxStatus);
long ENET_SetOperatingMode(void);
void ENET_InitClocksGPIO(void);
void ENET_MIIWriteReg (u8 phyDev, u8 phyReg, u32 phyVal);
u32 ENET_MIIReadReg (u8 phyDev, u32 phyReg );
void ENET_RxDscrInit(void);
void ENET_TxDscrInit(void);
void ENET_Init(void);
void ENET_Start(void);
u32 ENET_RxPacketGetSize(void);
void ENET_TxPkt(void *ppkt, u16 size);
u32 ENET_HandleRxPkt(void *ppkt);
/*Driver internal constants---------------------------------------------------*/
/* MII Address */
/* Description of bit field values of the MII Address Register */
#define MAC_MIIA_PADDR 0x0000F800
#define MAC_MII_ADDR_PHY_ADDR MAC_MIIA_PADDR /* Phy Address (default: 0): select one of 32 dev */
#define MAC_MII_ADDR_MII_REG 0x000007C0 /* MII Register (default: 0) */
#define MAC_MII_ADDR_MII_WRITE 0x00000002 /* MII Write */
#define MAC_MIIA_PHY_DEV_ADDR (0x00005000 & MAC_MIIA_PADDR) /*To be changed if PHY device address changes */
#define MAC_MII_ADDR_MII_BUSY 0x00000001 /* MII Busy */
/* MII DATA register */
#define MAC_MII_DATA_REG 0x0000FFFF /* MII Data */
/* MII Read / write timeouts*/
#define MII_READ_TO 0x0004FFFF
#define MII_WRITE_TO 0x0004FFFF
/* Description of common PHY registers */
#define MAC_MII_REG_XCR 0x00000000 /* Tranceiver control register */
#define MAC_MII_REG_XSR 0x00000001 /* Tranceiver status register */
#define MAC_MII_REG_PID1 0x00000002 /* Tranceiver PHY identifier 1 */
#define MAC_MII_REG_PID2 0x00000003 /* Tranceiver PHY identifier 2 */
#define MAC_MII_REG_ANA 0x00000004 /* Auto-Negociation Advertissement register */
#define MAC_MII_REG_ANLPA 0x00000005 /* Auto-Negociation Link Partner Ability register */
#define MAC_MII_REG_ANE 0x00000006 /* Auto-Negociation Expansion register */
/* MAC_MCR register fields */
#define MAC_MCR_RA 0x80000000
#define MAC_MCR_EN 0x40000000
#define MAC_MCR_PS 0x03000000
#define MAC_MCR_DRO 0x00800000
#define MAC_MCR_LM 0x00600000
#define MAC_MCR_FDM 0x00100000
#define MAC_MCR_AFM 0x000E0000
#define MAC_MCR_PWF 0x00010000
#define MAC_MCR_VFM 0x00008000
#define MAC_MCR_ELC 0x00001000
#define MAC_MCR_DBF 0x00000800
#define MAC_MCR_DPR 0x00000400
#define MAC_MCR_RVFF 0x00000200
#define MAC_MCR_APR 0x00000100
#define MAC_MCR_BL 0x000000C0
#define MAC_MCR_DCE 0x00000020
#define MAC_MCR_RVBE 0x00000010
#define MAC_MCR_TE 0x00000008
#define MAC_MCR_RE 0x00000004
#define MAC_MCR_RCFA 0x00000001
/* MTS */
#define MAC_MTS_FA 0x00000001
#define MAC_MTS_NC 0x00000004
#define MAC_MTS_LOC 0x00000008
#define MAC_MTS_ED 0x00000010
#define MAC_MTS_LC 0x00000020
#define MAC_MTS_EC 0x00000040
#define MAC_MTS_UR 0x00000080
#define MAC_MTS_DEF 0x00000100
#define MAC_MTS_LCO 0x00000200
#define MAC_MTS_CC 0x00003C00
#define MAC_MTS_BC 0x7FFC0000
#define MAC_MTS_PR 0x80000000
/* MRS */
#define MAC_MRS_FL 0x000007FF
#define MAC_MRS_FCI 0x00002000
#define MAC_MRS_WT 0x00004000
#define MAC_MRS_RF 0x00008000
#define MAC_MRS_OL 0x00010000
#define MAC_MRS_LC 0x00020000
#define MAC_MRS_FT 0x00040000
#define MAC_MRS_ME 0x00080000
#define MAC_MRS_EB 0x00100000
#define MAC_MRS_CE 0x00200000
#define MAC_MRS_VL1 0x00400000
#define MAC_MRS_VL2 0x00800000
#define MAC_MRS_LE 0x01000000
#define MAC_MRS_CF 0x02000000
#define MAC_MRS_UCF 0x04000000
#define MAC_MRS_MCF 0x08000000
#define MAC_MRS_BF 0x10000000
#define MAC_MRS_FF 0x20000000
#define MAC_MRS_PF 0x40000000
#define MAC_MRS_FA 0x80000000
/* SCR */
#define DMA_SCR_SRESET 0x00000001 /* Soft Reset (DMA_SCR_RESET) */
#define DMA_SCR_LOOPB 0x00000002 /* Loopback mode (DMA_SCR_LOOPB) */
#define DMA_SCR_RX_MBSIZE 0x00000010 /* Max defined burst length in RX mode (DMA_SCR_RX_MAX_BURST_...) */
#define DMA_SCR_TX_MBSIZE 0x000000C0 /* Max defined burst length in TX mode (DMA_SCR_TX_MAX_BURST_...) */
#define DMA_SCR_RX_MAX_BURST_SZ DMA_SCR_RX_MBSIZE /* Maximum value of defined burst length in RX mode */
#define DMA_SCR_RX_MAX_BURST_SZ_VAL 0x00000000 /* Default value of burst length in RX mode */
#define DMA_SCR_TX_MAX_BURST_SZ DMA_SCR_TX_MBSIZE /* Maximum value of defined burst length in TX mode */
#define DMA_SCR_TX_MAX_BURST_SZ_VAL 0x000000C0 /* Default value of burst length in TX mode */
/* DMA_RX_START */
#define DMA_RX_START_DMAEN 0x00000001
#define DMA_RX_START_STFETCH 0x00000004
#define DMA_RX_START_FFAIL 0x00000020
#define DMA_RX_START_RUNT 0x00000040
#define DMA_RX_START_COLLS 0x00000080
#define DMA_RX_START_DMA_EN 0x00000001 /* set = 0 by sw force a DMA abort */
#define DMA_RX_START_FETCH 0x00000004 /* start fetching the 1st descriptor */
#define DMA_RX_START_FILTER_FAIL 0x00000020 /* if = 1 the address filtering failed cond */
#define DMA_RX_START_RUNT 0x00000040 /* discard damaged RX frames from cpu charge */
#define DMA_RX_START_COLLS_SEEN 0x00000080 /* Late Collision Seen Cond discard frame automat. */
#define DMA_RX_START_DFETCH_DLY 0x00FFFF00 /* Descriptor Fetch Delay */
#define DMA_RX_START_DFETCH_DLY_POS 8
#define DMA_RX_START_DFETCH_DEFAULT 0x00010000 /* Descriptor Fetch Delay default value */
/* DMA_DSCR_PACK_STAT */
#define DMA_DSCR_PACK_STAT 0x00010000
/* DMA_TX_START */
#define DMA_TX_START_DMAEN 0x00000001
#define DMA_TX_START_STFETCH 0x00000004
#define DMA_TX_START_URUN 0x00000020
#define DMA_TX_START_DISPAD 0x00000040
#define DMA_TX_START_ADDCTC 0x00000080
#define DMA_TX_START_DMA_EN 0x00000001 /* set = 0 by sw force a DMA abort */
#define DMA_TX_START_FETCH 0x00000004 /* start fetching the 1st descriptor */
#define DMA_RX_START_FILTER_FAIL 0x00000020 /* if = 1 the address filtering failed cond */
#define DMA_TX_START_DFETCH_DLY 0x00FFFF00 /* Descriptor Fetch Delay */
#define DMA_TX_START_DFETCH_DEFAULT 0x00010000 /* Descriptor Fetch Delay */
#define DMA_TX_START_DFETCH_DLY_POS 0x8
#define DMA_TX_START_URUN 0x00000020
#define DMA_TX_START_DIS_PADDING 0x00000040 /* Avoid automatic addition of padding bits by MAC*/
#define DMA_TX_START_ADD_CRC_DIS 0x00000080 /* Tell MAC not to ADD CRC field at end of frame */
/* DMA_DSCR_CNTL */
#define DMA_DSCR_CNTL_XFERCOUNT 0x00000FFF
#define DMA_DSCR_CNTL_NXTEN 0x00004000
/* DMA_DSCR_ADDR */
#define DMA_DSCR_ADDR 0xFFFFFFFC /* for DMA Start Address (32 bit Word Align) */
#define DMA_DSCR_ADDR_FIX_ADDR 0x00000002 /* Disable incrementing of DMA_ADDR */
#define DMA_DSCR_ADDR_WRAPEN_SET 0x00000001
#define DMA_DSCR_ADDR_WRAPEN_RST 0x00000000
/* DMA_DSCR_NEXT_ADDR TX/RX */
#define DMA_DSCR_NXT_DSCR_ADDR 0xFFFFFFFC /* Points to Next descriptor starting address */
#define DMA_DSCR_NXT_NPOL_EN 0x00000001 /* Next Descriptor Polling Enable */
#define DMA_DSCR_NXT_NEXT_EN 0x00000002 /* Next Descriptor Fetch mode Enable */
/* DMA Descriptor Packet Status: TX */
#define DMA_DSCR_TX_STATUS_FA_MSK 0x00000001 /* Frame Aborted */
#define DMA_DSCR_TX_STATUS_JTO_MSK 0x00000002 /* Jabber Timeout. */
#define DMA_DSCR_TX_STATUS_NOC_MSK 0x00000004 /* No Carrier */
#define DMA_DSCR_TX_STATUS_LOC_MSK 0x00000008 /* Loss of Carrier */
#define DMA_DSCR_TX_STATUS_EXCD_MSK 0x00000010 /* Excessive Deferral */
#define DMA_DSCR_TX_STATUS_LCOLL_MSK 0x00000020 /* Late Collision */
#define DMA_DSCR_TX_STATUS_ECOLL_MSK 0x00000040 /* Excessive Collisions */
#define DMA_DSCR_TX_STATUS_URUN_MSK 0x00000080 /* Under Run */
#define DMA_DSCR_TX_STATUS_DEFER_MSK 0x00000100 /* Deferred */
#define DMA_DSCR_TX_STATUS_LCOLLO_MSK 0x00000200 /* Late Collision Observed */
#define DMA_DSCR_TX_STATUS_CCNT_MSK 0x00003C00 /* Collision Count */
#define DMA_DSCR_TX_STATUS_HBFAIL_MSK 0x00004000 /* Heart Beat Fail */
#define DMA_DSCR_TX_STATUS_VALID_MSK 0x00010000 /* Valid bit indicator - This bit marks the dscriptors this word belong */
#define DMA_DSCR_TX_STATUS_PKT_RTRY_MSK 0x80000000 /* Packet Retry */
#define DMA_DSCR_TX_STATUS_ORED_ERR_MSK 0x000003D7 /* for total number of errors */
/* DMA Descriptor Packet Status: RX */
#define DMA_DSCR_RX_STATUS_FLEN_MSK 0x000007ff /* 0x00003FFF * Frame Length (max 2047) */
#define DMA_DSCR_RX_STATUS_FTLONG_MSK 0x00001000 /* Over Lenght */
#define DMA_DSCR_RX_STATUS_FCI_MSK 0x00002000 /* Frame too Long */
#define DMA_DSCR_RX_STATUS_WDTO_MSK 0x00004000 /* Watchdog Timeout */
#define DMA_DSCR_RX_STATUS_RUNTFR_MSK 0x00008000 /* Runt Frame */
#define DMA_DSCR_RX_STATUS_VALID_MSK 0x00010000 /* Valid bit indicator - This bit marks the dscriptors this word */
#define DMA_DSCR_RX_STATUS_COLLSEEN_MSK 0x00020000 /* Collision Seen */
#define DMA_DSCR_RX_STATUS_FTYPE_MSK 0x00040000 /* Frame Type */
#define DMA_DSCR_RX_STATUS_MII_ERR_MSK 0x00080000 /* MII Error */
#define DMA_DSCR_RX_STATUS_DRBBIT_MSK 0x00100000 /* Dribbling Bit */
#define DMA_DSCR_RX_STATUS_CRC_ERR_MSK 0x00200000 /* CRC Error */
#define DMA_DSCR_RX_STATUS_VLAN1_FR_MSK 0x00400000 /* One-Level VLAN Frame */
#define DMA_DSCR_RX_STATUS_VLAN2_FR_MSK 0x00800000 /* Two-Level VLAN Frame */
#define DMA_DSCR_RX_STATUS_LEN_ERR_MSK 0x01000000 /* Length Error */
#define DMA_DSCR_RX_STATUS_CTL_FR_MSK 0x02000000 /* Control Frame */
#define DMA_DSCR_RX_STATUS_UCTRL_FR_MSK 0x04000000 /* Unsupported Control Frame */
#define DMA_DSCR_RX_STATUS_MCAST_FR_MSK 0x08000000 /* Multicast Frame */
#define DMA_DSCR_RX_STATUS_BCAST_FR_MSK 0x10000000 /* BroadCast Frame */
#define DMA_DSCR_RX_STATUS_FLT_FAIL_MSK 0x20000000 /* Filtering Fail */
#define DMA_DSCR_RX_STATUS_PKT_FILT_MSK 0x40000000 /* Packet Filter */
#define DMA_DSCR_RX_STATUS_MIS_FR_MSK 0x80000000 /* Missed Frame */
#define DMA_DSCR_RX_STATUS_ERROR_MSK (DMA_DSCR_RX_STATUS_LEN_ERR | DMA_DSCR_RX_STATUS_CRC_ERR | \
DMA_DSCR_RX_STATUS_MII_ERR | DMA_DSCR_RX_STATUS_RUNTFR | \
DMA_DSCR_RX_STATUS_FTLONG | DMA_DSCR_RX_STATUS_COLLSEEN)
#define DMA_DSCR_RX_STATUS_ORED_ERR_MSK 0x00000000 /*Mask for total number of errors */
#endif /* _ENET_H_ */
/******************** (C) COPYRIGHT 2006 STMicroelectronics *******************/

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Demo/ARM9_STR91X_IAR/Library/include/91x_fmi.h
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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_fmi.h
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : This file contains all the functions prototypes for the
* FMI software library.
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion ------------------------------------ */
#ifndef __91x_FMI_H
#define __91x_FMI_H
/* ========================================================================== */
/* When bank 1 is remapped at address 0x0, decomment the following line */
/* ========================================================================== */
//#define Remap_Bank_1
/* Includes ------------------------------------------------------------------*/
#include "91x_map.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* FMI banks */
#ifdef Remap_Bank_1
#define FMI_BANK_0 ((*(vu32*)0x54000010) << 2) /* FMI Bank 0 */
#define FMI_BANK_1 ((*(vu32*)0x5400000C) << 2) /* FMI Bank 1 */
#else /* Remap Bank 0 */
#define FMI_BANK_0 ((*(vu32*)0x5400000C) << 2) /* FMI Bank 0 */
#define FMI_BANK_1 ((*(vu32*)0x54000010) << 2) /* FMI Bank 1 */
#endif
/* FMI sectors */
#define FMI_B0S0 0x00000000 + FMI_BANK_0 /* Bank 0 sector 0 */
#define FMI_B0S1 0x00010000 + FMI_BANK_0 /* Bank 0 sector 1 */
#define FMI_B0S2 0x00020000 + FMI_BANK_0 /* Bank 0 sector 2 */
#define FMI_B0S3 0x00030000 + FMI_BANK_0 /* Bank 0 sector 3 */
#define FMI_B0S4 0x00040000 + FMI_BANK_0 /* Bank 0 sector 4 */
#define FMI_B0S5 0x00050000 + FMI_BANK_0 /* Bank 0 sector 5 */
#define FMI_B0S6 0x00060000 + FMI_BANK_0 /* Bank 0 sector 6 */
#define FMI_B0S7 0x00070000 + FMI_BANK_0 /* Bank 0 sector 7 */
#define FMI_B1S0 0x00000000 + FMI_BANK_1 /* Bank 1 sector 0 */
#define FMI_B1S1 0x00002000 + FMI_BANK_1 /* Bank 1 sector 1 */
#define FMI_B1S2 0x00004000 + FMI_BANK_1 /* Bank 1 sector 2 */
#define FMI_B1S3 0x00006000 + FMI_BANK_1 /* Bank 1 sector 3 */
/* FMI Flags */
#define FMI_FLAG_SPS 0x02 /* Sector Protection Status Flag */
#define FMI_FLAG_PSS 0x04 /* Program Suspend Status Flag */
#define FMI_FLAG_PS 0x10 /* Program Status Flag */
#define FMI_FLAG_ES 0x20 /* Erase Status Flag */
#define FMI_FLAG_ESS 0x40 /* Erase Suspend Status Flag */
#define FMI_FLAG_PECS 0x80 /* FPEC Status Flag */
/* FMI read wait states */
#define FMI_READ_WAIT_STATE_1 0x0000 /* One read wait state */
#define FMI_READ_WAIT_STATE_2 0x2000 /* Two read wait states */
#define FMI_READ_WAIT_STATE_3 0x4000 /* Three read wait states */
/* FMI write wait states */
#define FMI_WRITE_WAIT_STATE_0 0xFFFFFEFF /* Zero wait state */
#define FMI_WRITE_WAIT_STATE_1 0x00000100 /* One wait state */
/* FMI power down configuration */
#define FMI_PWD_ENABLE 0x1000 /* FMI Power Down Enable */
#define FMI_PWD_DISABLE 0x0000 /* FMI Power Down Disable */
/* FMI low voltage detector */
#define FMI_LVD_ENABLE 0x0000 /* FMI Low Voltage Detector Enable */
#define FMI_LVD_DISABLE 0x0800 /* FMI Low Voltage Detector Disable */
/* FMI frequency range */
#define FMI_FREQ_LOW 0x0000 /* FMI Low bus working frequency */
#define FMI_FREQ_HIGH 0x0040 /* FMI High bus working gfrequency */
/* Above 66 MHz*/
/* FMI OTP word addresses */
#define FMI_OTP_WORD_0 0x00 /* OTP word 0 */
#define FMI_OTP_WORD_1 0x04 /* OTP word 1 */
#define FMI_OTP_WORD_2 0x08 /* OTP word 2 */
#define FMI_OTP_WORD_3 0x0C /* OTP word 3 */
#define FMI_OTP_WORD_4 0x10 /* OTP word 4 */
#define FMI_OTP_WORD_5 0x14 /* OTP word 5 */
#define FMI_OTP_WORD_6 0x18 /* OTP word 6 */
#define FMI_OTP_WORD_7 0x1C /* OTP word 7 */
/* FMI OTP halfword addresses */
#define FMI_OTP_LOW_HALFWORD_0 0x00 /* OTP Low halfword 0 */
#define FMI_OTP_HIGH_HALFWORD_0 0x02 /* OTP High halfword 0 */
#define FMI_OTP_LOW_HALFWORD_1 0x04 /* OTP Low halfword 1 */
#define FMI_OTP_HIGH_HALFWORD_1 0x06 /* OTP High halfword 1 */
#define FMI_OTP_LOW_HALFWORD_2 0x08 /* OTP Low halfword 2 */
#define FMI_OTP_HIGH_HALFWORD_2 0x0A /* OTP High halfword 2 */
#define FMI_OTP_LOW_HALFWORD_3 0x0C /* OTP Low halfword 3 */
#define FMI_OTP_HIGH_HALFWORD_3 0x0E /* OTP High halfword 3 */
#define FMI_OTP_LOW_HALFWORD_4 0x10 /* OTP Low halfword 4 */
#define FMI_OTP_HIGH_HALFWORD_4 0x12 /* OTP High halfword 4 */
#define FMI_OTP_LOW_HALFWORD_5 0x14 /* OTP Low halfword 5 */
#define FMI_OTP_HIGH_HALFWORD_5 0x16 /* OTP High halfword 5 */
#define FMI_OTP_LOW_HALFWORD_6 0x18 /* OTP Low halfword 6 */
#define FMI_OTP_HIGH_HALFWORD_6 0x1A /* OTP High halfword 6 */
#define FMI_OTP_LOW_HALFWORD_7 0x1C /* OTP Low halfword 7 */
#define FMI_OTP_HIGH_HALFWORD_7 0x1E /* OTP High halfword 7 */
/* FMI sectors Masks */
#define FMI_B0S0_MASK 0x0001 /* FMI B0S0 mask */
#define FMI_B0S1_MASK 0x0002 /* FMI B0S1 mask */
#define FMI_B0S2_MASK 0x0004 /* FMI B0S2 mask */
#define FMI_B0S3_MASK 0x0008 /* FMI B0S3 mask */
#define FMI_B0S4_MASK 0x0010 /* FMI B0S4 mask */
#define FMI_B0S5_MASK 0x0020 /* FMI B0S5 mask */
#define FMI_B0S6_MASK 0x0040 /* FMI B0S6 mask */
#define FMI_B0S7_MASK 0x0080 /* FMI B0S7 mask */
#define FMI_B1S0_MASK 0x0100 /* FMI B1S0 mask */
#define FMI_B1S1_MASK 0x0200 /* FMI B1S1 mask */
#define FMI_B1S2_MASK 0x0400 /* FMI B1S2 mask */
#define FMI_B1S3_MASK 0x0800 /* FMI B1S3 mask */
/* Timeout error */
#define FMI_TIME_OUT_ERROR 0x00 /* Timeout error */
#define FMI_NO_TIME_OUT_ERROR 0x01 /* No Timeout error */
/* Module private variables --------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void FMI_BankRemapConfig(u8 FMI_BootBankSize, u8 FMI_NonBootBankSize, \
u32 FMI_BootBankAddress, u32 FMI_NonBootBankAddress);
void FMI_Config(u16 FMI_ReadWaitState, u32 FMI_WriteWaitState, u16 FMI_PWD,\
u16 FMI_LVDEN, u16 FMI_FreqRange);
void FMI_EraseSector(vu32 FMI_Sector);
void FMI_EraseBank(vu32 FMI_Bank);
void FMI_WriteHalfWord(u32 FMI_Address, u16 FMI_Data);
void FMI_WriteOTPHalfWord(u8 FMI_OTPHWAddress, u16 FMI_OTPData);
u32 FMI_ReadWord(u32 FMI_Address);
u32 FMI_ReadOTPData(u8 FMI_OTPAddress);
FlagStatus FMI_GetFlagStatus(u8 FMI_Flag, vu32 FMI_Bank);
u16 FMI_GetReadWaitStateValue(void);
u16 FMI_GetWriteWaitStateValue(void);
void FMI_SuspendEnable(vu32 FMI_Bank);
void FMI_ResumeEnable(vu32 FMI_Bank);
void FMI_ClearFlag(vu32 FMI_Bank);
void FMI_WriteProtectionCmd(vu32 FMI_Sector, FunctionalState FMI_NewState);
FlagStatus FMI_GetWriteProtectionStatus(u32 FMI_Sector_Protection);
u8 FMI_WaitForLastOperation(vu32 FMI_Bank);
#endif /* __91x_FMI_H */
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_gpio.h
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : This file contains all the functions prototypes for the
* GPIO software library.
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion ------------------------------------ */
#ifndef _91x_GPIO_H
#define _91x_GPIO_H
/* Includes ------------------------------------------------------------------*/
#include "91x_map.h"
/* GPIO Init structure definition */
typedef struct
{
u8 GPIO_Pin;
u8 GPIO_Direction;
u8 GPIO_Type;
u8 GPIO_IPConnected;
u16 GPIO_Alternate;
}GPIO_InitTypeDef;
/* Bit_SET and Bit_RESET enumeration */
typedef enum
{ Bit_RESET = 0,
Bit_SET
}BitAction;
/* Exported constants --------------------------------------------------------*/
#define GPIO_Pin_None 0x00
#define GPIO_Pin_0 0x01
#define GPIO_Pin_1 0x02
#define GPIO_Pin_2 0x04
#define GPIO_Pin_3 0x08
#define GPIO_Pin_4 0x10
#define GPIO_Pin_5 0x20
#define GPIO_Pin_6 0x40
#define GPIO_Pin_7 0x80
#define GPIO_Pin_All 0xFF
#define GPIO_PinInput 0x00
#define GPIO_PinOutput 0x01
#define GPIO_Type_PushPull 0x00
#define GPIO_Type_OpenCollector 0x01
#define GPIO_IPConnected_Disable 0x00
#define GPIO_IPConnected_Enable 0x01
#define GPIO_InputAlt1 0x00
#define GPIO_OutputAlt1 0x01
#define GPIO_OutputAlt2 0x02
#define GPIO_OutputAlt3 0x03
#define GPIO_ANAChannel0 0x01
#define GPIO_ANAChannel1 0x02
#define GPIO_ANAChannel2 0x04
#define GPIO_ANAChannel3 0x08
#define GPIO_ANAChannel4 0x10
#define GPIO_ANAChannel5 0x20
#define GPIO_ANAChannel6 0x40
#define GPIO_ANAChannel7 0x80
#define GPIO_ANAChannelALL 0xFF
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin);
u8 GPIO_Read(GPIO_TypeDef* GPIOx);
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin, BitAction BitVal);
void GPIO_Write(GPIO_TypeDef* GPIOx, u8 PortVal);
void GPIO_EMIConfig(FunctionalState NewState);
void GPIO_ANAPinConfig(u8 GPIO_ANAChannel, FunctionalState NewState);
#endif /* _91x_GPIO_H */
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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Demo/ARM9_STR91X_IAR/Library/include/91x_it.h
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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_it.h
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : This file contains the headers of the interrupt
* handlers'routines
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion ------------------------------------ */
#ifndef _91x_IT_H
#define _91x_IT_H
/* Includes ------------------------------------------------------------------*/
#include "91x_lib.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Module private variables --------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void Undefined_Handler (void);
void SWI_Handler (void);
void Prefetch_Handler (void);
void Abort_Handler (void);
void FIQ_Handler (void);
void WDG_IRQHandler (void);
void SW_IRQHandler (void);
void ARMRX_IRQHandler (void);
void ARMTX_IRQHandler (void);
void TIM0_IRQHandler (void);
void TIM1_IRQHandler (void);
void TIM2_IRQHandler (void);
void TIM3_IRQHandler (void);
void USBHP_IRQHandler (void);
void USBLP_IRQHandler (void);
void SCU_IRQHandler (void);
void ENET_IRQHandler (void);
void DMA_IRQHandler (void);
void CAN_IRQHandler (void);
void MC_IRQHandler (void);
void ADC_IRQHandler (void);
void UART0_IRQHandler (void);
void UART1_IRQHandler (void);
void UART2_IRQHandler (void);
void I2C0_IRQHandler (void);
void I2C1_IRQHandler (void);
void SSP0_IRQHandler (void);
void SSP1_IRQHandler (void);
void LVD_IRQHandler (void);
void RTC_IRQHandler (void);
void WIU_IRQHandler (void);
void EXTIT0_IRQHandler (void);
void EXTIT1_IRQHandler (void);
void EXTIT2_IRQHandler (void);
void EXTIT3_IRQHandler (void);
void USBWU_IRQHandler (void);
void PFQBC_IRQHandler (void);
#endif /* _91x_IT_H */
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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Demo/ARM9_STR91X_IAR/Library/include/91x_lib.h
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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_lib.h
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : Used to include the peripherals header file in the
* user application.
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#ifndef __91x_LIB_H
#define __91x_LIB_H
#include "91x_map.h"
#include "91x_conf.h"
#ifdef _AHBAPB
#include "91x_ahbapb.h"
#endif /* _AHBAPB */
#ifdef _EMI
#include "91x_emi.h"
#endif /* _EMI */
#ifdef _DMA
#include "91x_dma.h"
#endif /* _DMA */
#ifdef _FMI
#include "91x_fmi.h"
#endif /* _FMI */
#ifdef _VIC
#include "91x_vic.h"
#endif /* _VIC */
#ifdef _WIU
#include "91x_wiu.h"
#endif /* _WIU */
#ifdef _TIM
#include "91x_tim.h"
#endif /* _TIM */
#ifdef _GPIO
#include "91x_gpio.h"
#endif /* _GPIO */
#ifdef _RTC
#include "91x_rtc.h"
#endif /* _RTC */
#ifdef _SCU
#include "91x_scu.h"
#endif /* _SCU */
#ifdef _UART
#include "91x_uart.h"
#endif /* _UART */
#ifdef _SSP
#include "91x_ssp.h"
#endif /* _SSP */
#ifdef _CAN
#include "91x_can.h"
#endif /* _CAN */
#ifdef _ADC
#include "91x_adc.h"
#endif /* _ADC */
#ifdef _WDG
#include "91x_wdg.h"
#endif /* _WDG */
#ifdef _I2C
#include "91x_i2c.h"
#endif /* _I2C */
#ifdef _WIU
#include "91x_wiu.h"
#endif
#ifdef _MC
#include "91x_mc.h"
#endif
#ifdef _ENET
#include "91x_enet.h"
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Module private variables --------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void debug( void );
#endif /* __91x_LIB_H */
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_map.h
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : Peripherals registers definition and memory mapping.
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion ------------------------------------ */
#ifndef __91x_MAP_H
#define __91x_MAP_H
#ifndef EXT
#define EXT extern
#endif /* EXT */
/* Includes ------------------------------------------------------------------*/
#include "91x_conf.h"
#include "91x_type.h"
/******************************************************************************/
/* IP registers structures */
/******************************************************************************/
/*------------------------------------ FMI -----------------------------------*/
typedef struct
{
vu32 BBSR; /* Boot Bank Size Register */
vu32 NBBSR; /* Non-Boot Bank Size Register */
vu32 EMPTY1;
vu32 BBADR; /* Boot Bank Base Address Register */
vu32 NBBADR; /* Non-Boot Bank Base Address Register */
vu32 EMPTY2;
vu32 CR; /* Control Register */
vu32 SR; /* Status Register */
vu32 BCE5ADDR; /* BC Fifth Entry Target Address Register */
} FMI_TypeDef;
/*---------------------- Analog to Digital Convertor ------------------------*/
typedef struct
{
vu16 CR; /* Control Register */
vu16 EMPTY1;
vu16 CCR; /* Channel Configuration Register */
vu16 EMPTY2;
vu16 HTR; /* Higher Threshold Register */
vu16 EMPTY3;
vu16 LTR; /* Lower Threshold Register */
vu16 EMPTY4;
vu16 CRR; /* Compare Result Register */
vu16 EMPTY5;
vu16 DR0; /* Data Register for Channel 0 */
vu16 EMPTY6;
vu16 DR1; /* Data Register for Channel 1 */
vu16 EMPTY7;
vu16 DR2; /* Data Register for Channel 2 */
vu16 EMPTY8;
vu16 DR3; /* Data Register for Channel 3 */
vu16 EMPTY9;
vu16 DR4; /* Data Register for Channel 4 */
vu16 EMPTY10;
vu16 DR5; /* Data Register for Channel 5 */
vu16 EMPTY11;
vu16 DR6; /* Data Register for Channel 6 */
vu16 EMPTY12;
vu16 DR7; /* Data Register for Channel 7 */
vu16 EMPTY13;
vu16 PRS; /* Prescaler Value Register */
vu16 EMPTY14;
} ADC_TypeDef;
/*--------------------- AHB APB BRIDGE registers strcture --------------------*/
typedef struct
{
vu32 BSR; /* Bridge Status Register */
vu32 BCR; /* Bridge Configuration Register */
vu32 PAER; /* Peripheral Address Error register */
} AHBAPB_TypeDef;
/*--------------- Controller Area Network Interface Register -----------------*/
typedef struct
{
vu16 CRR; /* IFn Command request Register */
vu16 EMPTY1;
vu16 CMR; /* IFn Command Mask Register */
vu16 EMPTY2;
vu16 M1R; /* IFn Message Mask 1 Register */
vu16 EMPTY3;
vu16 M2R; /* IFn Message Mask 2 Register */
vu16 EMPTY4;
vu16 A1R; /* IFn Message Arbitration 1 Register */
vu16 EMPTY5;
vu16 A2R; /* IFn Message Arbitration 2 Register */
vu16 EMPTY6;
vu16 MCR; /* IFn Message Control Register */
vu16 EMPTY7;
vu16 DA1R; /* IFn DATA A 1 Register */
vu16 EMPTY8;
vu16 DA2R; /* IFn DATA A 2 Register */
vu16 EMPTY9;
vu16 DB1R; /* IFn DATA B 1 Register */
vu16 EMPTY10;
vu16 DB2R; /* IFn DATA B 2 Register */
vu16 EMPTY11[27];
} CAN_MsgObj_TypeDef;
typedef struct
{
vu16 CR; /* Control Register */
vu16 EMPTY1;
vu16 SR; /* Status Register */
vu16 EMPTY2;
vu16 ERR; /* Error counter Register */
vu16 EMPTY3;
vu16 BTR; /* Bit Timing Register */
vu16 EMPTY4;
vu16 IDR; /* Interrupt Identifier Register */
vu16 EMPTY5;
vu16 TESTR; /* Test Register */
vu16 EMPTY6;
vu16 BRPR; /* BRP Extension Register */
vu16 EMPTY7[3];
CAN_MsgObj_TypeDef sMsgObj[2];
vu16 EMPTY8[16];
vu16 TXR1R; /* Transmission request 1 Register */
vu16 EMPTY9;
vu16 TXR2R; /* Transmission Request 2 Register */
vu16 EMPTY10[13];
vu16 ND1R; /* New Data 1 Register */
vu16 EMPTY11;
vu16 ND2R; /* New Data 2 Register */
vu16 EMPTY12[13];
vu16 IP1R; /* Interrupt Pending 1 Register */
vu16 EMPTY13;
vu16 IP2R; /* Interrupt Pending 2 Register */
vu16 EMPTY14[13];
vu16 MV1R; /* Message Valid 1 Register */
vu16 EMPTY15;
vu16 MV2R; /* Message VAlid 2 Register */
vu16 EMPTY16;
} CAN_TypeDef;
/*----------------------- System Control Unit---------------------------------*/
typedef struct
{
vu32 CLKCNTR; /* Clock Control Register */
vu32 PLLCONF; /* PLL Configuration Register */
vu32 SYSSTATUS; /* System Status Register */
vu32 PWRMNG; /* Power Management Register */
vu32 ITCMSK; /* Interrupt Mask Register */
vu32 PCGRO; /* Peripheral Clock Gating Register 0 */
vu32 PCGR1; /* Peripheral Clock Gating Register 1 */
vu32 PRR0; /* Peripheral Reset Register 0 */
vu32 PRR1; /* Peripheral Reset Register 1 */
vu32 MGR0; /* Idle Mode Mask Gating Register 0 */
vu32 MGR1; /* Idle Mode Mask Gating Register 1 */
vu32 PECGR0; /* Peripheral Emulation Clock Gating Register 0 */
vu32 PECGR1; /* Peripheral Emulation Clock Gating Register 1 */
vu32 SCR0; /* System Configuration Register 0 */
vu32 SCR1; /* System Configuration Register 1 */
vu32 SCR2; /* System Configuration Register 2 */
u32 EMPTY1;
vu32 GPIOOUT[8]; /* GPIO Output Registers */
vu32 GPIOIN[8]; /* GPIO Input Registers */
vu32 GPIOTYPE[10]; /* GPIO Type Registers */
vu32 GPIOEMI; /* GPIO EMI Selector Register */
vu32 WKUPSEL; /* Wake-Up Selection Register */
u32 EMPTY2[2];
vu32 GPIOANA; /* GPIO Analag mode Register */
} SCU_TypeDef;
/*------------------------- DMA Channelx Registers ---------------------------*/
typedef struct
{
vu32 SRC; /* Channelx Source Address Register */
vu32 DES; /* Channelx Destination Address Register */
vu32 LLI; /* Channelx Lincked List Item Register */
vu32 CC; /* Channelx Contol Register */
vu32 CCNF; /* Channelx Configuration Register */
} DMA_Channel_TypeDef;
/* x can be ,0,1,2,3,4,5,6 or 7. There are eight Channels AHB BUS Master */
/*----------------------------- DMA Controller -------------------------------*/
typedef struct
{
vu32 ISR; /* Interrupt Status Register */
vu32 TCISR; /* Terminal Count Interrupt Status Register */
vu32 TCICR; /* Terminal CountInterrupt Clear Register */
vu32 EISR; /* Error Interrupt Status Register */
vu32 EICR; /* Error Interrupt Clear Register */
vu32 TCRISR; /* Terminal Count Raw Interrupt Status Register */
vu32 ERISR; /* Raw Error Interrupt Status Register */
vu32 ENCSR; /* Enabled Channel Status Register */
vu32 SBRR; /* Software Burst Request Register */
vu32 SSRR; /* Software Single Request Register */
vu32 SLBRR; /* Software Last Burst Request Register */
vu32 SLSRR; /* Software Last Single Request Register */
vu32 CNFR; /* Configuration Register */
vu32 SYNR; /* Syncronization Register */
} DMA_TypeDef;
/*--------------------------------- TIM Timer --------------------------------*/
typedef struct
{
vu16 IC1R; /* Input Capture 1 Register */
vu16 EMPTY1;
vu16 IC2R; /* Input Capture 2 Register */
vu16 EMPTY2;
vu16 OC1R; /* Output Compare 1 Register */
vu16 EMPTY3;
vu16 OC2R; /* Output Compare 2 Register */
vu16 EMPTY4;
vu16 CNTR; /* Counter Register */
vu16 EMPTY5;
vu16 CR1; /* Control Register 1 */
vu16 EMPTY6;
vu16 CR2; /* Control Register 2 */
vu16 EMPTY7;
vu16 SR; /* Status Register */
vu16 EMPTY8;
} TIM_TypeDef;
/*---------------------------- EMI Bankx Registers ---------------------------*/
typedef struct
{
vu32 ICR; /* Bankx Idle Cycle Control Register */
vu32 RCR; /* Bankx Read Wait State Control Register */
vu32 WCR; /* Bankx Write Wait State Control Register */
vu32 OECR; /* Bankx Output Enable Assertion Delay Control Register */
vu32 WECR; /* Bankx Write Enable Assertion Delay Control Register */
vu32 BCR; /* Bankx Control Register */
} EMI_Bank_TypeDef;
/*---------------------------- Ethernet Controller ---------------------------*/
/* MAC Registers */
typedef struct
{
vu32 MCR; /* ENET Control Register */
vu32 MAH; /* ENET Address High Register */
vu32 MAL; /* ENET Address Low Register */
vu32 MCHA; /* Multicast Address High Register */
vu32 MCLA; /* Multicast Address Low Register */
vu32 MIIA; /* MII Address Register */
vu32 MIID; /* MII Data Register */
vu32 MCF; /* ENET Control Frame Register */
vu32 VL1; /* VLAN1 Register */
vu32 VL2; /* VLAN2 register */
vu32 MTS; /* ENET Transmission Status Register */
vu32 MRS; /* ENET Reception Status Register */
} ENET_MAC_TypeDef;
/* DMA Registers */
typedef struct
{
vu32 SCR; /* DMA Status and Control Register */
vu32 IER; /* DMA Interrupt Sources Enable Register */
vu32 ISR; /* DMA Interrupt Status Register */
vu32 CCR; /* Clock Control Relation : HCLK, PCLK and
ENET_CLK phase relations */
vu32 RXSTR; /* Rx DMA start Register */
vu32 RXCR; /* Rx DMA Control Register */
vu32 RXSAR; /* Rx DMA Base Address Register */
vu32 RXNDAR; /* Rx DMA Next Descriptor Address Register */
vu32 RXCAR; /* Rx DMA Current Address Register */
vu32 RXCTCR; /* Rx DMA Current Transfer Count Register */
vu32 RXTOR; /* Rx DMA FIFO Time Out Register */
vu32 RXSR; /* Rx DMA FIFO Status Register */
vu32 TXSTR; /* Tx DMA start Register */
vu32 TXCR; /* Tx DMA Control Register */
vu32 TXSAR; /* Tx DMA Base Address Register */
vu32 TXNDAR; /* Tx DMA Next Descriptor Address Register */
vu32 TXCAR; /* Tx DMA Current Address Register */
vu32 TXTCR; /* Tx DMA Current Transfer Count Register */
vu32 TXTOR; /* Tx DMA FIFO Time Out Register */
vu32 TXSR; /* Tx DMA FIFO Status Register */
} ENET_DMA_TypeDef;
/*------------------------------------- GPIO ---------------------------------*/
typedef struct
{
vu8 DR[1021]; /* Data Register */
vu32 DDR; /* Data Direction Register */
} GPIO_TypeDef;
/*-------------------------------- I2C interface -----------------------------*/
typedef struct
{
vu8 CR; /* Control Register */
vu8 EMPTY1[3];
vu8 SR1; /* Status Register 1 */
vu8 EMPTY2[3];
vu8 SR2; /* Status Register 2 */
vu8 EMPTY3[3];
vu8 CCR; /* Clock Control Register */
vu8 EMPTY4[3];
vu8 OAR1; /* Own Address Register 1 */
vu8 EMPTY5[3];
vu8 OAR2; /* Own Address Register 2 */
vu8 EMPTY6[3];
vu8 DR; /* Data Register */
vu8 EMPTY7[3];
vu8 ECCR; /* Extended Clock Control Register */
vu8 EMPTY8[3];
} I2C_TypeDef;
/*------------------------------------- VIC ----------------------------------*/
typedef struct
{
vu32 ISR; /* IRQ Status Register */
vu32 FSR; /* FIQ Status Register */
vu32 RINTSR; /* Raw Interrupt Status Register */
vu32 INTSR; /* Interrupt Select Register */
vu32 INTER; /* Interrupt Enable Register */
vu32 INTECR; /* Interrupt Enable Clear Register */
vu32 SWINTR; /* Software Interrupt Register */
vu32 SWINTCR; /* Software Interrupt clear Register */
vu32 PER; /* Protection Enable Register */
vu32 EMPTY1[3];
vu32 VAR; /* Vector Address Register */
vu32 DVAR; /* Default Vector Address Register */
vu32 EMPTY2[50];
vu32 VAiR[16]; /* Vector Address 0-15 Register */
vu32 EMPTY3[48];
vu32 VCiR[16]; /* Vector Control 0-15 Register */
} VIC_TypeDef;
/*-------------------------------- Motor Control -----------------------------*/
typedef struct
{
vu16 TCPT; /* Tacho Capture Register */
vu16 EMPTY1;
vu16 TCMP; /* Tacho Compare Register */
vu16 EMPTY2;
vu16 IPR; /* Input Pending Register */
vu16 EMPTY3;
vu16 TPRS; /* Tacho Prescaler Register */
vu16 EMPTY4;
vu16 CPRS; /* PWM Counter Prescaler Register */
vu16 EMPTY5;
vu16 REP; /* Repetition Counter Register */
vu16 EMPTY6;
vu16 CMPW; /* Compare Phase W Preload Register */
vu16 EMPTY7;
vu16 CMPV; /* Compare Phase V Preload Register */
vu16 EMPTY8;
vu16 CMPU; /* Compare Phase U Preload Register */
vu16 EMPTY9;
vu16 CMP0; /* Compare 0 Preload Register */
vu16 EMPTY10;
vu16 PCR0; /* Peripheral Control Register 0 */
vu16 EMPTY11;
vu16 PCR1; /* Peripheral Control Register 1 */
vu16 EMPTY12;
vu16 PCR2; /* Peripheral Control Register 2 */
vu16 EMPTY13;
vu16 PSR; /* Polarity Selection Register */
vu16 EMPTY14;
vu16 OPR; /* Output Peripheral Register */
vu16 EMPTY15;
vu16 IMR; /* Interrupt Mask Register */
vu16 EMPTY16;
vu16 DTG; /* Dead Time Generator Register */
vu16 EMPTY17;
vu16 ESC; /* Emergency Stop Clear Register */
vu16 EMPTY18;
}MC_TypeDef;
/*------------------------------------- RTC ----------------------------------*/
typedef struct
{
vu32 TR; /* Time Register */
vu32 DTR; /* Date Register */
vu32 ATR; /* Alarm time Register */
vu32 CR; /* Control Register */
vu32 SR; /* Status Register */
vu32 MILR; /* Millisec Register */
}RTC_TypeDef;
/*------------------------------------- SSP ----------------------------------*/
typedef struct
{
vu16 CR0; /* Control Register 1 */
vu16 EMPTY1;
vu16 CR1; /* Control Register 2 */
vu16 EMPTY2;
vu16 DR; /* Data Register */
vu16 EMPTY3;
vu16 SR; /* Status Register */
vu16 EMPTY4;
vu16 PR; /* Clock Prescale Register */
vu16 EMPTY5;
vu16 IMSCR; /* Interrupt Mask Set or Clear Register */
vu16 EMPTY6;
vu16 RISR; /* Raw Interrupt Status Register */
vu16 EMPTY7;
vu16 MISR; /* Masked Interrupt Status Register */
vu16 EMPTY8;
vu16 ICR; /* Interrupt Clear Register */
vu16 EMPTY9;
vu16 DMACR; /* DMA Control Register */
vu16 EMPTY10;
}SSP_TypeDef;
/*------------------------------------ UART ----------------------------------*/
typedef struct
{
vu16 DR; /* Data Register */
vu16 EMPTY1;
vu16 RSECR; /* Receive Status Register (read)/Error Clear Register (write) */
vu16 EMPTY2[9];
vu16 FR; /* Flag Register */
vu16 EMPTY3[3];
vu16 ILPR; /* IrDA Low-Power counter Register */
vu16 EMPTY4;
vu16 IBRD; /* Integer Baud Rate Divisor Register */
vu16 EMPTY5;
vu16 FBRD; /* Fractional Baud Rate Divisor Register */
vu16 EMPTY6;
vu16 LCR; /* Line Control Register, High byte */
vu16 EMPTY7;
vu16 CR; /* Control Register */
vu16 EMPTY8;
vu16 IFLS; /* Interrupt FIFO Level Select Register */
vu16 EMPTY9;
vu16 IMSC; /* Interrupt Mask Set/Clear Register */
vu16 EMPTY10;
vu16 RIS; /* Raw Interrupt Status Register */
vu16 EMPTY11;
vu16 MIS; /* Masked Interrupt Status Register */
vu16 EMPTY12;
vu16 ICR; /* Interrupt Clear Register */
vu16 EMPTY13;
vu16 DMACR; /* DMA Control Register */
vu16 EMPTY14;
}UART_TypeDef;
/*------------------------------- Wake-up System -----------------------------*/
typedef struct
{
vu32 CTRL; /* Control Register */
vu32 MR; /* Mask Register */
vu32 TR; /* Trigger Register */
vu32 PR; /* Pending Register */
vu32 INTR; /* Software Interrupt Register */
} WIU_TypeDef;
/*------------------------------- WatchDog Timer -----------------------------*/
typedef struct
{
vu16 CR; /* Control Register */
vu16 EMPTY1;
vu16 PR; /* Presclar Register */
vu16 EMPTY2;
vu16 VR; /* Pre-load Value Register */
vu16 EMPTY3;
vu16 CNT; /* Counter Register */
vu16 EMPTY4;
vu16 SR; /* Status Register */
vu16 EMPTY5;
vu16 MR; /* Mask Register */
vu16 EMPTY6;
vu16 KR; /* Key Register */
vu16 EMPTY7;
} WDG_TypeDef;
/*******************************************************************************
* Memory Mapping of STR91x *
*******************************************************************************/
#define AHB_APB_BRDG0_U (0x58000000) /* AHB/APB Bridge 0 UnBuffered Space */
#define AHB_APB_BRDG0_B (0x48000000) /* AHB/APB Bridge 0 Buffered Space */
#define AHB_APB_BRDG1_U (0x5C000000) /* AHB/APB Bridge 1 UnBuffered Space */
#define AHB_APB_BRDG1_B (0x4C000000) /* AHB/APB Bridge 1 Buffered Space */
#define AHB_EMI_U (0x74000000) /* EMI UnBuffered Space */
#define AHB_EMI_B (0x64000000) /* EMI Buffered Space */
#define AHB_DMA_U (0x78000000) /* DMA UnBuffered Space */
#define AHB_DMA_B (0x68000000) /* DMA Buffered Space */
#define AHB_ENET_MAC_U (0x7C000400) /* ENET_MAC UnBuffered Space */
#define AHB_ENET_MAC_B (0x6C000000) /* ENET_MAC Buffered Space */
#define AHB_ENET_DMA_U (0x7C000000) /* ENET_DMA Unbuffered Space */
#define AHB_ENET_DMA_B (0x6C000400) /* ENET_DMA Buffered Space */
#define AHB_VIC1_U (0xFC000000) /* Secondary VIC1 UnBuffered Space */
#define AHB_VIC0_U (0xFFFFF000) /* Primary VIC0 UnBuffered Space */
#define AHB_FMI_U (0x54000000) /* FMI Unbuffered Space */
#define AHB_FMI_B (0x44000000) /* FMI buffered Space */
/*******************************************************************************
* Addresses related to the VICs' peripherals *
*******************************************************************************/
#define VIC0_BASE (AHB_VIC0_U)
#define VIC1_BASE (AHB_VIC1_U)
/*******************************************************************************
* Addresses related to the EMI banks *
*******************************************************************************/
#define AHB_EMIB3_OFST (0x00000040) /* Offset of EMI bank3 */
#define AHB_EMIB2_OFST (0x00000020) /* Offset of EMI bank2 */
#define AHB_EMIB1_OFST (0x00000000) /* Offset of EMI bank1 */
#define AHB_EMIB0_OFST (0x000000E0) /* Offset of EMI bank0 */
/*******************************************************************************
* Addresses related to the DMA peripheral *
*******************************************************************************/
#define AHB_DMA_Channel0_OFST (0x00000100) /* Offset of Channel 0 */
#define AHB_DMA_Channel1_OFST (0x00000120) /* Offset of Channel 1 */
#define AHB_DMA_Channel2_OFST (0x00000140) /* Offset of Channel 2 */
#define AHB_DMA_Channel3_OFST (0x00000160) /* Offset of Channel 3 */
#define AHB_DMA_Channel4_OFST (0x00000180) /* Offset of Channel 4 */
#define AHB_DMA_Channel5_OFST (0x000001A0) /* Offset of Channel 5 */
#define AHB_DMA_Channel6_OFST (0x000001C0) /* Offset of Channel 6 */
#define AHB_DMA_Channel7_OFST (0x000001E0) /* Offset of Channel 7 */
/*******************************************************************************
* Addresses related to the APB0 sub-system *
*******************************************************************************/
#define APB_WIU_OFST (0x00001000) /* Offset of WIU */
#define APB_TIM0_OFST (0x00002000) /* Offset of TIM0 */
#define APB_TIM1_OFST (0x00003000) /* Offset of TIM1 */
#define APB_TIM2_OFST (0x00004000) /* Offset of TIM2 */
#define APB_TIM3_OFST (0x00005000) /* Offset of TIM3 */
#define APB_GPIO0_OFST (0x00006000) /* Offset of GPIO0 */
#define APB_GPIO1_OFST (0x00007000) /* Offset of GPIO1 */
#define APB_GPIO2_OFST (0x00008000) /* Offset of GPIO2 */
#define APB_GPIO3_OFST (0x00009000) /* Offset of GPIO3 */
#define APB_GPIO4_OFST (0x0000A000) /* Offset of GPIO4 */
#define APB_GPIO5_OFST (0x0000B000) /* Offset of GPIO5 */
#define APB_GPIO6_OFST (0x0000C000) /* Offset of GPIO6 */
#define APB_GPIO7_OFST (0x0000D000) /* Offset of GPIO7 */
#define APB_GPIO8_OFST (0x0000E000) /* Offset of GPIO8 */
#define APB_GPIO9_OFST (0x0000F000) /* Offset of GPIO9 */
/*******************************************************************************
* Addresses related to the APB1 sub-system *
*******************************************************************************/
#define APB_RTC_OFST (0x00001000) /* Offset of RTC */
#define APB_SCU_OFST (0x00002000) /* Offset of System Controller */
#define APB_MC_OFST (0x00003000) /* Offset of Motor Control */
#define APB_UART0_OFST (0x00004000) /* Offset of UART0 */
#define APB_UART1_OFST (0x00005000) /* Offset of UART1 */
#define APB_UART2_OFST (0x00006000) /* Offset of UART2 */
#define APB_SSP0_OFST (0x00007000) /* Offset of SSP0 */
#define APB_SSP1_OFST (0x00008000) /* Offset of SSPI */
#define APB_CAN_OFST (0x00009000) /* Offset of CAN */
#define APB_ADC_OFST (0x0000A000) /* Offset of ADC */
#define APB_WDG_OFST (0x0000B000) /* Offset of WDG */
#define APB_I2C0_OFST (0x0000C000) /* Offset of I2C0 */
#define APB_I2C1_OFST (0x0000D000) /* Offset of I2C1 */
/*----------------------------------------------------------------------------*/
/*----------------------------- Unbuffered Mode ------------------------------*/
/*----------------------------------------------------------------------------*/
#ifndef Buffered
/*******************************************************************************
* AHBAPB peripheral Unbuffered Base Address *
*******************************************************************************/
#define AHBAPB0_BASE (AHB_APB_BRDG0_U)
#define AHBAPB1_BASE (AHB_APB_BRDG1_U)
/*******************************************************************************
* ENET peripheral Unbuffered Base Address *
*******************************************************************************/
#define ENET_MAC_BASE (AHB_ENET_MAC_U)
#define ENET_DMA_BASE (AHB_ENET_DMA_U)
/*******************************************************************************
* DMA peripheral Unbuffered Base Address *
*******************************************************************************/
#define DMA_BASE (AHB_DMA_U)
/*******************************************************************************
* EMI peripheral Unbuffered Base Address *
*******************************************************************************/
#define EMI_BASE (AHB_EMI_U)
/*******************************************************************************
* FMI peripheral Unbuffered Base Address *
*******************************************************************************/
#define FMI_BASE (AHB_FMI_U)
#else /* Buffered */
/*----------------------------------------------------------------------------*/
/*------------------------------ Buffered Mode -------------------------------*/
/*----------------------------------------------------------------------------*/
/*******************************************************************************
* AHBAPB peripheral Buffered Base Address *
*******************************************************************************/
#define AHBAPB0_BASE (AHB_APB_BRDG0_B)
#define AHBAPB1_BASE (AHB_APB_BRDG1_B)
/*******************************************************************************
* ENET peripheral Unbuffered Base Address *
*******************************************************************************/
#define ENET_MAC_BASE (AHB_ENET_MAC_B)
#define ENET_DMA_BASE (AHB_ENET_DMA_B)
/*******************************************************************************
* DMA peripheral Buffered Base Address *
*******************************************************************************/
#define DMA_BASE (AHB_DMA_B)
/*******************************************************************************
* EMI peripheral Buffered Base Address *
*******************************************************************************/
#define EMI_BASE (AHB_EMI_B)
/*******************************************************************************
* FMI peripheral Buffered Base Address *
*******************************************************************************/
#define FMI_BASE (AHB_FMI_B)
#endif /* Buffered */
/*******************************************************************************
* DMA channels Base Address *
*******************************************************************************/
#define DMA_Channel0_BASE (DMA_BASE + AHB_DMA_Channel0_OFST)
#define DMA_Channel1_BASE (DMA_BASE + AHB_DMA_Channel1_OFST)
#define DMA_Channel2_BASE (DMA_BASE + AHB_DMA_Channel2_OFST)
#define DMA_Channel3_BASE (DMA_BASE + AHB_DMA_Channel3_OFST)
#define DMA_Channel4_BASE (DMA_BASE + AHB_DMA_Channel4_OFST)
#define DMA_Channel5_BASE (DMA_BASE + AHB_DMA_Channel5_OFST)
#define DMA_Channel6_BASE (DMA_BASE + AHB_DMA_Channel6_OFST)
#define DMA_Channel7_BASE (DMA_BASE + AHB_DMA_Channel7_OFST)
/*******************************************************************************
* EMI Banks peripheral Base Address *
*******************************************************************************/
#define EMI_Bank0_BASE (EMI_BASE + AHB_EMIB0_OFST)
#define EMI_Bank1_BASE (EMI_BASE + AHB_EMIB1_OFST)
#define EMI_Bank2_BASE (EMI_BASE + AHB_EMIB2_OFST)
#define EMI_Bank3_BASE (EMI_BASE + AHB_EMIB3_OFST)
/*******************************************************************************
* APB0 Peripherals' Base addresses *
*******************************************************************************/
#define WIU_BASE (AHBAPB0_BASE + APB_WIU_OFST)
#define TIM0_BASE (AHBAPB0_BASE + APB_TIM0_OFST)
#define TIM1_BASE (AHBAPB0_BASE + APB_TIM1_OFST)
#define TIM2_BASE (AHBAPB0_BASE + APB_TIM2_OFST)
#define TIM3_BASE (AHBAPB0_BASE + APB_TIM3_OFST)
#define GPIO0_BASE (AHBAPB0_BASE + APB_GPIO0_OFST)
#define GPIO1_BASE (AHBAPB0_BASE + APB_GPIO1_OFST)
#define GPIO2_BASE (AHBAPB0_BASE + APB_GPIO2_OFST)
#define GPIO3_BASE (AHBAPB0_BASE + APB_GPIO3_OFST)
#define GPIO4_BASE (AHBAPB0_BASE + APB_GPIO4_OFST)
#define GPIO5_BASE (AHBAPB0_BASE + APB_GPIO5_OFST)
#define GPIO6_BASE (AHBAPB0_BASE + APB_GPIO6_OFST)
#define GPIO7_BASE (AHBAPB0_BASE + APB_GPIO7_OFST)
#define GPIO8_BASE (AHBAPB0_BASE + APB_GPIO8_OFST)
#define GPIO9_BASE (AHBAPB0_BASE + APB_GPIO9_OFST)
/*******************************************************************************
* APB1 Peripherals' Base addresses *
*******************************************************************************/
#define RTC_BASE (AHBAPB1_BASE + APB_RTC_OFST)
#define SCU_BASE (AHBAPB1_BASE + APB_SCU_OFST)
#define MC_BASE (AHBAPB1_BASE + APB_MC_OFST)
#define UART0_BASE (AHBAPB1_BASE + APB_UART0_OFST)
#define UART1_BASE (AHBAPB1_BASE + APB_UART1_OFST)
#define UART2_BASE (AHBAPB1_BASE + APB_UART2_OFST)
#define SSP0_BASE (AHBAPB1_BASE + APB_SSP0_OFST)
#define SSP1_BASE (AHBAPB1_BASE + APB_SSP1_OFST)
#define CAN_BASE (AHBAPB1_BASE + APB_CAN_OFST)
#define ADC_BASE (AHBAPB1_BASE + APB_ADC_OFST)
#define WDG_BASE (AHBAPB1_BASE + APB_WDG_OFST)
#define I2C0_BASE (AHBAPB1_BASE + APB_I2C0_OFST)
#define I2C1_BASE (AHBAPB1_BASE + APB_I2C1_OFST)
/*******************************************************************************
* IPs' declaration *
*******************************************************************************/
/*------------------------------ Non Debug Mode ------------------------------*/
#ifndef DEBUG
/*********************************** AHBAPB ***********************************/
#define AHBAPB0 ((AHBAPB_TypeDef *)AHBAPB0_BASE)
#define AHBAPB1 ((AHBAPB_TypeDef *)AHBAPB1_BASE)
/************************************* EMI ************************************/
#define EMI ((EMI_TypeDef *)EMI_BASE)
/************************************* DMA ************************************/
#define DMA ((DMA_TypeDef *)DMA_BASE)
#define DMA_Channel0 ((DMA_Channel_TypeDef *)DMA_Channel0_BASE)
#define DMA_Channel1 ((DMA_Channel_TypeDef *)DMA_Channel1_BASE)
#define DMA_Channel2 ((DMA_Channel_TypeDef *)DMA_Channel2_BASE)
#define DMA_Channel3 ((DMA_Channel_TypeDef *)DMA_Channel3_BASE)
#define DMA_Channel4 ((DMA_Channel_TypeDef *)DMA_Channel4_BASE)
#define DMA_Channel5 ((DMA_Channel_TypeDef *)DMA_Channel5_BASE)
#define DMA_Channel6 ((DMA_Channel_TypeDef *)DMA_Channel6_BASE)
#define DMA_Channel7 ((DMA_Channel_TypeDef *)DMA_Channel7_BASE)
/************************************* EMI ************************************/
#define EMI_Bank0 ((EMI_Bank_TypeDef *)EMI_Bank0_BASE)
#define EMI_Bank1 ((EMI_Bank_TypeDef *)EMI_Bank1_BASE)
#define EMI_Bank2 ((EMI_Bank_TypeDef *)EMI_Bank2_BASE)
#define EMI_Bank3 ((EMI_Bank_TypeDef *)EMI_Bank3_BASE)
/************************************* ENET_MAC ************************************/
#define ENET_MAC ((ENET_MAC_TypeDef *)ENET_MAC_BASE)
/************************************* ENET_DMA ************************************/
#define ENET_DMA ((ENET_DMA_TypeDef *)ENET_DMA_BASE)
/************************************* FMI ************************************/
#define FMI ((FMI_TypeDef *)FMI_BASE)
/************************************* VIC ************************************/
#define VIC0 ((VIC_TypeDef *)VIC0_BASE)
#define VIC1 ((VIC_TypeDef *)VIC1_BASE)
/*******************************************************************************
* APB0 Peripherals' *
*******************************************************************************/
#define WIU ((WIU_TypeDef *)WIU_BASE)
#define TIM0 ((TIM_TypeDef *)TIM0_BASE)
#define TIM1 ((TIM_TypeDef *)TIM1_BASE)
#define TIM2 ((TIM_TypeDef *)TIM2_BASE)
#define TIM3 ((TIM_TypeDef *)TIM3_BASE)
#define GPIO0 ((GPIO_TypeDef *)GPIO0_BASE)
#define GPIO1 ((GPIO_TypeDef *)GPIO1_BASE)
#define GPIO2 ((GPIO_TypeDef *)GPIO2_BASE)
#define GPIO3 ((GPIO_TypeDef *)GPIO3_BASE)
#define GPIO4 ((GPIO_TypeDef *)GPIO4_BASE)
#define GPIO5 ((GPIO_TypeDef *)GPIO5_BASE)
#define GPIO6 ((GPIO_TypeDef *)GPIO6_BASE)
#define GPIO7 ((GPIO_TypeDef *)GPIO7_BASE)
#define GPIO8 ((GPIO_TypeDef *)GPIO8_BASE)
#define GPIO9 ((GPIO_TypeDef *)GPIO9_BASE)
/*******************************************************************************
* APB1 Peripherals' *
*******************************************************************************/
#define RTC ((RTC_TypeDef *)RTC_BASE)
#define SCU ((SCU_TypeDef *)SCU_BASE)
#define MC ((MC_TypeDef *)MC_BASE)
#define UART0 ((UART_TypeDef *)UART0_BASE)
#define UART1 ((UART_TypeDef *)UART1_BASE)
#define UART2 ((UART_TypeDef *)UART2_BASE)
#define SSP0 ((SSP_TypeDef *)SSP0_BASE)
#define SSP1 ((SSP_TypeDef *)SSP1_BASE)
#define CAN ((CAN_TypeDef *)CAN_BASE)
#define ADC ((ADC_TypeDef *)ADC_BASE)
#define WDG ((WDG_TypeDef *)WDG_BASE)
#define I2C0 ((I2C_TypeDef *)I2C0_BASE)
#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
#define ENET_MAC ((ENET_MAC_TypeDef *)ENET_MAC_BASE)
#define ENET_DMA ((ENET_DMA_TypeDef *)ENET_DMA_BASE)
#else /* DEBUG */
/*-------------------------------- Debug Mode --------------------------------*/
EXT AHBAPB_TypeDef *AHBAPB0;
EXT AHBAPB_TypeDef *AHBAPB1;
EXT DMA_TypeDef *DMA;
EXT DMA_Channel_TypeDef *DMA_Channel0;
EXT DMA_Channel_TypeDef *DMA_Channel1;
EXT DMA_Channel_TypeDef *DMA_Channel2;
EXT DMA_Channel_TypeDef *DMA_Channel3;
EXT DMA_Channel_TypeDef *DMA_Channel4;
EXT DMA_Channel_TypeDef *DMA_Channel5;
EXT DMA_Channel_TypeDef *DMA_Channel6;
EXT DMA_Channel_TypeDef *DMA_Channel7;
EXT EMI_Bank_TypeDef *EMI_Bank0;
EXT EMI_Bank_TypeDef *EMI_Bank1;
EXT EMI_Bank_TypeDef *EMI_Bank2;
EXT EMI_Bank_TypeDef *EMI_Bank3;
EXT FMI_TypeDef *FMI;
EXT VIC_TypeDef *VIC0;
EXT VIC_TypeDef *VIC1;
EXT WIU_TypeDef *WIU;
EXT TIM_TypeDef *TIM0;
EXT TIM_TypeDef *TIM1;
EXT TIM_TypeDef *TIM2;
EXT TIM_TypeDef *TIM3;
EXT GPIO_TypeDef *GPIO0;
EXT GPIO_TypeDef *GPIO1;
EXT GPIO_TypeDef *GPIO2;
EXT GPIO_TypeDef *GPIO3;
EXT GPIO_TypeDef *GPIO4;
EXT GPIO_TypeDef *GPIO5;
EXT GPIO_TypeDef *GPIO6;
EXT GPIO_TypeDef *GPIO7;
EXT GPIO_TypeDef *GPIO8;
EXT GPIO_TypeDef *GPIO9;
EXT RTC_TypeDef *RTC;
EXT SCU_TypeDef *SCU;
EXT MC_TypeDef *MC;
EXT UART_TypeDef *UART0;
EXT UART_TypeDef *UART1;
EXT UART_TypeDef *UART2;
EXT SSP_TypeDef *SSP0;
EXT SSP_TypeDef *SSP1;
EXT CAN_TypeDef *CAN;
EXT ADC_TypeDef *ADC;
EXT WDG_TypeDef *WDG;
EXT I2C_TypeDef *I2C0;
EXT I2C_TypeDef *I2C1;
EXT ENET_MAC_TypeDef *ENET_MAC;
EXT ENET_DMA_TypeDef *ENET_DMA;
#endif /* DEBUG */
#endif /* __91x_MAP_H*/
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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Demo/ARM9_STR91X_IAR/Library/include/91x_scu.h
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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_scu.h
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : This file provides the SCU library software functions
* prototypes & definitions
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __91x_SCU_H
#define __91x_SCU_H
/* Includes ------------------------------------------------------------------*/
#include "91x_map.h"
/* Exported constants --------------------------------------------------------*/
/*MCLK_Source*/
#define SCU_MCLK_PLL 0x0
#define SCU_MCLK_RTC 0x1
#define SCU_MCLK_OSC 0x2
/*RCLK_Divisor*/
#define SCU_RCLK_Div1 0xFFFFFFE3
#define SCU_RCLK_Div2 0x4
#define SCU_RCLK_Div4 0x8
#define SCU_RCLK_Div8 0xC
#define SCU_RCLK_Div16 0x10
#define SCU_RCLK_Div1024 0x14
/*HCLK_Divisor*/
#define SCU_HCLK_Div1 0xFFFFFF9F
#define SCU_HCLK_Div2 0x20
#define SCU_HCLK_Div4 0x40
/*PCLK_Divisor*/
#define SCU_PCLK_Div1 0xFFFFFE7F
#define SCU_PCLK_Div2 0x80
#define SCU_PCLK_Div4 0x100
#define SCU_PCLK_Div8 0x180
/*FMICLK_Divisor*/
#define SCU_FMICLK_Div1 0xFFFEFFFF
#define SCU_FMICLK_Div2 0x10000
/*BRCLK_Divisor*/
#define SCU_BRCLK_Div1 0xFFFFFDFF
#define SCU_BRCLK_Div2 0x200
/*TIMCLK_Source*/
#define SCU_TIMCLK_EXT 0x1
#define SCU_TIMCLK_INT 0x0
/*TIMx*/
#define SCU_TIM01 0x0
#define SCU_TIM23 0x1
/*USBCLK_Source*/
#define SCU_USBCLK_MCLK 0xFFFFF3FF
#define SCU_USBCLK_MCLK2 0x400
#define SCU_USBCLK_EXT 0x800
/*SCU_EMIBCLK*/
#define SCU_EMIBCLK_Div1 0xFFF9FFFF
#define SCU_EMIBCLK_Div2 0x20000
/*SCU_EMIMODE*/
#define SCU_EMI_MUX 0xFFFFFFBF
#define SCU_EMI_DEMUX 0x40
/*SCU_EMIALE_LEN*/
#define SCU_EMIALE_LEN1 0xFFFFFEFF
#define SCU_EMIALE_LEN2 0x100
/*SCU_EMIALE_POL*/
#define SCU_EMIALE_POLLow 0xFFFFFF7F
#define SCU_EMIALE_POLHigh 0x80
/*UART_IrDA_Mode*/
#define SCU_UARTMode_IrDA 0x1
#define SCU_UARTMode_UART 0x0
/*APBPeriph*/
#define __TIM01 0x1
#define __TIM23 0x2
#define __MC 0x4
#define __UART0 0x8
#define __UART1 0x10
#define __UART2 0x20
#define __I2C0 0x40
#define __I2C1 0x80
#define __SSP0 0x100
#define __SSP1 0x200
#define __CAN 0x400
#define __ADC 0x800
#define __WDG 0x1000
#define __WIU 0x2000
#define __GPIO0 0x4000
#define __GPIO1 0x8000
#define __GPIO2 0x10000
#define __GPIO3 0x20000
#define __GPIO4 0x40000
#define __GPIO5 0x80000
#define __GPIO6 0x100000
#define __GPIO7 0x200000
#define __GPIO8 0x400000
#define __GPIO9 0x800000
#define __RTC 0x1000000
/*AHBPeriph*/
#define __FMI 0x1
#define __FPQBC 0x2
#define __SRAM 0x8
#define __SRAM_ARBITER 0x10
#define __VIC 0x20
#define __EMI 0x40
#define __EMI_MEM_CLK 0x80
#define __DMA 0x100
#define __USB 0x200
#define __USB48M 0x400
#define __ENET 0x800
#define __PFQBC_AHB 0x1000
/*SCU_IT*/
#define SCU_IT_LVD_RST 0x10
#define SCU_IT_SRAM_ERROR 0x8
#define SCU_IT_ACK_PFQBC 0x4
#define SCU_IT_LOCK_LOST 0x2
#define SCU_IT_LOCK 0x1
/*SCU_FLAG*/
#define SCU_FLAG_SRAM_ERROR 0x20
#define SCU_FLAG_ACK_PFQBC 0x10
#define SCU_FLAG_LVD_RESET 0x8
#define SCU_FLAG_WDG_RST 0x4
#define SCU_FLAG_LOCK_LOST 0x2
#define SCU_FLAG_LOCK 0x1
/* Module private variables --------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
ErrorStatus SCU_MCLKSourceConfig(u32 MCLK_Source);
ErrorStatus SCU_PLLFactorsConfig(u8 PLLN, u8 PLLM, u8 PLLP);
ErrorStatus SCU_PLLCmd(FunctionalState NewState);
void SCU_RCLKDivisorConfig(u32 RCLK_Divisor);
void SCU_HCLKDivisorConfig(u32 HCLK_Divisor);
void SCU_PCLKDivisorConfig(u32 PCLK_Divisor);
void SCU_APBPeriphClockConfig(u32 APBPeriph, FunctionalState NewState);
void SCU_AHBPeriphClockConfig(u32 AHBPeriph, FunctionalState NewState);
void SCU_APBPeriphReset(u32 APBPeriph, FunctionalState NewState);
void SCU_AHBPeriphReset(u32 AHBPeriph, FunctionalState NewState);
void SCU_APBPeriphIdleConfig(u32 APBPeriph, FunctionalState NewState);
void SCU_AHBPeriphIdleConfig(u32 AHBPeriph, FunctionalState NewState);
void SCU_APBPeriphDebugConfig(u32 APBPeriph, FunctionalState NewState);
void SCU_AHBPeriphDebugConfig(u32 AHBPeriph, FunctionalState NewState);
void SCU_BRCLKDivisorConfig(u32 BRCLK_Divisor);
void SCU_TIMCLKSourceConfig(u8 TIMx, u32 TIMCLK_Source);
void SCU_TIMPresConfig(u8 TIMx, u16 Prescaler);
void SCU_USBCLKConfig(u32 USBCLK_Source);
void SCU_PHYCLKConfig(FunctionalState NewState);
void SCU_FMICLKDivisorConfig(u32 FMICLK_Divisor);
void SCU_EMIBCLKDivisorConfig(u32 SCU_EMIBCLK);
void SCU_EMIModeConfig(u32 SCU_EMIMODE);
void SCU_EMIALEConfig(u32 SCU_EMIALE_LEN, u32 SCU_EMIALE_POL);
void SCU_ITConfig(u32 SCU_IT, FunctionalState NewState);
FlagStatus SCU_GetFlagStatus(u32 SCU_Flag);
void SCU_ClearFlag(u32 SCU_Flag);
u32 SCU_GetPLLFreqValue(void);
u32 SCU_GetMCLKFreqValue(void);
u32 SCU_GetRCLKFreqValue(void);
u32 SCU_GetHCLKFreqValue(void);
u32 SCU_GetPCLKFreqValue(void);
void SCU_WakeUpLineConfig(u8 EXTint);
void SCU_SpecIntRunModeConfig(FunctionalState NewState);
void SCU_EnterIdleMode(void);
void SCU_EnterSleepMode(void);
void SCU_UARTIrDASelect(UART_TypeDef * UARTx, u8 UART_IrDA_Mode);
void SCU_PFQBCCmd(FunctionalState NewState);
#endif /*__91x_SCU_H*/
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_tim.h
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : This file contains all the functions prototypes for the
* TIM software library.
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __91x_TIM_H
#define __91x_TIM_H
/* Includes ------------------------------------------------------------------*/
#include "91x_map.h"
#include "91x_scu.h"
/* Exported types ----------------------------------------------------------- */
/* TIM Init structure define */
typedef struct
{
u16 TIM_Mode; /* Timer mode */
u16 TIM_OC1_Modes; /* Output Compare 1 Mode: Timing or Wave */
u16 TIM_OC2_Modes; /* Output Compare 2 Mode: Timing or Wave */
u16 TIM_Clock_Source; /* Timer Clock source APB/SCU/EXTERNAL */
u16 TIM_Clock_Edge; /* Timer Clock Edge: Rising or Falling Edge */
u16 TIM_OPM_INPUT_Edge; /* Timer Input Capture 1 Edge used in OPM Mode */
u16 TIM_ICAP1_Edge; /* Timer Input Capture 1 Edge used in ICAP1 Mode */
u16 TIM_ICAP2_Edge; /* Timer Input Capture 2 Edge used in ICAP2 Mode */
u8 TIM_Prescaler; /* Timer Prescaler factor */
u16 TIM_Pulse_Level_1; /* Level applied on the Output Compare Pin 1 */
u16 TIM_Pulse_Level_2; /* Level applied on the Output Compare Pin 2 */
u16 TIM_Period_Level; /* Level applied during the Period of a PWM Mode */
u16 TIM_Pulse_Length_1; /* Pulse 1 Length used in Output Compare 1 Mode */
u16 TIM_Pulse_Length_2; /* Pulse 2 Length used in Output Compare 2 Mode */
u16 TIM_Full_Period; /* Period Length used in PWM Mode */
} TIM_InitTypeDef;
typedef enum
{
TIM_START,
TIM_STOP,
TIM_CLEAR
} TIM_CounterOperations;
/* Exported constants --------------------------------------------------------*/
/* TIM MODE */
#define TIM_PWMI 0x4000 /* PWM INPUT Mode */
#define TIM_OCM_CHANNEL_1 0x0040 /* OUTPUT COMPARE CHANNEL 1 Mode */
#define TIM_OCM_CHANNEL_2 0x0080 /* OUTPUT COMPARE CHANNEL 2 Mode */
#define TIM_OCM_CHANNEL_12 0x00C0 /* OUTPUT COMPARE CHANNEL 1 & 2 Mode */
#define TIM_PWM 0x0010 /* PWM Mode */
#define TIM_OPM 0x0020 /* ONE PULSE Mode */
#define TIM_ICAP_CHANNEL_1 0x0400 /* INPUT CAPTURE 1 Mode */
#define TIM_ICAP_CHANNEL_2 0x0500 /* INPUT CAPTURE 2 Mode */
#define TIM_ICAP_CHANNEL_12 0x0600 /* INPUT CAPTURE 1 & 2 Mode */
/* TIM OUTPUT COMPARE MODE */
#define TIM_WAVE 0x0001
#define TIM_TIMING 0x0002
/* TIM CLOCK SOURCE */
#define TIM_CLK_APB 0xFFFE
#define TIM_CLK_EXTERNAL 0x0001
#define TIM_CLK_SCU 0x0001
/* TIM CLOCK EDGE */
#define TIM_CLK_EDGE_FALLING 0xFFFD
#define TIM_CLK_EDGE_RISING 0x0002
/* TIM OPM INPUT EDGE */
#define TIM_OPM_EDGE_FALLING 0xFFFB
#define TIM_OPM_EDGE_RISING 0x0004
/* TIM ICAPA INPUT EDGE */
#define TIM_ICAP1_EDGE_FALLING 0xFFFB
#define TIM_ICAP1_EDGE_RISING 0x0004
/* TIM ICAPB INPUT EDGE */
#define TIM_ICAP2_EDGE_FALLING 0xFFF7
#define TIM_ICAP2_EDGE_RISING 0x0008
/* TIM OUTPUT LEVEL */
#define TIM_HIGH 0x0200
#define TIM_LOW 0x0300
/* TIM OUTPUT EDGE */
#define TIM_OUTPUT_EDGE_RISING 0x8000
#define TIM_OUTPUT_EDGE_FALLING 0x0800
/* TIM channels */
#define TIM_PWM_OC1_Channel 0x1 /* PWM/Output Compare 1 Channel */
#define TIM_OC2_Channel 0x2 /* Output Compare 2 Channel */
/* TIM DMA SOURCE */
#define TIM_DMA_IC1 0x0000 /* Input Capture Channel 1 DMA Source */
#define TIM_DMA_OC1 0x1000 /* OUTPUT Compare Channel 1 DMA Source */
#define TIM_DMA_IC2 0x2000 /* Input Capture Channel 2 DMA Source */
#define TIM_DMA_OC2 0x3000 /* OUTPUT Compare Channel 2 DMA Source */
/* TIM DMA ENABLE or DISABLE */
#define TIM_DMA_ENABLE 0x0400 /* DMA Enable */
#define TIM_DMA_DISABLE 0xFBFF /* DMA Disable */
/* TIM Interruption Sources*/
#define TIM_IT_IC1 0x8000 /* Input Capture Channel 1 Interrupt Source */
#define TIM_IT_OC1 0x4000 /* Output Compare Channel 1 Interrupt Source */
#define TIM_IT_TO 0x2000 /* Timer OverFlow Interrupt Source */
#define TIM_IT_IC2 0x1000 /* Input Capture Channel 2 Interrupt Source */
#define TIM_IT_OC2 0x0800 /* Output Compare Channel 2 Interrupt Source */
/* TIM Flags */
#define TIM_FLAG_IC1 0x8000 /* Input Capture Channel 1 Flag */
#define TIM_FLAG_OC1 0x4000 /* Output Compare Channel 1 Flag */
#define TIM_FLAG_TO 0x2000 /* Timer OverFlow Flag */
#define TIM_FLAG_IC2 0x1000 /* Input Capture Channel 2 Flag */
#define TIM_FLAG_OC2 0x0800 /* Output Compare Channel 2 Flag */
/* Module private variables --------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void TIM_Init(TIM_TypeDef *TIMx, TIM_InitTypeDef *TIM_InitStruct);
void TIM_DeInit(TIM_TypeDef *TIMx);
void TIM_StructInit(TIM_InitTypeDef *TIM_InitStruct);
void TIM_CounterCmd(TIM_TypeDef *TIMx, TIM_CounterOperations TIM_operation);
void TIM_PrescalerConfig(TIM_TypeDef *TIMx, u8 TIM_Prescaler);
u8 TIM_GetPrescalerValue(TIM_TypeDef *TIMx);
u16 TIM_GetCounterValue(TIM_TypeDef *TIMx);
u16 TIM_GetICAP1Value(TIM_TypeDef *TIMx);
u16 TIM_GetICAP2Value(TIM_TypeDef *TIMx);
void TIM_SetPulse(TIM_TypeDef *TIMx,u16 TIM_Channel ,u16 TIM_Pulse);
FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, u16 TIM_Flag);
void TIM_ClearFlag(TIM_TypeDef *TIMx, u16 TIM_Flag);
u16 TIM_GetPWMIPulse(TIM_TypeDef *TIMx);
u16 TIM_GetPWMIPeriod(TIM_TypeDef *TIMx);
void TIM_ITConfig(TIM_TypeDef *TIMx, u16 TIM_IT, FunctionalState TIM_Newstate);
void TIM_DMAConfig(TIM_TypeDef *TIMx, u16 TIM_DMA_Sources);
void TIM_DMACmd(TIM_TypeDef *TIMx, FunctionalState TIM_Newstate);
#endif /* __91x_TIM_H */
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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Demo/ARM9_STR91X_IAR/Library/include/91x_type.h
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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_type.h
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : It contains common types and constants used in all the
* peripherals' drivers.
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
**********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*********************************************************************************/
#ifndef __91x_type_H
#define __91x_type_H
typedef long long u64;
typedef unsigned long u32;
typedef unsigned short u16;
typedef unsigned char u8;
typedef signed long s32;
typedef signed short s16;
typedef signed char s8;
typedef volatile unsigned long vu32;
typedef volatile unsigned short vu16;
typedef volatile unsigned char vu8;
typedef volatile signed long vs32;
typedef volatile signed short vs16;
typedef volatile signed char vs8;
typedef enum { FALSE = 0, TRUE = !FALSE } bool;
typedef enum { RESET = 0, SET = !RESET } FlagStatus, ITStatus;
typedef enum { DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
typedef enum { ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
#endif /* __91x_type_H */
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_uart.h
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : This file contains all the functions prototypes for the
* UART software library.
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __91x_UART_H
#define __91x_UART_H
/* Includes ------------------------------------------------------------------*/
#include <91x_map.h>
/* Exported types ------------------------------------------------------------*/
/* UART FIFO Level enumeration */
typedef enum
{
UART_FIFOLevel_1_8 = 0x0000, /* FIFO size 16 bytes, FIFO level 2 bytes */
UART_FIFOLevel_1_4 = 0x0001, /* FIFO size 16 bytes, FIFO level 4 bytes */
UART_FIFOLevel_1_2 = 0x0002, /* FIFO size 16 bytes, FIFO level 8 bytes */
UART_FIFOLevel_3_4 = 0x0003, /* FIFO size 16 bytes, FIFO level 12 bytes */
UART_FIFOLevel_7_8 = 0x0004 /* FIFO size 16 bytes, FIFO level 14 bytes */
}UART_FIFOLevel;
/* UART Init Structure definition */
typedef struct
{
u16 UART_WordLength;
u16 UART_StopBits;
u16 UART_Parity;
u32 UART_BaudRate;
u16 UART_HardwareFlowControl;
u16 UART_Mode;
u16 UART_FIFO;
UART_FIFOLevel UART_TxFIFOLevel;
UART_FIFOLevel UART_RxFIFOLevel;
}UART_InitTypeDef;
/* UART RTS enumeration */
typedef enum
{
LowLevel = 0,
HighLevel
}UART_LevelTypeDef;
/* Exported constants --------------------------------------------------------*/
/* UART Data Length */
#define UART_WordLength_5D 0x0000 /* 5 bits Data */
#define UART_WordLength_6D 0x0020 /* 6 bits Data */
#define UART_WordLength_7D 0x0040 /* 7 bits Data */
#define UART_WordLength_8D 0x0060 /* 8 bits Data */
/* UART Stop Bits */
#define UART_StopBits_1 0xFFF7 /* Disable two stop bit is transmitted
at the end of frame */
#define UART_StopBits_2 0x0008 /* Enable Two stop bits are transmitted
at the end of frame */
/* UART Parity */
#define UART_Parity_No 0x0000 /* Parity Disable */
#define UART_Parity_Even 0x0006 /* Even Parity */
#define UART_Parity_Odd 0x0002 /* Odd Parity */
#define UART_Parity_OddStick 0x0082 /* 1 is transmitted as bit parity */
#define UART_Parity_EvenStick 0x0086 /* 0 is transmitted as bit parity */
/* UART Hardware Flow Control */
#define UART_HardwareFlowControl_None 0x0000 /* HFC Disable */
#define UART_HardwareFlowControl_RTS 0x4000 /* RTS Enable */
#define UART_HardwareFlowControl_CTS 0x8000 /* CTS Enable */
#define UART_HardwareFlowControl_RTS_CTS 0xC000 /* CTS and RTS Enable */
/* UART Mode */
#define UART_Mode_Rx 0x0200 /* UART Rx Enabled */
#define UART_Mode_Tx 0x0100 /* UART Tx Enbled */
#define UART_Mode_Tx_Rx 0x0300 /* UART Tx and Rx Enabled */
/* UART FIFO */
#define UART_FIFO_Disable 0xFFEF /* FIFOs Disable */
#define UART_FIFO_Enable 0x0010 /* FIFOs Enable */
/* UART Interrupt definition */
#define UART_IT_OverrunError 0x0400 /* Overrun Error interrupt mask */
#define UART_IT_BreakError 0x0200 /* Break Error interrupt mask */
#define UART_IT_ParityError 0x0100 /* Parity Error interrupt mask */
#define UART_IT_FrameError 0x0080 /* Frame Error interrupt mask */
#define UART_IT_ReceiveTimeOut 0x0040 /* Receive Time Out interrupt mask */
#define UART_IT_Transmit 0x0020 /* Transmit interrupt mask */
#define UART_IT_Receive 0x0010 /* Receive interrupt mask */
#define UART_IT_DSR 0x0008 /* DSR interrupt mask */
#define UART_IT_DCD 0x0004 /* DCD interrupt mask */
#define UART_IT_CTS 0x0002 /* CTS interrupt mask */
#define UART_IT_RI 0x0001 /* RI interrupt mask */
/* UART DMA On Error */
#define UART_DMAOnError_Enable 0xFFFB /* DMA receive request enabled
when the UART error interrupt
is asserted. */
#define UART_DMAOnError_Disable 0x0004 /* DMA receive request disabled
when the UART error interrupt
is asserted. */
/* UART DMA Request */
#define UART_DMAReq_Tx 0x02 /* Transmit DMA Enable */
#define UART_DMAReq_Rx 0x01 /* Receive DMA Enable */
/* UART FLAG */
#define UART_FLAG_OverrunError 0x23 /* Overrun error flag */
#define UART_FLAG_Break 0x22 /* break error flag */
#define UART_FLAG_ParityError 0x21 /* parity error flag */
#define UART_FLAG_FrameError 0x20 /* frame error flag */
#define UART_FLAG_RI 0x48 /* RI flag */
#define UART_FLAG_TxFIFOEmpty 0x47 /* Transmit FIFO Empty flag */
#define UART_FLAG_RxFIFOFull 0x46 /* Receive FIFO Full flag */
#define UART_FLAG_TxFIFOFull 0x45 /* Transmit FIFO Full flag */
#define UART_FLAG_RxFIFOEmpty 0x44 /* Receive FIFO Empty flag */
#define UART_FLAG_Busy 0x43 /* UART Busy flag */
#define UART_FLAG_DCD 0x42 /* DCD flag */
#define UART_FLAG_DSR 0x41 /* DSR flag */
#define UART_FLAG_CTS 0x40 /* CTS flag */
#define UART_RawIT_OverrunError 0x6A /* Overrun Error Raw IT flag */
#define UART_RawIT_BreakError 0x69 /* Break Error Raw IT flag */
#define UART_RawIT_ParityError 0x68 /* Parity Error Raw IT flag */
#define UART_RawIT_FrameError 0x67 /* Frame Error Raw IT flag */
#define UART_RawIT_ReceiveTimeOut 0x66 /* ReceiveTimeOut Raw IT flag */
#define UART_RawIT_Transmit 0x65 /* Transmit Raw IT flag */
#define UART_RawIT_Receive 0x64 /* Receive Raw IT flag */
#define UART_RawIT_DSR 0x63 /* DSR Raw IT flag */
#define UART_RawIT_DCD 0x62 /* DCD Raw IT flag */
#define UART_RawIT_CTS 0x61 /* CTS Raw IT flag */
#define UART_RawIT_RI 0x60 /* RI Raw IT flag */
/*IrDAx select*/
#define IrDA0 0x01 /*IrDA0 select*/
#define IrDA1 0x02 /*IrDA0 select*/
#define IrDA2 0x03 /*IrDA0 select*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void UART_DeInit(UART_TypeDef* UARTx);
void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct);
void UART_StructInit(UART_InitTypeDef* UART_InitStruct);
void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState);
void UART_ITConfig(UART_TypeDef* UARTx, u16 UART_IT, FunctionalState NewState);
void UART_DMAConfig(UART_TypeDef* UARTx, u16 UART_DMAOnError);
void UART_DMACmd(UART_TypeDef* UARTx, u8 UART_DMAReq, FunctionalState NewState);
void UART_LoopBackConfig(UART_TypeDef* UARTx, FunctionalState NewState);
FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, u16 UART_FLAG);
void UART_ClearFlag(UART_TypeDef* UARTx);
void UART_ClearITPendingBit(UART_TypeDef* UARTx, u16 UART_IT);
void UART_IrDALowPowerConfig(u8 IrDAx, FunctionalState NewState);
void UART_IrDACmd(u8 IrDAx, FunctionalState NewState);
void UART_IrDASetCounter(u8 IrDAx, u32 IrDA_Counter);
void UART_SendData(UART_TypeDef* UARTx, u8 Data);
u8 UART_ReceiveData(UART_TypeDef* UARTx);
void UART_SendBreak(UART_TypeDef* UARTx);
void UART_DTRConfig(UART_LevelTypeDef LevelState);
void UART_RTSConfig(UART_LevelTypeDef LevelState);
ITStatus UART_GetITStatus(UART_TypeDef* UARTx, u16 UART_IT);
#endif /* __91x_UART_H */
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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Demo/ARM9_STR91X_IAR/Library/include/91x_vic.h
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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_vic.h
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : This file contains all the functions prototypes for the
* VIC software library.
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion ------------------------------------ */
#ifndef __91x_VIC_H
#define __91x_VIC_H
/* Includes ------------------------------------------------------------------*/
#include "91x_map.h"
#include "91x_it.h"
/* Exported types ------------------------------------------------------------*/
/* Type of interrupt */
typedef enum
{
VIC_IRQ,
VIC_FIQ
} VIC_ITLineMode;
/* Exported constants --------------------------------------------------------*/
/* VIC sources*/
#define WDG_ITLine 0
#define SW_ITLine 1
#define ARMRX_ITLine 2
#define ARMTX_ITLine 3
#define TIM0_ITLine 4
#define TIM1_ITLine 5
#define TIM2_ITLine 6
#define TIM3_ITLine 7
#define USBHP_ITLine 8
#define USBLP_ITLine 9
#define SCU_ITLine 10
#define ENET_ITLine 11
#define DMA_ITLine 12
#define CAN_ITLine 13
#define MC_ITLine 14
#define ADC_ITLine 15
#define UART0_ITLine 16
#define UART1_ITLine 17
#define UART2_ITLine 18
#define I2C0_ITLine 19
#define I2C1_ITLine 20
#define SSP0_ITLine 21
#define SSP1_ITLine 22
#define LVD_ITLine 23
#define RTC_ITLine 24
#define WIU_ITLine 25
#define EXTIT0_ITLine 26
#define EXTIT1_ITLine 27
#define EXTIT2_ITLine 28
#define EXTIT3_ITLine 29
#define USBWU_ITLine 30
#define PFQBC_ITLine 31
/* Module private variables --------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void VIC_DeInit(void);
FlagStatus VIC_GetIRQStatus(u16 VIC_Source);
FlagStatus VIC_GetFIQStatus(u16 VIC_Source);
FlagStatus VIC_GetSourceITStatus(u16 VIC_Source);
void VIC_ITCmd(u16 VIC_Source, FunctionalState VIC_NewState);
void VIC_SWITCmd(u16 VIC_Source, FunctionalState VIC_NewState);
void VIC_ProtectionCmd(FunctionalState VIC_NewState);
u32 VIC_GetCurrentISRAdd(VIC_TypeDef* VICx);
u32 VIC_GetISRVectAdd(u16 VIC_Source);
void VIC_Config(u16 VIC_Source, VIC_ITLineMode VIC_LineMode, u8 VIC_Priority);
#endif /* __91x_VIC_H */
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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Demo/ARM9_STR91X_IAR/Library/include/91x_wdg.h
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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_wdg.h
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : This file contains all the functions prototypes for the
* WDG software library.
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __91x_WDG_H
#define __91x_WDG_H
/* Includes ------------------------------------------------------------------*/
#include "91x_map.h"
/* Exported types ------------------------------------------------------------*/
typedef struct
{
u16 WDG_Mode;
u16 WDG_ClockSource;
u16 WDG_Prescaler;
u16 WDG_Preload;
} WDG_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/* WDG_Mode */
#define WDG_Mode_Wdg 0x0001 /*WDG configured to run in watchdog mode.*/
#define WDG_Mode_Timer 0xFFFE /*WDG configured to be in Free-running Timer mode.*/
/* WDG_ClockSource */
#define WDG_ClockSource_Rtc 0x0004 /* External clock ( 32 khz RTC clock ) will be used as counting clock.*/
#define WDG_ClockSource_Apb 0xFFFB /*The APB clock signal will be used as counting clock.*/
/* WDG_Prescaler */
/*This member must be a number between 0x00 and 0xFF.
Specifies the Prescaler value to divide the clock source.
The clock of the Watchdog Timer Counter is divided by " WDG_Prescaler + 1".*/
/* WDG_Preload */
/*This member must be a number between 0x0000 and 0xFFFF.
This value is loaded in the WDG Counter when it starts counting.*/
/* WDG Sequence */
#define WDG_KeyValue1 0xA55A
#define WDG_KeyValue2 0x5AA5
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void WDG_DeInit(void);
void WDG_Init(WDG_InitTypeDef* WDG_InitStruct);
void WDG_StructInit(WDG_InitTypeDef* WDG_InitStruct);
void WDG_Cmd(FunctionalState NewState);
void WDG_ITConfig(FunctionalState NewState);
u16 WDG_GetCounter(void);
FlagStatus WDG_GetFlagStatus(void);
void WDG_ClearFlag(void);
ITStatus WDG_GetITStatus(void);
void WDG_ClearITPendingBit(void);
#endif /* __WDG_H */
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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Demo/ARM9_STR91X_IAR/Library/source/91x_can.c
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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_can.c
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : This file provides all the CAN software functions.
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "91x_can.h"
#include "91x_scu.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/*----------------------------------------------------------------------------*/
/* Macro Name : xxx_ID_MSK, xxx_ID_ARB */
/* Description : Form the Mask and Arbitration registers value to filter */
/* a range of identifiers or a fixed identifier, for standard*/
/* and extended IDs */
/*----------------------------------------------------------------------------*/
#define RANGE_ID_MSK(range_start, range_end) (~((range_end) - (range_start)))
#define RANGE_ID_ARB(range_start, range_end) ((range_start) & (range_end))
#define FIXED_ID_MSK(id) RANGE_ID_MSK((id), (id))
#define FIXED_ID_ARB(id) RANGE_ID_ARB((id), (id))
#define STD_RANGE_ID_MSK(range_start, range_end) ((u16)((RANGE_ID_MSK((range_start), (range_end)) & 0x7FF) << 2))
#define STD_RANGE_ID_ARB(range_start, range_end) ((u16)(RANGE_ID_ARB((range_start), (range_end)) << 2))
#define STD_FIXED_ID_MSK(id) ((u16)((FIXED_ID_MSK(id) & 0x7FF) << 2))
#define STD_FIXED_ID_ARB(id) ((u16)(FIXED_ID_ARB(id) << 2))
#define EXT_RANGE_ID_MSK_L(range_start, range_end) ((u16)(RANGE_ID_MSK((range_start), (range_end)) >> 11))
#define EXT_RANGE_ID_MSK_H(range_start, range_end) ((u16)(STD_RANGE_ID_MSK((range_start), (range_end)) | ((RANGE_ID_MSK((range_start), (range_end)) >> 27) & 0x03)))
#define EXT_RANGE_ID_ARB_L(range_start, range_end) ((u16)(RANGE_ID_ARB((range_start), (range_end)) >> 11))
#define EXT_RANGE_ID_ARB_H(range_start, range_end) ((u16)(STD_RANGE_ID_ARB((range_start), (range_end)) | ((RANGE_ID_ARB((range_start), (range_end)) >> 27) & 0x03)))
#define EXT_FIXED_ID_MSK_L(id) ((u16)(FIXED_ID_MSK(id) >> 11))
#define EXT_FIXED_ID_MSK_H(id) ((u16)(STD_FIXED_ID_MSK(id) | ((FIXED_ID_MSK(id) >> 27) & 0x03)))
#define EXT_FIXED_ID_ARB_L(id) ((u16)(FIXED_ID_ARB(id) >> 11))
#define EXT_FIXED_ID_ARB_H(id) ((u16)(STD_FIXED_ID_ARB(id) | ((FIXED_ID_ARB(id) >> 27) & 0x03)))
/* macro to format the timing register value from the timing parameters*/
#define CAN_TIMING(tseg1, tseg2, sjw, brp) ((((tseg2-1) & 0x07) << 12) | (((tseg1-1) & 0x0F) << 8) | (((sjw-1) & 0x03) << 6) | ((brp-1) & 0x3F))
/* Private variables ---------------------------------------------------------*/
/* array of pre-defined timing parameters for standard bitrates*/
u16 CanTimings[] = { /* value bitrate NTQ TSEG1 TSEG2 SJW BRP */
CAN_TIMING(11, 4, 4, 5), /* 0x3AC4 100 kbit/s 16 11 4 4 5 */
CAN_TIMING(11, 4, 4, 4), /* 0x3AC3 125 kbit/s 16 11 4 4 4 */
CAN_TIMING( 4, 3, 3, 4), /* 0x2383 250 kbit/s 8 4 3 3 4 */
CAN_TIMING(13, 2, 1, 1), /* 0x1C00 500 kbit/s 16 13 2 1 1 */
CAN_TIMING( 4, 3, 1, 1), /* 0x2300 1 Mbit/s 8 4 3 1 1 */
};
/* Private function prototypes -----------------------------------------------*/
static u32 GetFreeIF(void);
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : CAN_DeInit
* Description : Deinitializes the CAN peripheral registers to their default
* reset values.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void CAN_DeInit (void)
{
/* Reset the CAN registers values*/
SCU_APBPeriphReset(__CAN,ENABLE); /*CAN peripheral is under Reset */
SCU_APBPeriphReset(__CAN,DISABLE); /*CAN peripheral Reset off*/
}
/*******************************************************************************
* Function Name : CAN_Init
* Description : Initializes the CAN peripheral according to the specified
* parameters in the CAN_InitStruct.
* Input : CAN_InitStruct: pointer to a CAN_InitTypeDef structure that
* contains the configuration information for the CAN peripheral.
* Output : None
* Return : None
*******************************************************************************/
void CAN_Init(CAN_InitTypeDef* CAN_InitStruct)
{
CAN_EnterInitMode(CAN_CR_CCE | CAN_InitStruct->CAN_ConfigParameters);
CAN_SetBitrate(CAN_InitStruct->CAN_Bitrate);
CAN_LeaveInitMode();
CAN_LeaveTestMode();
}
/*******************************************************************************
* Function Name : CAN_StructInit
* Description : Fills each CAN_InitStruct member with its reset value.
* Input : CAN_InitStruct : pointer to a CAN_InitTypeDef structure which
* will be initialized.
* Output : None
* Return : None.
*******************************************************************************/
void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)
{
/* Reset CAN init structure parameters values */
CAN_InitStruct->CAN_ConfigParameters = 0x0;
CAN_InitStruct->CAN_Bitrate = 0x2301;
}
/*******************************************************************************
* Function Name : CAN_SetBitrate
* Description : Setups a standard CAN bitrate.
* Input : bitrate: specifies the bit rate.
* Output : None
* Return : None
*******************************************************************************/
void CAN_SetBitrate(u32 bitrate)
{
CAN->BTR = CanTimings[bitrate]; /* write the predefined timing value */
CAN->BRPR = 0; /* clear the Extended Baud Rate Prescaler */
}
/*******************************************************************************
* Function Name : CAN_SetTiming
* Description : Setups the CAN timing with specific parameters
* Input : - tseg1: specifies Time Segment before the sample point.
* This parameter must be a number between 1 and 16.
* - tseg2: Time Segment after the sample point. This parameter
* must be a number between 1 and 8.
* - sjw: Synchronisation Jump Width. This parameter must be
* a number between 1 and 4.
* - brp: Baud Rate Prescaler. This parameter must be a number
* between 1 and 1024.
* Output : None
* Return : None
*******************************************************************************/
void CAN_SetTiming(u32 tseg1, u32 tseg2, u32 sjw, u32 brp)
{
CAN->BTR = CAN_TIMING(tseg1, tseg2, sjw, brp);
CAN->BRPR = ((brp-1) >> 6) & 0x0F;
}
/*******************************************************************************
* Function Name : GetFreeIF
* Description : Searchs the first free message interface, starting from 0.
* Input : None
* Output : None
* Return : A free message interface number (0 or 1) if found, else 2
*******************************************************************************/
static u32 GetFreeIF(void)
{
if ((CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) == 0)
return 0;
else if ((CAN->sMsgObj[1].CRR & CAN_CRR_BUSY) == 0)
return 1;
else
return 2;
}
/*******************************************************************************
* Function Name : CAN_SetUnusedMsgObj
* Description : Configures the message object as unused
* Input : msgobj: specifies the Message object number, from 0 to 31.
* Output : None
* Return : An ErrorStatus enumuration value:
* - SUCCESS: Interface to treat the message
* - ERROR: No interface to treat the message
*******************************************************************************/
ErrorStatus CAN_SetUnusedMsgObj(u32 msgobj)
{
u32 msg_if=0;
if ((msg_if = GetFreeIF()) == 2)
{
return ERROR;
}
CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD
| CAN_CMR_MASK
| CAN_CMR_ARB
| CAN_CMR_CONTROL
| CAN_CMR_DATAA
| CAN_CMR_DATAB;
CAN->sMsgObj[msg_if].M1R = 0;
CAN->sMsgObj[msg_if].M2R = 0;
CAN->sMsgObj[msg_if].A1R = 0;
CAN->sMsgObj[msg_if].A2R = 0;
CAN->sMsgObj[msg_if].MCR = 0;
CAN->sMsgObj[msg_if].DA1R = 0;
CAN->sMsgObj[msg_if].DA2R = 0;
CAN->sMsgObj[msg_if].DB1R = 0;
CAN->sMsgObj[msg_if].DB2R = 0;
CAN->sMsgObj[msg_if].CRR = 1 + msgobj;
return SUCCESS;
}
/*******************************************************************************
* Function Name : CAN_SetTxMsgObj
* Description : Configures the message object as TX.
* Input : - msgobj: specifies the Message object number, from 0 to 31.
* - idType: specifies the identifier type of the frames that
* will be transmitted using this message object.
* This parameter can be one of the following values:
* - CAN_STD_ID (standard ID, 11-bit)
* - CAN_EXT_ID (extended ID, 29-bit)
* Output : None
* Return : An ErrorStatus enumuration value:
* - SUCCESS: Interface to treat the message
* - ERROR: No interface to treat the message
*******************************************************************************/
ErrorStatus CAN_SetTxMsgObj(u32 msgobj, u32 idType)
{
u32 msg_if=0;
if ((msg_if = GetFreeIF()) == 2)
{
return ERROR;
}
CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD
| CAN_CMR_MASK
| CAN_CMR_ARB
| CAN_CMR_CONTROL
| CAN_CMR_DATAA
| CAN_CMR_DATAB;
CAN->sMsgObj[msg_if].M1R = 0;
CAN->sMsgObj[msg_if].A1R = 0;
if (idType == CAN_STD_ID)
{
CAN->sMsgObj[msg_if].M2R = CAN_M2R_MDIR;
CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_DIR;
}
else
{
CAN->sMsgObj[msg_if].M2R = CAN_M2R_MDIR | CAN_M2R_MXTD;
CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_DIR | CAN_A2R_XTD;
}
CAN->sMsgObj[msg_if].MCR = CAN_MCR_TXIE | CAN_MCR_EOB;
CAN->sMsgObj[msg_if].DA1R = 0;
CAN->sMsgObj[msg_if].DA2R = 0;
CAN->sMsgObj[msg_if].DB1R = 0;
CAN->sMsgObj[msg_if].DB2R = 0;
CAN->sMsgObj[msg_if].CRR = 1 + msgobj;
return SUCCESS;
}
/*******************************************************************************
* Function Name : CAN_SetRxMsgObj
* Description : Configures the message object as RX.
* Input : - msgobj: specifies the Message object number, from 0 to 31.
* - idType: specifies the identifier type of the frames that
* will be transmitted using this message object.
* This parameter can be one of the following values:
* - CAN_STD_ID (standard ID, 11-bit)
* - CAN_EXT_ID (extended ID, 29-bit)
* - idLow: specifies the low part of the identifier range used
* for acceptance filtering.
* - idHigh: specifies the high part of the identifier range
* used for acceptance filtering.
* - singleOrFifoLast: specifies the end-of-buffer indicator.
* This parameter can be one of the following values:
* - TRUE: for a single receive object or a FIFO receive
* object that is the last one of the FIFO.
* - FALSE: for a FIFO receive object that is not the
* last one.
* Output : None
* Return : An ErrorStatus enumuration value:
* - SUCCESS: Interface to treat the message
* - ERROR: No interface to treat the message
*******************************************************************************/
ErrorStatus CAN_SetRxMsgObj(u32 msgobj, u32 idType, u32 idLow, u32 idHigh, bool singleOrFifoLast)
{
u32 msg_if=0;
if ((msg_if = GetFreeIF()) == 2)
{
return ERROR;
}
CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD
| CAN_CMR_MASK
| CAN_CMR_ARB
| CAN_CMR_CONTROL
| CAN_CMR_DATAA
| CAN_CMR_DATAB;
if (idType == CAN_STD_ID)
{
CAN->sMsgObj[msg_if].M1R = 0;
CAN->sMsgObj[msg_if].M2R = STD_RANGE_ID_MSK(idLow, idHigh);
CAN->sMsgObj[msg_if].A1R = 0;
CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | STD_RANGE_ID_ARB(idLow, idHigh);
}
else
{
CAN->sMsgObj[msg_if].M1R = EXT_RANGE_ID_MSK_L(idLow, idHigh);
CAN->sMsgObj[msg_if].M2R = CAN_M2R_MXTD | EXT_RANGE_ID_MSK_H(idLow, idHigh);
CAN->sMsgObj[msg_if].A1R = EXT_RANGE_ID_ARB_L(idLow, idHigh);
CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_XTD | EXT_RANGE_ID_ARB_H(idLow, idHigh);
}
CAN->sMsgObj[msg_if].MCR = CAN_MCR_RXIE | CAN_MCR_UMASK | (singleOrFifoLast ? CAN_MCR_EOB : 0);
CAN->sMsgObj[msg_if].DA1R = 0;
CAN->sMsgObj[msg_if].DA2R = 0;
CAN->sMsgObj[msg_if].DB1R = 0;
CAN->sMsgObj[msg_if].DB2R = 0;
CAN->sMsgObj[msg_if].CRR = 1 + msgobj;
return SUCCESS;
}
/*******************************************************************************
* Function Name : CAN_InvalidateAllMsgObj
* Description : Configures all the message objects as unused.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void CAN_InvalidateAllMsgObj(void)
{
u32 i=0;
for (i = 0; i < 32; i++)
CAN_SetUnusedMsgObj(i);
}
/*******************************************************************************
* Function Name : CAN_ReleaseMessage
* Description : Releases the message object
* Input : - msgobj: specifies the Message object number, from 0 to 31.
* Output : None
* Return : An ErrorStatus enumuration value:
* - SUCCESS: Interface to treat the message
* - ERROR: No interface to treat the message
*******************************************************************************/
ErrorStatus CAN_ReleaseMessage(u32 msgobj)
{
u32 msg_if=0;
if ((msg_if = GetFreeIF()) == 2)
{
return ERROR;
}
CAN->sMsgObj[msg_if].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT;
CAN->sMsgObj[msg_if].CRR = 1 + msgobj;
return SUCCESS;
}
/*******************************************************************************
* Function Name : CAN_SendMessage
* Description : Start transmission of a message
* Input : - msgobj: specifies the Message object number, from 0 to 31.
* : - pCanMsg: pointer to the message structure containing data
* to transmit.
* Output : None
* Return : An ErrorStatus enumuration value:
* - SUCCESS: Transmission OK
* - ERROR: No transmission
*******************************************************************************/
ErrorStatus CAN_SendMessage(u32 msgobj, canmsg* pCanMsg)
{
if (CAN->sMsgObj[0].CRR & CAN_CRR_BUSY)
{
return ERROR;
}
CAN->SR &= ~CAN_SR_TXOK;
/* read the Arbitration and Message Control*/
CAN->sMsgObj[0].CMR = CAN_CMR_ARB | CAN_CMR_CONTROL;
CAN->sMsgObj[0].CRR = 1 + msgobj;
if (CAN->sMsgObj[0].CRR & CAN_CRR_BUSY)
{
return ERROR;
}
/* update the contents needed for transmission*/
CAN->sMsgObj[0].CMR = CAN_CMR_WRRD
| CAN_CMR_ARB
| CAN_CMR_CONTROL
| CAN_CMR_DATAA
| CAN_CMR_DATAB;
if ((CAN->sMsgObj[0].A2R & CAN_A2R_XTD) == 0)
{
/* standard ID*/
CAN->sMsgObj[0].A1R = 0;
CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | STD_FIXED_ID_ARB(pCanMsg->Id);
}
else
{
/* extended ID*/
CAN->sMsgObj[0].A1R = EXT_FIXED_ID_ARB_L(pCanMsg->Id);
CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | EXT_FIXED_ID_ARB_H(pCanMsg->Id);
}
CAN->sMsgObj[0].MCR = (CAN->sMsgObj[0].MCR & 0xFEF0) | CAN_MCR_NEWDAT | CAN_MCR_TXRQST | pCanMsg->Dlc;
CAN->sMsgObj[0].DA1R = ((u16)pCanMsg->Data[1]<<8) | pCanMsg->Data[0];
CAN->sMsgObj[0].DA2R = ((u16)pCanMsg->Data[3]<<8) | pCanMsg->Data[2];
CAN->sMsgObj[0].DB1R = ((u16)pCanMsg->Data[5]<<8) | pCanMsg->Data[4];
CAN->sMsgObj[0].DB2R = ((u16)pCanMsg->Data[7]<<8) | pCanMsg->Data[6];
CAN->sMsgObj[0].CRR = 1 + msgobj;
return SUCCESS;
}
/*******************************************************************************
* Function Name : CAN_ReceiveMessage
* Description : Gets the message, if received.
* Input : - msgobj: specifies the Message object number, from 0 to 31.
* - release: specifies the message release indicator.
* This parameter can be one of the following values:
* - TRUE: the message object is released when getting
* the data.
* - FALSE: the message object is not released.
* - pCanMsg: pointer to the message structure where received
* data is copied.
* Output : None
* Return : An ErrorStatus enumuration value:
* - SUCCESS: Reception OK
* - ERROR: No message pending
*******************************************************************************/
ErrorStatus CAN_ReceiveMessage(u32 msgobj, bool release, canmsg* pCanMsg)
{
if (!CAN_IsMessageWaiting(msgobj))
{
return ERROR;
}
CAN->SR &= ~CAN_SR_RXOK;
/* read the message contents*/
CAN->sMsgObj[1].CMR = CAN_CMR_MASK
| CAN_CMR_ARB
| CAN_CMR_CONTROL
| CAN_CMR_CLRINTPND
| (release ? CAN_CMR_TXRQSTNEWDAT : 0)
| CAN_CMR_DATAA
| CAN_CMR_DATAB;
CAN->sMsgObj[1].CRR = 1 + msgobj;
if (CAN->sMsgObj[1].CRR & CAN_CRR_BUSY)
{
return ERROR;
}
if ((CAN->sMsgObj[1].A2R & CAN_A2R_XTD) == 0)
{
/* standard ID*/
pCanMsg->IdType = CAN_STD_ID;
pCanMsg->Id = (CAN->sMsgObj[1].A2R >> 2) & 0x07FF;
}
else
{
/* extended ID*/
pCanMsg->IdType = CAN_EXT_ID;
pCanMsg->Id = ((CAN->sMsgObj[1].A2R >> 2) & 0x07FF);
pCanMsg->Id |= ((u32)CAN->sMsgObj[1].A1R << 11);
pCanMsg->Id |= (((u32)CAN->sMsgObj[1].A2R & 0x0003) << 27);
}
pCanMsg->Dlc = CAN->sMsgObj[1].MCR & 0x0F;
pCanMsg->Data[0] = (u8) CAN->sMsgObj[1].DA1R;
pCanMsg->Data[1] = (u8)(CAN->sMsgObj[1].DA1R >> 8);
pCanMsg->Data[2] = (u8) CAN->sMsgObj[1].DA2R;
pCanMsg->Data[3] = (u8)(CAN->sMsgObj[1].DA2R >> 8);
pCanMsg->Data[4] = (u8) CAN->sMsgObj[1].DB1R;
pCanMsg->Data[5] = (u8)(CAN->sMsgObj[1].DB1R >> 8);
pCanMsg->Data[6] = (u8) CAN->sMsgObj[1].DB2R;
pCanMsg->Data[7] = (u8)(CAN->sMsgObj[1].DB2R >> 8);
return SUCCESS;
}
/*******************************************************************************
* Function Name : CAN_WaitEndOfTx
* Description : Waits until current transmission is finished.
* Input : None
* Output : None
* Return : An ErrorStatus enumuration value:
* - SUCCESS: Transmission ended
* - ERROR: Transmission did not occur yet
*******************************************************************************/
ErrorStatus CAN_WaitEndOfTx(void)
{
if ((CAN->SR & CAN_SR_TXOK) == 0)
{
return ERROR;
}
CAN->SR &= ~CAN_SR_TXOK;
return SUCCESS;
}
/*******************************************************************************
* Function Name : CAN_BasicSendMessage
* Description : Starts transmission of a message in BASIC mode. This mode
* does not use the message RAM.
* Input : pCanMsg: Pointer to the message structure containing data to
* transmit.
* Output : None
* Return : An ErrorStatus enumuration value:
* - SUCCESS: Transmission OK
* - ERROR: No transmission
*******************************************************************************/
ErrorStatus CAN_BasicSendMessage(canmsg* pCanMsg)
{
/* clear NewDat bit in IF2 to detect next reception*/
CAN->sMsgObj[1].MCR &= ~CAN_MCR_NEWDAT;
CAN->SR &= ~CAN_SR_TXOK;
CAN->sMsgObj[0].CMR = CAN_CMR_WRRD
| CAN_CMR_ARB
| CAN_CMR_CONTROL
| CAN_CMR_DATAA
| CAN_CMR_DATAB;
if (pCanMsg->IdType == CAN_STD_ID)
{
/* standard ID*/
CAN->sMsgObj[0].A1R = 0;
CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | STD_FIXED_ID_ARB(pCanMsg->Id);
}
else
{
/* extended ID*/
CAN->sMsgObj[0].A1R = EXT_FIXED_ID_ARB_L(pCanMsg->Id);
CAN->sMsgObj[0].A2R = ((CAN->sMsgObj[0].A2R) & 0xE000) | EXT_FIXED_ID_ARB_H(pCanMsg->Id);
}
CAN->sMsgObj[0].MCR = (CAN->sMsgObj[0].MCR & 0xFCF0) | pCanMsg->Dlc;
CAN->sMsgObj[0].DA1R = ((u16)pCanMsg->Data[1]<<8) | pCanMsg->Data[0];
CAN->sMsgObj[0].DA2R = ((u16)pCanMsg->Data[3]<<8) | pCanMsg->Data[2];
CAN->sMsgObj[0].DB1R = ((u16)pCanMsg->Data[5]<<8) | pCanMsg->Data[4];
CAN->sMsgObj[0].DB2R = ((u16)pCanMsg->Data[7]<<8) | pCanMsg->Data[6];
/* request transmission*/
if (CAN->sMsgObj[0].CRR == CAN_CRR_BUSY )
{
return ERROR;
}
return SUCCESS;
}
/*******************************************************************************
* Function Name : CAN_BasicReceiveMessage
* Description : Gets the message in BASIC mode, if received. This mode does
* not use the message RAM.
* Input : pCanMsg: pointer to the message structure where message is copied.
* Output : None
* Return : An ErrorStatus enumuration value:
* - SUCCESS: Reception OK
* - ERROR: No message pending
*******************************************************************************/
ErrorStatus CAN_BasicReceiveMessage(canmsg* pCanMsg)
{
if ((CAN->sMsgObj[1].MCR & CAN_MCR_NEWDAT) == 0)
{
return ERROR;
}
CAN->SR &= ~CAN_SR_RXOK;
CAN->sMsgObj[1].CMR = CAN_CMR_ARB
| CAN_CMR_CONTROL
| CAN_CMR_DATAA
| CAN_CMR_DATAB;
if ((CAN->sMsgObj[1].A2R & CAN_A2R_XTD) == 0)
{
/* standard ID*/
pCanMsg->IdType = CAN_STD_ID;
pCanMsg->Id = (CAN->sMsgObj[1].A2R >> 2) & 0x07FF;
}
else
{
/* extended ID*/
pCanMsg->IdType = CAN_EXT_ID;
pCanMsg->Id = ((CAN->sMsgObj[1].A2R >> 2) & 0x07FF);
pCanMsg->Id |= ((u32)CAN->sMsgObj[1].A1R << 11);
pCanMsg->Id |= (((u32)CAN->sMsgObj[1].A2R & 0x0003) << 27);
}
pCanMsg->Dlc = CAN->sMsgObj[1].MCR & 0x0F;
pCanMsg->Data[0] = (u8) CAN->sMsgObj[1].DA1R;
pCanMsg->Data[1] = (u8)(CAN->sMsgObj[1].DA1R >> 8);
pCanMsg->Data[2] = (u8) CAN->sMsgObj[1].DA2R;
pCanMsg->Data[3] = (u8)(CAN->sMsgObj[1].DA2R >> 8);
pCanMsg->Data[4] = (u8) CAN->sMsgObj[1].DB1R;
pCanMsg->Data[5] = (u8)(CAN->sMsgObj[1].DB1R >> 8);
pCanMsg->Data[6] = (u8) CAN->sMsgObj[1].DB2R;
pCanMsg->Data[7] = (u8)(CAN->sMsgObj[1].DB2R >> 8);
return SUCCESS;
}
/*******************************************************************************
* Function Name : CAN_EnterInitMode
* Description : Switchs the CAN into initialization mode. This function must
* be used in conjunction with CAN_LeaveInitMode().
* Input : InitMask: specifies the CAN configuration in normal mode.
* Output : None
* Return : None
*******************************************************************************/
void CAN_EnterInitMode(u8 InitMask)
{
CAN->CR = InitMask | CAN_CR_INIT;
CAN->SR = 0; /* reset the status*/
}
/*******************************************************************************
* Function Name : CAN_LeaveInitMode
* Description : Leaves the initialization mode (switch into normal mode).
* This function must be used in conjunction with CAN_EnterInitMode().
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void CAN_LeaveInitMode(void)
{
CAN->CR &= ~(CAN_CR_INIT | CAN_CR_CCE);
}
/*******************************************************************************
* Function Name : CAN_EnterTestMode
* Description : Switchs the CAN into test mode. This function must be used in
* conjunction with CAN_LeaveTestMode().
* Input : TestMask: specifies the configuration in test modes.
* Output : None
* Return : None
*******************************************************************************/
void CAN_EnterTestMode(u8 TestMask)
{
CAN->CR |= CAN_CR_TEST;
CAN->TESTR |= TestMask;
}
/*******************************************************************************
* Function Name : CAN_LeaveTestMode
* Description : Leaves the current test mode (switch into normal mode).
* This function must be used in conjunction with CAN_EnterTestMode().
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void CAN_LeaveTestMode(void)
{
CAN->CR |= CAN_CR_TEST;
CAN->TESTR &= ~(CAN_TESTR_LBACK | CAN_TESTR_SILENT | CAN_TESTR_BASIC);
CAN->CR &= ~CAN_CR_TEST;
}
/*******************************************************************************
* Function Name : CAN_ReleaseTxMessage
* Description : Releases the transmit message object.
* Input : - msgobj: specifies the Message object number, from 0 to 31.
* Output : None
* Return : None
*******************************************************************************/
void CAN_ReleaseTxMessage(u32 msgobj)
{
CAN->sMsgObj[0].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT;
CAN->sMsgObj[0].CRR = 1 + msgobj;
}
/*******************************************************************************
* Function Name : CAN_ReleaseRxMessage
* Description : Releases the receive message object.
* Input : - msgobj: specifies the Message object number, from 0 to 31.
* Output : None
* Return : None
*******************************************************************************/
void CAN_ReleaseRxMessage(u32 msgobj)
{
CAN->sMsgObj[1].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQSTNEWDAT;
CAN->sMsgObj[1].CRR = 1 + msgobj;
}
/*******************************************************************************
* Function Name : CAN_IsMessageWaiting
* Description : Tests the waiting status of a received message.
* Input : - msgobj: specifies the Message object number, from 0 to 31.
* Output : None
* Return : A non-zero value if the corresponding message object has
* received a message waiting to be copied, else 0.
*******************************************************************************/
u32 CAN_IsMessageWaiting(u32 msgobj)
{
return (msgobj < 16 ? CAN->ND1R & (1 << msgobj) : CAN->ND2R & (1 << (msgobj-16)));
}
/*******************************************************************************
* Function Name : CAN_IsTransmitRequested
* Description : Tests the request status of a transmitted message.
* Input : - msgobj: specifies the Message object number, from 0 to 31.
* Output : None
* Return : A non-zero value if the corresponding message is requested
* to transmit, else 0.
*******************************************************************************/
u32 CAN_IsTransmitRequested(u32 msgobj)
{
return (msgobj < 16 ? CAN->TXR1R & (1 << msgobj) : CAN->TXR2R & (1 << (msgobj-16)));
}
/*******************************************************************************
* Function Name : CAN_IsInterruptPending
* Description : Tests the interrupt status of a message object.
* Input : - msgobj: specifies the Message object number, from 0 to 31.
* Output : None
* Return : A non-zero value if the corresponding message has an
* interrupt pending, else 0.
*******************************************************************************/
u32 CAN_IsInterruptPending(u32 msgobj)
{
return (msgobj < 16 ? CAN->IP1R & (1 << msgobj) : CAN->IP2R & (1 << (msgobj-16)));
}
/*******************************************************************************
* Function Name : CAN_IsObjectValid
* Description : Tests the validity of a message object (ready to use).
* Input : - msgobj: specifies the Message object number, from 0 to 31.
* Output : None
* Return : A non-zero value if the corresponding message object is
* valid, else 0.
*******************************************************************************/
u32 CAN_IsObjectValid(u32 msgobj)
{
return (msgobj < 16 ? CAN->MV1R & (1 << msgobj) : CAN->MV2R & (1 << (msgobj-16)));
}
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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Demo/ARM9_STR91X_IAR/Library/source/91x_enet.c
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/********************
* Original work (C) COPYRIGHT 2006 STMicroelectronics **************************
* Modifications (C) CopyRight 2006 Richard barry
* File Name : 91x_enet.c
* Author : MCD Application Team
* Date First Issued : May 2006
* Description : ENET library functions
********************************************************************************
* History:
* May 2006: v1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "FreeRTOS.h"
#include "task.h"
#include "91x_lib.h"
#include "string.h" //include when using memcpy function
/* Include of other module interface headers ---------------------------------*/
/* Local includes ------------------------------------------------------------*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#ifndef NULL
#define NULL (0)
#endif
/* Function return values */
#define ENET_OK (1)
#define ENET_NOK (0)
/* PHY interface constants. */
#define STE100P_STATUS_REG 0x01
#define STE100P_CONTROL_REG 0x00
#define STE100P_LINK_ABILITY 0x05
#define STE100P_STATUS_LINKED 0x0004
#define STE100P_AUTO_NEGOTIATE_ABILITY 0x1000
#define STE100P_AUTO_NEGOTIATE_COMPLETE 0x20
#define STE100P_10HALF 0x0020
#define STE100P_10FULL 0x0040
#define STE100P_100HALF 0x0080
#define STE100P_100FULL 0x0100
#define STE100P_CTRL_FULL 0x0100
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
#define ENET_NUM_RX_BUFFERS 8
static ENET_DMADSCRBase dmaTxDscrBase, dmaRxDscrBase[ ENET_NUM_RX_BUFFERS ];
static volatile u8 RxBuff[ ENET_NUM_RX_BUFFERS ][ENET_BUFFER_SIZE], TxBuff[ENET_BUFFER_SIZE];
/* Private function prototypes -----------------------------------------------*/
extern MEMCOPY_L2S_BY4();
/* Interface functions -------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : ENET_SetMACConfig(ENET_MACConfig * MAC_Config)
* Description : MAC Control Register Configuration
* Input : MAC_Config structure
* Output : None
* Return : None
*******************************************************************************/
void ENET_MACControlConfig(ENET_MACConfig *MAC_Config)
{
/* ReceiveALL bit */
if (MAC_Config->ReceiveALL==ENABLE) ENET_MAC->MCR |= MAC_MCR_RA;
else ENET_MAC->MCR &=~MAC_MCR_RA;
/* MIIPrescaler */
ENET_MAC->MCR &=~(0x3<<24);
if ((MAC_Config->MIIPrescaler) == MIIPrescaler_2)
ENET_MAC->MCR |=0x1<<24;
/* Loopback mode */
if (MAC_Config->LoopbackMode==ENABLE)
{
ENET_MAC->MCR &=~MAC_MCR_LM;
ENET_MAC->MCR |=0x1<<21;
ENET_MAC->MCR &=~MAC_MCR_DRO; /*enable frame reception during transmission*/
}
/* Address filtering mode */
ENET_MAC->MCR &=~MAC_MCR_AFM;
ENET_MAC->MCR |= MAC_Config->AddressFilteringMode;
/* VLAN Filtering Mode */
ENET_MAC->MCR = (MAC_Config->VLANFilteringMode)<<15;
/*Wrong Frame Pass */
if (MAC_Config->PassWrongFrame == ENABLE) ENET_MAC->MCR |=MAC_MCR_PWF;
else ENET_MAC->MCR &=~MAC_MCR_PWF;
/* Late Collision Retransmission*/
if (MAC_Config->LateCollision == ENABLE) ENET_MAC->MCR |=MAC_MCR_ELC;
else ENET_MAC->MCR &=~MAC_MCR_ELC;
/* Broadcast Frame Reception */
if (MAC_Config->BroadcastFrameReception == ENABLE) ENET_MAC->MCR |=MAC_MCR_DBF;
else ENET_MAC->MCR &=~MAC_MCR_DBF;
/* PacketRetry */
if (MAC_Config->PacketRetry == ENABLE) ENET_MAC->MCR &=~MAC_MCR_DPR;
else ENET_MAC->MCR |=MAC_MCR_DPR;
/* RxFrameFiltering */
if (MAC_Config->RxFrameFiltering == ENABLE) ENET_MAC->MCR |=MAC_MCR_RVFF;
else ENET_MAC->MCR &=~MAC_MCR_RVFF;
/* AutomaticPadRemoval */
if (MAC_Config->AutomaticPadRemoval == ENABLE) ENET_MAC->MCR |=MAC_MCR_APR;
else ENET_MAC->MCR &=~MAC_MCR_APR;
/* DefferalCheck */
if (MAC_Config->DeferralCheck == ENABLE) ENET_MAC->MCR |=MAC_MCR_DCE;
else ENET_MAC->MCR &=~MAC_MCR_DCE;
}
/*******************************************************************************
* Function Name : ENET_SetOperatingMode
* Description : Sets the Operating mode
* Input : ENET_OperatingMode:(see ENET_OperatingMode in 91x_enet.h)
* Output : None
* Return : None
*******************************************************************************/
portBASE_TYPE ENET_SetOperatingMode( void )
{
unsigned portLONG ulStatusReg, ulControlReg, ulLinkAbilityReg;
/* Link status is latched, so read twice to get current value */
ulStatusReg = ENET_MIIReadReg(0, STE100P_STATUS_REG);
ulStatusReg = ENET_MIIReadReg(0, STE100P_STATUS_REG);
if( !( ulStatusReg & STE100P_STATUS_LINKED ) )
{
/* No Link. */
return pdFAIL;
}
ulControlReg = ENET_MIIReadReg(0, STE100P_CONTROL_REG);
if (ulControlReg & STE100P_AUTO_NEGOTIATE_ABILITY)
{
/* AutoNegotiation is enabled. */
if (!(ulStatusReg & STE100P_AUTO_NEGOTIATE_COMPLETE))
{
/* Auto-negotiation in progress. */
return pdFAIL;
}
ulLinkAbilityReg = ENET_MIIReadReg(0, STE100P_LINK_ABILITY);
if( ( ulLinkAbilityReg & STE100P_100FULL ) || ( ulLinkAbilityReg & STE100P_10FULL ) )
{
ENET_MAC->MCR |=MAC_MCR_FDM; /* full duplex mode */
ENET_MAC->MCR &=~MAC_MCR_DRO; /* enable frame reception during transmission */
}
else
{
ENET_MAC->MCR &=~MAC_MCR_FDM; /* half duplex mode */
ENET_MAC->MCR |=MAC_MCR_DRO; /* disable frame reception during transmission */
}
}
else
{
if( ulStatusReg & STE100P_CTRL_FULL )
{
ENET_MAC->MCR |=MAC_MCR_FDM; /* full duplex mode */
ENET_MAC->MCR &=~MAC_MCR_DRO; /* enable frame reception during transmission */
}
else
{
ENET_MAC->MCR &=~MAC_MCR_FDM; /* half duplex mode */
ENET_MAC->MCR |=MAC_MCR_DRO; /* disable frame reception during transmission */
}
}
return pdPASS;
}
/*******************************************************************************
* Function Name : ENET_MIIWriteReg
* Description : Writes a value on the PHY registers
* Input : phyDev PHY device address
: phyReg PHY register to be written
* : phyVal PHY register value
* Output : None
* Return : None
*******************************************************************************/
void ENET_MIIWriteReg (u8 phyDev, u8 phyReg, u32 phyVal)
{
volatile u32 addr;
volatile u32 res; /* temporary result for address register status */
volatile u32 timeout;
/* Prepare the MII register address */
addr = 0;
addr |= ((phyDev<<11) & MAC_MII_ADDR_PHY_ADDR); /* set the PHY address */
addr |= ((phyReg<<6) & MAC_MII_ADDR_MII_REG); /* select the corresponding register */
addr |= MAC_MII_ADDR_MII_WRITE; /* in write mode */
addr |= MAC_MII_ADDR_MII_BUSY;
/* Check for the Busy flag */
timeout=0;
do
{
timeout++;
res = ENET_MAC->MIIA;
} while ((res & MAC_MII_ADDR_MII_BUSY) && (timeout < (u32 )MII_WRITE_TO));
/* Give the value to the MII data register */
ENET_MAC->MIID = (phyVal & 0xFFFF);
/* write the result value into the MII Address register */
ENET_MAC->MIIA =addr;
/* Check for the Busy flag */
timeout=0;
do
{
timeout++;
res = ENET_MAC->MIIA;
} while ((res & MAC_MII_ADDR_MII_BUSY) && (timeout < (u32 )MII_WRITE_TO));
}
/*******************************************************************************
* Function Name : ENET_MIIReadReg
* Description : Writes a value on the PHY
* Input : phyDev PHY device address
* : phyReg PHY register to be read
* Output : None
* Return : The read value (16 bits)
*******************************************************************************/
u32 ENET_MIIReadReg (u8 phyDev, u32 phyReg )
{
u32 rValue;
u32 addr;
u32 res; /* temporary result for address register status */
u32 timeout; /* timeout value for read process */
/* prepare the MII register address */
addr = 0;
addr |= ((phyDev<<11) & MAC_MII_ADDR_PHY_ADDR); /* set the PHY address */
addr |= ((phyReg<<6) & MAC_MII_ADDR_MII_REG); /* select the corresponding register */
addr &= ~(MAC_MII_ADDR_MII_WRITE); /* ... in read mode */
addr |= MAC_MII_ADDR_MII_BUSY;
/* Check for the Busy flag */
timeout = 0;
do
{
timeout++;
res = ENET_MAC->MIIA;
} while ((res & MAC_MII_ADDR_MII_BUSY) && (timeout < (u32 )MII_READ_TO));
/* write the result value into the MII Address register */
ENET_MAC->MIIA = addr;
/* Check for the Busy flag */
timeout = 0;
do
{
timeout++;
res = ENET_MAC->MIIA;
} while ((res & MAC_MII_ADDR_MII_BUSY) && (timeout < (u32 )MII_READ_TO));
/* read the result value from data register*/
rValue = ENET_MAC->MIID;
return (rValue & 0x0000FFFF);
}
/*******************************************************************************
* Function Name : ENET_RxDscrInit
* Description : Initializes the Rx ENET descriptor chain. Single Descriptor
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void ENET_RxDscrInit(void)
{
int i;
for( i = 0; i < ENET_NUM_RX_BUFFERS; i++ )
{
/* Assign temp Rx array to the ENET buffer */
dmaRxDscrBase[ i ].dmaAddr = (u32)&(RxBuff[ i ][ 0 ]);
/* Initialize RX ENET Status and control */
dmaRxDscrBase[ i ].dmaStatCntl = 0x4000;
/* Initialize the next descriptor- In our case its single descriptor */
dmaRxDscrBase[ i ].dmaNext = (u32)&(dmaRxDscrBase[i+1]) | 0x01;
/* Set the max packet size */
dmaRxDscrBase[ i ].dmaStatCntl = ENET_MAX_PACKET_SIZE | ENET_NEXT_ENABLE;
/* Setting the VALID bit */
dmaRxDscrBase[ i ].dmaPackStatus = DMA_DSCR_RX_STATUS_VALID_MSK;
}
dmaRxDscrBase[ ENET_NUM_RX_BUFFERS - 1 ].dmaNext = (u32)&(dmaRxDscrBase[ 0 ]);
/* Setting the RX NEXT Descriptor Register inside the ENET */
ENET_DMA->RXNDAR = (u32)&(dmaRxDscrBase) | 0x01;
}
/*******************************************************************************
* Function Name : ENET_TxDscrInit
* Description : Initializes the Tx ENET descriptor chain with single descriptor
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void ENET_TxDscrInit(void)
{
/* ENET Start Address */
dmaTxDscrBase.dmaAddr = (u32)TxBuff;
/* Next Descriptor Address */
dmaTxDscrBase.dmaNext = (u32)&(dmaTxDscrBase);
/* Initialize ENET status and control */
dmaTxDscrBase.dmaStatCntl = 0;
/* Tx next set to Tx decriptor base */
ENET_DMA->TXNDAR = (u32)&(dmaTxDscrBase);
/* Enable next enable */
ENET_DMA->TXNDAR |= DMA_DSCR_NXT_NPOL_EN;
}
/*******************************************************************************
* Function Name : ENET_Init
* Description : ENET MAC, PHY and DMA initializations
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void ENET_Init ()
{
vu32 regValue;
ENET_MACConfig *MAC_Config;
ENET_MACConfig config;
u32 macAddrLow, macAddrHigh;
/* De-assert the SRESET bit of ENET + MAC devices */
ENET_DMA->SCR &=~DMA_SCR_SRESET;
MAC_Config =&config;
/* Initialize MAC control register with common values */
MAC_Config->ReceiveALL = DISABLE;
if (SCU_GetHCLKFreqValue() > 50000)
MAC_Config->MIIPrescaler = MIIPrescaler_2;
MAC_Config->LoopbackMode = DISABLE;
MAC_Config->AddressFilteringMode = MAC_Perfect_Multicast_Perfect;
MAC_Config->PassWrongFrame = DISABLE;
MAC_Config->LateCollision = DISABLE;
MAC_Config->BroadcastFrameReception = ENABLE;
MAC_Config->PacketRetry = ENABLE;
MAC_Config->RxFrameFiltering = ENABLE;
MAC_Config->AutomaticPadRemoval = ENABLE;
MAC_Config->DeferralCheck = ENABLE;
/* Configure MAC control register */
ENET_MACControlConfig(MAC_Config);
/* DMA initialization */
/* Read the ENET DMA Status and Control Register */
regValue = ENET_DMA->SCR;
/* Setup Tx Max burst size */
regValue &= ~(u32)DMA_SCR_TX_MAX_BURST_SZ;
regValue |= (u32)DMA_SCR_TX_MAX_BURST_SZ_VAL;
/* Setup Rx Max Burst size */
regValue &= ~(u32)DMA_SCR_RX_MAX_BURST_SZ;
regValue |= (u32)DMA_SCR_RX_MAX_BURST_SZ_VAL;
/* Write Tx & Rx burst size to the ENET status and control register */
ENET_DMA->SCR = regValue;
/* Put the PHY in reset mode */
ENET_MIIWriteReg(0x0,MAC_MII_REG_XCR, 0x8000);
/* Delay to assure PHY reset */
vTaskDelay( 3000 );
/* initialize the opearting mode */
while( ENET_SetOperatingMode() == pdFAIL )
{
vTaskDelay( 3000 );
}
/*set MAC physical*/
macAddrLow = (MAC_ADDR3<<24) + (MAC_ADDR2<<16) + \
(MAC_ADDR1<<8) + MAC_ADDR0;
// Higher MAC address
macAddrHigh = (MAC_ADDR5<<8) + MAC_ADDR4;
/* Initialize Rx and Tx descriptors in memory */
ENET_TxDscrInit();
ENET_RxDscrInit();
}
/********************************************************************************
* Function Name : ENET_HandleRxPkt
* Description : receive a packet and copy it to memory pointed by ppkt.
* Input : ppkt: pointer on application receive buffer.
* Output : None
* Return : ENET_NOK - If there is no packet
* : ENET_OK - If there is a packet
*******************************************************************************/
u32 ENET_HandleRxPkt ( void *ppkt)
{
ENET_DMADSCRBase *pDescr;
u16 size;
static int iNextRx = 0;
if( dmaRxDscrBase[ iNextRx ].dmaPackStatus & DMA_DSCR_RX_STATUS_VALID_MSK )
{
return 0;
}
pDescr = &dmaRxDscrBase[ iNextRx ];
/*Get the size of the packet*/
size = ((pDescr->dmaPackStatus & 0x7ff) - 4);
//MEMCOPY_L2S_BY4((u8*)ppkt, RxBuff, size); /*optimized memcopy function*/
memcpy(ppkt, RxBuff[iNextRx], size); //string.h library*/
/* Give the buffer back to ENET */
pDescr->dmaPackStatus = DMA_DSCR_RX_STATUS_VALID_MSK;
iNextRx++;
if( iNextRx >= ENET_NUM_RX_BUFFERS )
{
iNextRx = 0;
}
/* Return no error */
return size;
}
/*******************************************************************************
* Function Name : ENET_TxPkt
* Description : Transmit a packet
* Input : ppkt: pointer to application packet Buffer
* : size: Tx Packet size
* Output : None
* Return : None
*******************************************************************************/
u8 *pcGetNextBuffer( void )
{
if( dmaTxDscrBase.dmaPackStatus & DMA_DSCR_TX_STATUS_VALID_MSK )
{
return NULL;
}
else
{
return ( unsigned char * ) TxBuff;
}
}
void ENET_TxPkt(void *ppkt, u16 size)
{
/* Setting the Frame Length*/
dmaTxDscrBase.dmaStatCntl = (size&0xFFF);
/* Start the ENET by setting the VALID bit in dmaPackStatus of current descr*/
dmaTxDscrBase.dmaPackStatus = DMA_DSCR_TX_STATUS_VALID_MSK;
/* Start the transmit operation */
ENET_DMA->TXSTR|= DMA_TX_START_FETCH;
}
/*******************************************************************************
* Function Name : ENET_Start
* Description : Enables ENET MAC reception / transmission & starts DMA fetch
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void ENET_Start ( void)
{
u32 value;
/* Force a ENET abort by software for the receive block */
ENET_DMA->RXSTR &=~ DMA_RX_START_DMA_EN;
/* Force a ENET abort by software for the transmit block */
ENET_DMA->TXSTR &=~DMA_TX_START_DMA_EN;
/* Reset all interrupts */
ENET_DMA->ISR = 0xFFFFFFFF;
/* Setup Descriptor Fetch ENET_PhyDelay for Receive Block */
value = ENET_DMA->RXSTR;
value &= ~( DMA_RX_START_DFETCH_DLY );
value |= DMA_RX_START_DFETCH_DEFAULT;
ENET_DMA->RXSTR= value;
/* Setup Descriptor Fetch ENET_PhyDelay for Transmit Block */
value = ENET_DMA->TXSTR;
value &= ~( DMA_TX_START_DFETCH_DLY );
value |= DMA_TX_START_DFETCH_DEFAULT;
ENET_DMA->TXSTR= value;
/* Set Tx underrun bit */
value &= ~( DMA_TX_START_URUN );
value |= DMA_TX_START_URUN;
ENET_DMA->TXSTR = value;
/* Clear the interrupts */
ENET_DMA->IER = 0x0;
/* MAC TX enable */
ENET_MAC->MCR|= MAC_MCR_TE;
/* MAC RX enable */
ENET_MAC->MCR|= MAC_MCR_RE;
/* Start the DMA Fetch */
ENET_DMA->RXSTR|= DMA_RX_START_FETCH;
}
/*******************************************************************************
* Function Name : ENET_InitClocksGPIO
* Description : Reset, clocks & GPIO Ethernet Pin initializations
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void ENET_InitClocksGPIO(void)
{
GPIO_InitTypeDef GPIO_Struct;
SCU_AHBPeriphClockConfig(__ENET, ENABLE);
SCU_AHBPeriphReset(__ENET,DISABLE);
SCU_PHYCLKConfig(ENABLE);
GPIO_DeInit(GPIO1);
GPIO_Struct.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 |GPIO_Pin_3 |GPIO_Pin_4 |GPIO_Pin_7 ;
GPIO_Struct.GPIO_Type = GPIO_Type_PushPull;
GPIO_Struct.GPIO_Direction = GPIO_PinOutput;
GPIO_Struct.GPIO_IPConnected = GPIO_IPConnected_Disable;
GPIO_Struct.GPIO_Alternate=GPIO_OutputAlt2;
GPIO_Init(GPIO1, &GPIO_Struct);
GPIO_DeInit(GPIO5);
GPIO_Struct.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3;
GPIO_Struct.GPIO_Type = GPIO_Type_PushPull;
GPIO_Struct.GPIO_Direction = GPIO_PinOutput;
GPIO_Struct.GPIO_IPConnected = GPIO_IPConnected_Disable;
GPIO_Struct.GPIO_Alternate=GPIO_OutputAlt2;
GPIO_Init(GPIO5, &GPIO_Struct);
}
/******************** (C) COPYRIGHT 2006 STMicroelectronics *******************/

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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_fmi.c
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : This file provides all the FMI software functions.
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Standard include ----------------------------------------------------------*/
#include "91x_fmi.h"
/* Include of other module interface headers ---------------------------------*/
/* Local includes ------------------------------------------------------------*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define TIMEOUT 0xFFFFFF /* Timeout value */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Interface functions -------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : FMI_BankRemapConfig
* Description : Configure the addresses and sizes of bank 0 and bank 1.
* Input1 : FMI_BootBankSize: specifies the boot bank size.
* This parameter can be one of the following values:
* - 0x0: 32KBytes.
* - 0x1: 64KBytes.
* - 0x2: 128KBytes.
* - 0x3: 256KBytes.
* - 0x4: 512KBytes.
* ....
* - 0xB: 64MBytes.
* Input2 : FMI_NonBootBankSize: specifies the non boot bank size.
* This parameter can be one of the following values:
* - 0x0: 8KBytes.
* - 0x1: 16KBytes.
* - 0x2: 32KBytes.
* - 0x3: 64KBytes.
* ....
* - 0xD: 64MBytes.
* Input3 : FMI_BootBankAddress: specifies the address of the boot bank.
* Input4 : FMI_NonBootBankAddress: specifies the address of the non
* boot bank.
* Output : None
* Return : None
*******************************************************************************/
void FMI_BankRemapConfig(u8 FMI_BootBankSize, u8 FMI_NonBootBankSize, \
u32 FMI_BootBankAddress, u32 FMI_NonBootBankAddress)
{
FMI->BBSR = FMI_BootBankSize;
FMI->NBBSR = FMI_NonBootBankSize;
FMI->BBADR = (FMI_BootBankAddress >> 2);
FMI->NBBADR = (FMI_NonBootBankAddress >> 2);
FMI->CR |= 0x18; /* Enable bank 1 */
}
/*******************************************************************************
* Function Name : FMI_Config
* Description : Configure the FMI.
* Input1 : FMI_ReadWaitState: specifies the needed read wait states.
* This parameter can be one of the following values:
* - FMI_READ_WAIT_STATE_1: One read wait state.
* - FMI_READ_WAIT_STATE_2: Two read wait states.
* - FMI_READ_WAIT_STATE_3: Three read wait states.
* Input2 : FMI_WriteWaitState: specifies the needed write wait states.
* This parameter can be one of the following values:
* - FMI_WRITE_WAIT_STATE_1: One write wait state.
* - FMI_WRITE_WAIT_STATE_2: Two write wait states.
* Input3 : FMI_PWD: specifies the power down mode status.
* This parameter can be one of the following values:
* - FMI_PWD_ENABLE: Enable the PWD.
* - FMI_PWD_DISABLE: Disable the PWD.
* Input4 : FMI_LVDEN: specifies the low voltage detector status.
* This parameter can be one of the following values:
* - FMI_LVD_ENABLE: Enable the LVD.
* - FMI_LVD_DISABLE: Disable the LVD.
* Input5 : FMI_FreqRange: specifies the working frequency range.
* This parameter can be one of the following values:
* - FMI_FREQ_LOW: Low working frequency (up to 66MHz).
* - FMI_FREQ_HIGH: High working frequency (above 66MHz) .
* Output : None
* Return : None
*******************************************************************************/
void FMI_Config(u16 FMI_ReadWaitState, u32 FMI_WriteWaitState, u16 FMI_PWD,\
u16 FMI_LVDEN, u16 FMI_FreqRange)
{
/* Configure the write wait state value */
if (FMI_WriteWaitState == FMI_WRITE_WAIT_STATE_1)
{
FMI->CR |= FMI_WRITE_WAIT_STATE_1;
}
else
{
FMI->CR &= FMI_WRITE_WAIT_STATE_0;
}
/* Write a write flash configuration register command */
*(vu16 *)FMI_BANK_1 = 0x60;
/* Configure the flash configuration register */
*(vu16 *)(FMI_BANK_1|FMI_ReadWaitState|FMI_PWD|FMI_LVDEN|FMI_FreqRange) = 0x03;
}
/*******************************************************************************
* Function Name : FMI_EraseSector
* Description : Erase the needed sector.
* Input : FMI_Sector: specifies the sector to be erased.
* This parameter can be one of the following values:
* - FMI_B0S0: FMI bank 0 sector 0.
* - FMI_B0S1: FMI bank 0 sector 1.
* - FMI_B0S2: FMI bank 0 sector 2.
* - FMI_B0S3: FMI bank 0 sector 3.
* - FMI_B0S4: FMI bank 0 sector 4.
* - FMI_B0S5: FMI bank 0 sector 5.
* - FMI_B0S6: FMI bank 0 sector 6.
* - FMI_B0S7: FMI bank 0 sector 7.
* - FMI_B1S0: FMI bank 1 sector 0.
* - FMI_B1S1: FMI bank 1 sector 1.
* - FMI_B1S2: FMI bank 1 sector 2.
* - FMI_B1S3: FMI bank 1 sector 3.
* Output : None
* Return : None
*******************************************************************************/
void FMI_EraseSector(vu32 FMI_Sector)
{
/* Write an erase set-up command to the sector */
*(vu16 *)FMI_Sector = 0x20;
/* Write an erase confirm command to the sector */
*(vu16 *)FMI_Sector = 0xD0;
}
/*******************************************************************************
* Function Name : FMI_EraseBank
* Description : Erase the needed bank.
* Input : FMI_Bank: specifies the bank to be erased.
* This parameter can be one of the following values:
* - FMI_BANK_0: FMI bank 0.
* - FMI_BANK_1: FMI bank 1.
* Output : None
* Return : None
*******************************************************************************/
void FMI_EraseBank(vu32 FMI_Bank)
{
/* Write a bank erase set-up command to the bank */
*(vu16 *)FMI_Bank = 0x80;
/* Write an erase confirm command to the sector */
*(vu16 *)FMI_Bank = 0xD0;
}
/*******************************************************************************
* Function Name : FMI_WriteHalfWord
* Description : Write a halfword to the needed Flash memory address.
* Input 1 : FMI_Address: specifies the address offset where the data will
* be written.
* Input 2 : FMI_Data: the needed data.
* Output : None
* Return : None
*******************************************************************************/
void FMI_WriteHalfWord(u32 FMI_Address, u16 FMI_Data)
{
/* Write a program command to the sector to be written */
*(vu16 *)(FMI_Address & 0xFFFFFFFC) = 0x40;
/* Write the halfword to the destination address */
*(vu16 *)FMI_Address = FMI_Data;
}
/*******************************************************************************
* Function Name : FMI_WriteOTPHalfWord
* Description : Write a halfword to the needed OTP sector address.
* Input 1 : FMI_OTPHWAddress: specifies the halfword address offset
* where the data will be written.
* This parameter can be one of the following values:
* - FMI_OTP_LOW_HALFWORD_0: OTP Low halfword 0.
* - FMI_OTP_HIGH_HALFWORD_0: OTP High halfword 0.
* - FMI_OTP_LOW_HALFWORD_1: OTP Low halfword 1.
* - FMI_OTP_HIGH_HALFWORD_1: OTP High halfword 1.
* - FMI_OTP_LOW_HALFWORD_2: OTP Low halfword 2.
* - FMI_OTP_HIGH_HALFWORD_2: OTP High halfword 2.
* - FMI_OTP_LOW_HALFWORD_3: OTP Low halfword 3.
* - FMI_OTP_HIGH_HALFWORD_3: OTP High halfword 3.
* - FMI_OTP_LOW_HALFWORD_4: OTP Low halfword 4.
* - FMI_OTP_HIGH_HALFWORD_4: OTP High halfword 4.
* - FMI_OTP_LOW_HALFWORD_5: OTP Low halfword 5.
* - FMI_OTP_HIGH_HALFWORD_5: OTP High halfword 5.
* - FMI_OTP_LOW_HALFWORD_6: OTP Low halfword 6.
* - FMI_OTP_HIGH_HALFWORD_6: OTP High halfword 6.
* - FMI_OTP_LOW_HALFWORD_7: OTP Low halfword 7.
* - FMI_OTP_HIGH_HALFWORD_7: OTP High halfword 7.
* Input 2 : FMI_OTPData: The needed OTP data.
* Output : None
* Return : None
*******************************************************************************/
void FMI_WriteOTPHalfWord(u8 FMI_OTPHWAddress, u16 FMI_OTPData)
{
/* Write a write OTP command to the needed address */
*(vu16 *)(FMI_BANK_1) = 0xC0;
/* Write the halfword to the destination address */
*(vu16 *)(FMI_BANK_1 + FMI_OTPHWAddress) = FMI_OTPData;
}
/*******************************************************************************
* Function Name : FMI_ReadWord
* Description : Read the correspondent data.
* Input : FMI_Address: specifies the needed address.
* Output : None
* Return : The data contained in the specified address.
*******************************************************************************/
u32 FMI_ReadWord(u32 FMI_Address)
{
return(*(u32*)FMI_Address);
}
/*******************************************************************************
* Function Name : FMI_ReadOTPData
* Description : Read data from the OTP sector.
* Input : FMI_OTPAddress: specifies the address of the data to be read.
* This parameter can be one of the following values:
* - FMI_OTP_WORD_0: FMI bank 0 sector 0.
* - FMI_OTP_WORD_1: FMI bank 0 sector 1.
* - FMI_OTP_WORD_2: FMI bank 0 sector 2.
* - FMI_OTP_WORD_3: FMI bank 0 sector 3.
* - FMI_OTP_WORD_4: FMI bank 0 sector 4.
* - FMI_OTP_WORD_5: FMI bank 0 sector 5.
* - FMI_OTP_WORD_6: FMI bank 0 sector 6.
* - FMI_OTP_WORD_7: FMI bank 0 sector 7.
* Output : None
* Return : The needed OTP words.
*******************************************************************************/
u32 FMI_ReadOTPData(u8 FMI_OTPAddress)
{
u32 OTP_Data = 0x0;
/* write a read OTP sector command */
*(vu16 *)(FMI_BANK_1) = 0x98;
/* Read the correspondent data */
OTP_Data = (*(vu32*)(FMI_BANK_1 + FMI_OTPAddress));
/* Write a read array command */
*(vu16 *)(FMI_BANK_1) = 0xFF;
return OTP_Data;
}
/*******************************************************************************
* Function Name : FMI_GetFlagStatus
* Description : Check whether the specified FMI flag is set or not.
* Input1 : FMI_Flag: flag to check.
* This parameter can be one of the following values:
* - FMI_FLAG_SPS: Sector Protection Status Flag.
* - FMI_FLAG_PSS: Program Suspend Status Flag.
* - FMI_FLAG_PS: Program Status Flag.
* - FMI_FLAG_ES: Erase Status Flag.
* - FMI_FLAG_ESS: Erase Suspend Status Flag.
* - FMI_FLAG_PECS: FPEC Status Flag.
* Input2 : FMI_Bank: specifies the needed bank.
* This parameter can be one of the following values:
* - FMI_BANK_0: FMI bank 0.
* - FMI_BANK_1: FMI bank 1.
* Output : None
* Return : None
*******************************************************************************/
FlagStatus FMI_GetFlagStatus(u8 FMI_Flag, vu32 FMI_Bank)
{
u16 FMI_Status_Register = 0;
/* Write a read status register command */
*(vu16 *)FMI_Bank = 0x70;
/* Wait until operation completion */
while(!((*(vu16 *)FMI_Bank) & 0x80));
/* Read the status register */
FMI_Status_Register = *(vu16 *)FMI_Bank;
/* Write a read array command */
*(vu16 *)FMI_Bank = 0xFF;
if((FMI_Status_Register & FMI_Flag) != RESET)
{
return SET;
}
else
{
return RESET;
}
}
/*******************************************************************************
* Function Name : FMI_GetReadWaitStateValue
* Description : Get the current Read wait state value.
* Input : None
* Output : None
* Return : The current read wait states value.
*******************************************************************************/
u16 FMI_GetReadWaitStateValue(void)
{
u16 FMI_Configuration_Register = 0;
/* Write a read flash configuration register command */
*(vu16 *)FMI_BANK_1 = 0x90;
/* Read the flash configuration register */
FMI_Configuration_Register = *(vu16 *)(FMI_BANK_1 + 0x14);
/* Write a read array command */
*(vu16 *)FMI_BANK_1 = 0xFF;
FMI_Configuration_Register = ((FMI_Configuration_Register>>11) + 1) & 0x3;
/* Return the wait states value */
return FMI_Configuration_Register;
}
/*******************************************************************************
* Function Name : FMI_GetWriteWaitStateValue
* Description : Get the current write wait state value.
* Input : None
* Output : None
* Return : The current write wait states value.
*******************************************************************************/
u16 FMI_GetWriteWaitStateValue(void)
{
return ((u16)((FMI->CR & 0x100) >> 8));
}
/*******************************************************************************
* Function Name : FMI_SuspendEnable
* Description : Suspend command enable.
* Input : FMI_Bank: specifies the bank to be suspended.
* This parameter can be one of the following values:
* - FMI_BANK_0: FMI bank 0.
* - FMI_BANK_1: FMI bank 1.
* Output : None
* Return : None
*******************************************************************************/
void FMI_SuspendEnable(vu32 FMI_Bank)
{
/* Write a suspend command to the bank */
*(vu16 *)FMI_Bank = 0xB0;
}
/*******************************************************************************
* Function Name : FMI_ResumeEnable
* Description : Resume the suspended command.
* Input : FMI_Bank: specifies the suspended bank.
* This parameter can be one of the following values:
* - FMI_BANK_0: FMI bank 0.
* - FMI_BANK_1: FMI bank 1.
* Output : None
* Return : None
*******************************************************************************/
void FMI_ResumeEnable(vu32 FMI_Bank)
{
/* Write a resume command to the bank */
*(vu16 *)FMI_Bank = 0xD0;
}
/*******************************************************************************
* Function Name : FMI_ClearFlag
* Description : Clear the FMI Flags on the correspondent bank.
* Input : FMI_Bank: specifies the needed bank.
* This parameter can be one of the following values:
* - FMI_BANK_0: FMI bank 0.
* - FMI_BANK_1: FMI bank 1.
* Output : None
* Return : None
*******************************************************************************/
void FMI_ClearFlag(vu32 FMI_Bank)
{
/* Write a clear status register command */
*(vu16 *)FMI_Bank = 0x50;
}
/*******************************************************************************
* Function Name : FMI_WriteProtectionCmd
* Description : Enable or disable the write protection for the needed sector.
* Input1 : FMI_Sector: specifies the sector to be protected or
* unprotected.
* This parameter can be one of the following values:
* - FMI_B0S0: FMI bank 0 sector 0.
* - FMI_B0S1: FMI bank 0 sector 1.
* - FMI_B0S2: FMI bank 0 sector 2.
* - FMI_B0S3: FMI bank 0 sector 3.
* - FMI_B0S4: FMI bank 0 sector 4.
* - FMI_B0S5: FMI bank 0 sector 5.
* - FMI_B0S6: FMI bank 0 sector 6.
* - FMI_B0S7: FMI bank 0 sector 7.
* - FMI_B1S0: FMI bank 1 sector 0.
* - FMI_B1S1: FMI bank 1 sector 1.
* - FMI_B1S2: FMI bank 1 sector 2.
* - FMI_B1S3: FMI bank 1 sector 3.
* Input2 : FMI_NewState: specifies the protection status.
* This parameter can be one of the following values:
* - ENABLE: Enable the protection.
* - DISABLE: Disable the protection.
* Output : None
* Return : None
*******************************************************************************/
void FMI_WriteProtectionCmd(vu32 FMI_Sector, FunctionalState FMI_NewState)
{
if (FMI_NewState == ENABLE)
{
*(vu16*)FMI_Sector = 0x60;
*(vu16*)FMI_Sector = 0x01;
*(vu16*)FMI_Sector = 0xFF;
}
else /* DISABLE */
{
*(vu16*)FMI_Sector = 0x60;
*(vu16*)FMI_Sector = 0xD0;
*(vu16*)FMI_Sector = 0xFF;
}
}
/*******************************************************************************
* Function Name : FMI_GetWriteProtectionStatus
* Description : Get the write protection status for the needed sector.
* Input : FMI_Sector_Mask: specifies the needed sector mask.
* This parameter can be one of the following values:
* - FMI_B0S0_MASK: FMI bank 0 sector 0.
* - FMI_B0S1_MASK: FMI bank 0 sector 1.
* - FMI_B0S2_MASK: FMI bank 0 sector 2.
* - FMI_B0S3_MASK: FMI bank 0 sector 3.
* - FMI_B0S4_MASK: FMI bank 0 sector 4.
* - FMI_B0S5_MASK: FMI bank 0 sector 5.
* - FMI_B0S6_MASK: FMI bank 0 sector 6.
* - FMI_B0S7_MASK: FMI bank 0 sector 7.
* - FMI_B1S0_MASK: FMI bank 1 sector 0.
* - FMI_B1S1_MASK: FMI bank 1 sector 1.
* - FMI_B1S2_MASK: FMI bank 1 sector 2.
* - FMI_B1S3_MASK: FMI bank 1 sector 3.
* Output : None
* Return : The Protection Status of the needed sector.
* - RESET: The needed sector is not write protected.
* - SET : The needed sector is write protected.
*******************************************************************************/
FlagStatus FMI_GetWriteProtectionStatus(u32 FMI_Sector_Mask)
{
u16 Protection_Level_1_Register = 0;
/* Write a read flash protection level 1 register command */
*(vu16 *)FMI_BANK_1 = 0x90;
/* Read the flash protection level 1 register */
Protection_Level_1_Register = *(vu16 *)(FMI_BANK_1 + 0x10);
/* Write a read array command */
*(vu16 *)FMI_BANK_1 = 0xFF;
if (Protection_Level_1_Register &= FMI_Sector_Mask)
{
return SET;
}
else
{
return RESET;
}
}
/*******************************************************************************
* Function Name : FMI_WaitForLastOperation
* Description : Wait until the last operation (Write halfword, Write OTP
* halfword, Erase sector and Erase bank) completion.
* Input : FMI_Bank: specifies the bank where the operation is on going.
* This parameter can be one of the following values:
* - FMI_BANK_0: FMI bank 0.
* - FMI_BANK_1: FMI bank 1.
* Output : None
* Return : The timeout status.
* This parameter can be one of the following values:
* - FMI_TIME_OUT_ERROR: Timeout error occurred.
* - FMI_NO_TIME_OUT_ERROR: No timeout error.
*******************************************************************************/
u8 FMI_WaitForLastOperation(vu32 FMI_Bank)
{
u32 Time_Out = 0;
/* Write a read status register command */
*(vu16 *)(FMI_Bank) = 0x70;
/* Wait until operation compeletion */
while((!((*(vu16 *)FMI_Bank) & 0x80))&&(Time_Out < TIMEOUT ))
{
Time_Out ++; /* Time Out */
}
/* Write a read array command */
*(vu16 *)FMI_Bank = 0xFF;
if (Time_Out == TIMEOUT)
{
return FMI_TIME_OUT_ERROR;
}
else
{
return FMI_NO_TIME_OUT_ERROR;
}
}
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_gpio.c
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : This file provides all the GPIO software functions.
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "91x_gpio.h"
#include "91x_scu.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static u8 GPIO_GetGPIONumber(GPIO_TypeDef* GPIOx);
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : GPIO_DeInit
* Description : Deinitializes the GPIOx peripheral registers to their default
* reset values.
* Input : GPIOx: where x can be (0..9) to select the GPIO peripheral.
* Output : None
* Return : None
*******************************************************************************/
void GPIO_DeInit(GPIO_TypeDef* GPIOx)
{
/* Reset the GPIO registers values */
if(GPIOx == GPIO0)
{
SCU_APBPeriphReset(__GPIO0,ENABLE);
SCU_APBPeriphReset(__GPIO0,DISABLE);
SCU->GPIOTYPE[0x00] = 0x0000 ;
SCU->GPIOOUT[0x00] = 0x0000;
SCU->GPIOIN[0x00] = 0x0000;
}
if(GPIOx == GPIO1)
{
SCU_APBPeriphReset(__GPIO1,ENABLE);
SCU_APBPeriphReset(__GPIO1,DISABLE);
SCU->GPIOTYPE[0x01] = 0x0000 ;
SCU->GPIOOUT[0x01] = 0x0000;
SCU->GPIOIN[0x01] = 0x0000;
}
if(GPIOx == GPIO2)
{
SCU_APBPeriphReset(__GPIO2,ENABLE);
SCU_APBPeriphReset(__GPIO2,DISABLE);
SCU->GPIOTYPE[0x02] = 0x0000 ;
SCU->GPIOOUT[0x02] = 0x0000;
SCU->GPIOIN[0x02] = 0x0000;
}
if(GPIOx == GPIO3)
{
SCU_APBPeriphReset(__GPIO3,ENABLE);
SCU_APBPeriphReset(__GPIO3,DISABLE);
SCU->GPIOTYPE[0x03] = 0x0000 ;
SCU->GPIOOUT[0x03] = 0x0000;
SCU->GPIOIN[0x03] = 0x0000;
}
if(GPIOx == GPIO4)
{
SCU_APBPeriphReset(__GPIO4,ENABLE);
SCU_APBPeriphReset(__GPIO4,DISABLE);
SCU->GPIOTYPE[0x04] = 0x0000 ;
SCU->GPIOOUT[0x04] = 0x0000;
SCU->GPIOIN[0x04] = 0x0000;
SCU->GPIOANA = 0x00;
}
if(GPIOx == GPIO5)
{
SCU_APBPeriphReset(__GPIO5,ENABLE);
SCU_APBPeriphReset(__GPIO5,DISABLE);
SCU->GPIOTYPE[0x05] = 0x0000 ;
SCU->GPIOOUT[0x05] = 0x0000;
SCU->GPIOIN[0x05] = 0x0000;
}
if(GPIOx == GPIO6)
{
SCU_APBPeriphReset(__GPIO6,ENABLE);
SCU_APBPeriphReset(__GPIO6,DISABLE);
SCU->GPIOTYPE[0x06] = 0x0000 ;
SCU->GPIOOUT[0x06] = 0x0000;
SCU->GPIOIN[0x06] = 0x0000;
}
if(GPIOx == GPIO7)
{
SCU_APBPeriphReset(__GPIO7,ENABLE);
SCU_APBPeriphReset(__GPIO7,DISABLE);
SCU->GPIOOUT[0x07] = 0xAAAA;
SCU->GPIOOUT[0x07] = 0x0000;
SCU->GPIOIN[0x07] = 0x0000;
}
if(GPIOx == GPIO8)
{
SCU_APBPeriphReset(__GPIO8,ENABLE);
SCU_APBPeriphReset(__GPIO8,DISABLE);
SCU->GPIOEMI = 0x00;
}
if(GPIOx == GPIO9)
{
SCU_APBPeriphReset(__GPIO9,ENABLE);
SCU_APBPeriphReset(__GPIO9,DISABLE);
SCU->GPIOEMI = 0x00;
}
}
/*******************************************************************************
* Function Name : GPIO_Init
* Description : Initializes the GPIOx peripheral according to the specified
* parameters in the GPIO_InitStruct .
* Input :- GPIOx: where x can be (0..9) to select the GPIO peripheral.
* - GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
* contains the configuration information for the specified GPIO
* peripheral.
* Output : None
* Return : None
*******************************************************************************/
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
{
/* Select pin direction */
u8 PinNumber = 0;
u8 Counter = 0;
u8 GPIO_Number = 0;
GPIO_Number = GPIO_GetGPIONumber(GPIOx);
if(GPIO_InitStruct->GPIO_Direction == GPIO_PinOutput)
{
GPIOx->DDR |= GPIO_InitStruct->GPIO_Pin;
}
else
{
GPIOx->DDR &= ~GPIO_InitStruct->GPIO_Pin;
}
for (Counter = 0; Counter < 8;Counter++)
{
/*Search pin number*/
PinNumber = (GPIO_InitStruct->GPIO_Pin & (1 <<Counter));
if((PinNumber >> Counter) == 1)
{
/*Output ALternate 0*/
SCU->GPIOOUT[GPIO_Number] &= ~(0x3 <<(Counter *2));
if(GPIO_InitStruct->GPIO_Alternate == GPIO_OutputAlt1)
{
/*Output ALternate 1*/
SCU->GPIOOUT[GPIO_Number] |= 1 << (Counter *2);
}
if(GPIO_InitStruct->GPIO_Alternate == GPIO_OutputAlt2)
{
/*Output ALternate 2*/
SCU->GPIOOUT[GPIO_Number] |= 0x2 << (Counter *2);
}
if(GPIO_InitStruct->GPIO_Alternate == GPIO_OutputAlt3)
{
/*Output ALternate 3*/
SCU->GPIOOUT[GPIO_Number] |= 0x3 << (Counter *2);
}
/*Type configuration: PushPull or Open Collector*/
SCU->GPIOTYPE[GPIO_Number] &= ~(0x1 << Counter) ;
if(GPIO_InitStruct->GPIO_Type == GPIO_Type_OpenCollector)
{
/*Open Drain configuration*/
SCU->GPIOTYPE[GPIO_Number] |= 0x1 << Counter;
}
/*IP Connected disable*/
SCU->GPIOIN[GPIO_Number] &= ~(0x1 << Counter) ;
if(GPIO_InitStruct->GPIO_IPConnected == GPIO_IPConnected_Enable)
{
/*IP Connected enable*/
SCU->GPIOIN[GPIO_Number] |= 0x1 << Counter;
}
}
}
}
/*******************************************************************************
* Function Name : GPIO_StructInit
* Description : Initialize the GPIO Init Structure parameters
* Input : GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure
* which will be initialized.
* Output : None
* Return : None
*******************************************************************************/
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
{
/* Reset GPIO init structure parameters values */
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
GPIO_InitStruct->GPIO_Direction = GPIO_PinInput;
GPIO_InitStruct->GPIO_Type = GPIO_Type_PushPull;
GPIO_InitStruct->GPIO_IPConnected = GPIO_IPConnected_Disable;
GPIO_InitStruct->GPIO_Alternate = GPIO_InputAlt1;
}
/*******************************************************************************
* Function Name : GPIO_ReadBit
* Description : Reads the specified port pin
* Input : - GPIOx: where x can be (0..9) to select the GPIO peripheral.
* : - GPIO_Pin: the Pin number. This parameter can be GPIO_Pin_x
* where x can be (0..7).
* Output : None
* Return : The port pin value
*******************************************************************************/
u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin)
{
if ((((GPIOx->DR[GPIO_Pin<<2])) & GPIO_Pin) != Bit_RESET )
{
return Bit_SET;
}
else
{
return Bit_RESET;
}
}
/*******************************************************************************
* Function Name : GPIO_Read
* Description : Reads the specified GPIO data port
* Input : - GPIOx: where x can be (0..9) to select the GPIO peripheral.
* Output : None
* Return : GPIO data port word value.
*******************************************************************************/
u8 GPIO_Read(GPIO_TypeDef* GPIOx)
{
return (GPIOx->DR[0x3FC]);
}
/*******************************************************************************
* Function Name : GPIO_WriteBit
* Description : Sets or clears the selected data port bit.
* Input : - GPIOx: where x can be (0..9) to select the GPIO peripheral.
* - GPIO_Pin: the Pin number. This parameter can be GPIO_Pin_x
* where x can be (0..7).
* - BitVal: this parameter specifies the value to be written
* to the selected bit.
* BitVal must be one of the BitAction enum values:
* - Bit_RESET: to clear the port pin
* - Bit_SET: to set the port pin
* Output : None
* Return : None
*******************************************************************************/
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin, BitAction BitVal)
{
if(BitVal == Bit_SET)
{
GPIOx->DR[GPIO_Pin <<2] = GPIO_Pin;
}
else
{
GPIOx->DR[GPIO_Pin <<2] = 0x00;
}
}
/*******************************************************************************
* Function Name : GPIO_Write
* Description : Writes the passed value in the selected data GPIOx port
* register.
* Input :- GPIOx: where x can be (0..9) to select the GPIO peripheral.
* - PortVal: the value to be written to the data port register.
* Output : None
* Return : None
*******************************************************************************/
void GPIO_Write(GPIO_TypeDef* GPIOx, u8 PortVal)
{
GPIOx->DR[0x3FC] = PortVal;
}
/*******************************************************************************
* Function Name : GPIO_EMIConfig
* Description : Enables or disables GPIO 8 and 9 in EMI mode.
* Input : - NewState: new state of the EMI.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void GPIO_EMIConfig(FunctionalState NewState)
{
if(NewState == ENABLE)
{
SCU->GPIOEMI = 0x01;
}
else
{
SCU->GPIOEMI = 0x00;
}
}
/*******************************************************************************
* Function Name : GPIO_ANAPinConfig
* Description : Enables or disables pins from GPIO 4 in Analogue mode.
* Input :- GPIO_ANAChannel: selects the ADC channel pin.
* This parameter can be one of the following values:
* GPIO_ANAChannel0
* GPIO_ANAChannel1
* GPIO_ANAChannel2
* GPIO_ANAChannel3
* GPIO_ANAChannel4
* GPIO_ANAChannel5
* GPIO_ANAChannel6
* GPIO_ANAChannel7
* GPIO_ANAChannelALL
* - NewState: new state of the port pin.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void GPIO_ANAPinConfig(u8 GPIO_ANAChannel, FunctionalState NewState)
{
if(NewState == ENABLE)
{
if(GPIO_ANAChannel == GPIO_ANAChannelALL)
{
SCU->GPIOOUT[4] = 0x0000;
SCU->GPIOIN[4] = 0x00;
}
else
{
SCU->GPIOOUT[4] &= ~(0x3<<(GPIO_ANAChannel-1));
SCU->GPIOIN[4] &= ~GPIO_ANAChannel;
}
SCU->GPIOANA |= GPIO_ANAChannel;
}
else
{
SCU->GPIOANA &= ~GPIO_ANAChannel;
}
}
/*******************************************************************************
* Function Name : GPIO_GetGPIONumber
* Description : searche the GPIO number.
* Input : GPIOx: where x can be (0..9) to select the GPIO peripheral.
* Output : None
* Return : GPIO number
*******************************************************************************/
u8 GPIO_GetGPIONumber(GPIO_TypeDef* GPIOx)
{
if(GPIOx == GPIO1)
{
return 1;
}
if(GPIOx == GPIO2)
{
return 2;
}
if(GPIOx == GPIO3)
{
return 3;
}
if(GPIOx == GPIO4)
{
return 4;
}
if(GPIOx == GPIO5)
{
return 5;
}
if(GPIOx == GPIO6)
{
return 6;
}
if(GPIOx == GPIO7)
{
return 7;
}
if(GPIOx == GPIO8)
{
return 8;
}
if(GPIOx == GPIO9)
{
return 9;
}
return 0;
}
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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Demo/ARM9_STR91X_IAR/Library/source/91x_it.c
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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_it.c
* Author : MCD Application Team
* Date First Issued : 03/31/2006 : Beta Version V0.1
* Description : Main Interrupt Service Routines.
********************************************************************************
* This file can be used to describe all the exceptions subroutines
* that may occur within user application.
* When an interrupt happens, the software will branch automatically
* to the corresponding routine according to the interrupt vector
* loaded in the PC register.
* The following routines are all empty, user can write code for
* exceptions handlers and peripherals IRQ interrupts.
********************************************************************************
* History:
* 03/31/2006 : Beta Version V0.1
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#include "91x_it.h"
/*******************************************************************************
* Function Name : Undefined_Handler
* Description : This function Undefined instruction exception.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void Undefined_Handler(void)
{
// NOT USED.
}
/*******************************************************************************
* Function Name : SWI_Handler
* Description : This function handles SW exception.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void SWI_Handler(void)
{
// NOT USED.
}
/*******************************************************************************
* Function Name : Prefetch_Handler
* Description : This function handles preftetch abort exception.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void Prefetch_Handler(void)
{
// NOT USED.
}
/*******************************************************************************
* Function Name : Abort_Handler
* Description : This function handles data abort exception.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void Abort_Handler(void)
{
// NOT USED.
}
/*******************************************************************************
* Function Name : FIQ_Handler
* Description : This function handles FIQ exception.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void FIQ_Handler(void)
{
// NOT USED.
}
/*******************************************************************************
* Function Name : SW_IRQHandler
* Description : This function handles the SW interrupt request
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void SW_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : ARMRX_IRQHandler
* Description : This function handles the ARMRX interrupt request
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void ARMRX_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : ARMTX_IRQHandler
* Description : This function handles the ARMTX interrupt request
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void ARMTX_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : TIM0_IRQHandler
* Description : This function handles the TIM0 interrupt request
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TIM0_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : TIM1_IRQHandler
* Description : This function handles the TIM1 interrupt request
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TIM1_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : TIM2_IRQHandler
* Description : This function handles the TIM2 interrupt request
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TIM2_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : TIM3_IRQHandler
* Description : This function handles the TIM3 interrupt request
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void TIM3_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : USBHP_IRQHandler
* Description : This function handles the USBHP interrupt request
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void USBHP_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : USBLP_IRQHandler
* Description : This function handles the USBLP interrupt request
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void USBLP_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : SCU_IRQHandler
* Description : This function handles the SCU interrupt request
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void SCU_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : DMA_IRQHandler
* Description : This function handles the DMA interrupt request
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void DMA_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : CAN_IRQHandler
* Description : This function handles the CAN interrupt request
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void CAN_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : MC_IRQHandler
* Description : This function handles the MC interrupt request
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void MC_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : ADC_IRQHandler
* Description : This function handles the ADC interrupt request
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void ADC_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : UART0_IRQHandler
* Description : This function handles the UART0 interrupt request
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void UART0_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : UART2_IRQHandler
* Description : This function handles the UART2 interrupt request
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void UART2_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : I2C0_IRQHandler
* Description : This function handles the I2C0 interrupt request
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void I2C0_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : I2C1_IRQHandler
* Description : This function handles the I2C1 interrupt request
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void I2C1_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : SSP0_IRQHandler
* Description : This function handles the SSP0 interrupt request
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void SSP0_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : SSP1_IRQHandler
* Description : This function handles the SSP1 interrupt request
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void SSP1_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : LVD_IRQHandler
* Description : This function handles the LVD interrupt request
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void LVD_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : RTC_IRQHandler
* Description : This function handles the RTC interrupt request
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void RTC_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : WIU_IRQHandler
* Description : This function handles the WIU interrupt request
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void WIU_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : EXTIT0_IRQHandler
* Description : This function handles the EXTIT0 interrupt request
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void EXTIT0_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : EXTIT1_IRQHandler
* Description : This function handles the EXTIT1 interrupt request
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void EXTIT1_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : EXTIT2_IRQHandler
* Description : This function handles the EXTIT2 interrupt request
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void EXTIT2_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : EXTIT3_IRQHandler
* Description : This function handles the EXTIT3 interrupt request
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void EXTIT3_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : USBWU_IRQHandler
* Description : This function handles the USBWU interrupt request
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void USBWU_IRQHandler(void)
{
}
/*******************************************************************************
* Function Name : PFQBC_IRQHandler
* Description : This function handles the PFQBC interrupt request
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void PFQBC_IRQHandler(void)
{
}
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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Demo/ARM9_STR91X_IAR/Library/source/91x_lib.c
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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_lib.c
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : This file provides all peripherals pointers
: initialization.
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#define EXT
/* Standard include ----------------------------------------------------------*/
#include "91x_map.h"
/* Include of other module interface headers ---------------------------------*/
/* Local includes ------------------------------------------------------------*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Interface functions -------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
#ifdef DEBUG
/*******************************************************************************
* Function Name : debug
* Description : this function initialize peripherals pointers
* Input : no one
* Output : no one
* Return : no one
*******************************************************************************/
void debug(void)
{
/************************* DMA *************************/
#ifdef _DMA
DMA = (DMA_TypeDef *)DMA_BASE;
#endif /* _DMA */
/************************* DMA *************************/
#ifdef _DMA_Channel0
DMA_Channel0= (DMA_Channel_TypeDef *)DMA_Channel0_BASE;
#endif /* _DMA_Channel0 */
#ifdef _DMA_Channel1
DMA_Channel1= (DMA_Channel_TypeDef *)DMA_Channel1_BASE;
#endif /* _DMA_Channel1 */
#ifdef _DMA_Channel2
DMA_Channel2 = (DMA_Channel_TypeDef *)DMA_Channel2_BASE;
#endif /* _DMA_Channel2 */
#ifdef _DMA_Channel3
DMA_Channel3 = (DMA_Channel_TypeDef *)DMA_Channel3_BASE;
#endif /* _DMA_Channel3 */
#ifdef _DMA_Channel4
DMA_Channel4 = (DMA_Channel_TypeDef *)DMA_Channel4_BASE;
#endif /* _DMA_Channel4 */
#ifdef _DMA_Channel5
DMA_Channel5= (DMA_Channel_TypeDef *)DMA_Channel5_BASE;
#endif /* _DMA_Channel5*/
#ifdef _DMA_Channel6
DMA_Channel6 = (DMA_Channel_TypeDef *)DMA_Channel6_BASE;
#endif /* _DMA_Channel6 */
#ifdef _DMA_Channel7
DMA_Channel7 = (DMA_Channel_TypeDef *)DMA_Channel7_BASE;
#endif /* _DMA_Channel7 */
/************************* EMI *************************/
#ifdef _EMI_Bank0
EMI_Bank0= (EMI_Bank_TypeDef *)EMI_Bank0_BASE;
#endif /* _EMI_Bank0 */
#ifdef _EMI_Bank1
EMI_Bank1= (EMI_Bank_TypeDef *)EMI_Bank1_BASE;
#endif /* _EMI_Bank1 */
#ifdef _EMI_Bank2
EMI_Bank2 = (EMI_Bank_TypeDef *)EMI_Bank2_BASE;
#endif /* _EMI_Bank2 */
#ifdef _EMI_Bank3
EMI_Bank3 = (EMI_Bank_TypeDef *)EMI_Bank3_BASE;
#endif /* _EMI_Bank3 */
/************************* AHBAPB *************************/
#ifdef _AHBAPB0
AHBAPB0 = (AHBAPB_TypeDef *)AHBAPB0_BASE;
#endif /* _AHBAPB0 */
#ifdef _AHBAPB1
AHBAPB1 = (AHBAPB_TypeDef *)AHBAPB1_BASE;
#endif /*_AHBAPB1 */
/************************* FMI *************************/
#ifdef _FMI
FMI = (FMI_TypeDef *)FMI_BASE;
#endif /* _FMI */
/************************* VIC *************************/
#ifdef _VIC0
VIC0 = (VIC_TypeDef *)VIC0_BASE;
#endif /* _VIC0 */
#ifdef _VIC1
VIC1 = (VIC_TypeDef *)VIC1_BASE;
#endif /* _VIC1 */
/************************* WIU *************************/
#ifdef _WIU
WIU = (WIU_TypeDef *)WIU_BASE;
#endif /* _WIU */
/************************* TIM *************************/
#ifdef _TIM0
TIM0 = (TIM_TypeDef *)TIM0_BASE;
#endif /* _TIM0 */
#ifdef _TIM1
TIM1 = (TIM_TypeDef *)TIM1_BASE;
#endif /* _TIM1 */
#ifdef _TIM2
TIM2 = (TIM_TypeDef *)TIM2_BASE;
#endif /* _TIM2 */
#ifdef _TIM3
TIM3 = (TIM_TypeDef *)TIM3_BASE;
#endif /* _TIM3 */
/************************* GPIO ************************/
#ifdef _GPIO0
GPIO0 = (GPIO_TypeDef *)GPIO0_BASE;
#endif /* _GPIO0 */
#ifdef _GPIO1
GPIO1 = (GPIO_TypeDef *)GPIO1_BASE;
#endif /* _GPIO1 */
#ifdef _GPIO2
GPIO2 = (GPIO_TypeDef *)GPIO2_BASE;
#endif /* _GPIO2 */
#ifdef _GPIO3
GPIO3 = (GPIO_TypeDef *)GPIO3_BASE;
#endif /* _GPIO3 */
#ifdef _GPIO4
GPIO4 = (GPIO_TypeDef *)GPIO4_BASE;
#endif /* _GPIO4 */
#ifdef _GPIO5
GPIO5 = (GPIO_TypeDef *)GPIO5_BASE;
#endif /* _GPIO5 */
#ifdef _GPIO6
GPIO6 = (GPIO_TypeDef *)GPIO6_BASE;
#endif /* _GPIO6 */
#ifdef _GPIO7
GPIO7 = (GPIO_TypeDef *)GPIO7_BASE;
#endif /* _GPIO7 */
#ifdef _GPIO8
GPIO8 = (GPIO_TypeDef *)GPIO8_BASE;
#endif /* _GPIO8 */
#ifdef _GPIO9
GPIO9 = (GPIO_TypeDef *)GPIO9_BASE;
#endif /* _GPIO9 */
/************************* RTC *************************/
#ifdef _RTC
RTC = (RTC_TypeDef *)RTC_BASE;
#endif /* _RTC */
/************************* PRCCU ***********************/
#ifdef _SCU
SCU = (SCU_TypeDef *)SCU_BASE;
#endif /* _PRCCU */
/************************** MC *************************/
#ifdef _MC
MC = (MC_TypeDef *)MC_BASE;
#endif /* _MC */
/************************* UART ************************/
#ifdef _UART0
UART0 = (UART_TypeDef *)UART0_BASE;
#endif /* _UART0 */
#ifdef _UART1
UART1 = (UART_TypeDef *)UART1_BASE;
#endif /* _UART1 */
#ifdef _UART2
UART2 = (UART_TypeDef *)UART2_BASE;
#endif /* _UART2 */
/************************* SSP *************************/
#ifdef _SSP0
SSP0 = (SSP_TypeDef *)SSP0_BASE;
#endif /* _SSP0 */
#ifdef _SSP1
SSP1 = (SSP_TypeDef *)SSP1_BASE;
#endif /* _SSP1 */
/************************* CAN *************************/
#ifdef _CAN
CAN = (CAN_TypeDef *)CAN_BASE;
#endif /* _CAN */
/************************* ADC *************************/
#ifdef _ADC
ADC = (ADC_TypeDef *)ADC_BASE;
#endif /* _ADC */
/************************* WDG *************************/
#ifdef _WDG
WDG = (WDG_TypeDef *)WDG_BASE;
#endif /* _WDG */
/************************* I2C *************************/
#ifdef _I2C0
I2C0 = (I2C_TypeDef *)I2C0_BASE;
#endif /* _I2C0 */
#ifdef _I2C1
I2C1 = (I2C_TypeDef *)I2C1_BASE;
#endif /* _I2C1 */
/********************** ENET **************************/
#ifdef _ENET
ENET_MAC = (ENET_MAC_TypeDef *)ENET_MAC_BASE;
ENET_DMA = (ENET_DMA_TypeDef *)ENET_DMA_BASE;
#endif /* _ENET */
}
#endif /* DEBUG */
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_scu.c
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : This file provides the SCU library software functions
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "91x_scu.h"
/* Include of other module interface headers ---------------------------------*/
/* Local includes ------------------------------------------------------------*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define SCU_PLLEN 0x80000
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Interface functions -------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : SCU_MCLKSourceConfig
* Description : Configures the MCLK source clock
* Input : MCLK_Source = SCU_MCLK_OSC, SCU_MCLK_PLL or SCU_MCLK_RTC
* Output : None
* Return : ErrorStatus: SUCCESS or ERROR
* Note : this function returns ERROR if trying to select the PLL as
* clock source while the PLL is disabled or not locked.
*******************************************************************************/
ErrorStatus SCU_MCLKSourceConfig(u32 MCLK_Source)
{
u32 CLKCNTR_Value;
CLKCNTR_Value = SCU->CLKCNTR; /*get CLKCNTR register value*/
CLKCNTR_Value &=~0x3; /*clear field MCLKSEL*/
if (MCLK_Source == SCU_MCLK_PLL) /*PLL selected as clock source*/
{
/*check if PLL enabled & locked*/
if (!((SCU->PLLCONF&SCU_PLLEN)&&(SCU->SYSSTATUS&SCU_FLAG_LOCK)))
return ERROR;
}
else CLKCNTR_Value |=MCLK_Source; /*OSC or RTC selected as clock source*/
SCU->CLKCNTR = CLKCNTR_Value; /*Update CLKCNTR register value*/
return SUCCESS;
}
/*******************************************************************************
* Function Name : SCU_PLLFactorsConfig
* Description : Sets the PLL factors
* Input : PLLN, PLLM and PLLP
* Output : None
* Return : ErrorStatus: ERROR or SUCCESS
* Notes : -The PLL factors must respect the PLL specification requirements
* -The function returns ERROR if trying to change PLL
* factors while PLL is selected as Main Clock source (MCLK)
* -This function disables the PLL, to enable the PLL use
* function" SCU_PLLCmd(ENABLE)" after setting the PLL factors
******************************************************************************/
ErrorStatus SCU_PLLFactorsConfig(u8 PLLN, u8 PLLM, u8 PLLP)
{
if (SCU_PLLCmd(DISABLE)==SUCCESS) /*Disable PLL*/
{
SCU->PLLCONF =0; /*clear PLLCONF register*/
SCU->PLLCONF |=(PLLN<<8); /*update PLLN field*/
SCU->PLLCONF |=PLLM; /*update PLLM field*/
SCU->PLLCONF |=PLLP<<16; /*update PLLP field*/
return SUCCESS;
}
return ERROR;
}
/*******************************************************************************
* Function Name : SCU_PLLCmd
* Description : Enable or Disable the PLL
* Input : NewState = ENABLE or DISABLE
* Output : None
* Return : ErrorStatus: SUCCESS or ERROR
* Note : -The function returns ERROR if:
* *trying to disable the PLL while it is selected as the MCLK
* *trying to enable the PLL while it is already enabled and
* locked
*******************************************************************************/
ErrorStatus SCU_PLLCmd(FunctionalState NewState)
{
vu32 i;
if (NewState==ENABLE)
{
if (!((SCU->PLLCONF&SCU_PLLEN)&&(SCU->SYSSTATUS&SCU_FLAG_LOCK)))
{
SCU->SYSSTATUS|=SCU_FLAG_LOCK; /*clear LOCK bit*/
SCU->PLLCONF |=SCU_PLLEN; /*PLL Enable*/
while(!SCU->SYSSTATUS&SCU_FLAG_LOCK); /*Wait PLL to lock*/
return SUCCESS;
}
else return ERROR;
}
else /*NewState = DISABLE*/
{
if(SCU->CLKCNTR&0x3) /*check if PLL not sys CLK*/
{
for(i=10;i>0;i--); /*delay before PLL disabling*/
SCU->PLLCONF &=~SCU_PLLEN; /*PLL Disable*/
return SUCCESS;
}
else return ERROR;
}
}
/*******************************************************************************
* Function Name : SCU_RCLKDivisorConfig
* Description : Sets the RCLK divisor value
* Input : RCLK_Divisor
* Output : None
* Return : None
*******************************************************************************/
void SCU_RCLKDivisorConfig(u32 RCLK_Divisor)
{
SCU->CLKCNTR &=SCU_RCLK_Div1; /*clear RCLKDIV[2:0] field*/
if (RCLK_Divisor!=SCU_RCLK_Div1)
SCU->CLKCNTR |= RCLK_Divisor; /*update field with RCLK divisor*/
}
/*******************************************************************************
* Function Name : SCU_HCLKDivisorConfig
* Description : Sets the HCLK divisor value
* Input : HCLK_Divisor
* Output : None
* Return : None
*******************************************************************************/
void SCU_HCLKDivisorConfig(u32 HCLK_Divisor)
{
SCU->CLKCNTR &=SCU_HCLK_Div1; /*clear AHBDIV[1:0] field*/
if (HCLK_Divisor!=SCU_HCLK_Div1)
SCU->CLKCNTR |= HCLK_Divisor; /*update field with HCLK divisor*/
}
/*******************************************************************************
* Function Name : SCU_PCLKDivisorConfig
* Description : Sets the PCLK divisor value
* Input : PCLK_Divisor
* Output : None
* Return : None
*******************************************************************************/
void SCU_PCLKDivisorConfig(u32 PCLK_Divisor)
{
SCU->CLKCNTR &=SCU_PCLK_Div1; /*clear APBDIV[1:0] field*/
if (PCLK_Divisor!=SCU_PCLK_Div1)
SCU->CLKCNTR |= PCLK_Divisor; /*update field with PCLK Divisor*/
}
/*******************************************************************************
* Function Name : SCU_APBPeriphClockConfig
* Description : Enable the clock for an APB peripheral
* Input : -APBPerip : APB peripherals(__RTC, __ADC ,...)
* -NewState : ENABLE or DISABLE
* Output : None
* Return : None
*******************************************************************************/
void SCU_APBPeriphClockConfig(u32 APBPeriph, FunctionalState NewState)
{
if (NewState==ENABLE) /*Enable clock for APB peripheral*/
SCU->PCGR1 |=APBPeriph;
else
SCU->PCGR1 &=~APBPeriph; /*Disable clock for APB peripheral*/
}
/*******************************************************************************
* Function Name : SCU_AHBPeriphClockConfig
* Description : Enable the clock for an AHB peripheral
* Input : -AHBPerip: AHB peripherals(__USB, __DMA,...)
* -NewState : ENABLE or DISABLE
* Output : None
* Return : None
*******************************************************************************/
void SCU_AHBPeriphClockConfig(u32 AHBPeriph, FunctionalState NewState)
{
if (NewState==ENABLE) /*Enable clock for AHB peripheral*/
SCU->PCGRO |=AHBPeriph;
else
SCU->PCGRO &=~AHBPeriph; /*Disable clock for AHB peripheral*/
}
/*******************************************************************************
* Function Name : SCU_APBPeriphReset
* Description : Assert or deassert Reset on APB peripheral
* Input : -APBPeriph: APB peripherals(__RTC, __ADC,...)
-NewState : ENABLE or DISABLE
* Output : None
* Return : None
*******************************************************************************/
void SCU_APBPeriphReset(u32 APBPeriph, FunctionalState NewState)
{
if (NewState==DISABLE) /*APB peripheral not held in Reset*/
SCU->PRR1 |=APBPeriph;
else
SCU->PRR1 &=~APBPeriph; /*APB peripheral held in Reset*/
}
/*******************************************************************************
* Function Name : SCU_AHBPeriphReset
* Description : Assert or deassert Reset on AHB peripheral
* Input : -AHBPeriph: AHB peripherals(__USB, __DMA,...)
-NewState : ENABLE or DISABLE
* Output : None
* Return : None
*******************************************************************************/
void SCU_AHBPeriphReset(u32 AHBPeriph, FunctionalState NewState)
{
if (NewState==DISABLE)
SCU->PRR0 |=AHBPeriph; /*AHB peripheral not held in Reset*/
else
SCU->PRR0 &=~AHBPeriph; /*AHB peripheral held in Reset*/
}
/*******************************************************************************
* Function Name : SCU_APBPeriphIdleConfig
* Description : Enable or Disable Periph Clock during Idle mode
* Input : -APBPeriph: APB peripherals(__RTC, __ADC,...)
-NewState : ENABLE or DISABLE
* Output : None
* Return : None
*******************************************************************************/
void SCU_APBPeriphIdleConfig(u32 APBPeriph, FunctionalState NewState)
{
if (NewState==ENABLE)
SCU->MGR1 |=APBPeriph; /*APB peripheral clock enabled during Idle mode*/
else
SCU->MGR1 &=~APBPeriph; /*APB peripheral clock disabled during Idle mode*/
}
/*******************************************************************************
* Function Name : SCU_AHBPeriphIdleConfig
* Description : Enable or Disable Periph Clock during Idle mode
* Input : -AHBPeriph: AHB peripherals(__USB, __DMA,...)
-NewState : ENABLE or DISABLE
* Output : None
* Return : None
*******************************************************************************/
void SCU_AHBPeriphIdleConfig(u32 AHBPeriph, FunctionalState NewState)
{
if (NewState==ENABLE)
SCU->MGR0 |=AHBPeriph; /*AHB peripheral clock enabled during Idle mode*/
else
SCU->MGR0 &=~AHBPeriph; /*AHB peripheral clock disabled during Idle mode*/
}
/*******************************************************************************
* Function Name : SCU_APBPeriphDebugConfig
* Description : Enable or Disable Periph Clock during ARM debug state
* Input : -APBPeriph: APB peripherals(__RTC, __ADC,...)
-NewState : ENABLE or DISABLE
* Output : None
* Return : None
*******************************************************************************/
void SCU_APBPeriphDebugConfig(u32 APBPeriph, FunctionalState NewState)
{
if (NewState==ENABLE)
SCU->PECGR1 |=APBPeriph; /*APB peripheral clock enabled during ARM debug state*/
else
SCU->PECGR1 &=~APBPeriph; /*APB peripheral clock disabled during ARM debug state*/
}
/*******************************************************************************
* Function Name : SCU_AHBPeriphDebugConfig
* Description : Enable or Disable Periph Clock during ARM debug state
* Input : -AHBPeriph: AHB peripherals(__USB, __DMA,...)
-NewState : ENABLE or DISABLE
* Output : None
* Return : None
*******************************************************************************/
void SCU_AHBPeriphDebugConfig(u32 AHBPeriph, FunctionalState NewState)
{
if (NewState==ENABLE)
SCU->PECGR0 |=AHBPeriph; /*AHB peripheral clock enabled during ARM debug state*/
else
SCU->PECGR0 &=~AHBPeriph; /*AHB peripheral clock disabled during ARM debug state*/
}
/*******************************************************************************
* Function Name : SCU_BRCLKDivisorConfig
* Description : Sets the BRCLK divisor value
* Input : BRCLK_Divisor
* Output : None
* Return : None
*******************************************************************************/
void SCU_BRCLKDivisorConfig(u32 BRCLK_Divisor)
{
SCU->CLKCNTR &=SCU_BRCLK_Div1; /*Clear BRSEL bit*/
if (BRCLK_Divisor!=SCU_BRCLK_Div1)
SCU->CLKCNTR |= SCU_BRCLK_Div2; /*set bit BRSEL*/
}
/*******************************************************************************
* Function Name : SCU_TIMCLKSourceConfig
* Description : Sets the TIMx clock source
* Input : - TIMx : SCU_TIM01 or SCU_TIM23
* - TIMCLK_Source = SCU_TIMCLK_EXT or SCU_TIMCLK_INT
* Output : None
* Return : None
*******************************************************************************/
void SCU_TIMCLKSourceConfig(u8 TIMx, u32 TIMCLK_Source)
{
if (TIMx== SCU_TIM01) /*TIM01 clock source configuration*/
{
SCU->CLKCNTR &=0xFFFFDFFF;
if (TIMCLK_Source == SCU_TIMCLK_EXT)
SCU->CLKCNTR |=0x2000;
}
else
{
SCU->CLKCNTR &=0xFFFFBFFF; /*TIM23 clock source configuration*/
if (TIMCLK_Source == SCU_TIMCLK_EXT)
SCU->CLKCNTR |=0x4000;
}
}
/*******************************************************************************
* Function Name : SCU_TIMPresConfig
* Description : Sets the TIMx Prescaler Value
* Input : - TIMx : SCU_TIM01 or SCU_TIM23
* - Prescaler (16 bit value)
* Output : None
* Return : None
*******************************************************************************/
void SCU_TIMPresConfig(u8 TIMx, u16 Prescaler)
{
if (TIMx==SCU_TIM01) /*TIM01 Prescaler configuration*/
SCU->SCR1 = Prescaler&0xFFFF;
else
SCU->SCR2 = Prescaler&0xFFFF; /*TIM23 Prescaler configuration*/
}
/*******************************************************************************
* Function Name : SCU_USBCLKConfig
* Description : Configures the clock source for the 48MHz USBCLK
* Input : USBCLK_Source: SCU_USBCLK_MCLK,SCU_USBCLK_MCLK2 or SCU_USBCLK_EXT
* Output : None
* Return : None
*******************************************************************************/
void SCU_USBCLKConfig(u32 USBCLK_Source)
{
SCU->CLKCNTR &=SCU_USBCLK_MCLK; /*clear USBSEL[1:0] field*/
if (USBCLK_Source!=SCU_USBCLK_MCLK)
SCU->CLKCNTR |= USBCLK_Source; /*update field with USBCLK_Source*/
}
/*******************************************************************************
* Function Name : SCU_PHYCLKConfig
* Description : Enable or Disable PHY clock output
* Input : NewState : ENABLE or DISABLE
* Output : None
* Return : None
*******************************************************************************/
void SCU_PHYCLKConfig(FunctionalState NewState)
{
if (NewState==ENABLE)
SCU->CLKCNTR |= 0x1000; /*enable MIIPHY clock*/
else
SCU->CLKCNTR &=~0x1000; /*disable MIIPHY clock*/
}
/*******************************************************************************
* Function Name : SCU_FMICLKDivisorConfig
* Description : Set the FMI clock divisor
* Input : FMICLK_Divisor: SCU_FMICLK_Div1 or SCU_FMICLK_DIV2
* Output : None
* Return : None
*******************************************************************************/
void SCU_FMICLKDivisorConfig(u32 FMICLK_Divisor)
{
SCU->CLKCNTR &=SCU_FMICLK_Div1; /*FMICLK = RCLK*/
if (FMICLK_Divisor!=SCU_FMICLK_Div1)
SCU->CLKCNTR |=SCU_FMICLK_Div2; /*FMICLK = RCLK/2 */
}
/*******************************************************************************
* Function Name : SCU_EMIBCLKDivisorConfig
* Description : Set the EMI Bus clock divisor: EMIBCLK = HCLK or HCLK/2
* Input : SCU_EMICLK: SCU_EMIBCLK_Div1 , SCU_EMIBCLK_Div2
* Output : None
* Return : None
*******************************************************************************/
void SCU_EMIBCLKDivisorConfig(u32 SCU_EMIBCLK)
{
SCU->CLKCNTR &=SCU_EMIBCLK_Div1; /*EMIBCLK = HCLK */
if (SCU_EMIBCLK!=SCU_EMIBCLK_Div1)
SCU->CLKCNTR |= SCU_EMIBCLK_Div2; /*EMIBCLK = HCLK/2 */
}
/*******************************************************************************
* Function Name : SCU_EMIModeConfig
* Description : Configure the EMI as Multiplexed or Demultiplexed
* Input : SCU_EMIMODE : SCU_EMI_MUX or SCU_EMI_DEMUX
* Output : None
* Return : None
*******************************************************************************/
void SCU_EMIModeConfig(u32 SCU_EMIMODE)
{
SCU->SCR0 &=SCU_EMI_MUX; /*EMI mode = Multiplexed*/
if (SCU_EMIMODE!=SCU_EMI_MUX)
SCU->SCR0 |= SCU_EMI_DEMUX; /*EMI mode = Demultiplexed*/
}
/*******************************************************************************
* Function Name : SCU_EMIALEConfig
* Description : Configure the ALE signal (length & polarity)
* Input : -SCU_EMIALE_LEN : SCU_EMIALE_LEN1 or SCU_EMIALE_LEN2
* -SCU_EMIALE_POL : SCU_EMIALE_POLLow or SCU_EMI_POLHigh
* Output : None
* Return : None
*******************************************************************************/
void SCU_EMIALEConfig(u32 SCU_EMIALE_LEN, u32 SCU_EMIALE_POL)
{
/*Configure EMI ALE Length*/
SCU->SCR0 &=SCU_EMIALE_LEN1;
if (SCU_EMIALE_LEN!=SCU_EMIALE_LEN1)
SCU->SCR0 |= SCU_EMIALE_LEN2;
/*Configure EMI ALE POL*/
SCU->SCR0 &=SCU_EMIALE_POLLow;
if (SCU_EMIALE_POL!=SCU_EMIALE_POLLow)
SCU->SCR0 |= SCU_EMIALE_POLHigh;
}
/*******************************************************************************
* Function Name : SCU_ITConfig
* Description : ENBALE or DISABLE an SCU interrupt
* Input : -SCU_IT: interrupt mask
* -NewState: ENABLE or DISABLE
* Output : None
* Return : None
*******************************************************************************/
void SCU_ITConfig(u32 SCU_IT, FunctionalState NewState)
{
if (NewState==ENABLE)
SCU->ITCMSK&=~SCU_IT; /*IT enable */
else
SCU->ITCMSK|=SCU_IT; /*IT disable( mask)*/
}
/*******************************************************************************
* Function Name : SCU_GetFlagStatus
* Description : Returns flag status
* Input : SCU_Flag
* Output : NONE
* Return : SET or RESET
*******************************************************************************/
FlagStatus SCU_GetFlagStatus(u32 SCU_Flag)
{
if (SCU->SYSSTATUS&SCU_Flag)
return SET;
else return RESET;
}
/*******************************************************************************
* Function Name : SCU_ClearFlag
* Description : Clears a SYSTATUS Flag
* Input : SCU_Flag
* Output : None
* Return : None
*******************************************************************************/
void SCU_ClearFlag(u32 SCU_Flag)
{
SCU->SYSSTATUS = SCU_Flag;
}
/*******************************************************************************
* Function Name : SCU_GetPLLfreqValue
* Description : Gets the current PLL frequency
* Input : None
* Output : None
* Return : PLL frequency (KHz)
*******************************************************************************/
u32 SCU_GetPLLFreqValue(void)
{
u8 PLL_M;
u8 PLL_N;
u8 PLL_P;
PLL_M = SCU->PLLCONF&0xFF;
PLL_N = (SCU->PLLCONF&0xFF00)>>8;
PLL_P = (SCU->PLLCONF&0x70000)>>16;
if ((PLL_M>0)&&(PLL_N>0))
return (u32)(((_Main_Crystal*2)*PLL_N)/(PLL_M<<PLL_P));
else return 0;
}
/*******************************************************************************
* Function Name : SCU_GetMCLKFreqValue
* Description : Gets the current MCLK frequency
* Input : None
* Output : None
* Return : MCLK frequency (KHz)
*******************************************************************************/
u32 SCU_GetMCLKFreqValue(void)
{
if ((SCU->CLKCNTR&0x3) == 0x2) return (u32)(_Main_Crystal);
if ((SCU->CLKCNTR&0x3) == 0x1) return (u32)(32);
else return (SCU_GetPLLFreqValue());
}
/*******************************************************************************
* Function Name : SCU_GetRCLKFreqValue
* Description : Gets the current RCLK frequency
* Input : None
* Output : None
* Return : RCLK frequency (KHz)
*******************************************************************************/
u32 SCU_GetRCLKFreqValue(void)
{
u8 RCLK_Div;
RCLK_Div = (SCU->CLKCNTR&0x1C)>>2;
if (RCLK_Div==0x5) RCLK_Div=10;
return (u32)(SCU_GetMCLKFreqValue() >>RCLK_Div);
}
/*******************************************************************************
* Function Name : SCU_GetHCLKFreqValue
* Description : Gets the current PCLK frequency
* Input : None
* Output : None
* Return : HCLK frequency (KHz)
*******************************************************************************/
u32 SCU_GetHCLKFreqValue(void)
{
u8 HCLK_Div;
HCLK_Div = (SCU->CLKCNTR&0x60)>>5;
return (u32)(SCU_GetRCLKFreqValue() >>HCLK_Div);
}
/*******************************************************************************
* Function Name : SCU_GetPCLKFreqValue
* Description : Gets the current HCLK frequency
* Input : None
* Output : None
* Return : PCLK frequency (KHz)
*******************************************************************************/
u32 SCU_GetPCLKFreqValue(void)
{
u8 PCLK_Div;
PCLK_Div = (SCU->CLKCNTR&0x180)>>7;
return (u32)(SCU_GetRCLKFreqValue() >>PCLK_Div);
}
/*******************************************************************************
* Function Name : SCU_WakeUpLineConfig
* Description : Configures an External interrupt as WakeUp line
* Input : EXTint : 0 -> 31
* Output : None
* Return : None
*******************************************************************************/
void SCU_WakeUpLineConfig(u8 EXTint)
{
if (EXTint < 8)
{
SCU->WKUPSEL&=~0x7;
SCU->WKUPSEL|=EXTint;
}
else if (EXTint<16)
{
SCU->WKUPSEL&=~0x38;
SCU->WKUPSEL|=(EXTint-8)<<3;
}
else if (EXTint<24)
{
SCU->WKUPSEL&=~0x1C0;
SCU->WKUPSEL|=(EXTint-16)<<6;
}
else
{
SCU->WKUPSEL&=~0xE00;
SCU->WKUPSEL|=(EXTint-24)<<9;
}
}
/*******************************************************************************
* Function Name : SCU_SpecIntRunModeConfig
* Description : Enables or Disables the Special Run mode
* Input : newstate = ENABLE or DISABLE
* Output : None
* Return : None
*******************************************************************************/
void SCU_SpecIntRunModeConfig(FunctionalState NewState)
{
if (NewState == ENABLE)
SCU->PWRMNG |=0x8;
else
SCU->PWRMNG &=~0x8;
}
/*******************************************************************************
* Function Name : SCU_EnterIdleMode
* Description : Enters in Idle mode
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void SCU_EnterIdleMode(void)
{
SCU->PWRMNG |=0x1;
}
/*******************************************************************************
* Function Name : SCU_EnterSleepMode
* Description : Enters in Sleep mode
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void SCU_EnterSleepMode(void)
{
SCU->PWRMNG |=0x2;
}
/*******************************************************************************
* Function Name : SCU_UARTIrDAConfig
* Description : Enable or Disable the Irda mode for UARTx
* Input : - UARTx :x=0,1 or 2
* - UART_IrDA_Mode : SCU_UARTMode_IrDA or SCU_UARTMode_UART
* Output : None
* Return : None
*******************************************************************************/
void SCU_UARTIrDASelect(UART_TypeDef * UARTx, u8 UART_IrDA_Mode)
{
if (UART_IrDA_Mode == SCU_UARTMode_IrDA)
{
if (UARTx== UART0) SCU->SCR0 |=0x400;
else if (UARTx==UART1) SCU->SCR0 |=0x800;
else SCU->SCR0 |=0x1000;
}
else
{
if (UARTx== UART0) SCU->SCR0 &=~0x400;
else if (UARTx==UART1) SCU->SCR0 &=~0x800;
else SCU->SCR0 &=~0x1000;
}
}
/*******************************************************************************
* Function Name : SCU_PFQBCCmd
* Description : Enable or Disable PFQBC
* Input : NewState : ENABLE or DISABLE
* Output : None
* Return : None
*******************************************************************************/
void SCU_PFQBCCmd(FunctionalState NewState)
{
if (NewState==ENABLE)
SCU->SCR0 |=0x1;
else SCU->SCR0 &=~0x1;
}
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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Demo/ARM9_STR91X_IAR/Library/source/91x_uart.c
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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_uart.c
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : This file provides all the UART software functions.
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "91x_uart.h"
#include "91x_scu.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* UART IrDA Mask */
#define UART_IrDA_Disable_Mask 0xFFFD /* IrDA Disable Mask */
#define UART_IrDA_Enable_Mask 0x0002 /* IrDA Enable Mask */
#define IrDA_LowPower_Enable_Mask 0x0004 /*IrDA lower power mode enable*/
#define IrDA_LowPower_Disable_Mask 0xFFFB /*IrDA lower power mode enable*/
/* UART Mask */
#define UART_Enable_Mask 0x0001 /* UART Enable Mask */
#define UART_Disable_Mask 0xFFFE /* UART Disable Mask */
/* UART LoopBack */
#define UART_LoopBack_Disable_Mask 0xFF7F /* LoopBack Disable Mask */
#define UART_LoopBack_Enable_Mask 0x0080 /* LoopBack Enable Mask */
#define UART_WordLength_Mask 0xFF9F /* UART Word Length Mask */
#define UART_Parity_Mask 0xFF79 /* UART Parity Mask */
#define UART_HardwareFlowControl_Mask 0x3FFF /* UART Hardware Flow Control Mask */
#define UART_TxRxFIFOLevel_Mask 0xFFC0 /* UART Tx Rx FIFO Level Mask */
#define UART_BreakChar_Mask 0x0001 /* UART Break Character send Mask*/
#define UART_FLAG_Mask 0x1F /* UART Flag Mask */
#define UART_Mode_Mask 0xFCFF /* UART Mode Mask */
#define UART_RTS_LowLevel_Mask 0x0800 /* RTS signal is low */
#define UART_RTS_HighLevel_Mask 0xF7FF /* RTS signal is High */
#define UART_DTR_LowLevel_Mask 0x0400 /* DTR signal is low */
#define UART_DTR_HighLevel_Mask 0xFBFF /* DTR signal is High */
#define UART_ClearFlag_Mask 0xAA /* Clear Flag Mask */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : UART_DeInit
* Description : Deinitializes the UARTx peripheral registers
* to their default reset values.
* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral.
* Output : None
* Return : None
*******************************************************************************/
void UART_DeInit(UART_TypeDef* UARTx)
{
/* Reset the UARTx registers values */
if(UARTx == UART0)
{
SCU_APBPeriphReset(__UART0,ENABLE);
SCU_APBPeriphReset(__UART0,DISABLE);
}
else if(UARTx == UART1)
{
SCU_APBPeriphReset(__UART1,ENABLE);
SCU_APBPeriphReset(__UART1,DISABLE);
}
else if(UARTx == UART2)
{
SCU_APBPeriphReset(__UART2,ENABLE);
SCU_APBPeriphReset(__UART2,DISABLE);
}
}
/*******************************************************************************
* Function Name : UART_Init
* Description : Initializes the UARTx peripheral according to the specified
* parameters in the UART_InitStruct .
* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral.
* - UART_InitStruct: pointer to a UART_InitTypeDef structure
* that contains the configuration information for the
* specified UART peripheral.
* Output : None
* Return : None
*******************************************************************************/
void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct)
{
u64 UART_MainClock = 0;
u32 IntegerDivider = 0;
u32 FractionalDivider = 0;
/* Clear the LCR[6:5] bits */
UARTx->LCR &= UART_WordLength_Mask;
/* Set the LCR[6:5] bits according to UART_WordLength value */
UARTx->LCR |= UART_InitStruct->UART_WordLength;
/* Choose Stop Bits */
if(UART_InitStruct->UART_StopBits == UART_StopBits_2)
{
/* 2 Stop Bit */
UARTx->LCR |= UART_StopBits_2;
}
else
{
/* One Stop Bits */
UARTx->LCR &= UART_StopBits_1;
}
/* Configure the Parity */
/* Clear the LCR[7]and LCR[2:1] bits */
UARTx->LCR &= UART_Parity_Mask;
/* Set the LCR[7]and LCR[2:1] bits according to UART_Parity value */
UARTx->LCR |= UART_InitStruct->UART_Parity;
/* Configure the BaudRate */
UART_MainClock = (SCU_GetMCLKFreqValue())*1000;
if((SCU->CLKCNTR & 0x200) != 0x200)
{
UART_MainClock = UART_MainClock/2;
}
/* Determine the integer part */
IntegerDivider = ((100) * (UART_MainClock) / (16 * (UART_InitStruct->UART_BaudRate)));
UARTx->IBRD = IntegerDivider / 100;
/* Determine the fractional part */
FractionalDivider = IntegerDivider - (100 * (UARTx->IBRD));
UARTx->FBRD = ((((FractionalDivider * 64) + 50) / 100));
/* Choose the Hardware Flow Control */
/* Clear the CR[15:14] bits */
UARTx->CR &= UART_HardwareFlowControl_Mask;
/* Set the CR[15:14] bits according to UART_HardwareFlowControl value */
UARTx->CR |= UART_InitStruct->UART_HardwareFlowControl;
/* Configure the UART mode */
/* Clear the CR[9:8] bits */
UARTx->CR &= UART_Mode_Mask;
/* Set the CR[9:8] bits according to UART_Mode value */
UARTx->CR |= UART_InitStruct->UART_Mode;
/* Enable or disable the FIFOs */
/* Set the FIFOs Levels */
if(UART_InitStruct->UART_FIFO == UART_FIFO_Enable)
{
/* Enable the FIFOs */
UARTx->LCR |= UART_FIFO_Enable;
/* Clear TXIFLSEL and RXIFLSEL bits */
UARTx->IFLS &= UART_TxRxFIFOLevel_Mask;
/* Set RXIFLSEL bits according to UART_RxFIFOLevel value */
UARTx->IFLS |= (UART_InitStruct->UART_RxFIFOLevel << 3);
/* Set TXIFLSEL bits according to UART_TxFIFOLevel value */
UARTx->IFLS |= UART_InitStruct->UART_TxFIFOLevel;
}
else
{
/* Disable the FIFOs */
UARTx->LCR &= UART_FIFO_Disable;
}
}
/*******************************************************************************
* Function Name : UART_StructInit
* Description : Fills each UART_InitStruct member with its reset value.
* Input : UART_InitStruct: pointer to a UART_InitTypeDef structure which
* will be initialized.
* Output : None
* Return : None
*******************************************************************************/
void UART_StructInit(UART_InitTypeDef* UART_InitStruct)
{
/* Reset the UART_InitStruct members */
UART_InitStruct->UART_WordLength = UART_WordLength_8D;
UART_InitStruct->UART_StopBits = UART_StopBits_1;
UART_InitStruct->UART_Parity = UART_Parity_Odd ;
UART_InitStruct->UART_BaudRate = 9600;
UART_InitStruct->UART_HardwareFlowControl = UART_HardwareFlowControl_None;
UART_InitStruct->UART_Mode = UART_Mode_Tx_Rx;
UART_InitStruct->UART_FIFO = UART_FIFO_Enable;
UART_InitStruct->UART_TxFIFOLevel = UART_FIFOLevel_1_2;
UART_InitStruct->UART_RxFIFOLevel = UART_FIFOLevel_1_2;
}
/*******************************************************************************
* Function Name : UART_Cmd
* Description : Enables or disables the specified UART peripheral.
* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral
* - NewState: new state of the UARTx peripheral.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState)
{
if (NewState == ENABLE)
{
/* Enable the selected UART by setting the UARTEN bit in the CR register */
UARTx->CR |= UART_Enable_Mask;
}
else
{
/* Disable the selected UART by clearing the UARTEN bit in the CR register */
UARTx->CR &= UART_Disable_Mask;
}
}
/*******************************************************************************
* Function Name : UART_ITConfig
* Description : Enables or disables the specified UART interrupts.
* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral
* - UART_IT: specifies the UART interrupts sources to be
* enabled or disabled. This parameter can be any combination
* of the following values:
* - UART_IT_OverrunError: Overrun Error interrupt
* - UART_IT_BreakError: Break Error interrupt
* - UART_IT_ParityError: Parity Error interrupt
* - UART_IT_FrameError: Frame Error interrupt
* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt
* - UART_IT_Transmit: Transmit interrupt
* - UART_IT_Receive: Receive interrupt
* - UART_IT_DSR: DSR interrupt
* - UART_IT_DCD: DCD interrupt
* - UART_IT_CTS: CTS interrupt
* - UART_IT_RI: RI interrupt
* - NewState: new state of the UARTx peripheral.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void UART_ITConfig(UART_TypeDef* UARTx, u16 UART_IT, FunctionalState NewState)
{
if(NewState == ENABLE)
{
/* Enables the selected interrupts */
UARTx->IMSC |= UART_IT;
}
else
{
/* Disables the selected interrupts */
UARTx->IMSC &= ~UART_IT;
}
}
/*******************************************************************************
* Function Name : UART_DMAConfig
* Description : Configures the UARTx’s DMA interface.
* Input : - UARTx: where x can be 1 or 2 to select the UART peripheral
* - UART_DMAOnError: specifies the DMA on error request.
* This parameter can be:
* - UART_DMAOnError_Enable: DMA receive request enabled
* when the UART error interrupt is asserted.
* - UART_DMAOnError_Disable: DMA receive request disabled
* when the UART error interrupt is asserted.
* Output : None
* Return : None
*******************************************************************************/
void UART_DMAConfig(UART_TypeDef* UARTx, u16 UART_DMAOnError)
{
if(UART_DMAOnError == UART_DMAOnError_Enable)
{
UARTx->DMACR &= UART_DMAOnError_Enable;
}
else
{
UARTx->DMACR |= UART_DMAOnError_Disable;
}
}
/*******************************************************************************
* Function Name : UART_DMACmd
* Description : Enables or disables the UARTx’s DMA interface.
* Input : - UARTx: where x can be 1 or 2 to select the UART peripheral
* - UART_DMAReq: enables or disables the request of DMA from UART.
* This parameter can be:
* - UART_DMAReq_Tx: Transmit DMA Enable
* - UART_DMAReq_Rx: Receive DMA Enable
* - NewState: new state of the UARTx peripheral.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void UART_DMACmd(UART_TypeDef* UARTx, u8 UART_DMAReq, FunctionalState NewState)
{
if(UART_DMAReq == UART_DMAReq_Tx)
{
if(NewState == ENABLE)
{
UARTx->DMACR |= UART_DMAReq_Tx;
}
else
{
UARTx->DMACR &= ~UART_DMAReq_Tx;
}
}
if(UART_DMAReq == UART_DMAReq_Rx)
{
if(NewState == ENABLE)
{
UARTx->DMACR |= UART_DMAReq_Rx;
}
else
{
UARTx->DMACR &= ~UART_DMAReq_Rx;
}
}
}
/*******************************************************************************
* Function Name : UART_LoopBackConfig
* Description : Enables or disables the LoopBack mode.
* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral
* - NewState: new state of the UARTx peripheral.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void UART_LoopBackConfig(UART_TypeDef* UARTx, FunctionalState NewState)
{
if (NewState == ENABLE)
{
/* Enable the LoopBack mode of the specified UART */
UARTx->CR |= UART_LoopBack_Enable_Mask;
}
else
{
/* Disable the LoopBack mode of the specified UART */
UARTx->CR &= UART_LoopBack_Disable_Mask;
}
}
/*******************************************************************************
* Function Name : UART_GetFlagStatus
* Description : Checks whether the specified UART flag is set or not.
* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral
* - UART_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* - UART_FLAG_OverrunError: Overrun error flag
* - UART_FLAG_Break: break error flag
* - UART_FLAG_ParityError: parity error flag
* - UART_FLAG_FrameError: frame error flag
* - UART_FLAG_RI: RI flag
* - UART_FLAG_TxFIFOEmpty: Transmit FIFO Empty flag
* - UART_FLAG_RxFIFOFull: Receive FIFO Full flag
* - UART_FLAG_TxFIFOFull: Transmit FIFO Full flag
* - UART_FLAG_RxFIFOEmpty: Receive FIFO Empty flag
* - UART_FLAG_Busy: UART Busy flag
* - UART_FLAG_CTS: CTS flag
* - UART_FLAG_DCD: DCD flag
* - UART_FLAG_DSR: DSR flag
* - UART_RawIT_OverrunError: Overrun Error interrupt flag
* - UART_RawIT_BreakError: Break Error interrupt flag
* - UART_RawIT_ParityError: Parity Error interrupt flag
* - UART_RawIT_FrameError: Frame Error interrupt flag
* - UART_RawIT_ReceiveTimeOut: ReceiveTimeOut interrupt flag
* - UART_RawIT_Transmit: Transmit interrupt flag
* - UART_RawIT_Receive: Receive interrupt flag
* - UART_RawIT_DSR: DSR interrupt flag
* - UART_RawIT_DCD: DCD interrupt flag
* - UART_RawIT_CTS: CTS interrupt flag
* - UART_RawIT_RI: RI interrupt flag
* Output : None
* Return : The new state of UART_FLAG (SET or RESET).
*******************************************************************************/
FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, u16 UART_FLAG)
{
u32 UARTReg = 0, FlagPos = 0;
u32 StatusReg = 0;
/* Get the UART register index */
UARTReg = UART_FLAG >> 5;
/* Get the flag position */
FlagPos = UART_FLAG & UART_FLAG_Mask;
if(UARTReg == 1) /* The flag to check is in RSR register */
{
StatusReg = UARTx->RSECR;
}
else if (UARTReg == 2) /* The flag to check is in FR register */
{
StatusReg = UARTx->FR;
}
else if(UARTReg == 3) /* The flag to check is in RIS register */
{
StatusReg = UARTx->RIS;
}
if((StatusReg & (1 << FlagPos))!= RESET)
{
return SET;
}
else
{
return RESET;
}
}
/*******************************************************************************
* Function Name : UART_ClearFlag
* Description : Clears the UARTx’s flags(Frame, Parity, Break, Overrun error).
* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral.
* Output : None
* Return : None
*******************************************************************************/
void UART_ClearFlag(UART_TypeDef* UARTx)
{
/* Clear the flag */
UARTx->RSECR = UART_ClearFlag_Mask;
}
/*******************************************************************************
* Function Name : UART_GetITStatus
* Description : Checks whether the specified UART interrupt has occured or not.
* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral.
* - UART_IT: specifies the interrupt pending bit to be checked.
* This parameter can be one of the following values:
* - UART_IT_OverrunError: Overrun Error interrupt
* - UART_IT_BreakError: Break Error interrupt
* - UART_IT_ParityError: Parity Error interrupt
* - UART_IT_FrameError: Frame Error interrupt
* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt
* - UART_IT_Transmit: Transmit interrupt
* - UART_IT_Receive: Receive interrupt
* - UART_IT_DSR: DSR interrupt
* - UART_IT_DCD: DCD interrupt
* - UART_IT_CTS: CTS interrupt
* - UART_IT_RI: RI interrupt
* Output : None
* Return : The new state of UART_IT (SET or RESET).
*******************************************************************************/
ITStatus UART_GetITStatus(UART_TypeDef* UARTx, u16 UART_IT)
{
if((UARTx->MIS & UART_IT) != RESET)
{
return SET;
}
else
{
return RESET;
}
}
/*******************************************************************************
* Function Name : UART_ClearITPendingBit
* Description : Clears the UARTx’s interrupt pending bits.
* Input : - UARTx: where x can be 0,1or 2 to select the UART peripheral.
* - UART_IT: specifies the interrupt pending bit to clear.
* More than one interrupt can be cleared using the “|” operator.
* This parameter can be:
* - UART_IT_OverrunError: Overrun Error interrupt
* - UART_IT_BreakError: Break Error interrupt
* - UART_IT_ParityError: Parity Error interrupt
* - UART_IT_FrameError: Frame Error interrupt
* - UART_IT_ReceiveTimeOut: Receive Time Out interrupt
* - UART_IT_Transmit: Transmit interrupt
* - UART_IT_Receive: Receive interrupt
* - UART_IT_DSR: DSR interrupt
* - UART_IT_DCD: DCD interrupt
* - UART_IT_CTS: CTS interrupt
* - UART_IT_RI: RI interrupt
* Output : None
* Return : None
*******************************************************************************/
void UART_ClearITPendingBit(UART_TypeDef* UARTx, u16 UART_IT)
{
/* Clear the specified interrupt */
UARTx->ICR &= UART_IT;
}
/*******************************************************************************
* Function Name : UART_IrDALowPowerConfig
* Description : Sets the IrDA low power mode
* Input : - IrDAx: where x can be 0,1 or 2 to select the UART/IrDA peripheral.
* - NewState: new state of the UARTIrDA peripheral.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void UART_IrDALowPowerConfig(u8 IrDAx, FunctionalState NewState)
{
UART_TypeDef* UARTx;
switch(IrDAx)
{
case IrDA0: UARTx = UART0;
break;
case IrDA1: UARTx = UART1;
break;
case IrDA2: UARTx = UART2;
break;
}
if (NewState == ENABLE)
{
UARTx->CR |= IrDA_LowPower_Enable_Mask;
}
else
{
UARTx->CR &= IrDA_LowPower_Disable_Mask;
}
}
/*******************************************************************************
* Function Name : UART_IrDASetCounter
* Description : Sets the IrDA counter divisor value.
* Input : - UARTx: where x can be 0,1 or 2 to select the UART/IrDA peripheral.
* - IrDA_Counter: IrDA counter divisor new value n low power mode(Hz).
* Output : None
* Return : None
*******************************************************************************/
void UART_IrDASetCounter(u8 IrDAx, u32 IrDA_Counter)
{
UART_TypeDef* UARTx;
u32 APBClock;
switch(IrDAx)
{
case IrDA0: UARTx = UART0;
break;
case IrDA1: UARTx = UART1;
break;
case IrDA2: UARTx = UART2;
break;
}
/* Get the APB frequency */
APBClock = (SCU_GetPCLKFreqValue())*1000;
/* Determine the Counter Divisor part */
UARTx->ILPR = (((APBClock*10) / ( IrDA_Counter)) + 5 )/10;
}
/*******************************************************************************
* Function Name : UART_IrDACmd
* Description : Enables or disables the UARTx’s IrDA interface.
* Input : - IrDAx: where x can be 0,1 or 2 to select the UART/IrDA peripheral
* - NewState: new state of the UARTx peripheral.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void UART_IrDACmd(u8 IrDAx, FunctionalState NewState)
{
UART_TypeDef* UARTx;
switch(IrDAx)
{
case IrDA0: UARTx = UART0;
break;
case IrDA1: UARTx = UART1;
break;
case IrDA2: UARTx = UART2;
break;
}
if(NewState == ENABLE)
{
/* Enable the IrDA mode of the specified UART */
UARTx->CR |= UART_IrDA_Enable_Mask;
}
else
{
/* Disable the IrDA mode of the specified UART */
UARTx->CR &= UART_IrDA_Disable_Mask;
}
}
/*******************************************************************************
* Function Name : UART_SendData
* Description : Transmits signle Byte of data through the UARTx peripheral.
* Input : - UARTx: where x can be 0,1 or 2 to select the UART peripheral.
* - Data: the byte to transmit
* Output : None
* Return : None
*******************************************************************************/
void UART_SendData(UART_TypeDef* UARTx, u8 Data)
{
/* Transmit one byte */
UARTx->DR = Data;
}
/*******************************************************************************
* Function Name : UART_ReceiveData
* Description : Returns the most recent received Byte by the UARTx peripheral.
* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral.
* Output : None
* Return : The received data
*******************************************************************************/
u8 UART_ReceiveData(UART_TypeDef* UARTx)
{
/* Receive one byte */
return ((u8)UARTx->DR);
}
/*******************************************************************************
* Function Name : UART_SendBreak
* Description : Transmits break characters.
* Input : UARTx: where x can be 0,1 or 2 to select the UART peripheral.
* Output : None
* Return : None
*******************************************************************************/
void UART_SendBreak(UART_TypeDef* UARTx)
{
/* Send break characters */
UARTx->LCR |= UART_BreakChar_Mask;
}
/*******************************************************************************
* Function Name : UART_RTSConfig
* Description : Sets or Resets the RTS signal
* Input : - LevelState: new state of the RTS signal for UART0 only.
* This parameter can be: LowLevel or HighLevel
* Output : None
* Return : None
*******************************************************************************/
void UART_RTSConfig(UART_LevelTypeDef LevelState)
{
if(LevelState == LowLevel)
{
UART0->CR |= UART_RTS_LowLevel_Mask;
}
else
{
UART0->CR &= UART_RTS_HighLevel_Mask;
}
}
/*******************************************************************************
* Function Name : UART_DTRConfig
* Description : Sets or Resets the DTR signal for UART0 only
* Input : - LevelState: new state of the DTR signal.
* This parameter can be: LowLevel or HighLevel
* Output : None
* Return : None
*******************************************************************************/
void UART_DTRConfig(UART_LevelTypeDef LevelState)
{
if(LevelState == LowLevel)
{
UART0->CR |= UART_DTR_LowLevel_Mask;
}
else
{
UART0->CR &= UART_DTR_HighLevel_Mask;
}
}
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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Demo/ARM9_STR91X_IAR/Library/source/91x_vic.c
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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_vic.c
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : This file provides all the VIC software functions.
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Standard include ----------------------------------------------------------*/
#include "91x_vic.h"
/* Include of other module interface headers ---------------------------------*/
/* Local includes ------------------------------------------------------------*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define VIC_REGISTER_NUMBER 16
#define VIC_PROTECTION_ENABLE_MASK 0x1
#define VIC_PROTECTION_DISABLE_MASK 0xFFFFFFFE
#define VIC_VECTOR_ENABLE_MASK 0x20
#define VIC_IT_SOURCE_MASK 0xFFFFFFE0
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static void VIC_ITModeConfig(u16 VIC_Source, VIC_ITLineMode VIC_LineMode);
static void VIC_ISRVectAddConfig(u16 VIC_Source, u16 VIC_Priority, \
void (*VIC_VectAddress)(void));
static void VIC_VectEnableConfig(u16 VIC_Source, u16 VIC_Priority);
static void VIC_ITSourceConfig(u16 VIC_Source, u16 VIC_Priority);
/* Interface functions -------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name : VIC_DeInit
* Description : Deinitialize the VIC module registers to their default reset
* values.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void VIC_DeInit(void)
{
SCU_AHBPeriphReset(__VIC, ENABLE); /* VIC peripheral is under Reset */
SCU_AHBPeriphReset(__VIC, DISABLE); /* VIC peripheral Reset off */
}
/*******************************************************************************
* Function Name : VIC_GetIRQStatus
* Description : Get the status of interrupts after IRQ masking.
* Input : VIC_Source: specifies the number of the source line.
* This parameter can be one of the following values:
* - WDG_ITLine : VIC source 0
* - SW_ITLine : VIC source 1
* - ARMRX_ITLine : VIC source 2
* - ARMTX_ITLine : VIC source 3
* - TIM0_ITLine : VIC source 4
* - TIM1_ITLine : VIC source 5
* - TIM2_ITLine : VIC source 6
* - TIM3_ITLine : VIC source 7
* - USBHP_ITLine : VIC source 8
* - USBLP_ITLine : VIC source 9
* - SCU_ITLine : VIC source 10
* - ENET_ITLine : VIC source 11
* - DMA_ITLine : VIC source 12
* - CAN_ITLine : VIC source 13
* - MC_ITLine : VIC source 14
* - ADC_ITLine : VIC source 15
* - UART0_ITLine : VIC source 16
* - UART1_ITLine : VIC source 17
* - UART2_ITLine : VIC source 18
* - I2C0_ITLine : VIC source 19
* - I2C1_ITLine : VIC source 20
* - SSP0_ITLine : VIC source 21
* - SSP1_ITLine : VIC source 22
* - LVD_ITLine : VIC source 23
* - RTC_ITLine : VIC source 24
* - WIU_ITLine : VIC source 25
* - EXTIT0_ITLine: VIC source 26
* - EXTIT1_ITLine: VIC source 27
* - EXTIT2_ITLine: VIC source 28
* - EXTIT3_ITLine: VIC source 29
* - USBWU_ITLine : VIC source 30
* - PFQBC_ITLine : VIC source 31
* Output : None
* Return : The status of the IRQ interrupt after masking (SET or RESET).
*******************************************************************************/
FlagStatus VIC_GetIRQStatus(u16 VIC_Source)
{
u32 VIC_Mask = 1;
if (VIC_Source < VIC_REGISTER_NUMBER)
{
if ((VIC0->ISR | VIC_Mask << VIC_Source) != RESET)
return SET;
else
return RESET;
}
else
{
if ((VIC1->ISR | VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)) != RESET)
return SET;
else
return RESET;
}
}
/*******************************************************************************
* Function Name : VIC_GetFIQStatus
* Description : Get the status of interrupts after FIQ masking
* Input : VIC_Source: specifies the number of the source line.
* This parameter can be one of the following values:
* - WDG_ITLine : VIC source 0
* - SW_ITLine : VIC source 1
* - ARMRX_ITLine : VIC source 2
* - ARMTX_ITLine : VIC source 3
* - TIM0_ITLine : VIC source 4
* - TIM1_ITLine : VIC source 5
* - TIM2_ITLine : VIC source 6
* - TIM3_ITLine : VIC source 7
* - USBHP_ITLine : VIC source 8
* - USBLP_ITLine : VIC source 9
* - SCU_ITLine : VIC source 10
* - ENET_ITLine : VIC source 11
* - DMA_ITLine : VIC source 12
* - CAN_ITLine : VIC source 13
* - MC_ITLine : VIC source 14
* - ADC_ITLine : VIC source 15
* - UART0_ITLine : VIC source 16
* - UART1_ITLine : VIC source 17
* - UART2_ITLine : VIC source 18
* - I2C0_ITLine : VIC source 19
* - I2C1_ITLine : VIC source 20
* - SSP0_ITLine : VIC source 21
* - SSP1_ITLine : VIC source 22
* - LVD_ITLine : VIC source 23
* - RTC_ITLine : VIC source 24
* - WIU_ITLine : VIC source 25
* - EXTIT0_ITLine: VIC source 26
* - EXTIT1_ITLine: VIC source 27
* - EXTIT2_ITLine: VIC source 28
* - EXTIT3_ITLine: VIC source 29
* - USBWU_ITLine : VIC source 30
* - PFQBC_ITLine : VIC source 31
* Output : None
* Return : The status of the FIQ interrupt after masking (SET or RESET)
*******************************************************************************/
FlagStatus VIC_GetFIQStatus(u16 VIC_Source)
{
u32 VIC_Mask = 1;
if (VIC_Source < VIC_REGISTER_NUMBER)
{
if ((VIC0->RINTSR | VIC_Mask << VIC_Source) != RESET)
return SET;
else
return RESET;
}
else
{
if ((VIC1->RINTSR | VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)) != RESET)
return SET;
else
return RESET;
}
}
/*******************************************************************************
* Function Name : VIC_GetSourceITStatus
* Description : Get the status of the source interrupts before masking.
* Input : VIC_Source: specifies the number of the source line.
* This parameter can be one of the following values:
* - WDG_ITLine : VIC source 0
* - SW_ITLine : VIC source 1
* - ARMRX_ITLine : VIC source 2
* - ARMTX_ITLine : VIC source 3
* - TIM0_ITLine : VIC source 4
* - TIM1_ITLine : VIC source 5
* - TIM2_ITLine : VIC source 6
* - TIM3_ITLine : VIC source 7
* - USBHP_ITLine : VIC source 8
* - USBLP_ITLine : VIC source 9
* - SCU_ITLine : VIC source 10
* - ENET_ITLine : VIC source 11
* - DMA_ITLine : VIC source 12
* - CAN_ITLine : VIC source 13
* - MC_ITLine : VIC source 14
* - ADC_ITLine : VIC source 15
* - UART0_ITLine : VIC source 16
* - UART1_ITLine : VIC source 17
* - UART2_ITLine : VIC source 18
* - I2C0_ITLine : VIC source 19
* - I2C1_ITLine : VIC source 20
* - SSP0_ITLine : VIC source 21
* - SSP1_ITLine : VIC source 22
* - LVD_ITLine : VIC source 23
* - RTC_ITLine : VIC source 24
* - WIU_ITLine : VIC source 25
* - EXTIT0_ITLine: VIC source 26
* - EXTIT1_ITLine: VIC source 27
* - EXTIT2_ITLine: VIC source 28
* - EXTIT3_ITLine: VIC source 29
* - USBWU_ITLine : VIC source 30
* - PFQBC_ITLine : VIC source 31
* Output : None
* Return : The status of the source interrupt before masking
*******************************************************************************/
FlagStatus VIC_GetSourceITStatus(u16 VIC_Source)
{
u32 VIC_Mask = 1;
if (VIC_Source < VIC_REGISTER_NUMBER)
{
if ((VIC0->FSR | VIC_Mask << VIC_Source) != RESET)
return SET;
else
return RESET;
}
else
{
if ((VIC1->FSR | VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER)) != RESET)
return SET;
else
return RESET;
}
}
/*******************************************************************************
* Function Name : VIC_ITModeConfig
* Description : Select the type of interrupt (IRQ or FIQ)
* Input1 : VIC_Source: specifies the number of the source line.
* This parameter can be one of the following values:
* - WDG_ITLine : VIC source 0
* - SW_ITLine : VIC source 1
* - ARMRX_ITLine : VIC source 2
* - ARMTX_ITLine : VIC source 3
* - TIM0_ITLine : VIC source 4
* - TIM1_ITLine : VIC source 5
* - TIM2_ITLine : VIC source 6
* - TIM3_ITLine : VIC source 7
* - USBHP_ITLine : VIC source 8
* - USBLP_ITLine : VIC source 9
* - SCU_ITLine : VIC source 10
* - ENET_ITLine : VIC source 11
* - DMA_ITLine : VIC source 12
* - CAN_ITLine : VIC source 13
* - MC_ITLine : VIC source 14
* - ADC_ITLine : VIC source 15
* - UART0_ITLine : VIC source 16
* - UART1_ITLine : VIC source 17
* - UART2_ITLine : VIC source 18
* - I2C0_ITLine : VIC source 19
* - I2C1_ITLine : VIC source 20
* - SSP0_ITLine : VIC source 21
* - SSP1_ITLine : VIC source 22
* - LVD_ITLine : VIC source 23
* - RTC_ITLine : VIC source 24
* - WIU_ITLine : VIC source 25
* - EXTIT0_ITLine: VIC source 26
* - EXTIT1_ITLine: VIC source 27
* - EXTIT2_ITLine: VIC source 28
* - EXTIT3_ITLine: VIC source 29
* - USBWU_ITLine : VIC source 30
* - PFQBC_ITLine : VIC source 31
* Input2 : VIC_LineMode :specifies the type of interrupt of the source
* line. This parameter can be one of the following values:
* - VIC_IRQ: the correspondent line is configured as IRQ.
* - VIC_FIQ: the correspondent line is configured as FIQ.
* Output : None
* Return : None
*******************************************************************************/
static void VIC_ITModeConfig(u16 VIC_Source, VIC_ITLineMode VIC_LineMode)
{
u32 VIC_Mask = 1;
if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */
{
if (VIC_LineMode == VIC_IRQ)
VIC0->INTSR &= ~(VIC_Mask << VIC_Source);
else /* VIC_LineMode == VIC_FIQ */
VIC0->INTSR |= (VIC_Mask << VIC_Source);
}
else /* VIC1 */
{
if (VIC_LineMode == VIC_IRQ)
VIC1->INTSR &= ~(VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER));
else /* VIC_LineMode == VIC_FIQ */
VIC1->INTSR |= (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER));
}
}
/*******************************************************************************
* Function Name : VIC_ITCmd
* Description : Enable or disable the interrupt request lines.
* Input1 : VIC_Source: specifies the number of the source line.
* This parameter can be one of the following values:
* - WDG_ITLine : VIC source 0
* - SW_ITLine : VIC source 1
* - ARMRX_ITLine : VIC source 2
* - ARMTX_ITLine : VIC source 3
* - TIM0_ITLine : VIC source 4
* - TIM1_ITLine : VIC source 5
* - TIM2_ITLine : VIC source 6
* - TIM3_ITLine : VIC source 7
* - USBHP_ITLine : VIC source 8
* - USBLP_ITLine : VIC source 9
* - SCU_ITLine : VIC source 10
* - ENET_ITLine : VIC source 11
* - DMA_ITLine : VIC source 12
* - CAN_ITLine : VIC source 13
* - MC_ITLine : VIC source 14
* - ADC_ITLine : VIC source 15
* - UART0_ITLine : VIC source 16
* - UART1_ITLine : VIC source 17
* - UART2_ITLine : VIC source 18
* - I2C0_ITLine : VIC source 19
* - I2C1_ITLine : VIC source 20
* - SSP0_ITLine : VIC source 21
* - SSP1_ITLine : VIC source 22
* - LVD_ITLine : VIC source 23
* - RTC_ITLine : VIC source 24
* - WIU_ITLine : VIC source 25
* - EXTIT0_ITLine: VIC source 26
* - EXTIT1_ITLine: VIC source 27
* - EXTIT2_ITLine: VIC source 28
* - EXTIT3_ITLine: VIC source 29
* - USBWU_ITLine : VIC source 30
* - PFQBC_ITLine : VIC source 31
* Input2 : FMI_NewState: specifies the line status.
* This parameter can be one of the following values:
* - ENABLE: The line is enabled.
* - DISABLE: The line is disabled.
* Output : None
* Return : None
*******************************************************************************/
void VIC_ITCmd(u16 VIC_Source, FunctionalState VIC_NewState)
{
u32 VIC_Mask = 1;
if (VIC_NewState == ENABLE)
{
if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */
VIC0->INTER |= (VIC_Mask << VIC_Source);
else /* VIC1 */
VIC1->INTER |= (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER));
}
else /* VIC_NewState == DISABLE */
{
if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */
VIC0->INTECR |= (VIC_Mask << VIC_Source);
else /* VIC1 */
VIC1->INTECR |= (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER));
}
}
/*******************************************************************************
* Function Name : VIC_SWITCmd
* Description : Generate a software interrupt for the specific source
* interrupt.
* Input1 : VIC_Source: specifies the number of the source line.
* This parameter can be one of the following values:
* - WDG_ITLine : VIC source 0
* - SW_ITLine : VIC source 1
* - ARMRX_ITLine : VIC source 2
* - ARMTX_ITLine : VIC source 3
* - TIM0_ITLine : VIC source 4
* - TIM1_ITLine : VIC source 5
* - TIM2_ITLine : VIC source 6
* - TIM3_ITLine : VIC source 7
* - USBHP_ITLine : VIC source 8
* - USBLP_ITLine : VIC source 9
* - SCU_ITLine : VIC source 10
* - ENET_ITLine : VIC source 11
* - DMA_ITLine : VIC source 12
* - CAN_ITLine : VIC source 13
* - MC_ITLine : VIC source 14
* - ADC_ITLine : VIC source 15
* - UART0_ITLine : VIC source 16
* - UART1_ITLine : VIC source 17
* - UART2_ITLine : VIC source 18
* - I2C0_ITLine : VIC source 19
* - I2C1_ITLine : VIC source 20
* - SSP0_ITLine : VIC source 21
* - SSP1_ITLine : VIC source 22
* - LVD_ITLine : VIC source 23
* - RTC_ITLine : VIC source 24
* - WIU_ITLine : VIC source 25
* - EXTIT0_ITLine: VIC source 26
* - EXTIT1_ITLine: VIC source 27
* - EXTIT2_ITLine: VIC source 28
* - EXTIT3_ITLine: VIC source 29
* - USBWU_ITLine : VIC source 30
* - PFQBC_ITLine : VIC source 31
* Input2 : FMI_NewState: specifies the software interrupt status.
* This parameter can be one of the following values:
* - ENABLE: The software interrupt is enabled.
* - DISABLE: The software interrupt is disabled.
* Output : None
* Return : None
*******************************************************************************/
void VIC_SWITCmd(u16 VIC_Source, FunctionalState VIC_NewState)
{
u32 VIC_Mask = 1;
if (VIC_NewState == ENABLE)
{
if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */
VIC0->SWINTR |= (VIC_Mask << VIC_Source);
else /* VIC1 */
VIC1->SWINTR |= (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER));
}
else /* VIC_NewState == DISABLE */
{
if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */
VIC0->SWINTCR = (VIC_Mask << VIC_Source);
else /* VIC1 */
VIC1->SWINTCR = (VIC_Mask << (VIC_Source - VIC_REGISTER_NUMBER));
}
}
/*******************************************************************************
* Function Name : VIC_ProtectionCmd
* Description : Enable or Disable the register access protection.
* Input : FMI_NewState: specifies the protection status.
* This parameter can be one of the following values:
* - ENABLE: The protection is enabled.
* - DISABLE: The protection is disabled.
* Output : None
* Return : None
*******************************************************************************/
void VIC_ProtectionCmd(FunctionalState VIC_NewState)
{
if (VIC_NewState == ENABLE)
{
VIC0->PER |= VIC_PROTECTION_ENABLE_MASK;
VIC1->PER |= VIC_PROTECTION_ENABLE_MASK;
}
else
{
VIC0->PER &= VIC_PROTECTION_DISABLE_MASK;
VIC1->PER &= VIC_PROTECTION_DISABLE_MASK;
}
}
/*******************************************************************************
* Function Name : VIC_GetCurrentISRAdd
* Description : Get the address of the current active ISR.
* Input : VICx: specifies the VIC peripheral
* This parameter can be one of the following values:
* - VIC0: To select VIC0.
* - VIC1: To select VIC1.
* Output : None
* Return : The Address of the active ISR.
*******************************************************************************/
u32 VIC_GetCurrentISRAdd(VIC_TypeDef* VICx)
{
return VICx->VAR;
}
/*******************************************************************************
* Function Name : VIC_ISRVectAddConfig
* Description : Configuration of the ISR vector address.
* Input1 : VIC_Source: specifies the number of the source line.
* This parameter can be one of the following values:
* - WDG_ITLine : VIC source 0
* - SW_ITLine : VIC source 1
* - ARMRX_ITLine : VIC source 2
* - ARMTX_ITLine : VIC source 3
* - TIM0_ITLine : VIC source 4
* - TIM1_ITLine : VIC source 5
* - TIM2_ITLine : VIC source 6
* - TIM3_ITLine : VIC source 7
* - USBHP_ITLine : VIC source 8
* - USBLP_ITLine : VIC source 9
* - SCU_ITLine : VIC source 10
* - ENET_ITLine : VIC source 11
* - DMA_ITLine : VIC source 12
* - CAN_ITLine : VIC source 13
* - MC_ITLine : VIC source 14
* - ADC_ITLine : VIC source 15
* - UART0_ITLine : VIC source 16
* - UART1_ITLine : VIC source 17
* - UART2_ITLine : VIC source 18
* - I2C0_ITLine : VIC source 19
* - I2C1_ITLine : VIC source 20
* - SSP0_ITLine : VIC source 21
* - SSP1_ITLine : VIC source 22
* - LVD_ITLine : VIC source 23
* - RTC_ITLine : VIC source 24
* - WIU_ITLine : VIC source 25
* - EXTIT0_ITLine: VIC source 26
* - EXTIT1_ITLine: VIC source 27
* - EXTIT2_ITLine: VIC source 28
* - EXTIT3_ITLine: VIC source 29
* - USBWU_ITLine : VIC source 30
* - PFQBC_ITLine : VIC source 31
* Input2 : VIC_Priority: specifies the priority of the interrupt.
* It can be a value from 0 to 15. 0 is the highest priority.
* Input3 : void (*VIC_VectAddress)(void): specifies the ISR vector
* address pointer.
* Output : None
* Return : None
*******************************************************************************/
static void VIC_ISRVectAddConfig(u16 VIC_Source, u16 VIC_Priority, \
void (*VIC_VectAddress)(void))
{
if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */
VIC0->VAiR[VIC_Priority] = (u32)VIC_VectAddress;
else /* VIC1 */
VIC1->VAiR[VIC_Priority] = (u32)VIC_VectAddress;
}
/*******************************************************************************
* Function Name : VIC_GetISRVectAdd
* Description : Get the ISR vector address of the correspondent line.
* Input : VIC_Source: specifies the number of the source line.
* This parameter can be one of the following values:
* - WDG_ITLine : VIC source 0
* - SW_ITLine : VIC source 1
* - ARMRX_ITLine : VIC source 2
* - ARMTX_ITLine : VIC source 3
* - TIM0_ITLine : VIC source 4
* - TIM1_ITLine : VIC source 5
* - TIM2_ITLine : VIC source 6
* - TIM3_ITLine : VIC source 7
* - USBHP_ITLine : VIC source 8
* - USBLP_ITLine : VIC source 9
* - SCU_ITLine : VIC source 10
* - ENET_ITLine : VIC source 11
* - DMA_ITLine : VIC source 12
* - CAN_ITLine : VIC source 13
* - MC_ITLine : VIC source 14
* - ADC_ITLine : VIC source 15
* - UART0_ITLine : VIC source 16
* - UART1_ITLine : VIC source 17
* - UART2_ITLine : VIC source 18
* - I2C0_ITLine : VIC source 19
* - I2C1_ITLine : VIC source 20
* - SSP0_ITLine : VIC source 21
* - SSP1_ITLine : VIC source 22
* - LVD_ITLine : VIC source 23
* - RTC_ITLine : VIC source 24
* - WIU_ITLine : VIC source 25
* - EXTIT0_ITLine: VIC source 26
* - EXTIT1_ITLine: VIC source 27
* - EXTIT2_ITLine: VIC source 28
* - EXTIT3_ITLine: VIC source 29
* - USBWU_ITLine : VIC source 30
* - PFQBC_ITLine : VIC source 31
* Output : None
* Return : The correspondent ISR vector address.
*******************************************************************************/
u32 VIC_GetISRVectAdd(u16 VIC_Source)
{
if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */
return VIC0->VAiR[VIC_Source];
else /* VIC1 */
return VIC1->VAiR[VIC_Source - VIC_REGISTER_NUMBER];
}
/*******************************************************************************
* Function Name : VIC_VectEnableConfig
* Description : Enable the vector interrupt.
* Input1 : VIC_Source: specifies the number of the source line.
* This parameter can be one of the following values:
* - WDG_ITLine : VIC source 0
* - SW_ITLine : VIC source 1
* - ARMRX_ITLine : VIC source 2
* - ARMTX_ITLine : VIC source 3
* - TIM0_ITLine : VIC source 4
* - TIM1_ITLine : VIC source 5
* - TIM2_ITLine : VIC source 6
* - TIM3_ITLine : VIC source 7
* - USBHP_ITLine : VIC source 8
* - USBLP_ITLine : VIC source 9
* - SCU_ITLine : VIC source 10
* - ENET_ITLine : VIC source 11
* - DMA_ITLine : VIC source 12
* - CAN_ITLine : VIC source 13
* - MC_ITLine : VIC source 14
* - ADC_ITLine : VIC source 15
* - UART0_ITLine : VIC source 16
* - UART1_ITLine : VIC source 17
* - UART2_ITLine : VIC source 18
* - I2C0_ITLine : VIC source 19
* - I2C1_ITLine : VIC source 20
* - SSP0_ITLine : VIC source 21
* - SSP1_ITLine : VIC source 22
* - LVD_ITLine : VIC source 23
* - RTC_ITLine : VIC source 24
* - WIU_ITLine : VIC source 25
* - EXTIT0_ITLine: VIC source 26
* - EXTIT1_ITLine: VIC source 27
* - EXTIT2_ITLine: VIC source 28
* - EXTIT3_ITLine: VIC source 29
* - USBWU_ITLine : VIC source 30
* - PFQBC_ITLine : VIC source 31
* Input2 : VIC_Priority: specifies the priority of the interrupt.
* It can be a value from 0 to 15. 0 is the highest priority.
* Output : None
* Return : None
*******************************************************************************/
static void VIC_VectEnableConfig(u16 VIC_Source, u16 VIC_Priority)
{
if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */
VIC0->VCiR[VIC_Priority] |= VIC_VECTOR_ENABLE_MASK;
else /* VIC1 */
VIC1->VCiR[VIC_Priority] |= VIC_VECTOR_ENABLE_MASK;
}
/*******************************************************************************
* Function Name : VIC_ITSourceConfig
* Description : Select the interrupt source.
* Input1 : VIC_Source: specifies the number of the source line.
* This parameter can be one of the following values:
* - WDG_ITLine : VIC source 0
* - SW_ITLine : VIC source 1
* - ARMRX_ITLine : VIC source 2
* - ARMTX_ITLine : VIC source 3
* - TIM0_ITLine : VIC source 4
* - TIM1_ITLine : VIC source 5
* - TIM2_ITLine : VIC source 6
* - TIM3_ITLine : VIC source 7
* - USBHP_ITLine : VIC source 8
* - USBLP_ITLine : VIC source 9
* - SCU_ITLine : VIC source 10
* - ENET_ITLine : VIC source 11
* - DMA_ITLine : VIC source 12
* - CAN_ITLine : VIC source 13
* - MC_ITLine : VIC source 14
* - ADC_ITLine : VIC source 15
* - UART0_ITLine : VIC source 16
* - UART1_ITLine : VIC source 17
* - UART2_ITLine : VIC source 18
* - I2C0_ITLine : VIC source 19
* - I2C1_ITLine : VIC source 20
* - SSP0_ITLine : VIC source 21
* - SSP1_ITLine : VIC source 22
* - LVD_ITLine : VIC source 23
* - RTC_ITLine : VIC source 24
* - WIU_ITLine : VIC source 25
* - EXTIT0_ITLine: VIC source 26
* - EXTIT1_ITLine: VIC source 27
* - EXTIT2_ITLine: VIC source 28
* - EXTIT3_ITLine: VIC source 29
* - USBWU_ITLine : VIC source 30
* - PFQBC_ITLine : VIC source 31
* Input2 : VIC_Priority: specifies the priority of the interrupt.
* It can be a value from 0 to 15. 0 is the highest priority.
* Output : None
* Return : None
*******************************************************************************/
static void VIC_ITSourceConfig(u16 VIC_Source, u16 VIC_Priority)
{
if (VIC_Source < VIC_REGISTER_NUMBER) /* VIC0 */
{
VIC0->VCiR[VIC_Priority] &= VIC_IT_SOURCE_MASK;
VIC0->VCiR[VIC_Priority] |= VIC_Source;
}
else /* VIC1 */
{
VIC1->VCiR[VIC_Priority] &= VIC_IT_SOURCE_MASK;
VIC1->VCiR[VIC_Priority] |= VIC_Source - VIC_REGISTER_NUMBER;
}
}
/*******************************************************************************
* Function Name : VIC_Config
* Description : Configure the ISR, the line, the mode and the priority for
* each interrupt source line.
* Input1 : VIC_Source: specifies the number of the source line.
* This parameter can be one of the following values:
* - WDG_ITLine : VIC source 0
* - SW_ITLine : VIC source 1
* - ARMRX_ITLine : VIC source 2
* - ARMTX_ITLine : VIC source 3
* - TIM0_ITLine : VIC source 4
* - TIM1_ITLine : VIC source 5
* - TIM2_ITLine : VIC source 6
* - TIM3_ITLine : VIC source 7
* - USBHP_ITLine : VIC source 8
* - USBLP_ITLine : VIC source 9
* - SCU_ITLine : VIC source 10
* - ENET_ITLine : VIC source 11
* - DMA_ITLine : VIC source 12
* - CAN_ITLine : VIC source 13
* - MC_ITLine : VIC source 14
* - ADC_ITLine : VIC source 15
* - UART0_ITLine : VIC source 16
* - UART1_ITLine : VIC source 17
* - UART2_ITLine : VIC source 18
* - I2C0_ITLine : VIC source 19
* - I2C1_ITLine : VIC source 20
* - SSP0_ITLine : VIC source 21
* - SSP1_ITLine : VIC source 22
* - LVD_ITLine : VIC source 23
* - RTC_ITLine : VIC source 24
* - WIU_ITLine : VIC source 25
* - EXTIT0_ITLine: VIC source 26
* - EXTIT1_ITLine: VIC source 27
* - EXTIT2_ITLine: VIC source 28
* - EXTIT3_ITLine: VIC source 29
* - USBWU_ITLine : VIC source 30
* - PFQBC_ITLine : VIC source 31
* Input2 : VIC_LineMode :specifies the type of interrupt of the source
* line. This parameter can be one of the following values:
* - VIC_IRQ: the correspondent line is configured as IRQ.
* - VIC_FIQ: the correspondent line is configured as FIQ.
* Input3 : VIC_Priority: specifies the priority of the interrupt.
* It can be a value from 0 to 15. 0 is the highest priority.
* Output : None
* Return : None
*******************************************************************************/
void VIC_Config(u16 VIC_Source, VIC_ITLineMode VIC_LineMode, u8 VIC_Priority)
{
switch (VIC_Source)
{
case 0: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, WDG_IRQHandler);
break;
case 1: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, SW_IRQHandler);
break;
case 2: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, ARMRX_IRQHandler);
break;
case 3: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, ARMTX_IRQHandler);
break;
case 4: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, TIM0_IRQHandler);
break;
case 5: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, TIM1_IRQHandler);
break;
case 6: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, TIM2_IRQHandler);
break;
case 7: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, TIM3_IRQHandler);
break;
case 8: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, USBHP_IRQHandler);
break;
case 9: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, USBLP_IRQHandler);
break;
case 10: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, SCU_IRQHandler);
break;
case 11: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, ENET_IRQHandler);
break;
case 12: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, DMA_IRQHandler);
break;
case 13: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, CAN_IRQHandler);
break;
case 14: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, MC_IRQHandler);
break;
case 15: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, ADC_IRQHandler);
break;
case 16: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, UART0_IRQHandler);
break;
case 17: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, UART1_IRQHandler);
break;
case 18: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, UART2_IRQHandler);
break;
case 19: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, I2C0_IRQHandler);
break;
case 20: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, I2C1_IRQHandler);
break;
case 21: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, SSP0_IRQHandler);
break;
case 22: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, SSP1_IRQHandler);
break;
case 23: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, LVD_IRQHandler);
break;
case 24: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, RTC_IRQHandler);
break;
case 25: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, WIU_IRQHandler);
break;
case 26: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, EXTIT0_IRQHandler);
break;
case 27: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, EXTIT1_IRQHandler);
break;
case 28: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, EXTIT2_IRQHandler);
break;
case 29: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, EXTIT3_IRQHandler);
break;
case 30: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, USBWU_IRQHandler);
break;
case 31: VIC_ISRVectAddConfig(VIC_Source, VIC_Priority, PFQBC_IRQHandler);
break;
default: break;
}
VIC_ITModeConfig(VIC_Source, VIC_LineMode);
VIC_VectEnableConfig(VIC_Source, VIC_Priority);
VIC_ITSourceConfig(VIC_Source, VIC_Priority);
}
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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Demo/ARM9_STR91X_IAR/Library/source/91x_wdg.c
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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : 91x_wdg.c
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : This file provides all the WDG software functions.
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "91x_wdg.h"
#include "91x_scu.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* WDG End of Count interrupt Flag */
#define WDG_FLAG_EC 0x0001
/* WDG End of Count interrupt request */
#define WDG_IT_EC 0x0001
/* WDG Start/Stop counter */
#define WDG_Counter_Start 0x0002
#define WDG_Counter_Stop 0xFFFD
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Registers reset value */
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/******************************************************************************
* Function Name : WDG_DeInit
* Description : Deinitializes the WDG peripheral registers to their default
* reset values.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void WDG_DeInit(void)
{
SCU_APBPeriphReset(__WDG, ENABLE); /*WDG peripheral under Reset */
SCU_APBPeriphReset(__WDG, DISABLE); /*WDG peripheral Reset off*/
}
/*******************************************************************************
* Function Name : WDG_StructInit
* Description : Fills the WDG_InitTypeDef structure member with its reset
* value.
* Input : WDG_InitStruct : pointer to a WDG_InitTypeDef structure
* which will be initialized.
* Output : None
* Return : None
*******************************************************************************/
void WDG_StructInit(WDG_InitTypeDef *WDG_InitStruct)
{
/* Select the Watchdog running mode*/
WDG_InitStruct->WDG_Mode = WDG_Mode_Timer;
/* Select the source clock */
WDG_InitStruct-> WDG_ClockSource = WDG_ClockSource_Apb;
/* Initialize Prescaler */
WDG_InitStruct->WDG_Prescaler =0xFF;
/* Initialize Preload */
WDG_InitStruct->WDG_Preload =0xFFFF;
}
/*******************************************************************************
* Function Name : WDG_Init
* Description : Initializes WDG peripheral according to the specified
* parameters in the WDG_InitStruct.
* Input : WDG_InitStruct: pointer to a WDG_InitTypeDef structure that
* contains the configuration information for the WDG peripheral.
* Output : None
* Return : None
*******************************************************************************/
void WDG_Init(WDG_InitTypeDef* WDG_InitStruct)
{
if(WDG_InitStruct->WDG_ClockSource == WDG_ClockSource_Apb)
{
/* Select The APB clock as clock source */
WDG->CR &= WDG_ClockSource_Apb;
}
else
{
/* Select the RTC clock as source */
WDG->CR |= WDG_ClockSource_Rtc ;
}
/* Configure WDG Prescaler register value */
WDG->PR = WDG_InitStruct->WDG_Prescaler;
/* Configure WDG Pre-load register value */
WDG->VR = WDG_InitStruct->WDG_Preload ;
if(WDG_InitStruct->WDG_Mode == WDG_Mode_Timer)
{
/* Select Timer mode */
WDG->CR &= WDG_Mode_Timer;
}
else
{
/* Select WDG mode */
WDG->CR |= WDG_Mode_Wdg ;
}
}
/*******************************************************************************
* Function Name : WDG_Cmd
* Description : Enables or disables the WDG peripheral.
* Input : NewState: new state of the WDG peripheral (Newstate can be
* ENABLE or DISABLE)
* Output : None
* Return : None
*******************************************************************************/
void WDG_Cmd(FunctionalState NewState )
{
if((WDG->CR & WDG_Mode_Wdg) == 0)
{
/* Timer mode */
if(NewState == ENABLE)
{
/* Start timer by setting SC bit in Control register */
WDG->CR |= WDG_Counter_Start;
}
else
{
/* Stop timer by clearning SC bit in Control register */
WDG->CR &= WDG_Counter_Stop;
}
}
else
{
/* Watchdog mode */
if(NewState == ENABLE)
{
WDG->KR = WDG_KeyValue1;
WDG->KR = WDG_KeyValue2;
}
}
}
/*******************************************************************************
* Function Name : WDG_ITConfig
* Description : Enables or disables the WDG End of Count(EC) interrupt.
* Input : Newstate: new state of the End of Count(EC) WDG interrupt.
* This parameter can be: ENABLE or DISABLE.
* Output : None
* Return : None
*******************************************************************************/
void WDG_ITConfig(FunctionalState NewState)
{
if(NewState == ENABLE)
{
/* Enable the End of Count interrupt */
WDG->MR |= WDG_IT_EC;
}
else
{
/* Disable the End of Count interrupt */
WDG->MR &= ~WDG_IT_EC;
}
}
/*******************************************************************************
* Function Name : WDG_GetCounter
* Description : Gets the WDG’s current counter value.
* Input : None
* Output : None
* Return : The WDG current counter value
*******************************************************************************/
u16 WDG_GetCounter(void)
{
return WDG->CNT;
}
/*******************************************************************************
* Function Name : WDG_GetITStatus
* Description : Checks whether the WDG End of Count(EC) interrupt is occured or not.
* Input : None
* Output : None
* Return : The new state of WDG_IT (SET or RESET).
*******************************************************************************/
ITStatus WDG_GetITStatus(void)
{
if(((WDG->SR & WDG_IT_EC) != RESET )&&((WDG->MR & WDG_IT_EC) != RESET ))
{
return SET;
}
else
{
return RESET;
}
}
/*******************************************************************************
* Function Name : WDG_ClearITPendingBit
* Description : Clears the WDG's End of Count(EC) interrupt pending bit.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void WDG_ClearITPendingBit(void)
{
/* Clear the EC pending bit */
WDG->SR &= ~WDG_IT_EC;
}
/*******************************************************************************
* Function Name : WDG_ClearFlag
* Description : Clears the WDG's End of Count(EC) Flag.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void WDG_ClearFlag(void)
{
/* Clear the EC Flag */
WDG->SR &= ~WDG_FLAG_EC;
}
/*******************************************************************************
* Function Name : WDG_GetFlagStatus
* Description : Checks whether the WDG End of Count(EC) flag is set or not.
* Input : None
* Output : None
* Return : The new state of the WDG_FLAG (SET or RESET).
*******************************************************************************/
FlagStatus WDG_GetFlagStatus(void)
{
if((WDG->SR & WDG_FLAG_EC) != RESET )
{
return SET;
}
else
{
return RESET;
}
}
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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Demo/ARM9_STR91X_IAR/ParTest/ParTest.c
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/*
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
/* Library includes. */
#include "91x_lib.h"
/* Scheduler includes. */
#include "FreeRTOS.h"
/* Demo application includes. */
#include "partest.h"
#define partstMAX_LEDs 4
#define partstLED_PORT *( ( unsigned portSHORT * ) 0x5800f3fc )
/*-----------------------------------------------------------*/
static GPIO_InitTypeDef GPIO9_InitStruct;
void vParTestInitialise( void )
{
/* Configure the bits used to flash LED's on port 9 as output. */
GPIO_StructInit( &GPIO9_InitStruct );
GPIO9_InitStruct.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3;
GPIO9_InitStruct.GPIO_Direction = GPIO_PinOutput;
GPIO_Init( GPIO9, &GPIO9_InitStruct );
}
/*-----------------------------------------------------------*/
void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
{
unsigned portSHORT usLED = 0x0001;
if( uxLED < partstMAX_LEDs )
{
usLED <<= uxLED;
portENTER_CRITICAL();
{
if( xValue )
{
partstLED_PORT &= ~usLED;
}
else
{
partstLED_PORT |= usLED;
}
}
portEXIT_CRITICAL();
}
}
/*-----------------------------------------------------------*/
void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
{
unsigned portSHORT usLED = 0x0001;
if( uxLED < partstMAX_LEDs )
{
usLED <<= uxLED;
portENTER_CRITICAL();
{
if( partstLED_PORT & usLED )
{
partstLED_PORT &= ~usLED;
}
else
{
partstLED_PORT |= usLED;
}
}
portEXIT_CRITICAL();
}
}

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Demo/ARM9_STR91X_IAR/RTOSDemo.eww
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<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\RTOSDemo.ewp</path>
</project>
<batchBuild/>
</workspace>

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Demo/ARM9_STR91X_IAR/STCode/lcd.h
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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name : lcd.h
* Author : MCD Application Team
* Date First Issued : 05/18/2006 : Version 1.0
* Description : This file contains all the functions prototypes for the
* lcd software driver.
********************************************************************************
* History:
* 05/24/2006 : Version 1.1
* 05/18/2006 : Version 1.0
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Define to prevent recursive inclusion ---------------------------------------*/
#ifndef __LCD_H
#define __LCD_H
/* Includes --------------------------------------------------------------------*/
#include "91x_lib.h"
/* Exported types --------------------------------------------------------------*/
/* Data lines configuration mode */
typedef enum
{
Input,
Output
} DataConfigMode_TypeDef;
/* Text color mode */
typedef enum
{
BlackText=0,
WhiteText=1
} TextColorMode_TypeDef;
/* Dot On/Off mode */
typedef enum
{
Dot_On,
Dot_Off
} DotMode_TypeDef;
/* Exported constants ----------------------------------------------------------*/
/* LCD Control pins */
#define CtrlPin_E2 0x20
#define CtrlPin_E1 0x10
#define CtrlPin_RW 0x40
#define CtrlPin_DI 0x80
/* LCD Commands */
#define DISPLAY_ON 0xAF
#define DISPLAY_OFF 0xAE
#define START_LINE 0xC0
#define START_COLUMN 0x00
#define CLOCKWISE_OUTPUT 0xA0
#define DYNAMIC_DRIVE 0xA4
#define DUTY_CYCLE 0xA9
#define READ_MODIFY_WRITE_OFF 0xEE
#define SOFTWARE_RESET 0xE2
/* LCD Lines when LCD is managed as 2*17 characters */
#define Line1 0x0
#define Line2 0x2
/* Exported macro --------------------------------------------------------------*/
/* Exported functions ----------------------------------------------------------*/
/*----- Low layer function -----*/
void LCD_CtrlLinesConfig(void);
void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, u32 CtrlPins, BitAction BitVal);
void LCD_DataLinesConfig(DataConfigMode_TypeDef Mode);
void LCD_DataLinesWrite(GPIO_TypeDef* GPIOx, u32 PortVal);
/*----- Medium layer function -----*/
void LCD_CheckMasterStatus(void);
void LCD_CheckSlaveStatus(void);
void LCD_SendMasterCmd(u8 Cmd);
void LCD_SendSlaveCmd(u8 Cmd);
void LCD_SendMasterData(u8 Data);
u32 LCD_ReadMasterData(void);
void LCD_SendSlaveData(u8 Data);
u32 LCD_ReadSlaveData(void);
void LCD_SetMasterPage(u8 Page);
void LCD_SetSlavePage(u8 Page);
void LCD_SetMasterColumn(u8 Address);
void LCD_SetSlaveColumn(u8 Address);
void LCD_DrawChar(u8 Line, u8 Column, u8 Width, u8 *Bmp);
char LCD_HexToAsciiLow(u8 byte);
char LCD_HexToAsciiHigh(u8 byte);
void LCD_SetTextColor(TextColorMode_TypeDef TextColor);
/*----- High layer function -----*/
void LCD_Init(void);
/* LCD managed as 2 Lines, 17 characters each one (2Lines*17Char) */
void LCD_ClearLine(u8 Line);
void LCD_DisplayChar(u8 Line, u8 Column, u8 Ascii, TextColorMode_TypeDef CharMode);
void LCD_DisplayString(u8 Line, u8 *ptr, TextColorMode_TypeDef CharMode);
void LCD_Printf(u8* ptr, ...);
/* LCD managed as 122*32 dots */
void LCD_ClearMaster(void);
void LCD_ClearSlave(void);
void LCD_Clear(void);
void LCD_DrawMasterGraphic(u8 *Bmp);
void LCD_DrawSlaveGraphic(u8 *Bmp);
void LCD_DrawGraphic(u8 *Bmp);
void LCD_ScrollGraphic(u8 *Bmp, u32 nCount);
void LCD_DrawPixel(u8 XPos, u8 YPos, DotMode_TypeDef Mode);
void LCD_DrawLine(u8 XPos1, u8 YPos1, u8 XPos2, u8 YPos2);
void LCD_DrawBox(u8 XPos, u8 YPos, u8 Dx, u8 Dy);
#endif /*__LCD_H */
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE******/

218
Demo/ARM9_STR91X_IAR/lnkarm_flash.xcl
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/*;******************** (C) COPYRIGHT 2005 STMicroelectronics **************************
;* File Name : lnkarm_ram.xcl
;* Author : MCD Application Team
;* Date First Issued : 09/27/2005 : V1.0
;* Description : XLINK command file for EWARM/ICCARM
;* : Usage: xlink -f lnkarm <your_object_file(s)>
;* : -s <program start label> <C/C++ runtime library>
;*************************************************************************************
;* History:
;* 09/27/2005 : V1.0
;*************************************************************************************
; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
; OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
; OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
; CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*************************************************************************************/
// Code memory in flash
-DROMSTART=0x00000000
-DROMEND=0x00080000
-DVECSTART=ROMSTART
// Data memory
-DRAMSTART=0x4000000
-DRAMEND=0x04018000
//*************************************************************************
// In this file it is assumed that the system has the following
// memory layout:
//
// Exception vectors [0x000000--0x00001F] RAM or ROM
// ROMSTART--ROMEND [0x008000--0x0FFFFF] ROM (or other non-volatile memory)
// RAMSTART--RAMEND [0x100000--0x7FFFFF] RAM (or other read/write memory)
//
// -------------
// Code segments - may be placed anywhere in memory.
// -------------
//
// INTVEC -- Exception vector table.
// SWITAB -- Software interrupt vector table.
// ICODE -- Startup (cstartup) and exception code.
// DIFUNCT -- Dynamic initialization vectors used by C++.
// CODE -- Compiler generated code.
// CODE_I -- Compiler generated code declared __ramfunc (executes in RAM)
// CODE_ID -- Initializer for CODE_I (ROM).
//
// -------------
// Data segments - may be placed anywhere in memory.
// -------------
//
// CSTACK -- The stack used by C/C++ programs (system and user mode).
// IRQ_STACK -- The stack used by IRQ service routines.
// SVC_STACK -- The stack used in supervisor mode
// (Define other exception stacks as needed for
// FIQ, ABT, UND).
// HEAP -- The heap used by malloc and free in C and new and
// delete in C++.
// INITTAB -- Table containing addresses and sizes of segments that
// need to be initialized at startup (by cstartup).
// CHECKSUM -- The linker places checksum byte(s) in this segment,
// when the -J linker command line option is used.
// DATA_y -- Data objects.
//
// Where _y can be one of:
//
// _AN -- Holds uninitialized located objects, i.e. objects with
// an absolute location given by the @ operator or the
// #pragma location directive. Since these segments
// contain objects which already have a fixed address,
// they should not be mentioned in this linker command
// file.
// _C -- Constants (ROM).
// _I -- Initialized data (RAM).
// _ID -- The original content of _I (copied to _I by cstartup) (ROM).
// _N -- Uninitialized data (RAM).
// _Z -- Zero initialized data (RAM).
//
// Note: Be sure to use end values for the defined address ranges.
// Otherwise, the linker may allocate space outside the
// intended memory range.
//*************************************************************************
//************************************************
// Inform the linker about the CPU family used.
//************************************************
-carm
//*************************************************************************
// Segment placement - General information
//
// All numbers in the segment placement command lines below are interpreted
// as hexadecimal unless they are immediately preceded by a '.', which
// denotes decimal notation.
//
// When specifying the segment placement using the -P instead of the -Z
// option, the linker is free to split each segment into its segment parts
// and randomly place these parts within the given ranges in order to
// achieve a more efficient memory usage. One disadvantage, however, is
// that it is not possible to find the start or end address (using
// the assembler operators .sfb./.sfe.) of a segment which has been split
// and reformed.
//
// When generating an output file which is to be used for programming
// external ROM/Flash devices, the -M linker option is very useful
// (see xlink.pdf for details).
//*************************************************************************
//*************************************************************************
// Read-only segments mapped to ROM.
//*************************************************************************
//************************************************
// Address range for reset and exception
// vectors (INTVEC).
// The vector area is 32 bytes,
// an additional 32 bytes is allocated for the
// constant table used by ldr PC in cstartup.s79.
//************************************************
-Z(CODE)INTVEC=ROMSTART-ROMEND
//************************************************
// Startup code and exception routines (ICODE).
//************************************************
-Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND
-Z(CODE)SWITAB=ROMSTART-ROMEND
//************************************************
// Code segments may be placed anywhere.
//************************************************
-Z(CODE)CODE=ROMSTART-ROMEND
//************************************************
// Original ROM location for __ramfunc code copied
// to and executed from RAM.
//************************************************
-Z(CONST)CODE_ID=ROMSTART-ROMEND
//************************************************
// Various constants and initializers.
//************************************************
-Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND
-Z(CONST)CHECKSUM=ROMSTART-ROMEND
//*************************************************************************
// Read/write segments mapped to RAM.
//*************************************************************************
//************************************************
// Data segments.
//************************************************
-Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND
//************************************************
// __ramfunc code copied to and executed from RAM.
//************************************************
-Z(DATA)CODE_I=RAMSTART-RAMEND
//************************************************
// ICCARM produces code for __ramfunc functions in
// CODE_I segments. The -Q XLINK command line
// option redirects XLINK to emit the code in the
// CODE_ID segment instead, but to keep symbol and
// debug information associated with the CODE_I
// segment, where the code will execute.
//************************************************
-QCODE_I=CODE_ID
//*************************************************************************
// Stack and heap segments.
//*************************************************************************
//-D_CSTACK_SIZE=0x1000
//-D_SVC_STACK_SIZE=0x100
//-D_IRQ_STACK_SIZE=0x400
//-D_FIQ_STACK_SIZE=0x40
//-D_ABT_STACK_SIZE=0x40
//-D_UND_STACK_SIZE=0x40
//-D_HEAP_SIZE=0x400
//-Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND
//-Z(DATA)SVC_STACK+_SVC_STACK_SIZE=RAMSTART-RAMEND
//-Z(DATA)ABT_STACK+_ABT_STACK_SIZE=RAMSTART-RAMEND
//-Z(DATA)UND_STACK+_UND_STACK_SIZE=RAMSTART-RAMEND
//-Z(DATA)FIQ_STACK+_FIQ_STACK_SIZE=RAMSTART-RAMEND
//-Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE=RAMSTART-RAMEND
//-Z(DATA)HEAP+_HEAP_SIZE=RAMSTART-RAMEND
//*************************************************************************
// ELF/DWARF support.
//
// Uncomment the line "-Felf" below to generate ELF/DWARF output.
// Available format specifiers are:
//
// "-yn": Suppress DWARF debug output
// "-yp": Multiple ELF program sections
// "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag)
//
// "-Felf" and the format specifiers can also be supplied directly as
// command line options, or selected from the Xlink Output tab in the
// IAR Embedded Workbench.
//*************************************************************************
// -Felf

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/*
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
/*
NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
The processor MUST be in supervisor mode when vTaskStartScheduler is
called. The demo applications included in the FreeRTOS.org download switch
to supervisor mode prior to main being called. If you are not using one of
these demo application projects then ensure Supervisor mode is used.
*/
/*
* Creates all the demo application tasks, then starts the scheduler. The WEB
* documentation provides more details of the demo application tasks.
*
* A few tasks are created that are not part of the standard demo. These are
* the 'LCD' task, the 'LCD Message' task, a WEB server task and the 'Check'
* task.
*
* The LCD task is the only task that accesses the LCD directly, so mutual
* exclusion is ensured. Any task wishing to display text sends the LCD task
* a message containing a pointer to the string that should be displayed.
* The LCD task itself just blocks on a queue waiting for such a message to
* arrive - processing each in turn.
*
* The LCD Message task does nothing other than periodically send messages to
* the LCD task. The messages originating from the LCD Message task are
* displayed on the top row of the LCD.
*
* The Check task only executes every three seconds but has the highest
* priority so is guaranteed to get processor time. Its main function is to
* check that all the other tasks are still operational. Most tasks maintain
* a unique count that is incremented each time the task successfully completes
* a cycle of its function. Should any error occur within such a task the
* count is permanently halted. The check task sets a bit in an error status
* flag should it find any counter variable at a value that indicates an
* error has occurred. The error flag value is converted to a string and sent
* to the LCD task for display on the bottom row on the LCD.
*/
/* Standard includes. */
#include <stdio.h>
/* Library includes. */
#include "91x_lib.h"
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
/* Demo application includes. */
#include "lcd.h"
#include "flash.h"
#include "integer.h"
#include "PollQ.h"
#include "BlockQ.h"
#include "semtest.h"
#include "dynamic.h"
#include "partest.h"
#include "flop.h"
#include "comtest2.h"
#include "serial.h"
/* Priorities for the demo application tasks. */
#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 )
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 3 )
#define mainLCD_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainMSG_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
/* Delays used by the various tasks defined in this file. */
#define mainCHECK_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS )
#define mainSTRING_WRITE_DELAY ( 500 / portTICK_RATE_MS )
#define mainLCD_DELAY ( 20 / portTICK_RATE_MS )
/* Constants for the ComTest tasks. */
#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 )
#define mainCOM_TEST_LED ( 3 )
/* The maximum number of messages that can be pending to be written to the LCD. */
#define mainLCD_QUEUE_LEN ( 6 )
/* Dimension the buffer used to write the error flag string. */
#define mainMAX_FLAG_STRING_LEN ( 32 )
/* The structure that is passed on the LCD message queue. */
typedef struct
{
portCHAR **ppcMessageToDisplay; /*<< Points to a char* pointing to the message to display. */
portBASE_TYPE xRow; /*<< The row on which the message should be displayed. */
} xLCDMessage;
/*-----------------------------------------------------------*/
/*
* The task that executes at the highest priority and calls
* prvCheckOtherTasksAreStillRunning(). See the description at the top
* of the file.
*/
static void vErrorChecks( void *pvParameters );
/*
* Configure the processor clock and ports.
*/
static void prvSetupHardware( void );
/*
* Checks that all the demo application tasks are still executing without error
* - as described at the top of the file. Called by vErrorChecks().
*/
static void prvCheckOtherTasksAreStillRunning( void );
/*
* The WEB server task prototype. The task is created in this file but defined
* elsewhere.
*/
extern void vuIP_Task(void *pvParameters);
/*
* The task that displays text on the LCD.
*/
static void prvLCDTask( void * pvParameters );
/*
* The task that sends messages to be displayed on the top row of the LCD.
*/
static void prvLCDMessageTask( void * pvParameters );
/*-----------------------------------------------------------*/
/* The queue used to pass messages to the LCD task. */
static xQueueHandle xLCDQueue;
/* Error status flag. */
static unsigned portLONG ulErrorFlags = 0;
/*-----------------------------------------------------------*/
/*
* Starts all the other tasks, then starts the scheduler.
*/
void main( void )
{
#ifdef DEBUG
debug();
#endif
/* Setup any hardware that has not already been configured by the low
level init routines. */
prvSetupHardware();
/* Create the queue used to send data to the LCD task. */
xLCDQueue = xQueueCreate( mainLCD_QUEUE_LEN, sizeof( xLCDMessage ) );
/* Start all the standard demo application tasks. */
vStartIntegerMathTasks( tskIDLE_PRIORITY );
vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
vStartDynamicPriorityTasks();
vStartMathTasks( tskIDLE_PRIORITY );
vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );
/* Start the tasks which are defined in this file. */
xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
xTaskCreate( prvLCDTask, "LCD", configMINIMAL_STACK_SIZE, ( void * ) &xLCDQueue, mainLCD_TASK_PRIORITY, NULL );
xTaskCreate( prvLCDMessageTask, "MSG", configMINIMAL_STACK_SIZE, ( void * ) &xLCDQueue, mainMSG_TASK_PRIORITY, NULL );
/* Finally, create the WEB server task. */
xTaskCreate( vuIP_Task, "uIP", configMINIMAL_STACK_SIZE * 3, NULL, mainCHECK_TASK_PRIORITY - 1, NULL );
/* Start the scheduler.
NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
The processor MUST be in supervisor mode when vTaskStartScheduler is
called. The demo applications included in the FreeRTOS.org download switch
to supervisor mode prior to main being called. If you are not using one of
these demo application projects then ensure Supervisor mode is used here. */
vTaskStartScheduler();
/* We should never get here as control is now taken by the scheduler. */
for( ;; );
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
/* Configuration taken from the ST code.
Set Flash banks size & address */
FMI_BankRemapConfig( 4, 2, 0, 0x80000 );
/* FMI Waite States */
FMI_Config( FMI_READ_WAIT_STATE_2, FMI_WRITE_WAIT_STATE_0, FMI_PWD_ENABLE, FMI_LVD_ENABLE, FMI_FREQ_HIGH );
/* Configure the FPLL = 96MHz */
SCU_PLLFactorsConfig( 192, 25, 2 );
SCU_PLLCmd( ENABLE );
SCU_MCLKSourceConfig( SCU_MCLK_PLL );
WDG_Cmd( DISABLE );
VIC_DeInit();
/* GPIO8 clock source enable, used by the LCD. */
SCU_APBPeriphClockConfig(__GPIO8, ENABLE);
GPIO_DeInit(GPIO8);
/* GPIO 9 clock source enable, used by the LCD. */
SCU_APBPeriphClockConfig(__GPIO9, ENABLE);
GPIO_DeInit(GPIO9);
/* Enable VIC clock */
SCU_AHBPeriphClockConfig(__VIC, ENABLE);
SCU_AHBPeriphReset(__VIC, DISABLE);
/* Peripheral initialisation. */
LCD_Init();
vParTestInitialise();
}
/*-----------------------------------------------------------*/
static void vErrorChecks( void *pvParameters )
{
static portCHAR cCheckVal[ mainMAX_FLAG_STRING_LEN ];
portCHAR *pcFlagString;
xLCDMessage xMessageToSend;
portTickType xLastWakeTime;
portCHAR *pcStringsToDisplay[] = {
"Check status flag"
};
/* The parameters are not used in this task. */
( void ) pvParameters;
pcFlagString = &cCheckVal[ 0 ];
/* Initialise xLastWakeTime to ensure the first call to vTaskDelayUntil()
functions correctly. */
xLastWakeTime = xTaskGetTickCount();
/* Cycle for ever, delaying then checking all the other tasks are still
operating without error. */
for( ;; )
{
/* Delay until it is time to execute again. */
vTaskDelayUntil( &xLastWakeTime, mainCHECK_PERIOD );
/* Check all the other tasks to see if the error flag needs updating. */
prvCheckOtherTasksAreStillRunning();
/* Create a string indicating the error flag status. */
sprintf( cCheckVal, "equals 0x%x ", ulErrorFlags );
xMessageToSend.xRow = Line2;
/* Send the first part of the message to the LCD task. */
xMessageToSend.ppcMessageToDisplay = &pcStringsToDisplay[ 0 ];
xQueueSend( xLCDQueue, ( void * ) &xMessageToSend, 0 );
vTaskDelay( mainSTRING_WRITE_DELAY );
/* Send the second part of the message to the LCD task. */
xMessageToSend.ppcMessageToDisplay = &pcFlagString;
xQueueSend( xLCDQueue, ( void * ) &xMessageToSend, 0 );
}
}
/*-----------------------------------------------------------*/
static void prvCheckOtherTasksAreStillRunning( void )
{
if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
{
ulErrorFlags |= 0x01;
}
if( xArePollingQueuesStillRunning() != pdTRUE )
{
ulErrorFlags |= 0x02;
}
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
{
ulErrorFlags |= 0x04;
}
if( xAreBlockingQueuesStillRunning() != pdTRUE )
{
ulErrorFlags |= 0x08;
}
if( xAreComTestTasksStillRunning() != pdTRUE )
{
ulErrorFlags |= 0x10;
}
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
{
ulErrorFlags |= 0x20;
}
if( xAreMathsTaskStillRunning() != pdTRUE )
{
ulErrorFlags |= 0x40;
}
}
/*-----------------------------------------------------------*/
static void prvLCDMessageTask( void * pvParameters )
{
xQueueHandle *pxLCDQueue;
xLCDMessage xMessageToSend;
portBASE_TYPE xIndex = 0;
/* The strings that are written to the LCD. */
portCHAR *pcStringsToDisplay[] = {
"IAR ",
"STR912 ",
"Demo ",
"www.FreeRTOS.org",
""
};
/* To test the parameter passing mechanism, the queue on which messages are
posted is passed in as a parameter even though it is available as a file
scope variable anyway. */
pxLCDQueue = ( xQueueHandle * ) pvParameters;
for( ;; )
{
/* Wait until it is time to move onto the next string. */
vTaskDelay( mainSTRING_WRITE_DELAY );
/* Configure the message object to send to the LCD task. */
xMessageToSend.ppcMessageToDisplay = &pcStringsToDisplay[ xIndex ];
xMessageToSend.xRow = Line1;
/* Post the message to be displayed. */
xQueueSend( *pxLCDQueue, ( void * ) &xMessageToSend, 0 );
/* Move onto the next message, wrapping when necessary. */
xIndex++;
if( *( pcStringsToDisplay[ xIndex ] ) == 0x00 )
{
xIndex = 0;
/* Delay longer before going back to the start of the messages. */
vTaskDelay( mainSTRING_WRITE_DELAY * 2 );
}
}
}
/*-----------------------------------------------------------*/
void prvLCDTask( void * pvParameters )
{
xQueueHandle *pxLCDQueue;
xLCDMessage xReceivedMessage;
portCHAR *pcString;
/* To test the parameter passing mechanism, the queue on which messages are
received is passed in as a parameter even though it is available as a file
scope variable anyway. */
pxLCDQueue = ( xQueueHandle * ) pvParameters;
for( ;; )
{
/* Wait for a message to arrive. */
if( xQueueReceive( *pxLCDQueue, &xReceivedMessage, portMAX_DELAY ) )
{
/* Where is the string we are going to display? */
pcString = *xReceivedMessage.ppcMessageToDisplay;
LCD_DisplayString(xReceivedMessage.xRow, pcString, BlackText);
/* The delay here is just to ensure the LCD task does not starve
out lower priority tasks as writhing to the LCD can take a long
time. */
vTaskDelay( mainLCD_DELAY );
}
}
}
/*-----------------------------------------------------------*/

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Demo/ARM9_STR91X_IAR/serial/serial.c
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/*
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
/*
BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART1.
*/
/* Library includes. */
#include "91x_lib.h"
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "queue.h"
#include "semphr.h"
/* Demo application includes. */
#include "serial.h"
/*-----------------------------------------------------------*/
/* Misc defines. */
#define serINVALID_QUEUE ( ( xQueueHandle ) 0 )
#define serNO_BLOCK ( ( portTickType ) 0 )
#define serTX_BLOCK_TIME ( 40 / portTICK_RATE_MS )
/* Interrupt and status bit definitions. */
#define mainTXRIS 0x20
#define mainRXRIS 0x50
#define serTX_FIFO_FULL 0x20
#define serCLEAR_ALL_INTERRUPTS 0x3ff
/*-----------------------------------------------------------*/
/* The queue used to hold received characters. */
static xQueueHandle xRxedChars;
/* The semaphore used to wake a task waiting for space to become available
in the FIFO. */
static xSemaphoreHandle xTxFIFOSemaphore;
/*-----------------------------------------------------------*/
/* UART interrupt handler. */
void UART1_IRQHandler( void );
/* The interrupt service routine - called from the assembly entry point. */
__arm void UART1_IRQHandler( void );
/*-----------------------------------------------------------*/
/* Flag to indicate whether or not a task is blocked waiting for space on
the FIFO. */
static portLONG lTaskWaiting = pdFALSE;
/*
* See the serial2.h header file.
*/
xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
{
xComPortHandle xReturn;
UART_InitTypeDef xUART1_Init;
GPIO_InitTypeDef GPIO_InitStructure;
/* Create the queues used to hold Rx characters. */
xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
/* Create the semaphore used to wake a task waiting for space to become
available in the FIFO. */
vSemaphoreCreateBinary( xTxFIFOSemaphore );
/* If the queue/semaphore was created correctly then setup the serial port
hardware. */
if( ( xRxedChars != serINVALID_QUEUE ) && ( xTxFIFOSemaphore != serINVALID_QUEUE ) )
{
/* Pre take the semaphore so a task will block if it tries to access
it. */
xSemaphoreTake( xTxFIFOSemaphore, 0 );
/* Configure the UART. */
xUART1_Init.UART_WordLength = UART_WordLength_8D;
xUART1_Init.UART_StopBits = UART_StopBits_1;
xUART1_Init.UART_Parity = UART_Parity_No;
xUART1_Init.UART_BaudRate = ulWantedBaud;
xUART1_Init.UART_HardwareFlowControl = UART_HardwareFlowControl_None;
xUART1_Init.UART_Mode = UART_Mode_Tx_Rx;
xUART1_Init.UART_FIFO = UART_FIFO_Enable;
/* Enable the UART1 Clock */
SCU_APBPeriphClockConfig( __UART1, ENABLE );
/* Enable the GPIO3 Clock */
SCU_APBPeriphClockConfig( __GPIO3, ENABLE );
/* Configure UART1_Rx pin GPIO3.2 */
GPIO_InitStructure.GPIO_Direction = GPIO_PinInput;
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull ;
GPIO_InitStructure.GPIO_IPConnected = GPIO_IPConnected_Enable;
GPIO_InitStructure.GPIO_Alternate = GPIO_InputAlt1 ;
GPIO_Init( GPIO3, &GPIO_InitStructure );
/* Configure UART1_Tx pin GPIO3.3 */
GPIO_InitStructure.GPIO_Direction = GPIO_PinOutput;
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3;
GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull ;
GPIO_InitStructure.GPIO_IPConnected = GPIO_IPConnected_Enable;
GPIO_InitStructure.GPIO_Alternate = GPIO_OutputAlt2 ;
GPIO_Init( GPIO3, &GPIO_InitStructure );
portENTER_CRITICAL();
{
/* Configure the UART itself. */
UART_DeInit( UART1 );
UART_Init( UART1, &xUART1_Init );
UART_ITConfig( UART1, UART_IT_Receive | UART_IT_Transmit, ENABLE );
UART1->ICR = serCLEAR_ALL_INTERRUPTS;
UART_LoopBackConfig( UART1, DISABLE );
UART_IrDACmd( IrDA1, DISABLE );
/* Configure the VIC for the UART interrupts. */
VIC_Config( UART1_ITLine, VIC_IRQ, 9 );
VIC_ITCmd( UART1_ITLine, ENABLE );
UART_Cmd( UART1, ENABLE );
lTaskWaiting = pdFALSE;
}
portEXIT_CRITICAL();
}
else
{
xReturn = ( xComPortHandle ) 0;
}
/* This demo file only supports a single port but we have to return
something to comply with the standard demo header file. */
return xReturn;
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )
{
/* The port handle is not required as this driver only supports one port. */
( void ) pxPort;
/* Get the next character from the buffer. Return false if no characters
are available, or arrive before xBlockTime expires. */
if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
{
return pdTRUE;
}
else
{
return pdFALSE;
}
}
/*-----------------------------------------------------------*/
void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength )
{
signed portCHAR *pxNext;
/* A couple of parameters that this port does not use. */
( void ) usStringLength;
( void ) pxPort;
/* NOTE: This implementation does not handle the queue being full as no
block time is used! */
/* The port handle is not required as this driver only supports UART1. */
( void ) pxPort;
/* Send each character in the string, one at a time. */
pxNext = ( signed portCHAR * ) pcString;
while( *pxNext )
{
xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );
pxNext++;
}
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )
{
portBASE_TYPE xReturn;
portENTER_CRITICAL();
{
/* Can we write to the FIFO? */
if( UART1->FR & serTX_FIFO_FULL )
{
/* Wait for the interrupt letting us know there is space on the
FIFO. It is ok to block in a critical section, interrupts will be
enabled for other tasks once we force a switch. */
lTaskWaiting = pdTRUE;
/* Just to be a bit different this driver uses a semaphore to
block the sending task when the FIFO is full. The standard COMTest
task assumes a queue of adequate length exists so does not use
a block time. For this demo the block time is therefore hard
coded. */
xReturn = xSemaphoreTake( xTxFIFOSemaphore, serTX_BLOCK_TIME );
if( xReturn )
{
UART1->DR = cOutChar;
}
}
else
{
UART1->DR = cOutChar;
xReturn = pdPASS;
}
}
portEXIT_CRITICAL();
return xReturn;
}
/*-----------------------------------------------------------*/
void vSerialClose( xComPortHandle xPort )
{
/* Not supported as not required by the demo application. */
}
/*-----------------------------------------------------------*/
void UART1_IRQHandler( void )
{
signed portCHAR cChar;
portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByPost = pdFALSE;
while( UART1->RIS & mainRXRIS )
{
/* The interrupt was caused by a character being received. Grab the
character from the DR and place it in the queue of received
characters. */
cChar = UART1->DR;
xTaskWokenByPost = xQueueSendFromISR( xRxedChars, &cChar, xTaskWokenByPost );
}
if( UART1->RIS & mainTXRIS )
{
if( lTaskWaiting == pdTRUE )
{
/* This interrupt was caused by space becoming available on the Tx
FIFO, wake any task that is waiting to post (if any). */
xTaskWokenByTx = xSemaphoreGiveFromISR( xTxFIFOSemaphore, xTaskWokenByTx );
lTaskWaiting = pdFALSE;
}
UART1->ICR = mainTXRIS;
}
/* If a task was woken by either a character being received or a character
being transmitted then we may need to switch to another task. */
portEND_SWITCHING_ISR( ( xTaskWokenByPost || xTaskWokenByTx ) );
}

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<?xml version="1.0" encoding="iso-8859-1"?>
<Workspace>
<ConfigDictionary>
<CurrentConfigs><Project>RTOSDemo/Debug</Project></CurrentConfigs></ConfigDictionary>
<Desktop>
<Static>
<Workspace>
<ColumnWidths>
<Column0>208</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
</Workspace>
<Build>
<PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1004</ColumnWidth1><ColumnWidth2>267</ColumnWidth2><ColumnWidth3>66</ColumnWidth3></Build>
<TerminalIO/>
<Debug-Log><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows><Window><Factory>Build</Factory></Window><Window><Factory>Find-in-Files</Factory></Window><Window><Factory>Breakpoints</Factory></Window></Windows></PreferedWindows></Debug-Log>
<Find-in-Files>
<PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows><Window><Factory>Build</Factory></Window><Window><Factory>Debug-Log</Factory></Window><Window><Factory>Breakpoints</Factory></Window></Windows></PreferedWindows><ColumnWidth0>482</ColumnWidth0><ColumnWidth1>68</ColumnWidth1><ColumnWidth2>826</ColumnWidth2></Find-in-Files>
<Disassembly><MixedMode>1</MixedMode><CodeCovEnabled>0</CodeCovEnabled><CodeCovShow>0</CodeCovShow></Disassembly><Breakpoints><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows><Window><Factory>Build</Factory></Window><Window><Factory>Find-in-Files</Factory></Window><Window><Factory>Debug-Log</Factory></Window></Windows></PreferedWindows></Breakpoints></Static>
<Windows>
<Wnd2>
<Tabs>
<Tab>
<Identity>TabID-19472-27051</Identity>
<TabName>Workspace</TabName>
<Factory>Workspace</Factory>
<Session>
<NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/Demo Source</ExpandedNode></NodeDict></Session>
</Tab>
</Tabs>
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Demo/ARM9_STR91X_IAR/webserver/Makefile.webserver
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APP_SOURCES += httpd.c http-strings.c httpd-fs.c httpd-cgi.c

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Demo/ARM9_STR91X_IAR/webserver/clock-arch.h
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/*
* Copyright (c) 2006, Swedish Institute of Computer Science.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the Institute nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* This file is part of the uIP TCP/IP stack
*
* $Id: clock-arch.h,v 1.2 2006/06/12 08:00:31 adam Exp $
*/
#ifndef __CLOCK_ARCH_H__
#define __CLOCK_ARCH_H__
#include "FreeRTOS.h"
typedef unsigned long clock_time_t;
#define CLOCK_CONF_SECOND configTICK_RATE_HZ
#endif /* __CLOCK_ARCH_H__ */

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Demo/ARM9_STR91X_IAR/webserver/http-strings
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http_http "http://"
http_200 "200 "
http_301 "301 "
http_302 "302 "
http_get "GET "
http_10 "HTTP/1.0"
http_11 "HTTP/1.1"
http_content_type "content-type: "
http_texthtml "text/html"
http_location "location: "
http_host "host: "
http_crnl "\r\n"
http_index_html "/index.html"
http_404_html "/404.html"
http_referer "Referer:"
http_header_200 "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n"
http_header_404 "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n"
http_content_type_plain "Content-type: text/plain\r\n\r\n"
http_content_type_html "Content-type: text/html\r\n\r\n"
http_content_type_css "Content-type: text/css\r\n\r\n"
http_content_type_text "Content-type: text/text\r\n\r\n"
http_content_type_png "Content-type: image/png\r\n\r\n"
http_content_type_gif "Content-type: image/gif\r\n\r\n"
http_content_type_jpg "Content-type: image/jpeg\r\n\r\n"
http_content_type_binary "Content-type: application/octet-stream\r\n\r\n"
http_html ".html"
http_shtml ".shtml"
http_htm ".htm"
http_css ".css"
http_png ".png"
http_gif ".gif"
http_jpg ".jpg"
http_text ".txt"
http_txt ".txt"

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Demo/ARM9_STR91X_IAR/webserver/http-strings.c
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const char http_http[8] =
/* "http://" */
{0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, };
const char http_200[5] =
/* "200 " */
{0x32, 0x30, 0x30, 0x20, };
const char http_301[5] =
/* "301 " */
{0x33, 0x30, 0x31, 0x20, };
const char http_302[5] =
/* "302 " */
{0x33, 0x30, 0x32, 0x20, };
const char http_get[5] =
/* "GET " */
{0x47, 0x45, 0x54, 0x20, };
const char http_10[9] =
/* "HTTP/1.0" */
{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, };
const char http_11[9] =
/* "HTTP/1.1" */
{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x31, };
const char http_content_type[15] =
/* "content-type: " */
{0x63, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, };
const char http_texthtml[10] =
/* "text/html" */
{0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, };
const char http_location[11] =
/* "location: " */
{0x6c, 0x6f, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, };
const char http_host[7] =
/* "host: " */
{0x68, 0x6f, 0x73, 0x74, 0x3a, 0x20, };
const char http_crnl[3] =
/* "\r\n" */
{0xd, 0xa, };
const char http_index_html[12] =
/* "/index.html" */
{0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, };
const char http_404_html[10] =
/* "/404.html" */
{0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, };
const char http_referer[9] =
/* "Referer:" */
{0x52, 0x65, 0x66, 0x65, 0x72, 0x65, 0x72, 0x3a, };
const char http_header_200[84] =
/* "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */
{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32, 0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, };
const char http_header_404[91] =
/* "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */
{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x34, 0x30, 0x34, 0x20, 0x4e, 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, };
const char http_content_type_plain[29] =
/* "Content-type: text/plain\r\n\r\n" */
{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x70, 0x6c, 0x61, 0x69, 0x6e, 0xd, 0xa, 0xd, 0xa, };
const char http_content_type_html[28] =
/* "Content-type: text/html\r\n\r\n" */
{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0xd, 0xa, 0xd, 0xa, };
const char http_content_type_css [27] =
/* "Content-type: text/css\r\n\r\n" */
{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x63, 0x73, 0x73, 0xd, 0xa, 0xd, 0xa, };
const char http_content_type_text[28] =
/* "Content-type: text/text\r\n\r\n" */
{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x74, 0x65, 0x78, 0x74, 0xd, 0xa, 0xd, 0xa, };
const char http_content_type_png [28] =
/* "Content-type: image/png\r\n\r\n" */
{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x70, 0x6e, 0x67, 0xd, 0xa, 0xd, 0xa, };
const char http_content_type_gif [28] =
/* "Content-type: image/gif\r\n\r\n" */
{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x67, 0x69, 0x66, 0xd, 0xa, 0xd, 0xa, };
const char http_content_type_jpg [29] =
/* "Content-type: image/jpeg\r\n\r\n" */
{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x6a, 0x70, 0x65, 0x67, 0xd, 0xa, 0xd, 0xa, };
const char http_content_type_binary[43] =
/* "Content-type: application/octet-stream\r\n\r\n" */
{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x6f, 0x63, 0x74, 0x65, 0x74, 0x2d, 0x73, 0x74, 0x72, 0x65, 0x61, 0x6d, 0xd, 0xa, 0xd, 0xa, };
const char http_html[6] =
/* ".html" */
{0x2e, 0x68, 0x74, 0x6d, 0x6c, };
const char http_shtml[7] =
/* ".shtml" */
{0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, };
const char http_htm[5] =
/* ".htm" */
{0x2e, 0x68, 0x74, 0x6d, };
const char http_css[5] =
/* ".css" */
{0x2e, 0x63, 0x73, 0x73, };
const char http_png[5] =
/* ".png" */
{0x2e, 0x70, 0x6e, 0x67, };
const char http_gif[5] =
/* ".gif" */
{0x2e, 0x67, 0x69, 0x66, };
const char http_jpg[5] =
/* ".jpg" */
{0x2e, 0x6a, 0x70, 0x67, };
const char http_text[5] =
/* ".txt" */
{0x2e, 0x74, 0x78, 0x74, };
const char http_txt[5] =
/* ".txt" */
{0x2e, 0x74, 0x78, 0x74, };

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Demo/ARM9_STR91X_IAR/webserver/http-strings.h
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extern const char http_http[8];
extern const char http_200[5];
extern const char http_301[5];
extern const char http_302[5];
extern const char http_get[5];
extern const char http_10[9];
extern const char http_11[9];
extern const char http_content_type[15];
extern const char http_texthtml[10];
extern const char http_location[11];
extern const char http_host[7];
extern const char http_crnl[3];
extern const char http_index_html[12];
extern const char http_404_html[10];
extern const char http_referer[9];
extern const char http_header_200[84];
extern const char http_header_404[91];
extern const char http_content_type_plain[29];
extern const char http_content_type_html[28];
extern const char http_content_type_css [27];
extern const char http_content_type_text[28];
extern const char http_content_type_png [28];
extern const char http_content_type_gif [28];
extern const char http_content_type_jpg [29];
extern const char http_content_type_binary[43];
extern const char http_html[6];
extern const char http_shtml[7];
extern const char http_htm[5];
extern const char http_css[5];
extern const char http_png[5];
extern const char http_gif[5];
extern const char http_jpg[5];
extern const char http_text[5];
extern const char http_txt[5];

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/**
* \addtogroup httpd
* @{
*/
/**
* \file
* Web server script interface
* \author
* Adam Dunkels <adam@sics.se>
*
*/
/*
* Copyright (c) 2001-2006, Adam Dunkels.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote
* products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* This file is part of the uIP TCP/IP stack.
*
* $Id: httpd-cgi.c,v 1.2 2006/06/11 21:46:37 adam Exp $
*
*/
#include "uip.h"
#include "psock.h"
#include "httpd.h"
#include "httpd-cgi.h"
#include "httpd-fs.h"
#include <stdio.h>
#include <string.h>
HTTPD_CGI_CALL(file, "file-stats", file_stats);
HTTPD_CGI_CALL(tcp, "tcp-connections", tcp_stats);
HTTPD_CGI_CALL(net, "net-stats", net_stats);
HTTPD_CGI_CALL(rtos, "rtos-stats", rtos_stats );
static const struct httpd_cgi_call *calls[] = { &file, &tcp, &net, &rtos, NULL };
/*---------------------------------------------------------------------------*/
static
PT_THREAD(nullfunction(struct httpd_state *s, char *ptr))
{
PSOCK_BEGIN(&s->sout);
PSOCK_END(&s->sout);
}
/*---------------------------------------------------------------------------*/
httpd_cgifunction
httpd_cgi(char *name)
{
const struct httpd_cgi_call **f;
/* Find the matching name in the table, return the function. */
for(f = calls; *f != NULL; ++f) {
if(strncmp((*f)->name, name, strlen((*f)->name)) == 0) {
return (*f)->function;
}
}
return nullfunction;
}
/*---------------------------------------------------------------------------*/
static unsigned short
generate_file_stats(void *arg)
{
char *f = (char *)arg;
return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, "%5u", httpd_fs_count(f));
}
/*---------------------------------------------------------------------------*/
static
PT_THREAD(file_stats(struct httpd_state *s, char *ptr))
{
PSOCK_BEGIN(&s->sout);
PSOCK_GENERATOR_SEND(&s->sout, generate_file_stats, strchr(ptr, ' ') + 1);
PSOCK_END(&s->sout);
}
/*---------------------------------------------------------------------------*/
static const char closed[] = /* "CLOSED",*/
{0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0};
static const char syn_rcvd[] = /* "SYN-RCVD",*/
{0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56,
0x44, 0};
static const char syn_sent[] = /* "SYN-SENT",*/
{0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e,
0x54, 0};
static const char established[] = /* "ESTABLISHED",*/
{0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48,
0x45, 0x44, 0};
static const char fin_wait_1[] = /* "FIN-WAIT-1",*/
{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49,
0x54, 0x2d, 0x31, 0};
static const char fin_wait_2[] = /* "FIN-WAIT-2",*/
{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49,
0x54, 0x2d, 0x32, 0};
static const char closing[] = /* "CLOSING",*/
{0x43, 0x4c, 0x4f, 0x53, 0x49,
0x4e, 0x47, 0};
static const char time_wait[] = /* "TIME-WAIT,"*/
{0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41,
0x49, 0x54, 0};
static const char last_ack[] = /* "LAST-ACK"*/
{0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43,
0x4b, 0};
static const char *states[] = {
closed,
syn_rcvd,
syn_sent,
established,
fin_wait_1,
fin_wait_2,
closing,
time_wait,
last_ack};
static unsigned short
generate_tcp_stats(void *arg)
{
struct uip_conn *conn;
struct httpd_state *s = (struct httpd_state *)arg;
conn = &uip_conns[s->count];
return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE,
"<tr><td>%d</td><td>%u.%u.%u.%u:%u</td><td>%s</td><td>%u</td><td>%u</td><td>%c %c</td></tr>\r\n",
htons(conn->lport),
htons(conn->ripaddr[0]) >> 8,
htons(conn->ripaddr[0]) & 0xff,
htons(conn->ripaddr[1]) >> 8,
htons(conn->ripaddr[1]) & 0xff,
htons(conn->rport),
states[conn->tcpstateflags & UIP_TS_MASK],
conn->nrtx,
conn->timer,
(uip_outstanding(conn))? '*':' ',
(uip_stopped(conn))? '!':' ');
}
/*---------------------------------------------------------------------------*/
static
PT_THREAD(tcp_stats(struct httpd_state *s, char *ptr))
{
PSOCK_BEGIN(&s->sout);
for(s->count = 0; s->count < UIP_CONNS; ++s->count) {
if((uip_conns[s->count].tcpstateflags & UIP_TS_MASK) != UIP_CLOSED) {
PSOCK_GENERATOR_SEND(&s->sout, generate_tcp_stats, s);
}
}
PSOCK_END(&s->sout);
}
/*---------------------------------------------------------------------------*/
static unsigned short
generate_net_stats(void *arg)
{
struct httpd_state *s = (struct httpd_state *)arg;
return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE,
"%5u\n", ((uip_stats_t *)&uip_stat)[s->count]);
}
static
PT_THREAD(net_stats(struct httpd_state *s, char *ptr))
{
PSOCK_BEGIN(&s->sout);
#if UIP_STATISTICS
for(s->count = 0; s->count < sizeof(uip_stat) / sizeof(uip_stats_t);
++s->count) {
PSOCK_GENERATOR_SEND(&s->sout, generate_net_stats, s);
}
#endif /* UIP_STATISTICS */
PSOCK_END(&s->sout);
}
/*---------------------------------------------------------------------------*/
extern void vTaskList( signed char *pcWriteBuffer );
static char cCountBuf[ 32 ];
long lRefreshCount = 0;
static unsigned short
generate_rtos_stats(void *arg)
{
lRefreshCount++;
sprintf( cCountBuf, "<p><br>Refresh count = %d", lRefreshCount );
vTaskList( uip_appdata );
strcat( uip_appdata, cCountBuf );
return strlen( uip_appdata );
}
/*---------------------------------------------------------------------------*/
static
PT_THREAD(rtos_stats(struct httpd_state *s, char *ptr))
{
PSOCK_BEGIN(&s->sout);
// for( s->count = 0; s->count < 4; ++s->count )
// {
PSOCK_GENERATOR_SEND(&s->sout, generate_rtos_stats, NULL);
// }
PSOCK_END(&s->sout);
}
/** @} */

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/**
* \addtogroup httpd
* @{
*/
/**
* \file
* Web server script interface header file
* \author
* Adam Dunkels <adam@sics.se>
*
*/
/*
* Copyright (c) 2001, Adam Dunkels.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote
* products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* This file is part of the uIP TCP/IP stack.
*
* $Id: httpd-cgi.h,v 1.2 2006/06/11 21:46:38 adam Exp $
*
*/
#ifndef __HTTPD_CGI_H__
#define __HTTPD_CGI_H__
#include "psock.h"
#include "httpd.h"
typedef PT_THREAD((* httpd_cgifunction)(struct httpd_state *, char *));
httpd_cgifunction httpd_cgi(char *name);
struct httpd_cgi_call {
const char *name;
const httpd_cgifunction function;
};
/**
* \brief HTTPD CGI function declaration
* \param name The C variable name of the function
* \param str The string name of the function, used in the script file
* \param function A pointer to the function that implements it
*
* This macro is used for declaring a HTTPD CGI
* function. This function is then added to the list of
* HTTPD CGI functions with the httpd_cgi_add() function.
*
* \hideinitializer
*/
#define HTTPD_CGI_CALL(name, str, function) \
static PT_THREAD(function(struct httpd_state *, char *)); \
static const struct httpd_cgi_call name = {str, function}
void httpd_cgi_init(void);
#endif /* __HTTPD_CGI_H__ */
/** @} */

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/*
* Copyright (c) 2001, Swedish Institute of Computer Science.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the Institute nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* This file is part of the lwIP TCP/IP stack.
*
* Author: Adam Dunkels <adam@sics.se>
*
* $Id: httpd-fs.c,v 1.1 2006/06/07 09:13:08 adam Exp $
*/
#include "httpd.h"
#include "httpd-fs.h"
#include "httpd-fsdata.h"
#ifndef NULL
#define NULL 0
#endif /* NULL */
#include "httpd-fsdata.c"
#if HTTPD_FS_STATISTICS
static u16_t count[HTTPD_FS_NUMFILES];
#endif /* HTTPD_FS_STATISTICS */
/*-----------------------------------------------------------------------------------*/
static u8_t
httpd_fs_strcmp(const char *str1, const char *str2)
{
u8_t i;
i = 0;
loop:
if(str2[i] == 0 ||
str1[i] == '\r' ||
str1[i] == '\n') {
return 0;
}
if(str1[i] != str2[i]) {
return 1;
}
++i;
goto loop;
}
/*-----------------------------------------------------------------------------------*/
int
httpd_fs_open(const char *name, struct httpd_fs_file *file)
{
#if HTTPD_FS_STATISTICS
u16_t i = 0;
#endif /* HTTPD_FS_STATISTICS */
struct httpd_fsdata_file_noconst *f;
for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT;
f != NULL;
f = (struct httpd_fsdata_file_noconst *)f->next) {
if(httpd_fs_strcmp(name, f->name) == 0) {
file->data = f->data;
file->len = f->len;
#if HTTPD_FS_STATISTICS
++count[i];
#endif /* HTTPD_FS_STATISTICS */
return 1;
}
#if HTTPD_FS_STATISTICS
++i;
#endif /* HTTPD_FS_STATISTICS */
}
return 0;
}
/*-----------------------------------------------------------------------------------*/
void
httpd_fs_init(void)
{
#if HTTPD_FS_STATISTICS
u16_t i;
for(i = 0; i < HTTPD_FS_NUMFILES; i++) {
count[i] = 0;
}
#endif /* HTTPD_FS_STATISTICS */
}
/*-----------------------------------------------------------------------------------*/
#if HTTPD_FS_STATISTICS
u16_t httpd_fs_count
(char *name)
{
struct httpd_fsdata_file_noconst *f;
u16_t i;
i = 0;
for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT;
f != NULL;
f = (struct httpd_fsdata_file_noconst *)f->next) {
if(httpd_fs_strcmp(name, f->name) == 0) {
return count[i];
}
++i;
}
return 0;
}
#endif /* HTTPD_FS_STATISTICS */
/*-----------------------------------------------------------------------------------*/

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/*
* Copyright (c) 2001, Swedish Institute of Computer Science.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the Institute nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* This file is part of the lwIP TCP/IP stack.
*
* Author: Adam Dunkels <adam@sics.se>
*
* $Id: httpd-fs.h,v 1.1 2006/06/07 09:13:08 adam Exp $
*/
#ifndef __HTTPD_FS_H__
#define __HTTPD_FS_H__
#define HTTPD_FS_STATISTICS 1
struct httpd_fs_file {
char *data;
int len;
};
/* file must be allocated by caller and will be filled in
by the function. */
int httpd_fs_open(const char *name, struct httpd_fs_file *file);
#ifdef HTTPD_FS_STATISTICS
#if HTTPD_FS_STATISTICS == 1
u16_t httpd_fs_count(char *name);
#endif /* HTTPD_FS_STATISTICS */
#endif /* HTTPD_FS_STATISTICS */
void httpd_fs_init(void);
#endif /* __HTTPD_FS_H__ */

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<html>
<body bgcolor="white">
<center>
<h1>404 - file not found</h1>
<h3>Go <a href="/">here</a> instead.</h3>
</center>
</body>
</html>

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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html>
<head>
<title>FreeRTOS.org uIP WEB server demo</title>
</head>
<BODY onLoad="window.setTimeout(&quot;location.href='index.shtml'&quot;,100)"bgcolor="#CCCCff">
<font face="arial">
Loading index.shtml. Click <a href="index.shtml">here</a> if not automatically redirected.
</font>
</font>
</body>
</html>

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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html>
<head>
<title>FreeRTOS.org uIP WEB server demo</title>
</head>
<BODY onLoad="window.setTimeout(&quot;location.href='index.shtml'&quot;,2000)"bgcolor="#CCCCff">
<font face="arial">
<a href="index.shtml">RTOS Stats</a> <b>|</b> <a href="stats.shtml">TCP Stats</a> <b>|</b> <a href="tcp.shtml">Connections</a> <b>|</b> <a href="http://www.freertos.org/">FreeRTOS.org Homepage</a>
<br><p>
<hr>
<br><p>
<h2>Task statistics</h2>
Page will refresh evey 2 seconds.<p>
<font face="courier"><pre>Task State Priority Stack #<br>************************************************<br>
%! rtos-stats
</pre></font>
</font>
</body>
</html>

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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html>
<head>
<title>FreeRTOS.org uIP WEB server demo</title>
</head>
<BODY bgcolor="#CCCCff">
<font face="arial">
<a href="index.shtml">RTOS Stats</a> <b>|</b> <a href="stats.shtml">TCP Stats</a> <b>|</b> <a href="tcp.shtml">Connections</a> <b>|</b> <a href="http://www.freertos.org/">FreeRTOS.org Homepage</a>
<br><p>
<hr>
<br><p>
<h2>Network statistics</h2>
<table width="300" border="0">
<tr><td align="left"><font face="courier"><pre>
IP Packets dropped
Packets received
Packets sent
IP errors IP version/header length
IP length, high byte
IP length, low byte
IP fragments
Header checksum
Wrong protocol
ICMP Packets dropped
Packets received
Packets sent
Type errors
TCP Packets dropped
Packets received
Packets sent
Checksum errors
Data packets without ACKs
Resets
Retransmissions
No connection avaliable
Connection attempts to closed ports
</pre></font></td><td><pre>%! net-stats
</pre></table>
</font>
</body>
</html>

21
Demo/ARM9_STR91X_IAR/webserver/httpd-fs/tcp.shtml
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html>
<head>
<title>FreeRTOS.org uIP WEB server demo</title>
</head>
<BODY bgcolor="#CCCCff">
<font face="arial">
<a href="index.shtml">RTOS Stats</a> <b>|</b> <a href="stats.shtml">TCP Stats</a> <b>|</b> <a href="tcp.shtml">Connections</a> <b>|</b> <a href="http://www.freertos.org/">FreeRTOS.org Homepage</a>
<br><p>
<hr>
<br>
<h2>Network connections</h2>
<p>
<table>
<tr><th>Local</th><th>Remote</th><th>State</th><th>Retransmissions</th><th>Timer</th><th>Flags</th></tr>
%! tcp-connections
</pre></font>
</font>
</body>
</html>

363
Demo/ARM9_STR91X_IAR/webserver/httpd-fsdata.c
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static const unsigned char data_tcp_shtml[] = {
/* /tcp.shtml */
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const struct httpd_fsdata_file file_404_html[] = {{NULL, data_404_html, data_404_html + 10, sizeof(data_404_html) - 10}};
const struct httpd_fsdata_file file_index_html[] = {{file_404_html, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12}};
const struct httpd_fsdata_file file_index_shtml[] = {{file_index_html, data_index_shtml, data_index_shtml + 13, sizeof(data_index_shtml) - 13}};
const struct httpd_fsdata_file file_stats_shtml[] = {{file_index_shtml, data_stats_shtml, data_stats_shtml + 13, sizeof(data_stats_shtml) - 13}};
const struct httpd_fsdata_file file_tcp_shtml[] = {{file_stats_shtml, data_tcp_shtml, data_tcp_shtml + 11, sizeof(data_tcp_shtml) - 11}};
#define HTTPD_FS_ROOT file_tcp_shtml
#define HTTPD_FS_NUMFILES 5

64
Demo/ARM9_STR91X_IAR/webserver/httpd-fsdata.h
Unescape Escape View File

@ -0,0 +1,64 @@
/*
* Copyright (c) 2001, Swedish Institute of Computer Science.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the Institute nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* This file is part of the lwIP TCP/IP stack.
*
* Author: Adam Dunkels <adam@sics.se>
*
* $Id: httpd-fsdata.h,v 1.1 2006/06/07 09:13:08 adam Exp $
*/
#ifndef __HTTPD_FSDATA_H__
#define __HTTPD_FSDATA_H__
#include "uip.h"
struct httpd_fsdata_file {
const struct httpd_fsdata_file *next;
const char *name;
const char *data;
const int len;
#ifdef HTTPD_FS_STATISTICS
#if HTTPD_FS_STATISTICS == 1
u16_t count;
#endif /* HTTPD_FS_STATISTICS */
#endif /* HTTPD_FS_STATISTICS */
};
struct httpd_fsdata_file_noconst {
struct httpd_fsdata_file *next;
char *name;
char *data;
int len;
#ifdef HTTPD_FS_STATISTICS
#if HTTPD_FS_STATISTICS == 1
u16_t count;
#endif /* HTTPD_FS_STATISTICS */
#endif /* HTTPD_FS_STATISTICS */
};
#endif /* __HTTPD_FSDATA_H__ */

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Demo/ARM9_STR91X_IAR/webserver/httpd.c
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/**
* \addtogroup apps
* @{
*/
/**
* \defgroup httpd Web server
* @{
* The uIP web server is a very simplistic implementation of an HTTP
* server. It can serve web pages and files from a read-only ROM
* filesystem, and provides a very small scripting language.
*/
/**
* \file
* Web server
* \author
* Adam Dunkels <adam@sics.se>
*/
/*
* Copyright (c) 2004, Adam Dunkels.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the Institute nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* This file is part of the uIP TCP/IP stack.
*
* Author: Adam Dunkels <adam@sics.se>
*
* $Id: httpd.c,v 1.2 2006/06/11 21:46:38 adam Exp $
*/
#include "uip.h"
#include "httpd.h"
#include "httpd-fs.h"
#include "httpd-cgi.h"
#include "http-strings.h"
#include <string.h>
#define STATE_WAITING 0
#define STATE_OUTPUT 1
#define ISO_nl 0x0a
#define ISO_space 0x20
#define ISO_bang 0x21
#define ISO_percent 0x25
#define ISO_period 0x2e
#define ISO_slash 0x2f
#define ISO_colon 0x3a
/*---------------------------------------------------------------------------*/
static unsigned short
generate_part_of_file(void *state)
{
struct httpd_state *s = (struct httpd_state *)state;
if(s->file.len > uip_mss()) {
s->len = uip_mss();
} else {
s->len = s->file.len;
}
memcpy(uip_appdata, s->file.data, s->len);
return s->len;
}
/*---------------------------------------------------------------------------*/
static
PT_THREAD(send_file(struct httpd_state *s))
{
PSOCK_BEGIN(&s->sout);
do {
PSOCK_GENERATOR_SEND(&s->sout, generate_part_of_file, s);
s->file.len -= s->len;
s->file.data += s->len;
} while(s->file.len > 0);
PSOCK_END(&s->sout);
}
/*---------------------------------------------------------------------------*/
static
PT_THREAD(send_part_of_file(struct httpd_state *s))
{
PSOCK_BEGIN(&s->sout);
PSOCK_SEND(&s->sout, s->file.data, s->len);
PSOCK_END(&s->sout);
}
/*---------------------------------------------------------------------------*/
static void
next_scriptstate(struct httpd_state *s)
{
char *p;
p = strchr(s->scriptptr, ISO_nl) + 1;
s->scriptlen -= (unsigned short)(p - s->scriptptr);
s->scriptptr = p;
}
/*---------------------------------------------------------------------------*/
static
PT_THREAD(handle_script(struct httpd_state *s))
{
char *ptr;
PT_BEGIN(&s->scriptpt);
while(s->file.len > 0) {
/* Check if we should start executing a script. */
if(*s->file.data == ISO_percent &&
*(s->file.data + 1) == ISO_bang) {
s->scriptptr = s->file.data + 3;
s->scriptlen = s->file.len - 3;
if(*(s->scriptptr - 1) == ISO_colon) {
httpd_fs_open(s->scriptptr + 1, &s->file);
PT_WAIT_THREAD(&s->scriptpt, send_file(s));
} else {
PT_WAIT_THREAD(&s->scriptpt,
httpd_cgi(s->scriptptr)(s, s->scriptptr));
}
next_scriptstate(s);
/* The script is over, so we reset the pointers and continue
sending the rest of the file. */
s->file.data = s->scriptptr;
s->file.len = s->scriptlen;
} else {
/* See if we find the start of script marker in the block of HTML
to be sent. */
if(s->file.len > uip_mss()) {
s->len = uip_mss();
} else {
s->len = s->file.len;
}
if(*s->file.data == ISO_percent) {
ptr = strchr(s->file.data + 1, ISO_percent);
} else {
ptr = strchr(s->file.data, ISO_percent);
}
if(ptr != NULL &&
ptr != s->file.data) {
s->len = (int)(ptr - s->file.data);
if(s->len >= uip_mss()) {
s->len = uip_mss();
}
}
PT_WAIT_THREAD(&s->scriptpt, send_part_of_file(s));
s->file.data += s->len;
s->file.len -= s->len;
}
}
PT_END(&s->scriptpt);
}
/*---------------------------------------------------------------------------*/
static
PT_THREAD(send_headers(struct httpd_state *s, const char *statushdr))
{
char *ptr;
PSOCK_BEGIN(&s->sout);
PSOCK_SEND_STR(&s->sout, statushdr);
ptr = strrchr(s->filename, ISO_period);
if(ptr == NULL) {
PSOCK_SEND_STR(&s->sout, http_content_type_binary);
} else if(strncmp(http_html, ptr, 5) == 0 ||
strncmp(http_shtml, ptr, 6) == 0) {
PSOCK_SEND_STR(&s->sout, http_content_type_html);
} else if(strncmp(http_css, ptr, 4) == 0) {
PSOCK_SEND_STR(&s->sout, http_content_type_css);
} else if(strncmp(http_png, ptr, 4) == 0) {
PSOCK_SEND_STR(&s->sout, http_content_type_png);
} else if(strncmp(http_gif, ptr, 4) == 0) {
PSOCK_SEND_STR(&s->sout, http_content_type_gif);
} else if(strncmp(http_jpg, ptr, 4) == 0) {
PSOCK_SEND_STR(&s->sout, http_content_type_jpg);
} else {
PSOCK_SEND_STR(&s->sout, http_content_type_plain);
}
PSOCK_END(&s->sout);
}
/*---------------------------------------------------------------------------*/
static
PT_THREAD(handle_output(struct httpd_state *s))
{
char *ptr;
PT_BEGIN(&s->outputpt);
if(!httpd_fs_open(s->filename, &s->file)) {
httpd_fs_open(http_404_html, &s->file);
strcpy(s->filename, http_404_html);
PT_WAIT_THREAD(&s->outputpt,
send_headers(s,
http_header_404));
PT_WAIT_THREAD(&s->outputpt,
send_file(s));
} else {
PT_WAIT_THREAD(&s->outputpt,
send_headers(s,
http_header_200));
ptr = strchr(s->filename, ISO_period);
if(ptr != NULL && strncmp(ptr, http_shtml, 6) == 0) {
PT_INIT(&s->scriptpt);
PT_WAIT_THREAD(&s->outputpt, handle_script(s));
} else {
PT_WAIT_THREAD(&s->outputpt,
send_file(s));
}
}
PSOCK_CLOSE(&s->sout);
PT_END(&s->outputpt);
}
/*---------------------------------------------------------------------------*/
static
PT_THREAD(handle_input(struct httpd_state *s))
{
PSOCK_BEGIN(&s->sin);
PSOCK_READTO(&s->sin, ISO_space);
if(strncmp(s->inputbuf, http_get, 4) != 0) {
PSOCK_CLOSE_EXIT(&s->sin);
}
PSOCK_READTO(&s->sin, ISO_space);
if(s->inputbuf[0] != ISO_slash) {
PSOCK_CLOSE_EXIT(&s->sin);
}
if(s->inputbuf[1] == ISO_space) {
strncpy(s->filename, http_index_html, sizeof(s->filename));
} else {
s->inputbuf[PSOCK_DATALEN(&s->sin) - 1] = 0;
strncpy(s->filename, &s->inputbuf[0], sizeof(s->filename));
}
/* httpd_log_file(uip_conn->ripaddr, s->filename);*/
s->state = STATE_OUTPUT;
while(1) {
PSOCK_READTO(&s->sin, ISO_nl);
if(strncmp(s->inputbuf, http_referer, 8) == 0) {
s->inputbuf[PSOCK_DATALEN(&s->sin) - 2] = 0;
/* httpd_log(&s->inputbuf[9]);*/
}
}
PSOCK_END(&s->sin);
}
/*---------------------------------------------------------------------------*/
static void
handle_connection(struct httpd_state *s)
{
handle_input(s);
if(s->state == STATE_OUTPUT) {
handle_output(s);
}
}
/*---------------------------------------------------------------------------*/
void
httpd_appcall(void)
{
struct httpd_state *s = (struct httpd_state *)&(uip_conn->appstate);
if(uip_closed() || uip_aborted() || uip_timedout()) {
} else if(uip_connected()) {
PSOCK_INIT(&s->sin, s->inputbuf, sizeof(s->inputbuf) - 1);
PSOCK_INIT(&s->sout, s->inputbuf, sizeof(s->inputbuf) - 1);
PT_INIT(&s->outputpt);
s->state = STATE_WAITING;
/* timer_set(&s->timer, CLOCK_SECOND * 100);*/
s->timer = 0;
handle_connection(s);
} else if(s != NULL) {
if(uip_poll()) {
++s->timer;
if(s->timer >= 20) {
uip_abort();
}
} else {
s->timer = 0;
}
handle_connection(s);
} else {
uip_abort();
}
}
/*---------------------------------------------------------------------------*/
/**
* \brief Initialize the web server
*
* This function initializes the web server and should be
* called at system boot-up.
*/
void
httpd_init(void)
{
uip_listen(HTONS(80));
}
/*---------------------------------------------------------------------------*/
/** @} */

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Demo/ARM9_STR91X_IAR/webserver/httpd.h
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/*
* Copyright (c) 2001-2005, Adam Dunkels.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote
* products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* This file is part of the uIP TCP/IP stack.
*
* $Id: httpd.h,v 1.2 2006/06/11 21:46:38 adam Exp $
*
*/
#ifndef __HTTPD_H__
#define __HTTPD_H__
#include "psock.h"
#include "httpd-fs.h"
struct httpd_state {
unsigned char timer;
struct psock sin, sout;
struct pt outputpt, scriptpt;
char inputbuf[50];
char filename[20];
char state;
struct httpd_fs_file file;
int len;
char *scriptptr;
int scriptlen;
unsigned short count;
};
void httpd_init(void);
void httpd_appcall(void);
void httpd_log(char *msg);
void httpd_log_file(u16_t *requester, char *file);
#endif /* __HTTPD_H__ */

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Demo/ARM9_STR91X_IAR/webserver/makefsdata
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#!/usr/bin/perl
open(OUTPUT, "> httpd-fsdata.c");
chdir("httpd-fs");
opendir(DIR, ".");
@files = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR);
closedir(DIR);
foreach $file (@files) {
if(-d $file && $file !~ /^\./) {
print "Processing directory $file\n";
opendir(DIR, $file);
@newfiles = grep { !/^\./ && !/(CVS|~)/ } readdir(DIR);
closedir(DIR);
printf "Adding files @newfiles\n";
@files = (@files, map { $_ = "$file/$_" } @newfiles);
next;
}
}
foreach $file (@files) {
if(-f $file) {
print "Adding file $file\n";
open(FILE, $file) || die "Could not open file $file\n";
$file =~ s-^-/-;
$fvar = $file;
$fvar =~ s-/-_-g;
$fvar =~ s-\.-_-g;
# for AVR, add PROGMEM here
print(OUTPUT "static const unsigned char data".$fvar."[] = {\n");
print(OUTPUT "\t/* $file */\n\t");
for($j = 0; $j < length($file); $j++) {
printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1)));
}
printf(OUTPUT "0,\n");
$i = 0;
while(read(FILE, $data, 1)) {
if($i == 0) {
print(OUTPUT "\t");
}
printf(OUTPUT "%#02x, ", unpack("C", $data));
$i++;
if($i == 10) {
print(OUTPUT "\n");
$i = 0;
}
}
print(OUTPUT "0};\n\n");
close(FILE);
push(@fvars, $fvar);
push(@pfiles, $file);
}
}
for($i = 0; $i < @fvars; $i++) {
$file = $pfiles[$i];
$fvar = $fvars[$i];
if($i == 0) {
$prevfile = "NULL";
} else {
$prevfile = "file" . $fvars[$i - 1];
}
print(OUTPUT "const struct httpd_fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, ");
print(OUTPUT "data$fvar + ". (length($file) + 1) .", ");
print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n");
}
print(OUTPUT "#define HTTPD_FS_ROOT file$fvars[$i - 1]\n\n");
print(OUTPUT "#define HTTPD_FS_NUMFILES $i\n");

40
Demo/ARM9_STR91X_IAR/webserver/makestrings
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#!/usr/bin/perl
sub stringify {
my $name = shift(@_);
open(OUTPUTC, "> $name.c");
open(OUTPUTH, "> $name.h");
open(FILE, "$name");
while(<FILE>) {
if(/(.+) "(.+)"/) {
$var = $1;
$data = $2;
$datan = $data;
$datan =~ s/\\r/\r/g;
$datan =~ s/\\n/\n/g;
$datan =~ s/\\01/\01/g;
$datan =~ s/\\0/\0/g;
printf(OUTPUTC "const char $var\[%d] = \n", length($datan) + 1);
printf(OUTPUTC "/* \"$data\" */\n");
printf(OUTPUTC "{");
for($j = 0; $j < length($datan); $j++) {
printf(OUTPUTC "%#02x, ", unpack("C", substr($datan, $j, 1)));
}
printf(OUTPUTC "};\n");
printf(OUTPUTH "extern const char $var\[%d];\n", length($datan) + 1);
}
}
close(OUTPUTC);
close(OUTPUTH);
}
stringify("http-strings");
exit 0;

299
Demo/ARM9_STR91X_IAR/webserver/uIP_Task.c
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/*
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
/* Standard includes. */
#include <string.h>
/* Library includes. */
#include "91x_lib.h"
#include "91x_enet.h"
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "semphr.h"
/* uip includes. */
#include "uip.h"
#include "uip_arp.h"
#include "httpd.h"
#include "timer.h"
#include "clock-arch.h"
/*-----------------------------------------------------------*/
/* MAC address configuration. */
#define uipMAC_ADDR0 0x00
#define uipMAC_ADDR1 0x12
#define uipMAC_ADDR2 0x13
#define uipMAC_ADDR3 0x14
#define uipMAC_ADDR4 0x15
#define uipMAC_ADDR5 0x16
/* IP address configuration. */
#define uipIP_ADDR0 172
#define uipIP_ADDR1 25
#define uipIP_ADDR2 218
#define uipIP_ADDR3 26
/* Shortcut to the header within the Rx buffer. */
#define xHeader ((struct uip_eth_hdr *) &uip_buf[ 0 ])
/* uIP update frequencies. */
#define uipMAX_BLOCK_TIME (configTICK_RATE_HZ / 4)
/* Interrupt status bit definition. */
#define uipDMI_RX_CURRENT_DONE 0x8000
/* If no buffers are available, then wait this long before looking again. */
#define uipBUFFER_WAIT_DELAY ( 10 / portTICK_RATE_MS )
#define uipBUFFER_WAIT_ATTEMPTS ( 10 )
/* Standard constant. */
#define uipTOTAL_FRAME_HEADER_SIZE 54
/*-----------------------------------------------------------*/
/*
* Send the uIP buffer to the MAC.
*/
static void prvENET_Send(void);
/*
* Setup the MAC address in the MAC itself, and in the uIP stack.
*/
static void prvSetMACAddress( void );
/*
* Used to return a pointer to the next buffer to be used.
*/
extern unsigned portCHAR *pcGetNextBuffer( void );
/*
* Port functions required by the uIP stack.
*/
void clock_init( void );
clock_time_t clock_time( void );
/*-----------------------------------------------------------*/
/* The semaphore used by the ISR to wake the uIP task. */
xSemaphoreHandle xSemaphore = NULL;
/*-----------------------------------------------------------*/
void clock_init(void)
{
/* This is done when the scheduler starts. */
}
/*-----------------------------------------------------------*/
clock_time_t clock_time( void )
{
return xTaskGetTickCount();
}
/*-----------------------------------------------------------*/
void vuIP_Task( void *pvParameters )
{
portBASE_TYPE i;
uip_ipaddr_t xIPAddr;
struct timer periodic_timer, arp_timer;
/* Create the semaphore used by the ISR to wake this task. */
vSemaphoreCreateBinary( xSemaphore );
/* Initialise the uIP stack. */
timer_set( &periodic_timer, configTICK_RATE_HZ / 2 );
timer_set( &arp_timer, configTICK_RATE_HZ * 10 );
uip_init();
uip_ipaddr( xIPAddr, uipIP_ADDR0, uipIP_ADDR1, uipIP_ADDR2, uipIP_ADDR3 );
uip_sethostaddr( xIPAddr );
httpd_init();
/* Initialise the MAC. */
ENET_InitClocksGPIO();
ENET_Init();
portENTER_CRITICAL();
{
ENET_Start();
prvSetMACAddress();
VIC_Config( ENET_ITLine, VIC_IRQ, 1 );
VIC_ITCmd( ENET_ITLine, ENABLE );
ENET_DMA->ISR = uipDMI_RX_CURRENT_DONE;
ENET_DMA->IER = uipDMI_RX_CURRENT_DONE;
}
portEXIT_CRITICAL();
while(1)
{
/* Is there received data ready to be processed? */
uip_len = ENET_HandleRxPkt( uip_buf );
if( uip_len > 0 )
{
/* Standard uIP loop taken from the uIP manual. */
if( xHeader->type == htons( UIP_ETHTYPE_IP ) )
{
uip_arp_ipin();
uip_input();
/* If the above function invocation resulted in data that
should be sent out on the network, the global variable
uip_len is set to a value > 0. */
if( uip_len > 0 )
{
uip_arp_out();
prvENET_Send();
}
}
else if( xHeader->type == htons( UIP_ETHTYPE_ARP ) )
{
uip_arp_arpin();
/* If the above function invocation resulted in data that
should be sent out on the network, the global variable
uip_len is set to a value > 0. */
if( uip_len > 0 )
{
prvENET_Send();
}
}
}
else
{
if( timer_expired( &periodic_timer ) )
{
timer_reset( &periodic_timer );
for( i = 0; i < UIP_CONNS; i++ )
{
uip_periodic( i );
/* If the above function invocation resulted in data that
should be sent out on the network, the global variable
uip_len is set to a value > 0. */
if( uip_len > 0 )
{
uip_arp_out();
prvENET_Send();
}
}
/* Call the ARP timer function every 10 seconds. */
if( timer_expired( &arp_timer ) )
{
timer_reset( &arp_timer );
uip_arp_timer();
}
}
else
{
/* We did not receive a packet, and there was no periodic
processing to perform. Block for a fixed period. If a packet
is received during this period we will be woken by the ISR
giving us the Semaphore. */
xSemaphoreTake( xSemaphore, configTICK_RATE_HZ / 2 );
}
}
}
}
/*-----------------------------------------------------------*/
static void prvENET_Send(void)
{
portBASE_TYPE i;
static unsigned portCHAR *pcTxData;
/* Get a DMA buffer into which we can write the data to send. */
for( i = 0; i < uipBUFFER_WAIT_ATTEMPTS; i++ )
{
pcTxData = pcGetNextBuffer();
if( pcTxData )
{
break;
}
else
{
vTaskDelay( uipBUFFER_WAIT_DELAY );
}
}
if( pcTxData )
{
/* Copy the header into the Tx buffer. */
memcpy( ( void * ) pcTxData, ( void * ) uip_buf, uipTOTAL_FRAME_HEADER_SIZE );
/* If there is room, also copy in the application data if any. */
if( ( uip_len > uipTOTAL_FRAME_HEADER_SIZE ) && ( uip_len <= ( ENET_BUFFER_SIZE - uipTOTAL_FRAME_HEADER_SIZE ) ) )
{
memcpy( ( void * ) &( pcTxData[ uipTOTAL_FRAME_HEADER_SIZE ] ), ( void * ) uip_appdata, ( uip_len - uipTOTAL_FRAME_HEADER_SIZE ) );
}
ENET_TxPkt( &pcTxData, uip_len );
}
}
/*-----------------------------------------------------------*/
void ENET_IRQHandler(void)
{
portBASE_TYPE xSwitchRequired;
/* Give the semaphore in case the uIP task needs waking. */
xSwitchRequired = xSemaphoreGiveFromISR( xSemaphore, pdFALSE );
/* Clear the interrupt. */
ENET_DMA->ISR = uipDMI_RX_CURRENT_DONE;
/* Switch tasks if necessary. */
portEND_SWITCHING_ISR( xSwitchRequired );
}
/*-----------------------------------------------------------*/
static void prvSetMACAddress( void )
{
struct uip_eth_addr xAddr;
/* Configure the MAC address in the uIP stack. */
xAddr.addr[ 0 ] = uipMAC_ADDR0;
xAddr.addr[ 1 ] = uipMAC_ADDR1;
xAddr.addr[ 2 ] = uipMAC_ADDR2;
xAddr.addr[ 3 ] = uipMAC_ADDR3;
xAddr.addr[ 4 ] = uipMAC_ADDR4;
xAddr.addr[ 5 ] = uipMAC_ADDR5;
uip_setethaddr( xAddr );
/* Write the MAC address to the MAC. */
ENET_MAC->MAL = ( uipMAC_ADDR3 << 24 ) | ( uipMAC_ADDR2 << 16 ) | ( uipMAC_ADDR1 << 8 ) | ( uipMAC_ADDR0 );
ENET_MAC->MAH = ( uipMAC_ADDR5 << 8 ) | ( uipMAC_ADDR4 );
}

157
Demo/ARM9_STR91X_IAR/webserver/uip-conf.h
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/**
* \addtogroup uipopt
* @{
*/
/**
* \name Project-specific configuration options
* @{
*
* uIP has a number of configuration options that can be overridden
* for each project. These are kept in a project-specific uip-conf.h
* file and all configuration names have the prefix UIP_CONF.
*/
/*
* Copyright (c) 2006, Swedish Institute of Computer Science.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the Institute nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* This file is part of the uIP TCP/IP stack
*
* $Id: uip-conf.h,v 1.6 2006/06/12 08:00:31 adam Exp $
*/
/**
* \file
* An example uIP configuration file
* \author
* Adam Dunkels <adam@sics.se>
*/
#ifndef __UIP_CONF_H__
#define __UIP_CONF_H__
#include <inttypes.h>
/**
* 8 bit datatype
*
* This typedef defines the 8-bit type used throughout uIP.
*
* \hideinitializer
*/
typedef uint8_t u8_t;
/**
* 16 bit datatype
*
* This typedef defines the 16-bit type used throughout uIP.
*
* \hideinitializer
*/
typedef uint16_t u16_t;
/**
* Statistics datatype
*
* This typedef defines the dataype used for keeping statistics in
* uIP.
*
* \hideinitializer
*/
typedef unsigned short uip_stats_t;
/**
* Maximum number of TCP connections.
*
* \hideinitializer
*/
#define UIP_CONF_MAX_CONNECTIONS 40
/**
* Maximum number of listening TCP ports.
*
* \hideinitializer
*/
#define UIP_CONF_MAX_LISTENPORTS 40
/**
* uIP buffer size.
*
* \hideinitializer
*/
#define UIP_CONF_BUFFER_SIZE 1500
/**
* CPU byte order.
*
* \hideinitializer
*/
#define UIP_CONF_BYTE_ORDER LITTLE_ENDIAN
/**
* Logging on or off
*
* \hideinitializer
*/
#define UIP_CONF_LOGGING 0
/**
* UDP support on or off
*
* \hideinitializer
*/
#define UIP_CONF_UDP 0
/**
* UDP checksums on or off
*
* \hideinitializer
*/
#define UIP_CONF_UDP_CHECKSUMS 1
/**
* uIP statistics on or off
*
* \hideinitializer
*/
#define UIP_CONF_STATISTICS 1
/* Here we include the header file for the application(s) we use in
our project. */
/*#include "smtp.h"*/
/*#include "hello-world.h"*/
/*#include "telnetd.h"*/
#include "webserver.h"
/*#include "dhcpc.h"*/
/*#include "resolv.h"*/
/*#include "webclient.h"*/
#endif /* __UIP_CONF_H__ */
/** @} */
/** @} */

49
Demo/ARM9_STR91X_IAR/webserver/webserver.h
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/*
* Copyright (c) 2002, Adam Dunkels.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* 3. The name of the author may not be used to endorse or promote
* products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* This file is part of the uIP TCP/IP stack
*
* $Id: webserver.h,v 1.2 2006/06/11 21:46:38 adam Exp $
*
*/
#ifndef __WEBSERVER_H__
#define __WEBSERVER_H__
#include "httpd.h"
typedef struct httpd_state uip_tcp_appstate_t;
/* UIP_APPCALL: the name of the application function. This function
must return void and take no arguments (i.e., C type "void
appfunc(void)"). */
#ifndef UIP_APPCALL
#define UIP_APPCALL httpd_appcall
#endif
#endif /* __WEBSERVER_H__ */

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Demo/AVR_ATMega323_IAR/FreeRTOSConfig.h
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/*
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/AVR_ATMega323_IAR/ParTest/ParTest.c
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/*
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/AVR_ATMega323_IAR/main.c
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/*
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/AVR_ATMega323_IAR/serial/serial.c
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.

2
Demo/AVR_ATMega323_WinAVR/FreeRTOSConfig.h
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@ -1,5 +1,5 @@
/*
FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.
FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS.org distribution.

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