Add PIC24, dsPIC and Coldfire files.
Richard Barry
19 years ago
parent
5561c55286
commit
3878b82c9b
@ -0,0 +1,4 @@
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2006-08-31 (REL_1_2) Christian Walter <wolti@sil.at>:
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Notes: Recreated from lwIP port.
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@ -0,0 +1,75 @@
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/*
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FreeRTOS V4.1.0 - Copyright (C) 2003-2006 Richard Barry.
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MCF5235 Port - Copyright (C) 2006 Christian Walter.
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This file is part of the FreeRTOS distribution.
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FreeRTOS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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FreeRTOS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with FreeRTOS; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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A special exception to the GPL can be applied should you wish to distribute
|
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a combined work that includes FreeRTOS, without being obliged to provide
|
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the source code for any proprietary components. See the licensing section
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||||
of http://www.FreeRTOS.org for full details of how and when the exception
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can be applied.
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***************************************************************************
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See http://www.FreeRTOS.org for documentation, latest information, license
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and contact details. Please ensure to read the configuration and relevant
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port sections of the online documentation.
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***************************************************************************
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*/
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#ifndef FREERTOS_CONFIG_H
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#define FREERTOS_CONFIG_H
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/*-----------------------------------------------------------
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* Application specific definitions.
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*
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* These definitions should be adjusted for your particular hardware and
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* application requirements.
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*
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* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
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* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
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*----------------------------------------------------------*/
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#define configUSE_PREEMPTION 1
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#define configUSE_IDLE_HOOK 0
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#define configUSE_TICK_HOOK 0
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#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 25000000 )
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#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
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#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 7 )
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#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 256 )
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#define configMAX_TASK_NAME_LEN ( 16 )
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#define configUSE_TRACE_FACILITY 1
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#define configUSE_16_BIT_TICKS 0
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#define configIDLE_SHOULD_YIELD 1
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/* Co-routine definitions. */
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#define configUSE_CO_ROUTINES 0
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#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
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/* Set the following definitions to 1 to include the API function, or zero
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to exclude the API function. */
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#define INCLUDE_vTaskPrioritySet 1
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#define INCLUDE_uxTaskPriorityGet 1
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#define INCLUDE_vTaskDelete 1
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#define INCLUDE_vTaskCleanUpResources 0
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#define INCLUDE_vTaskSuspend 1
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#define INCLUDE_vTaskDelayUntil 1
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#define INCLUDE_vTaskDelay 1
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#define INCLUDE_xTaskGetCurrentTaskHandle 1
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#endif /* FREERTOS_CONFIG_H */
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@ -0,0 +1,87 @@
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#
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# FreeRTOS 4.1.0 - MCF5235 Coldfire Port
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#
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# Copyright (c) 2006 Christian Walter, Vienna 2006.
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#
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# $Id: Makefile,v 1.1 2006/08/31 22:45:48 wolti Exp $
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#
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# ---------------------------------------------------------------------------
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BASE = /opt/gcc-m68k/bin
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CC = $(BASE)/m68k-elf-gcc
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CXX = $(BASE)/m68k-elf-g++
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OBJCOPY = $(BASE)/m68k-elf-objcopy
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SIZE = $(BASE)/m68k-elf-size
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INSIGHT = $(BASE)/m68k-bdm-elf-insight
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BDMFLASH = $(BASE)/bdmflash
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#CFLAGS = -MD -O2 -m528x -Wall
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CFLAGS = -MD -gdwarf-2 -g3 -m528x -Wall \
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-D'GCC_MCF5235=1' -D'_GCC_USES_FP=1' \
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-D'__IPSBAR=((vuint8 *) 0x40000000)' -D'FSYS_2=25000000UL' \
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-I. -Iinclude -Iinclude/arch -Ifec \
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-I../../Source/include -I../Common/include
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ASFLAGS = -MD -gdwarf-2 -g3 -m528x -Wa,--register-prefix-optional \
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-Wa,--bitwise-or -Wa,--defsym,IPSBAR=0x40000000
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LDSCRIPT = m5235-ram.ld
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LDFLAGS = -nostartfiles -m528x -Wl,--script=$(LDSCRIPT)
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TGT = demo
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OTHER_CSRC =
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OTHER_ASRC = $(addprefix system/, crt0.S vector.S)
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CSRC = demo.c \
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$(addprefix system/, init.c newlib.c serial.c) \
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$(addprefix ../Common/Minimal/, PollQ.c integer.c flop.c BlockQ.c semtest.c dynamic.c ) \
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$(addprefix ../../Source/, tasks.c queue.c list.c) \
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$(addprefix ../../Source/portable/MemMang/, heap_3.c) \
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$(addprefix ../../Source/portable/GCC/MCF5235/, port.c)
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ASRC = $(addprefix system/, mcf5xxx.S )
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OBJS = $(CSRC:.c=.o) $(ASRC:.S=.o)
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NOLINK_OBJS = $(OTHER_CSRC:.c=.o) $(OTHER_ASRC:.S=.o)
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DEPS = $(OBJS:.o=.d) $(NOLINK_OBJS:.o=.d)
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BIN = $(TGT).elf
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.PHONY: clean all
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all: $(BIN)
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flash-programm: $(TGT).elf
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$(OBJCOPY) -O binary $(TGT).elf $(TGT).bin
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@BIN_SIZE=`du -b $(TGT).bin | awk '//{ print $$1; }'`; \
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echo "programming $(TGT).bin with size $$BIN_SIZE to flash..."; \
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$(BDMFLASH) /dev/bdmcf20 0x00000000 1 2 write $(TGT).bin 0
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flash-verify:
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@BIN_SIZE=`du -b $(TGT).bin | awk '//{ print $$1; }'`; \
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echo "loading $$BIN_SIZE bytes from target into $(TGT).vrf..."; \
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$(BDMFLASH) /dev/bdmcf20 0x00000000 1 2 read $(TGT).vrf 0 $$BIN_SIZE
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flash-erase:
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$(BDMFLASH) /dev/bdmcf20 0x00000000 1 2 erase
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debug:
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$(INSIGHT) --command=m5235.gdb --se=$(TGT).elf
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$(BIN): $(OBJS) $(NOLINK_OBJS)
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$(CC) $(LDFLAGS) -Wl,-Map=$(TGT).map $(OBJS) $(LDLIBS) -o $@
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clean:
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rm -f $(DEPS)
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rm -f $(OBJS) $(NOLINK_OBJS)
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rm -f $(BIN) $(TGT).map
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# ---------------------------------------------------------------------------
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# rules for code generation
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# ---------------------------------------------------------------------------
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%.o: %.c
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$(CC) $(CFLAGS) -o $@ -c $<
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%.o: %.S
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$(CC) $(ASFLAGS) -o $@ -c $<
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# ---------------------------------------------------------------------------
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# # compiler generated dependencies
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# ---------------------------------------------------------------------------
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-include $(DEPS)
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@ -0,0 +1,298 @@
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/*
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FreeRTOS V4.1.0 - Copyright (C) 2003-2006 Richard Barry.
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MCF5235 Port - Copyright (C) 2006 Christian Walter.
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This file is part of the FreeRTOS distribution.
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FreeRTOS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
|
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the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
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You should have received a copy of the GNU General Public License
|
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along with FreeRTOS; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
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|
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A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes FreeRTOS, without being obliged to provide
|
||||
the source code for any proprietary components. See the licensing section
|
||||
of http://www.FreeRTOS.org for full details of how and when the exception
|
||||
can be applied.
|
||||
|
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***************************************************************************
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See http://www.FreeRTOS.org for documentation, latest information, license
|
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and contact details. Please ensure to read the configuration and relevant
|
||||
port sections of the online documentation.
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||||
***************************************************************************
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*/
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/* ------------------------ System includes ------------------------------- */
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#include <stdlib.h>
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#include <string.h>
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/* ------------------------ FreeRTOS includes ----------------------------- */
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#include "FreeRTOS.h"
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#include "task.h"
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/* ------------------------ Demo application includes --------------------- */
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#include "partest.h"
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#include "flash.h"
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#include "integer.h"
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#include "PollQ.h"
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#include "comtest2.h"
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#include "semtest.h"
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#include "flop.h"
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#include "dynamic.h"
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#include "BlockQ.h"
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#include "serial.h"
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/* ------------------------ Defines --------------------------------------- */
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/* Constants for the ComTest tasks. */
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#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 38400 )
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#define mainCOM_TEST_LED ( -1 )
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/* Priorities for the demo application tasks. */
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#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
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#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )
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#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )
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#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 )
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#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
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#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )
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/* Interval in which tasks are checked. */
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#define mainCHECK_PERIOD ( ( portTickType ) 2000 / portTICK_RATE_MS )
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/* Constants used by the vMemCheckTask() task. */
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#define mainCOUNT_INITIAL_VALUE ( ( unsigned portLONG ) 0 )
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#define mainNO_TASK ( 0 )
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/* The size of the memory blocks allocated by the vMemCheckTask() task. */
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#define mainMEM_CHECK_SIZE_1 ( ( size_t ) 51 )
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#define mainMEM_CHECK_SIZE_2 ( ( size_t ) 52 )
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#define mainMEM_CHECK_SIZE_3 ( ( size_t ) 151 )
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/* ------------------------ Static variables ------------------------------ */
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xComPortHandle xSTDComPort = NULL;
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/* ------------------------ Static functions ------------------------------ */
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static portTASK_FUNCTION( vErrorChecks, pvParameters );
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static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG
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ulMemCheckTaskCount );
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static portTASK_FUNCTION( vMemCheckTask, pvParameters );
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/* ------------------------ Implementation -------------------------------- */
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int
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main( int argc, char *argv[] )
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{
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asm volatile ( "move.w #0x2000, %sr\n\t" );
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xSTDComPort = xSerialPortInitMinimal( 38400, 8 );
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/* Start the demo/test application tasks. */
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vStartIntegerMathTasks( tskIDLE_PRIORITY );
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vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
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vStartMathTasks( tskIDLE_PRIORITY );
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vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
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vStartDynamicPriorityTasks( );
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vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
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/* Start the check task - which is defined in this file. */
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xTaskCreate( vErrorChecks, ( signed portCHAR * )"Check", 512, NULL,
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mainCHECK_TASK_PRIORITY, NULL );
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/* Now all the tasks have been started - start the scheduler. */
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vTaskStartScheduler( );
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/* Should never get here! */
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return 0;
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}
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static
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portTASK_FUNCTION( vErrorChecks, pvParameters )
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{
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unsigned portLONG ulMemCheckTaskRunningCount;
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xTaskHandle xCreatedTask;
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/* The parameters are not used in this function. */
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( void )pvParameters;
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xSerialPortInitMinimal( mainCOM_TEST_BAUD_RATE, 8 );
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for( ;; )
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{
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ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE;
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xCreatedTask = mainNO_TASK;
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if( xTaskCreate
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( vMemCheckTask, ( signed portCHAR * )"MEM_CHECK",
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configMINIMAL_STACK_SIZE, ( void * )&ulMemCheckTaskRunningCount,
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tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS )
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{
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xSerialPutChar( xSTDComPort, 'E', portMAX_DELAY );
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}
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/* Delay until it is time to execute again. */
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vTaskDelay( mainCHECK_PERIOD );
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/* Delete the dynamically created task. */
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if( xCreatedTask != mainNO_TASK )
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{
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vTaskDelete( xCreatedTask );
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}
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if( prvCheckOtherTasksAreStillRunning( ulMemCheckTaskRunningCount ) !=
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pdPASS )
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{
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xSerialPutChar( xSTDComPort, 'E', portMAX_DELAY );
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}
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else
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{
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xSerialPutChar( xSTDComPort, '.', portMAX_DELAY );
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}
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}
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}
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static portLONG
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prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount )
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{
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portLONG lReturn = ( portLONG ) pdPASS;
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/* Check all the demo tasks (other than the flash tasks) to ensure
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* that they are all still running, and that none of them have detected
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* an error.
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*/
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if( xAreIntegerMathsTaskStillRunning( ) != pdTRUE )
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{
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lReturn = ( portLONG ) pdFAIL;
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}
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if( xArePollingQueuesStillRunning( ) != pdTRUE )
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{
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lReturn = ( portLONG ) pdFAIL;
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}
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if( xAreMathsTaskStillRunning( ) != pdTRUE )
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{
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lReturn = ( portLONG ) pdFAIL;
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}
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if( xAreSemaphoreTasksStillRunning( ) != pdTRUE )
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{
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lReturn = ( portLONG ) pdFAIL;
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}
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if( xAreDynamicPriorityTasksStillRunning( ) != pdTRUE )
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{
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lReturn = ( portLONG ) pdFAIL;
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}
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if( xAreBlockingQueuesStillRunning( ) != pdTRUE )
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{
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lReturn = ( portLONG ) pdFAIL;
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}
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if( ulMemCheckTaskCount == mainCOUNT_INITIAL_VALUE )
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{
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// The vMemCheckTask did not increment the counter - it must
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// have failed.
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lReturn = ( portLONG ) pdFAIL;
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}
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return lReturn;
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}
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static void
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vMemCheckTask( void *pvParameters )
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{
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unsigned portLONG *pulMemCheckTaskRunningCounter;
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void *pvMem1, *pvMem2, *pvMem3;
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static portLONG lErrorOccurred = pdFALSE;
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/* This task is dynamically created then deleted during each cycle of the
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vErrorChecks task to check the operation of the memory allocator. Each time
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the task is created memory is allocated for the stack and TCB. Each time
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the task is deleted this memory is returned to the heap. This task itself
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exercises the allocator by allocating and freeing blocks.
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The task executes at the idle priority so does not require a delay.
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pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the
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vErrorChecks() task that this task is still executing without error. */
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pulMemCheckTaskRunningCounter = ( unsigned portLONG * )pvParameters;
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for( ;; )
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{
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if( lErrorOccurred == pdFALSE )
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{
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/* We have never seen an error so increment the counter. */
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( *pulMemCheckTaskRunningCounter )++;
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}
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/* Allocate some memory - just to give the allocator some extra
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exercise. This has to be in a critical section to ensure the
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task does not get deleted while it has memory allocated. */
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vTaskSuspendAll( );
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{
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pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 );
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if( pvMem1 == NULL )
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{
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lErrorOccurred = pdTRUE;
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}
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else
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{
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memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 );
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vPortFree( pvMem1 );
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}
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}
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xTaskResumeAll( );
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/* Again - with a different size block. */
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vTaskSuspendAll( );
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{
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pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 );
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if( pvMem2 == NULL )
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{
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lErrorOccurred = pdTRUE;
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}
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else
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{
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memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 );
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vPortFree( pvMem2 );
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}
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}
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xTaskResumeAll( );
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/* Again - with a different size block. */
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vTaskSuspendAll( );
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{
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pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 );
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if( pvMem3 == NULL )
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{
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lErrorOccurred = pdTRUE;
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}
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else
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{
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memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 );
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vPortFree( pvMem3 );
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}
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}
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xTaskResumeAll( );
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}
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}
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void
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vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
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||||
{
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}
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void
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vParTestToggleLED( unsigned portBASE_TYPE uxLED )
|
||||
{
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}
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@ -0,0 +1,46 @@
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/*
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* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_H__
|
||||
#define __MCF523X_H__
|
||||
|
||||
/*********************************************************************/
|
||||
|
||||
#include "mcf523x/mcf523x_fec.h"
|
||||
#include "mcf523x/mcf523x_rng.h"
|
||||
#include "mcf523x/mcf523x_fmpll.h"
|
||||
#include "mcf523x/mcf523x_cs.h"
|
||||
#include "mcf523x/mcf523x_intc0.h"
|
||||
#include "mcf523x/mcf523x_intc1.h"
|
||||
#include "mcf523x/mcf523x_sdramc.h"
|
||||
#include "mcf523x/mcf523x_sram.h"
|
||||
#include "mcf523x/mcf523x_uart.h"
|
||||
#include "mcf523x/mcf523x_timer.h"
|
||||
#include "mcf523x/mcf523x_qspi.h"
|
||||
#include "mcf523x/mcf523x_eport.h"
|
||||
#include "mcf523x/mcf523x_i2c.h"
|
||||
#include "mcf523x/mcf523x_scm.h"
|
||||
#include "mcf523x/mcf523x_pit.h"
|
||||
#include "mcf523x/mcf523x_can.h"
|
||||
#include "mcf523x/mcf523x_wtm.h"
|
||||
#include "mcf523x/mcf523x_gpio.h"
|
||||
#include "mcf523x/mcf523x_mdha.h"
|
||||
#include "mcf523x/mcf523x_ccm.h"
|
||||
#include "mcf523x/mcf523x_rcm.h"
|
||||
#include "mcf523x/mcf523x_etpu.h"
|
||||
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_H__ */
|
||||
@ -0,0 +1,325 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_can.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_CAN_H__
|
||||
#define __MCF523X_CAN_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* FlexCAN Module (CAN)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_CAN_CANMCR0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0000]))
|
||||
#define MCF_CAN_CANCTRL0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0004]))
|
||||
#define MCF_CAN_TIMER0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0008]))
|
||||
#define MCF_CAN_RXGMASK0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0010]))
|
||||
#define MCF_CAN_RX14MASK0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0014]))
|
||||
#define MCF_CAN_RX15MASK0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0018]))
|
||||
#define MCF_CAN_ERRCNT0 (*(vuint32*)(void*)(&__IPSBAR[0x1C001C]))
|
||||
#define MCF_CAN_ERRSTAT0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0020]))
|
||||
#define MCF_CAN_IMASK0 (*(vuint16*)(void*)(&__IPSBAR[0x1C002A]))
|
||||
#define MCF_CAN_IFLAG0 (*(vuint16*)(void*)(&__IPSBAR[0x1C0032]))
|
||||
#define MCF_CAN_CANMCR1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0000]))
|
||||
#define MCF_CAN_CANCTRL1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0004]))
|
||||
#define MCF_CAN_TIMER1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0008]))
|
||||
#define MCF_CAN_RXGMASK1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0010]))
|
||||
#define MCF_CAN_RX14MASK1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0014]))
|
||||
#define MCF_CAN_RX15MASK1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0018]))
|
||||
#define MCF_CAN_ERRCNT1 (*(vuint32*)(void*)(&__IPSBAR[0x1F001C]))
|
||||
#define MCF_CAN_ERRSTAT1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0020]))
|
||||
#define MCF_CAN_IMASK1 (*(vuint16*)(void*)(&__IPSBAR[0x1F002A]))
|
||||
#define MCF_CAN_IFLAG1 (*(vuint16*)(void*)(&__IPSBAR[0x1F0032]))
|
||||
#define MCF_CAN_CANMCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0000+((x)*0x30000)]))
|
||||
#define MCF_CAN_CANCTRL(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0004+((x)*0x30000)]))
|
||||
#define MCF_CAN_TIMER(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0008+((x)*0x30000)]))
|
||||
#define MCF_CAN_RXGMASK(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0010+((x)*0x30000)]))
|
||||
#define MCF_CAN_RX14MASK(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0014+((x)*0x30000)]))
|
||||
#define MCF_CAN_RX15MASK(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0018+((x)*0x30000)]))
|
||||
#define MCF_CAN_ERRCNT(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C001C+((x)*0x30000)]))
|
||||
#define MCF_CAN_ERRSTAT(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0020+((x)*0x30000)]))
|
||||
#define MCF_CAN_IMASK(x) (*(vuint16*)(void*)(&__IPSBAR[0x1C002A+((x)*0x30000)]))
|
||||
#define MCF_CAN_IFLAG(x) (*(vuint16*)(void*)(&__IPSBAR[0x1C0032+((x)*0x30000)]))
|
||||
|
||||
#define MCF_CAN_MBUF0_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0080+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF0_TMSTP(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0082+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF0_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0084+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF0_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0088+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF0_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0089+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF0_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF0_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF0_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF0_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF0_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF0_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008F+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0090+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_TMSTP(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0092+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0094+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0098+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0099+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009F+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00A0+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00A4+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00A8+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00A9+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AA+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AB+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AC+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AD+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AE+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AF+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF3_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00B0+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF3_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00B4+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF3_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00B8+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF3_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00B9+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF3_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BA+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF3_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BB+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF3_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BC+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF3_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BD+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF3_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BE+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF3_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BF+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF4_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00C0+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF4_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00C4+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF4_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00C8+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF4_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00C9+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF4_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CA+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF4_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CB+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF4_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CC+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF4_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CD+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF4_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CE+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF4_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CF+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF5_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00D0+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF5_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00D4+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF5_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00D8+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF5_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00D9+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF5_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DA+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF5_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DB+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF5_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DC+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF5_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DD+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF5_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DE+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF5_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DF+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF6_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00E0+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF6_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00E4+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF6_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00E8+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF6_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00E9+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF6_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EA+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF6_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EB+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF6_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EC+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF6_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00ED+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF6_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EE+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF6_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EF+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF7_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00F0+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF7_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00F4+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF7_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00F8+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF7_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00F9+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF7_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FA+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF7_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FB+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF7_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FC+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF7_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FD+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF7_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FE+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF7_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FF+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0100+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0104+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0108+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0109+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010F+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0100+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0114+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0118+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0119+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011F+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0120+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0124+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0128+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0129+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012F+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0130+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0134+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0138+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0139+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013F+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0140+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0144+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0148+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0149+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014F+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0150+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0154+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0158+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0159+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015F+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0160+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0164+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0168+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0169+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016F+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0170+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0174+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0178+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0179+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017F+((x)*0x30000)]))
|
||||
|
||||
|
||||
#define MCF_CAN_MBUF0_DATAL(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0088+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF0_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C008C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_DATAL(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0098+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C009C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_DATAL(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00A8+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00AC+((x)*0x30000)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_CANMCR */
|
||||
#define MCF_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0)
|
||||
#define MCF_CAN_CANMCR_SUPV (0x00800000)
|
||||
#define MCF_CAN_CANMCR_FRZACK (0x01000000)
|
||||
#define MCF_CAN_CANMCR_SOFTRST (0x02000000)
|
||||
#define MCF_CAN_CANMCR_HALT (0x10000000)
|
||||
#define MCF_CAN_CANMCR_FRZ (0x40000000)
|
||||
#define MCF_CAN_CANMCR_MDIS (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_CANCTRL */
|
||||
#define MCF_CAN_CANCTRL_PROPSEG(x) (((x)&0x00000007)<<0)
|
||||
#define MCF_CAN_CANCTRL_LOM (0x00000008)
|
||||
#define MCF_CAN_CANCTRL_LBUF (0x00000010)
|
||||
#define MCF_CAN_CANCTRL_TSYNC (0x00000020)
|
||||
#define MCF_CAN_CANCTRL_BOFFREC (0x00000040)
|
||||
#define MCF_CAN_CANCTRL_SAMP (0x00000080)
|
||||
#define MCF_CAN_CANCTRL_LPB (0x00001000)
|
||||
#define MCF_CAN_CANCTRL_CLKSRC (0x00002000)
|
||||
#define MCF_CAN_CANCTRL_ERRMSK (0x00004000)
|
||||
#define MCF_CAN_CANCTRL_BOFFMSK (0x00008000)
|
||||
#define MCF_CAN_CANCTRL_PSEG2(x) (((x)&0x00000007)<<16)
|
||||
#define MCF_CAN_CANCTRL_PSEG1(x) (((x)&0x00000007)<<19)
|
||||
#define MCF_CAN_CANCTRL_RJW(x) (((x)&0x00000003)<<22)
|
||||
#define MCF_CAN_CANCTRL_PRESDIV(x) (((x)&0x000000FF)<<24)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_TIMER */
|
||||
#define MCF_CAN_TIMER_TIMER(x) (((x)&0x0000FFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_RXGMASK */
|
||||
#define MCF_CAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_RX14MASK */
|
||||
#define MCF_CAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_RX15MASK */
|
||||
#define MCF_CAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_ERRCNT */
|
||||
#define MCF_CAN_ERRCNT_TXECTR(x) (((x)&0x000000FF)<<0)
|
||||
#define MCF_CAN_ERRCNT_RXECTR(x) (((x)&0x000000FF)<<8)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_ERRSTAT */
|
||||
#define MCF_CAN_ERRSTAT_WAKINT (0x00000001)
|
||||
#define MCF_CAN_ERRSTAT_ERRINT (0x00000002)
|
||||
#define MCF_CAN_ERRSTAT_BOFFINT (0x00000004)
|
||||
#define MCF_CAN_ERRSTAT_FLTCONF(x) (((x)&0x00000003)<<4)
|
||||
#define MCF_CAN_ERRSTAT_TXRX (0x00000040)
|
||||
#define MCF_CAN_ERRSTAT_IDLE (0x00000080)
|
||||
#define MCF_CAN_ERRSTAT_RXWRN (0x00000100)
|
||||
#define MCF_CAN_ERRSTAT_TXWRN (0x00000200)
|
||||
#define MCF_CAN_ERRSTAT_STFERR (0x00000400)
|
||||
#define MCF_CAN_ERRSTAT_FRMERR (0x00000800)
|
||||
#define MCF_CAN_ERRSTAT_CRCERR (0x00001000)
|
||||
#define MCF_CAN_ERRSTAT_ACKERR (0x00002000)
|
||||
#define MCF_CAN_ERRSTAT_BITERR(x) (((x)&0x00000003)<<14)
|
||||
#define MCF_CAN_ERRSTAT_FLTCONF_ACTIVE (0x00000000)
|
||||
#define MCF_CAN_ERRSTAT_FLTCONF_PASSIVE (0x00000010)
|
||||
#define MCF_CAN_ERRSTAT_FLTCONF_BUSOFF (0x00000020)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_IMASK */
|
||||
#define MCF_CAN_IMASK_BUF0M (0x0001)
|
||||
#define MCF_CAN_IMASK_BUF1M (0x0002)
|
||||
#define MCF_CAN_IMASK_BUF2M (0x0004)
|
||||
#define MCF_CAN_IMASK_BUF3M (0x0008)
|
||||
#define MCF_CAN_IMASK_BUF4M (0x0010)
|
||||
#define MCF_CAN_IMASK_BUF5M (0x0020)
|
||||
#define MCF_CAN_IMASK_BUF6M (0x0040)
|
||||
#define MCF_CAN_IMASK_BUF7M (0x0080)
|
||||
#define MCF_CAN_IMASK_BUF8M (0x0100)
|
||||
#define MCF_CAN_IMASK_BUF9M (0x0200)
|
||||
#define MCF_CAN_IMASK_BUF10M (0x0400)
|
||||
#define MCF_CAN_IMASK_BUF11M (0x0800)
|
||||
#define MCF_CAN_IMASK_BUF12M (0x1000)
|
||||
#define MCF_CAN_IMASK_BUF13M (0x2000)
|
||||
#define MCF_CAN_IMASK_BUF14M (0x4000)
|
||||
#define MCF_CAN_IMASK_BUF15M (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_IFLAG */
|
||||
#define MCF_CAN_IFLAG_BUF0I (0x0001)
|
||||
#define MCF_CAN_IFLAG_BUF1I (0x0002)
|
||||
#define MCF_CAN_IFLAG_BUF2I (0x0004)
|
||||
#define MCF_CAN_IFLAG_BUF3I (0x0008)
|
||||
#define MCF_CAN_IFLAG_BUF4I (0x0010)
|
||||
#define MCF_CAN_IFLAG_BUF5I (0x0020)
|
||||
#define MCF_CAN_IFLAG_BUF6I (0x0040)
|
||||
#define MCF_CAN_IFLAG_BUF7I (0x0080)
|
||||
#define MCF_CAN_IFLAG_BUF8I (0x0100)
|
||||
#define MCF_CAN_IFLAG_BUF9I (0x0200)
|
||||
#define MCF_CAN_IFLAG_BUF10I (0x0400)
|
||||
#define MCF_CAN_IFLAG_BUF11I (0x0800)
|
||||
#define MCF_CAN_IFLAG_BUF12I (0x1000)
|
||||
#define MCF_CAN_IFLAG_BUF13I (0x2000)
|
||||
#define MCF_CAN_IFLAG_BUF14I (0x4000)
|
||||
#define MCF_CAN_IFLAG_BUF15I (0x8000)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_CAN_H__ */
|
||||
@ -0,0 +1,56 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_ccm.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_CCM_H__
|
||||
#define __MCF523X_CCM_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Chip Configuration Module (CCM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_CCM_CCR (*(vuint16*)(void*)(&__IPSBAR[0x110004]))
|
||||
#define MCF_CCM_LPCR (*(vuint8 *)(void*)(&__IPSBAR[0x110007]))
|
||||
#define MCF_CCM_CIR (*(vuint16*)(void*)(&__IPSBAR[0x11000A]))
|
||||
#define MCF_CCM_RCON (*(vuint16*)(void*)(&__IPSBAR[0x110008]))
|
||||
|
||||
/* Bit definitions and macros for MCF_CCM_CCR */
|
||||
#define MCF_CCM_CCR_BMT(x) (((x)&0x0007)<<0)
|
||||
#define MCF_CCM_CCR_BME (0x0008)
|
||||
#define MCF_CCM_CCR_SZEN (0x0040)
|
||||
#define MCF_CCM_CCR_MODE(x) (((x)&0x0007)<<8)
|
||||
|
||||
/* Bit definitions and macros for MCF_CCM_LPCR */
|
||||
#define MCF_CCM_LPCR_STPMD(x) (((x)&0x03)<<3)
|
||||
#define MCF_CCM_LPCR_LPMD(x) (((x)&0x03)<<6)
|
||||
#define MCF_CCM_LPCR_LPMD_STOP (0xC0)
|
||||
#define MCF_CCM_LPCR_LPMD_WAIT (0x80)
|
||||
#define MCF_CCM_LPCR_LPMD_DOZE (0x40)
|
||||
#define MCF_CCM_LPCR_LPMD_RUN (0x00)
|
||||
|
||||
/* Bit definitions and macros for MCF_CCM_CIR */
|
||||
#define MCF_CCM_CIR_PRN(x) (((x)&0x003F)<<0)
|
||||
#define MCF_CCM_CIR_PIN(x) (((x)&0x03FF)<<6)
|
||||
|
||||
/* Bit definitions and macros for MCF_CCM_RCON */
|
||||
#define MCF_CCM_RCON_MODE (0x0001)
|
||||
#define MCF_CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3)
|
||||
#define MCF_CCM_RCON_RLOAD (0x0020)
|
||||
#define MCF_CCM_RCON_RCSC(x) (((x)&0x0003)<<8)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_CCM_H__ */
|
||||
@ -0,0 +1,101 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_cs.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_CS_H__
|
||||
#define __MCF523X_CS_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Chip Selects (CS)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_CS_CSAR0 (*(vuint16*)(void*)(&__IPSBAR[0x000080]))
|
||||
#define MCF_CS_CSMR0 (*(vuint32*)(void*)(&__IPSBAR[0x000084]))
|
||||
#define MCF_CS_CSCR0 (*(vuint16*)(void*)(&__IPSBAR[0x00008A]))
|
||||
#define MCF_CS_CSAR1 (*(vuint16*)(void*)(&__IPSBAR[0x00008C]))
|
||||
#define MCF_CS_CSMR1 (*(vuint32*)(void*)(&__IPSBAR[0x000090]))
|
||||
#define MCF_CS_CSCR1 (*(vuint16*)(void*)(&__IPSBAR[0x000096]))
|
||||
#define MCF_CS_CSAR2 (*(vuint16*)(void*)(&__IPSBAR[0x000098]))
|
||||
#define MCF_CS_CSMR2 (*(vuint32*)(void*)(&__IPSBAR[0x00009C]))
|
||||
#define MCF_CS_CSCR2 (*(vuint16*)(void*)(&__IPSBAR[0x0000A2]))
|
||||
#define MCF_CS_CSAR3 (*(vuint16*)(void*)(&__IPSBAR[0x0000A4]))
|
||||
#define MCF_CS_CSMR3 (*(vuint32*)(void*)(&__IPSBAR[0x0000A8]))
|
||||
#define MCF_CS_CSCR3 (*(vuint16*)(void*)(&__IPSBAR[0x0000AE]))
|
||||
#define MCF_CS_CSAR4 (*(vuint16*)(void*)(&__IPSBAR[0x0000B0]))
|
||||
#define MCF_CS_CSMR4 (*(vuint32*)(void*)(&__IPSBAR[0x0000B4]))
|
||||
#define MCF_CS_CSCR4 (*(vuint16*)(void*)(&__IPSBAR[0x0000BA]))
|
||||
#define MCF_CS_CSAR5 (*(vuint16*)(void*)(&__IPSBAR[0x0000BC]))
|
||||
#define MCF_CS_CSMR5 (*(vuint32*)(void*)(&__IPSBAR[0x0000C0]))
|
||||
#define MCF_CS_CSCR5 (*(vuint16*)(void*)(&__IPSBAR[0x0000C6]))
|
||||
#define MCF_CS_CSAR6 (*(vuint16*)(void*)(&__IPSBAR[0x0000C8]))
|
||||
#define MCF_CS_CSMR6 (*(vuint32*)(void*)(&__IPSBAR[0x0000CC]))
|
||||
#define MCF_CS_CSCR6 (*(vuint16*)(void*)(&__IPSBAR[0x0000D2]))
|
||||
#define MCF_CS_CSAR7 (*(vuint16*)(void*)(&__IPSBAR[0x0000D4]))
|
||||
#define MCF_CS_CSMR7 (*(vuint32*)(void*)(&__IPSBAR[0x0000D8]))
|
||||
#define MCF_CS_CSCR7 (*(vuint16*)(void*)(&__IPSBAR[0x0000DE]))
|
||||
#define MCF_CS_CSAR(x) (*(vuint16*)(void*)(&__IPSBAR[0x000080+((x)*0x00C)]))
|
||||
#define MCF_CS_CSMR(x) (*(vuint32*)(void*)(&__IPSBAR[0x000084+((x)*0x00C)]))
|
||||
#define MCF_CS_CSCR(x) (*(vuint16*)(void*)(&__IPSBAR[0x00008A+((x)*0x00C)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_CS_CSAR */
|
||||
#define MCF_CS_CSAR_BA(x) ((uint16)(((x)&0xFFFF0000)>>16))
|
||||
|
||||
/* Bit definitions and macros for MCF_CS_CSMR */
|
||||
#define MCF_CS_CSMR_V (0x00000001)
|
||||
#define MCF_CS_CSMR_UD (0x00000002)
|
||||
#define MCF_CS_CSMR_UC (0x00000004)
|
||||
#define MCF_CS_CSMR_SD (0x00000008)
|
||||
#define MCF_CS_CSMR_SC (0x00000010)
|
||||
#define MCF_CS_CSMR_CI (0x00000020)
|
||||
#define MCF_CS_CSMR_AM (0x00000040)
|
||||
#define MCF_CS_CSMR_WP (0x00000100)
|
||||
#define MCF_CS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16)
|
||||
#define MCF_CS_CSMR_BAM_4G (0xFFFF0000)
|
||||
#define MCF_CS_CSMR_BAM_2G (0x7FFF0000)
|
||||
#define MCF_CS_CSMR_BAM_1G (0x3FFF0000)
|
||||
#define MCF_CS_CSMR_BAM_1024M (0x3FFF0000)
|
||||
#define MCF_CS_CSMR_BAM_512M (0x1FFF0000)
|
||||
#define MCF_CS_CSMR_BAM_256M (0x0FFF0000)
|
||||
#define MCF_CS_CSMR_BAM_128M (0x07FF0000)
|
||||
#define MCF_CS_CSMR_BAM_64M (0x03FF0000)
|
||||
#define MCF_CS_CSMR_BAM_32M (0x01FF0000)
|
||||
#define MCF_CS_CSMR_BAM_16M (0x00FF0000)
|
||||
#define MCF_CS_CSMR_BAM_8M (0x007F0000)
|
||||
#define MCF_CS_CSMR_BAM_4M (0x003F0000)
|
||||
#define MCF_CS_CSMR_BAM_2M (0x001F0000)
|
||||
#define MCF_CS_CSMR_BAM_1M (0x000F0000)
|
||||
#define MCF_CS_CSMR_BAM_1024K (0x000F0000)
|
||||
#define MCF_CS_CSMR_BAM_512K (0x00070000)
|
||||
#define MCF_CS_CSMR_BAM_256K (0x00030000)
|
||||
#define MCF_CS_CSMR_BAM_128K (0x00010000)
|
||||
#define MCF_CS_CSMR_BAM_64K (0x00000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_CS_CSCR */
|
||||
#define MCF_CS_CSCR_SWWS(x) (((x)&0x0007)<<0)
|
||||
#define MCF_CS_CSCR_BSTW (0x0008)
|
||||
#define MCF_CS_CSCR_BSTR (0x0010)
|
||||
#define MCF_CS_CSCR_BEM (0x0020)
|
||||
#define MCF_CS_CSCR_PS(x) (((x)&0x0003)<<6)
|
||||
#define MCF_CS_CSCR_AA (0x0100)
|
||||
#define MCF_CS_CSCR_IWS(x) (((x)&0x000F)<<10)
|
||||
#define MCF_CS_CSCR_SRWS(x) (((x)&0x0003)<<14)
|
||||
#define MCF_CS_CSCR_PS_8 (0x0040)
|
||||
#define MCF_CS_CSCR_PS_16 (0x0080)
|
||||
#define MCF_CS_CSCR_PS_32 (0x0000)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_CS_H__ */
|
||||
@ -0,0 +1,92 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_eport.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_EPORT_H__
|
||||
#define __MCF523X_EPORT_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Edge Port Module (EPORT)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_EPORT_EPPAR (*(vuint16*)(void*)(&__IPSBAR[0x130000]))
|
||||
#define MCF_EPORT_EPDDR (*(vuint8 *)(void*)(&__IPSBAR[0x130002]))
|
||||
#define MCF_EPORT_EPIER (*(vuint8 *)(void*)(&__IPSBAR[0x130003]))
|
||||
#define MCF_EPORT_EPDR (*(vuint8 *)(void*)(&__IPSBAR[0x130004]))
|
||||
#define MCF_EPORT_EPPDR (*(vuint8 *)(void*)(&__IPSBAR[0x130005]))
|
||||
#define MCF_EPORT_EPFR (*(vuint8 *)(void*)(&__IPSBAR[0x130006]))
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPPAR */
|
||||
#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
|
||||
#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4)
|
||||
#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6)
|
||||
#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8)
|
||||
#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10)
|
||||
#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12)
|
||||
#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14)
|
||||
#define MCF_EPORT_EPPAR_EPPAx_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPAx_RISING (1)
|
||||
#define MCF_EPORT_EPPAR_EPPAx_FALLING (2)
|
||||
#define MCF_EPORT_EPPAR_EPPAx_BOTH (3)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPDDR */
|
||||
#define MCF_EPORT_EPDDR_EPDD1 (0x02)
|
||||
#define MCF_EPORT_EPDDR_EPDD2 (0x04)
|
||||
#define MCF_EPORT_EPDDR_EPDD3 (0x08)
|
||||
#define MCF_EPORT_EPDDR_EPDD4 (0x10)
|
||||
#define MCF_EPORT_EPDDR_EPDD5 (0x20)
|
||||
#define MCF_EPORT_EPDDR_EPDD6 (0x40)
|
||||
#define MCF_EPORT_EPDDR_EPDD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPIER */
|
||||
#define MCF_EPORT_EPIER_EPIE1 (0x02)
|
||||
#define MCF_EPORT_EPIER_EPIE2 (0x04)
|
||||
#define MCF_EPORT_EPIER_EPIE3 (0x08)
|
||||
#define MCF_EPORT_EPIER_EPIE4 (0x10)
|
||||
#define MCF_EPORT_EPIER_EPIE5 (0x20)
|
||||
#define MCF_EPORT_EPIER_EPIE6 (0x40)
|
||||
#define MCF_EPORT_EPIER_EPIE7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPDR */
|
||||
#define MCF_EPORT_EPDR_EPD1 (0x02)
|
||||
#define MCF_EPORT_EPDR_EPD2 (0x04)
|
||||
#define MCF_EPORT_EPDR_EPD3 (0x08)
|
||||
#define MCF_EPORT_EPDR_EPD4 (0x10)
|
||||
#define MCF_EPORT_EPDR_EPD5 (0x20)
|
||||
#define MCF_EPORT_EPDR_EPD6 (0x40)
|
||||
#define MCF_EPORT_EPDR_EPD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPPDR */
|
||||
#define MCF_EPORT_EPPDR_EPPD1 (0x02)
|
||||
#define MCF_EPORT_EPPDR_EPPD2 (0x04)
|
||||
#define MCF_EPORT_EPPDR_EPPD3 (0x08)
|
||||
#define MCF_EPORT_EPPDR_EPPD4 (0x10)
|
||||
#define MCF_EPORT_EPPDR_EPPD5 (0x20)
|
||||
#define MCF_EPORT_EPPDR_EPPD6 (0x40)
|
||||
#define MCF_EPORT_EPPDR_EPPD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPFR */
|
||||
#define MCF_EPORT_EPFR_EPF1 (0x02)
|
||||
#define MCF_EPORT_EPFR_EPF2 (0x04)
|
||||
#define MCF_EPORT_EPFR_EPF3 (0x08)
|
||||
#define MCF_EPORT_EPFR_EPF4 (0x10)
|
||||
#define MCF_EPORT_EPFR_EPF5 (0x20)
|
||||
#define MCF_EPORT_EPFR_EPF6 (0x40)
|
||||
#define MCF_EPORT_EPFR_EPF7 (0x80)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_EPORT_H__ */
|
||||
@ -0,0 +1,493 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_etpu.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_ETPU_H__
|
||||
#define __MCF523X_ETPU_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* enhanced Time Processor Unit (ETPU)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_ETPU_EMCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0000]))
|
||||
#define MCF_ETPU_ECDCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0004]))
|
||||
#define MCF_ETPU_EMISCCR (*(vuint32*)(void*)(&__IPSBAR[0x1D000C]))
|
||||
#define MCF_ETPU_ESCMODR (*(vuint32*)(void*)(&__IPSBAR[0x1D0010]))
|
||||
#define MCF_ETPU_EECR (*(vuint32*)(void*)(&__IPSBAR[0x1D0014]))
|
||||
#define MCF_ETPU_ETBCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0020]))
|
||||
#define MCF_ETPU_ETB1R (*(vuint32*)(void*)(&__IPSBAR[0x1D0024]))
|
||||
#define MCF_ETPU_ETB2R (*(vuint32*)(void*)(&__IPSBAR[0x1D0028]))
|
||||
#define MCF_ETPU_EREDCR (*(vuint32*)(void*)(&__IPSBAR[0x1D002C]))
|
||||
#define MCF_ETPU_ECISR (*(vuint32*)(void*)(&__IPSBAR[0x1D0200]))
|
||||
#define MCF_ETPU_ECDTRSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0210]))
|
||||
#define MCF_ETPU_ECIOSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0220]))
|
||||
#define MCF_ETPU_ECDTROSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0230]))
|
||||
#define MCF_ETPU_ECIER (*(vuint32*)(void*)(&__IPSBAR[0x1D0240]))
|
||||
#define MCF_ETPU_ECDTRER (*(vuint32*)(void*)(&__IPSBAR[0x1D0250]))
|
||||
#define MCF_ETPU_ECPSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0280]))
|
||||
#define MCF_ETPU_ECSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0290]))
|
||||
#define MCF_ETPU_EC0SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0404]))
|
||||
#define MCF_ETPU_EC1SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0414]))
|
||||
#define MCF_ETPU_EC2SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0424]))
|
||||
#define MCF_ETPU_EC3SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0434]))
|
||||
#define MCF_ETPU_EC4SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0444]))
|
||||
#define MCF_ETPU_EC5SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0454]))
|
||||
#define MCF_ETPU_EC6SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0464]))
|
||||
#define MCF_ETPU_EC7SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0474]))
|
||||
#define MCF_ETPU_EC8SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0484]))
|
||||
#define MCF_ETPU_EC9SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0494]))
|
||||
#define MCF_ETPU_EC10SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A4]))
|
||||
#define MCF_ETPU_EC11SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B4]))
|
||||
#define MCF_ETPU_EC12SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C4]))
|
||||
#define MCF_ETPU_EC13SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D4]))
|
||||
#define MCF_ETPU_EC14SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E4]))
|
||||
#define MCF_ETPU_EC15SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F4]))
|
||||
#define MCF_ETPU_EC16SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0504]))
|
||||
#define MCF_ETPU_EC17SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0514]))
|
||||
#define MCF_ETPU_EC18SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0524]))
|
||||
#define MCF_ETPU_EC19SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0534]))
|
||||
#define MCF_ETPU_EC20SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0544]))
|
||||
#define MCF_ETPU_EC21SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0554]))
|
||||
#define MCF_ETPU_EC22SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0564]))
|
||||
#define MCF_ETPU_EC23SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0574]))
|
||||
#define MCF_ETPU_EC24SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0584]))
|
||||
#define MCF_ETPU_EC25SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0594]))
|
||||
#define MCF_ETPU_EC26SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A4]))
|
||||
#define MCF_ETPU_EC27SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B4]))
|
||||
#define MCF_ETPU_EC28SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C4]))
|
||||
#define MCF_ETPU_EC29SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D4]))
|
||||
#define MCF_ETPU_EC30SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E4]))
|
||||
#define MCF_ETPU_EC31SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F4]))
|
||||
#define MCF_ETPU_ECnSCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0404+((x)*0x010)]))
|
||||
#define MCF_ETPU_EC0CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0400]))
|
||||
#define MCF_ETPU_EC1CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0410]))
|
||||
#define MCF_ETPU_EC2CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0420]))
|
||||
#define MCF_ETPU_EC3CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0430]))
|
||||
#define MCF_ETPU_EC4CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0440]))
|
||||
#define MCF_ETPU_EC5CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0450]))
|
||||
#define MCF_ETPU_EC6CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0460]))
|
||||
#define MCF_ETPU_EC7CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0470]))
|
||||
#define MCF_ETPU_EC8CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0480]))
|
||||
#define MCF_ETPU_EC9CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0490]))
|
||||
#define MCF_ETPU_EC10CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A0]))
|
||||
#define MCF_ETPU_EC11CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B0]))
|
||||
#define MCF_ETPU_EC12CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C0]))
|
||||
#define MCF_ETPU_EC13CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D0]))
|
||||
#define MCF_ETPU_EC14CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E0]))
|
||||
#define MCF_ETPU_EC15CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F0]))
|
||||
#define MCF_ETPU_EC16CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0500]))
|
||||
#define MCF_ETPU_EC17CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0510]))
|
||||
#define MCF_ETPU_EC18CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0520]))
|
||||
#define MCF_ETPU_EC19CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0530]))
|
||||
#define MCF_ETPU_EC20CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0540]))
|
||||
#define MCF_ETPU_EC21CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0550]))
|
||||
#define MCF_ETPU_EC22CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0560]))
|
||||
#define MCF_ETPU_EC23CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0570]))
|
||||
#define MCF_ETPU_EC24CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0580]))
|
||||
#define MCF_ETPU_EC25CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0590]))
|
||||
#define MCF_ETPU_EC26CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A0]))
|
||||
#define MCF_ETPU_EC27CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B0]))
|
||||
#define MCF_ETPU_EC28CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C0]))
|
||||
#define MCF_ETPU_EC29CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D0]))
|
||||
#define MCF_ETPU_EC30CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E0]))
|
||||
#define MCF_ETPU_EC31CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F0]))
|
||||
#define MCF_ETPU_ECnCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0400+((x)*0x010)]))
|
||||
#define MCF_ETPU_EC0HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0408]))
|
||||
#define MCF_ETPU_EC1HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0418]))
|
||||
#define MCF_ETPU_EC2HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0428]))
|
||||
#define MCF_ETPU_EC3HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0438]))
|
||||
#define MCF_ETPU_EC4HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0448]))
|
||||
#define MCF_ETPU_EC5HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0458]))
|
||||
#define MCF_ETPU_EC6HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0468]))
|
||||
#define MCF_ETPU_EC7HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0478]))
|
||||
#define MCF_ETPU_EC8HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0488]))
|
||||
#define MCF_ETPU_EC9HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0498]))
|
||||
#define MCF_ETPU_EC10HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A8]))
|
||||
#define MCF_ETPU_EC11HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B8]))
|
||||
#define MCF_ETPU_EC12HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C8]))
|
||||
#define MCF_ETPU_EC13HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D8]))
|
||||
#define MCF_ETPU_EC14HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E8]))
|
||||
#define MCF_ETPU_EC15HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F8]))
|
||||
#define MCF_ETPU_EC16HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0508]))
|
||||
#define MCF_ETPU_EC17HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0518]))
|
||||
#define MCF_ETPU_EC18HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0528]))
|
||||
#define MCF_ETPU_EC19HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0538]))
|
||||
#define MCF_ETPU_EC20HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0548]))
|
||||
#define MCF_ETPU_EC21HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0558]))
|
||||
#define MCF_ETPU_EC22HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0568]))
|
||||
#define MCF_ETPU_EC23HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0578]))
|
||||
#define MCF_ETPU_EC24HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0588]))
|
||||
#define MCF_ETPU_EC25HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0598]))
|
||||
#define MCF_ETPU_EC26HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A8]))
|
||||
#define MCF_ETPU_EC27HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B8]))
|
||||
#define MCF_ETPU_EC28HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C8]))
|
||||
#define MCF_ETPU_EC29HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D8]))
|
||||
#define MCF_ETPU_EC30HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E8]))
|
||||
#define MCF_ETPU_EC31HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F8]))
|
||||
#define MCF_ETPU_ECnHSSR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0408+((x)*0x010)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_EMCR */
|
||||
#define MCF_ETPU_EMCR_GTBE (0x00000001)
|
||||
#define MCF_ETPU_EMCR_VIS (0x00000040)
|
||||
#define MCF_ETPU_EMCR_SCMMISEN (0x00000200)
|
||||
#define MCF_ETPU_EMCR_SCMMISF (0x00000400)
|
||||
#define MCF_ETPU_EMCR_SCMSIZE(x) (((x)&0x0000001F)<<16)
|
||||
#define MCF_ETPU_EMCR_ILF2 (0x01000000)
|
||||
#define MCF_ETPU_EMCR_ILF1 (0x02000000)
|
||||
#define MCF_ETPU_EMCR_MGE2 (0x04000000)
|
||||
#define MCF_ETPU_EMCR_MGE1 (0x08000000)
|
||||
#define MCF_ETPU_EMCR_GEC (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECDCR */
|
||||
#define MCF_ETPU_ECDCR_PARM1(x) (((x)&0x0000007F)<<0)
|
||||
#define MCF_ETPU_ECDCR_WR (0x00000080)
|
||||
#define MCF_ETPU_ECDCR_PARM0(x) (((x)&0x0000007F)<<8)
|
||||
#define MCF_ETPU_ECDCR_PWIDTH (0x00008000)
|
||||
#define MCF_ETPU_ECDCR_PBASE(x) (((x)&0x000003FF)<<16)
|
||||
#define MCF_ETPU_ECDCR_CTBASE(x) (((x)&0x0000001F)<<26)
|
||||
#define MCF_ETPU_ECDCR_STS (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_EECR */
|
||||
#define MCF_ETPU_EECR_ETB(x) (((x)&0x0000001F)<<0)
|
||||
#define MCF_ETPU_EECR_CDFC(x) (((x)&0x00000003)<<14)
|
||||
#define MCF_ETPU_EECR_FPSK(x) (((x)&0x00000007)<<16)
|
||||
#define MCF_ETPU_EECR_HLTF (0x00800000)
|
||||
#define MCF_ETPU_EECR_STF (0x10000000)
|
||||
#define MCF_ETPU_EECR_MDIS (0x40000000)
|
||||
#define MCF_ETPU_EECR_FEND (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ETBCR */
|
||||
#define MCF_ETPU_ETBCR_TCR1P(x) (((x)&0x000000FF)<<0)
|
||||
#define MCF_ETPU_ETBCR_TCR1CTL(x) (((x)&0x00000003)<<14)
|
||||
#define MCF_ETPU_ETBCR_TCR2P(x) (((x)&0x0000003F)<<16)
|
||||
#define MCF_ETPU_ETBCR_AM (0x02000000)
|
||||
#define MCF_ETPU_ETBCR_TCRCF(x) (((x)&0x00000003)<<27)
|
||||
#define MCF_ETPU_ETBCR_TCR2CTL(x) (((x)&0x00000007)<<29)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ETB1R */
|
||||
#define MCF_ETPU_ETB1R_TCR1(x) (((x)&0x00FFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ETB2R */
|
||||
#define MCF_ETPU_ETB2R_TCR2(x) (((x)&0x00FFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_EREDCR */
|
||||
#define MCF_ETPU_EREDCR_SRV2(x) (((x)&0x0000000F)<<0)
|
||||
#define MCF_ETPU_EREDCR_SERVER_ID2(x) (((x)&0x0000000F)<<8)
|
||||
#define MCF_ETPU_EREDCR_RSC2 (0x00004000)
|
||||
#define MCF_ETPU_EREDCR_REN2 (0x00008000)
|
||||
#define MCF_ETPU_EREDCR_SRV1(x) (((x)&0x0000000F)<<16)
|
||||
#define MCF_ETPU_EREDCR_SERVER_ID1(x) (((x)&0x0000000F)<<24)
|
||||
#define MCF_ETPU_EREDCR_RSC1 (0x40000000)
|
||||
#define MCF_ETPU_EREDCR_REN1 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECISR */
|
||||
#define MCF_ETPU_ECISR_CIS0 (0x00000001)
|
||||
#define MCF_ETPU_ECISR_CIS1 (0x00000002)
|
||||
#define MCF_ETPU_ECISR_CIS2 (0x00000004)
|
||||
#define MCF_ETPU_ECISR_CIS3 (0x00000008)
|
||||
#define MCF_ETPU_ECISR_CIS4 (0x00000010)
|
||||
#define MCF_ETPU_ECISR_CIS5 (0x00000020)
|
||||
#define MCF_ETPU_ECISR_CIS6 (0x00000040)
|
||||
#define MCF_ETPU_ECISR_CIS7 (0x00000080)
|
||||
#define MCF_ETPU_ECISR_CIS8 (0x00000100)
|
||||
#define MCF_ETPU_ECISR_CIS9 (0x00000200)
|
||||
#define MCF_ETPU_ECISR_CIS10 (0x00000400)
|
||||
#define MCF_ETPU_ECISR_CIS11 (0x00000800)
|
||||
#define MCF_ETPU_ECISR_CIS12 (0x00001000)
|
||||
#define MCF_ETPU_ECISR_CIS13 (0x00002000)
|
||||
#define MCF_ETPU_ECISR_CIS14 (0x00004000)
|
||||
#define MCF_ETPU_ECISR_CIS15 (0x00008000)
|
||||
#define MCF_ETPU_ECISR_CIS16 (0x00010000)
|
||||
#define MCF_ETPU_ECISR_CIS17 (0x00020000)
|
||||
#define MCF_ETPU_ECISR_CIS18 (0x00040000)
|
||||
#define MCF_ETPU_ECISR_CIS19 (0x00080000)
|
||||
#define MCF_ETPU_ECISR_CIS20 (0x00100000)
|
||||
#define MCF_ETPU_ECISR_CIS21 (0x00200000)
|
||||
#define MCF_ETPU_ECISR_CIS22 (0x00400000)
|
||||
#define MCF_ETPU_ECISR_CIS23 (0x00800000)
|
||||
#define MCF_ETPU_ECISR_CIS24 (0x01000000)
|
||||
#define MCF_ETPU_ECISR_CIS25 (0x02000000)
|
||||
#define MCF_ETPU_ECISR_CIS26 (0x04000000)
|
||||
#define MCF_ETPU_ECISR_CIS27 (0x08000000)
|
||||
#define MCF_ETPU_ECISR_CIS28 (0x10000000)
|
||||
#define MCF_ETPU_ECISR_CIS29 (0x20000000)
|
||||
#define MCF_ETPU_ECISR_CIS30 (0x40000000)
|
||||
#define MCF_ETPU_ECISR_CIS31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECDTRSR */
|
||||
#define MCF_ETPU_ECDTRSR_DTRS0 (0x00000001)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS1 (0x00000002)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS2 (0x00000004)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS3 (0x00000008)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS4 (0x00000010)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS5 (0x00000020)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS6 (0x00000040)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS7 (0x00000080)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS8 (0x00000100)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS9 (0x00000200)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS10 (0x00000400)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS11 (0x00000800)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS12 (0x00001000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS13 (0x00002000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS14 (0x00004000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS15 (0x00008000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS16 (0x00010000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS17 (0x00020000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS18 (0x00040000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS19 (0x00080000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS20 (0x00100000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS21 (0x00200000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS22 (0x00400000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS23 (0x00800000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS24 (0x01000000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS25 (0x02000000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS26 (0x04000000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS27 (0x08000000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS28 (0x10000000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS29 (0x20000000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS30 (0x40000000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECIOSR */
|
||||
#define MCF_ETPU_ECIOSR_CIOS0 (0x00000001)
|
||||
#define MCF_ETPU_ECIOSR_CIOS1 (0x00000002)
|
||||
#define MCF_ETPU_ECIOSR_CIOS2 (0x00000004)
|
||||
#define MCF_ETPU_ECIOSR_CIOS3 (0x00000008)
|
||||
#define MCF_ETPU_ECIOSR_CIOS4 (0x00000010)
|
||||
#define MCF_ETPU_ECIOSR_CIOS5 (0x00000020)
|
||||
#define MCF_ETPU_ECIOSR_CIOS6 (0x00000040)
|
||||
#define MCF_ETPU_ECIOSR_CIOS7 (0x00000080)
|
||||
#define MCF_ETPU_ECIOSR_CIOS8 (0x00000100)
|
||||
#define MCF_ETPU_ECIOSR_CIOS9 (0x00000200)
|
||||
#define MCF_ETPU_ECIOSR_CIOS10 (0x00000400)
|
||||
#define MCF_ETPU_ECIOSR_CIOS11 (0x00000800)
|
||||
#define MCF_ETPU_ECIOSR_CIOS12 (0x00001000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS13 (0x00002000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS14 (0x00004000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS15 (0x00008000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS16 (0x00010000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS17 (0x00020000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS18 (0x00040000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS19 (0x00080000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS20 (0x00100000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS21 (0x00200000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS22 (0x00400000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS23 (0x00800000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS24 (0x01000000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS25 (0x02000000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS26 (0x04000000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS27 (0x08000000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS28 (0x10000000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS29 (0x20000000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS30 (0x40000000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECDTROSR */
|
||||
#define MCF_ETPU_ECDTROSR_DTROS0 (0x00000001)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS1 (0x00000002)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS2 (0x00000004)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS3 (0x00000008)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS4 (0x00000010)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS5 (0x00000020)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS6 (0x00000040)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS7 (0x00000080)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS8 (0x00000100)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS9 (0x00000200)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS10 (0x00000400)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS11 (0x00000800)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS12 (0x00001000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS13 (0x00002000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS14 (0x00004000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS15 (0x00008000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS16 (0x00010000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS17 (0x00020000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS18 (0x00040000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS19 (0x00080000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS20 (0x00100000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS21 (0x00200000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS22 (0x00400000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS23 (0x00800000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS24 (0x01000000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS25 (0x02000000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS26 (0x04000000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS27 (0x08000000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS28 (0x10000000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS29 (0x20000000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS30 (0x40000000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECIER */
|
||||
#define MCF_ETPU_ECIER_CIE0 (0x00000001)
|
||||
#define MCF_ETPU_ECIER_CIE1 (0x00000002)
|
||||
#define MCF_ETPU_ECIER_CIE2 (0x00000004)
|
||||
#define MCF_ETPU_ECIER_CIE3 (0x00000008)
|
||||
#define MCF_ETPU_ECIER_CIE4 (0x00000010)
|
||||
#define MCF_ETPU_ECIER_CIE5 (0x00000020)
|
||||
#define MCF_ETPU_ECIER_CIE6 (0x00000040)
|
||||
#define MCF_ETPU_ECIER_CIE7 (0x00000080)
|
||||
#define MCF_ETPU_ECIER_CIE8 (0x00000100)
|
||||
#define MCF_ETPU_ECIER_CIE9 (0x00000200)
|
||||
#define MCF_ETPU_ECIER_CIE10 (0x00000400)
|
||||
#define MCF_ETPU_ECIER_CIE11 (0x00000800)
|
||||
#define MCF_ETPU_ECIER_CIE12 (0x00001000)
|
||||
#define MCF_ETPU_ECIER_CIE13 (0x00002000)
|
||||
#define MCF_ETPU_ECIER_CIE14 (0x00004000)
|
||||
#define MCF_ETPU_ECIER_CIE15 (0x00008000)
|
||||
#define MCF_ETPU_ECIER_CIE16 (0x00010000)
|
||||
#define MCF_ETPU_ECIER_CIE17 (0x00020000)
|
||||
#define MCF_ETPU_ECIER_CIE18 (0x00040000)
|
||||
#define MCF_ETPU_ECIER_CIE19 (0x00080000)
|
||||
#define MCF_ETPU_ECIER_CIE20 (0x00100000)
|
||||
#define MCF_ETPU_ECIER_CIE21 (0x00200000)
|
||||
#define MCF_ETPU_ECIER_CIE22 (0x00400000)
|
||||
#define MCF_ETPU_ECIER_CIE23 (0x00800000)
|
||||
#define MCF_ETPU_ECIER_CIE24 (0x01000000)
|
||||
#define MCF_ETPU_ECIER_CIE25 (0x02000000)
|
||||
#define MCF_ETPU_ECIER_CIE26 (0x04000000)
|
||||
#define MCF_ETPU_ECIER_CIE27 (0x08000000)
|
||||
#define MCF_ETPU_ECIER_CIE28 (0x10000000)
|
||||
#define MCF_ETPU_ECIER_CIE29 (0x20000000)
|
||||
#define MCF_ETPU_ECIER_CIE30 (0x40000000)
|
||||
#define MCF_ETPU_ECIER_CIE31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECDTRER */
|
||||
#define MCF_ETPU_ECDTRER_DTRE0 (0x00000001)
|
||||
#define MCF_ETPU_ECDTRER_DTRE1 (0x00000002)
|
||||
#define MCF_ETPU_ECDTRER_DTRE2 (0x00000004)
|
||||
#define MCF_ETPU_ECDTRER_DTRE3 (0x00000008)
|
||||
#define MCF_ETPU_ECDTRER_DTRE4 (0x00000010)
|
||||
#define MCF_ETPU_ECDTRER_DTRE5 (0x00000020)
|
||||
#define MCF_ETPU_ECDTRER_DTRE6 (0x00000040)
|
||||
#define MCF_ETPU_ECDTRER_DTRE7 (0x00000080)
|
||||
#define MCF_ETPU_ECDTRER_DTRE8 (0x00000100)
|
||||
#define MCF_ETPU_ECDTRER_DTRE9 (0x00000200)
|
||||
#define MCF_ETPU_ECDTRER_DTRE10 (0x00000400)
|
||||
#define MCF_ETPU_ECDTRER_DTRE11 (0x00000800)
|
||||
#define MCF_ETPU_ECDTRER_DTRE12 (0x00001000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE13 (0x00002000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE14 (0x00004000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE15 (0x00008000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE16 (0x00010000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE17 (0x00020000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE18 (0x00040000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE19 (0x00080000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE20 (0x00100000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE21 (0x00200000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE22 (0x00400000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE23 (0x00800000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE24 (0x01000000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE25 (0x02000000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE26 (0x04000000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE27 (0x08000000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE28 (0x10000000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE29 (0x20000000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE30 (0x40000000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECPSSR */
|
||||
#define MCF_ETPU_ECPSSR_SR0 (0x00000001)
|
||||
#define MCF_ETPU_ECPSSR_SR1 (0x00000002)
|
||||
#define MCF_ETPU_ECPSSR_SR2 (0x00000004)
|
||||
#define MCF_ETPU_ECPSSR_SR3 (0x00000008)
|
||||
#define MCF_ETPU_ECPSSR_SR4 (0x00000010)
|
||||
#define MCF_ETPU_ECPSSR_SR5 (0x00000020)
|
||||
#define MCF_ETPU_ECPSSR_SR6 (0x00000040)
|
||||
#define MCF_ETPU_ECPSSR_SR7 (0x00000080)
|
||||
#define MCF_ETPU_ECPSSR_SR8 (0x00000100)
|
||||
#define MCF_ETPU_ECPSSR_SR9 (0x00000200)
|
||||
#define MCF_ETPU_ECPSSR_SR10 (0x00000400)
|
||||
#define MCF_ETPU_ECPSSR_SR11 (0x00000800)
|
||||
#define MCF_ETPU_ECPSSR_SR12 (0x00001000)
|
||||
#define MCF_ETPU_ECPSSR_SR13 (0x00002000)
|
||||
#define MCF_ETPU_ECPSSR_SR14 (0x00004000)
|
||||
#define MCF_ETPU_ECPSSR_SR15 (0x00008000)
|
||||
#define MCF_ETPU_ECPSSR_SR16 (0x00010000)
|
||||
#define MCF_ETPU_ECPSSR_SR17 (0x00020000)
|
||||
#define MCF_ETPU_ECPSSR_SR18 (0x00040000)
|
||||
#define MCF_ETPU_ECPSSR_SR19 (0x00080000)
|
||||
#define MCF_ETPU_ECPSSR_SR20 (0x00100000)
|
||||
#define MCF_ETPU_ECPSSR_SR21 (0x00200000)
|
||||
#define MCF_ETPU_ECPSSR_SR22 (0x00400000)
|
||||
#define MCF_ETPU_ECPSSR_SR23 (0x00800000)
|
||||
#define MCF_ETPU_ECPSSR_SR24 (0x01000000)
|
||||
#define MCF_ETPU_ECPSSR_SR25 (0x02000000)
|
||||
#define MCF_ETPU_ECPSSR_SR26 (0x04000000)
|
||||
#define MCF_ETPU_ECPSSR_SR27 (0x08000000)
|
||||
#define MCF_ETPU_ECPSSR_SR28 (0x10000000)
|
||||
#define MCF_ETPU_ECPSSR_SR29 (0x20000000)
|
||||
#define MCF_ETPU_ECPSSR_SR30 (0x40000000)
|
||||
#define MCF_ETPU_ECPSSR_SR31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECSSR */
|
||||
#define MCF_ETPU_ECSSR_SS0 (0x00000001)
|
||||
#define MCF_ETPU_ECSSR_SS1 (0x00000002)
|
||||
#define MCF_ETPU_ECSSR_SS2 (0x00000004)
|
||||
#define MCF_ETPU_ECSSR_SS3 (0x00000008)
|
||||
#define MCF_ETPU_ECSSR_SS4 (0x00000010)
|
||||
#define MCF_ETPU_ECSSR_SS5 (0x00000020)
|
||||
#define MCF_ETPU_ECSSR_SS6 (0x00000040)
|
||||
#define MCF_ETPU_ECSSR_SS7 (0x00000080)
|
||||
#define MCF_ETPU_ECSSR_SS8 (0x00000100)
|
||||
#define MCF_ETPU_ECSSR_SS9 (0x00000200)
|
||||
#define MCF_ETPU_ECSSR_SS10 (0x00000400)
|
||||
#define MCF_ETPU_ECSSR_SS11 (0x00000800)
|
||||
#define MCF_ETPU_ECSSR_SS12 (0x00001000)
|
||||
#define MCF_ETPU_ECSSR_SS13 (0x00002000)
|
||||
#define MCF_ETPU_ECSSR_SS14 (0x00004000)
|
||||
#define MCF_ETPU_ECSSR_SS15 (0x00008000)
|
||||
#define MCF_ETPU_ECSSR_SS16 (0x00010000)
|
||||
#define MCF_ETPU_ECSSR_SS17 (0x00020000)
|
||||
#define MCF_ETPU_ECSSR_SS18 (0x00040000)
|
||||
#define MCF_ETPU_ECSSR_SS19 (0x00080000)
|
||||
#define MCF_ETPU_ECSSR_SS20 (0x00100000)
|
||||
#define MCF_ETPU_ECSSR_SS21 (0x00200000)
|
||||
#define MCF_ETPU_ECSSR_SS22 (0x00400000)
|
||||
#define MCF_ETPU_ECSSR_SS23 (0x00800000)
|
||||
#define MCF_ETPU_ECSSR_SS24 (0x01000000)
|
||||
#define MCF_ETPU_ECSSR_SS25 (0x02000000)
|
||||
#define MCF_ETPU_ECSSR_SS26 (0x04000000)
|
||||
#define MCF_ETPU_ECSSR_SS27 (0x08000000)
|
||||
#define MCF_ETPU_ECSSR_SS28 (0x10000000)
|
||||
#define MCF_ETPU_ECSSR_SS29 (0x20000000)
|
||||
#define MCF_ETPU_ECSSR_SS30 (0x40000000)
|
||||
#define MCF_ETPU_ECSSR_SS31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECnSCR */
|
||||
#define MCF_ETPU_ECnSCR_FM(x) (((x)&0x00000003)<<0)
|
||||
#define MCF_ETPU_ECnSCR_OBE (0x00002000)
|
||||
#define MCF_ETPU_ECnSCR_OPS (0x00004000)
|
||||
#define MCF_ETPU_ECnSCR_IPS (0x00008000)
|
||||
#define MCF_ETPU_ECnSCR_DTROS (0x00400000)
|
||||
#define MCF_ETPU_ECnSCR_DTRS (0x00800000)
|
||||
#define MCF_ETPU_ECnSCR_CIOS (0x40000000)
|
||||
#define MCF_ETPU_ECnSCR_CIS (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECnCR */
|
||||
#define MCF_ETPU_ECnCR_CPBA(x) (((x)&0x000007FF)<<0)
|
||||
#define MCF_ETPU_ECnCR_OPOL (0x00004000)
|
||||
#define MCF_ETPU_ECnCR_ODIS (0x00008000)
|
||||
#define MCF_ETPU_ECnCR_CFS(x) (((x)&0x0000001F)<<16)
|
||||
#define MCF_ETPU_ECnCR_ETCS (0x01000000)
|
||||
#define MCF_ETPU_ECnCR_CPR(x) (((x)&0x00000003)<<28)
|
||||
#define MCF_ETPU_ECnCR_DTRE (0x40000000)
|
||||
#define MCF_ETPU_ECnCR_CIE (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECnHSSR */
|
||||
#define MCF_ETPU_ECnHSSR_HSR(x) (((x)&0x00000007)<<0)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_ETPU_H__ */
|
||||
@ -0,0 +1,208 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_fec.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_FEC_H__
|
||||
#define __MCF523X_FEC_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Fast Ethernet Controller (FEC)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_FEC_EIR (*(vuint32*)(void*)(&__IPSBAR[0x001004]))
|
||||
#define MCF_FEC_EIMR (*(vuint32*)(void*)(&__IPSBAR[0x001008]))
|
||||
#define MCF_FEC_RDAR (*(vuint32*)(void*)(&__IPSBAR[0x001010]))
|
||||
#define MCF_FEC_TDAR (*(vuint32*)(void*)(&__IPSBAR[0x001014]))
|
||||
#define MCF_FEC_ECR (*(vuint32*)(void*)(&__IPSBAR[0x001024]))
|
||||
#define MCF_FEC_MMFR (*(vuint32*)(void*)(&__IPSBAR[0x001040]))
|
||||
#define MCF_FEC_MSCR (*(vuint32*)(void*)(&__IPSBAR[0x001044]))
|
||||
#define MCF_FEC_MIBC (*(vuint32*)(void*)(&__IPSBAR[0x001064]))
|
||||
#define MCF_FEC_RCR (*(vuint32*)(void*)(&__IPSBAR[0x001084]))
|
||||
#define MCF_FEC_TCR (*(vuint32*)(void*)(&__IPSBAR[0x0010C4]))
|
||||
#define MCF_FEC_PALR (*(vuint32*)(void*)(&__IPSBAR[0x0010E4]))
|
||||
#define MCF_FEC_PAUR (*(vuint32*)(void*)(&__IPSBAR[0x0010E8]))
|
||||
#define MCF_FEC_OPD (*(vuint32*)(void*)(&__IPSBAR[0x0010EC]))
|
||||
#define MCF_FEC_IAUR (*(vuint32*)(void*)(&__IPSBAR[0x001118]))
|
||||
#define MCF_FEC_IALR (*(vuint32*)(void*)(&__IPSBAR[0x00111C]))
|
||||
#define MCF_FEC_GAUR (*(vuint32*)(void*)(&__IPSBAR[0x001120]))
|
||||
#define MCF_FEC_GALR (*(vuint32*)(void*)(&__IPSBAR[0x001124]))
|
||||
#define MCF_FEC_TFWR (*(vuint32*)(void*)(&__IPSBAR[0x001144]))
|
||||
#define MCF_FEC_FRBR (*(vuint32*)(void*)(&__IPSBAR[0x00114C]))
|
||||
#define MCF_FEC_FRSR (*(vuint32*)(void*)(&__IPSBAR[0x001150]))
|
||||
#define MCF_FEC_ERDSR (*(vuint32*)(void*)(&__IPSBAR[0x001180]))
|
||||
#define MCF_FEC_ETDSR (*(vuint32*)(void*)(&__IPSBAR[0x001184]))
|
||||
#define MCF_FEC_EMRBR (*(vuint32*)(void*)(&__IPSBAR[0x001188]))
|
||||
#define MCF_FEC_RMON_T_DROP (*(vuint32*)(void*)(&__IPSBAR[0x001200]))
|
||||
#define MCF_FEC_RMON_T_PACKETS (*(vuint32*)(void*)(&__IPSBAR[0x001204]))
|
||||
#define MCF_FEC_RMON_T_BC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x001208]))
|
||||
#define MCF_FEC_RMON_T_MC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x00120C]))
|
||||
#define MCF_FEC_RMON_T_CRC_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x001210]))
|
||||
#define MCF_FEC_RMON_T_UNDERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001214]))
|
||||
#define MCF_FEC_RMON_T_OVERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001218]))
|
||||
#define MCF_FEC_RMON_T_FRAG (*(vuint32*)(void*)(&__IPSBAR[0x00121C]))
|
||||
#define MCF_FEC_RMON_T_JAB (*(vuint32*)(void*)(&__IPSBAR[0x001220]))
|
||||
#define MCF_FEC_RMON_T_COL (*(vuint32*)(void*)(&__IPSBAR[0x001224]))
|
||||
#define MCF_FEC_RMON_T_P64 (*(vuint32*)(void*)(&__IPSBAR[0x001228]))
|
||||
#define MCF_FEC_RMON_T_P65TO127 (*(vuint32*)(void*)(&__IPSBAR[0x00122C]))
|
||||
#define MCF_FEC_RMON_T_P128TO255 (*(vuint32*)(void*)(&__IPSBAR[0x001230]))
|
||||
#define MCF_FEC_RMON_T_P256TO511 (*(vuint32*)(void*)(&__IPSBAR[0x001234]))
|
||||
#define MCF_FEC_RMON_T_P512TO1023 (*(vuint32*)(void*)(&__IPSBAR[0x001238]))
|
||||
#define MCF_FEC_RMON_T_P1024TO2047 (*(vuint32*)(void*)(&__IPSBAR[0x00123C]))
|
||||
#define MCF_FEC_RMON_T_P_GTE2048 (*(vuint32*)(void*)(&__IPSBAR[0x001240]))
|
||||
#define MCF_FEC_RMON_T_OCTETS (*(vuint32*)(void*)(&__IPSBAR[0x001244]))
|
||||
#define MCF_FEC_IEEE_T_DROP (*(vuint32*)(void*)(&__IPSBAR[0x001248]))
|
||||
#define MCF_FEC_IEEE_T_FRAME_OK (*(vuint32*)(void*)(&__IPSBAR[0x00124C]))
|
||||
#define MCF_FEC_IEEE_T_1COL (*(vuint32*)(void*)(&__IPSBAR[0x001250]))
|
||||
#define MCF_FEC_IEEE_T_MCOL (*(vuint32*)(void*)(&__IPSBAR[0x001254]))
|
||||
#define MCF_FEC_IEEE_T_DEF (*(vuint32*)(void*)(&__IPSBAR[0x001258]))
|
||||
#define MCF_FEC_IEEE_T_LCOL (*(vuint32*)(void*)(&__IPSBAR[0x00125C]))
|
||||
#define MCF_FEC_IEEE_T_EXCOL (*(vuint32*)(void*)(&__IPSBAR[0x001260]))
|
||||
#define MCF_FEC_IEEE_T_MACERR (*(vuint32*)(void*)(&__IPSBAR[0x001264]))
|
||||
#define MCF_FEC_IEEE_T_CSERR (*(vuint32*)(void*)(&__IPSBAR[0x001268]))
|
||||
#define MCF_FEC_IEEE_T_SQE (*(vuint32*)(void*)(&__IPSBAR[0x00126C]))
|
||||
#define MCF_FEC_IEEE_T_FDXFC (*(vuint32*)(void*)(&__IPSBAR[0x001270]))
|
||||
#define MCF_FEC_IEEE_T_OCTETS_OK (*(vuint32*)(void*)(&__IPSBAR[0x001274]))
|
||||
#define MCF_FEC_RMON_R_PACKETS (*(vuint32*)(void*)(&__IPSBAR[0x001284]))
|
||||
#define MCF_FEC_RMON_R_BC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x001288]))
|
||||
#define MCF_FEC_RMON_R_MC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x00128C]))
|
||||
#define MCF_FEC_RMON_R_CRC_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x001290]))
|
||||
#define MCF_FEC_RMON_R_UNDERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001294]))
|
||||
#define MCF_FEC_RMON_R_OVERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001298]))
|
||||
#define MCF_FEC_RMON_R_FRAG (*(vuint32*)(void*)(&__IPSBAR[0x00129C]))
|
||||
#define MCF_FEC_RMON_R_JAB (*(vuint32*)(void*)(&__IPSBAR[0x0012A0]))
|
||||
#define MCF_FEC_RMON_R_RESVD_0 (*(vuint32*)(void*)(&__IPSBAR[0x0012A4]))
|
||||
#define MCF_FEC_RMON_R_P64 (*(vuint32*)(void*)(&__IPSBAR[0x0012A8]))
|
||||
#define MCF_FEC_RMON_R_P65TO127 (*(vuint32*)(void*)(&__IPSBAR[0x0012AC]))
|
||||
#define MCF_FEC_RMON_R_P128TO255 (*(vuint32*)(void*)(&__IPSBAR[0x0012B0]))
|
||||
#define MCF_FEC_RMON_R_P256TO511 (*(vuint32*)(void*)(&__IPSBAR[0x0012B4]))
|
||||
#define MCF_FEC_RMON_R_512TO1023 (*(vuint32*)(void*)(&__IPSBAR[0x0012B8]))
|
||||
#define MCF_FEC_RMON_R_P_GTE2048 (*(vuint32*)(void*)(&__IPSBAR[0x0012C0]))
|
||||
#define MCF_FEC_RMON_R_1024TO2047 (*(vuint32*)(void*)(&__IPSBAR[0x0012BC]))
|
||||
#define MCF_FEC_RMON_R_OCTETS (*(vuint32*)(void*)(&__IPSBAR[0x0012C4]))
|
||||
#define MCF_FEC_IEEE_R_DROP (*(vuint32*)(void*)(&__IPSBAR[0x0012C8]))
|
||||
#define MCF_FEC_IEEE_R_FRAME_OK (*(vuint32*)(void*)(&__IPSBAR[0x0012CC]))
|
||||
#define MCF_FEC_IEEE_R_CRC (*(vuint32*)(void*)(&__IPSBAR[0x0012D0]))
|
||||
#define MCF_FEC_IEEE_R_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x0012D4]))
|
||||
#define MCF_FEC_IEEE_R_MACERR (*(vuint32*)(void*)(&__IPSBAR[0x0012D8]))
|
||||
#define MCF_FEC_IEEE_R_FDXFC (*(vuint32*)(void*)(&__IPSBAR[0x0012DC]))
|
||||
#define MCF_FEC_IEEE_R_OCTETS_OK (*(vuint32*)(void*)(&__IPSBAR[0x0012E0]))
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_EIR */
|
||||
#define MCF_FEC_EIR_UN (0x00080000)
|
||||
#define MCF_FEC_EIR_RL (0x00100000)
|
||||
#define MCF_FEC_EIR_LC (0x00200000)
|
||||
#define MCF_FEC_EIR_EBERR (0x00400000)
|
||||
#define MCF_FEC_EIR_MII (0x00800000)
|
||||
#define MCF_FEC_EIR_RXB (0x01000000)
|
||||
#define MCF_FEC_EIR_RXF (0x02000000)
|
||||
#define MCF_FEC_EIR_TXB (0x04000000)
|
||||
#define MCF_FEC_EIR_TXF (0x08000000)
|
||||
#define MCF_FEC_EIR_GRA (0x10000000)
|
||||
#define MCF_FEC_EIR_BABT (0x20000000)
|
||||
#define MCF_FEC_EIR_BABR (0x40000000)
|
||||
#define MCF_FEC_EIR_HBERR (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_EIMR */
|
||||
#define MCF_FEC_EIMR_UN (0x00080000)
|
||||
#define MCF_FEC_EIMR_RL (0x00100000)
|
||||
#define MCF_FEC_EIMR_LC (0x00200000)
|
||||
#define MCF_FEC_EIMR_EBERR (0x00400000)
|
||||
#define MCF_FEC_EIMR_MII (0x00800000)
|
||||
#define MCF_FEC_EIMR_RXB (0x01000000)
|
||||
#define MCF_FEC_EIMR_RXF (0x02000000)
|
||||
#define MCF_FEC_EIMR_TXB (0x04000000)
|
||||
#define MCF_FEC_EIMR_TXF (0x08000000)
|
||||
#define MCF_FEC_EIMR_GRA (0x10000000)
|
||||
#define MCF_FEC_EIMR_BABT (0x20000000)
|
||||
#define MCF_FEC_EIMR_BABR (0x40000000)
|
||||
#define MCF_FEC_EIMR_HBERR (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RDAR */
|
||||
#define MCF_FEC_RDAR_R_DES_ACTIVE (0x01000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_TDAR */
|
||||
#define MCF_FEC_TDAR_X_DES_ACTIVE (0x01000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_ECR */
|
||||
#define MCF_FEC_ECR_RESET (0x00000001)
|
||||
#define MCF_FEC_ECR_ETHER_EN (0x00000002)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_MMFR */
|
||||
#define MCF_FEC_MMFR_DATA(x) (((x)&0x0000FFFF)<<0)
|
||||
#define MCF_FEC_MMFR_TA(x) (((x)&0x00000003)<<16)
|
||||
#define MCF_FEC_MMFR_RA(x) (((x)&0x0000001F)<<18)
|
||||
#define MCF_FEC_MMFR_PA(x) (((x)&0x0000001F)<<23)
|
||||
#define MCF_FEC_MMFR_OP(x) (((x)&0x00000003)<<28)
|
||||
#define MCF_FEC_MMFR_ST(x) (((x)&0x00000003)<<30)
|
||||
#define MCF_FEC_MMFR_ST_01 (0x40000000)
|
||||
#define MCF_FEC_MMFR_OP_READ (0x20000000)
|
||||
#define MCF_FEC_MMFR_OP_WRITE (0x10000000)
|
||||
#define MCF_FEC_MMFR_TA_10 (0x00020000)
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_MSCR */
|
||||
#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x0000003F)<<1)
|
||||
#define MCF_FEC_MSCR_DIS_PREAMBLE (0x00000080)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_MIBC */
|
||||
#define MCF_FEC_MIBC_MIB_IDLE (0x40000000)
|
||||
#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RCR */
|
||||
#define MCF_FEC_RCR_LOOP (0x00000001)
|
||||
#define MCF_FEC_RCR_DRT (0x00000002)
|
||||
#define MCF_FEC_RCR_MII_MODE (0x00000004)
|
||||
#define MCF_FEC_RCR_PROM (0x00000008)
|
||||
#define MCF_FEC_RCR_BC_REJ (0x00000010)
|
||||
#define MCF_FEC_RCR_FCE (0x00000020)
|
||||
#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x000007FF)<<16)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_TCR */
|
||||
#define MCF_FEC_TCR_GTS (0x00000001)
|
||||
#define MCF_FEC_TCR_HBC (0x00000002)
|
||||
#define MCF_FEC_TCR_FDEN (0x00000004)
|
||||
#define MCF_FEC_TCR_TFC_PAUSE (0x00000008)
|
||||
#define MCF_FEC_TCR_RFC_PAUSE (0x00000010)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_PAUR */
|
||||
#define MCF_FEC_PAUR_TYPE(x) (((x)&0x0000FFFF)<<0)
|
||||
#define MCF_FEC_PAUR_PADDR2(x) (((x)&0x0000FFFF)<<16)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_OPD */
|
||||
#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0)
|
||||
#define MCF_FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_TFWR */
|
||||
#define MCF_FEC_TFWR_X_WMRK(x) (((x)&0x00000003)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FRBR */
|
||||
#define MCF_FEC_FRBR_R_BOUND(x) (((x)&0x000000FF)<<2)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FRSR */
|
||||
#define MCF_FEC_FRSR_R_FSTART(x) (((x)&0x000000FF)<<2)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_ERDSR */
|
||||
#define MCF_FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_ETDSR */
|
||||
#define MCF_FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_EMRBR */
|
||||
#define MCF_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x0000007F)<<4)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_FEC_H__ */
|
||||
@ -0,0 +1,55 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_fmpll.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_FMPLL_H__
|
||||
#define __MCF523X_FMPLL_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Frequency Modulated Phase Locked Loop (FMPLL)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_FMPLL_SYNCR (*(vuint32*)(void*)(&__IPSBAR[0x120000]))
|
||||
#define MCF_FMPLL_SYNSR (*(vuint32*)(void*)(&__IPSBAR[0x120004]))
|
||||
|
||||
/* Bit definitions and macros for MCF_FMPLL_SYNCR */
|
||||
#define MCF_FMPLL_SYNCR_EXP(x) (((x)&0x000003FF)<<0)
|
||||
#define MCF_FMPLL_SYNCR_DEPTH(x) (((x)&0x00000003)<<10)
|
||||
#define MCF_FMPLL_SYNCR_RATE (0x00001000)
|
||||
#define MCF_FMPLL_SYNCR_LOCIRQ (0x00002000)
|
||||
#define MCF_FMPLL_SYNCR_LOLIRQ (0x00004000)
|
||||
#define MCF_FMPLL_SYNCR_DISCLK (0x00008000)
|
||||
#define MCF_FMPLL_SYNCR_LOCRE (0x00010000)
|
||||
#define MCF_FMPLL_SYNCR_LOLRE (0x00020000)
|
||||
#define MCF_FMPLL_SYNCR_LOCEN (0x00040000)
|
||||
#define MCF_FMPLL_SYNCR_RFD(x) (((x)&0x00000007)<<19)
|
||||
#define MCF_FMPLL_SYNCR_MFD(x) (((x)&0x00000007)<<24)
|
||||
|
||||
/* Bit definitions and macros for MCF_FMPLL_SYNSR */
|
||||
#define MCF_FMPLL_SYNSR_CALPASS (0x00000001)
|
||||
#define MCF_FMPLL_SYNSR_CALDONE (0x00000002)
|
||||
#define MCF_FMPLL_SYNSR_LOCF (0x00000004)
|
||||
#define MCF_FMPLL_SYNSR_LOCK (0x00000008)
|
||||
#define MCF_FMPLL_SYNSR_LOCKS (0x00000010)
|
||||
#define MCF_FMPLL_SYNSR_PLLREF (0x00000020)
|
||||
#define MCF_FMPLL_SYNSR_PLLSEL (0x00000040)
|
||||
#define MCF_FMPLL_SYNSR_MODE (0x00000080)
|
||||
#define MCF_FMPLL_SYNSR_LOC (0x00000100)
|
||||
#define MCF_FMPLL_SYNSR_LOLF (0x00000200)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_FMPLL_H__ */
|
||||
@ -0,0 +1,676 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_gpio.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_GPIO_H__
|
||||
#define __MCF523X_GPIO_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* General Purpose I/O (GPIO)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_GPIO_PODR_ADDR (*(vuint8 *)(void*)(&__IPSBAR[0x100000]))
|
||||
#define MCF_GPIO_PODR_DATAH (*(vuint8 *)(void*)(&__IPSBAR[0x100001]))
|
||||
#define MCF_GPIO_PODR_DATAL (*(vuint8 *)(void*)(&__IPSBAR[0x100002]))
|
||||
#define MCF_GPIO_PODR_BUSCTL (*(vuint8 *)(void*)(&__IPSBAR[0x100003]))
|
||||
#define MCF_GPIO_PODR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100004]))
|
||||
#define MCF_GPIO_PODR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100005]))
|
||||
#define MCF_GPIO_PODR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100006]))
|
||||
#define MCF_GPIO_PODR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100007]))
|
||||
#define MCF_GPIO_PODR_UARTH (*(vuint8 *)(void*)(&__IPSBAR[0x100008]))
|
||||
#define MCF_GPIO_PODR_UARTL (*(vuint8 *)(void*)(&__IPSBAR[0x100009]))
|
||||
#define MCF_GPIO_PODR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10000A]))
|
||||
#define MCF_GPIO_PODR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x10000B]))
|
||||
#define MCF_GPIO_PODR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10000C]))
|
||||
#define MCF_GPIO_PDDR_APDDR (*(vuint8 *)(void*)(&__IPSBAR[0x100010]))
|
||||
#define MCF_GPIO_PDDR_DATAH (*(vuint8 *)(void*)(&__IPSBAR[0x100011]))
|
||||
#define MCF_GPIO_PDDR_DATAL (*(vuint8 *)(void*)(&__IPSBAR[0x100012]))
|
||||
#define MCF_GPIO_PDDR_BUSCTL (*(vuint8 *)(void*)(&__IPSBAR[0x100013]))
|
||||
#define MCF_GPIO_PDDR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100014]))
|
||||
#define MCF_GPIO_PDDR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100015]))
|
||||
#define MCF_GPIO_PDDR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100016]))
|
||||
#define MCF_GPIO_PDDR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100017]))
|
||||
#define MCF_GPIO_PDDR_UARTH (*(vuint8 *)(void*)(&__IPSBAR[0x100018]))
|
||||
#define MCF_GPIO_PDDR_UARTL (*(vuint8 *)(void*)(&__IPSBAR[0x100019]))
|
||||
#define MCF_GPIO_PDDR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10001A]))
|
||||
#define MCF_GPIO_PDDR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x10001B]))
|
||||
#define MCF_GPIO_PDDR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10001C]))
|
||||
#define MCF_GPIO_PPDSDR_ADDR (*(vuint8 *)(void*)(&__IPSBAR[0x100020]))
|
||||
#define MCF_GPIO_PPDSDR_DATAH (*(vuint8 *)(void*)(&__IPSBAR[0x100021]))
|
||||
#define MCF_GPIO_PPDSDR_DATAL (*(vuint8 *)(void*)(&__IPSBAR[0x100022]))
|
||||
#define MCF_GPIO_PPDSDR_BUSCTL (*(vuint8 *)(void*)(&__IPSBAR[0x100023]))
|
||||
#define MCF_GPIO_PPDSDR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100024]))
|
||||
#define MCF_GPIO_PPDSDR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100027]))
|
||||
#define MCF_GPIO_PPDSDR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100025]))
|
||||
#define MCF_GPIO_PPDSDR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100026]))
|
||||
#define MCF_GPIO_PPDSDR_UARTH (*(vuint8 *)(void*)(&__IPSBAR[0x100028]))
|
||||
#define MCF_GPIO_PPDSDR_UARTL (*(vuint8 *)(void*)(&__IPSBAR[0x100029]))
|
||||
#define MCF_GPIO_PPDSDR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10002A]))
|
||||
#define MCF_GPIO_PPDSDR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x10002B]))
|
||||
#define MCF_GPIO_PPDSDR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10002C]))
|
||||
#define MCF_GPIO_PCLRR_ADDR (*(vuint8 *)(void*)(&__IPSBAR[0x100030]))
|
||||
#define MCF_GPIO_PCLRR_DATAH (*(vuint8 *)(void*)(&__IPSBAR[0x100031]))
|
||||
#define MCF_GPIO_PCLRR_DATAL (*(vuint8 *)(void*)(&__IPSBAR[0x100032]))
|
||||
#define MCF_GPIO_PCLRR_BUSCTL (*(vuint8 *)(void*)(&__IPSBAR[0x100033]))
|
||||
#define MCF_GPIO_PCLRR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100034]))
|
||||
#define MCF_GPIO_PCLRR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100035]))
|
||||
#define MCF_GPIO_PCLRR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100036]))
|
||||
#define MCF_GPIO_PCLRR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100037]))
|
||||
#define MCF_GPIO_PCLRR_UARTH (*(vuint8 *)(void*)(&__IPSBAR[0x100038]))
|
||||
#define MCF_GPIO_PCLRR_UARTL (*(vuint8 *)(void*)(&__IPSBAR[0x100039]))
|
||||
#define MCF_GPIO_PCLRR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10003A]))
|
||||
#define MCF_GPIO_PCLRR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x10003B]))
|
||||
#define MCF_GPIO_PCLRR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10003C]))
|
||||
#define MCF_GPIO_PAR_AD (*(vuint8 *)(void*)(&__IPSBAR[0x100040]))
|
||||
#define MCF_GPIO_PAR_BUSCTL (*(vuint16*)(void*)(&__IPSBAR[0x100042]))
|
||||
#define MCF_GPIO_PAR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100044]))
|
||||
#define MCF_GPIO_PAR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100045]))
|
||||
#define MCF_GPIO_PAR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100046]))
|
||||
#define MCF_GPIO_PAR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100047]))
|
||||
#define MCF_GPIO_PAR_UART (*(vuint16*)(void*)(&__IPSBAR[0x100048]))
|
||||
#define MCF_GPIO_PAR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10004A]))
|
||||
#define MCF_GPIO_PAR_TIMER (*(vuint16*)(void*)(&__IPSBAR[0x10004C]))
|
||||
#define MCF_GPIO_PAR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10004E]))
|
||||
#define MCF_GPIO_DSCR_EIM (*(vuint8 *)(void*)(&__IPSBAR[0x100050]))
|
||||
#define MCF_GPIO_DSCR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x100051]))
|
||||
#define MCF_GPIO_DSCR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100052]))
|
||||
#define MCF_GPIO_DSCR_UART (*(vuint8 *)(void*)(&__IPSBAR[0x100053]))
|
||||
#define MCF_GPIO_DSCR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x100054]))
|
||||
#define MCF_GPIO_DSCR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x100055]))
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_ADDR */
|
||||
#define MCF_GPIO_PODR_ADDR_PODR_ADDR5 (0x20)
|
||||
#define MCF_GPIO_PODR_ADDR_PODR_ADDR6 (0x40)
|
||||
#define MCF_GPIO_PODR_ADDR_PODR_ADDR7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_DATAH */
|
||||
#define MCF_GPIO_PODR_DATAH_PODR_DATAH0 (0x01)
|
||||
#define MCF_GPIO_PODR_DATAH_PODR_DATAH1 (0x02)
|
||||
#define MCF_GPIO_PODR_DATAH_PODR_DATAH2 (0x04)
|
||||
#define MCF_GPIO_PODR_DATAH_PODR_DATAH3 (0x08)
|
||||
#define MCF_GPIO_PODR_DATAH_PODR_DATAH4 (0x10)
|
||||
#define MCF_GPIO_PODR_DATAH_PODR_DATAH5 (0x20)
|
||||
#define MCF_GPIO_PODR_DATAH_PODR_DATAH6 (0x40)
|
||||
#define MCF_GPIO_PODR_DATAH_PODR_DATAH7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_DATAL */
|
||||
#define MCF_GPIO_PODR_DATAL_PODR_DATAL0 (0x01)
|
||||
#define MCF_GPIO_PODR_DATAL_PODR_DATAL1 (0x02)
|
||||
#define MCF_GPIO_PODR_DATAL_PODR_DATAL2 (0x04)
|
||||
#define MCF_GPIO_PODR_DATAL_PODR_DATAL3 (0x08)
|
||||
#define MCF_GPIO_PODR_DATAL_PODR_DATAL4 (0x10)
|
||||
#define MCF_GPIO_PODR_DATAL_PODR_DATAL5 (0x20)
|
||||
#define MCF_GPIO_PODR_DATAL_PODR_DATAL6 (0x40)
|
||||
#define MCF_GPIO_PODR_DATAL_PODR_DATAL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_BUSCTL */
|
||||
#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL0 (0x01)
|
||||
#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL1 (0x02)
|
||||
#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL2 (0x04)
|
||||
#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL3 (0x08)
|
||||
#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL4 (0x10)
|
||||
#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL5 (0x20)
|
||||
#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL6 (0x40)
|
||||
#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_BS */
|
||||
#define MCF_GPIO_PODR_BS_PODR_BS0 (0x01)
|
||||
#define MCF_GPIO_PODR_BS_PODR_BS1 (0x02)
|
||||
#define MCF_GPIO_PODR_BS_PODR_BS2 (0x04)
|
||||
#define MCF_GPIO_PODR_BS_PODR_BS3 (0x08)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_CS */
|
||||
#define MCF_GPIO_PODR_CS_PODR_CS1 (0x02)
|
||||
#define MCF_GPIO_PODR_CS_PODR_CS2 (0x04)
|
||||
#define MCF_GPIO_PODR_CS_PODR_CS3 (0x08)
|
||||
#define MCF_GPIO_PODR_CS_PODR_CS4 (0x10)
|
||||
#define MCF_GPIO_PODR_CS_PODR_CS5 (0x20)
|
||||
#define MCF_GPIO_PODR_CS_PODR_CS6 (0x40)
|
||||
#define MCF_GPIO_PODR_CS_PODR_CS7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_SDRAM */
|
||||
#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM0 (0x01)
|
||||
#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM1 (0x02)
|
||||
#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM2 (0x04)
|
||||
#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM3 (0x08)
|
||||
#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM4 (0x10)
|
||||
#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM5 (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
|
||||
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01)
|
||||
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02)
|
||||
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04)
|
||||
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_UARTH */
|
||||
#define MCF_GPIO_PODR_UARTH_PODR_UARTH0 (0x01)
|
||||
#define MCF_GPIO_PODR_UARTH_PODR_UARTH1 (0x02)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_UARTL */
|
||||
#define MCF_GPIO_PODR_UARTL_PODR_UARTL0 (0x01)
|
||||
#define MCF_GPIO_PODR_UARTL_PODR_UARTL1 (0x02)
|
||||
#define MCF_GPIO_PODR_UARTL_PODR_UARTL2 (0x04)
|
||||
#define MCF_GPIO_PODR_UARTL_PODR_UARTL3 (0x08)
|
||||
#define MCF_GPIO_PODR_UARTL_PODR_UARTL4 (0x10)
|
||||
#define MCF_GPIO_PODR_UARTL_PODR_UARTL5 (0x20)
|
||||
#define MCF_GPIO_PODR_UARTL_PODR_UARTL6 (0x40)
|
||||
#define MCF_GPIO_PODR_UARTL_PODR_UARTL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_QSPI */
|
||||
#define MCF_GPIO_PODR_QSPI_PODR_QSPI0 (0x01)
|
||||
#define MCF_GPIO_PODR_QSPI_PODR_QSPI1 (0x02)
|
||||
#define MCF_GPIO_PODR_QSPI_PODR_QSPI2 (0x04)
|
||||
#define MCF_GPIO_PODR_QSPI_PODR_QSPI3 (0x08)
|
||||
#define MCF_GPIO_PODR_QSPI_PODR_QSPI4 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_TIMER */
|
||||
#define MCF_GPIO_PODR_TIMER_PODR_TIMER0 (0x01)
|
||||
#define MCF_GPIO_PODR_TIMER_PODR_TIMER1 (0x02)
|
||||
#define MCF_GPIO_PODR_TIMER_PODR_TIMER2 (0x04)
|
||||
#define MCF_GPIO_PODR_TIMER_PODR_TIMER3 (0x08)
|
||||
#define MCF_GPIO_PODR_TIMER_PODR_TIMER4 (0x10)
|
||||
#define MCF_GPIO_PODR_TIMER_PODR_TIMER5 (0x20)
|
||||
#define MCF_GPIO_PODR_TIMER_PODR_TIMER6 (0x40)
|
||||
#define MCF_GPIO_PODR_TIMER_PODR_TIMER7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_ETPU */
|
||||
#define MCF_GPIO_PODR_ETPU_PODR_ETPU0 (0x01)
|
||||
#define MCF_GPIO_PODR_ETPU_PODR_ETPU1 (0x02)
|
||||
#define MCF_GPIO_PODR_ETPU_PODR_ETPU2 (0x04)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_APDDR */
|
||||
#define MCF_GPIO_PDDR_APDDR_PDDR_APDDR5 (0x20)
|
||||
#define MCF_GPIO_PDDR_APDDR_PDDR_APDDR6 (0x40)
|
||||
#define MCF_GPIO_PDDR_APDDR_PDDR_APDDR7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_DATAH */
|
||||
#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH0 (0x01)
|
||||
#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH1 (0x02)
|
||||
#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH2 (0x04)
|
||||
#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH3 (0x08)
|
||||
#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH4 (0x10)
|
||||
#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH5 (0x20)
|
||||
#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH6 (0x40)
|
||||
#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_DATAL */
|
||||
#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL0 (0x01)
|
||||
#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL1 (0x02)
|
||||
#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL2 (0x04)
|
||||
#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL3 (0x08)
|
||||
#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL4 (0x10)
|
||||
#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL5 (0x20)
|
||||
#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL6 (0x40)
|
||||
#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_BUSCTL */
|
||||
#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL0 (0x01)
|
||||
#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1 (0x02)
|
||||
#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2 (0x04)
|
||||
#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3 (0x08)
|
||||
#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL4 (0x10)
|
||||
#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL5 (0x20)
|
||||
#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL6 (0x40)
|
||||
#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_BS */
|
||||
#define MCF_GPIO_PDDR_BS_PDDR_BS0 (0x01)
|
||||
#define MCF_GPIO_PDDR_BS_PDDR_BS3(x) (((x)&0x07)<<1)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_CS */
|
||||
#define MCF_GPIO_PDDR_CS_PDDR_CS1 (0x02)
|
||||
#define MCF_GPIO_PDDR_CS_PDDR_CS2 (0x04)
|
||||
#define MCF_GPIO_PDDR_CS_PDDR_CS3 (0x08)
|
||||
#define MCF_GPIO_PDDR_CS_PDDR_CS4 (0x10)
|
||||
#define MCF_GPIO_PDDR_CS_PDDR_CS5 (0x20)
|
||||
#define MCF_GPIO_PDDR_CS_PDDR_CS6 (0x40)
|
||||
#define MCF_GPIO_PDDR_CS_PDDR_CS7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_SDRAM */
|
||||
#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM0 (0x01)
|
||||
#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM1 (0x02)
|
||||
#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM2 (0x04)
|
||||
#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM3 (0x08)
|
||||
#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM4 (0x10)
|
||||
#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM5 (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
|
||||
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01)
|
||||
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02)
|
||||
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04)
|
||||
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_UARTH */
|
||||
#define MCF_GPIO_PDDR_UARTH_PDDR_UARTH0 (0x01)
|
||||
#define MCF_GPIO_PDDR_UARTH_PDDR_UARTH1 (0x02)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_UARTL */
|
||||
#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL0 (0x01)
|
||||
#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL1 (0x02)
|
||||
#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL2 (0x04)
|
||||
#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL3 (0x08)
|
||||
#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL4 (0x10)
|
||||
#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL5 (0x20)
|
||||
#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL6 (0x40)
|
||||
#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_QSPI */
|
||||
#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI0 (0x01)
|
||||
#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI1 (0x02)
|
||||
#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI2 (0x04)
|
||||
#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI3 (0x08)
|
||||
#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI4 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_TIMER */
|
||||
#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER0 (0x01)
|
||||
#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER1 (0x02)
|
||||
#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER2 (0x04)
|
||||
#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER3 (0x08)
|
||||
#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER4 (0x10)
|
||||
#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER5 (0x20)
|
||||
#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER6 (0x40)
|
||||
#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_ETPU */
|
||||
#define MCF_GPIO_PDDR_ETPU_PDDR_ETPU0 (0x01)
|
||||
#define MCF_GPIO_PDDR_ETPU_PDDR_ETPU1 (0x02)
|
||||
#define MCF_GPIO_PDDR_ETPU_PDDR_ETPU2 (0x04)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_ADDR */
|
||||
#define MCF_GPIO_PPDSDR_ADDR_PPDSDR_ADDR5 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_ADDR_PPDSDR_ADDR6 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_ADDR_PPDSDR_ADDR7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_DATAH */
|
||||
#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH0 (0x01)
|
||||
#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH1 (0x02)
|
||||
#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH2 (0x04)
|
||||
#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH3 (0x08)
|
||||
#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH5 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH6 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_DATAL */
|
||||
#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL0 (0x01)
|
||||
#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL1 (0x02)
|
||||
#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL2 (0x04)
|
||||
#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL3 (0x08)
|
||||
#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL5 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL6 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_BUSCTL */
|
||||
#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL0 (0x01)
|
||||
#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL1 (0x02)
|
||||
#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL2 (0x04)
|
||||
#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL3 (0x08)
|
||||
#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL5 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL6 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_BS */
|
||||
#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS0 (0x01)
|
||||
#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS1 (0x02)
|
||||
#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS2 (0x04)
|
||||
#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS3 (0x08)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
|
||||
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01)
|
||||
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02)
|
||||
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04)
|
||||
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_CS */
|
||||
#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS1 (0x02)
|
||||
#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS2 (0x04)
|
||||
#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS3 (0x08)
|
||||
#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS5 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS6 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_SDRAM */
|
||||
#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM0 (0x01)
|
||||
#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM1 (0x02)
|
||||
#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM2 (0x04)
|
||||
#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM3 (0x08)
|
||||
#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM5 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM6 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_UARTH */
|
||||
#define MCF_GPIO_PPDSDR_UARTH_PPDSDR_UARTH0 (0x01)
|
||||
#define MCF_GPIO_PPDSDR_UARTH_PPDSDR_UARTH1 (0x02)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_UARTL */
|
||||
#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL0 (0x01)
|
||||
#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL1 (0x02)
|
||||
#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL2 (0x04)
|
||||
#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL3 (0x08)
|
||||
#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL5 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL6 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_QSPI */
|
||||
#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI0 (0x01)
|
||||
#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI1 (0x02)
|
||||
#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI2 (0x04)
|
||||
#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI3 (0x08)
|
||||
#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI4 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_TIMER */
|
||||
#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER0 (0x01)
|
||||
#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER1 (0x02)
|
||||
#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER2 (0x04)
|
||||
#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER3 (0x08)
|
||||
#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER5 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER6 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_ETPU */
|
||||
#define MCF_GPIO_PPDSDR_ETPU_PPDSDR_ETPU0 (0x01)
|
||||
#define MCF_GPIO_PPDSDR_ETPU_PPDSDR_ETPU1 (0x02)
|
||||
#define MCF_GPIO_PPDSDR_ETPU_PPDSDR_ETPU2 (0x04)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_ADDR */
|
||||
#define MCF_GPIO_PCLRR_ADDR_PCLRR_ADDR5 (0x20)
|
||||
#define MCF_GPIO_PCLRR_ADDR_PCLRR_ADDR6 (0x40)
|
||||
#define MCF_GPIO_PCLRR_ADDR_PCLRR_ADDR7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_DATAH */
|
||||
#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH0 (0x01)
|
||||
#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH1 (0x02)
|
||||
#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH2 (0x04)
|
||||
#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH3 (0x08)
|
||||
#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH5 (0x20)
|
||||
#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH6 (0x40)
|
||||
#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_DATAL */
|
||||
#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL0 (0x01)
|
||||
#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL1 (0x02)
|
||||
#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL2 (0x04)
|
||||
#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL3 (0x08)
|
||||
#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL5 (0x20)
|
||||
#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL6 (0x40)
|
||||
#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_BUSCTL */
|
||||
#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL0 (0x01)
|
||||
#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL1 (0x02)
|
||||
#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL2 (0x04)
|
||||
#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL3 (0x08)
|
||||
#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL5 (0x20)
|
||||
#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL6 (0x40)
|
||||
#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_BS */
|
||||
#define MCF_GPIO_PCLRR_BS_PCLRR_BS0 (0x01)
|
||||
#define MCF_GPIO_PCLRR_BS_PCLRR_BS1 (0x02)
|
||||
#define MCF_GPIO_PCLRR_BS_PCLRR_BS2 (0x04)
|
||||
#define MCF_GPIO_PCLRR_BS_PCLRR_BS3 (0x08)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_CS */
|
||||
#define MCF_GPIO_PCLRR_CS_PCLRR_CS1 (0x02)
|
||||
#define MCF_GPIO_PCLRR_CS_PCLRR_CS2 (0x04)
|
||||
#define MCF_GPIO_PCLRR_CS_PCLRR_CS3 (0x08)
|
||||
#define MCF_GPIO_PCLRR_CS_PCLRR_CS4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_CS_PCLRR_CS5 (0x20)
|
||||
#define MCF_GPIO_PCLRR_CS_PCLRR_CS6 (0x40)
|
||||
#define MCF_GPIO_PCLRR_CS_PCLRR_CS7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_SDRAM */
|
||||
#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM0 (0x01)
|
||||
#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM1 (0x02)
|
||||
#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM2 (0x04)
|
||||
#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM3 (0x08)
|
||||
#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM5 (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
|
||||
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01)
|
||||
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02)
|
||||
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x04)
|
||||
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_UARTH */
|
||||
#define MCF_GPIO_PCLRR_UARTH_PCLRR_UARTH0 (0x01)
|
||||
#define MCF_GPIO_PCLRR_UARTH_PCLRR_UARTH1 (0x02)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_UARTL */
|
||||
#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL0 (0x01)
|
||||
#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL1 (0x02)
|
||||
#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL2 (0x04)
|
||||
#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL3 (0x08)
|
||||
#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL5 (0x20)
|
||||
#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL6 (0x40)
|
||||
#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_QSPI */
|
||||
#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI0 (0x01)
|
||||
#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI1 (0x02)
|
||||
#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI2 (0x04)
|
||||
#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI3 (0x08)
|
||||
#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI4 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_TIMER */
|
||||
#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER0 (0x01)
|
||||
#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER1 (0x02)
|
||||
#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER2 (0x04)
|
||||
#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER3 (0x08)
|
||||
#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER5 (0x20)
|
||||
#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER6 (0x40)
|
||||
#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_ETPU */
|
||||
#define MCF_GPIO_PCLRR_ETPU_PCLRR_ETPU0 (0x01)
|
||||
#define MCF_GPIO_PCLRR_ETPU_PCLRR_ETPU1 (0x02)
|
||||
#define MCF_GPIO_PCLRR_ETPU_PCLRR_ETPU2 (0x04)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PAR_AD */
|
||||
#define MCF_GPIO_PAR_AD_PAR_DATAL (0x01)
|
||||
#define MCF_GPIO_PAR_AD_PAR_ADDR21 (0x20)
|
||||
#define MCF_GPIO_PAR_AD_PAR_ADDR22 (0x40)
|
||||
#define MCF_GPIO_PAR_AD_PAR_ADDR23 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PAR_BUSCTL */
|
||||
#define MCF_GPIO_PAR_BUSCTL_PAR_TIP(x) (((x)&0x0003)<<0)
|
||||
#define MCF_GPIO_PAR_BUSCTL_PAR_TS(x) (((x)&0x0003)<<2)
|
||||
#define MCF_GPIO_PAR_BUSCTL_PAR_TSIZ0 (0x0010)
|
||||
#define MCF_GPIO_PAR_BUSCTL_PAR_TSIZ1 (0x0040)
|
||||
#define MCF_GPIO_PAR_BUSCTL_PAR_RWB (0x0100)
|
||||
#define MCF_GPIO_PAR_BUSCTL_PAR_TEA(x) (((x)&0x0003)<<10)
|
||||
#define MCF_GPIO_PAR_BUSCTL_PAR_TA (0x1000)
|
||||
#define MCF_GPIO_PAR_BUSCTL_PAR_OE (0x4000)
|
||||
#define MCF_GPIO_PAR_BUSCTL_PAR_TEA_GPIO (0x0000)
|
||||
#define MCF_GPIO_PAR_BUSCTL_PAR_TEA_DMA (0x0800)
|
||||
#define MCF_GPIO_PAR_BUSCTL_PAR_TEA_TEA (0x0C00)
|
||||
#define MCF_GPIO_PAR_BUSCTL_PAR_TS_GPIO (0x0000)
|
||||
#define MCF_GPIO_PAR_BUSCTL_PAR_TS_DMA (0x0080)
|
||||
#define MCF_GPIO_PAR_BUSCTL_PAR_TS_TS (0x00C0)
|
||||
#define MCF_GPIO_PAR_BUSCTL_PAR_TIP_GPIO (0x0000)
|
||||
#define MCF_GPIO_PAR_BUSCTL_PAR_TIP_DMA (0x0002)
|
||||
#define MCF_GPIO_PAR_BUSCTL_PAR_TIP_TEA (0x0003)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PAR_BS */
|
||||
#define MCF_GPIO_PAR_BS_PAR_BS0 (0x01)
|
||||
#define MCF_GPIO_PAR_BS_PAR_BS1 (0x02)
|
||||
#define MCF_GPIO_PAR_BS_PAR_BS2 (0x04)
|
||||
#define MCF_GPIO_PAR_BS_PAR_BS3 (0x08)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PAR_CS */
|
||||
#define MCF_GPIO_PAR_CS_PAR_CS1 (0x02)
|
||||
#define MCF_GPIO_PAR_CS_PAR_CS2 (0x04)
|
||||
#define MCF_GPIO_PAR_CS_PAR_CS3 (0x08)
|
||||
#define MCF_GPIO_PAR_CS_PAR_CS4 (0x10)
|
||||
#define MCF_GPIO_PAR_CS_PAR_CS5 (0x20)
|
||||
#define MCF_GPIO_PAR_CS_PAR_CS6 (0x40)
|
||||
#define MCF_GPIO_PAR_CS_PAR_CS7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PAR_SDRAM */
|
||||
#define MCF_GPIO_PAR_SDRAM_PAR_SDCS0 (0x01)
|
||||
#define MCF_GPIO_PAR_SDRAM_PAR_SDCS1 (0x02)
|
||||
#define MCF_GPIO_PAR_SDRAM_PAR_SCKE (0x04)
|
||||
#define MCF_GPIO_PAR_SDRAM_PAR_SRAS (0x08)
|
||||
#define MCF_GPIO_PAR_SDRAM_PAR_SCAS (0x10)
|
||||
#define MCF_GPIO_PAR_SDRAM_PAR_SDWE (0x20)
|
||||
#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PAR_FECI2C */
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x03)<<0)
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x03)<<2)
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO(x) (((x)&0x03)<<4)
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_EMDC(x) (((x)&0x03)<<6)
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_GPIO (0x00)
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_UART2 (0x40)
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_I2C (0x80)
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC (0xC0)
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_GPIO (0x00)
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_UART2 (0x10)
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_I2C (0x20)
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC (0x30)
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_SCL_GPIO (0x00)
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_SCL_FLEX (0x08)
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_SCL_I2C (0x0C)
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_SDA_GPIO (0x00)
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_SDA_FLEX (0x02)
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_SDA_I2C (0x03)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PAR_UART */
|
||||
#define MCF_GPIO_PAR_UART_PAR_U0RTS (0x0001)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U0CTS (0x0002)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U0TXD (0x0004)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U0RXD (0x0008)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U1RTS(x) (((x)&0x0003)<<4)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U1CTS(x) (((x)&0x0003)<<6)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U1TXD(x) (((x)&0x0003)<<8)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U1RXD(x) (((x)&0x0003)<<10)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U2TXD (0x1000)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U2RXD (0x2000)
|
||||
#define MCF_GPIO_PAR_UART_PAR_CAN1EN (0x4000)
|
||||
#define MCF_GPIO_PAR_UART_PAR_DREQ2 (0x8000)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U1RXD_GPIO (0x0000)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U1RXD_FLEX (0x0800)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U1RXD_UART1 (0x0C00)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U1TXD_GPIO (0x0000)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U1TXD_FLEX (0x0200)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U1TXD_UART1 (0x0300)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U1CTS_GPIO (0x0000)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U1CTS_UART2 (0x0080)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U1CTS_UART1 (0x00C0)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U1RTS_GPIO (0x0000)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U1RTS_UART2 (0x0020)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U1RTS_UART1 (0x0030)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PAR_QSPI */
|
||||
#define MCF_GPIO_PAR_QSPI_PAR_SCK(x) (((x)&0x03)<<0)
|
||||
#define MCF_GPIO_PAR_QSPI_PAR_DOUT (0x04)
|
||||
#define MCF_GPIO_PAR_QSPI_PAR_DIN(x) (((x)&0x03)<<3)
|
||||
#define MCF_GPIO_PAR_QSPI_PAR_PCS0 (0x20)
|
||||
#define MCF_GPIO_PAR_QSPI_PAR_PCS1(x) (((x)&0x03)<<6)
|
||||
#define MCF_GPIO_PAR_QSPI_PAR_PCS1_GPIO (0x00)
|
||||
#define MCF_GPIO_PAR_QSPI_PAR_PCS1_SDRAMC (0x80)
|
||||
#define MCF_GPIO_PAR_QSPI_PAR_PCS1_QSPI (0xC0)
|
||||
#define MCF_GPIO_PAR_QSPI_PAR_DIN_GPIO (0x00)
|
||||
#define MCF_GPIO_PAR_QSPI_PAR_DIN_I2C (0x10)
|
||||
#define MCF_GPIO_PAR_QSPI_PAR_DIN_QSPI (0x1C)
|
||||
#define MCF_GPIO_PAR_QSPI_PAR_SCK_GPIO (0x00)
|
||||
#define MCF_GPIO_PAR_QSPI_PAR_SCK_I2C (0x02)
|
||||
#define MCF_GPIO_PAR_QSPI_PAR_SCK_QSPI (0x03)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T0OUT(x) (((x)&0x0003)<<0)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T1OUT(x) (((x)&0x0003)<<2)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T2OUT(x) (((x)&0x0003)<<4)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T3OUT(x) (((x)&0x0003)<<6)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T0IN(x) (((x)&0x0003)<<8)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T1IN(x) (((x)&0x0003)<<10)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T2IN(x) (((x)&0x0003)<<12)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T3IN(x) (((x)&0x0003)<<14)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T3IN_GPIO (0x0000)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T3IN_QSPI (0x4000)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T3IN_UART2 (0x8000)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T3IN_T3IN (0xC000)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T2IN_GPIO (0x0000)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T2IN_T2OUT (0x1000)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T2IN_DMA (0x2000)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T2IN_T2IN (0x3000)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T1IN_GPIO (0x0000)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T1IN_T1OUT (0x0400)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T1IN_DMA (0x0800)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T1IN_T1IN (0x0C00)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T0IN_GPIO (0x0000)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T0IN_DMA (0x0200)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T0IN_T0IN (0x0300)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_GPIO (0x0000)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_QSPI (0x0040)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_UART2 (0x0080)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_T3OUT (0x00C0)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T2OUT_GPIO (0x0000)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T2OUT_DMA (0x0020)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T2OUT_T2OUT (0x0030)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T1OUT_GPIO (0x0000)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T1OUT_DMA (0x0008)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T1OUT_T1OUT (0x000C)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T0OUT_GPIO (0x0000)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T0OUT_DMA (0x0002)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T0OUT_T0OUT (0x0003)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PAR_ETPU */
|
||||
#define MCF_GPIO_PAR_ETPU_PAR_LTPU_ODIS (0x01)
|
||||
#define MCF_GPIO_PAR_ETPU_PAR_UTPU_ODIS (0x02)
|
||||
#define MCF_GPIO_PAR_ETPU_PAR_TCRCLK (0x04)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DSCR_EIM */
|
||||
#define MCF_GPIO_DSCR_EIM_DSCR_EIM0 (0x01)
|
||||
#define MCF_GPIO_DSCR_EIM_DSCR_EIM1 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DSCR_ETPU */
|
||||
#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_7_0 (0x01)
|
||||
#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_15_8 (0x04)
|
||||
#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_23_16 (0x10)
|
||||
#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_31_24 (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DSCR_FECI2C */
|
||||
#define MCF_GPIO_DSCR_FECI2C_DSCR_I2C (0x01)
|
||||
#define MCF_GPIO_DSCR_FECI2C_DSCR_FEC (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DSCR_UART */
|
||||
#define MCF_GPIO_DSCR_UART_DSCR_UART0 (0x01)
|
||||
#define MCF_GPIO_DSCR_UART_DSCR_UART1 (0x04)
|
||||
#define MCF_GPIO_DSCR_UART_DSCR_UART2 (0x10)
|
||||
#define MCF_GPIO_DSCR_UART_DSCR_IRQ (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DSCR_QSPI */
|
||||
#define MCF_GPIO_DSCR_QSPI_DSCR_QSPI (0x01)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DSCR_TIMER */
|
||||
#define MCF_GPIO_DSCR_TIMER_DSCR_TIMER (0x01)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_GPIO_H__ */
|
||||
@ -0,0 +1,63 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_i2c.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_I2C_H__
|
||||
#define __MCF523X_I2C_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* I2C Module (I2C)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_I2C_I2AR (*(vuint8 *)(void*)(&__IPSBAR[0x000300]))
|
||||
#define MCF_I2C_I2FDR (*(vuint8 *)(void*)(&__IPSBAR[0x000304]))
|
||||
#define MCF_I2C_I2CR (*(vuint8 *)(void*)(&__IPSBAR[0x000308]))
|
||||
#define MCF_I2C_I2SR (*(vuint8 *)(void*)(&__IPSBAR[0x00030C]))
|
||||
#define MCF_I2C_I2DR (*(vuint8 *)(void*)(&__IPSBAR[0x000310]))
|
||||
#define MCF_I2C_I2ICR (*(vuint8 *)(void*)(&__IPSBAR[0x000320]))
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2AR */
|
||||
#define MCF_I2C_I2AR_ADR(x) (((x)&0x7F)<<1)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2FDR */
|
||||
#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2CR */
|
||||
#define MCF_I2C_I2CR_RSTA (0x04)
|
||||
#define MCF_I2C_I2CR_TXAK (0x08)
|
||||
#define MCF_I2C_I2CR_MTX (0x10)
|
||||
#define MCF_I2C_I2CR_MSTA (0x20)
|
||||
#define MCF_I2C_I2CR_IIEN (0x40)
|
||||
#define MCF_I2C_I2CR_IEN (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2SR */
|
||||
#define MCF_I2C_I2SR_RXAK (0x01)
|
||||
#define MCF_I2C_I2SR_IIF (0x02)
|
||||
#define MCF_I2C_I2SR_SRW (0x04)
|
||||
#define MCF_I2C_I2SR_IAL (0x10)
|
||||
#define MCF_I2C_I2SR_IBB (0x20)
|
||||
#define MCF_I2C_I2SR_IAAS (0x40)
|
||||
#define MCF_I2C_I2SR_ICF (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2ICR */
|
||||
#define MCF_I2C_I2ICR_IE (0x01)
|
||||
#define MCF_I2C_I2ICR_RE (0x02)
|
||||
#define MCF_I2C_I2ICR_TE (0x04)
|
||||
#define MCF_I2C_I2ICR_BNBE (0x08)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_I2C_H__ */
|
||||
@ -0,0 +1,323 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_intc0.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_INTC0_H__
|
||||
#define __MCF523X_INTC0_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Interrupt Controller 0 (INTC0)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_INTC0_IPRH (*(vuint32*)(void*)(&__IPSBAR[0x000C00]))
|
||||
#define MCF_INTC0_IPRL (*(vuint32*)(void*)(&__IPSBAR[0x000C04]))
|
||||
#define MCF_INTC0_IMRH (*(vuint32*)(void*)(&__IPSBAR[0x000C08]))
|
||||
#define MCF_INTC0_IMRL (*(vuint32*)(void*)(&__IPSBAR[0x000C0C]))
|
||||
#define MCF_INTC0_INTFRCH (*(vuint32*)(void*)(&__IPSBAR[0x000C10]))
|
||||
#define MCF_INTC0_INTFRCL (*(vuint32*)(void*)(&__IPSBAR[0x000C14]))
|
||||
#define MCF_INTC0_IRLR (*(vuint8 *)(void*)(&__IPSBAR[0x000C18]))
|
||||
#define MCF_INTC0_IACKLPR (*(vuint8 *)(void*)(&__IPSBAR[0x000C19]))
|
||||
#define MCF_INTC0_ICR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000C40]))
|
||||
#define MCF_INTC0_ICR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000C41]))
|
||||
#define MCF_INTC0_ICR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000C42]))
|
||||
#define MCF_INTC0_ICR3 (*(vuint8 *)(void*)(&__IPSBAR[0x000C43]))
|
||||
#define MCF_INTC0_ICR4 (*(vuint8 *)(void*)(&__IPSBAR[0x000C44]))
|
||||
#define MCF_INTC0_ICR5 (*(vuint8 *)(void*)(&__IPSBAR[0x000C45]))
|
||||
#define MCF_INTC0_ICR6 (*(vuint8 *)(void*)(&__IPSBAR[0x000C46]))
|
||||
#define MCF_INTC0_ICR7 (*(vuint8 *)(void*)(&__IPSBAR[0x000C47]))
|
||||
#define MCF_INTC0_ICR8 (*(vuint8 *)(void*)(&__IPSBAR[0x000C48]))
|
||||
#define MCF_INTC0_ICR9 (*(vuint8 *)(void*)(&__IPSBAR[0x000C49]))
|
||||
#define MCF_INTC0_ICR10 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4A]))
|
||||
#define MCF_INTC0_ICR11 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4B]))
|
||||
#define MCF_INTC0_ICR12 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4C]))
|
||||
#define MCF_INTC0_ICR13 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4D]))
|
||||
#define MCF_INTC0_ICR14 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4E]))
|
||||
#define MCF_INTC0_ICR15 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4F]))
|
||||
#define MCF_INTC0_ICR16 (*(vuint8 *)(void*)(&__IPSBAR[0x000C50]))
|
||||
#define MCF_INTC0_ICR17 (*(vuint8 *)(void*)(&__IPSBAR[0x000C51]))
|
||||
#define MCF_INTC0_ICR18 (*(vuint8 *)(void*)(&__IPSBAR[0x000C52]))
|
||||
#define MCF_INTC0_ICR19 (*(vuint8 *)(void*)(&__IPSBAR[0x000C53]))
|
||||
#define MCF_INTC0_ICR20 (*(vuint8 *)(void*)(&__IPSBAR[0x000C54]))
|
||||
#define MCF_INTC0_ICR21 (*(vuint8 *)(void*)(&__IPSBAR[0x000C55]))
|
||||
#define MCF_INTC0_ICR22 (*(vuint8 *)(void*)(&__IPSBAR[0x000C56]))
|
||||
#define MCF_INTC0_ICR23 (*(vuint8 *)(void*)(&__IPSBAR[0x000C57]))
|
||||
#define MCF_INTC0_ICR24 (*(vuint8 *)(void*)(&__IPSBAR[0x000C58]))
|
||||
#define MCF_INTC0_ICR25 (*(vuint8 *)(void*)(&__IPSBAR[0x000C59]))
|
||||
#define MCF_INTC0_ICR26 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5A]))
|
||||
#define MCF_INTC0_ICR27 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5B]))
|
||||
#define MCF_INTC0_ICR28 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5C]))
|
||||
#define MCF_INTC0_ICR29 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5D]))
|
||||
#define MCF_INTC0_ICR30 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5E]))
|
||||
#define MCF_INTC0_ICR31 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5F]))
|
||||
#define MCF_INTC0_ICR32 (*(vuint8 *)(void*)(&__IPSBAR[0x000C60]))
|
||||
#define MCF_INTC0_ICR33 (*(vuint8 *)(void*)(&__IPSBAR[0x000C61]))
|
||||
#define MCF_INTC0_ICR34 (*(vuint8 *)(void*)(&__IPSBAR[0x000C62]))
|
||||
#define MCF_INTC0_ICR35 (*(vuint8 *)(void*)(&__IPSBAR[0x000C63]))
|
||||
#define MCF_INTC0_ICR36 (*(vuint8 *)(void*)(&__IPSBAR[0x000C64]))
|
||||
#define MCF_INTC0_ICR37 (*(vuint8 *)(void*)(&__IPSBAR[0x000C65]))
|
||||
#define MCF_INTC0_ICR38 (*(vuint8 *)(void*)(&__IPSBAR[0x000C66]))
|
||||
#define MCF_INTC0_ICR39 (*(vuint8 *)(void*)(&__IPSBAR[0x000C67]))
|
||||
#define MCF_INTC0_ICR40 (*(vuint8 *)(void*)(&__IPSBAR[0x000C68]))
|
||||
#define MCF_INTC0_ICR41 (*(vuint8 *)(void*)(&__IPSBAR[0x000C69]))
|
||||
#define MCF_INTC0_ICR42 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6A]))
|
||||
#define MCF_INTC0_ICR43 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6B]))
|
||||
#define MCF_INTC0_ICR44 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6C]))
|
||||
#define MCF_INTC0_ICR45 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6D]))
|
||||
#define MCF_INTC0_ICR46 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6E]))
|
||||
#define MCF_INTC0_ICR47 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6F]))
|
||||
#define MCF_INTC0_ICR48 (*(vuint8 *)(void*)(&__IPSBAR[0x000C70]))
|
||||
#define MCF_INTC0_ICR49 (*(vuint8 *)(void*)(&__IPSBAR[0x000C71]))
|
||||
#define MCF_INTC0_ICR50 (*(vuint8 *)(void*)(&__IPSBAR[0x000C72]))
|
||||
#define MCF_INTC0_ICR51 (*(vuint8 *)(void*)(&__IPSBAR[0x000C73]))
|
||||
#define MCF_INTC0_ICR52 (*(vuint8 *)(void*)(&__IPSBAR[0x000C74]))
|
||||
#define MCF_INTC0_ICR53 (*(vuint8 *)(void*)(&__IPSBAR[0x000C75]))
|
||||
#define MCF_INTC0_ICR54 (*(vuint8 *)(void*)(&__IPSBAR[0x000C76]))
|
||||
#define MCF_INTC0_ICR55 (*(vuint8 *)(void*)(&__IPSBAR[0x000C77]))
|
||||
#define MCF_INTC0_ICR56 (*(vuint8 *)(void*)(&__IPSBAR[0x000C78]))
|
||||
#define MCF_INTC0_ICR57 (*(vuint8 *)(void*)(&__IPSBAR[0x000C79]))
|
||||
#define MCF_INTC0_ICR58 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7A]))
|
||||
#define MCF_INTC0_ICR59 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7B]))
|
||||
#define MCF_INTC0_ICR60 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7C]))
|
||||
#define MCF_INTC0_ICR61 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7D]))
|
||||
#define MCF_INTC0_ICR62 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7E]))
|
||||
#define MCF_INTC0_ICR63 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7F]))
|
||||
#define MCF_INTC0_ICRn(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000C40+((x)*0x001)]))
|
||||
#define MCF_INTC0_SWIACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CE0]))
|
||||
#define MCF_INTC0_L1IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CE4]))
|
||||
#define MCF_INTC0_L2IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CE8]))
|
||||
#define MCF_INTC0_L3IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CEC]))
|
||||
#define MCF_INTC0_L4IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CF0]))
|
||||
#define MCF_INTC0_L5IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CF4]))
|
||||
#define MCF_INTC0_L6IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CF8]))
|
||||
#define MCF_INTC0_L7IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CFC]))
|
||||
#define MCF_INTC0_LnIACK(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000CE4+((x)*0x004)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_IPRH */
|
||||
#define MCF_INTC0_IPRH_INT32 (0x00000001)
|
||||
#define MCF_INTC0_IPRH_INT33 (0x00000002)
|
||||
#define MCF_INTC0_IPRH_INT34 (0x00000004)
|
||||
#define MCF_INTC0_IPRH_INT35 (0x00000008)
|
||||
#define MCF_INTC0_IPRH_INT36 (0x00000010)
|
||||
#define MCF_INTC0_IPRH_INT37 (0x00000020)
|
||||
#define MCF_INTC0_IPRH_INT38 (0x00000040)
|
||||
#define MCF_INTC0_IPRH_INT39 (0x00000080)
|
||||
#define MCF_INTC0_IPRH_INT40 (0x00000100)
|
||||
#define MCF_INTC0_IPRH_INT41 (0x00000200)
|
||||
#define MCF_INTC0_IPRH_INT42 (0x00000400)
|
||||
#define MCF_INTC0_IPRH_INT43 (0x00000800)
|
||||
#define MCF_INTC0_IPRH_INT44 (0x00001000)
|
||||
#define MCF_INTC0_IPRH_INT45 (0x00002000)
|
||||
#define MCF_INTC0_IPRH_INT46 (0x00004000)
|
||||
#define MCF_INTC0_IPRH_INT47 (0x00008000)
|
||||
#define MCF_INTC0_IPRH_INT48 (0x00010000)
|
||||
#define MCF_INTC0_IPRH_INT49 (0x00020000)
|
||||
#define MCF_INTC0_IPRH_INT50 (0x00040000)
|
||||
#define MCF_INTC0_IPRH_INT51 (0x00080000)
|
||||
#define MCF_INTC0_IPRH_INT52 (0x00100000)
|
||||
#define MCF_INTC0_IPRH_INT53 (0x00200000)
|
||||
#define MCF_INTC0_IPRH_INT54 (0x00400000)
|
||||
#define MCF_INTC0_IPRH_INT55 (0x00800000)
|
||||
#define MCF_INTC0_IPRH_INT56 (0x01000000)
|
||||
#define MCF_INTC0_IPRH_INT57 (0x02000000)
|
||||
#define MCF_INTC0_IPRH_INT58 (0x04000000)
|
||||
#define MCF_INTC0_IPRH_INT59 (0x08000000)
|
||||
#define MCF_INTC0_IPRH_INT60 (0x10000000)
|
||||
#define MCF_INTC0_IPRH_INT61 (0x20000000)
|
||||
#define MCF_INTC0_IPRH_INT62 (0x40000000)
|
||||
#define MCF_INTC0_IPRH_INT63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_IPRL */
|
||||
#define MCF_INTC0_IPRL_INT1 (0x00000002)
|
||||
#define MCF_INTC0_IPRL_INT2 (0x00000004)
|
||||
#define MCF_INTC0_IPRL_INT3 (0x00000008)
|
||||
#define MCF_INTC0_IPRL_INT4 (0x00000010)
|
||||
#define MCF_INTC0_IPRL_INT5 (0x00000020)
|
||||
#define MCF_INTC0_IPRL_INT6 (0x00000040)
|
||||
#define MCF_INTC0_IPRL_INT7 (0x00000080)
|
||||
#define MCF_INTC0_IPRL_INT8 (0x00000100)
|
||||
#define MCF_INTC0_IPRL_INT9 (0x00000200)
|
||||
#define MCF_INTC0_IPRL_INT10 (0x00000400)
|
||||
#define MCF_INTC0_IPRL_INT11 (0x00000800)
|
||||
#define MCF_INTC0_IPRL_INT12 (0x00001000)
|
||||
#define MCF_INTC0_IPRL_INT13 (0x00002000)
|
||||
#define MCF_INTC0_IPRL_INT14 (0x00004000)
|
||||
#define MCF_INTC0_IPRL_INT15 (0x00008000)
|
||||
#define MCF_INTC0_IPRL_INT16 (0x00010000)
|
||||
#define MCF_INTC0_IPRL_INT17 (0x00020000)
|
||||
#define MCF_INTC0_IPRL_INT18 (0x00040000)
|
||||
#define MCF_INTC0_IPRL_INT19 (0x00080000)
|
||||
#define MCF_INTC0_IPRL_INT20 (0x00100000)
|
||||
#define MCF_INTC0_IPRL_INT21 (0x00200000)
|
||||
#define MCF_INTC0_IPRL_INT22 (0x00400000)
|
||||
#define MCF_INTC0_IPRL_INT23 (0x00800000)
|
||||
#define MCF_INTC0_IPRL_INT24 (0x01000000)
|
||||
#define MCF_INTC0_IPRL_INT25 (0x02000000)
|
||||
#define MCF_INTC0_IPRL_INT26 (0x04000000)
|
||||
#define MCF_INTC0_IPRL_INT27 (0x08000000)
|
||||
#define MCF_INTC0_IPRL_INT28 (0x10000000)
|
||||
#define MCF_INTC0_IPRL_INT29 (0x20000000)
|
||||
#define MCF_INTC0_IPRL_INT30 (0x40000000)
|
||||
#define MCF_INTC0_IPRL_INT31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_IMRH */
|
||||
#define MCF_INTC0_IMRH_INT_MASK32 (0x00000001)
|
||||
#define MCF_INTC0_IMRH_INT_MASK33 (0x00000002)
|
||||
#define MCF_INTC0_IMRH_INT_MASK34 (0x00000004)
|
||||
#define MCF_INTC0_IMRH_INT_MASK35 (0x00000008)
|
||||
#define MCF_INTC0_IMRH_INT_MASK36 (0x00000010)
|
||||
#define MCF_INTC0_IMRH_INT_MASK37 (0x00000020)
|
||||
#define MCF_INTC0_IMRH_INT_MASK38 (0x00000040)
|
||||
#define MCF_INTC0_IMRH_INT_MASK39 (0x00000080)
|
||||
#define MCF_INTC0_IMRH_INT_MASK40 (0x00000100)
|
||||
#define MCF_INTC0_IMRH_INT_MASK41 (0x00000200)
|
||||
#define MCF_INTC0_IMRH_INT_MASK42 (0x00000400)
|
||||
#define MCF_INTC0_IMRH_INT_MASK43 (0x00000800)
|
||||
#define MCF_INTC0_IMRH_INT_MASK44 (0x00001000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK45 (0x00002000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK46 (0x00004000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK47 (0x00008000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK48 (0x00010000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK49 (0x00020000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK50 (0x00040000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK51 (0x00080000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK52 (0x00100000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK53 (0x00200000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK54 (0x00400000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK55 (0x00800000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK56 (0x01000000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK57 (0x02000000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK58 (0x04000000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK59 (0x08000000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK60 (0x10000000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK61 (0x20000000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK62 (0x40000000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_IMRL */
|
||||
#define MCF_INTC0_IMRL_MASKALL (0x00000001)
|
||||
#define MCF_INTC0_IMRL_INT_MASK1 (0x00000002)
|
||||
#define MCF_INTC0_IMRL_INT_MASK2 (0x00000004)
|
||||
#define MCF_INTC0_IMRL_INT_MASK3 (0x00000008)
|
||||
#define MCF_INTC0_IMRL_INT_MASK4 (0x00000010)
|
||||
#define MCF_INTC0_IMRL_INT_MASK5 (0x00000020)
|
||||
#define MCF_INTC0_IMRL_INT_MASK6 (0x00000040)
|
||||
#define MCF_INTC0_IMRL_INT_MASK7 (0x00000080)
|
||||
#define MCF_INTC0_IMRL_INT_MASK8 (0x00000100)
|
||||
#define MCF_INTC0_IMRL_INT_MASK9 (0x00000200)
|
||||
#define MCF_INTC0_IMRL_INT_MASK10 (0x00000400)
|
||||
#define MCF_INTC0_IMRL_INT_MASK11 (0x00000800)
|
||||
#define MCF_INTC0_IMRL_INT_MASK12 (0x00001000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK13 (0x00002000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK14 (0x00004000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK15 (0x00008000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK16 (0x00010000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK17 (0x00020000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK18 (0x00040000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK19 (0x00080000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK20 (0x00100000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK21 (0x00200000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK22 (0x00400000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK23 (0x00800000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK24 (0x01000000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK25 (0x02000000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK26 (0x04000000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK27 (0x08000000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK28 (0x10000000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK29 (0x20000000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK30 (0x40000000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_INTFRCH */
|
||||
#define MCF_INTC0_INTFRCH_INTFRC32 (0x00000001)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC33 (0x00000002)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC34 (0x00000004)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC35 (0x00000008)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC36 (0x00000010)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC37 (0x00000020)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC38 (0x00000040)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC39 (0x00000080)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC40 (0x00000100)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC41 (0x00000200)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC42 (0x00000400)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC43 (0x00000800)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC44 (0x00001000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC45 (0x00002000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC46 (0x00004000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC47 (0x00008000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC48 (0x00010000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC49 (0x00020000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC50 (0x00040000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC51 (0x00080000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC52 (0x00100000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC53 (0x00200000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC54 (0x00400000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC55 (0x00800000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC56 (0x01000000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC57 (0x02000000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC58 (0x04000000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC59 (0x08000000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC60 (0x10000000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC61 (0x20000000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC62 (0x40000000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_INTFRCL */
|
||||
#define MCF_INTC0_INTFRCL_INTFRC1 (0x00000002)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC2 (0x00000004)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC3 (0x00000008)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC4 (0x00000010)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC5 (0x00000020)
|
||||
#define MCF_INTC0_INTFRCL_INT6 (0x00000040)
|
||||
#define MCF_INTC0_INTFRCL_INT7 (0x00000080)
|
||||
#define MCF_INTC0_INTFRCL_INT8 (0x00000100)
|
||||
#define MCF_INTC0_INTFRCL_INT9 (0x00000200)
|
||||
#define MCF_INTC0_INTFRCL_INT10 (0x00000400)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC11 (0x00000800)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC12 (0x00001000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC13 (0x00002000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC14 (0x00004000)
|
||||
#define MCF_INTC0_INTFRCL_INT15 (0x00008000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC16 (0x00010000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC17 (0x00020000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC18 (0x00040000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC19 (0x00080000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC20 (0x00100000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC21 (0x00200000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC22 (0x00400000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC23 (0x00800000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC24 (0x01000000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC25 (0x02000000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC26 (0x04000000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC27 (0x08000000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC28 (0x10000000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC29 (0x20000000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC30 (0x40000000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_IRLR */
|
||||
#define MCF_INTC0_IRLR_IRQ(x) (((x)&0x7F)<<1)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_IACKLPR */
|
||||
#define MCF_INTC0_IACKLPR_PRI(x) (((x)&0x0F)<<0)
|
||||
#define MCF_INTC0_IACKLPR_LEVEL(x) (((x)&0x07)<<4)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_ICRn */
|
||||
#define MCF_INTC0_ICRn_IP(x) (((x)&0x07)<<0)
|
||||
#define MCF_INTC0_ICRn_IL(x) (((x)&0x07)<<3)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_INTC0_H__ */
|
||||
@ -0,0 +1,323 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_intc1.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_INTC1_H__
|
||||
#define __MCF523X_INTC1_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Interrupt Controller 1 (INTC1)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_INTC1_IPRH (*(vuint32*)(void*)(&__IPSBAR[0x000D00]))
|
||||
#define MCF_INTC1_IPRL (*(vuint32*)(void*)(&__IPSBAR[0x000D04]))
|
||||
#define MCF_INTC1_IMRH (*(vuint32*)(void*)(&__IPSBAR[0x000D08]))
|
||||
#define MCF_INTC1_IMRL (*(vuint32*)(void*)(&__IPSBAR[0x000D0C]))
|
||||
#define MCF_INTC1_INTFRCH (*(vuint32*)(void*)(&__IPSBAR[0x000D10]))
|
||||
#define MCF_INTC1_INTFRCL (*(vuint32*)(void*)(&__IPSBAR[0x000D14]))
|
||||
#define MCF_INTC1_IRLR (*(vuint8 *)(void*)(&__IPSBAR[0x000D18]))
|
||||
#define MCF_INTC1_IACKLPR (*(vuint8 *)(void*)(&__IPSBAR[0x000D19]))
|
||||
#define MCF_INTC1_ICR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000D40]))
|
||||
#define MCF_INTC1_ICR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000D41]))
|
||||
#define MCF_INTC1_ICR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000D42]))
|
||||
#define MCF_INTC1_ICR3 (*(vuint8 *)(void*)(&__IPSBAR[0x000D43]))
|
||||
#define MCF_INTC1_ICR4 (*(vuint8 *)(void*)(&__IPSBAR[0x000D44]))
|
||||
#define MCF_INTC1_ICR5 (*(vuint8 *)(void*)(&__IPSBAR[0x000D45]))
|
||||
#define MCF_INTC1_ICR6 (*(vuint8 *)(void*)(&__IPSBAR[0x000D46]))
|
||||
#define MCF_INTC1_ICR7 (*(vuint8 *)(void*)(&__IPSBAR[0x000D47]))
|
||||
#define MCF_INTC1_ICR8 (*(vuint8 *)(void*)(&__IPSBAR[0x000D48]))
|
||||
#define MCF_INTC1_ICR9 (*(vuint8 *)(void*)(&__IPSBAR[0x000D49]))
|
||||
#define MCF_INTC1_ICR10 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4A]))
|
||||
#define MCF_INTC1_ICR11 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4B]))
|
||||
#define MCF_INTC1_ICR12 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4C]))
|
||||
#define MCF_INTC1_ICR13 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4D]))
|
||||
#define MCF_INTC1_ICR14 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4E]))
|
||||
#define MCF_INTC1_ICR15 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4F]))
|
||||
#define MCF_INTC1_ICR16 (*(vuint8 *)(void*)(&__IPSBAR[0x000D50]))
|
||||
#define MCF_INTC1_ICR17 (*(vuint8 *)(void*)(&__IPSBAR[0x000D51]))
|
||||
#define MCF_INTC1_ICR18 (*(vuint8 *)(void*)(&__IPSBAR[0x000D52]))
|
||||
#define MCF_INTC1_ICR19 (*(vuint8 *)(void*)(&__IPSBAR[0x000D53]))
|
||||
#define MCF_INTC1_ICR20 (*(vuint8 *)(void*)(&__IPSBAR[0x000D54]))
|
||||
#define MCF_INTC1_ICR21 (*(vuint8 *)(void*)(&__IPSBAR[0x000D55]))
|
||||
#define MCF_INTC1_ICR22 (*(vuint8 *)(void*)(&__IPSBAR[0x000D56]))
|
||||
#define MCF_INTC1_ICR23 (*(vuint8 *)(void*)(&__IPSBAR[0x000D57]))
|
||||
#define MCF_INTC1_ICR24 (*(vuint8 *)(void*)(&__IPSBAR[0x000D58]))
|
||||
#define MCF_INTC1_ICR25 (*(vuint8 *)(void*)(&__IPSBAR[0x000D59]))
|
||||
#define MCF_INTC1_ICR26 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5A]))
|
||||
#define MCF_INTC1_ICR27 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5B]))
|
||||
#define MCF_INTC1_ICR28 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5C]))
|
||||
#define MCF_INTC1_ICR29 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5D]))
|
||||
#define MCF_INTC1_ICR30 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5E]))
|
||||
#define MCF_INTC1_ICR31 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5F]))
|
||||
#define MCF_INTC1_ICR32 (*(vuint8 *)(void*)(&__IPSBAR[0x000D60]))
|
||||
#define MCF_INTC1_ICR33 (*(vuint8 *)(void*)(&__IPSBAR[0x000D61]))
|
||||
#define MCF_INTC1_ICR34 (*(vuint8 *)(void*)(&__IPSBAR[0x000D62]))
|
||||
#define MCF_INTC1_ICR35 (*(vuint8 *)(void*)(&__IPSBAR[0x000D63]))
|
||||
#define MCF_INTC1_ICR36 (*(vuint8 *)(void*)(&__IPSBAR[0x000D64]))
|
||||
#define MCF_INTC1_ICR37 (*(vuint8 *)(void*)(&__IPSBAR[0x000D65]))
|
||||
#define MCF_INTC1_ICR38 (*(vuint8 *)(void*)(&__IPSBAR[0x000D66]))
|
||||
#define MCF_INTC1_ICR39 (*(vuint8 *)(void*)(&__IPSBAR[0x000D67]))
|
||||
#define MCF_INTC1_ICR40 (*(vuint8 *)(void*)(&__IPSBAR[0x000D68]))
|
||||
#define MCF_INTC1_ICR41 (*(vuint8 *)(void*)(&__IPSBAR[0x000D69]))
|
||||
#define MCF_INTC1_ICR42 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6A]))
|
||||
#define MCF_INTC1_ICR43 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6B]))
|
||||
#define MCF_INTC1_ICR44 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6C]))
|
||||
#define MCF_INTC1_ICR45 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6D]))
|
||||
#define MCF_INTC1_ICR46 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6E]))
|
||||
#define MCF_INTC1_ICR47 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6F]))
|
||||
#define MCF_INTC1_ICR48 (*(vuint8 *)(void*)(&__IPSBAR[0x000D70]))
|
||||
#define MCF_INTC1_ICR49 (*(vuint8 *)(void*)(&__IPSBAR[0x000D71]))
|
||||
#define MCF_INTC1_ICR50 (*(vuint8 *)(void*)(&__IPSBAR[0x000D72]))
|
||||
#define MCF_INTC1_ICR51 (*(vuint8 *)(void*)(&__IPSBAR[0x000D73]))
|
||||
#define MCF_INTC1_ICR52 (*(vuint8 *)(void*)(&__IPSBAR[0x000D74]))
|
||||
#define MCF_INTC1_ICR53 (*(vuint8 *)(void*)(&__IPSBAR[0x000D75]))
|
||||
#define MCF_INTC1_ICR54 (*(vuint8 *)(void*)(&__IPSBAR[0x000D76]))
|
||||
#define MCF_INTC1_ICR55 (*(vuint8 *)(void*)(&__IPSBAR[0x000D77]))
|
||||
#define MCF_INTC1_ICR56 (*(vuint8 *)(void*)(&__IPSBAR[0x000D78]))
|
||||
#define MCF_INTC1_ICR57 (*(vuint8 *)(void*)(&__IPSBAR[0x000D79]))
|
||||
#define MCF_INTC1_ICR58 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7A]))
|
||||
#define MCF_INTC1_ICR59 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7B]))
|
||||
#define MCF_INTC1_ICR60 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7C]))
|
||||
#define MCF_INTC1_ICR61 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7D]))
|
||||
#define MCF_INTC1_ICR62 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7E]))
|
||||
#define MCF_INTC1_ICR63 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7F]))
|
||||
#define MCF_INTC1_ICRn(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000D40+((x)*0x001)]))
|
||||
#define MCF_INTC1_SWIACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DE0]))
|
||||
#define MCF_INTC1_L1IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DE4]))
|
||||
#define MCF_INTC1_L2IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DE8]))
|
||||
#define MCF_INTC1_L3IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DEC]))
|
||||
#define MCF_INTC1_L4IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DF0]))
|
||||
#define MCF_INTC1_L5IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DF4]))
|
||||
#define MCF_INTC1_L6IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DF8]))
|
||||
#define MCF_INTC1_L7IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DFC]))
|
||||
#define MCF_INTC1_LnIACK(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000DE4+((x)*0x004)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_IPRH */
|
||||
#define MCF_INTC1_IPRH_INT32 (0x00000001)
|
||||
#define MCF_INTC1_IPRH_INT33 (0x00000002)
|
||||
#define MCF_INTC1_IPRH_INT34 (0x00000004)
|
||||
#define MCF_INTC1_IPRH_INT35 (0x00000008)
|
||||
#define MCF_INTC1_IPRH_INT36 (0x00000010)
|
||||
#define MCF_INTC1_IPRH_INT37 (0x00000020)
|
||||
#define MCF_INTC1_IPRH_INT38 (0x00000040)
|
||||
#define MCF_INTC1_IPRH_INT39 (0x00000080)
|
||||
#define MCF_INTC1_IPRH_INT40 (0x00000100)
|
||||
#define MCF_INTC1_IPRH_INT41 (0x00000200)
|
||||
#define MCF_INTC1_IPRH_INT42 (0x00000400)
|
||||
#define MCF_INTC1_IPRH_INT43 (0x00000800)
|
||||
#define MCF_INTC1_IPRH_INT44 (0x00001000)
|
||||
#define MCF_INTC1_IPRH_INT45 (0x00002000)
|
||||
#define MCF_INTC1_IPRH_INT46 (0x00004000)
|
||||
#define MCF_INTC1_IPRH_INT47 (0x00008000)
|
||||
#define MCF_INTC1_IPRH_INT48 (0x00010000)
|
||||
#define MCF_INTC1_IPRH_INT49 (0x00020000)
|
||||
#define MCF_INTC1_IPRH_INT50 (0x00040000)
|
||||
#define MCF_INTC1_IPRH_INT51 (0x00080000)
|
||||
#define MCF_INTC1_IPRH_INT52 (0x00100000)
|
||||
#define MCF_INTC1_IPRH_INT53 (0x00200000)
|
||||
#define MCF_INTC1_IPRH_INT54 (0x00400000)
|
||||
#define MCF_INTC1_IPRH_INT55 (0x00800000)
|
||||
#define MCF_INTC1_IPRH_INT56 (0x01000000)
|
||||
#define MCF_INTC1_IPRH_INT57 (0x02000000)
|
||||
#define MCF_INTC1_IPRH_INT58 (0x04000000)
|
||||
#define MCF_INTC1_IPRH_INT59 (0x08000000)
|
||||
#define MCF_INTC1_IPRH_INT60 (0x10000000)
|
||||
#define MCF_INTC1_IPRH_INT61 (0x20000000)
|
||||
#define MCF_INTC1_IPRH_INT62 (0x40000000)
|
||||
#define MCF_INTC1_IPRH_INT63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_IPRL */
|
||||
#define MCF_INTC1_IPRL_INT1 (0x00000002)
|
||||
#define MCF_INTC1_IPRL_INT2 (0x00000004)
|
||||
#define MCF_INTC1_IPRL_INT3 (0x00000008)
|
||||
#define MCF_INTC1_IPRL_INT4 (0x00000010)
|
||||
#define MCF_INTC1_IPRL_INT5 (0x00000020)
|
||||
#define MCF_INTC1_IPRL_INT6 (0x00000040)
|
||||
#define MCF_INTC1_IPRL_INT7 (0x00000080)
|
||||
#define MCF_INTC1_IPRL_INT8 (0x00000100)
|
||||
#define MCF_INTC1_IPRL_INT9 (0x00000200)
|
||||
#define MCF_INTC1_IPRL_INT10 (0x00000400)
|
||||
#define MCF_INTC1_IPRL_INT11 (0x00000800)
|
||||
#define MCF_INTC1_IPRL_INT12 (0x00001000)
|
||||
#define MCF_INTC1_IPRL_INT13 (0x00002000)
|
||||
#define MCF_INTC1_IPRL_INT14 (0x00004000)
|
||||
#define MCF_INTC1_IPRL_INT15 (0x00008000)
|
||||
#define MCF_INTC1_IPRL_INT16 (0x00010000)
|
||||
#define MCF_INTC1_IPRL_INT17 (0x00020000)
|
||||
#define MCF_INTC1_IPRL_INT18 (0x00040000)
|
||||
#define MCF_INTC1_IPRL_INT19 (0x00080000)
|
||||
#define MCF_INTC1_IPRL_INT20 (0x00100000)
|
||||
#define MCF_INTC1_IPRL_INT21 (0x00200000)
|
||||
#define MCF_INTC1_IPRL_INT22 (0x00400000)
|
||||
#define MCF_INTC1_IPRL_INT23 (0x00800000)
|
||||
#define MCF_INTC1_IPRL_INT24 (0x01000000)
|
||||
#define MCF_INTC1_IPRL_INT25 (0x02000000)
|
||||
#define MCF_INTC1_IPRL_INT26 (0x04000000)
|
||||
#define MCF_INTC1_IPRL_INT27 (0x08000000)
|
||||
#define MCF_INTC1_IPRL_INT28 (0x10000000)
|
||||
#define MCF_INTC1_IPRL_INT29 (0x20000000)
|
||||
#define MCF_INTC1_IPRL_INT30 (0x40000000)
|
||||
#define MCF_INTC1_IPRL_INT31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_IMRH */
|
||||
#define MCF_INTC1_IMRH_INT_MASK32 (0x00000001)
|
||||
#define MCF_INTC1_IMRH_INT_MASK33 (0x00000002)
|
||||
#define MCF_INTC1_IMRH_INT_MASK34 (0x00000004)
|
||||
#define MCF_INTC1_IMRH_INT_MASK35 (0x00000008)
|
||||
#define MCF_INTC1_IMRH_INT_MASK36 (0x00000010)
|
||||
#define MCF_INTC1_IMRH_INT_MASK37 (0x00000020)
|
||||
#define MCF_INTC1_IMRH_INT_MASK38 (0x00000040)
|
||||
#define MCF_INTC1_IMRH_INT_MASK39 (0x00000080)
|
||||
#define MCF_INTC1_IMRH_INT_MASK40 (0x00000100)
|
||||
#define MCF_INTC1_IMRH_INT_MASK41 (0x00000200)
|
||||
#define MCF_INTC1_IMRH_INT_MASK42 (0x00000400)
|
||||
#define MCF_INTC1_IMRH_INT_MASK43 (0x00000800)
|
||||
#define MCF_INTC1_IMRH_INT_MASK44 (0x00001000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK45 (0x00002000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK46 (0x00004000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK47 (0x00008000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK48 (0x00010000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK49 (0x00020000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK50 (0x00040000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK51 (0x00080000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK52 (0x00100000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK53 (0x00200000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK54 (0x00400000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK55 (0x00800000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK56 (0x01000000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK57 (0x02000000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK58 (0x04000000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK59 (0x08000000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK60 (0x10000000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK61 (0x20000000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK62 (0x40000000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_IMRL */
|
||||
#define MCF_INTC1_IMRL_MASKALL (0x00000001)
|
||||
#define MCF_INTC1_IMRL_INT_MASK1 (0x00000002)
|
||||
#define MCF_INTC1_IMRL_INT_MASK2 (0x00000004)
|
||||
#define MCF_INTC1_IMRL_INT_MASK3 (0x00000008)
|
||||
#define MCF_INTC1_IMRL_INT_MASK4 (0x00000010)
|
||||
#define MCF_INTC1_IMRL_INT_MASK5 (0x00000020)
|
||||
#define MCF_INTC1_IMRL_INT_MASK6 (0x00000040)
|
||||
#define MCF_INTC1_IMRL_INT_MASK7 (0x00000080)
|
||||
#define MCF_INTC1_IMRL_INT_MASK8 (0x00000100)
|
||||
#define MCF_INTC1_IMRL_INT_MASK9 (0x00000200)
|
||||
#define MCF_INTC1_IMRL_INT_MASK10 (0x00000400)
|
||||
#define MCF_INTC1_IMRL_INT_MASK11 (0x00000800)
|
||||
#define MCF_INTC1_IMRL_INT_MASK12 (0x00001000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK13 (0x00002000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK14 (0x00004000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK15 (0x00008000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK16 (0x00010000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK17 (0x00020000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK18 (0x00040000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK19 (0x00080000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK20 (0x00100000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK21 (0x00200000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK22 (0x00400000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK23 (0x00800000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK24 (0x01000000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK25 (0x02000000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK26 (0x04000000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK27 (0x08000000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK28 (0x10000000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK29 (0x20000000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK30 (0x40000000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_INTFRCH */
|
||||
#define MCF_INTC1_INTFRCH_INTFRC32 (0x00000001)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC33 (0x00000002)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC34 (0x00000004)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC35 (0x00000008)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC36 (0x00000010)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC37 (0x00000020)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC38 (0x00000040)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC39 (0x00000080)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC40 (0x00000100)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC41 (0x00000200)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC42 (0x00000400)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC43 (0x00000800)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC44 (0x00001000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC45 (0x00002000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC46 (0x00004000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC47 (0x00008000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC48 (0x00010000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC49 (0x00020000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC50 (0x00040000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC51 (0x00080000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC52 (0x00100000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC53 (0x00200000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC54 (0x00400000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC55 (0x00800000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC56 (0x01000000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC57 (0x02000000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC58 (0x04000000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC59 (0x08000000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC60 (0x10000000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC61 (0x20000000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC62 (0x40000000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_INTFRCL */
|
||||
#define MCF_INTC1_INTFRCL_INTFRC1 (0x00000002)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC2 (0x00000004)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC3 (0x00000008)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC4 (0x00000010)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC5 (0x00000020)
|
||||
#define MCF_INTC1_INTFRCL_INT6 (0x00000040)
|
||||
#define MCF_INTC1_INTFRCL_INT7 (0x00000080)
|
||||
#define MCF_INTC1_INTFRCL_INT8 (0x00000100)
|
||||
#define MCF_INTC1_INTFRCL_INT9 (0x00000200)
|
||||
#define MCF_INTC1_INTFRCL_INT10 (0x00000400)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC11 (0x00000800)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC12 (0x00001000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC13 (0x00002000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC14 (0x00004000)
|
||||
#define MCF_INTC1_INTFRCL_INT15 (0x00008000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC16 (0x00010000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC17 (0x00020000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC18 (0x00040000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC19 (0x00080000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC20 (0x00100000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC21 (0x00200000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC22 (0x00400000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC23 (0x00800000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC24 (0x01000000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC25 (0x02000000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC26 (0x04000000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC27 (0x08000000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC28 (0x10000000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC29 (0x20000000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC30 (0x40000000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_IRLR */
|
||||
#define MCF_INTC1_IRLR_IRQ(x) (((x)&0x7F)<<1)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_IACKLPR */
|
||||
#define MCF_INTC1_IACKLPR_PRI(x) (((x)&0x0F)<<0)
|
||||
#define MCF_INTC1_IACKLPR_LEVEL(x) (((x)&0x07)<<4)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_ICRn */
|
||||
#define MCF_INTC1_ICRn_IP(x) (((x)&0x07)<<0)
|
||||
#define MCF_INTC1_ICRn_IL(x) (((x)&0x07)<<3)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_INTC1_H__ */
|
||||
@ -0,0 +1,101 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_mdha.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_MDHA_H__
|
||||
#define __MCF523X_MDHA_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Message Digest Hardware Accelerator (MDHA)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_MDHA_MDMR (*(vuint32*)(void*)(&__IPSBAR[0x190000]))
|
||||
#define MCF_MDHA_MDCR (*(vuint32*)(void*)(&__IPSBAR[0x190004]))
|
||||
#define MCF_MDHA_MDCMR (*(vuint32*)(void*)(&__IPSBAR[0x190008]))
|
||||
#define MCF_MDHA_MDSR (*(vuint32*)(void*)(&__IPSBAR[0x19000C]))
|
||||
#define MCF_MDHA_MDISR (*(vuint32*)(void*)(&__IPSBAR[0x190010]))
|
||||
#define MCF_MDHA_MDIMR (*(vuint32*)(void*)(&__IPSBAR[0x190014]))
|
||||
#define MCF_MDHA_MDDSR (*(vuint32*)(void*)(&__IPSBAR[0x19001C]))
|
||||
#define MCF_MDHA_MDIN (*(vuint32*)(void*)(&__IPSBAR[0x190020]))
|
||||
#define MCF_MDHA_MDA0 (*(vuint32*)(void*)(&__IPSBAR[0x190030]))
|
||||
#define MCF_MDHA_MDB0 (*(vuint32*)(void*)(&__IPSBAR[0x190034]))
|
||||
#define MCF_MDHA_MDC0 (*(vuint32*)(void*)(&__IPSBAR[0x190038]))
|
||||
#define MCF_MDHA_MDD0 (*(vuint32*)(void*)(&__IPSBAR[0x19003C]))
|
||||
#define MCF_MDHA_MDE0 (*(vuint32*)(void*)(&__IPSBAR[0x190040]))
|
||||
#define MCF_MDHA_MDMDS (*(vuint32*)(void*)(&__IPSBAR[0x190044]))
|
||||
#define MCF_MDHA_MDA1 (*(vuint32*)(void*)(&__IPSBAR[0x190070]))
|
||||
#define MCF_MDHA_MDB1 (*(vuint32*)(void*)(&__IPSBAR[0x190074]))
|
||||
#define MCF_MDHA_MDC1 (*(vuint32*)(void*)(&__IPSBAR[0x190078]))
|
||||
#define MCF_MDHA_MDD1 (*(vuint32*)(void*)(&__IPSBAR[0x19007C]))
|
||||
#define MCF_MDHA_MDE1 (*(vuint32*)(void*)(&__IPSBAR[0x190080]))
|
||||
|
||||
/* Bit definitions and macros for MCF_MDHA_MDMR */
|
||||
#define MCF_MDHA_MDMR_ALG (0x00000001)
|
||||
#define MCF_MDHA_MDMR_PDATA (0x00000004)
|
||||
#define MCF_MDHA_MDMR_MAC(x) (((x)&0x00000003)<<3)
|
||||
#define MCF_MDHA_MDMR_INIT (0x00000020)
|
||||
#define MCF_MDHA_MDMR_IPAD (0x00000040)
|
||||
#define MCF_MDHA_MDMR_OPAD (0x00000080)
|
||||
#define MCF_MDHA_MDMR_SWAP (0x00000100)
|
||||
#define MCF_MDHA_MDMR_MACFULL (0x00000200)
|
||||
#define MCF_MDHA_MDMR_SSL (0x00000400)
|
||||
|
||||
/* Bit definitions and macros for MCF_MDHA_MDCR */
|
||||
#define MCF_MDHA_MDCR_IE (0x00000001)
|
||||
|
||||
/* Bit definitions and macros for MCF_MDHA_MDCMR */
|
||||
#define MCF_MDHA_MDCMR_SWR (0x00000001)
|
||||
#define MCF_MDHA_MDCMR_RI (0x00000002)
|
||||
#define MCF_MDHA_MDCMR_CI (0x00000004)
|
||||
#define MCF_MDHA_MDCMR_GO (0x00000008)
|
||||
|
||||
/* Bit definitions and macros for MCF_MDHA_MDSR */
|
||||
#define MCF_MDHA_MDSR_INT (0x00000001)
|
||||
#define MCF_MDHA_MDSR_DONE (0x00000002)
|
||||
#define MCF_MDHA_MDSR_ERR (0x00000004)
|
||||
#define MCF_MDHA_MDSR_RD (0x00000008)
|
||||
#define MCF_MDHA_MDSR_BUSY (0x00000010)
|
||||
#define MCF_MDHA_MDSR_END (0x00000020)
|
||||
#define MCF_MDHA_MDSR_HSH (0x00000040)
|
||||
#define MCF_MDHA_MDSR_GNW (0x00000080)
|
||||
#define MCF_MDHA_MDSR_FS(x) (((x)&0x00000007)<<8)
|
||||
#define MCF_MDHA_MDSR_APD(x) (((x)&0x00000007)<<13)
|
||||
#define MCF_MDHA_MDSR_IFL(x) (((x)&0x000000FF)<<16)
|
||||
|
||||
/* Bit definitions and macros for MCF_MDHA_MDIR */
|
||||
#define MCF_MDHA_MDIR_IFO (0x00000001)
|
||||
#define MCF_MDHA_MDIR_NON (0x00000004)
|
||||
#define MCF_MDHA_MDIR_IME (0x00000010)
|
||||
#define MCF_MDHA_MDIR_IDS (0x00000020)
|
||||
#define MCF_MDHA_MDIR_RMDP (0x00000080)
|
||||
#define MCF_MDHA_MDIR_ERE (0x00000100)
|
||||
#define MCF_MDHA_MDIR_GTDS (0x00000200)
|
||||
|
||||
/* Bit definitions and macros for MCF_MDHA_MDIMR */
|
||||
#define MCF_MDHA_MDIMR_IFO (0x00000001)
|
||||
#define MCF_MDHA_MDIMR_NON (0x00000004)
|
||||
#define MCF_MDHA_MDIMR_IME (0x00000010)
|
||||
#define MCF_MDHA_MDIMR_IDS (0x00000020)
|
||||
#define MCF_MDHA_MDIMR_RMDP (0x00000080)
|
||||
#define MCF_MDHA_MDIMR_ERE (0x00000100)
|
||||
#define MCF_MDHA_MDIMR_GTDS (0x00000200)
|
||||
|
||||
/* Bit definitions and macros for MCF_MDHA_MDDSR */
|
||||
#define MCF_MDHA_MDDSR_DATASIZE(x) (((x)&0x1FFFFFFF)<<0)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_MDHA_H__ */
|
||||
@ -0,0 +1,89 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_pit.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_PIT_H__
|
||||
#define __MCF523X_PIT_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Programmable Interrupt Timer Modules (PIT)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_PIT_PCSR0 (*(vuint16*)(void*)(&__IPSBAR[0x150000]))
|
||||
#define MCF_PIT_PMR0 (*(vuint16*)(void*)(&__IPSBAR[0x150002]))
|
||||
#define MCF_PIT_PCNTR0 (*(vuint16*)(void*)(&__IPSBAR[0x150004]))
|
||||
#define MCF_PIT_PCSR1 (*(vuint16*)(void*)(&__IPSBAR[0x160000]))
|
||||
#define MCF_PIT_PMR1 (*(vuint16*)(void*)(&__IPSBAR[0x160002]))
|
||||
#define MCF_PIT_PCNTR1 (*(vuint16*)(void*)(&__IPSBAR[0x160004]))
|
||||
#define MCF_PIT_PCSR2 (*(vuint16*)(void*)(&__IPSBAR[0x170000]))
|
||||
#define MCF_PIT_PMR2 (*(vuint16*)(void*)(&__IPSBAR[0x170002]))
|
||||
#define MCF_PIT_PCNTR2 (*(vuint16*)(void*)(&__IPSBAR[0x170004]))
|
||||
#define MCF_PIT_PCSR3 (*(vuint16*)(void*)(&__IPSBAR[0x180000]))
|
||||
#define MCF_PIT_PMR3 (*(vuint16*)(void*)(&__IPSBAR[0x180002]))
|
||||
#define MCF_PIT_PCNTR3 (*(vuint16*)(void*)(&__IPSBAR[0x180004]))
|
||||
#define MCF_PIT_PCSR(x) (*(vuint16*)(void*)(&__IPSBAR[0x150000+((x)*0x10000)]))
|
||||
#define MCF_PIT_PMR(x) (*(vuint16*)(void*)(&__IPSBAR[0x150002+((x)*0x10000)]))
|
||||
#define MCF_PIT_PCNTR(x) (*(vuint16*)(void*)(&__IPSBAR[0x150004+((x)*0x10000)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_PIT_PCSR */
|
||||
#define MCF_PIT_PCSR_EN (0x0001)
|
||||
#define MCF_PIT_PCSR_RLD (0x0002)
|
||||
#define MCF_PIT_PCSR_PIF (0x0004)
|
||||
#define MCF_PIT_PCSR_PIE (0x0008)
|
||||
#define MCF_PIT_PCSR_OVW (0x0010)
|
||||
#define MCF_PIT_PCSR_HALTED (0x0020)
|
||||
#define MCF_PIT_PCSR_DOZE (0x0040)
|
||||
#define MCF_PIT_PCSR_PRE(x) (((x)&0x000F)<<8)
|
||||
|
||||
/* Bit definitions and macros for MCF_PIT_PMR */
|
||||
#define MCF_PIT_PMR_PM0 (0x0001)
|
||||
#define MCF_PIT_PMR_PM1 (0x0002)
|
||||
#define MCF_PIT_PMR_PM2 (0x0004)
|
||||
#define MCF_PIT_PMR_PM3 (0x0008)
|
||||
#define MCF_PIT_PMR_PM4 (0x0010)
|
||||
#define MCF_PIT_PMR_PM5 (0x0020)
|
||||
#define MCF_PIT_PMR_PM6 (0x0040)
|
||||
#define MCF_PIT_PMR_PM7 (0x0080)
|
||||
#define MCF_PIT_PMR_PM8 (0x0100)
|
||||
#define MCF_PIT_PMR_PM9 (0x0200)
|
||||
#define MCF_PIT_PMR_PM10 (0x0400)
|
||||
#define MCF_PIT_PMR_PM11 (0x0800)
|
||||
#define MCF_PIT_PMR_PM12 (0x1000)
|
||||
#define MCF_PIT_PMR_PM13 (0x2000)
|
||||
#define MCF_PIT_PMR_PM14 (0x4000)
|
||||
#define MCF_PIT_PMR_PM15 (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PIT_PCNTR */
|
||||
#define MCF_PIT_PCNTR_PC0 (0x0001)
|
||||
#define MCF_PIT_PCNTR_PC1 (0x0002)
|
||||
#define MCF_PIT_PCNTR_PC2 (0x0004)
|
||||
#define MCF_PIT_PCNTR_PC3 (0x0008)
|
||||
#define MCF_PIT_PCNTR_PC4 (0x0010)
|
||||
#define MCF_PIT_PCNTR_PC5 (0x0020)
|
||||
#define MCF_PIT_PCNTR_PC6 (0x0040)
|
||||
#define MCF_PIT_PCNTR_PC7 (0x0080)
|
||||
#define MCF_PIT_PCNTR_PC8 (0x0100)
|
||||
#define MCF_PIT_PCNTR_PC9 (0x0200)
|
||||
#define MCF_PIT_PCNTR_PC10 (0x0400)
|
||||
#define MCF_PIT_PCNTR_PC11 (0x0800)
|
||||
#define MCF_PIT_PCNTR_PC12 (0x1000)
|
||||
#define MCF_PIT_PCNTR_PC13 (0x2000)
|
||||
#define MCF_PIT_PCNTR_PC14 (0x4000)
|
||||
#define MCF_PIT_PCNTR_PC15 (0x8000)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_PIT_H__ */
|
||||
@ -0,0 +1,69 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_qspi.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_QSPI_H__
|
||||
#define __MCF523X_QSPI_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Queued Serial Peripheral Interface (QSPI)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_QSPI_QMR (*(vuint16*)(void*)(&__IPSBAR[0x000340]))
|
||||
#define MCF_QSPI_QDLYR (*(vuint16*)(void*)(&__IPSBAR[0x000344]))
|
||||
#define MCF_QSPI_QWR (*(vuint16*)(void*)(&__IPSBAR[0x000348]))
|
||||
#define MCF_QSPI_QIR (*(vuint16*)(void*)(&__IPSBAR[0x00034C]))
|
||||
#define MCF_QSPI_QAR (*(vuint16*)(void*)(&__IPSBAR[0x000350]))
|
||||
#define MCF_QSPI_QDR (*(vuint16*)(void*)(&__IPSBAR[0x000354]))
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QMR */
|
||||
#define MCF_QSPI_QMR_BAUD(x) (((x)&0x00FF)<<0)
|
||||
#define MCF_QSPI_QMR_CPHA (0x0100)
|
||||
#define MCF_QSPI_QMR_CPOL (0x0200)
|
||||
#define MCF_QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
|
||||
#define MCF_QSPI_QMR_DOHIE (0x4000)
|
||||
#define MCF_QSPI_QMR_MSTR (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QDLYR */
|
||||
#define MCF_QSPI_QDLYR_DTL(x) (((x)&0x00FF)<<0)
|
||||
#define MCF_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
|
||||
#define MCF_QSPI_QDLYR_SPE (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QWR */
|
||||
#define MCF_QSPI_QWR_NEWQP(x) (((x)&0x000F)<<0)
|
||||
#define MCF_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
|
||||
#define MCF_QSPI_QWR_CSIV (0x1000)
|
||||
#define MCF_QSPI_QWR_WRTO (0x2000)
|
||||
#define MCF_QSPI_QWR_WREN (0x4000)
|
||||
#define MCF_QSPI_QWR_HALT (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QIR */
|
||||
#define MCF_QSPI_QIR_SPIF (0x0001)
|
||||
#define MCF_QSPI_QIR_ABRT (0x0004)
|
||||
#define MCF_QSPI_QIR_WCEF (0x0008)
|
||||
#define MCF_QSPI_QIR_SPIFE (0x0100)
|
||||
#define MCF_QSPI_QIR_ABRTE (0x0400)
|
||||
#define MCF_QSPI_QIR_WCEFE (0x0800)
|
||||
#define MCF_QSPI_QIR_ABRTL (0x1000)
|
||||
#define MCF_QSPI_QIR_ABRTB (0x4000)
|
||||
#define MCF_QSPI_QIR_WCEFB (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QAR */
|
||||
#define MCF_QSPI_QAR_ADDR(x) (((x)&0x003F)<<0)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_QSPI_H__ */
|
||||
@ -0,0 +1,42 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_rcm.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_RCM_H__
|
||||
#define __MCF523X_RCM_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Reset Configuration Module (RCM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_RCM_RCR (*(vuint8 *)(void*)(&__IPSBAR[0x110000]))
|
||||
#define MCF_RCM_RSR (*(vuint8 *)(void*)(&__IPSBAR[0x110001]))
|
||||
|
||||
/* Bit definitions and macros for MCF_RCM_RCR */
|
||||
#define MCF_RCM_RCR_FRCRSTOUT (0x40)
|
||||
#define MCF_RCM_RCR_SOFTRST (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_RCM_RSR */
|
||||
#define MCF_RCM_RSR_LOL (0x01)
|
||||
#define MCF_RCM_RSR_LOC (0x02)
|
||||
#define MCF_RCM_RSR_EXT (0x04)
|
||||
#define MCF_RCM_RSR_POR (0x08)
|
||||
#define MCF_RCM_RSR_WDR (0x10)
|
||||
#define MCF_RCM_RSR_SOFT (0x20)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_RCM_H__ */
|
||||
@ -0,0 +1,46 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_rng.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_RNG_H__
|
||||
#define __MCF523X_RNG_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Random Number Generator (RNG)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_RNG_RNGCR (*(vuint32*)(void*)(&__IPSBAR[0x1A0000]))
|
||||
#define MCF_RNG_RNGSR (*(vuint32*)(void*)(&__IPSBAR[0x1A0004]))
|
||||
#define MCF_RNG_RNGER (*(vuint32*)(void*)(&__IPSBAR[0x1A0008]))
|
||||
#define MCF_RNG_RNGOUT (*(vuint32*)(void*)(&__IPSBAR[0x1A000C]))
|
||||
|
||||
/* Bit definitions and macros for MCF_RNG_RNGCR */
|
||||
#define MCF_RNG_RNGCR_GO (0x00000001)
|
||||
#define MCF_RNG_RNGCR_HA (0x00000002)
|
||||
#define MCF_RNG_RNGCR_IM (0x00000004)
|
||||
#define MCF_RNG_RNGCR_CI (0x00000008)
|
||||
|
||||
/* Bit definitions and macros for MCF_RNG_RNGSR */
|
||||
#define MCF_RNG_RNGSR_SV (0x00000001)
|
||||
#define MCF_RNG_RNGSR_LRS (0x00000002)
|
||||
#define MCF_RNG_RNGSR_FUF (0x00000004)
|
||||
#define MCF_RNG_RNGSR_EI (0x00000008)
|
||||
#define MCF_RNG_RNGSR_OFL(x) (((x)&0x000000FF)<<8)
|
||||
#define MCF_RNG_RNGSR_OFS(x) (((x)&0x000000FF)<<16)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_RNG_H__ */
|
||||
@ -0,0 +1,150 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_scm.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_SCM_H__
|
||||
#define __MCF523X_SCM_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* System Control Module (SCM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_SCM_IPSBAR (*(vuint32*)(void*)(&__IPSBAR[0x000000]))
|
||||
#define MCF_SCM_RAMBAR (*(vuint32*)(void*)(&__IPSBAR[0x000008]))
|
||||
#define MCF_SCM_CRSR (*(vuint8 *)(void*)(&__IPSBAR[0x000010]))
|
||||
#define MCF_SCM_CWCR (*(vuint8 *)(void*)(&__IPSBAR[0x000011]))
|
||||
#define MCF_SCM_LPICR (*(vuint8 *)(void*)(&__IPSBAR[0x000012]))
|
||||
#define MCF_SCM_CWSR (*(vuint8 *)(void*)(&__IPSBAR[0x000013]))
|
||||
#define MCF_SCM_DMAREQC (*(vuint32*)(void*)(&__IPSBAR[0x000014]))
|
||||
#define MCF_SCM_MPARK (*(vuint32*)(void*)(&__IPSBAR[0x00001C]))
|
||||
#define MCF_SCM_MPR (*(vuint8 *)(void*)(&__IPSBAR[0x000020]))
|
||||
#define MCF_SCM_PACR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000024]))
|
||||
#define MCF_SCM_PACR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000025]))
|
||||
#define MCF_SCM_PACR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000026]))
|
||||
#define MCF_SCM_PACR3 (*(vuint8 *)(void*)(&__IPSBAR[0x000027]))
|
||||
#define MCF_SCM_PACR4 (*(vuint8 *)(void*)(&__IPSBAR[0x000028]))
|
||||
#define MCF_SCM_PACR5 (*(vuint8 *)(void*)(&__IPSBAR[0x00002A]))
|
||||
#define MCF_SCM_PACR6 (*(vuint8 *)(void*)(&__IPSBAR[0x00002B]))
|
||||
#define MCF_SCM_PACR7 (*(vuint8 *)(void*)(&__IPSBAR[0x00002C]))
|
||||
#define MCF_SCM_PACR8 (*(vuint8 *)(void*)(&__IPSBAR[0x00002E]))
|
||||
#define MCF_SCM_GPACR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000030]))
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_IPSBAR */
|
||||
#define MCF_SCM_IPSBAR_V (0x00000001)
|
||||
#define MCF_SCM_IPSBAR_BA(x) (((x)&0x00000003)<<30)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_RAMBAR */
|
||||
#define MCF_SCM_RAMBAR_BDE (0x00000200)
|
||||
#define MCF_SCM_RAMBAR_BA(x) (((x)&0x0000FFFF)<<16)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_CRSR */
|
||||
#define MCF_SCM_CRSR_CWDR (0x20)
|
||||
#define MCF_SCM_CRSR_EXT (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_CWCR */
|
||||
#define MCF_SCM_CWCR_CWTIC (0x01)
|
||||
#define MCF_SCM_CWCR_CWTAVAL (0x02)
|
||||
#define MCF_SCM_CWCR_CWTA (0x04)
|
||||
#define MCF_SCM_CWCR_CWT(x) (((x)&0x07)<<3)
|
||||
#define MCF_SCM_CWCR_CWRI (0x40)
|
||||
#define MCF_SCM_CWCR_CWE (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_LPICR */
|
||||
#define MCF_SCM_LPICR_XLPM_IPL(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_LPICR_ENBSTOP (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_DMAREQC */
|
||||
#define MCF_SCM_DMAREQC_DMAC0(x) (((x)&0x0000000F)<<0)
|
||||
#define MCF_SCM_DMAREQC_DMAC1(x) (((x)&0x0000000F)<<4)
|
||||
#define MCF_SCM_DMAREQC_DMAC2(x) (((x)&0x0000000F)<<8)
|
||||
#define MCF_SCM_DMAREQC_DMAC3(x) (((x)&0x0000000F)<<12)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_MPARK */
|
||||
#define MCF_SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0000000F)<<8)
|
||||
#define MCF_SCM_MPARK_PRKLAST (0x00001000)
|
||||
#define MCF_SCM_MPARK_TIMEOUT (0x00002000)
|
||||
#define MCF_SCM_MPARK_FIXED (0x00004000)
|
||||
#define MCF_SCM_MPARK_M1_PRTY(x) (((x)&0x00000003)<<16)
|
||||
#define MCF_SCM_MPARK_M0_PRTY(x) (((x)&0x00000003)<<18)
|
||||
#define MCF_SCM_MPARK_M2_PRTY(x) (((x)&0x00000003)<<20)
|
||||
#define MCF_SCM_MPARK_M3_PRTY(x) (((x)&0x00000003)<<22)
|
||||
#define MCF_SCM_MPARK_BCR24BIT (0x01000000)
|
||||
#define MCF_SCM_MPARK_M2_P_EN (0x02000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_MPR */
|
||||
#define MCF_SCM_MPR_MPR(x) (((x)&0x0F)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR0 */
|
||||
#define MCF_SCM_PACR0_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR0_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR0_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR0_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR1 */
|
||||
#define MCF_SCM_PACR1_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR1_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR1_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR1_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR2 */
|
||||
#define MCF_SCM_PACR2_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR2_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR2_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR2_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR3 */
|
||||
#define MCF_SCM_PACR3_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR3_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR3_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR3_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR4 */
|
||||
#define MCF_SCM_PACR4_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR4_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR4_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR4_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR5 */
|
||||
#define MCF_SCM_PACR5_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR5_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR5_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR5_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR6 */
|
||||
#define MCF_SCM_PACR6_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR6_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR6_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR6_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR7 */
|
||||
#define MCF_SCM_PACR7_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR7_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR7_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR7_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR8 */
|
||||
#define MCF_SCM_PACR8_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR8_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR8_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR8_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_GPACR0 */
|
||||
#define MCF_SCM_GPACR0_ACCESS_CTRL(x) (((x)&0x0F)<<0)
|
||||
#define MCF_SCM_GPACR0_LOCK (0x80)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_SCM_H__ */
|
||||
@ -0,0 +1,94 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_sdramc.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_SDRAMC_H__
|
||||
#define __MCF523X_SDRAMC_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* SDRAM Controller (SDRAMC)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_SDRAMC_DCR (*(vuint16*)(void*)(&__IPSBAR[0x000040]))
|
||||
#define MCF_SDRAMC_DACR0 (*(vuint32*)(void*)(&__IPSBAR[0x000048]))
|
||||
#define MCF_SDRAMC_DMR0 (*(vuint32*)(void*)(&__IPSBAR[0x00004C]))
|
||||
#define MCF_SDRAMC_DACR1 (*(vuint32*)(void*)(&__IPSBAR[0x000050]))
|
||||
#define MCF_SDRAMC_DMR1 (*(vuint32*)(void*)(&__IPSBAR[0x000054]))
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_DCR */
|
||||
#define MCF_SDRAMC_DCR_RC(x) (((x)&0x01FF)<<0)
|
||||
#define MCF_SDRAMC_DCR_RTIM(x) (((x)&0x0003)<<9)
|
||||
#define MCF_SDRAMC_DCR_IS (0x0800)
|
||||
#define MCF_SDRAMC_DCR_COC (0x1000)
|
||||
#define MCF_SDRAMC_DCR_NAM (0x2000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_DACR0 */
|
||||
#define MCF_SDRAMC_DACR0_IP (0x00000008)
|
||||
#define MCF_SDRAMC_DACR0_PS(x) (((x)&0x00000003)<<4)
|
||||
#define MCF_SDRAMC_DACR0_MRS (0x00000040)
|
||||
#define MCF_SDRAMC_DACR0_CBM(x) (((x)&0x00000007)<<8)
|
||||
#define MCF_SDRAMC_DACR0_CASL(x) (((x)&0x00000003)<<12)
|
||||
#define MCF_SDRAMC_DACR0_RE (0x00008000)
|
||||
#define MCF_SDRAMC_DACR0_BA(x) (((x)&0x00003FFF)<<18)
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_DMR0 */
|
||||
#define MCF_SDRAMC_DMR0_V (0x00000001)
|
||||
#define MCF_SDRAMC_DMR0_WP (0x00000100)
|
||||
#define MCF_SDRAMC_DMR0_BAM(x) (((x)&0x00003FFF)<<18)
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_DACR1 */
|
||||
#define MCF_SDRAMC_DACR1_IP (0x00000008)
|
||||
#define MCF_SDRAMC_DACR1_PS(x) (((x)&0x00000003)<<4)
|
||||
#define MCF_SDRAMC_DACR1_MRS (0x00000040)
|
||||
#define MCF_SDRAMC_DACR1_CBM(x) (((x)&0x00000007)<<8)
|
||||
#define MCF_SDRAMC_DACR1_CASL(x) (((x)&0x00000003)<<12)
|
||||
#define MCF_SDRAMC_DACR1_RE (0x00008000)
|
||||
#define MCF_SDRAMC_DACR1_BA(x) (((x)&0x00003FFF)<<18)
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_DMR1 */
|
||||
#define MCF_SDRAMC_DMR1_V (0x00000001)
|
||||
#define MCF_SDRAMC_DMR1_WP (0x00000100)
|
||||
#define MCF_SDRAMC_DMR1_BAM(x) (((x)&0x00003FFF)<<18)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#define MCF_SDRAMC_DMR_BAM_4G (0xFFFC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_2G (0x7FFC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_1G (0x3FFC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_1024M (0x3FFC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_512M (0x1FFC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_256M (0x0FFC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_128M (0x07FC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_64M (0x03FC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_32M (0x01FC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_16M (0x00FC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_8M (0x007C0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_4M (0x003C0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_2M (0x001C0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_1M (0x000C0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_1024K (0x000C0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_512K (0x00040000)
|
||||
#define MCF_SDRAMC_DMR_BAM_256K (0x00000000)
|
||||
#define MCF_SDRAMC_DMR_WP (0x00000100)
|
||||
#define MCF_SDRAMC_DMR_CI (0x00000040)
|
||||
#define MCF_SDRAMC_DMR_AM (0x00000020)
|
||||
#define MCF_SDRAMC_DMR_SC (0x00000010)
|
||||
#define MCF_SDRAMC_DMR_SD (0x00000008)
|
||||
#define MCF_SDRAMC_DMR_UC (0x00000004)
|
||||
#define MCF_SDRAMC_DMR_UD (0x00000002)
|
||||
#define MCF_SDRAMC_DMR_V (0x00000001)
|
||||
|
||||
#endif /* __MCF523X_SDRAMC_H__ */
|
||||
@ -0,0 +1,120 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_skha.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_SKHA_H__
|
||||
#define __MCF523X_SKHA_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Symmetric Key Hardware Accelerator (SKHA)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_SKHA_SKMR (*(vuint32*)(void*)(&__IPSBAR[0x1B0000]))
|
||||
#define MCF_SKHA_SKCR (*(vuint32*)(void*)(&__IPSBAR[0x1B0004]))
|
||||
#define MCF_SKHA_SKCMR (*(vuint32*)(void*)(&__IPSBAR[0x1B0008]))
|
||||
#define MCF_SKHA_SKSR (*(vuint32*)(void*)(&__IPSBAR[0x1B000C]))
|
||||
#define MCF_SKHA_SKIR (*(vuint32*)(void*)(&__IPSBAR[0x1B0010]))
|
||||
#define MCF_SKHA_SKIMR (*(vuint32*)(void*)(&__IPSBAR[0x1B0014]))
|
||||
#define MCF_SKHA_SKKSR (*(vuint32*)(void*)(&__IPSBAR[0x1B0018]))
|
||||
#define MCF_SKHA_SKDSR (*(vuint32*)(void*)(&__IPSBAR[0x1B001C]))
|
||||
#define MCF_SKHA_SKIN (*(vuint32*)(void*)(&__IPSBAR[0x1B0020]))
|
||||
#define MCF_SKHA_SKOUT (*(vuint32*)(void*)(&__IPSBAR[0x1B0024]))
|
||||
#define MCF_SKHA_SKKDR0 (*(vuint32*)(void*)(&__IPSBAR[0x1B0030]))
|
||||
#define MCF_SKHA_SKKDR1 (*(vuint32*)(void*)(&__IPSBAR[0x1B0034]))
|
||||
#define MCF_SKHA_SKKDR2 (*(vuint32*)(void*)(&__IPSBAR[0x1B0038]))
|
||||
#define MCF_SKHA_SKKDR3 (*(vuint32*)(void*)(&__IPSBAR[0x1B003C]))
|
||||
#define MCF_SKHA_SKKDR4 (*(vuint32*)(void*)(&__IPSBAR[0x1B0040]))
|
||||
#define MCF_SKHA_SKKDR5 (*(vuint32*)(void*)(&__IPSBAR[0x1B0044]))
|
||||
#define MCF_SKHA_SKKDRn(x) (*(vuint32*)(void*)(&__IPSBAR[0x1B0030+((x)*0x004)]))
|
||||
#define MCF_SKHA_SKCR0 (*(vuint32*)(void*)(&__IPSBAR[0x1B0070]))
|
||||
#define MCF_SKHA_SKCR1 (*(vuint32*)(void*)(&__IPSBAR[0x1B0074]))
|
||||
#define MCF_SKHA_SKCR2 (*(vuint32*)(void*)(&__IPSBAR[0x1B0078]))
|
||||
#define MCF_SKHA_SKCR3 (*(vuint32*)(void*)(&__IPSBAR[0x1B007C]))
|
||||
#define MCF_SKHA_SKCR4 (*(vuint32*)(void*)(&__IPSBAR[0x1B0080]))
|
||||
#define MCF_SKHA_SKCR5 (*(vuint32*)(void*)(&__IPSBAR[0x1B0084]))
|
||||
#define MCF_SKHA_SKCR6 (*(vuint32*)(void*)(&__IPSBAR[0x1B0088]))
|
||||
#define MCF_SKHA_SKCR7 (*(vuint32*)(void*)(&__IPSBAR[0x1B008C]))
|
||||
#define MCF_SKHA_SKCR8 (*(vuint32*)(void*)(&__IPSBAR[0x1B0090]))
|
||||
#define MCF_SKHA_SKCR9 (*(vuint32*)(void*)(&__IPSBAR[0x1B0094]))
|
||||
#define MCF_SKHA_SKCR10 (*(vuint32*)(void*)(&__IPSBAR[0x1B0098]))
|
||||
#define MCF_SKHA_SKCR11 (*(vuint32*)(void*)(&__IPSBAR[0x1B009C]))
|
||||
#define MCF_SKHA_SKCRn(x) (*(vuint32*)(void*)(&__IPSBAR[0x1B0070+((x)*0x004)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_SKHA_SKMR */
|
||||
#define MCF_SKHA_SKMR_ALG(x) (((x)&0x00000003)<<0)
|
||||
#define MCF_SKHA_SKMR_DIR (0x00000004)
|
||||
#define MCF_SKHA_SKMR_CM(x) (((x)&0x00000003)<<3)
|
||||
#define MCF_SKHA_SKMR_DKP (0x00000100)
|
||||
#define MCF_SKHA_SKMR_CTRM(x) (((x)&0x0000000F)<<9)
|
||||
#define MCF_SKHA_SKMR_CM_ECB (0x00000000)
|
||||
#define MCF_SKHA_SKMR_CM_CBC (0x00000008)
|
||||
#define MCF_SKHA_SKMR_CM_CTR (0x00000018)
|
||||
#define MCF_SKHA_SKMR_DIR_DEC (0x00000000)
|
||||
#define MCF_SKHA_SKMR_DIR_ENC (0x00000004)
|
||||
#define MCF_SKHA_SKMR_ALG_AES (0x00000000)
|
||||
#define MCF_SKHA_SKMR_ALG_DES (0x00000001)
|
||||
#define MCF_SKHA_SKMR_ALG_TDES (0x00000002)
|
||||
|
||||
/* Bit definitions and macros for MCF_SKHA_SKCR */
|
||||
#define MCF_SKHA_SKCR_IE (0x00000001)
|
||||
|
||||
/* Bit definitions and macros for MCF_SKHA_SKCMR */
|
||||
#define MCF_SKHA_SKCMR_SWR (0x00000001)
|
||||
#define MCF_SKHA_SKCMR_RI (0x00000002)
|
||||
#define MCF_SKHA_SKCMR_CI (0x00000004)
|
||||
#define MCF_SKHA_SKCMR_GO (0x00000008)
|
||||
|
||||
/* Bit definitions and macros for MCF_SKHA_SKSR */
|
||||
#define MCF_SKHA_SKSR_INT (0x00000001)
|
||||
#define MCF_SKHA_SKSR_DONE (0x00000002)
|
||||
#define MCF_SKHA_SKSR_ERR (0x00000004)
|
||||
#define MCF_SKHA_SKSR_RD (0x00000008)
|
||||
#define MCF_SKHA_SKSR_BUSY (0x00000010)
|
||||
#define MCF_SKHA_SKSR_IFL(x) (((x)&0x000000FF)<<16)
|
||||
#define MCF_SKHA_SKSR_OFL(x) (((x)&0x000000FF)<<24)
|
||||
|
||||
/* Bit definitions and macros for MCF_SKHA_SKIR */
|
||||
#define MCF_SKHA_SKIR_IFO (0x00000001)
|
||||
#define MCF_SKHA_SKIR_OFU (0x00000002)
|
||||
#define MCF_SKHA_SKIR_NEIF (0x00000004)
|
||||
#define MCF_SKHA_SKIR_NEOF (0x00000008)
|
||||
#define MCF_SKHA_SKIR_IME (0x00000010)
|
||||
#define MCF_SKHA_SKIR_DSE (0x00000020)
|
||||
#define MCF_SKHA_SKIR_KSE (0x00000040)
|
||||
#define MCF_SKHA_SKIR_RMDP (0x00000080)
|
||||
#define MCF_SKHA_SKIR_ERE (0x00000100)
|
||||
#define MCF_SKHA_SKIR_KPE (0x00000200)
|
||||
#define MCF_SKHA_SKIR_KRE (0x00000400)
|
||||
|
||||
/* Bit definitions and macros for MCF_SKHA_SKIMR */
|
||||
#define MCF_SKHA_SKIMR_IFO (0x00000001)
|
||||
#define MCF_SKHA_SKIMR_OFU (0x00000002)
|
||||
#define MCF_SKHA_SKIMR_NEIF (0x00000004)
|
||||
#define MCF_SKHA_SKIMR_NEOF (0x00000008)
|
||||
#define MCF_SKHA_SKIMR_IME (0x00000010)
|
||||
#define MCF_SKHA_SKIMR_DSE (0x00000020)
|
||||
#define MCF_SKHA_SKIMR_KSE (0x00000040)
|
||||
#define MCF_SKHA_SKIMR_RMDP (0x00000080)
|
||||
#define MCF_SKHA_SKIMR_ERE (0x00000100)
|
||||
#define MCF_SKHA_SKIMR_KPE (0x00000200)
|
||||
#define MCF_SKHA_SKIMR_KRE (0x00000400)
|
||||
|
||||
/* Bit definitions and macros for MCF_SKHA_SKKSR */
|
||||
#define MCF_SKHA_SKKSR_KEYSIZE(x) (((x)&0x0000003F)<<0)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_SKHA_H__ */
|
||||
@ -0,0 +1,42 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_sram.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_SRAM_H__
|
||||
#define __MCF523X_SRAM_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* 64KByte System SRAM (SRAM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_SRAM_RAMBAR (*(vuint32*)(void*)(&__IPSBAR[0x20000000]))
|
||||
|
||||
/* Bit definitions and macros for MCF_SRAM_RAMBAR */
|
||||
#define MCF_SRAM_RAMBAR_V (0x00000001)
|
||||
#define MCF_SRAM_RAMBAR_UD (0x00000002)
|
||||
#define MCF_SRAM_RAMBAR_UC (0x00000004)
|
||||
#define MCF_SRAM_RAMBAR_SD (0x00000008)
|
||||
#define MCF_SRAM_RAMBAR_SC (0x00000010)
|
||||
#define MCF_SRAM_RAMBAR_CI (0x00000020)
|
||||
#define MCF_SRAM_RAMBAR_WP (0x00000100)
|
||||
#define MCF_SRAM_RAMBAR_SPV (0x00000200)
|
||||
#define MCF_SRAM_RAMBAR_PRI2 (0x00000400)
|
||||
#define MCF_SRAM_RAMBAR_PRI1 (0x00000800)
|
||||
#define MCF_SRAM_RAMBAR_BA(x) (((x)&0x0000FFFF)<<16)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_SRAM_H__ */
|
||||
@ -0,0 +1,83 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_timer.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_TIMER_H__
|
||||
#define __MCF523X_TIMER_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* DMA Timers (TIMER)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_TIMER_DTMR0 (*(vuint16*)(void*)(&__IPSBAR[0x000400]))
|
||||
#define MCF_TIMER_DTXMR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000402]))
|
||||
#define MCF_TIMER_DTER0 (*(vuint8 *)(void*)(&__IPSBAR[0x000403]))
|
||||
#define MCF_TIMER_DTRR0 (*(vuint32*)(void*)(&__IPSBAR[0x000404]))
|
||||
#define MCF_TIMER_DTCR0 (*(vuint32*)(void*)(&__IPSBAR[0x000408]))
|
||||
#define MCF_TIMER_DTCN0 (*(vuint32*)(void*)(&__IPSBAR[0x00040C]))
|
||||
#define MCF_TIMER_DTMR1 (*(vuint16*)(void*)(&__IPSBAR[0x000440]))
|
||||
#define MCF_TIMER_DTXMR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000442]))
|
||||
#define MCF_TIMER_DTER1 (*(vuint8 *)(void*)(&__IPSBAR[0x000443]))
|
||||
#define MCF_TIMER_DTRR1 (*(vuint32*)(void*)(&__IPSBAR[0x000444]))
|
||||
#define MCF_TIMER_DTCR1 (*(vuint32*)(void*)(&__IPSBAR[0x000448]))
|
||||
#define MCF_TIMER_DTCN1 (*(vuint32*)(void*)(&__IPSBAR[0x00044C]))
|
||||
#define MCF_TIMER_DTMR2 (*(vuint16*)(void*)(&__IPSBAR[0x000480]))
|
||||
#define MCF_TIMER_DTXMR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000482]))
|
||||
#define MCF_TIMER_DTER2 (*(vuint8 *)(void*)(&__IPSBAR[0x000483]))
|
||||
#define MCF_TIMER_DTRR2 (*(vuint32*)(void*)(&__IPSBAR[0x000484]))
|
||||
#define MCF_TIMER_DTCR2 (*(vuint32*)(void*)(&__IPSBAR[0x000488]))
|
||||
#define MCF_TIMER_DTCN2 (*(vuint32*)(void*)(&__IPSBAR[0x00048C]))
|
||||
#define MCF_TIMER_DTMR3 (*(vuint16*)(void*)(&__IPSBAR[0x0004C0]))
|
||||
#define MCF_TIMER_DTXMR3 (*(vuint8 *)(void*)(&__IPSBAR[0x0004C2]))
|
||||
#define MCF_TIMER_DTER3 (*(vuint8 *)(void*)(&__IPSBAR[0x0004C3]))
|
||||
#define MCF_TIMER_DTRR3 (*(vuint32*)(void*)(&__IPSBAR[0x0004C4]))
|
||||
#define MCF_TIMER_DTCR3 (*(vuint32*)(void*)(&__IPSBAR[0x0004C8]))
|
||||
#define MCF_TIMER_DTCN3 (*(vuint32*)(void*)(&__IPSBAR[0x0004CC]))
|
||||
#define MCF_TIMER_DTMR(x) (*(vuint16*)(void*)(&__IPSBAR[0x000400+((x)*0x040)]))
|
||||
#define MCF_TIMER_DTXMR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000402+((x)*0x040)]))
|
||||
#define MCF_TIMER_DTER(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000403+((x)*0x040)]))
|
||||
#define MCF_TIMER_DTRR(x) (*(vuint32*)(void*)(&__IPSBAR[0x000404+((x)*0x040)]))
|
||||
#define MCF_TIMER_DTCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x000408+((x)*0x040)]))
|
||||
#define MCF_TIMER_DTCN(x) (*(vuint32*)(void*)(&__IPSBAR[0x00040C+((x)*0x040)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_TIMER_DTMR */
|
||||
#define MCF_TIMER_DTMR_RST (0x0001)
|
||||
#define MCF_TIMER_DTMR_CLK(x) (((x)&0x0003)<<1)
|
||||
#define MCF_TIMER_DTMR_FRR (0x0008)
|
||||
#define MCF_TIMER_DTMR_ORRI (0x0010)
|
||||
#define MCF_TIMER_DTMR_OM (0x0020)
|
||||
#define MCF_TIMER_DTMR_CE(x) (((x)&0x0003)<<6)
|
||||
#define MCF_TIMER_DTMR_PS(x) (((x)&0x00FF)<<8)
|
||||
#define MCF_TIMER_DTMR_CE_ANY (0x00C0)
|
||||
#define MCF_TIMER_DTMR_CE_FALL (0x0080)
|
||||
#define MCF_TIMER_DTMR_CE_RISE (0x0040)
|
||||
#define MCF_TIMER_DTMR_CE_NONE (0x0000)
|
||||
#define MCF_TIMER_DTMR_CLK_DTIN (0x0006)
|
||||
#define MCF_TIMER_DTMR_CLK_DIV16 (0x0004)
|
||||
#define MCF_TIMER_DTMR_CLK_DIV1 (0x0002)
|
||||
#define MCF_TIMER_DTMR_CLK_STOP (0x0000)
|
||||
|
||||
/* Bit definitions and macros for MCF_TIMER_DTXMR */
|
||||
#define MCF_TIMER_DTXMR_MODE16 (0x01)
|
||||
#define MCF_TIMER_DTXMR_DMAEN (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_TIMER_DTER */
|
||||
#define MCF_TIMER_DTER_CAP (0x01)
|
||||
#define MCF_TIMER_DTER_REF (0x02)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_TIMER_H__ */
|
||||
@ -0,0 +1,186 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_uart.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_UART_H__
|
||||
#define __MCF523X_UART_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Universal Asynchronous Receiver Transmitter (UART)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_UART_UMR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000200]))
|
||||
#define MCF_UART_USR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000204]))
|
||||
#define MCF_UART_UCSR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000204]))
|
||||
#define MCF_UART_UCR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000208]))
|
||||
#define MCF_UART_URB0 (*(vuint8 *)(void*)(&__IPSBAR[0x00020C]))
|
||||
#define MCF_UART_UTB0 (*(vuint8 *)(void*)(&__IPSBAR[0x00020C]))
|
||||
#define MCF_UART_UIPCR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000210]))
|
||||
#define MCF_UART_UACR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000210]))
|
||||
#define MCF_UART_UISR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000214]))
|
||||
#define MCF_UART_UIMR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000214]))
|
||||
#define MCF_UART_UBG10 (*(vuint8 *)(void*)(&__IPSBAR[0x000218]))
|
||||
#define MCF_UART_UBG20 (*(vuint8 *)(void*)(&__IPSBAR[0x00021C]))
|
||||
#define MCF_UART_UIP0 (*(vuint8 *)(void*)(&__IPSBAR[0x000234]))
|
||||
#define MCF_UART_UOP10 (*(vuint8 *)(void*)(&__IPSBAR[0x000238]))
|
||||
#define MCF_UART_UOP00 (*(vuint8 *)(void*)(&__IPSBAR[0x00023C]))
|
||||
#define MCF_UART_UMR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000240]))
|
||||
#define MCF_UART_USR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000244]))
|
||||
#define MCF_UART_UCSR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000244]))
|
||||
#define MCF_UART_UCR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000248]))
|
||||
#define MCF_UART_URB1 (*(vuint8 *)(void*)(&__IPSBAR[0x00024C]))
|
||||
#define MCF_UART_UTB1 (*(vuint8 *)(void*)(&__IPSBAR[0x00024C]))
|
||||
#define MCF_UART_UIPCR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000250]))
|
||||
#define MCF_UART_UACR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000250]))
|
||||
#define MCF_UART_UISR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000254]))
|
||||
#define MCF_UART_UIMR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000254]))
|
||||
#define MCF_UART_UBG11 (*(vuint8 *)(void*)(&__IPSBAR[0x000258]))
|
||||
#define MCF_UART_UBG21 (*(vuint8 *)(void*)(&__IPSBAR[0x00025C]))
|
||||
#define MCF_UART_UIP1 (*(vuint8 *)(void*)(&__IPSBAR[0x000274]))
|
||||
#define MCF_UART_UOP11 (*(vuint8 *)(void*)(&__IPSBAR[0x000278]))
|
||||
#define MCF_UART_UOP01 (*(vuint8 *)(void*)(&__IPSBAR[0x00027C]))
|
||||
#define MCF_UART_UMR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000280]))
|
||||
#define MCF_UART_USR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000284]))
|
||||
#define MCF_UART_UCSR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000284]))
|
||||
#define MCF_UART_UCR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000288]))
|
||||
#define MCF_UART_URB2 (*(vuint8 *)(void*)(&__IPSBAR[0x00028C]))
|
||||
#define MCF_UART_UTB2 (*(vuint8 *)(void*)(&__IPSBAR[0x00028C]))
|
||||
#define MCF_UART_UIPCR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000290]))
|
||||
#define MCF_UART_UACR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000290]))
|
||||
#define MCF_UART_UISR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000294]))
|
||||
#define MCF_UART_UIMR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000294]))
|
||||
#define MCF_UART_UBG12 (*(vuint8 *)(void*)(&__IPSBAR[0x000298]))
|
||||
#define MCF_UART_UBG22 (*(vuint8 *)(void*)(&__IPSBAR[0x00029C]))
|
||||
#define MCF_UART_UIP2 (*(vuint8 *)(void*)(&__IPSBAR[0x0002B4]))
|
||||
#define MCF_UART_UOP12 (*(vuint8 *)(void*)(&__IPSBAR[0x0002B8]))
|
||||
#define MCF_UART_UOP02 (*(vuint8 *)(void*)(&__IPSBAR[0x0002BC]))
|
||||
#define MCF_UART_UMR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000200+((x)*0x040)]))
|
||||
#define MCF_UART_USR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000204+((x)*0x040)]))
|
||||
#define MCF_UART_UCSR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000204+((x)*0x040)]))
|
||||
#define MCF_UART_UCR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000208+((x)*0x040)]))
|
||||
#define MCF_UART_URB(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00020C+((x)*0x040)]))
|
||||
#define MCF_UART_UTB(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00020C+((x)*0x040)]))
|
||||
#define MCF_UART_UIPCR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000210+((x)*0x040)]))
|
||||
#define MCF_UART_UACR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000210+((x)*0x040)]))
|
||||
#define MCF_UART_UISR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000214+((x)*0x040)]))
|
||||
#define MCF_UART_UIMR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000214+((x)*0x040)]))
|
||||
#define MCF_UART_UBG1(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000218+((x)*0x040)]))
|
||||
#define MCF_UART_UBG2(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00021C+((x)*0x040)]))
|
||||
#define MCF_UART_UIP(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000234+((x)*0x040)]))
|
||||
#define MCF_UART_UOP1(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000238+((x)*0x040)]))
|
||||
#define MCF_UART_UOP0(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00023C+((x)*0x040)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UMR */
|
||||
#define MCF_UART_UMR_BC(x) (((x)&0x03)<<0)
|
||||
#define MCF_UART_UMR_PT (0x04)
|
||||
#define MCF_UART_UMR_PM(x) (((x)&0x03)<<3)
|
||||
#define MCF_UART_UMR_ERR (0x20)
|
||||
#define MCF_UART_UMR_RXIRQ (0x40)
|
||||
#define MCF_UART_UMR_RXRTS (0x80)
|
||||
#define MCF_UART_UMR_SB(x) (((x)&0x0F)<<0)
|
||||
#define MCF_UART_UMR_TXCTS (0x10)
|
||||
#define MCF_UART_UMR_TXRTS (0x20)
|
||||
#define MCF_UART_UMR_CM(x) (((x)&0x03)<<6)
|
||||
#define MCF_UART_UMR_PM_MULTI_ADDR (0x1C)
|
||||
#define MCF_UART_UMR_PM_MULTI_DATA (0x18)
|
||||
#define MCF_UART_UMR_PM_NONE (0x10)
|
||||
#define MCF_UART_UMR_PM_FORCE_HI (0x0C)
|
||||
#define MCF_UART_UMR_PM_FORCE_LO (0x08)
|
||||
#define MCF_UART_UMR_PM_ODD (0x04)
|
||||
#define MCF_UART_UMR_PM_EVEN (0x00)
|
||||
#define MCF_UART_UMR_BC_5 (0x00)
|
||||
#define MCF_UART_UMR_BC_6 (0x01)
|
||||
#define MCF_UART_UMR_BC_7 (0x02)
|
||||
#define MCF_UART_UMR_BC_8 (0x03)
|
||||
#define MCF_UART_UMR_CM_NORMAL (0x00)
|
||||
#define MCF_UART_UMR_CM_ECHO (0x40)
|
||||
#define MCF_UART_UMR_CM_LOCAL_LOOP (0x80)
|
||||
#define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0)
|
||||
#define MCF_UART_UMR_SB_STOP_BITS_1 (0x07)
|
||||
#define MCF_UART_UMR_SB_STOP_BITS_15 (0x08)
|
||||
#define MCF_UART_UMR_SB_STOP_BITS_2 (0x0F)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_USR */
|
||||
#define MCF_UART_USR_RXRDY (0x01)
|
||||
#define MCF_UART_USR_FFULL (0x02)
|
||||
#define MCF_UART_USR_TXRDY (0x04)
|
||||
#define MCF_UART_USR_TXEMP (0x08)
|
||||
#define MCF_UART_USR_OE (0x10)
|
||||
#define MCF_UART_USR_PE (0x20)
|
||||
#define MCF_UART_USR_FE (0x40)
|
||||
#define MCF_UART_USR_RB (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UCSR */
|
||||
#define MCF_UART_UCSR_TCS(x) (((x)&0x0F)<<0)
|
||||
#define MCF_UART_UCSR_RCS(x) (((x)&0x0F)<<4)
|
||||
#define MCF_UART_UCSR_RCS_SYS_CLK (0xD0)
|
||||
#define MCF_UART_UCSR_RCS_CTM16 (0xE0)
|
||||
#define MCF_UART_UCSR_RCS_CTM (0xF0)
|
||||
#define MCF_UART_UCSR_TCS_SYS_CLK (0x0D)
|
||||
#define MCF_UART_UCSR_TCS_CTM16 (0x0E)
|
||||
#define MCF_UART_UCSR_TCS_CTM (0x0F)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UCR */
|
||||
#define MCF_UART_UCR_RXC(x) (((x)&0x03)<<0)
|
||||
#define MCF_UART_UCR_TXC(x) (((x)&0x03)<<2)
|
||||
#define MCF_UART_UCR_MISC(x) (((x)&0x07)<<4)
|
||||
#define MCF_UART_UCR_NONE (0x00)
|
||||
#define MCF_UART_UCR_STOP_BREAK (0x70)
|
||||
#define MCF_UART_UCR_START_BREAK (0x60)
|
||||
#define MCF_UART_UCR_BKCHGINT (0x50)
|
||||
#define MCF_UART_UCR_RESET_ERROR (0x40)
|
||||
#define MCF_UART_UCR_RESET_TX (0x30)
|
||||
#define MCF_UART_UCR_RESET_RX (0x20)
|
||||
#define MCF_UART_UCR_RESET_MR (0x10)
|
||||
#define MCF_UART_UCR_TX_DISABLED (0x08)
|
||||
#define MCF_UART_UCR_TX_ENABLED (0x04)
|
||||
#define MCF_UART_UCR_RX_DISABLED (0x02)
|
||||
#define MCF_UART_UCR_RX_ENABLED (0x01)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UIPCR */
|
||||
#define MCF_UART_UIPCR_CTS (0x01)
|
||||
#define MCF_UART_UIPCR_COS (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UACR */
|
||||
#define MCF_UART_UACR_IEC (0x01)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UISR */
|
||||
#define MCF_UART_UISR_TXRDY (0x01)
|
||||
#define MCF_UART_UISR_RXRDY_FU (0x02)
|
||||
#define MCF_UART_UISR_DB (0x04)
|
||||
#define MCF_UART_UISR_RXFTO (0x08)
|
||||
#define MCF_UART_UISR_TXFIFO (0x10)
|
||||
#define MCF_UART_UISR_RXFIFO (0x20)
|
||||
#define MCF_UART_UISR_COS (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UIMR */
|
||||
#define MCF_UART_UIMR_TXRDY (0x01)
|
||||
#define MCF_UART_UIMR_RXRDY_FU (0x02)
|
||||
#define MCF_UART_UIMR_DB (0x04)
|
||||
#define MCF_UART_UIMR_COS (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UIP */
|
||||
#define MCF_UART_UIP_CTS (0x01)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UOP1 */
|
||||
#define MCF_UART_UOP1_RTS (0x01)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UOP0 */
|
||||
#define MCF_UART_UOP0_RTS (0x01)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_UART_H__ */
|
||||
@ -0,0 +1,92 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_wtm.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_WTM_H__
|
||||
#define __MCF523X_WTM_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Watchdog Timer Modules (WTM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_WTM_WCR (*(vuint16*)(void*)(&__IPSBAR[0x140000]))
|
||||
#define MCF_WTM_WMR (*(vuint16*)(void*)(&__IPSBAR[0x140002]))
|
||||
#define MCF_WTM_WCNTR (*(vuint16*)(void*)(&__IPSBAR[0x140004]))
|
||||
#define MCF_WTM_WSR (*(vuint16*)(void*)(&__IPSBAR[0x140006]))
|
||||
|
||||
/* Bit definitions and macros for MCF_WTM_WCR */
|
||||
#define MCF_WTM_WCR_EN (0x0001)
|
||||
#define MCF_WTM_WCR_HALTED (0x0002)
|
||||
#define MCF_WTM_WCR_DOZE (0x0004)
|
||||
#define MCF_WTM_WCR_WAIT (0x0008)
|
||||
|
||||
/* Bit definitions and macros for MCF_WTM_WMR */
|
||||
#define MCF_WTM_WMR_WM0 (0x0001)
|
||||
#define MCF_WTM_WMR_WM1 (0x0002)
|
||||
#define MCF_WTM_WMR_WM2 (0x0004)
|
||||
#define MCF_WTM_WMR_WM3 (0x0008)
|
||||
#define MCF_WTM_WMR_WM4 (0x0010)
|
||||
#define MCF_WTM_WMR_WM5 (0x0020)
|
||||
#define MCF_WTM_WMR_WM6 (0x0040)
|
||||
#define MCF_WTM_WMR_WM7 (0x0080)
|
||||
#define MCF_WTM_WMR_WM8 (0x0100)
|
||||
#define MCF_WTM_WMR_WM9 (0x0200)
|
||||
#define MCF_WTM_WMR_WM10 (0x0400)
|
||||
#define MCF_WTM_WMR_WM11 (0x0800)
|
||||
#define MCF_WTM_WMR_WM12 (0x1000)
|
||||
#define MCF_WTM_WMR_WM13 (0x2000)
|
||||
#define MCF_WTM_WMR_WM14 (0x4000)
|
||||
#define MCF_WTM_WMR_WM15 (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_WTM_WCNTR */
|
||||
#define MCF_WTM_WCNTR_WC0 (0x0001)
|
||||
#define MCF_WTM_WCNTR_WC1 (0x0002)
|
||||
#define MCF_WTM_WCNTR_WC2 (0x0004)
|
||||
#define MCF_WTM_WCNTR_WC3 (0x0008)
|
||||
#define MCF_WTM_WCNTR_WC4 (0x0010)
|
||||
#define MCF_WTM_WCNTR_WC5 (0x0020)
|
||||
#define MCF_WTM_WCNTR_WC6 (0x0040)
|
||||
#define MCF_WTM_WCNTR_WC7 (0x0080)
|
||||
#define MCF_WTM_WCNTR_WC8 (0x0100)
|
||||
#define MCF_WTM_WCNTR_WC9 (0x0200)
|
||||
#define MCF_WTM_WCNTR_WC10 (0x0400)
|
||||
#define MCF_WTM_WCNTR_WC11 (0x0800)
|
||||
#define MCF_WTM_WCNTR_WC12 (0x1000)
|
||||
#define MCF_WTM_WCNTR_WC13 (0x2000)
|
||||
#define MCF_WTM_WCNTR_WC14 (0x4000)
|
||||
#define MCF_WTM_WCNTR_WC15 (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_WTM_WSR */
|
||||
#define MCF_WTM_WSR_WS0 (0x0001)
|
||||
#define MCF_WTM_WSR_WS1 (0x0002)
|
||||
#define MCF_WTM_WSR_WS2 (0x0004)
|
||||
#define MCF_WTM_WSR_WS3 (0x0008)
|
||||
#define MCF_WTM_WSR_WS4 (0x0010)
|
||||
#define MCF_WTM_WSR_WS5 (0x0020)
|
||||
#define MCF_WTM_WSR_WS6 (0x0040)
|
||||
#define MCF_WTM_WSR_WS7 (0x0080)
|
||||
#define MCF_WTM_WSR_WS8 (0x0100)
|
||||
#define MCF_WTM_WSR_WS9 (0x0200)
|
||||
#define MCF_WTM_WSR_WS10 (0x0400)
|
||||
#define MCF_WTM_WSR_WS11 (0x0800)
|
||||
#define MCF_WTM_WSR_WS12 (0x1000)
|
||||
#define MCF_WTM_WSR_WS13 (0x2000)
|
||||
#define MCF_WTM_WSR_WS14 (0x4000)
|
||||
#define MCF_WTM_WSR_WS15 (0x8000)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_WTM_H__ */
|
||||
@ -0,0 +1,196 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf5xxx.h
|
||||
* Purpose: Definitions common to all ColdFire processors
|
||||
*
|
||||
* Notes:
|
||||
*/
|
||||
|
||||
#ifndef _CPU_MCF5XXX_H
|
||||
#define _CPU_MCF5XXX_H
|
||||
|
||||
/***********************************************************************/
|
||||
/*
|
||||
* Misc. Defines
|
||||
*/
|
||||
|
||||
#ifdef FALSE
|
||||
#undef FALSE
|
||||
#endif
|
||||
#define FALSE (0)
|
||||
|
||||
#ifdef TRUE
|
||||
#undef TRUE
|
||||
#endif
|
||||
#define TRUE (1)
|
||||
|
||||
#ifdef NULL
|
||||
#undef NULL
|
||||
#endif
|
||||
#define NULL (0)
|
||||
|
||||
/***********************************************************************/
|
||||
/*
|
||||
* The basic data types
|
||||
*/
|
||||
|
||||
typedef unsigned char uint8; /* 8 bits */
|
||||
typedef unsigned short int uint16; /* 16 bits */
|
||||
typedef unsigned long int uint32; /* 32 bits */
|
||||
|
||||
typedef signed char int8; /* 8 bits */
|
||||
typedef signed short int int16; /* 16 bits */
|
||||
typedef signed long int int32; /* 32 bits */
|
||||
|
||||
typedef volatile uint8 vuint8; /* 8 bits */
|
||||
typedef volatile uint16 vuint16; /* 16 bits */
|
||||
typedef volatile uint32 vuint32; /* 32 bits */
|
||||
|
||||
/***********************************************************************/
|
||||
/*
|
||||
* Common M68K & ColdFire definitions
|
||||
*/
|
||||
|
||||
#define ADDRESS uint32
|
||||
#define INSTRUCTION uint16
|
||||
#define ILLEGAL 0x4AFC
|
||||
#define CPU_WORD_SIZE 16
|
||||
|
||||
#define MCF5XXX_SR_T (0x8000)
|
||||
#define MCF5XXX_SR_S (0x2000)
|
||||
#define MCF5XXX_SR_M (0x1000)
|
||||
#define MCF5XXX_SR_IPL (0x0700)
|
||||
#define MCF5XXX_SR_IPL_0 (0x0000)
|
||||
#define MCF5XXX_SR_IPL_1 (0x0100)
|
||||
#define MCF5XXX_SR_IPL_2 (0x0200)
|
||||
#define MCF5XXX_SR_IPL_3 (0x0300)
|
||||
#define MCF5XXX_SR_IPL_4 (0x0400)
|
||||
#define MCF5XXX_SR_IPL_5 (0x0500)
|
||||
#define MCF5XXX_SR_IPL_6 (0x0600)
|
||||
#define MCF5XXX_SR_IPL_7 (0x0700)
|
||||
#define MCF5XXX_SR_X (0x0010)
|
||||
#define MCF5XXX_SR_N (0x0008)
|
||||
#define MCF5XXX_SR_Z (0x0004)
|
||||
#define MCF5XXX_SR_V (0x0002)
|
||||
#define MCF5XXX_SR_C (0x0001)
|
||||
|
||||
#define MCF5XXX_CACR_CENB (0x80000000)
|
||||
#define MCF5XXX_CACR_CPDI (0x10000000)
|
||||
#define MCF5XXX_CACR_CPD (0x10000000)
|
||||
#define MCF5XXX_CACR_CFRZ (0x08000000)
|
||||
#define MCF5XXX_CACR_CINV (0x01000000)
|
||||
#define MCF5XXX_CACR_DIDI (0x00800000)
|
||||
#define MCF5XXX_CACR_DISD (0x00400000)
|
||||
#define MCF5XXX_CACR_INVI (0x00200000)
|
||||
#define MCF5XXX_CACR_INVD (0x00100000)
|
||||
#define MCF5XXX_CACR_CEIB (0x00000400)
|
||||
#define MCF5XXX_CACR_DCM_WR (0x00000000)
|
||||
#define MCF5XXX_CACR_DCM_CB (0x00000100)
|
||||
#define MCF5XXX_CACR_DCM_IP (0x00000200)
|
||||
#define MCF5XXX_CACR_DCM (0x00000200)
|
||||
#define MCF5XXX_CACR_DCM_II (0x00000300)
|
||||
#define MCF5XXX_CACR_DBWE (0x00000100)
|
||||
#define MCF5XXX_CACR_DWP (0x00000020)
|
||||
#define MCF5XXX_CACR_EUST (0x00000010)
|
||||
#define MCF5XXX_CACR_CLNF_00 (0x00000000)
|
||||
#define MCF5XXX_CACR_CLNF_01 (0x00000002)
|
||||
#define MCF5XXX_CACR_CLNF_10 (0x00000004)
|
||||
#define MCF5XXX_CACR_CLNF_11 (0x00000006)
|
||||
|
||||
#define MCF5XXX_ACR_AB(a) ((a)&0xFF000000)
|
||||
#define MCF5XXX_ACR_AM(a) (((a)&0xFF000000) >> 8)
|
||||
#define MCF5XXX_ACR_EN (0x00008000)
|
||||
#define MCF5XXX_ACR_SM_USER (0x00000000)
|
||||
#define MCF5XXX_ACR_SM_SUPER (0x00002000)
|
||||
#define MCF5XXX_ACR_SM_IGNORE (0x00006000)
|
||||
#define MCF5XXX_ACR_ENIB (0x00000080)
|
||||
#define MCF5XXX_ACR_CM (0x00000040)
|
||||
#define MCF5XXX_ACR_DCM_WR (0x00000000)
|
||||
#define MCF5XXX_ACR_DCM_CB (0x00000020)
|
||||
#define MCF5XXX_ACR_DCM_IP (0x00000040)
|
||||
#define MCF5XXX_ACR_DCM_II (0x00000060)
|
||||
#define MCF5XXX_ACR_CM (0x00000040)
|
||||
#define MCF5XXX_ACR_BWE (0x00000020)
|
||||
#define MCF5XXX_ACR_WP (0x00000004)
|
||||
|
||||
#define MCF5XXX_RAMBAR_BA(a) ((a)&0xFFFFC000)
|
||||
#define MCF5XXX_RAMBAR_PRI_00 (0x00000000)
|
||||
#define MCF5XXX_RAMBAR_PRI_01 (0x00004000)
|
||||
#define MCF5XXX_RAMBAR_PRI_10 (0x00008000)
|
||||
#define MCF5XXX_RAMBAR_PRI_11 (0x0000C000)
|
||||
#define MCF5XXX_RAMBAR_WP (0x00000100)
|
||||
#define MCF5XXX_RAMBAR_CI (0x00000020)
|
||||
#define MCF5XXX_RAMBAR_SC (0x00000010)
|
||||
#define MCF5XXX_RAMBAR_SD (0x00000008)
|
||||
#define MCF5XXX_RAMBAR_UC (0x00000004)
|
||||
#define MCF5XXX_RAMBAR_UD (0x00000002)
|
||||
#define MCF5XXX_RAMBAR_V (0x00000001)
|
||||
|
||||
/***********************************************************************/
|
||||
/*
|
||||
* The ColdFire family of processors has a simplified exception stack
|
||||
* frame that looks like the following:
|
||||
*
|
||||
* 3322222222221111 111111
|
||||
* 1098765432109876 5432109876543210
|
||||
* 8 +----------------+----------------+
|
||||
* | Program Counter |
|
||||
* 4 +----------------+----------------+
|
||||
* |FS/Fmt/Vector/FS| SR |
|
||||
* SP --> 0 +----------------+----------------+
|
||||
*
|
||||
* The stack self-aligns to a 4-byte boundary at an exception, with
|
||||
* the FS/Fmt/Vector/FS field indicating the size of the adjustment
|
||||
* (SP += 0,1,2,3 bytes).
|
||||
*/
|
||||
|
||||
#define MCF5XXX_RD_SF_FORMAT(PTR) \
|
||||
((*((uint16 *)(PTR)) >> 12) & 0x00FF)
|
||||
|
||||
#define MCF5XXX_RD_SF_VECTOR(PTR) \
|
||||
((*((uint16 *)(PTR)) >> 2) & 0x00FF)
|
||||
|
||||
#define MCF5XXX_RD_SF_FS(PTR) \
|
||||
( ((*((uint16 *)(PTR)) & 0x0C00) >> 8) | (*((uint16 *)(PTR)) & 0x0003) )
|
||||
|
||||
#define MCF5XXX_SF_SR(PTR) *((uint16 *)(PTR)+1)
|
||||
#define MCF5XXX_SF_PC(PTR) *((uint32 *)(PTR)+1)
|
||||
|
||||
/********************************************************************/
|
||||
/*
|
||||
* Functions provided by mcf5xxx.s
|
||||
*/
|
||||
|
||||
int asm_set_ipl (uint32);
|
||||
void mcf5xxx_wr_cacr (uint32);
|
||||
void mcf5xxx_wr_acr0 (uint32);
|
||||
void mcf5xxx_wr_acr1 (uint32);
|
||||
void mcf5xxx_wr_acr2 (uint32);
|
||||
void mcf5xxx_wr_acr3 (uint32);
|
||||
void mcf5xxx_wr_other_a7 (uint32);
|
||||
void mcf5xxx_wr_other_sp (uint32);
|
||||
void mcf5xxx_wr_vbr (uint32);
|
||||
void mcf5xxx_wr_macsr (uint32);
|
||||
void mcf5xxx_wr_mask (uint32);
|
||||
void mcf5xxx_wr_acc0 (uint32);
|
||||
void mcf5xxx_wr_accext01 (uint32);
|
||||
void mcf5xxx_wr_accext23 (uint32);
|
||||
void mcf5xxx_wr_acc1 (uint32);
|
||||
void mcf5xxx_wr_acc2 (uint32);
|
||||
void mcf5xxx_wr_acc3 (uint32);
|
||||
void mcf5xxx_wr_sr (uint32);
|
||||
void mcf5xxx_wr_rambar0 (uint32);
|
||||
void mcf5xxx_wr_rambar1 (uint32);
|
||||
void mcf5xxx_wr_mbar (uint32);
|
||||
void mcf5xxx_wr_mbar0 (uint32);
|
||||
void mcf5xxx_wr_mbar1 (uint32);
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* _CPU_MCF5XXX_H */
|
||||
|
||||
@ -0,0 +1,119 @@
|
||||
STARTUP(system/crt0.o)
|
||||
INPUT(system/vector.o)
|
||||
OUTPUT_ARCH(m68k)
|
||||
SEARCH_DIR(.)
|
||||
GROUP(-lc -lgcc)
|
||||
|
||||
__DYNAMIC = 0;
|
||||
|
||||
MEMORY
|
||||
{
|
||||
sdram (rwx) : ORIGIN = 0x00000000, LENGTH = 0x01000000
|
||||
sram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000
|
||||
ipsbar (rwx) : ORIGIN = 0x40000000, LENGTH = 0x40000000
|
||||
flash (rwx) : ORIGIN = 0x80000000, LENGTH = 0x00080000
|
||||
}
|
||||
|
||||
PROVIDE (__stack = 0x2000FFFC);
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.sdram : {} > sdram
|
||||
.ipsbar : {} > ipsbar
|
||||
.sram (NOLOAD) : { *(.vector_ram); *(.nbuf) } > sram
|
||||
.flash : {} > flash
|
||||
|
||||
.text :
|
||||
{
|
||||
__text_start = . ;
|
||||
*(.vector_rom)
|
||||
. = ALIGN (0x100);
|
||||
*(.text)
|
||||
. = ALIGN (16);
|
||||
|
||||
*(.eh_frame)
|
||||
. = ALIGN (16);
|
||||
|
||||
*(.gnu.linkonce.t.*)
|
||||
|
||||
. = ALIGN(0x4);
|
||||
__CTOR_LIST__ = .;
|
||||
___CTOR_LIST__ = .;
|
||||
LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
|
||||
*(.ctors)
|
||||
LONG(0)
|
||||
__CTOR_END__ = .;
|
||||
__DTOR_LIST__ = .;
|
||||
___DTOR_LIST__ = .;
|
||||
LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
|
||||
*(.dtors)
|
||||
LONG(0)
|
||||
__DTOR_END__ = .;
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.gcc_except_table)
|
||||
|
||||
. = ALIGN(0x2);
|
||||
__INIT_SECTION__ = . ;
|
||||
LONG (0x4e560000) /* linkw %fp,#0 */
|
||||
*(.init)
|
||||
SHORT (0x4e5e) /* unlk %fp */
|
||||
SHORT (0x4e75) /* rts */
|
||||
|
||||
__FINI_SECTION__ = . ;
|
||||
LONG (0x4e560000) /* linkw %fp,#0 */
|
||||
*(.fini)
|
||||
SHORT (0x4e5e) /* unlk %fp */
|
||||
SHORT (0x4e75) /* rts */
|
||||
|
||||
*(.lit)
|
||||
. = ALIGN(16);
|
||||
_etext = .;
|
||||
etext = .;
|
||||
} > sdram
|
||||
|
||||
.data :
|
||||
{
|
||||
copy_start = .;
|
||||
*(.shdata)
|
||||
*(.data)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN (16);
|
||||
_edata = .;
|
||||
copy_end = .;
|
||||
} > sdram
|
||||
__data_load_start = LOADADDR(.data);
|
||||
__data_load_end = __data_load_start + SIZEOF(.data);
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(0x4);
|
||||
__bss_start = . ;
|
||||
*(.shbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
_end = ALIGN (0x8);
|
||||
__end = _end;
|
||||
} > sdram
|
||||
|
||||
.stab 0 (NOLOAD) :
|
||||
{
|
||||
*(.stab)
|
||||
}
|
||||
|
||||
.stabstr 0 (NOLOAD) :
|
||||
{
|
||||
*(.stabstr)
|
||||
}
|
||||
}
|
||||
|
||||
__IPSBAR = ADDR(.ipsbar);
|
||||
|
||||
__SDRAM = ADDR(.sdram);
|
||||
__SDRAM_SIZE = SIZEOF(.sdram);
|
||||
|
||||
__SRAM = ADDR(.sram);
|
||||
__SRAM_SIZE = SIZEOF(.sram);
|
||||
|
||||
__FLASH = ADDR(.flash);
|
||||
__FLASH_SIZE = SIZEOF(.flash);
|
||||
@ -0,0 +1,119 @@
|
||||
STARTUP(system/crt0.o)
|
||||
INPUT(system/vector.o)
|
||||
OUTPUT_ARCH(m68k)
|
||||
SEARCH_DIR(.)
|
||||
GROUP(-lc -lgcc)
|
||||
|
||||
__DYNAMIC = 0;
|
||||
|
||||
MEMORY
|
||||
{
|
||||
sdram (rwx) : ORIGIN = 0x00000000, LENGTH = 0x01000000
|
||||
sram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000
|
||||
ipsbar (rwx) : ORIGIN = 0x40000000, LENGTH = 0x40000000
|
||||
flash (rwx) : ORIGIN = 0x80000000, LENGTH = 0x00080000
|
||||
}
|
||||
|
||||
PROVIDE (__stack = 0x2000FFFC);
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.sdram : {} > sdram
|
||||
.ipsbar : {} > ipsbar
|
||||
.sram (NOLOAD) : { *(.vector_ram); *(.nbuf) } > sram
|
||||
.flash : {} > flash
|
||||
|
||||
.text :
|
||||
{
|
||||
__text_start = . ;
|
||||
*(.vector_rom)
|
||||
. = ALIGN (0x100);
|
||||
*(.text)
|
||||
. = ALIGN (16);
|
||||
|
||||
*(.eh_frame)
|
||||
. = ALIGN (16);
|
||||
|
||||
*(.gnu.linkonce.t.*)
|
||||
|
||||
. = ALIGN(0x4);
|
||||
__CTOR_LIST__ = .;
|
||||
___CTOR_LIST__ = .;
|
||||
LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
|
||||
*(.ctors)
|
||||
LONG(0)
|
||||
__CTOR_END__ = .;
|
||||
__DTOR_LIST__ = .;
|
||||
___DTOR_LIST__ = .;
|
||||
LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
|
||||
*(.dtors)
|
||||
LONG(0)
|
||||
__DTOR_END__ = .;
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.gcc_except_table)
|
||||
|
||||
. = ALIGN(0x2);
|
||||
__INIT_SECTION__ = . ;
|
||||
LONG (0x4e560000) /* linkw %fp,#0 */
|
||||
*(.init)
|
||||
SHORT (0x4e5e) /* unlk %fp */
|
||||
SHORT (0x4e75) /* rts */
|
||||
|
||||
__FINI_SECTION__ = . ;
|
||||
LONG (0x4e560000) /* linkw %fp,#0 */
|
||||
*(.fini)
|
||||
SHORT (0x4e5e) /* unlk %fp */
|
||||
SHORT (0x4e75) /* rts */
|
||||
|
||||
*(.lit)
|
||||
. = ALIGN(16);
|
||||
_etext = .;
|
||||
etext = .;
|
||||
} > sdram
|
||||
|
||||
.data :
|
||||
{
|
||||
copy_start = .;
|
||||
*(.shdata)
|
||||
*(.data)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN (16);
|
||||
_edata = .;
|
||||
copy_end = .;
|
||||
} > sdram
|
||||
__data_load_start = LOADADDR(.data);
|
||||
__data_load_end = __data_load_start + SIZEOF(.data);
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(0x4);
|
||||
__bss_start = . ;
|
||||
*(.shbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
_end = ALIGN (0x8);
|
||||
__end = _end;
|
||||
} > sdram
|
||||
|
||||
.stab 0 (NOLOAD) :
|
||||
{
|
||||
*(.stab)
|
||||
}
|
||||
|
||||
.stabstr 0 (NOLOAD) :
|
||||
{
|
||||
*(.stabstr)
|
||||
}
|
||||
}
|
||||
|
||||
__IPSBAR = ADDR(.ipsbar);
|
||||
|
||||
__SDRAM = ADDR(.sdram);
|
||||
__SDRAM_SIZE = SIZEOF(.sdram);
|
||||
|
||||
__SRAM = ADDR(.sram);
|
||||
__SRAM_SIZE = SIZEOF(.sram);
|
||||
|
||||
__FLASH = ADDR(.flash);
|
||||
__FLASH_SIZE = SIZEOF(.flash);
|
||||
@ -0,0 +1,134 @@
|
||||
set $IPSBAR = 0x40000000
|
||||
|
||||
set $DCR = $IPSBAR + 0x000040
|
||||
set $DACR0 = $IPSBAR + 0x000048
|
||||
set $DMR0 = $IPSBAR + 0x00004C
|
||||
|
||||
set $CSAR0 = $IPSBAR + 0x000080
|
||||
set $CSMR0 = $IPSBAR + 0x000084
|
||||
set $CSCR0 = $IPSBAR + 0x00008A
|
||||
|
||||
set $PAR_SDRAM = $IPSBAR + 0x100046
|
||||
set $PAR_AD = $IPSBAR + 0x100040
|
||||
|
||||
set $WCR = $IPSBAR + 0x140000
|
||||
|
||||
define delay
|
||||
set $delay = 0
|
||||
while ($delay < 20000)
|
||||
set $delay += 1
|
||||
end
|
||||
end
|
||||
|
||||
define delay_memsync
|
||||
set $delay = 0
|
||||
while ($delay < 10000)
|
||||
set $delay += 1
|
||||
end
|
||||
end
|
||||
|
||||
define setup-cs
|
||||
# 2MB FLASH on CS0 at 0x80000000
|
||||
set *(unsigned short *)$CSAR0 = 0x00008000
|
||||
set *(unsigned long *)$CSMR0 = 0x001F0101
|
||||
set *(unsigned short *)$CSCR0 = 0x00001980
|
||||
end
|
||||
|
||||
define setup-sdram
|
||||
# Set PAR_SDRAM to allow SDRAM signals to be enable
|
||||
set *(unsigned char *)$PAR_SDRAM = 0x3F
|
||||
# Set PAR_AD to allow 32-bit SDRAM if the external boot device is 16-bit
|
||||
set *(unsigned char *)$PAR_AD = 0xE1
|
||||
|
||||
# SDRAM
|
||||
set *(unsigned short *)$DCR = 0x0446
|
||||
set *(unsigned long *)$DACR0 = 0x00001300
|
||||
set *(unsigned long *)$DMR0 = 0x00FC0001
|
||||
|
||||
# Set IP in DACR and init precharge.
|
||||
set *(unsigned long *)$DACR0 |= 0x00000008
|
||||
set *(0x00000000) = 0xAA55AA55
|
||||
delay
|
||||
|
||||
# Set RE in DACR
|
||||
set *(unsigned long *)$DACR0 |= 0x00008000
|
||||
# Issue IMRS
|
||||
set *(unsigned long *)$DACR0 |= 0x00000040
|
||||
set *(0x00000400) = 0xAA55AA55
|
||||
delay
|
||||
end
|
||||
|
||||
define setup-other
|
||||
# Turn Off WCR
|
||||
set *(unsigned char *)$WCR = 0x00
|
||||
end
|
||||
|
||||
define setup-and-load
|
||||
bdm-reset
|
||||
|
||||
# Set VBR to the vector table.
|
||||
set $vbr = 0x00000000
|
||||
# Set internal SRAM to start at 0x20000000
|
||||
set $rambar = 0x20000001
|
||||
|
||||
setup-other
|
||||
setup-cs
|
||||
setup-sdram
|
||||
end
|
||||
|
||||
define debug-sramtest
|
||||
set $srambase = 0x20000000
|
||||
set $sramsize = 0x00010000
|
||||
set $j = 0
|
||||
printf "Testing SRAM : 0x%08X - 0x%08X\n", $srambase, ($srambase + $sramsize)
|
||||
set $i = $srambase
|
||||
while $i < ($srambase + $sramsize)
|
||||
set *(unsigned long *)($i) = 0xAA55AA55
|
||||
delay_memsync
|
||||
if 0xAA55AA55 != *(unsigned long *)$i
|
||||
printf " 0x%08X = FAIL\n", $i
|
||||
else
|
||||
printf " 0x%08X = OK", $i
|
||||
if $j % 4 == 3
|
||||
printf "\n"
|
||||
end
|
||||
set $j = $j + 1
|
||||
end
|
||||
set $i = $i + 0x400
|
||||
end
|
||||
en
|
||||
|
||||
define debug-ramtest
|
||||
set $sdrambase = 0x00000000
|
||||
set $sdramsize = 0x01000000
|
||||
set $j = 0
|
||||
printf "Testing SDRAM : 0x%08X - 0x%08X\n", $sdrambase, ($sdrambase + $sdramsize)
|
||||
set $i = $sdrambase
|
||||
while $i < ($sdrambase + $sdramsize)
|
||||
set *(unsigned long *)($i) = 0xAA55AA55
|
||||
delay_memsync
|
||||
if 0xAA55AA55 != *(unsigned long *)$i
|
||||
printf " 0x%08X = FAIL\n", $i
|
||||
else
|
||||
printf " 0x%08X = OK", $i
|
||||
if $j % 4 == 3
|
||||
printf "\n"
|
||||
end
|
||||
set $j = $j + 1
|
||||
end
|
||||
set $i = $i + 0x10000
|
||||
end
|
||||
printf "\n"
|
||||
end
|
||||
|
||||
define execute
|
||||
set $pc = *(long *)0x00000004
|
||||
tbreak main
|
||||
tk gdbtk_update
|
||||
end
|
||||
|
||||
define debug-printexception
|
||||
printf "vector: %d", *(unsigned short *)$sp >> 2 &0x1F
|
||||
printf "old pc: 0x%08x", *(unsigned long *)($sp + 4)
|
||||
printf "old sr: 0x%02x", *(unsigned short *)($sp + 2)
|
||||
end
|
||||
@ -0,0 +1,115 @@
|
||||
/*
|
||||
FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter.
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with FreeRTOS; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
|
||||
A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes FreeRTOS, without being obliged to provide
|
||||
the source code for any proprietary components. See the licensing section
|
||||
of http://www.FreeRTOS.org for full details of how and when the exception
|
||||
can be applied.
|
||||
|
||||
***************************************************************************
|
||||
See http://www.FreeRTOS.org for documentation, latest information, license
|
||||
and contact details. Please ensure to read the configuration and relevant
|
||||
port sections of the online documentation.
|
||||
***************************************************************************
|
||||
*/
|
||||
|
||||
.title "crt0.S"
|
||||
|
||||
.extern main
|
||||
.extern __stack
|
||||
.extern __bss_start
|
||||
.extern __text_start
|
||||
.extern init_main
|
||||
|
||||
.equ MCF5XXX_RAMBAR_SPV, 0x00000200
|
||||
.equ MCF5XXX_RAMBAR_V, 0x00000001
|
||||
.global start
|
||||
|
||||
.align 4
|
||||
debug:
|
||||
.word 0x2C80 /* write to CSR */
|
||||
.word 0x0010
|
||||
.word 0x0400
|
||||
.word 0x0000
|
||||
|
||||
start:
|
||||
/* disable all interrupts on startup. */
|
||||
move.w #0x2700, sr
|
||||
|
||||
/* prepare internal SRAM. */
|
||||
move.l #__SRAM, d0
|
||||
ori.l #( MCF5XXX_RAMBAR_SPV | MCF5XXX_RAMBAR_V ), d0
|
||||
movec d0, rambar
|
||||
|
||||
/* prepare stack and frame pointer. */
|
||||
move.l #__stack, sp
|
||||
link a6, #-8
|
||||
|
||||
/* initialize hardware. */
|
||||
jsr init_main
|
||||
|
||||
/* zero out the bss section. */
|
||||
move.l #__bss_start, d1
|
||||
move.l #_end, d0
|
||||
cmp.l d0, d1
|
||||
jbeq 3f
|
||||
move.l d1, a0
|
||||
sub.l d1, d0
|
||||
subq.l #1, d0
|
||||
2:
|
||||
clr.b (a0)+
|
||||
subq.l #1, d0
|
||||
jbpl 2b
|
||||
3:
|
||||
|
||||
/* Relocate the data section. */
|
||||
move.l #__data_load_start, %a0 /* .data in ROM */
|
||||
move.l #copy_start, %a1 /* .data in RAM */
|
||||
|
||||
/* Test if the two sections overlap. This is the case when we are working
|
||||
* with the debugger and the debugger loads the .data section.
|
||||
*/
|
||||
cmpa.l %a0, %a1
|
||||
beq 2f
|
||||
1:
|
||||
/* Have we already copied everything. */
|
||||
cmpa.l #__data_load_end, %a0
|
||||
beq 2f
|
||||
move.b (%a0)+, (%a1)+
|
||||
bra 1b
|
||||
|
||||
2:
|
||||
|
||||
/* C library */
|
||||
move.l #__FINI_SECTION__, -(%sp)
|
||||
jsr atexit
|
||||
jsr __INIT_SECTION__
|
||||
|
||||
/* call main(int argc, char *argv[] */
|
||||
move.l #0, -(sp)
|
||||
move.l #0, -(sp)
|
||||
move.l #0, -(sp)
|
||||
jsr main
|
||||
lea (sp, 12), %sp
|
||||
|
||||
/* stop on exit from main. */
|
||||
1:
|
||||
halt
|
||||
|
||||
@ -0,0 +1,743 @@
|
||||
/*
|
||||
FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter.
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with FreeRTOS; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
|
||||
A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes FreeRTOS, without being obliged to provide
|
||||
the source code for any proprietary components. See the licensing section
|
||||
of http://www.FreeRTOS.org for full details of how and when the exception
|
||||
can be applied.
|
||||
|
||||
***************************************************************************
|
||||
See http://www.FreeRTOS.org for documentation, latest information, license
|
||||
and contact details. Please ensure to read the configuration and relevant
|
||||
port sections of the online documentation.
|
||||
***************************************************************************
|
||||
*/
|
||||
|
||||
#include "mcf5xxx.h"
|
||||
#include "mcf523x.h"
|
||||
|
||||
/* Function prototypes */
|
||||
void init_main( void );
|
||||
static void disable_interrupts( void );
|
||||
static void disable_watchdog_timer( void );
|
||||
static void disable_cache( void );
|
||||
static void init_ipsbar( void );
|
||||
static void init_basics( void );
|
||||
static void init_clock_config( void );
|
||||
static void init_chip_selects( void );
|
||||
static void init_bus_config( void );
|
||||
static void init_cache( void );
|
||||
static void init_eport( void );
|
||||
static void init_flexcan( void );
|
||||
static void init_power_management( void );
|
||||
static void init_dma_timers( void );
|
||||
static void init_interrupt_timers( void );
|
||||
static void init_watchdog_timers( void );
|
||||
static void init_pin_assignments( void );
|
||||
static void init_sdram_controller( void );
|
||||
static void init_interrupt_controller( void );
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* init_main - Main entry point for initialisation code *
|
||||
**********************************************************************/
|
||||
void
|
||||
init_main( void )
|
||||
{
|
||||
|
||||
/* Initialise base address of peripherals, VBR, etc */
|
||||
init_ipsbar( );
|
||||
init_basics( );
|
||||
init_clock_config( );
|
||||
|
||||
/* Disable interrupts, watchdog timer, cache */
|
||||
disable_interrupts( );
|
||||
disable_watchdog_timer( );
|
||||
disable_cache( );
|
||||
|
||||
/* Initialise individual modules */
|
||||
init_chip_selects( );
|
||||
init_bus_config( );
|
||||
init_cache( );
|
||||
init_eport( );
|
||||
init_flexcan( );
|
||||
init_power_management( );
|
||||
init_dma_timers( );
|
||||
init_interrupt_timers( );
|
||||
init_watchdog_timers( );
|
||||
init_pin_assignments( );
|
||||
init_sdram_controller( );
|
||||
|
||||
/* Initialise interrupt controller */
|
||||
init_interrupt_controller( );
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* disable_interrupts - Disable all interrupt sources *
|
||||
**********************************************************************/
|
||||
static void
|
||||
disable_interrupts( void )
|
||||
{
|
||||
vuint8 *p;
|
||||
int i;
|
||||
|
||||
|
||||
/* Set ICR008-ICR063 to 0x0 */
|
||||
p = ( vuint8 * ) & MCF_INTC0_ICR8;
|
||||
for( i = 8; i <= 63; i++ )
|
||||
*p++ = 0x0;
|
||||
|
||||
/* Set ICR108-ICR163 to 0x0 */
|
||||
p = ( vuint8 * ) & MCF_INTC1_ICR8;
|
||||
for( i = 108; i <= 163; i++ )
|
||||
*p++ = 0x0;
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* disable_watchdog_timer - Disable system watchdog timer *
|
||||
**********************************************************************/
|
||||
static void
|
||||
disable_watchdog_timer( void )
|
||||
{
|
||||
|
||||
/* Disable Core Watchdog Timer */
|
||||
MCF_SCM_CWCR = 0;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* disable_cache - Disable and invalidate cache *
|
||||
**********************************************************************/
|
||||
static void
|
||||
disable_cache( void )
|
||||
{
|
||||
asm ( "move.l #0x01000000, %d0" );
|
||||
asm ( "movec %d0, %CACR" );
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* init_basics - Configuration Information & VBR *
|
||||
**********************************************************************/
|
||||
static void
|
||||
init_basics( void )
|
||||
{
|
||||
int i;
|
||||
extern uint32 __RAMVEC[];
|
||||
extern uint32 __ROMVEC[];
|
||||
|
||||
/* Transfer size not driven on SIZ[1:0] pins during external cycles
|
||||
Processor Status (PST) and Debug Data (DDATA) functions disabled
|
||||
Bus monitor disabled
|
||||
Output pads configured for full strength
|
||||
*/
|
||||
MCF_CCM_CCR = ( 0x1 << 15 ) | MCF_CCM_CCR_BME;
|
||||
|
||||
/* Set up RAM vectors */
|
||||
for( i = 0; i < 256; i++ )
|
||||
|
||||
{
|
||||
__RAMVEC[i] = __ROMVEC[i];
|
||||
}
|
||||
asm( "move.l %0,%%d0": :"i"( __RAMVEC ) );
|
||||
asm( "movec %d0,%vbr" );
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* init_clock_config - Clock Module *
|
||||
**********************************************************************/
|
||||
static void
|
||||
init_clock_config( void )
|
||||
{
|
||||
/* Clock module uses normal PLL mode with 25.0000 MHz external reference (Fref)
|
||||
MFD = 0, RFD = 1
|
||||
Bus clock frequency = 25.00 MHz
|
||||
Processor clock frequency = 2 x bus clock = 50.00 MHz
|
||||
Frequency Modulation disabled
|
||||
Loss of clock detection disabled
|
||||
Reset/Interrupt on loss of lock disabled
|
||||
*/
|
||||
MCF_FMPLL_SYNCR = 0x00100000; /* Set RFD=RFD+1 to avoid frequency overshoot */
|
||||
while( ( MCF_FMPLL_SYNSR & 0x08 ) == 0 ) /* Wait for PLL to lock */
|
||||
;
|
||||
MCF_FMPLL_SYNCR = 0x00080000; /* Set desired RFD */
|
||||
while( ( MCF_FMPLL_SYNSR & 0x08 ) == 0 ) /* Wait for PLL to lock */
|
||||
;
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* init_ipsbar - Internal Peripheral System Base Address (IPSBAR) *
|
||||
**********************************************************************/
|
||||
static void
|
||||
init_ipsbar( void )
|
||||
{
|
||||
extern int __SRAM;
|
||||
|
||||
/* Base address of internal peripherals (IPSBAR) = 0x40000000
|
||||
|
||||
Note: Processor powers up with IPS base address = 0x40000000
|
||||
Write to IPS base + 0x00000000 to set new value
|
||||
*/
|
||||
*( vuint32 * ) 0x40000000 = ( vuint32 ) __IPSBAR + 1;
|
||||
|
||||
/* Configure RAMBAR in SCM module and allow dual-ported access. */
|
||||
MCF_SCM_RAMBAR = ( uint32 ) &__SRAM | MCF_SCM_RAMBAR_BDE;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* init_chip_selects - Chip Select Module *
|
||||
**********************************************************************/
|
||||
static void
|
||||
init_chip_selects( void )
|
||||
{
|
||||
extern void __FLASH;
|
||||
uint32 FLASH_ADDR = (uint32)&__FLASH;
|
||||
|
||||
/* Chip Select 0 - External Flash */
|
||||
MCF_CS_CSAR0 = MCF_CS_CSAR_BA( FLASH_ADDR );
|
||||
MCF_CS_CSCR0 = ( 0
|
||||
| MCF_CS_CSCR_IWS( 6 )
|
||||
| MCF_CS_CSCR_AA | MCF_CS_CSCR_PS_16 );
|
||||
MCF_CS_CSMR0 = MCF_CS_CSMR_BAM_2M | MCF_CS_CSMR_V;
|
||||
|
||||
/* Chip Select 1 disabled (CSMR1[V] = 0) */
|
||||
MCF_CS_CSAR1 = 0;
|
||||
MCF_CS_CSMR1 = 0;
|
||||
MCF_CS_CSCR1 = 0;
|
||||
|
||||
/* Chip Select 2 disabled (CSMR2[V] = 0) */
|
||||
MCF_CS_CSAR2 = 0;
|
||||
MCF_CS_CSMR2 = 0;
|
||||
MCF_CS_CSCR2 = 0;
|
||||
|
||||
/* Chip Select 3 disabled (CSMR3[V] = 0) */
|
||||
MCF_CS_CSAR3 = 0;
|
||||
MCF_CS_CSMR3 = 0;
|
||||
MCF_CS_CSCR3 = 0;
|
||||
|
||||
/* Chip Select 4 disabled (CSMR4[V] = 0) */
|
||||
MCF_CS_CSAR4 = 0;
|
||||
MCF_CS_CSMR4 = 0;
|
||||
MCF_CS_CSCR4 = 0;
|
||||
|
||||
/* Chip Select 5 disabled (CSMR5[V] = 0) */
|
||||
MCF_CS_CSAR5 = 0;
|
||||
MCF_CS_CSMR5 = 0;
|
||||
MCF_CS_CSCR5 = 0;
|
||||
|
||||
/* Chip Select 6 disabled (CSMR6[V] = 0) */
|
||||
MCF_CS_CSAR6 = 0;
|
||||
MCF_CS_CSMR6 = 0;
|
||||
MCF_CS_CSCR6 = 0;
|
||||
|
||||
/* Chip Select 7 disabled (CSMR7[V] = 0) */
|
||||
MCF_CS_CSAR7 = 0;
|
||||
MCF_CS_CSMR7 = 0;
|
||||
MCF_CS_CSCR7 = 0;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* init_bus_config - Internal Bus Arbitration *
|
||||
**********************************************************************/
|
||||
static void
|
||||
init_bus_config( void )
|
||||
{
|
||||
|
||||
/* Use round robin arbitration scheme
|
||||
Assigned priorities (highest first):
|
||||
Ethernet
|
||||
DMA Controller
|
||||
ColdFire Core
|
||||
DMA bandwidth control disabled
|
||||
Park on last active bus master
|
||||
*/
|
||||
MCF_SCM_MPARK =
|
||||
MCF_SCM_MPARK_M3_PRTY( 0x3 ) | MCF_SCM_MPARK_M2_PRTY( 0x2 ) |
|
||||
MCF_SCM_MPARK_M1_PRTY( 0x1 );
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* init_cache - Instruction/Data Cache *
|
||||
**********************************************************************/
|
||||
static void
|
||||
init_cache( void )
|
||||
{
|
||||
/* Configured as split cache: 4 KByte instruction cache and 4 Kbyte data cache
|
||||
ACR0: Don't cache accesses to 16 MB memory region at address $20000000
|
||||
ACR1: Don't cache accesses to 1 GB memory region at address $40000000
|
||||
CACR: Cache accesses to the rest of memory
|
||||
*/
|
||||
asm("move.l #0x80000000,%d0");
|
||||
asm("movec %d0,%CACR");
|
||||
asm("move.l #0x2000c040,%d0");
|
||||
asm("movec %d0,%ACR0");
|
||||
asm("move.l #0x403fc040,%d0");
|
||||
asm("movec %d0,%ACR1");
|
||||
|
||||
/* Instruction/Data cache disabled. */
|
||||
//asm( "move.l #0x00000000, %d0" );
|
||||
//asm( "movec %d0,%cacr" );
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* init_eport - Edge Port Module (EPORT) *
|
||||
**********************************************************************/
|
||||
static void
|
||||
init_eport( void )
|
||||
{
|
||||
|
||||
/* Pins 1-7 configured as GPIO inputs */
|
||||
MCF_EPORT_EPPAR = 0;
|
||||
MCF_EPORT_EPDDR = 0;
|
||||
MCF_EPORT_EPIER = 0;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* init_flexcan - FlexCAN Module *
|
||||
**********************************************************************/
|
||||
static void
|
||||
init_flexcan( void )
|
||||
{
|
||||
|
||||
/* FlexCAN controller 0 disabled (CANMCR0[MDIS]=1) */
|
||||
MCF_CAN_IMASK0 = 0;
|
||||
MCF_CAN_RXGMASK0 = MCF_CAN_RXGMASK_MI( 0x1fffffff );
|
||||
MCF_CAN_RX14MASK0 = MCF_CAN_RX14MASK_MI( 0x1fffffff );
|
||||
MCF_CAN_RX15MASK0 = MCF_CAN_RX15MASK_MI( 0x1fffffff );
|
||||
MCF_CAN_CANCTRL0 = 0;
|
||||
MCF_CAN_CANMCR0 =
|
||||
MCF_CAN_CANMCR_MDIS | MCF_CAN_CANMCR_FRZ | MCF_CAN_CANMCR_HALT |
|
||||
MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB( 0xf );
|
||||
|
||||
/* FlexCAN controller 1 disabled (CANMCR1[MDIS]=1) */
|
||||
MCF_CAN_IMASK1 = 0;
|
||||
MCF_CAN_RXGMASK1 = MCF_CAN_RXGMASK_MI( 0x1fffffff );
|
||||
MCF_CAN_RX14MASK1 = MCF_CAN_RX14MASK_MI( 0x1fffffff );
|
||||
MCF_CAN_RX15MASK1 = MCF_CAN_RX15MASK_MI( 0x1fffffff );
|
||||
MCF_CAN_CANCTRL1 = 0;
|
||||
MCF_CAN_CANMCR1 =
|
||||
MCF_CAN_CANMCR_MDIS | MCF_CAN_CANMCR_FRZ | MCF_CAN_CANMCR_HALT |
|
||||
MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB( 0xf );
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* init_power_management - Power Management *
|
||||
**********************************************************************/
|
||||
static void
|
||||
init_power_management( void )
|
||||
{
|
||||
|
||||
/* On executing STOP instruction, processor enters RUN mode
|
||||
Mode is exited when an interrupt of level 1 or higher is received
|
||||
*/
|
||||
MCF_SCM_LPICR = MCF_SCM_LPICR_ENBSTOP;
|
||||
MCF_CCM_LPCR = 0;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* init_sdram_controller - SDRAM Controller *
|
||||
**********************************************************************/
|
||||
static void
|
||||
init_sdram_controller( void )
|
||||
{
|
||||
extern void __SDRAM;
|
||||
uint32 SDRAM_ADDR = (uint32)&__SDRAM;
|
||||
int i;
|
||||
|
||||
|
||||
/*
|
||||
* Check to see if the SDRAM has already been initialized
|
||||
* by a run control tool
|
||||
*/
|
||||
if( !( MCF_SDRAMC_DACR0 & MCF_SDRAMC_DACR0_RE ) )
|
||||
{
|
||||
/* Initialize DRAM Control Register: DCR */
|
||||
MCF_SDRAMC_DCR = ( MCF_SDRAMC_DCR_RTIM( 1 ) |
|
||||
MCF_SDRAMC_DCR_RC( ( 15 * FSYS_2 ) >> 4 ) );
|
||||
|
||||
/* Initialize DACR0 */
|
||||
MCF_SDRAMC_DACR0 = ( MCF_SDRAMC_DACR0_BA( SDRAM_ADDR >> 18UL ) |
|
||||
MCF_SDRAMC_DACR0_CASL( 1 ) |
|
||||
MCF_SDRAMC_DACR0_CBM( 3 ) |
|
||||
MCF_SDRAMC_DACR0_PS( 0 ) );
|
||||
|
||||
/* Initialize DMR0 */
|
||||
MCF_SDRAMC_DMR0 = ( MCF_SDRAMC_DMR_BAM_16M | MCF_SDRAMC_DMR0_V );
|
||||
|
||||
/* Set IP (bit 3) in DACR */
|
||||
MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_IP;
|
||||
|
||||
/* Wait 30ns to allow banks to precharge */
|
||||
for( i = 0; i < 5; i++ )
|
||||
{
|
||||
asm volatile ( " nop" );
|
||||
}
|
||||
/* Write to this block to initiate precharge */
|
||||
*( uint32 * ) ( SDRAM_ADDR ) = 0xA5A59696;
|
||||
|
||||
/* Set RE (bit 15) in DACR */
|
||||
MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_RE;
|
||||
|
||||
/* Wait for at least 8 auto refresh cycles to occur */
|
||||
for( i = 0; i < 2000; i++ )
|
||||
{
|
||||
asm volatile ( "nop" );
|
||||
}
|
||||
/* Finish the configuration by issuing the IMRS. */
|
||||
MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_MRS;
|
||||
|
||||
/* Write to the SDRAM Mode Register */
|
||||
*( uint32 * ) ( SDRAM_ADDR + 0x400 ) = 0xA5A59696;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* init_dma_timers - DMA Timer Modules *
|
||||
**********************************************************************/
|
||||
static void
|
||||
init_dma_timers( void )
|
||||
{
|
||||
|
||||
/* DMA Timer 0 disabled (DTMR0[RST] = 0) */
|
||||
MCF_TIMER_DTMR0 = 0;
|
||||
MCF_TIMER_DTXMR0 = 0;
|
||||
MCF_TIMER_DTRR0 = 0xffffffff;
|
||||
|
||||
/* DMA Timer 1 disabled (DTMR1[RST] = 0) */
|
||||
MCF_TIMER_DTMR1 = 0;
|
||||
MCF_TIMER_DTXMR1 = 0;
|
||||
MCF_TIMER_DTRR1 = 0xffffffff;
|
||||
|
||||
/* DMA Timer 2 disabled (DTMR2[RST] = 0) */
|
||||
MCF_TIMER_DTMR2 = 0;
|
||||
MCF_TIMER_DTXMR2 = 0;
|
||||
MCF_TIMER_DTRR2 = 0xffffffff;
|
||||
|
||||
/* DMA Timer 3 disabled (DTMR3[RST] = 0) */
|
||||
MCF_TIMER_DTMR3 = 0;
|
||||
MCF_TIMER_DTXMR3 = 0;
|
||||
MCF_TIMER_DTRR3 = 0xffffffff;
|
||||
}
|
||||
|
||||
/**********************************************************************
|
||||
* init_interrupt_timers - Programmable Interrupt Timer (PIT) Modules *
|
||||
***********************************************************************/
|
||||
static void
|
||||
init_interrupt_timers( void )
|
||||
{
|
||||
|
||||
/* PIT0 disabled (PCSR0[EN]=0) */
|
||||
MCF_PIT_PCSR0 = 0;
|
||||
|
||||
/* PIT1 disabled (PCSR1[EN]=0) */
|
||||
MCF_PIT_PCSR1 = 0;
|
||||
|
||||
/* PIT2 disabled (PCSR2[EN]=0) */
|
||||
MCF_PIT_PCSR2 = 0;
|
||||
|
||||
/* PIT3 disabled (PCSR3[EN]=0) */
|
||||
MCF_PIT_PCSR3 = 0;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* init_watchdog_timers - Watchdog Timer Modules *
|
||||
**********************************************************************/
|
||||
static void
|
||||
init_watchdog_timers( void )
|
||||
{
|
||||
|
||||
/* Watchdog Timer disabled (WCR[EN]=0)
|
||||
NOTE: WCR and WMR cannot be written again until after the
|
||||
processor is reset.
|
||||
*/
|
||||
MCF_WTM_WCR = MCF_WTM_WCR_WAIT | MCF_WTM_WCR_DOZE | MCF_WTM_WCR_HALTED;
|
||||
MCF_WTM_WMR = 0xffff;
|
||||
|
||||
/* Core Watchdog Timer disabled (CWCR[CWE]=0) */
|
||||
MCF_SCM_CWCR = 0;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* init_interrupt_controller - Interrupt Controller *
|
||||
**********************************************************************/
|
||||
static void
|
||||
init_interrupt_controller( void )
|
||||
{
|
||||
|
||||
/* Configured interrupt sources in order of priority...
|
||||
Level 7: External interrupt /IRQ7, (initially masked)
|
||||
Level 6: External interrupt /IRQ6, (initially masked)
|
||||
Level 5: External interrupt /IRQ5, (initially masked)
|
||||
Level 4: External interrupt /IRQ4, (initially masked)
|
||||
Level 3: External interrupt /IRQ3, (initially masked)
|
||||
Level 2: External interrupt /IRQ2, (initially masked)
|
||||
Level 1: External interrupt /IRQ1, (initially masked)
|
||||
*/
|
||||
MCF_INTC0_ICR1 = 0;
|
||||
MCF_INTC0_ICR2 = 0;
|
||||
MCF_INTC0_ICR3 = 0;
|
||||
MCF_INTC0_ICR4 = 0;
|
||||
MCF_INTC0_ICR5 = 0;
|
||||
MCF_INTC0_ICR6 = 0;
|
||||
MCF_INTC0_ICR7 = 0;
|
||||
MCF_INTC0_ICR8 = 0;
|
||||
MCF_INTC0_ICR9 = 0;
|
||||
MCF_INTC0_ICR10 = 0;
|
||||
MCF_INTC0_ICR11 = 0;
|
||||
MCF_INTC0_ICR12 = 0;
|
||||
MCF_INTC0_ICR13 = 0;
|
||||
MCF_INTC0_ICR14 = 0;
|
||||
MCF_INTC0_ICR15 = 0;
|
||||
MCF_INTC0_ICR17 = 0;
|
||||
MCF_INTC0_ICR18 = 0;
|
||||
MCF_INTC0_ICR19 = 0;
|
||||
MCF_INTC0_ICR20 = 0;
|
||||
MCF_INTC0_ICR21 = 0;
|
||||
MCF_INTC0_ICR22 = 0;
|
||||
MCF_INTC0_ICR23 = 0;
|
||||
MCF_INTC0_ICR24 = 0;
|
||||
MCF_INTC0_ICR25 = 0;
|
||||
MCF_INTC0_ICR26 = 0;
|
||||
MCF_INTC0_ICR27 = 0;
|
||||
MCF_INTC0_ICR28 = 0;
|
||||
MCF_INTC0_ICR29 = 0;
|
||||
MCF_INTC0_ICR30 = 0;
|
||||
MCF_INTC0_ICR31 = 0;
|
||||
MCF_INTC0_ICR32 = 0;
|
||||
MCF_INTC0_ICR33 = 0;
|
||||
MCF_INTC0_ICR34 = 0;
|
||||
MCF_INTC0_ICR35 = 0;
|
||||
MCF_INTC0_ICR36 = 0;
|
||||
MCF_INTC0_ICR37 = 0;
|
||||
MCF_INTC0_ICR38 = 0;
|
||||
MCF_INTC0_ICR39 = 0;
|
||||
MCF_INTC0_ICR40 = 0;
|
||||
MCF_INTC0_ICR41 = 0;
|
||||
MCF_INTC0_ICR42 = 0;
|
||||
MCF_INTC0_ICR43 = 0;
|
||||
MCF_INTC0_ICR44 = 0;
|
||||
MCF_INTC0_ICR45 = 0;
|
||||
MCF_INTC0_ICR46 = 0;
|
||||
MCF_INTC0_ICR47 = 0;
|
||||
MCF_INTC0_ICR48 = 0;
|
||||
MCF_INTC0_ICR49 = 0;
|
||||
MCF_INTC0_ICR50 = 0;
|
||||
MCF_INTC0_ICR51 = 0;
|
||||
MCF_INTC0_ICR52 = 0;
|
||||
MCF_INTC0_ICR53 = 0;
|
||||
MCF_INTC0_ICR54 = 0;
|
||||
MCF_INTC0_ICR55 = 0;
|
||||
MCF_INTC0_ICR56 = 0;
|
||||
MCF_INTC0_ICR57 = 0;
|
||||
MCF_INTC0_ICR58 = 0;
|
||||
MCF_INTC0_ICR59 = 0;
|
||||
MCF_INTC0_ICR60 = 0;
|
||||
MCF_INTC1_ICR8 = 0;
|
||||
MCF_INTC1_ICR9 = 0;
|
||||
MCF_INTC1_ICR10 = 0;
|
||||
MCF_INTC1_ICR11 = 0;
|
||||
MCF_INTC1_ICR12 = 0;
|
||||
MCF_INTC1_ICR13 = 0;
|
||||
MCF_INTC1_ICR14 = 0;
|
||||
MCF_INTC1_ICR15 = 0;
|
||||
MCF_INTC1_ICR16 = 0;
|
||||
MCF_INTC1_ICR17 = 0;
|
||||
MCF_INTC1_ICR18 = 0;
|
||||
MCF_INTC1_ICR19 = 0;
|
||||
MCF_INTC1_ICR20 = 0;
|
||||
MCF_INTC1_ICR21 = 0;
|
||||
MCF_INTC1_ICR22 = 0;
|
||||
MCF_INTC1_ICR23 = 0;
|
||||
MCF_INTC1_ICR24 = 0;
|
||||
MCF_INTC1_ICR25 = 0;
|
||||
MCF_INTC1_ICR27 = 0;
|
||||
MCF_INTC1_ICR28 = 0;
|
||||
MCF_INTC1_ICR29 = 0;
|
||||
MCF_INTC1_ICR30 = 0;
|
||||
MCF_INTC1_ICR31 = 0;
|
||||
MCF_INTC1_ICR32 = 0;
|
||||
MCF_INTC1_ICR33 = 0;
|
||||
MCF_INTC1_ICR34 = 0;
|
||||
MCF_INTC1_ICR35 = 0;
|
||||
MCF_INTC1_ICR36 = 0;
|
||||
MCF_INTC1_ICR37 = 0;
|
||||
MCF_INTC1_ICR38 = 0;
|
||||
MCF_INTC1_ICR39 = 0;
|
||||
MCF_INTC1_ICR40 = 0;
|
||||
MCF_INTC1_ICR41 = 0;
|
||||
MCF_INTC1_ICR42 = 0;
|
||||
MCF_INTC1_ICR59 = 0;
|
||||
MCF_INTC0_IMRH = 0xffffffff;
|
||||
MCF_INTC0_IMRL =
|
||||
MCF_INTC0_IMRL_INT_MASK31 | MCF_INTC0_IMRL_INT_MASK30 |
|
||||
MCF_INTC0_IMRL_INT_MASK29 | MCF_INTC0_IMRL_INT_MASK28 |
|
||||
MCF_INTC0_IMRL_INT_MASK27 | MCF_INTC0_IMRL_INT_MASK26 |
|
||||
MCF_INTC0_IMRL_INT_MASK25 | MCF_INTC0_IMRL_INT_MASK24 |
|
||||
MCF_INTC0_IMRL_INT_MASK23 | MCF_INTC0_IMRL_INT_MASK22 |
|
||||
MCF_INTC0_IMRL_INT_MASK21 | MCF_INTC0_IMRL_INT_MASK20 |
|
||||
MCF_INTC0_IMRL_INT_MASK19 | MCF_INTC0_IMRL_INT_MASK18 |
|
||||
MCF_INTC0_IMRL_INT_MASK17 | MCF_INTC0_IMRL_INT_MASK16 |
|
||||
MCF_INTC0_IMRL_INT_MASK15 | MCF_INTC0_IMRL_INT_MASK14 |
|
||||
MCF_INTC0_IMRL_INT_MASK13 | MCF_INTC0_IMRL_INT_MASK12 |
|
||||
MCF_INTC0_IMRL_INT_MASK11 | MCF_INTC0_IMRL_INT_MASK10 |
|
||||
MCF_INTC0_IMRL_INT_MASK9 | MCF_INTC0_IMRL_INT_MASK8 |
|
||||
MCF_INTC0_IMRL_INT_MASK7 | MCF_INTC0_IMRL_INT_MASK6 |
|
||||
MCF_INTC0_IMRL_INT_MASK5 | MCF_INTC0_IMRL_INT_MASK4 |
|
||||
MCF_INTC0_IMRL_INT_MASK3 | MCF_INTC0_IMRL_INT_MASK2 |
|
||||
MCF_INTC0_IMRL_INT_MASK1;
|
||||
MCF_INTC1_IMRH = 0xffffffff;
|
||||
MCF_INTC1_IMRL =
|
||||
MCF_INTC1_IMRL_INT_MASK31 | MCF_INTC1_IMRL_INT_MASK30 |
|
||||
MCF_INTC1_IMRL_INT_MASK29 | MCF_INTC1_IMRL_INT_MASK28 |
|
||||
MCF_INTC1_IMRL_INT_MASK27 | MCF_INTC1_IMRL_INT_MASK26 |
|
||||
MCF_INTC1_IMRL_INT_MASK25 | MCF_INTC1_IMRL_INT_MASK24 |
|
||||
MCF_INTC1_IMRL_INT_MASK23 | MCF_INTC1_IMRL_INT_MASK22 |
|
||||
MCF_INTC1_IMRL_INT_MASK21 | MCF_INTC1_IMRL_INT_MASK20 |
|
||||
MCF_INTC1_IMRL_INT_MASK19 | MCF_INTC1_IMRL_INT_MASK18 |
|
||||
MCF_INTC1_IMRL_INT_MASK17 | MCF_INTC1_IMRL_INT_MASK16 |
|
||||
MCF_INTC1_IMRL_INT_MASK15 | MCF_INTC1_IMRL_INT_MASK14 |
|
||||
MCF_INTC1_IMRL_INT_MASK13 | MCF_INTC1_IMRL_INT_MASK12 |
|
||||
MCF_INTC1_IMRL_INT_MASK11 | MCF_INTC1_IMRL_INT_MASK10 |
|
||||
MCF_INTC1_IMRL_INT_MASK9 | MCF_INTC1_IMRL_INT_MASK8 |
|
||||
MCF_INTC1_IMRL_INT_MASK7 | MCF_INTC1_IMRL_INT_MASK6 |
|
||||
MCF_INTC1_IMRL_INT_MASK5 | MCF_INTC1_IMRL_INT_MASK4 |
|
||||
MCF_INTC1_IMRL_INT_MASK3 | MCF_INTC1_IMRL_INT_MASK2 |
|
||||
MCF_INTC1_IMRL_INT_MASK1;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* init_pin_assignments - Pin Assignment and General Purpose I/O *
|
||||
**********************************************************************/
|
||||
static void
|
||||
init_pin_assignments( void )
|
||||
{
|
||||
|
||||
/* Pin assignments for port ADDR
|
||||
Pins are all GPIO inputs
|
||||
*/
|
||||
MCF_GPIO_PDDR_APDDR = 0;
|
||||
MCF_GPIO_PAR_AD = MCF_GPIO_PAR_AD_PAR_ADDR23
|
||||
| MCF_GPIO_PAR_AD_PAR_ADDR22
|
||||
| MCF_GPIO_PAR_AD_PAR_ADDR21 | MCF_GPIO_PAR_AD_PAR_DATAL;
|
||||
|
||||
/* Pin assignments for ports DATAH and DATAL
|
||||
Pins are all GPIO inputs
|
||||
*/
|
||||
MCF_GPIO_PDDR_DATAH = 0;
|
||||
MCF_GPIO_PDDR_DATAL = 0;
|
||||
|
||||
/* Pin assignments for port BUSCTL
|
||||
Pin /OE : External bus output enable, /OE
|
||||
Pin /TA : External bus transfer acknowledge, /TA
|
||||
Pin /TEA : External bus transfer error acknowledge, /TEA
|
||||
Pin R/W : External bus read/write indication, R/W
|
||||
Pin TSIZ1 : External bus transfer size TSIZ1 or DMA acknowledge /DACK1
|
||||
Pin TSIZ0 : External bus transfer size TSIZ0 or DMA acknowledge /DACK0
|
||||
Pin /TS : External bus transfer start, /TS
|
||||
Pin /TIP : External bus transfer in progess, /TIP
|
||||
*/
|
||||
MCF_GPIO_PDDR_BUSCTL = 0;
|
||||
MCF_GPIO_PAR_BUSCTL =
|
||||
MCF_GPIO_PAR_BUSCTL_PAR_OE | MCF_GPIO_PAR_BUSCTL_PAR_TA |
|
||||
MCF_GPIO_PAR_BUSCTL_PAR_TEA( 0x3 ) | MCF_GPIO_PAR_BUSCTL_PAR_RWB |
|
||||
MCF_GPIO_PAR_BUSCTL_PAR_TSIZ1 | MCF_GPIO_PAR_BUSCTL_PAR_TSIZ0 |
|
||||
MCF_GPIO_PAR_BUSCTL_PAR_TS( 0x3 ) |
|
||||
MCF_GPIO_PAR_BUSCTL_PAR_TIP( 0x3 );
|
||||
|
||||
/* Pin assignments for port BS
|
||||
Pin /BS3 : External byte strobe /BS3
|
||||
Pin /BS2 : External byte strobe /BS2
|
||||
Pin /BS1 : External byte strobe /BS1
|
||||
Pin /BS0 : External byte strobe /BS0
|
||||
*/
|
||||
MCF_GPIO_PDDR_BS = 0;
|
||||
MCF_GPIO_PAR_BS =
|
||||
MCF_GPIO_PAR_BS_PAR_BS3 | MCF_GPIO_PAR_BS_PAR_BS2 |
|
||||
MCF_GPIO_PAR_BS_PAR_BS1 | MCF_GPIO_PAR_BS_PAR_BS0;
|
||||
|
||||
/* Pin assignments for port CS
|
||||
Pin /CS7 : Chip select /CS7
|
||||
Pin /CS6 : Chip select /CS6
|
||||
Pin /CS5 : Chip select /CS5
|
||||
Pin /CS4 : Chip select /CS4
|
||||
Pin /CS3 : Chip select /CS3
|
||||
Pin /CS2 : Chip select /CS2
|
||||
Pin /CS1 : Chip select /CS1
|
||||
*/
|
||||
MCF_GPIO_PDDR_CS = 0;
|
||||
MCF_GPIO_PAR_CS =
|
||||
MCF_GPIO_PAR_CS_PAR_CS7 | MCF_GPIO_PAR_CS_PAR_CS6 |
|
||||
MCF_GPIO_PAR_CS_PAR_CS5 | MCF_GPIO_PAR_CS_PAR_CS4 |
|
||||
MCF_GPIO_PAR_CS_PAR_CS3 | MCF_GPIO_PAR_CS_PAR_CS2 |
|
||||
MCF_GPIO_PAR_CS_PAR_CS1;
|
||||
|
||||
/* Pin assignments for port SDRAM
|
||||
Pin /SD_WE : SDRAM controller /SD_WE
|
||||
Pin /SD_SCAS : SDRAM controller /SD_SCAS
|
||||
Pin /SD_SRAS : SDRAM controller /SD_SRAS
|
||||
Pin /SD_SCKE : SDRAM controller /SD_SCKE
|
||||
Pin /SD_CS1 : SDRAM controller /SD_CS1
|
||||
Pin /SD_CS0 : SDRAM controller /SD_CS0
|
||||
*/
|
||||
MCF_GPIO_PDDR_SDRAM = 0;
|
||||
MCF_GPIO_PAR_SDRAM =
|
||||
MCF_GPIO_PAR_SDRAM_PAR_SDWE | MCF_GPIO_PAR_SDRAM_PAR_SCAS |
|
||||
MCF_GPIO_PAR_SDRAM_PAR_SRAS | MCF_GPIO_PAR_SDRAM_PAR_SCKE |
|
||||
MCF_GPIO_PAR_SDRAM_PAR_SDCS1 | MCF_GPIO_PAR_SDRAM_PAR_SDCS0;
|
||||
|
||||
/* Pin assignments for port FECI2C
|
||||
Pins are all GPIO inputs
|
||||
*/
|
||||
MCF_GPIO_PDDR_FECI2C = 0;
|
||||
MCF_GPIO_PAR_FECI2C =
|
||||
MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC | MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC;
|
||||
|
||||
/* Pin assignments for port UARTL
|
||||
Pins are all GPIO inputs
|
||||
*/
|
||||
MCF_GPIO_PDDR_UARTL = 0;
|
||||
MCF_GPIO_PAR_UART = 0;
|
||||
|
||||
/* Pin assignments for port UARTH
|
||||
Pin U2TXD : GPIO input
|
||||
Pin U2RXD : GPIO input
|
||||
Pin /IRQ2 : Interrupt request /IRQ2 or GPIO
|
||||
*/
|
||||
MCF_GPIO_PDDR_UARTH = 0;
|
||||
|
||||
/* Pin assignments for port QSPI
|
||||
Pins are all GPIO inputs
|
||||
*/
|
||||
MCF_GPIO_PDDR_QSPI = 0;
|
||||
MCF_GPIO_PAR_QSPI = 0;
|
||||
|
||||
/* Pin assignments for port TIMER
|
||||
Pins are all GPIO inputs
|
||||
*/
|
||||
MCF_GPIO_PDDR_TIMER = 0;
|
||||
MCF_GPIO_PAR_TIMER = 0;
|
||||
|
||||
/* Pin assignments for port ETPU
|
||||
Pins are all GPIO inputs
|
||||
*/
|
||||
MCF_GPIO_PDDR_ETPU = 0;
|
||||
MCF_GPIO_PAR_ETPU = 0;
|
||||
}
|
||||
@ -0,0 +1,249 @@
|
||||
/*
|
||||
* Lowest level routines for all ColdFire processors. Based on the
|
||||
* MCF523x examples from Freescale.
|
||||
*
|
||||
* Freescale explicitly grants the redistribution and modification
|
||||
* of these source files. The complete licensing information is
|
||||
* available in the file LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* Modifications Copyright (c) 2006 Christian Walter <wolti@sil.at>
|
||||
*
|
||||
* File: $Id: mcf5xxx.S,v 1.2 2006/09/24 22:50:22 wolti Exp $
|
||||
*/
|
||||
|
||||
.global asm_set_ipl
|
||||
.global _asm_set_ipl
|
||||
.global mcf5xxx_wr_cacr
|
||||
.global _mcf5xxx_wr_cacr
|
||||
.global mcf5xxx_wr_acr0
|
||||
.global _mcf5xxx_wr_acr0
|
||||
.global mcf5xxx_wr_acr1
|
||||
.global _mcf5xxx_wr_acr1
|
||||
.global mcf5xxx_wr_acr2
|
||||
.global _mcf5xxx_wr_acr2
|
||||
.global mcf5xxx_wr_acr3
|
||||
.global _mcf5xxx_wr_acr3
|
||||
.global mcf5xxx_wr_other_sp
|
||||
.global _mcf5xxx_wr_other_sp
|
||||
.global mcf5xxx_wr_other_a7
|
||||
.global _mcf5xxx_wr_other_a7
|
||||
.global mcf5xxx_wr_vbr
|
||||
.global _mcf5xxx_wr_vbr
|
||||
.global mcf5xxx_wr_macsr
|
||||
.global _mcf5xxx_wr_macsr
|
||||
.global mcf5xxx_wr_mask
|
||||
.global _mcf5xxx_wr_mask
|
||||
.global mcf5xxx_wr_acc0
|
||||
.global _mcf5xxx_wr_acc0
|
||||
.global mcf5xxx_wr_accext01
|
||||
.global _mcf5xxx_wr_accext01
|
||||
.global mcf5xxx_wr_accext23
|
||||
.global _mcf5xxx_wr_accext23
|
||||
.global mcf5xxx_wr_acc1
|
||||
.global _mcf5xxx_wr_acc1
|
||||
.global mcf5xxx_wr_acc2
|
||||
.global _mcf5xxx_wr_acc2
|
||||
.global mcf5xxx_wr_acc3
|
||||
.global _mcf5xxx_wr_acc3
|
||||
.global mcf5xxx_wr_sr
|
||||
.global _mcf5xxx_wr_sr
|
||||
.global mcf5xxx_wr_rambar0
|
||||
.global _mcf5xxx_wr_rambar0
|
||||
.global mcf5xxx_wr_rambar1
|
||||
.global _mcf5xxx_wr_rambar1
|
||||
.global mcf5xxx_wr_mbar
|
||||
.global _mcf5xxx_wr_mbar
|
||||
.global mcf5xxx_wr_mbar0
|
||||
.global _mcf5xxx_wr_mbar0
|
||||
.global mcf5xxx_wr_mbar1
|
||||
.global _mcf5xxx_wr_mbar1
|
||||
|
||||
.text
|
||||
|
||||
/********************************************************************/
|
||||
/*
|
||||
* This routines changes the IPL to the value passed into the routine.
|
||||
* It also returns the old IPL value back.
|
||||
* Calling convention from C:
|
||||
* old_ipl = asm_set_ipl(new_ipl);
|
||||
* For the Diab Data C compiler, it passes return value thru D0.
|
||||
* Note that only the least significant three bits of the passed
|
||||
* value are used.
|
||||
*/
|
||||
|
||||
asm_set_ipl:
|
||||
_asm_set_ipl:
|
||||
link a6,#-8
|
||||
movem.l d6-d7,(sp)
|
||||
|
||||
move.w sr,d7 /* current sr */
|
||||
|
||||
move.l d7,d0 /* prepare return value */
|
||||
andi.l #0x0700,d0 /* mask out IPL */
|
||||
lsr.l #8,d0 /* IPL */
|
||||
|
||||
move.l 8(a6),d6 /* get argument */
|
||||
andi.l #0x07,d6 /* least significant three bits */
|
||||
lsl.l #8,d6 /* move over to make mask */
|
||||
|
||||
andi.l #0x0000F8FF,d7 /* zero out current IPL */
|
||||
or.l d6,d7 /* place new IPL in sr */
|
||||
move.w d7,sr
|
||||
|
||||
movem.l (sp),d6-d7
|
||||
lea 8(sp),sp
|
||||
unlk a6
|
||||
rts
|
||||
|
||||
/********************************************************************/
|
||||
/*
|
||||
* These routines write to the special purpose registers in the ColdFire
|
||||
* core. Since these registers are write-only in the supervisor model,
|
||||
* no corresponding read routines exist.
|
||||
*/
|
||||
|
||||
mcf5xxx_wr_cacr:
|
||||
_mcf5xxx_wr_cacr:
|
||||
move.l 4(sp),d0
|
||||
.long 0x4e7b0002 /* movec d0,cacr */
|
||||
nop
|
||||
rts
|
||||
|
||||
mcf5xxx_wr_acr0:
|
||||
_mcf5xxx_wr_acr0:
|
||||
move.l 4(sp),d0
|
||||
.long 0x4e7b0004 /* movec d0,ACR0 */
|
||||
nop
|
||||
rts
|
||||
|
||||
mcf5xxx_wr_acr1:
|
||||
_mcf5xxx_wr_acr1:
|
||||
move.l 4(sp),d0
|
||||
.long 0x4e7b0005 /* movec d0,ACR1 */
|
||||
nop
|
||||
rts
|
||||
|
||||
mcf5xxx_wr_acr2:
|
||||
_mcf5xxx_wr_acr2:
|
||||
move.l 4(sp),d0
|
||||
.long 0x4e7b0006 /* movec d0,ACR2 */
|
||||
nop
|
||||
rts
|
||||
|
||||
mcf5xxx_wr_acr3:
|
||||
_mcf5xxx_wr_acr3:
|
||||
move.l 4(sp),d0
|
||||
.long 0x4e7b0007 /* movec d0,ACR3 */
|
||||
nop
|
||||
rts
|
||||
|
||||
mcf5xxx_wr_other_sp:
|
||||
_mcf5xxx_wr_other_sp:
|
||||
mcf5xxx_wr_other_a7:
|
||||
_mcf5xxx_wr_other_a7:
|
||||
move.l 4(sp),d0
|
||||
.long 0x4e7b0800 /* movec d0,OTHER_A7 */
|
||||
nop
|
||||
rts
|
||||
|
||||
mcf5xxx_wr_vbr:
|
||||
_mcf5xxx_wr_vbr:
|
||||
move.l 4(sp),d0
|
||||
.long 0x4e7b0801 /* movec d0,VBR */
|
||||
nop
|
||||
rts
|
||||
|
||||
mcf5xxx_wr_macsr:
|
||||
_mcf5xxx_wr_macsr:
|
||||
move.l 4(sp),d0
|
||||
.long 0x4e7b0804 /* movec d0,MACSR */
|
||||
nop
|
||||
rts
|
||||
|
||||
mcf5xxx_wr_mask:
|
||||
_mcf5xxx_wr_mask:
|
||||
move.l 4(sp),d0
|
||||
.long 0x4e7b0805 /* movec d0,MASK */
|
||||
nop
|
||||
rts
|
||||
|
||||
mcf5xxx_wr_acc0:
|
||||
_mcf5xxx_wr_acc0:
|
||||
move.l 4(sp),d0
|
||||
.long 0x4e7b0806 /* movec d0,ACC0 */
|
||||
nop
|
||||
rts
|
||||
|
||||
mcf5xxx_wr_accext01:
|
||||
_mcf5xxx_wr_accext01:
|
||||
move.l 4(sp),d0
|
||||
.long 0x4e7b0807 /* movec d0,ACCEXT01 */
|
||||
nop
|
||||
rts
|
||||
|
||||
mcf5xxx_wr_accext23:
|
||||
_mcf5xxx_wr_accext23:
|
||||
move.l 4(sp),d0
|
||||
.long 0x4e7b0808 /* movec d0,ACCEXT23 */
|
||||
nop
|
||||
rts
|
||||
|
||||
mcf5xxx_wr_acc1:
|
||||
_mcf5xxx_wr_acc1:
|
||||
move.l 4(sp),d0
|
||||
.long 0x4e7b0809 /* movec d0,ACC1 */
|
||||
nop
|
||||
rts
|
||||
|
||||
mcf5xxx_wr_acc2:
|
||||
_mcf5xxx_wr_acc2:
|
||||
move.l 4(sp),d0
|
||||
.long 0x4e7b080A /* movec d0,ACC2 */
|
||||
nop
|
||||
rts
|
||||
|
||||
mcf5xxx_wr_acc3:
|
||||
_mcf5xxx_wr_acc3:
|
||||
move.l 4(sp),d0
|
||||
.long 0x4e7b080B /* movec d0,ACC3 */
|
||||
nop
|
||||
rts
|
||||
|
||||
mcf5xxx_wr_sr:
|
||||
_mcf5xxx_wr_sr:
|
||||
move.l 4(sp),d0
|
||||
move.w d0,SR
|
||||
rts
|
||||
|
||||
mcf5xxx_wr_rambar0:
|
||||
_mcf5xxx_wr_rambar0:
|
||||
move.l 4(sp),d0
|
||||
.long 0x4e7b0C04 /* movec d0,RAMBAR0 */
|
||||
nop
|
||||
rts
|
||||
|
||||
mcf5xxx_wr_rambar1:
|
||||
_mcf5xxx_wr_rambar1:
|
||||
move.l 4(sp),d0
|
||||
.long 0x4e7b0C05 /* movec d0,RAMBAR1 */
|
||||
nop
|
||||
rts
|
||||
|
||||
mcf5xxx_wr_mbar:
|
||||
_mcf5xxx_wr_mbar:
|
||||
mcf5xxx_wr_mbar0:
|
||||
_mcf5xxx_wr_mbar0:
|
||||
move.l 4(sp),d0
|
||||
.long 0x4e7b0C0F /* movec d0,MBAR0 */
|
||||
nop
|
||||
rts
|
||||
|
||||
mcf5xxx_wr_mbar1:
|
||||
_mcf5xxx_wr_mbar1:
|
||||
move.l 4(sp),d0
|
||||
.long 0x4e7b0C0E /* movec d0,MBAR1 */
|
||||
nop
|
||||
rts
|
||||
|
||||
.end
|
||||
/********************************************************************/
|
||||
@ -0,0 +1,146 @@
|
||||
/*
|
||||
FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter.
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with FreeRTOS; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
|
||||
A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes FreeRTOS, without being obliged to provide
|
||||
the source code for any proprietary components. See the licensing section
|
||||
of http://www.FreeRTOS.org for full details of how and when the exception
|
||||
can be applied.
|
||||
|
||||
***************************************************************************
|
||||
See http://www.FreeRTOS.org for documentation, latest information, license
|
||||
and contact details. Please ensure to read the configuration and relevant
|
||||
port sections of the online documentation.
|
||||
***************************************************************************
|
||||
*/
|
||||
|
||||
/* ------------------------ System includes ------------------------------- */
|
||||
#include <sys/types.h>
|
||||
#include <sys/stat.h>
|
||||
#include <unistd.h>
|
||||
#include <errno.h>
|
||||
|
||||
/* ------------------------ FreeRTOS includes ----------------------------- */
|
||||
#include <FreeRTOS.h>
|
||||
#include <serial.h>
|
||||
|
||||
/* ------------------------ Prototypes ------------------------------------ */
|
||||
void vSerialPutStringNOISR( xComPortHandle pxPort,
|
||||
const signed portCHAR * const pcString,
|
||||
unsigned portSHORT usStringLength );
|
||||
|
||||
/* ------------------------ Start implementation -------------------------- */
|
||||
void
|
||||
_exit( int status )
|
||||
{
|
||||
asm volatile ( "halt" );
|
||||
|
||||
for( ;; );
|
||||
}
|
||||
|
||||
pid_t
|
||||
getpid( void )
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
kill( pid_t pid, int sig )
|
||||
{
|
||||
_exit( 0 );
|
||||
}
|
||||
|
||||
int
|
||||
close( int fd )
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
fstat( int fd, struct stat *buf )
|
||||
{
|
||||
buf->st_mode = S_IFCHR;
|
||||
buf->st_blksize = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
ssize_t
|
||||
write( int fd, const void *buf, size_t nbytes )
|
||||
{
|
||||
ssize_t res = nbytes;
|
||||
extern xComPortHandle xSTDComPort;
|
||||
switch ( fd )
|
||||
{
|
||||
case STDERR_FILENO:
|
||||
vSerialPutStringNOISR( xSTDComPort,
|
||||
( const signed portCHAR * const )buf,
|
||||
( unsigned portSHORT )nbytes );
|
||||
break;
|
||||
case STDOUT_FILENO:
|
||||
vSerialPutString( xSTDComPort,
|
||||
( const signed portCHAR * const)buf,
|
||||
( unsigned portSHORT )nbytes );
|
||||
break;
|
||||
default:
|
||||
errno = EIO;
|
||||
res = -1;
|
||||
break;
|
||||
}
|
||||
return res;
|
||||
}
|
||||
|
||||
int
|
||||
read( int fd, void *buf, size_t nbytes )
|
||||
{
|
||||
switch ( fd )
|
||||
{
|
||||
default:
|
||||
errno = EIO;
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
int
|
||||
isatty( int fd )
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
off_t
|
||||
lseek( int fd, off_t offset, int whence )
|
||||
{
|
||||
errno = EIO;
|
||||
return ( off_t ) - 1;
|
||||
}
|
||||
|
||||
extern char _end[];
|
||||
char *heap_ptr;
|
||||
|
||||
void *
|
||||
sbrk( ptrdiff_t nbytes )
|
||||
{
|
||||
char *base;
|
||||
|
||||
if( !heap_ptr )
|
||||
heap_ptr = ( char * )&_end;
|
||||
base = heap_ptr;
|
||||
heap_ptr += nbytes;
|
||||
|
||||
return base;
|
||||
}
|
||||
@ -0,0 +1,298 @@
|
||||
/*
|
||||
FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter.
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with FreeRTOS; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
|
||||
A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes FreeRTOS, without being obliged to provide
|
||||
the source code for any proprietary components. See the licensing section
|
||||
of http://www.FreeRTOS.org for full details of how and when the exception
|
||||
can be applied.
|
||||
|
||||
***************************************************************************
|
||||
See http://www.FreeRTOS.org for documentation, latest information, license
|
||||
and contact details. Please ensure to read the configuration and relevant
|
||||
port sections of the online documentation.
|
||||
***************************************************************************
|
||||
*/
|
||||
|
||||
/* ------------------------ MCF523x includes ------------------------------ */
|
||||
#include "mcf5xxx.h"
|
||||
#include "mcf523x.h"
|
||||
|
||||
/* ------------------------ FreeRTOS includes ----------------------------- */
|
||||
#include "FreeRTOS.h"
|
||||
#include "queue.h"
|
||||
#include "task.h"
|
||||
|
||||
#include "serial.h"
|
||||
|
||||
/* ----------------------- Defines ----------------------------------------- */
|
||||
#define BAUDRATE_VALUE(fsys, baud) ( ( fsys )/(32UL * baud) )
|
||||
#define MCF_UART_VECTOR ( 64 + 13 )
|
||||
#define COM_NIFACE 1
|
||||
#define COM_BLOCK_RETRYTIME 10
|
||||
|
||||
/* ------------------------ Static functions ------------------------------ */
|
||||
static void prvSerialISR( void );
|
||||
|
||||
/* ------------------------ Static variables ------------------------------ */
|
||||
typedef struct
|
||||
{
|
||||
portBASE_TYPE xInitialized;
|
||||
xQueueHandle xRXChars;
|
||||
xQueueHandle xTXChars;
|
||||
} xComPortIF_t;
|
||||
|
||||
static xComPortIF_t xComPortIF[ COM_NIFACE ];
|
||||
|
||||
/* ------------------------ Begin implementation -------------------------- */
|
||||
xComPortHandle
|
||||
xSerialPortInitMinimal( unsigned portLONG ulWantedBaud,
|
||||
unsigned portBASE_TYPE uxQueueLength )
|
||||
{
|
||||
extern void ( *__RAMVEC[] ) ( );
|
||||
xComPortHandle xReturn;
|
||||
portBASE_TYPE xOldIPL;
|
||||
|
||||
/* Create the queues used to hold Rx and Tx characters. */
|
||||
xComPortIF[ 0 ].xRXChars =
|
||||
xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE )sizeof( signed portCHAR ) );
|
||||
xComPortIF[ 0 ].xTXChars =
|
||||
xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE )sizeof( signed portCHAR ) );
|
||||
|
||||
/* If the queues were created correctly then setup the serial port hardware. */
|
||||
if( ( xComPortIF[ 0 ].xRXChars != 0 ) && ( xComPortIF[ 0 ].xTXChars != 0 ) )
|
||||
{
|
||||
xOldIPL = portSET_IPL( portIPL_MAX );
|
||||
|
||||
/* UART 0: Reset transmitter, receiver and mode register pointer */
|
||||
MCF_UART_UCR0 = MCF_UART_UCR_MISC( 0x3 );
|
||||
MCF_UART_UCR0 = MCF_UART_UCR_MISC( 0x2 );
|
||||
MCF_UART_UCR0 = MCF_UART_UCR_MISC( 0x1 );
|
||||
|
||||
/* Enable receive interrupts. */
|
||||
MCF_UART_UIMR0 = MCF_UART_UIMR_RXRDY_FU;
|
||||
|
||||
/* 8 Databits, 1 Stopbit and no parity */
|
||||
MCF_UART_UMR0 = MCF_UART_UMR_PM( 0x3 ) | MCF_UART_UMR_SB( 0x7 ) | MCF_UART_UMR_BC( 0x3 );
|
||||
|
||||
/* UART 0 Clocking */
|
||||
MCF_UART_UCSR0 = MCF_UART_UCSR_RCS( 0xd ) | MCF_UART_UCSR_TCS( 0xd );
|
||||
MCF_UART_UBG10 = BAUDRATE_VALUE( FSYS_2, ulWantedBaud ) >> 8U;
|
||||
MCF_UART_UBG20 = BAUDRATE_VALUE( FSYS_2, ulWantedBaud ) & 0xFFU;
|
||||
|
||||
/* UART 0: Enable interrupts */
|
||||
__RAMVEC[MCF_UART_VECTOR] = prvSerialISR;
|
||||
MCF_INTC0_ICR13 = MCF_INTC0_ICRn_IL( 0x2 ) | MCF_INTC0_ICRn_IP( 0x1 );
|
||||
MCF_INTC0_IMRL &= ~MCF_INTC0_IMRL_INT_MASK13;
|
||||
|
||||
/* UART 0 Miscellaneous */
|
||||
MCF_UART_UACR0 = 0;
|
||||
|
||||
/* UART 0: Enable pins */
|
||||
MCF_GPIO_PAR_UART = MCF_GPIO_PAR_UART_PAR_U0RXD | MCF_GPIO_PAR_UART_PAR_U0TXD;
|
||||
|
||||
/* Enable the UART. */
|
||||
MCF_UART_UCR0 = MCF_UART_UCR_RXC( 0x1 ) | MCF_UART_UCR_TXC( 0x1 );
|
||||
|
||||
xComPortIF[ 0 ].xInitialized = TRUE;
|
||||
xReturn = ( xComPortHandle ) &xComPortIF[ 0 ];
|
||||
|
||||
( void )portSET_IPL( xOldIPL );
|
||||
}
|
||||
else
|
||||
{
|
||||
xReturn = ( xComPortHandle ) 0;
|
||||
}
|
||||
|
||||
return xReturn;
|
||||
}
|
||||
|
||||
signed portBASE_TYPE
|
||||
xSerialGetChar( xComPortHandle pxPort, signed portCHAR * pcRxedChar,
|
||||
portTickType xBlockTime )
|
||||
{
|
||||
int i;
|
||||
portBASE_TYPE xResult = pdFALSE;
|
||||
/* Lookup the correct interface. */
|
||||
for( i = 0; i < COM_NIFACE; i++ )
|
||||
{
|
||||
if( pxPort == ( xComPortHandle ) &xComPortIF[ i ] )
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
/* This COM port is available. */
|
||||
if( ( i != COM_NIFACE ) && xComPortIF[ i ].xInitialized )
|
||||
{
|
||||
/* Get the next character from the buffer. Return false if no characters
|
||||
* are available, or arrive before xBlockTime expires.
|
||||
*/
|
||||
if( xQueueReceive( xComPortIF[ i ].xRXChars, pcRxedChar, xBlockTime ) )
|
||||
{
|
||||
xResult = pdTRUE;
|
||||
}
|
||||
}
|
||||
return xResult;
|
||||
}
|
||||
|
||||
void
|
||||
vSerialPutString( xComPortHandle pxPort, const signed portCHAR *
|
||||
const pcString, unsigned portSHORT usStringLength )
|
||||
{
|
||||
int i;
|
||||
signed portCHAR *pChNext;
|
||||
|
||||
/* Send each character in the string, one at a time. */
|
||||
pChNext = ( signed portCHAR * )pcString;
|
||||
for( i = 0; i < usStringLength; i++ )
|
||||
{
|
||||
/* Block until character has been transmitted. */
|
||||
while( xSerialPutChar( pxPort, *pChNext, COM_BLOCK_RETRYTIME ) != pdTRUE ); pChNext++;
|
||||
}
|
||||
}
|
||||
|
||||
signed portBASE_TYPE
|
||||
xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar,
|
||||
portTickType xBlockTime )
|
||||
{
|
||||
int i;
|
||||
portBASE_TYPE xResult = pdFALSE;
|
||||
portBASE_TYPE xOldIPL;
|
||||
/* Lookup the correct interface. */
|
||||
for( i = 0; i < COM_NIFACE; i++ )
|
||||
{
|
||||
if( pxPort == ( xComPortHandle ) &xComPortIF[ i ] )
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
/* This COM port is available. */
|
||||
if( ( i != COM_NIFACE ) && xComPortIF[ i ].xInitialized )
|
||||
{
|
||||
/* Place the character in the queue of characters to be transmitted. */
|
||||
if( xQueueSend( xComPortIF[ i ].xTXChars, &cOutChar, xBlockTime ) == pdPASS )
|
||||
{
|
||||
/* Turn on the Tx interrupt so the ISR will remove the character from the
|
||||
* queue and send it. */
|
||||
MCF_UART_UIMR0 = MCF_UART_UIMR_TXRDY | MCF_UART_UIMR_RXRDY_FU;
|
||||
xResult = pdTRUE;
|
||||
}
|
||||
}
|
||||
return xResult;
|
||||
}
|
||||
|
||||
signed portBASE_TYPE
|
||||
xSerialPutCharNOISR( xComPortHandle pxPort, signed portCHAR cOutChar )
|
||||
{
|
||||
int i;
|
||||
portBASE_TYPE xResult = pdFALSE;
|
||||
portBASE_TYPE xOldIPL = portSET_IPL( portIPL_MAX );
|
||||
/* Lookup the correct interface. */
|
||||
for( i = 0; i < COM_NIFACE; i++ )
|
||||
{
|
||||
if( pxPort == ( xComPortHandle ) &xComPortIF[ i ] )
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
/* This COM port is available. Support for this only available for COM1 right now. */
|
||||
if( ( i != COM_NIFACE ) && ( i == 0 ) )
|
||||
{
|
||||
/* Wait until the transmit buffer is ready. */
|
||||
while( !( MCF_UART_USR0 & MCF_UART_USR_TXRDY ) );
|
||||
/* Place the character in the transmit buffer. */
|
||||
MCF_UART_UTB0 = cOutChar;
|
||||
xResult = pdTRUE;
|
||||
}
|
||||
( void )portSET_IPL( xOldIPL );
|
||||
return xResult;
|
||||
}
|
||||
|
||||
void
|
||||
vSerialPutStringNOISR( xComPortHandle pxPort, const signed portCHAR *
|
||||
const pcString, unsigned portSHORT usStringLength )
|
||||
{
|
||||
int i;
|
||||
signed portCHAR *pChNext;
|
||||
portBASE_TYPE xOldIPL = portSET_IPL( portIPL_MAX );
|
||||
|
||||
/* Send each character in the string, one at a time. */
|
||||
pChNext = ( signed portCHAR * )pcString;
|
||||
for( i = 0; i < usStringLength; i++ )
|
||||
{
|
||||
/* Block until character has been transmitted. */
|
||||
while( xSerialPutCharNOISR( pxPort, *pChNext ) != pdTRUE );
|
||||
pChNext++;
|
||||
}
|
||||
( void )portSET_IPL( xOldIPL );
|
||||
}
|
||||
|
||||
void
|
||||
vSerialClose( xComPortHandle xPort )
|
||||
{
|
||||
/* Not supported as not required by the demo application. */
|
||||
}
|
||||
|
||||
void
|
||||
prvSerialISR( void )
|
||||
{
|
||||
static signed portCHAR cChar;
|
||||
static portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByRx = pdFALSE;
|
||||
|
||||
/* We have to remvoe the effect of the GCC. Please note that the
|
||||
* __attribute__ ((interrupt_handler)) does not work here because we
|
||||
* have to do the storing of the registers ourself. Another problem
|
||||
* is the usage of a frame pointer which is unlinked on entry.
|
||||
*/
|
||||
#if _GCC_USES_FP == 1
|
||||
asm volatile ( "unlk %fp\n\t" );
|
||||
#endif
|
||||
/* This ISR can cause a context switch, so the first statement must be
|
||||
* a call to the portENTER_SWITCHING_ISR() macro. This must be BEFORE any
|
||||
* variable declarations.
|
||||
*/
|
||||
portENTER_SWITCHING_ISR();
|
||||
|
||||
/* Ready to send a character from the buffer. */
|
||||
if( MCF_UART_USR0 & MCF_UART_USR_TXRDY )
|
||||
{
|
||||
/* Transmit buffer is ready. Test if there are characters available. */
|
||||
if( xQueueReceiveFromISR( xComPortIF[ 0 ].xTXChars, &cChar, &xTaskWokenByTx ) ==
|
||||
pdTRUE )
|
||||
{
|
||||
/* A character was retrieved from the queue so can be sent. */
|
||||
MCF_UART_UTB0 = cChar;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Leave only receiver enabled. */
|
||||
MCF_UART_UIMR0 = MCF_UART_UIMR_RXRDY_FU;
|
||||
}
|
||||
}
|
||||
if( MCF_UART_USR0 & MCF_UART_USR_RXRDY )
|
||||
{
|
||||
cChar = MCF_UART_URB0;
|
||||
xTaskWokenByRx =
|
||||
xQueueSendFromISR( xComPortIF[ 0].xRXChars, &cChar, xTaskWokenByRx );
|
||||
}
|
||||
/* Exit the ISR. If a task was woken by either a character being
|
||||
* or transmitted then a context switch will occur.
|
||||
*/
|
||||
portEXIT_SWITCHING_ISR( ( xTaskWokenByTx || xTaskWokenByRx ) );
|
||||
}
|
||||
@ -0,0 +1,302 @@
|
||||
/*
|
||||
FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter.
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with FreeRTOS; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
|
||||
A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes FreeRTOS, without being obliged to provide
|
||||
the source code for any proprietary components. See the licensing section
|
||||
of http://www.FreeRTOS.org for full details of how and when the exception
|
||||
can be applied.
|
||||
|
||||
***************************************************************************
|
||||
See http://www.FreeRTOS.org for documentation, latest information, license
|
||||
and contact details. Please ensure to read the configuration and relevant
|
||||
port sections of the online documentation.
|
||||
***************************************************************************
|
||||
*/
|
||||
|
||||
.extern __stack
|
||||
.extern start
|
||||
.extern fec_handler
|
||||
.extern fec_if
|
||||
.extern decrement_timers
|
||||
.global __RAMVEC
|
||||
.global __ROMVEC
|
||||
|
||||
.equ MCF_PIT_PCSR0, IPSBAR + 0x150000
|
||||
.equ MCF_PIT_PCSR_PIF, 0x0004
|
||||
|
||||
.section .vector_rom, "x"
|
||||
__ROMVEC:
|
||||
.long __stack /* Reset: Initial Stack Pointer */
|
||||
.long start /* Reset: Initial Program Counter */
|
||||
.long VecDefault /* Bus Error */
|
||||
.long VecDefault /* Address Error */
|
||||
.long VecDefault /* Illegal Instruction */
|
||||
.long VecDefault /* Zero Divison */
|
||||
.space 4 /* reserved */
|
||||
.space 4 /* reserved */
|
||||
.long VecDefault /* Privilege Violation */
|
||||
.long VecDefault /* Trace */
|
||||
.long VecDefault /* Unimplemented line-a opcode */
|
||||
.long VecDefault /* Unimplemented line-b opcode */
|
||||
.long VecDefault /* Non-PC breakpoint debug interrupt */
|
||||
.long VecDefault /* PC breakpoint debug interrupt */
|
||||
.long VecDefault /* Format Error */
|
||||
.long VecDefault /* Uninitialized Interrupt */
|
||||
.org 0x60
|
||||
.long IRQSpurious /* Spurious Interrupt */
|
||||
.long IRQDefault /* Level 1 Interrupt */
|
||||
.long IRQDefault /* Level 2 Interrupt */
|
||||
.long IRQDefault /* Level 3 Interrupt */
|
||||
.long IRQDefault /* Level 4 Interrupt */
|
||||
.long IRQDefault /* Level 5 Interrupt */
|
||||
.long IRQDefault /* Level 6 Interrupt */
|
||||
.long IRQDefault /* Level 7 Interrupt */
|
||||
.org 0x80
|
||||
.long TrapDefault /* TRAP 0 */
|
||||
.long TrapDefault /* TRAP 1 */
|
||||
.long TrapDefault /* TRAP 2 */
|
||||
.long TrapDefault /* TRAP 3 */
|
||||
.long TrapDefault /* TRAP 4 */
|
||||
.long TrapDefault /* TRAP 5 */
|
||||
.long TrapDefault /* TRAP 6 */
|
||||
.long TrapDefault /* TRAP 7 */
|
||||
.long TrapDefault /* TRAP 8 */
|
||||
.long TrapDefault /* TRAP 9 */
|
||||
.long TrapDefault /* TRAP 10 */
|
||||
.long TrapDefault /* TRAP 11 */
|
||||
.long TrapDefault /* TRAP 12 */
|
||||
.long TrapDefault /* TRAP 13 */
|
||||
.long TrapDefault /* TRAP 14 */
|
||||
.long TrapDefault /* TRAP 15 */
|
||||
.org 0x100
|
||||
.long IRQDefault /* User-Defined Interrupt 0 */
|
||||
.long IRQDefault /* User-Defined Interrupt 1 */
|
||||
.long IRQDefault /* User-Defined Interrupt 2 */
|
||||
.long IRQDefault /* User-Defined Interrupt 3 */
|
||||
.long IRQDefault /* User-Defined Interrupt 4 */
|
||||
.long IRQDefault /* User-Defined Interrupt 5 */
|
||||
.long IRQDefault /* User-Defined Interrupt 6 */
|
||||
.long IRQDefault /* User-Defined Interrupt 7 */
|
||||
.long IRQDefault /* User-Defined Interrupt 8 */
|
||||
.long IRQDefault /* User-Defined Interrupt 9 */
|
||||
.long IRQDefault /* User-Defined Interrupt 10 */
|
||||
.long IRQDefault /* User-Defined Interrupt 11 */
|
||||
.long IRQDefault /* User-Defined Interrupt 12 */
|
||||
.long IRQDefault /* User-Defined Interrupt 13 */
|
||||
.long IRQDefault /* User-Defined Interrupt 14 */
|
||||
.long IRQDefault /* User-Defined Interrupt 15 */
|
||||
.long IRQDefault /* User-Defined Interrupt 16 */
|
||||
.long IRQDefault /* User-Defined Interrupt 17 */
|
||||
.long IRQDefault /* User-Defined Interrupt 18 */
|
||||
.long IRQDefault /* User-Defined Interrupt 19 */
|
||||
.long IRQDefault /* User-Defined Interrupt 20 */
|
||||
.long IRQDefault /* User-Defined Interrupt 21 */
|
||||
.long IRQDefault /* User-Defined Interrupt 22 */
|
||||
.long IRQDefault /* Transmit frame interrupt */
|
||||
.long IRQDefault /* Transmit buffer interrupt */
|
||||
.long IRQDefault /* Transmit FIFO underrun */
|
||||
.long IRQDefault /* Collision retry limit */
|
||||
.long IRQDefault /* Receive frame interrupt */
|
||||
.long IRQDefault /* Receive buffer interrupt */
|
||||
.long IRQDefault /* MII interrupt */
|
||||
.long IRQDefault /* Late collision */
|
||||
.long IRQDefault /* Heartbeat error */
|
||||
.long IRQDefault /* Graceful stop complete */
|
||||
.long IRQDefault /* Ethernet bus error */
|
||||
.long IRQDefault /* Babbling transmit error */
|
||||
.long IRQDefault /* Babbling receive error */
|
||||
.long IRQDefault /* Timer interrupt */
|
||||
.long IRQDefault /* User-Defined Interrupt 37 */
|
||||
.long IRQDefault /* User-Defined Interrupt 38 */
|
||||
.long IRQDefault /* User-Defined Interrupt 39 */
|
||||
.long IRQDefault /* User-Defined Interrupt 40 */
|
||||
.long IRQDefault /* User-Defined Interrupt 41 */
|
||||
.long IRQDefault /* User-Defined Interrupt 42 */
|
||||
.long IRQDefault /* User-Defined Interrupt 43 */
|
||||
.long IRQDefault /* User-Defined Interrupt 44 */
|
||||
.long IRQDefault /* User-Defined Interrupt 45 */
|
||||
.long IRQDefault /* User-Defined Interrupt 46 */
|
||||
.long IRQDefault /* User-Defined Interrupt 47 */
|
||||
.long IRQDefault /* User-Defined Interrupt 48 */
|
||||
.long IRQDefault /* User-Defined Interrupt 49 */
|
||||
.long IRQDefault /* User-Defined Interrupt 50 */
|
||||
.long IRQDefault /* User-Defined Interrupt 51 */
|
||||
.long IRQDefault /* User-Defined Interrupt 52 */
|
||||
.long IRQDefault /* User-Defined Interrupt 53 */
|
||||
.long IRQDefault /* User-Defined Interrupt 54 */
|
||||
.long IRQDefault /* User-Defined Interrupt 55 */
|
||||
.long IRQDefault /* User-Defined Interrupt 56 */
|
||||
.long IRQDefault /* User-Defined Interrupt 57 */
|
||||
.long IRQDefault /* User-Defined Interrupt 58 */
|
||||
.long IRQDefault /* User-Defined Interrupt 59 */
|
||||
.long IRQDefault /* User-Defined Interrupt 60 */
|
||||
.long IRQDefault /* User-Defined Interrupt 61 */
|
||||
.long IRQDefault /* User-Defined Interrupt 62 */
|
||||
.long IRQDefault /* User-Defined Interrupt 63 */
|
||||
.long IRQDefault /* User-Defined Interrupt 64 */
|
||||
.long IRQDefault /* User-Defined Interrupt 65 */
|
||||
.long IRQDefault /* User-Defined Interrupt 66 */
|
||||
.long IRQDefault /* User-Defined Interrupt 67 */
|
||||
.long IRQDefault /* User-Defined Interrupt 68 */
|
||||
.long IRQDefault /* User-Defined Interrupt 69 */
|
||||
.long IRQDefault /* User-Defined Interrupt 70 */
|
||||
.long IRQDefault /* User-Defined Interrupt 71 */
|
||||
.long IRQDefault /* User-Defined Interrupt 72 */
|
||||
.long IRQDefault /* User-Defined Interrupt 73 */
|
||||
.long IRQDefault /* User-Defined Interrupt 74 */
|
||||
.long IRQDefault /* User-Defined Interrupt 75 */
|
||||
.long IRQDefault /* User-Defined Interrupt 76 */
|
||||
.long IRQDefault /* User-Defined Interrupt 77 */
|
||||
.long IRQDefault /* User-Defined Interrupt 78 */
|
||||
.long IRQDefault /* User-Defined Interrupt 79 */
|
||||
.long IRQDefault /* User-Defined Interrupt 80 */
|
||||
.long IRQDefault /* User-Defined Interrupt 81 */
|
||||
.long IRQDefault /* User-Defined Interrupt 82 */
|
||||
.long IRQDefault /* User-Defined Interrupt 83 */
|
||||
.long IRQDefault /* User-Defined Interrupt 84 */
|
||||
.long IRQDefault /* User-Defined Interrupt 85 */
|
||||
.long IRQDefault /* User-Defined Interrupt 86 */
|
||||
.long IRQDefault /* User-Defined Interrupt 87 */
|
||||
.long IRQDefault /* User-Defined Interrupt 88 */
|
||||
.long IRQDefault /* User-Defined Interrupt 89 */
|
||||
.long IRQDefault /* User-Defined Interrupt 90 */
|
||||
.long IRQDefault /* User-Defined Interrupt 91 */
|
||||
.long IRQDefault /* User-Defined Interrupt 92 */
|
||||
.long IRQDefault /* User-Defined Interrupt 93 */
|
||||
.long IRQDefault /* User-Defined Interrupt 94 */
|
||||
.long IRQDefault /* User-Defined Interrupt 95 */
|
||||
.long IRQDefault /* User-Defined Interrupt 96 */
|
||||
.long IRQDefault /* User-Defined Interrupt 97 */
|
||||
.long IRQDefault /* User-Defined Interrupt 98 */
|
||||
.long IRQDefault /* User-Defined Interrupt 99 */
|
||||
.long IRQDefault /* User-Defined Interrupt 100 */
|
||||
.long IRQDefault /* User-Defined Interrupt 101 */
|
||||
.long IRQDefault /* User-Defined Interrupt 102 */
|
||||
.long IRQDefault /* User-Defined Interrupt 103 */
|
||||
.long IRQDefault /* User-Defined Interrupt 104 */
|
||||
.long IRQDefault /* User-Defined Interrupt 105 */
|
||||
.long IRQDefault /* User-Defined Interrupt 106 */
|
||||
.long IRQDefault /* User-Defined Interrupt 107 */
|
||||
.long IRQDefault /* User-Defined Interrupt 108 */
|
||||
.long IRQDefault /* User-Defined Interrupt 109 */
|
||||
.long IRQDefault /* User-Defined Interrupt 110 */
|
||||
.long IRQDefault /* User-Defined Interrupt 111 */
|
||||
.long IRQDefault /* User-Defined Interrupt 112 */
|
||||
.long IRQDefault /* User-Defined Interrupt 113 */
|
||||
.long IRQDefault /* User-Defined Interrupt 114 */
|
||||
.long IRQDefault /* User-Defined Interrupt 115 */
|
||||
.long IRQDefault /* User-Defined Interrupt 116 */
|
||||
.long IRQDefault /* User-Defined Interrupt 117 */
|
||||
.long IRQDefault /* User-Defined Interrupt 118 */
|
||||
.long IRQDefault /* User-Defined Interrupt 119 */
|
||||
.long IRQDefault /* User-Defined Interrupt 120 */
|
||||
.long IRQDefault /* User-Defined Interrupt 121 */
|
||||
.long IRQDefault /* User-Defined Interrupt 122 */
|
||||
.long IRQDefault /* User-Defined Interrupt 123 */
|
||||
.long IRQDefault /* User-Defined Interrupt 124 */
|
||||
.long IRQDefault /* User-Defined Interrupt 125 */
|
||||
.long IRQDefault /* User-Defined Interrupt 126 */
|
||||
.long IRQDefault /* User-Defined Interrupt 127 */
|
||||
.long IRQDefault /* User-Defined Interrupt 128 */
|
||||
.long IRQDefault /* User-Defined Interrupt 129 */
|
||||
.long IRQDefault /* User-Defined Interrupt 130 */
|
||||
.long IRQDefault /* User-Defined Interrupt 131 */
|
||||
.long IRQDefault /* User-Defined Interrupt 132 */
|
||||
.long IRQDefault /* User-Defined Interrupt 133 */
|
||||
.long IRQDefault /* User-Defined Interrupt 134 */
|
||||
.long IRQDefault /* User-Defined Interrupt 135 */
|
||||
.long IRQDefault /* User-Defined Interrupt 136 */
|
||||
.long IRQDefault /* User-Defined Interrupt 137 */
|
||||
.long IRQDefault /* User-Defined Interrupt 138 */
|
||||
.long IRQDefault /* User-Defined Interrupt 139 */
|
||||
.long IRQDefault /* User-Defined Interrupt 140 */
|
||||
.long IRQDefault /* User-Defined Interrupt 141 */
|
||||
.long IRQDefault /* User-Defined Interrupt 142 */
|
||||
.long IRQDefault /* User-Defined Interrupt 143 */
|
||||
.long IRQDefault /* User-Defined Interrupt 144 */
|
||||
.long IRQDefault /* User-Defined Interrupt 145 */
|
||||
.long IRQDefault /* User-Defined Interrupt 146 */
|
||||
.long IRQDefault /* User-Defined Interrupt 147 */
|
||||
.long IRQDefault /* User-Defined Interrupt 148 */
|
||||
.long IRQDefault /* User-Defined Interrupt 149 */
|
||||
.long IRQDefault /* User-Defined Interrupt 150 */
|
||||
.long IRQDefault /* User-Defined Interrupt 151 */
|
||||
.long IRQDefault /* User-Defined Interrupt 152 */
|
||||
.long IRQDefault /* User-Defined Interrupt 153 */
|
||||
.long IRQDefault /* User-Defined Interrupt 154 */
|
||||
.long IRQDefault /* User-Defined Interrupt 155 */
|
||||
.long IRQDefault /* User-Defined Interrupt 156 */
|
||||
.long IRQDefault /* User-Defined Interrupt 157 */
|
||||
.long IRQDefault /* User-Defined Interrupt 158 */
|
||||
.long IRQDefault /* User-Defined Interrupt 159 */
|
||||
.long IRQDefault /* User-Defined Interrupt 160 */
|
||||
.long IRQDefault /* User-Defined Interrupt 161 */
|
||||
.long IRQDefault /* User-Defined Interrupt 162 */
|
||||
.long IRQDefault /* User-Defined Interrupt 163 */
|
||||
.long IRQDefault /* User-Defined Interrupt 164 */
|
||||
.long IRQDefault /* User-Defined Interrupt 165 */
|
||||
.long IRQDefault /* User-Defined Interrupt 166 */
|
||||
.long IRQDefault /* User-Defined Interrupt 167 */
|
||||
.long IRQDefault /* User-Defined Interrupt 168 */
|
||||
.long IRQDefault /* User-Defined Interrupt 169 */
|
||||
.long IRQDefault /* User-Defined Interrupt 170 */
|
||||
.long IRQDefault /* User-Defined Interrupt 171 */
|
||||
.long IRQDefault /* User-Defined Interrupt 172 */
|
||||
.long IRQDefault /* User-Defined Interrupt 173 */
|
||||
.long IRQDefault /* User-Defined Interrupt 174 */
|
||||
.long IRQDefault /* User-Defined Interrupt 175 */
|
||||
.long IRQDefault /* User-Defined Interrupt 176 */
|
||||
.long IRQDefault /* User-Defined Interrupt 177 */
|
||||
.long IRQDefault /* User-Defined Interrupt 178 */
|
||||
.long IRQDefault /* User-Defined Interrupt 179 */
|
||||
.long IRQDefault /* User-Defined Interrupt 180 */
|
||||
.long IRQDefault /* User-Defined Interrupt 181 */
|
||||
.long IRQDefault /* User-Defined Interrupt 182 */
|
||||
.long IRQDefault /* User-Defined Interrupt 183 */
|
||||
.long IRQDefault /* User-Defined Interrupt 184 */
|
||||
.long IRQDefault /* User-Defined Interrupt 185 */
|
||||
.long IRQDefault /* User-Defined Interrupt 186 */
|
||||
.long IRQDefault /* User-Defined Interrupt 187 */
|
||||
.long IRQDefault /* User-Defined Interrupt 188 */
|
||||
.long IRQDefault /* User-Defined Interrupt 189 */
|
||||
.long IRQDefault /* User-Defined Interrupt 190 */
|
||||
.long IRQDefault /* User-Defined Interrupt 191 */
|
||||
.org 0x00000400
|
||||
|
||||
.section .vector_ram
|
||||
__RAMVEC:
|
||||
.space 0x400
|
||||
|
||||
.section .text
|
||||
VecDefault:
|
||||
halt
|
||||
bra VecDefault
|
||||
|
||||
IRQDefault:
|
||||
halt
|
||||
bra IRQDefault
|
||||
|
||||
IRQSpurious:
|
||||
halt
|
||||
bra IRQSpurious
|
||||
|
||||
TrapDefault:
|
||||
halt
|
||||
bra TrapDefault
|
||||
@ -0,0 +1,77 @@
|
||||
/*
|
||||
FreeRTOS.org V4.1.0 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
FreeRTOS.org is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
FreeRTOS.org is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with FreeRTOS.org; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
|
||||
A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes FreeRTOS.org, without being obliged to provide
|
||||
the source code for any proprietary components. See the licensing section
|
||||
of http://www.FreeRTOS.org for full details of how and when the exception
|
||||
can be applied.
|
||||
|
||||
***************************************************************************
|
||||
See http://www.FreeRTOS.org for documentation, latest information, license
|
||||
and contact details. Please ensure to read the configuration and relevant
|
||||
port sections of the online documentation.
|
||||
***************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef FREERTOS_CONFIG_H
|
||||
#define FREERTOS_CONFIG_H
|
||||
|
||||
#include <p24FJ128GA010.h>
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Application specific definitions.
|
||||
*
|
||||
* These definitions should be adjusted for your particular hardware and
|
||||
* application requirements.
|
||||
*
|
||||
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
|
||||
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
|
||||
*----------------------------------------------------------*/
|
||||
|
||||
#define configUSE_PREEMPTION 1
|
||||
#define configUSE_IDLE_HOOK 1
|
||||
#define configUSE_TICK_HOOK 0
|
||||
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
|
||||
#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 16000000 ) /* Fosc / 2 */
|
||||
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 )
|
||||
#define configMINIMAL_STACK_SIZE ( 105 )
|
||||
#define configTOTAL_HEAP_SIZE ( ( size_t ) 5120 )
|
||||
#define configMAX_TASK_NAME_LEN ( 4 )
|
||||
#define configUSE_TRACE_FACILITY 0
|
||||
#define configUSE_16_BIT_TICKS 1
|
||||
#define configIDLE_SHOULD_YIELD 1
|
||||
|
||||
/* Co-routine definitions. */
|
||||
#define configUSE_CO_ROUTINES 1
|
||||
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
|
||||
|
||||
/* Set the following definitions to 1 to include the API function, or zero
|
||||
to exclude the API function. */
|
||||
|
||||
#define INCLUDE_vTaskPrioritySet 1
|
||||
#define INCLUDE_uxTaskPriorityGet 0
|
||||
#define INCLUDE_vTaskDelete 0
|
||||
#define INCLUDE_vTaskCleanUpResources 0
|
||||
#define INCLUDE_vTaskSuspend 1
|
||||
#define INCLUDE_vTaskDelayUntil 1
|
||||
#define INCLUDE_vTaskDelay 1
|
||||
|
||||
|
||||
#endif /* FREERTOS_CONFIG_H */
|
||||
@ -0,0 +1,103 @@
|
||||
/*
|
||||
FreeRTOS.org V4.1.0 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
FreeRTOS.org is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
FreeRTOS.org is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with FreeRTOS.org; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
|
||||
A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes FreeRTOS.org, without being obliged to provide
|
||||
the source code for any proprietary components. See the licensing section
|
||||
of http://www.FreeRTOS.org for full details of how and when the exception
|
||||
can be applied.
|
||||
|
||||
***************************************************************************
|
||||
See http://www.FreeRTOS.org for documentation, latest information, license
|
||||
and contact details. Please ensure to read the configuration and relevant
|
||||
port sections of the online documentation.
|
||||
***************************************************************************
|
||||
*/
|
||||
|
||||
/* Scheduler includes. */
|
||||
#include "FreeRTOS.h"
|
||||
|
||||
/* Demo app includes. */
|
||||
#include "partest.h"
|
||||
|
||||
#define ptOUTPUT 0
|
||||
#define ptALL_OFF 0
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Simple parallel port IO routines.
|
||||
*-----------------------------------------------------------*/
|
||||
|
||||
void vParTestInitialise( void )
|
||||
{
|
||||
/* The explorer 16 board has LED's on port A. All bits are set as output
|
||||
so PORTA is read-modified-written directly. */
|
||||
TRISA = ptOUTPUT;
|
||||
PORTA = ptALL_OFF;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
|
||||
{
|
||||
unsigned portBASE_TYPE uxLEDBit;
|
||||
|
||||
/* Which port A bit is being modified? */
|
||||
uxLEDBit = 1 << uxLED;
|
||||
|
||||
if( xValue )
|
||||
{
|
||||
/* Turn the LED on. */
|
||||
portENTER_CRITICAL();
|
||||
{
|
||||
PORTA |= uxLEDBit;
|
||||
}
|
||||
portEXIT_CRITICAL();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Turn the LED off. */
|
||||
portENTER_CRITICAL();
|
||||
{
|
||||
PORTA &= ~uxLEDBit;
|
||||
}
|
||||
portEXIT_CRITICAL();
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
|
||||
{
|
||||
unsigned portBASE_TYPE uxLEDBit;
|
||||
|
||||
uxLEDBit = 1 << uxLED;
|
||||
portENTER_CRITICAL();
|
||||
{
|
||||
/* If the LED is already on - turn it off. If the LED is already
|
||||
off, turn it on. */
|
||||
if( PORTA & uxLEDBit )
|
||||
{
|
||||
PORTA &= ~uxLEDBit;
|
||||
}
|
||||
else
|
||||
{
|
||||
PORTA |= uxLEDBit;
|
||||
}
|
||||
}
|
||||
portEXIT_CRITICAL();
|
||||
}
|
||||
|
||||
@ -0,0 +1,3 @@
|
||||
[Header]
|
||||
MagicCookie={0b13fe8c-dfe0-40eb-8900-6712719559a7}
|
||||
Version=1.0
|
||||
Binary file not shown.
@ -0,0 +1,67 @@
|
||||
[HEADER]
|
||||
magic_cookie={66E99B07-E706-4689-9E80-9B2582898A13}
|
||||
file_version=1.0
|
||||
[PATH_INFO]
|
||||
dir_src=
|
||||
dir_bin=
|
||||
dir_tmp=
|
||||
dir_sin=
|
||||
dir_inc=.;C:\E\Dev\FreeRTOS\Demo\Common\include;C:\E\Dev\FreeRTOS\Demo\PIC24_MPLAB;C:\E\Dev\FreeRTOS\source\include
|
||||
dir_lib=
|
||||
dir_lkr=
|
||||
[CAT_FILTERS]
|
||||
filter_src=*.s;*.c
|
||||
filter_inc=*.h;*.inc
|
||||
filter_obj=*.o
|
||||
filter_lib=*.a
|
||||
filter_lkr=*.gld
|
||||
[OTHER_FILES]
|
||||
file_000=no
|
||||
file_001=no
|
||||
file_002=no
|
||||
file_003=no
|
||||
file_004=no
|
||||
file_005=no
|
||||
file_006=no
|
||||
file_007=no
|
||||
file_008=no
|
||||
file_009=no
|
||||
file_010=no
|
||||
file_011=no
|
||||
file_012=no
|
||||
file_013=no
|
||||
file_014=no
|
||||
file_015=no
|
||||
file_016=no
|
||||
file_017=no
|
||||
file_018=no
|
||||
file_019=no
|
||||
[FILE_INFO]
|
||||
file_000=main.c
|
||||
file_001=..\..\source\list.c
|
||||
file_002=..\..\source\queue.c
|
||||
file_003=..\..\source\tasks.c
|
||||
file_004=..\..\source\portable\MPLAB\PIC24_dsPIC\port.c
|
||||
file_005=..\..\source\portable\MemMang\heap_1.c
|
||||
file_006=..\Common\Minimal\BlockQ.c
|
||||
file_007=..\..\source\croutine.c
|
||||
file_008=..\Common\Minimal\crflash.c
|
||||
file_009=ParTest\ParTest.c
|
||||
file_010=..\Common\Minimal\blocktim.c
|
||||
file_011=..\Common\Minimal\integer.c
|
||||
file_012=..\Common\Minimal\comtest.c
|
||||
file_013=serial\serial.c
|
||||
file_014=..\..\source\include\semphr.h
|
||||
file_015=..\..\source\include\task.h
|
||||
file_016=..\..\source\include\croutine.h
|
||||
file_017=..\..\source\include\queue.h
|
||||
file_018=FreeRTOSConfig.h
|
||||
file_019=p24FJ128GA010.gld
|
||||
[SUITE_INFO]
|
||||
suite_guid={479DDE59-4D56-455E-855E-FFF59A3DB57E}
|
||||
suite_state=
|
||||
[TOOL_SETTINGS]
|
||||
TS{7D9C6ECE-785D-44CB-BA22-17BF2E119622}=-g
|
||||
TS{25AC22BD-2378-4FDB-BFB6-7345A15512D3}=-g -Wall -DMPLAB_PIC24_PORT -mlarge-code -fomit-frame-pointer -fno-schedule-insns -fno-schedule-insns2
|
||||
TS{7DAC9A1D-4C45-45D6-B25A-D117C74E8F5A}=--defsym=__ICD2RAM=1 -Map="$(TARGETBASE).map" -o"$(TARGETBASE).$(TARGETSUFFIX)"
|
||||
TS{509E5861-1E2A-483B-8B6B-CA8DB7F2DD78}=
|
||||
@ -0,0 +1,3 @@
|
||||
[Header]
|
||||
MagicCookie={0b13fe8c-dfe0-40eb-8900-6712719559a7}
|
||||
Version=1.0
|
||||
@ -0,0 +1,421 @@
|
||||
/*
|
||||
FreeRTOS.org V4.1.0 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
FreeRTOS.org is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
FreeRTOS.org is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with FreeRTOS.org; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
|
||||
A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes FreeRTOS.org, without being obliged to provide
|
||||
the source code for any proprietary components. See the licensing section
|
||||
of http://www.FreeRTOS.org for full details of how and when the exception
|
||||
can be applied.
|
||||
|
||||
***************************************************************************
|
||||
See http://www.FreeRTOS.org for documentation, latest information, license
|
||||
and contact details. Please ensure to read the configuration and relevant
|
||||
port sections of the online documentation.
|
||||
***************************************************************************
|
||||
*/
|
||||
|
||||
/*
|
||||
* Creates all the demo application tasks, then starts the scheduler. The WEB
|
||||
* documentation provides more details of the standard demo application tasks.
|
||||
* In addition to the standard demo tasks, the following tasks are defined
|
||||
* within this file:
|
||||
*
|
||||
* "Register test" tasks - These tasks first set all the general purpose
|
||||
* registers to a known value (with each register containing a different value)
|
||||
* then test each general purpose register to ensure it still contains the
|
||||
* set value. There are two register test tasks, with different values being
|
||||
* used by each. The register test tasks will be preempted frequently due to
|
||||
* their low priority. Setting then testing the value of each register in this
|
||||
* manner ensures the context of the tasks is being correctly saved and then
|
||||
* restored as the preemptive context switches occur. An error is flagged
|
||||
* should any register be found to contain an unexpected value. In addition
|
||||
* the register test tasks maintain a count of the number of times they cycle,
|
||||
* so an error can also be flagged should the cycle count not increment as
|
||||
* expected (indicating the the tasks are not executing at all).
|
||||
*
|
||||
* "Check" task - This only executes every three seconds but has the highest
|
||||
* priority so is guaranteed to get processor time. Its main function is to
|
||||
* check that all the other tasks are still operational. Each task maintains a
|
||||
* unique count that is incremented each time the task successfully completes
|
||||
* its function. Should any error occur within such a task the count is
|
||||
* permanently halted. The check task inspects the count of each task to
|
||||
* ensure it has changed since the last time the check task executed. If all
|
||||
* the count variables have changed all the tasks are still executing error
|
||||
* free, and the check task toggles the onboard LED. Should any task contain
|
||||
* an error at any time check task cycle frequency is increased to 500ms,
|
||||
* causing the LED toggle rate to increase from 3 seconds to 500ms and in so
|
||||
* doing providing visual feedback that an error has occurred.
|
||||
*
|
||||
*/
|
||||
|
||||
/* Scheduler includes. */
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
#include "croutine.h"
|
||||
|
||||
/* Demo application includes. */
|
||||
#include "BlockQ.h"
|
||||
#include "crflash.h"
|
||||
#include "blocktim.h"
|
||||
#include "integer.h"
|
||||
#include "comtest2.h"
|
||||
#include "partest.h"
|
||||
|
||||
/* Demo task priorities. */
|
||||
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )
|
||||
#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
|
||||
#define mainCOM_TEST_PRIORITY ( 2 )
|
||||
|
||||
/* Delay between check task cycles when an error has/has not been detected. */
|
||||
#define mainNO_ERROR_DELAY ( ( portTickType ) 3000 / portTICK_RATE_MS )
|
||||
#define mainERROR_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS )
|
||||
|
||||
/* The number of flash co-routines to create. */
|
||||
#define mainNUM_FLASH_COROUTINES ( 3 )
|
||||
|
||||
/* Baud rate used by the comtest tasks. */
|
||||
#define mainCOM_TEST_BAUD_RATE ( 19200 )
|
||||
|
||||
/* The LED used by the comtest tasks. mainCOM_TEST_LED + 1 is also used.
|
||||
See the comtest.c file for more information. */
|
||||
#define mainCOM_TEST_LED ( 4 )
|
||||
|
||||
/* The LED used by the check task. */
|
||||
#define mainCHECK_LED ( 7 )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* The register test tasks as described at the top of this file.
|
||||
*/
|
||||
void xRegisterTest1( void *pvParameters );
|
||||
void xRegisterTest2( void *pvParameters );
|
||||
|
||||
/*
|
||||
* The check task as described at the top of this file.
|
||||
*/
|
||||
static void vCheckTask( void *pvParameters );
|
||||
|
||||
/*
|
||||
* Setup the processor ready for the demo.
|
||||
*/
|
||||
static void prvSetupHardware( void );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Variables used to detect errors within the register test tasks. */
|
||||
static volatile unsigned portSHORT usTest1CycleCounter = 0, usTest2CycleCounter = 0;
|
||||
static unsigned portSHORT usPreviousTest1Count = 0, usPreviousTest2Count = 0;
|
||||
|
||||
/* Set to pdTRUE should an error be detected in any of the standard demo tasks
|
||||
or tasks defined within this file. */
|
||||
static unsigned portSHORT usErrorDetected = pdFALSE;
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* Create the demo tasks then start the scheduler.
|
||||
*/
|
||||
int main( void )
|
||||
{
|
||||
/* Configure any hardware required for this demo. */
|
||||
prvSetupHardware();
|
||||
|
||||
/* Create the standard demo tasks. */
|
||||
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
|
||||
vStartIntegerMathTasks( tskIDLE_PRIORITY );
|
||||
vStartFlashCoRoutines( mainNUM_FLASH_COROUTINES );
|
||||
vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );
|
||||
vCreateBlockTimeTasks();
|
||||
|
||||
/* Create the test tasks defined within this file. */
|
||||
xTaskCreate( xRegisterTest1, "Reg1", configMINIMAL_STACK_SIZE, ( void * ) &usTest1CycleCounter, tskIDLE_PRIORITY, NULL );
|
||||
xTaskCreate( xRegisterTest2, "Reg2", configMINIMAL_STACK_SIZE, ( void * ) &usTest2CycleCounter, tskIDLE_PRIORITY, NULL );
|
||||
xTaskCreate( vCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
|
||||
|
||||
/* Finally start the scheduler. */
|
||||
vTaskStartScheduler();
|
||||
|
||||
/* Will only reach here if there is insufficient heap available to start
|
||||
the scheduler. */
|
||||
return 0;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvSetupHardware( void )
|
||||
{
|
||||
vParTestInitialise();
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void vCheckTask( void *pvParameters )
|
||||
{
|
||||
portTickType xLastExecutionTime;
|
||||
|
||||
/* Start with the no error delay. The long delay will cause the LED to flash
|
||||
slowly. */
|
||||
portTickType xDelay = mainNO_ERROR_DELAY;
|
||||
|
||||
/* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()
|
||||
works correctly. */
|
||||
xLastExecutionTime = xTaskGetTickCount();
|
||||
|
||||
for( ;; )
|
||||
{
|
||||
/* Wait until it is time for the next cycle. */
|
||||
vTaskDelayUntil( &xLastExecutionTime, xDelay );
|
||||
|
||||
/* Has an error been found in any of the standard demo tasks? */
|
||||
|
||||
if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
|
||||
{
|
||||
usErrorDetected = pdTRUE;
|
||||
}
|
||||
|
||||
if( xAreComTestTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
usErrorDetected = pdTRUE;
|
||||
}
|
||||
|
||||
if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
usErrorDetected = pdTRUE;
|
||||
}
|
||||
|
||||
if( xAreBlockingQueuesStillRunning() != pdTRUE )
|
||||
{
|
||||
usErrorDetected = pdTRUE;
|
||||
}
|
||||
|
||||
|
||||
/* Are the register test tasks still cycling? */
|
||||
|
||||
if( usTest1CycleCounter == usPreviousTest1Count )
|
||||
{
|
||||
usErrorDetected = pdTRUE;
|
||||
}
|
||||
|
||||
if( usTest2CycleCounter == usPreviousTest2Count )
|
||||
{
|
||||
usErrorDetected = pdTRUE;
|
||||
}
|
||||
|
||||
usPreviousTest2Count = usTest2CycleCounter;
|
||||
usPreviousTest1Count = usTest1CycleCounter;
|
||||
|
||||
|
||||
/* If an error has been detected in any task then the delay will be
|
||||
reduced to increase the cycle rate of this task. This has the effect
|
||||
of causing the LED to flash much faster giving a visual indication of
|
||||
the error condition. */
|
||||
if( usErrorDetected != pdFALSE )
|
||||
{
|
||||
xDelay = mainERROR_DELAY;
|
||||
}
|
||||
|
||||
/* Finally, toggle the LED before returning to delay to wait for the
|
||||
next cycle. */
|
||||
vParTestToggleLED( mainCHECK_LED );
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void xRegisterTest1( void *pvParameters )
|
||||
{
|
||||
/* This static so as not to use the frame pointer. They are volatile
|
||||
also to avoid it being stored in a register that we clobber during the test. */
|
||||
static unsigned portSHORT * volatile pusParameter;
|
||||
|
||||
/* The variable incremented by this task is passed in as the parameter
|
||||
even though it is defined within this file. This is just to test the
|
||||
parameter passing mechanism. */
|
||||
pusParameter = pvParameters;
|
||||
|
||||
for( ;; )
|
||||
{
|
||||
/* Increment the variable to show this task is still cycling. */
|
||||
( *pusParameter )++;
|
||||
|
||||
/* Set the w registers to known values, then check that each register
|
||||
contains the expected value. See the explanation at the top of this
|
||||
file for more information. */
|
||||
asm volatile( "mov.w #0x0101, W0 \n" \
|
||||
"mov.w #0x0102, W1 \n" \
|
||||
"mov.w #0x0103, W2 \n" \
|
||||
"mov.w #0x0104, W3 \n" \
|
||||
"mov.w #0x0105, W4 \n" \
|
||||
"mov.w #0x0106, W5 \n" \
|
||||
"mov.w #0x0107, W6 \n" \
|
||||
"mov.w #0x0108, W7 \n" \
|
||||
"mov.w #0x0109, W8 \n" \
|
||||
"mov.w #0x010a, W9 \n" \
|
||||
"mov.w #0x010b, W10 \n" \
|
||||
"mov.w #0x010c, W11 \n" \
|
||||
"mov.w #0x010d, W12 \n" \
|
||||
"mov.w #0x010e, W13 \n" \
|
||||
"mov.w #0x010f, W14 \n" \
|
||||
"sub #0x0101, W0 \n" \
|
||||
"cp0.w W0 \n" \
|
||||
"bra NZ, ERROR_TEST1 \n" \
|
||||
"sub #0x0102, W1 \n" \
|
||||
"cp0.w W1 \n" \
|
||||
"bra NZ, ERROR_TEST1 \n" \
|
||||
"sub #0x0103, W2 \n" \
|
||||
"cp0.w W2 \n" \
|
||||
"bra NZ, ERROR_TEST1 \n" \
|
||||
"sub #0x0104, W3 \n" \
|
||||
"cp0.w W3 \n" \
|
||||
"bra NZ, ERROR_TEST1 \n" \
|
||||
"sub #0x0105, W4 \n" \
|
||||
"cp0.w W4 \n" \
|
||||
"bra NZ, ERROR_TEST1 \n" \
|
||||
"sub #0x0106, W5 \n" \
|
||||
"cp0.w W5 \n" \
|
||||
"bra NZ, ERROR_TEST1 \n" \
|
||||
"sub #0x0107, W6 \n" \
|
||||
"cp0.w W6 \n" \
|
||||
"bra NZ, ERROR_TEST1 \n" \
|
||||
"sub #0x0108, W7 \n" \
|
||||
"cp0.w W7 \n" \
|
||||
"bra NZ, ERROR_TEST1 \n" \
|
||||
"sub #0x0109, W8 \n" \
|
||||
"cp0.w W8 \n" \
|
||||
"bra NZ, ERROR_TEST1 \n" \
|
||||
"sub #0x010a, W9 \n" \
|
||||
"cp0.w W9 \n" \
|
||||
"bra NZ, ERROR_TEST1 \n" \
|
||||
"sub #0x010b, W10 \n" \
|
||||
"cp0.w W10 \n" \
|
||||
"bra NZ, ERROR_TEST1 \n" \
|
||||
"sub #0x010c, W11 \n" \
|
||||
"cp0.w W11 \n" \
|
||||
"bra NZ, ERROR_TEST1 \n" \
|
||||
"sub #0x010d, W12 \n" \
|
||||
"cp0.w W12 \n" \
|
||||
"bra NZ, ERROR_TEST1 \n" \
|
||||
"sub #0x010e, W13 \n" \
|
||||
"cp0.w W13 \n" \
|
||||
"bra NZ, ERROR_TEST1 \n" \
|
||||
"sub #0x010f, W14 \n" \
|
||||
"cp0.w W14 \n" \
|
||||
"bra NZ, ERROR_TEST1 \n" \
|
||||
"bra NO_ERROR1 \n" \
|
||||
"ERROR_TEST1: \n" \
|
||||
"mov.w #1, W0 \n" \
|
||||
"mov.w W0, _usErrorDetected\n" \
|
||||
"NO_ERROR1: \n" );
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void xRegisterTest2( void *pvParameters )
|
||||
{
|
||||
/* This static so as not to use the frame pointer. They are volatile
|
||||
also to avoid it being stored in a register that we clobber during the test. */
|
||||
static unsigned portSHORT * volatile pusParameter;
|
||||
|
||||
/* The variable incremented by this task is passed in as the parameter
|
||||
even though it is defined within this file. This is just to test the
|
||||
parameter passing mechanism. */
|
||||
pusParameter = pvParameters;
|
||||
|
||||
for( ;; )
|
||||
{
|
||||
/* Increment the variable to show this task is still cycling. */
|
||||
( *pusParameter )++;
|
||||
|
||||
/* Set the w registers to known values, then check that each register
|
||||
contains the expected value. See the explanation at the top of this
|
||||
file for more information. */
|
||||
asm volatile( "mov.w #0x0100, W0 \n" \
|
||||
"mov.w #0x0101, W1 \n" \
|
||||
"mov.w #0x0102, W2 \n" \
|
||||
"mov.w #0x0103, W3 \n" \
|
||||
"mov.w #0x0104, W4 \n" \
|
||||
"mov.w #0x0105, W5 \n" \
|
||||
"mov.w #0x0106, W6 \n" \
|
||||
"mov.w #0x0107, W7 \n" \
|
||||
"mov.w #0x0108, W8 \n" \
|
||||
"mov.w #0x0109, W9 \n" \
|
||||
"mov.w #0x010a, W10 \n" \
|
||||
"mov.w #0x010b, W11 \n" \
|
||||
"mov.w #0x010c, W12 \n" \
|
||||
"mov.w #0x010d, W13 \n" \
|
||||
"mov.w #0x010e, W14 \n" \
|
||||
"sub #0x0100, W0 \n" \
|
||||
"cp0.w W0 \n" \
|
||||
"bra NZ, ERROR_TEST2 \n" \
|
||||
"sub #0x0101, W1 \n" \
|
||||
"cp0.w W1 \n" \
|
||||
"bra NZ, ERROR_TEST2 \n" \
|
||||
"sub #0x0102, W2 \n" \
|
||||
"cp0.w W2 \n" \
|
||||
"bra NZ, ERROR_TEST2 \n" \
|
||||
"sub #0x0103, W3 \n" \
|
||||
"cp0.w W3 \n" \
|
||||
"bra NZ, ERROR_TEST2 \n" \
|
||||
"sub #0x0104, W4 \n" \
|
||||
"cp0.w W4 \n" \
|
||||
"bra NZ, ERROR_TEST2 \n" \
|
||||
"sub #0x0105, W5 \n" \
|
||||
"cp0.w W5 \n" \
|
||||
"bra NZ, ERROR_TEST2 \n" \
|
||||
"sub #0x0106, W6 \n" \
|
||||
"cp0.w W6 \n" \
|
||||
"bra NZ, ERROR_TEST2 \n" \
|
||||
"sub #0x0107, W7 \n" \
|
||||
"cp0.w W7 \n" \
|
||||
"bra NZ, ERROR_TEST2 \n" \
|
||||
"sub #0x0108, W8 \n" \
|
||||
"cp0.w W8 \n" \
|
||||
"bra NZ, ERROR_TEST2 \n" \
|
||||
"sub #0x0109, W9 \n" \
|
||||
"cp0.w W9 \n" \
|
||||
"bra NZ, ERROR_TEST2 \n" \
|
||||
"sub #0x010a, W10 \n" \
|
||||
"cp0.w W10 \n" \
|
||||
"bra NZ, ERROR_TEST2 \n" \
|
||||
"sub #0x010b, W11 \n" \
|
||||
"cp0.w W11 \n" \
|
||||
"bra NZ, ERROR_TEST2 \n" \
|
||||
"sub #0x010c, W12 \n" \
|
||||
"cp0.w W12 \n" \
|
||||
"bra NZ, ERROR_TEST2 \n" \
|
||||
"sub #0x010d, W13 \n" \
|
||||
"cp0.w W13 \n" \
|
||||
"bra NZ, ERROR_TEST2 \n" \
|
||||
"sub #0x010e, W14 \n" \
|
||||
"cp0.w W14 \n" \
|
||||
"bra NZ, ERROR_TEST2 \n" \
|
||||
"bra NO_ERROR2 \n" \
|
||||
"ERROR_TEST2: \n" \
|
||||
"mov.w #1, W0 \n" \
|
||||
"mov.w W0, _usErrorDetected\n" \
|
||||
"NO_ERROR2: \n" );
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vApplicationIdleHook( void )
|
||||
{
|
||||
/* Schedule the co-routines from within the idle task hook. */
|
||||
vCoRoutineSchedule();
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,235 @@
|
||||
/*
|
||||
FreeRTOS.org V4.1.0 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
FreeRTOS.org is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
FreeRTOS.org is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with FreeRTOS.org; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
|
||||
A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes FreeRTOS.org, without being obliged to provide
|
||||
the source code for any proprietary components. See the licensing section
|
||||
of http://www.FreeRTOS.org for full details of how and when the exception
|
||||
can be applied.
|
||||
|
||||
***************************************************************************
|
||||
See http://www.FreeRTOS.org for documentation, latest information, license
|
||||
and contact details. Please ensure to read the configuration and relevant
|
||||
port sections of the online documentation.
|
||||
***************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER.
|
||||
|
||||
NOTE: This driver is primarily to test the scheduler functionality. It does
|
||||
not effectively use the buffers or DMA and is therefore not intended to be
|
||||
an example of an efficient driver. */
|
||||
|
||||
/* Standard include file. */
|
||||
#include <stdlib.h>
|
||||
|
||||
/* Scheduler include files. */
|
||||
#include "FreeRTOS.h"
|
||||
#include "queue.h"
|
||||
#include "task.h"
|
||||
|
||||
/* Demo app include files. */
|
||||
#include "serial.h"
|
||||
|
||||
/* Hardware setup. */
|
||||
#define serOUTPUT 0
|
||||
#define serINPUT 1
|
||||
#define serLOW_SPEED 0
|
||||
#define serONE_STOP_BIT 0
|
||||
#define serEIGHT_DATA_BITS_NO_PARITY 0
|
||||
#define serNORMAL_IDLE_STATE 0
|
||||
#define serAUTO_BAUD_OFF 0
|
||||
#define serLOOPBACK_OFF 0
|
||||
#define serWAKE_UP_DISABLE 0
|
||||
#define serNO_HARDWARE_FLOW_CONTROL 0
|
||||
#define serSTANDARD_IO 0
|
||||
#define serNO_IRDA 0
|
||||
#define serCONTINUE_IN_IDLE_MODE 0
|
||||
#define serUART_ENABLED 1
|
||||
#define serINTERRUPT_ON_SINGLE_CHAR 0
|
||||
#define serTX_ENABLE 1
|
||||
#define serINTERRUPT_ENABLE 1
|
||||
#define serINTERRUPT_DISABLE 0
|
||||
#define serCLEAR_FLAG 0
|
||||
#define serSET_FLAG 1
|
||||
|
||||
|
||||
/* The queues used to communicate between tasks and ISR's. */
|
||||
static xQueueHandle xRxedChars;
|
||||
static xQueueHandle xCharsForTx;
|
||||
|
||||
static portBASE_TYPE xTxHasEnded;
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
|
||||
{
|
||||
portCHAR cChar;
|
||||
|
||||
/* Create the queues used by the com test task. */
|
||||
xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
|
||||
xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
|
||||
|
||||
/* Setup the UART. */
|
||||
U2MODEbits.BRGH = serLOW_SPEED;
|
||||
U2MODEbits.STSEL = serONE_STOP_BIT;
|
||||
U2MODEbits.PDSEL = serEIGHT_DATA_BITS_NO_PARITY;
|
||||
U2MODEbits.RXINV = serNORMAL_IDLE_STATE;
|
||||
U2MODEbits.ABAUD = serAUTO_BAUD_OFF;
|
||||
U2MODEbits.LPBACK = serLOOPBACK_OFF;
|
||||
U2MODEbits.WAKE = serWAKE_UP_DISABLE;
|
||||
U2MODEbits.UEN = serNO_HARDWARE_FLOW_CONTROL;
|
||||
U2MODEbits.IREN = serNO_IRDA;
|
||||
U2MODEbits.USIDL = serCONTINUE_IN_IDLE_MODE;
|
||||
U2MODEbits.UARTEN = serUART_ENABLED;
|
||||
|
||||
U2BRG = (unsigned portSHORT)(( (float)configCPU_CLOCK_HZ / ( (float)16 * (float)ulWantedBaud ) ) - (float)0.5);
|
||||
|
||||
U2STAbits.URXISEL = serINTERRUPT_ON_SINGLE_CHAR;
|
||||
U2STAbits.UTXEN = serTX_ENABLE;
|
||||
U2STAbits.UTXINV = serNORMAL_IDLE_STATE;
|
||||
U2STAbits.UTXISEL0 = serINTERRUPT_ON_SINGLE_CHAR;
|
||||
U2STAbits.UTXISEL1 = serINTERRUPT_ON_SINGLE_CHAR;
|
||||
|
||||
/* It is assumed that this function is called prior to the scheduler being
|
||||
started. Therefore interrupts must not be allowed to occur yet as they
|
||||
may attempt to perform a context switch. */
|
||||
portDISABLE_INTERRUPTS();
|
||||
|
||||
IFS1bits.U2RXIF = serCLEAR_FLAG;
|
||||
IFS1bits.U2TXIF = serCLEAR_FLAG;
|
||||
IPC7bits.U2RXIP = portKERNEL_INTERRUPT_PRIORITY;
|
||||
IPC7bits.U2TXIP = portKERNEL_INTERRUPT_PRIORITY;
|
||||
IEC1bits.U2TXIE = serINTERRUPT_ENABLE;
|
||||
IEC1bits.U2RXIE = serINTERRUPT_ENABLE;
|
||||
|
||||
/* Clear the Rx buffer. */
|
||||
while( U2STAbits.URXDA == serSET_FLAG )
|
||||
{
|
||||
cChar = U2RXREG;
|
||||
}
|
||||
|
||||
xTxHasEnded = pdTRUE;
|
||||
|
||||
return NULL;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )
|
||||
{
|
||||
/* Only one port is supported. */
|
||||
( void ) pxPort;
|
||||
|
||||
/* Get the next character from the buffer. Return false if no characters
|
||||
are available or arrive before xBlockTime expires. */
|
||||
if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
|
||||
{
|
||||
return pdTRUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
return pdFALSE;
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )
|
||||
{
|
||||
/* Only one port is supported. */
|
||||
( void ) pxPort;
|
||||
|
||||
/* Return false if after the block time there is no room on the Tx queue. */
|
||||
if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
|
||||
{
|
||||
return pdFAIL;
|
||||
}
|
||||
|
||||
/* A critical section should not be required as xTxHasEnded will not be
|
||||
written to by the ISR if it is already 0 (is this correct?). */
|
||||
if( xTxHasEnded )
|
||||
{
|
||||
xTxHasEnded = pdFALSE;
|
||||
IFS1bits.U2TXIF = serSET_FLAG;
|
||||
}
|
||||
|
||||
return pdPASS;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vSerialClose( xComPortHandle xPort )
|
||||
{
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
volatile short s = 0;
|
||||
char c[80] = {0};
|
||||
|
||||
void __attribute__((__interrupt__)) _U2RXInterrupt( void )
|
||||
{
|
||||
portCHAR cChar;
|
||||
portBASE_TYPE xYieldRequired = pdFALSE;
|
||||
|
||||
/* Get the character and post it on the queue of Rxed characters.
|
||||
If the post causes a task to wake force a context switch as the woken task
|
||||
may have a higher priority than the task we have interrupted. */
|
||||
IFS1bits.U2RXIF = serCLEAR_FLAG;
|
||||
while( U2STAbits.URXDA )
|
||||
{
|
||||
cChar = U2RXREG;
|
||||
xYieldRequired = xQueueSendFromISR( xRxedChars, &cChar, xYieldRequired );
|
||||
}
|
||||
|
||||
if( xYieldRequired != pdFALSE )
|
||||
{
|
||||
taskYIELD();
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void __attribute__((__interrupt__)) _U2TXInterrupt( void )
|
||||
{
|
||||
signed portCHAR cChar;
|
||||
portBASE_TYPE xTaskWoken = pdFALSE;
|
||||
|
||||
/* If the transmit buffer is full we cannot get the next character.
|
||||
Another interrupt will occur the next time there is space so this does
|
||||
not matter. */
|
||||
IFS1bits.U2TXIF = serCLEAR_FLAG;
|
||||
while( !( U2STAbits.UTXBF ) )
|
||||
{
|
||||
if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWoken ) == pdTRUE )
|
||||
{
|
||||
/* Send the next character queued for Tx. */
|
||||
U2TXREG = cChar;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Queue empty, nothing to send. */
|
||||
xTxHasEnded = pdTRUE;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if( xTaskWoken != pdFALSE )
|
||||
{
|
||||
taskYIELD();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -0,0 +1,77 @@
|
||||
/*
|
||||
FreeRTOS.org V4.1.0 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
FreeRTOS.org is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
FreeRTOS.org is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with FreeRTOS.org; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
|
||||
A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes FreeRTOS.org, without being obliged to provide
|
||||
the source code for any proprietary components. See the licensing section
|
||||
of http://www.FreeRTOS.org for full details of how and when the exception
|
||||
can be applied.
|
||||
|
||||
***************************************************************************
|
||||
See http://www.FreeRTOS.org for documentation, latest information, license
|
||||
and contact details. Please ensure to read the configuration and relevant
|
||||
port sections of the online documentation.
|
||||
***************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef FREERTOS_CONFIG_H
|
||||
#define FREERTOS_CONFIG_H
|
||||
|
||||
#include <p33FJ256GP710.h>
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Application specific definitions.
|
||||
*
|
||||
* These definitions should be adjusted for your particular hardware and
|
||||
* application requirements.
|
||||
*
|
||||
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
|
||||
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
|
||||
*----------------------------------------------------------*/
|
||||
|
||||
#define configUSE_PREEMPTION 1
|
||||
#define configUSE_IDLE_HOOK 1
|
||||
#define configUSE_TICK_HOOK 0
|
||||
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
|
||||
#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 25000000 ) /* Fosc / 2 */
|
||||
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 )
|
||||
#define configMINIMAL_STACK_SIZE ( 105 )
|
||||
#define configTOTAL_HEAP_SIZE ( ( size_t ) 5120 )
|
||||
#define configMAX_TASK_NAME_LEN ( 4 )
|
||||
#define configUSE_TRACE_FACILITY 0
|
||||
#define configUSE_16_BIT_TICKS 1
|
||||
#define configIDLE_SHOULD_YIELD 1
|
||||
|
||||
/* Co-routine definitions. */
|
||||
#define configUSE_CO_ROUTINES 1
|
||||
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
|
||||
|
||||
/* Set the following definitions to 1 to include the API function, or zero
|
||||
to exclude the API function. */
|
||||
|
||||
#define INCLUDE_vTaskPrioritySet 1
|
||||
#define INCLUDE_uxTaskPriorityGet 0
|
||||
#define INCLUDE_vTaskDelete 0
|
||||
#define INCLUDE_vTaskCleanUpResources 0
|
||||
#define INCLUDE_vTaskSuspend 1
|
||||
#define INCLUDE_vTaskDelayUntil 1
|
||||
#define INCLUDE_vTaskDelay 1
|
||||
|
||||
|
||||
#endif /* FREERTOS_CONFIG_H */
|
||||
@ -0,0 +1,113 @@
|
||||
/*
|
||||
FreeRTOS.org V4.1.0 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
FreeRTOS.org is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
FreeRTOS.org is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with FreeRTOS.org; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
|
||||
A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes FreeRTOS.org, without being obliged to provide
|
||||
the source code for any proprietary components. See the licensing section
|
||||
of http://www.FreeRTOS.org for full details of how and when the exception
|
||||
can be applied.
|
||||
|
||||
***************************************************************************
|
||||
See http://www.FreeRTOS.org for documentation, latest information, license
|
||||
and contact details. Please ensure to read the configuration and relevant
|
||||
port sections of the online documentation.
|
||||
***************************************************************************
|
||||
*/
|
||||
|
||||
/* Scheduler includes. */
|
||||
#include "FreeRTOS.h"
|
||||
|
||||
/* Demo app includes. */
|
||||
#include "partest.h"
|
||||
|
||||
#define ptOUTPUT 0
|
||||
#define ptALL_OFF 0
|
||||
|
||||
unsigned portBASE_TYPE uxOutput;
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Simple parallel port IO routines.
|
||||
*-----------------------------------------------------------*/
|
||||
|
||||
void vParTestInitialise( void )
|
||||
{
|
||||
/* The explorer 16 board has LED's on port A. All bits are set as output
|
||||
so PORTA is read-modified-written directly. Two pins have change
|
||||
notification pullups that need disabling. */
|
||||
CNPU2bits.CN22PUE = 0;
|
||||
CNPU2bits.CN23PUE = 0;
|
||||
TRISA = ptOUTPUT;
|
||||
PORTA = ptALL_OFF;
|
||||
uxOutput = ptALL_OFF;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
|
||||
{
|
||||
unsigned portBASE_TYPE uxLEDBit;
|
||||
|
||||
/* Which port A bit is being modified? */
|
||||
uxLEDBit = 1 << uxLED;
|
||||
|
||||
if( xValue )
|
||||
{
|
||||
/* Turn the LED on. */
|
||||
portENTER_CRITICAL();
|
||||
{
|
||||
uxOutput |= uxLEDBit;
|
||||
PORTA = uxOutput;
|
||||
}
|
||||
portEXIT_CRITICAL();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Turn the LED off. */
|
||||
portENTER_CRITICAL();
|
||||
{
|
||||
uxOutput &= ~uxLEDBit;
|
||||
PORTA = uxOutput;
|
||||
}
|
||||
portEXIT_CRITICAL();
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
|
||||
{
|
||||
unsigned portBASE_TYPE uxLEDBit;
|
||||
|
||||
uxLEDBit = 1 << uxLED;
|
||||
portENTER_CRITICAL();
|
||||
{
|
||||
/* If the LED is already on - turn it off. If the LED is already
|
||||
off, turn it on. */
|
||||
if( uxOutput & uxLEDBit )
|
||||
{
|
||||
uxOutput &= ~uxLEDBit;
|
||||
PORTA = uxOutput;
|
||||
}
|
||||
else
|
||||
{
|
||||
uxOutput |= uxLEDBit;
|
||||
PORTA = uxOutput;
|
||||
}
|
||||
}
|
||||
portEXIT_CRITICAL();
|
||||
}
|
||||
|
||||
@ -0,0 +1,3 @@
|
||||
[Header]
|
||||
MagicCookie={0b13fe8c-dfe0-40eb-8900-6712719559a7}
|
||||
Version=1.0
|
||||
Binary file not shown.
@ -0,0 +1,67 @@
|
||||
[HEADER]
|
||||
magic_cookie={66E99B07-E706-4689-9E80-9B2582898A13}
|
||||
file_version=1.0
|
||||
[PATH_INFO]
|
||||
dir_src=
|
||||
dir_bin=
|
||||
dir_tmp=
|
||||
dir_sin=
|
||||
dir_inc=.;C:\E\Dev\FreeRTOS\Demo\Common\include;C:\E\Dev\FreeRTOS\Demo\dsPIC_MPLAB;C:\E\Dev\FreeRTOS\source\include
|
||||
dir_lib=
|
||||
dir_lkr=
|
||||
[CAT_FILTERS]
|
||||
filter_src=*.s;*.c
|
||||
filter_inc=*.h;*.inc
|
||||
filter_obj=*.o
|
||||
filter_lib=*.a
|
||||
filter_lkr=*.gld
|
||||
[OTHER_FILES]
|
||||
file_000=no
|
||||
file_001=no
|
||||
file_002=no
|
||||
file_003=no
|
||||
file_004=no
|
||||
file_005=no
|
||||
file_006=no
|
||||
file_007=no
|
||||
file_008=no
|
||||
file_009=no
|
||||
file_010=no
|
||||
file_011=no
|
||||
file_012=no
|
||||
file_013=no
|
||||
file_014=no
|
||||
file_015=no
|
||||
file_016=no
|
||||
file_017=no
|
||||
file_018=no
|
||||
file_019=no
|
||||
[FILE_INFO]
|
||||
file_000=main.c
|
||||
file_001=..\..\source\list.c
|
||||
file_002=..\..\source\queue.c
|
||||
file_003=..\..\source\tasks.c
|
||||
file_004=..\..\source\portable\MPLAB\PIC24_dsPIC\port.c
|
||||
file_005=..\..\source\portable\MemMang\heap_1.c
|
||||
file_006=..\Common\Minimal\BlockQ.c
|
||||
file_007=..\..\source\croutine.c
|
||||
file_008=..\Common\Minimal\crflash.c
|
||||
file_009=ParTest\ParTest.c
|
||||
file_010=..\Common\Minimal\blocktim.c
|
||||
file_011=..\Common\Minimal\integer.c
|
||||
file_012=..\Common\Minimal\comtest.c
|
||||
file_013=serial\serial.c
|
||||
file_014=..\..\source\include\semphr.h
|
||||
file_015=..\..\source\include\task.h
|
||||
file_016=..\..\source\include\croutine.h
|
||||
file_017=..\..\source\include\queue.h
|
||||
file_018=FreeRTOSConfig.h
|
||||
file_019=p33FJ256GP710.gld
|
||||
[SUITE_INFO]
|
||||
suite_guid={479DDE59-4D56-455E-855E-FFF59A3DB57E}
|
||||
suite_state=
|
||||
[TOOL_SETTINGS]
|
||||
TS{7D9C6ECE-785D-44CB-BA22-17BF2E119622}=-g
|
||||
TS{25AC22BD-2378-4FDB-BFB6-7345A15512D3}=-g -Wall -DMPLAB_DSPIC_PORT -O2 -fomit-frame-pointer -fno-schedule-insns -fno-schedule-insns2
|
||||
TS{7DAC9A1D-4C45-45D6-B25A-D117C74E8F5A}=--defsym=__ICD2RAM=1 -Map="$(TARGETBASE).map" -o"$(TARGETBASE).$(TARGETSUFFIX)"
|
||||
TS{509E5861-1E2A-483B-8B6B-CA8DB7F2DD78}=
|
||||
@ -0,0 +1,3 @@
|
||||
[Header]
|
||||
MagicCookie={0b13fe8c-dfe0-40eb-8900-6712719559a7}
|
||||
Version=1.0
|
||||
@ -0,0 +1,420 @@
|
||||
/*
|
||||
FreeRTOS.org V4.1.0 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
FreeRTOS.org is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
FreeRTOS.org is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with FreeRTOS.org; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
|
||||
A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes FreeRTOS.org, without being obliged to provide
|
||||
the source code for any proprietary components. See the licensing section
|
||||
of http://www.FreeRTOS.org for full details of how and when the exception
|
||||
can be applied.
|
||||
|
||||
***************************************************************************
|
||||
See http://www.FreeRTOS.org for documentation, latest information, license
|
||||
and contact details. Please ensure to read the configuration and relevant
|
||||
port sections of the online documentation.
|
||||
***************************************************************************
|
||||
*/
|
||||
|
||||
/*
|
||||
* Creates all the demo application tasks, then starts the scheduler. The WEB
|
||||
* documentation provides more details of the standard demo application tasks.
|
||||
* In addition to the standard demo tasks, the following tasks are defined
|
||||
* within this file:
|
||||
*
|
||||
* "Register test" tasks - These tasks first set all the general purpose
|
||||
* registers to a known value (with each register containing a different value)
|
||||
* then test each general purpose register to ensure it still contains the
|
||||
* set value. There are two register test tasks, with different values being
|
||||
* used by each. The register test tasks will be preempted frequently due to
|
||||
* their low priority. Setting then testing the value of each register in this
|
||||
* manner ensures the context of the tasks is being correctly saved and then
|
||||
* restored as the preemptive context switches occur. An error is flagged
|
||||
* should any register be found to contain an unexpected value. In addition
|
||||
* the register test tasks maintain a count of the number of times they cycle,
|
||||
* so an error can also be flagged should the cycle count not increment as
|
||||
* expected (indicating the the tasks are not executing at all).
|
||||
*
|
||||
* "Check" task - This only executes every three seconds but has the highest
|
||||
* priority so is guaranteed to get processor time. Its main function is to
|
||||
* check that all the other tasks are still operational. Each task maintains a
|
||||
* unique count that is incremented each time the task successfully completes
|
||||
* its function. Should any error occur within such a task the count is
|
||||
* permanently halted. The check task inspects the count of each task to
|
||||
* ensure it has changed since the last time the check task executed. If all
|
||||
* the count variables have changed all the tasks are still executing error
|
||||
* free, and the check task toggles the onboard LED. Should any task contain
|
||||
* an error at any time check task cycle frequency is increased to 500ms,
|
||||
* causing the LED toggle rate to increase from 3 seconds to 500ms and in so
|
||||
* doing providing visual feedback that an error has occurred.
|
||||
*
|
||||
*/
|
||||
|
||||
/* Scheduler includes. */
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
#include "croutine.h"
|
||||
|
||||
/* Demo application includes. */
|
||||
#include "BlockQ.h"
|
||||
#include "crflash.h"
|
||||
#include "blocktim.h"
|
||||
#include "integer.h"
|
||||
#include "comtest2.h"
|
||||
#include "partest.h"
|
||||
|
||||
/* Demo task priorities. */
|
||||
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )
|
||||
#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
|
||||
#define mainCOM_TEST_PRIORITY ( 2 )
|
||||
|
||||
/* Delay between check task cycles when an error has/has not been detected. */
|
||||
#define mainNO_ERROR_DELAY ( ( portTickType ) 3000 / portTICK_RATE_MS )
|
||||
#define mainERROR_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS )
|
||||
|
||||
/* The number of flash co-routines to create. */
|
||||
#define mainNUM_FLASH_COROUTINES ( 3 )
|
||||
|
||||
/* Baud rate used by the comtest tasks. */
|
||||
#define mainCOM_TEST_BAUD_RATE ( 19200 )
|
||||
|
||||
/* The LED used by the comtest tasks. mainCOM_TEST_LED + 1 is also used.
|
||||
See the comtest.c file for more information. */
|
||||
#define mainCOM_TEST_LED ( 4 )
|
||||
|
||||
/* The LED used by the check task. */
|
||||
#define mainCHECK_LED ( 7 )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* The register test tasks as described at the top of this file.
|
||||
*/
|
||||
void xRegisterTest1( void *pvParameters );
|
||||
void xRegisterTest2( void *pvParameters );
|
||||
|
||||
/*
|
||||
* The check task as described at the top of this file.
|
||||
*/
|
||||
static void vCheckTask( void *pvParameters );
|
||||
|
||||
/*
|
||||
* Setup the processor ready for the demo.
|
||||
*/
|
||||
static void prvSetupHardware( void );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Variables used to detect errors within the register test tasks. */
|
||||
static volatile unsigned portSHORT usTest1CycleCounter = 0, usTest2CycleCounter = 0;
|
||||
static unsigned portSHORT usPreviousTest1Count = 0, usPreviousTest2Count = 0;
|
||||
|
||||
/* Set to pdTRUE should an error be detected in any of the standard demo tasks
|
||||
or tasks defined within this file. */
|
||||
static unsigned portSHORT usErrorDetected = pdFALSE;
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* Create the demo tasks then start the scheduler.
|
||||
*/
|
||||
int main( void )
|
||||
{
|
||||
/* Configure any hardware required for this demo. */
|
||||
prvSetupHardware();
|
||||
|
||||
/* Create the standard demo tasks. */
|
||||
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
|
||||
vStartIntegerMathTasks( tskIDLE_PRIORITY );
|
||||
vStartFlashCoRoutines( mainNUM_FLASH_COROUTINES );
|
||||
vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );
|
||||
vCreateBlockTimeTasks();
|
||||
|
||||
/* Create the test tasks defined within this file. */
|
||||
xTaskCreate( xRegisterTest1, "Reg1", configMINIMAL_STACK_SIZE, ( void * ) &usTest1CycleCounter, tskIDLE_PRIORITY, NULL );
|
||||
xTaskCreate( xRegisterTest2, "Reg2", configMINIMAL_STACK_SIZE, ( void * ) &usTest2CycleCounter, tskIDLE_PRIORITY, NULL );
|
||||
xTaskCreate( vCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
|
||||
|
||||
/* Finally start the scheduler. */
|
||||
vTaskStartScheduler();
|
||||
|
||||
/* Will only reach here if there is insufficient heap available to start
|
||||
the scheduler. */
|
||||
return 0;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvSetupHardware( void )
|
||||
{
|
||||
vParTestInitialise();
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void vCheckTask( void *pvParameters )
|
||||
{
|
||||
portTickType xLastExecutionTime;
|
||||
|
||||
/* Start with the no error delay. The long delay will cause the LED to flash
|
||||
slowly. */
|
||||
portTickType xDelay = mainNO_ERROR_DELAY;
|
||||
|
||||
/* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()
|
||||
works correctly. */
|
||||
xLastExecutionTime = xTaskGetTickCount();
|
||||
|
||||
for( ;; )
|
||||
{
|
||||
/* Wait until it is time for the next cycle. */
|
||||
vTaskDelayUntil( &xLastExecutionTime, xDelay );
|
||||
|
||||
/* Has an error been found in any of the standard demo tasks? */
|
||||
|
||||
if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
|
||||
{
|
||||
usErrorDetected = pdTRUE;
|
||||
}
|
||||
|
||||
if( xAreComTestTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
usErrorDetected = pdTRUE;
|
||||
}
|
||||
|
||||
if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
|
||||
{
|
||||
usErrorDetected = pdTRUE;
|
||||
}
|
||||
|
||||
if( xAreBlockingQueuesStillRunning() != pdTRUE )
|
||||
{
|
||||
usErrorDetected = pdTRUE;
|
||||
}
|
||||
|
||||
|
||||
/* Are the register test tasks still cycling? */
|
||||
|
||||
if( usTest1CycleCounter == usPreviousTest1Count )
|
||||
{
|
||||
usErrorDetected = pdTRUE;
|
||||
}
|
||||
|
||||
if( usTest2CycleCounter == usPreviousTest2Count )
|
||||
{
|
||||
usErrorDetected = pdTRUE;
|
||||
}
|
||||
|
||||
usPreviousTest2Count = usTest2CycleCounter;
|
||||
usPreviousTest1Count = usTest1CycleCounter;
|
||||
|
||||
|
||||
/* If an error has been detected in any task then the delay will be
|
||||
reduced to increase the cycle rate of this task. This has the effect
|
||||
of causing the LED to flash much faster giving a visual indication of
|
||||
the error condition. */
|
||||
if( usErrorDetected != pdFALSE )
|
||||
{
|
||||
xDelay = mainERROR_DELAY;
|
||||
}
|
||||
|
||||
/* Finally, toggle the LED before returning to delay to wait for the
|
||||
next cycle. */
|
||||
vParTestToggleLED( mainCHECK_LED );
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void xRegisterTest1( void *pvParameters )
|
||||
{
|
||||
/* This static so as not to use the frame pointer. They are volatile
|
||||
also to avoid it being stored in a register that we clobber during the test. */
|
||||
static unsigned portSHORT * volatile pusParameter;
|
||||
|
||||
/* The variable incremented by this task is passed in as the parameter
|
||||
even though it is defined within this file. This is just to test the
|
||||
parameter passing mechanism. */
|
||||
pusParameter = pvParameters;
|
||||
|
||||
for( ;; )
|
||||
{
|
||||
/* Increment the variable to show this task is still cycling. */
|
||||
( *pusParameter )++;
|
||||
|
||||
/* Set the w registers to known values, then check that each register
|
||||
contains the expected value. See the explanation at the top of this
|
||||
file for more information. */
|
||||
asm volatile( "mov.w #0x0101, W0 \n" \
|
||||
"mov.w #0x0102, W1 \n" \
|
||||
"mov.w #0x0103, W2 \n" \
|
||||
"mov.w #0x0104, W3 \n" \
|
||||
"mov.w #0x0105, W4 \n" \
|
||||
"mov.w #0x0106, W5 \n" \
|
||||
"mov.w #0x0107, W6 \n" \
|
||||
"mov.w #0x0108, W7 \n" \
|
||||
"mov.w #0x0109, W8 \n" \
|
||||
"mov.w #0x010a, W9 \n" \
|
||||
"mov.w #0x010b, W10 \n" \
|
||||
"mov.w #0x010c, W11 \n" \
|
||||
"mov.w #0x010d, W12 \n" \
|
||||
"mov.w #0x010e, W13 \n" \
|
||||
"mov.w #0x010f, W14 \n" \
|
||||
"sub #0x0101, W0 \n" \
|
||||
"cp0.w W0 \n" \
|
||||
"bra NZ, ERROR_TEST1 \n" \
|
||||
"sub #0x0102, W1 \n" \
|
||||
"cp0.w W1 \n" \
|
||||
"bra NZ, ERROR_TEST1 \n" \
|
||||
"sub #0x0103, W2 \n" \
|
||||
"cp0.w W2 \n" \
|
||||
"bra NZ, ERROR_TEST1 \n" \
|
||||
"sub #0x0104, W3 \n" \
|
||||
"cp0.w W3 \n" \
|
||||
"bra NZ, ERROR_TEST1 \n" \
|
||||
"sub #0x0105, W4 \n" \
|
||||
"cp0.w W4 \n" \
|
||||
"bra NZ, ERROR_TEST1 \n" \
|
||||
"sub #0x0106, W5 \n" \
|
||||
"cp0.w W5 \n" \
|
||||
"bra NZ, ERROR_TEST1 \n" \
|
||||
"sub #0x0107, W6 \n" \
|
||||
"cp0.w W6 \n" \
|
||||
"bra NZ, ERROR_TEST1 \n" \
|
||||
"sub #0x0108, W7 \n" \
|
||||
"cp0.w W7 \n" \
|
||||
"bra NZ, ERROR_TEST1 \n" \
|
||||
"sub #0x0109, W8 \n" \
|
||||
"cp0.w W8 \n" \
|
||||
"bra NZ, ERROR_TEST1 \n" \
|
||||
"sub #0x010a, W9 \n" \
|
||||
"cp0.w W9 \n" \
|
||||
"bra NZ, ERROR_TEST1 \n" \
|
||||
"sub #0x010b, W10 \n" \
|
||||
"cp0.w W10 \n" \
|
||||
"bra NZ, ERROR_TEST1 \n" \
|
||||
"sub #0x010c, W11 \n" \
|
||||
"cp0.w W11 \n" \
|
||||
"bra NZ, ERROR_TEST1 \n" \
|
||||
"sub #0x010d, W12 \n" \
|
||||
"cp0.w W12 \n" \
|
||||
"bra NZ, ERROR_TEST1 \n" \
|
||||
"sub #0x010e, W13 \n" \
|
||||
"cp0.w W13 \n" \
|
||||
"bra NZ, ERROR_TEST1 \n" \
|
||||
"sub #0x010f, W14 \n" \
|
||||
"cp0.w W14 \n" \
|
||||
"bra NZ, ERROR_TEST1 \n" \
|
||||
"bra NO_ERROR1 \n" \
|
||||
"ERROR_TEST1: \n" \
|
||||
"mov.w #1, W0 \n" \
|
||||
"mov.w W0, _usErrorDetected\n" \
|
||||
"NO_ERROR1: \n" );
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void xRegisterTest2( void *pvParameters )
|
||||
{
|
||||
/* This static so as not to use the frame pointer. They are volatile
|
||||
also to avoid it being stored in a register that we clobber during the test. */
|
||||
static unsigned portSHORT * volatile pusParameter;
|
||||
|
||||
/* The variable incremented by this task is passed in as the parameter
|
||||
even though it is defined within this file. This is just to test the
|
||||
parameter passing mechanism. */
|
||||
pusParameter = pvParameters;
|
||||
|
||||
for( ;; )
|
||||
{
|
||||
/* Increment the variable to show this task is still cycling. */
|
||||
( *pusParameter )++;
|
||||
|
||||
/* Set the w registers to known values, then check that each register
|
||||
contains the expected value. See the explanation at the top of this
|
||||
file for more information. */
|
||||
asm volatile( "mov.w #0x0100, W0 \n" \
|
||||
"mov.w #0x0101, W1 \n" \
|
||||
"mov.w #0x0102, W2 \n" \
|
||||
"mov.w #0x0103, W3 \n" \
|
||||
"mov.w #0x0104, W4 \n" \
|
||||
"mov.w #0x0105, W5 \n" \
|
||||
"mov.w #0x0106, W6 \n" \
|
||||
"mov.w #0x0107, W7 \n" \
|
||||
"mov.w #0x0108, W8 \n" \
|
||||
"mov.w #0x0109, W9 \n" \
|
||||
"mov.w #0x010a, W10 \n" \
|
||||
"mov.w #0x010b, W11 \n" \
|
||||
"mov.w #0x010c, W12 \n" \
|
||||
"mov.w #0x010d, W13 \n" \
|
||||
"mov.w #0x010e, W14 \n" \
|
||||
"sub #0x0100, W0 \n" \
|
||||
"cp0.w W0 \n" \
|
||||
"bra NZ, ERROR_TEST2 \n" \
|
||||
"sub #0x0101, W1 \n" \
|
||||
"cp0.w W1 \n" \
|
||||
"bra NZ, ERROR_TEST2 \n" \
|
||||
"sub #0x0102, W2 \n" \
|
||||
"cp0.w W2 \n" \
|
||||
"bra NZ, ERROR_TEST2 \n" \
|
||||
"sub #0x0103, W3 \n" \
|
||||
"cp0.w W3 \n" \
|
||||
"bra NZ, ERROR_TEST2 \n" \
|
||||
"sub #0x0104, W4 \n" \
|
||||
"cp0.w W4 \n" \
|
||||
"bra NZ, ERROR_TEST2 \n" \
|
||||
"sub #0x0105, W5 \n" \
|
||||
"cp0.w W5 \n" \
|
||||
"bra NZ, ERROR_TEST2 \n" \
|
||||
"sub #0x0106, W6 \n" \
|
||||
"cp0.w W6 \n" \
|
||||
"bra NZ, ERROR_TEST2 \n" \
|
||||
"sub #0x0107, W7 \n" \
|
||||
"cp0.w W7 \n" \
|
||||
"bra NZ, ERROR_TEST2 \n" \
|
||||
"sub #0x0108, W8 \n" \
|
||||
"cp0.w W8 \n" \
|
||||
"bra NZ, ERROR_TEST2 \n" \
|
||||
"sub #0x0109, W9 \n" \
|
||||
"cp0.w W9 \n" \
|
||||
"bra NZ, ERROR_TEST2 \n" \
|
||||
"sub #0x010a, W10 \n" \
|
||||
"cp0.w W10 \n" \
|
||||
"bra NZ, ERROR_TEST2 \n" \
|
||||
"sub #0x010b, W11 \n" \
|
||||
"cp0.w W11 \n" \
|
||||
"bra NZ, ERROR_TEST2 \n" \
|
||||
"sub #0x010c, W12 \n" \
|
||||
"cp0.w W12 \n" \
|
||||
"bra NZ, ERROR_TEST2 \n" \
|
||||
"sub #0x010d, W13 \n" \
|
||||
"cp0.w W13 \n" \
|
||||
"bra NZ, ERROR_TEST2 \n" \
|
||||
"sub #0x010e, W14 \n" \
|
||||
"cp0.w W14 \n" \
|
||||
"bra NZ, ERROR_TEST2 \n" \
|
||||
"bra NO_ERROR2 \n" \
|
||||
"ERROR_TEST2: \n" \
|
||||
"mov.w #1, W0 \n" \
|
||||
"mov.w W0, _usErrorDetected\n" \
|
||||
"NO_ERROR2: \n" );
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vApplicationIdleHook( void )
|
||||
{
|
||||
/* Schedule the co-routines from within the idle task hook. */
|
||||
vCoRoutineSchedule();
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,234 @@
|
||||
/*
|
||||
FreeRTOS.org V4.1.0 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
FreeRTOS.org is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
FreeRTOS.org is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with FreeRTOS.org; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
|
||||
A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes FreeRTOS.org, without being obliged to provide
|
||||
the source code for any proprietary components. See the licensing section
|
||||
of http://www.FreeRTOS.org for full details of how and when the exception
|
||||
can be applied.
|
||||
|
||||
***************************************************************************
|
||||
See http://www.FreeRTOS.org for documentation, latest information, license
|
||||
and contact details. Please ensure to read the configuration and relevant
|
||||
port sections of the online documentation.
|
||||
***************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER.
|
||||
|
||||
NOTE: This driver is primarily to test the scheduler functionality. It does
|
||||
not effectively use the buffers or DMA and is therefore not intended to be
|
||||
an example of an efficient driver. */
|
||||
|
||||
/* Standard include file. */
|
||||
#include <stdlib.h>
|
||||
|
||||
/* Scheduler include files. */
|
||||
#include "FreeRTOS.h"
|
||||
#include "queue.h"
|
||||
#include "task.h"
|
||||
|
||||
/* Demo app include files. */
|
||||
#include "serial.h"
|
||||
|
||||
/* Hardware setup. */
|
||||
#define serOUTPUT 0
|
||||
#define serINPUT 1
|
||||
#define serLOW_SPEED 0
|
||||
#define serONE_STOP_BIT 0
|
||||
#define serEIGHT_DATA_BITS_NO_PARITY 0
|
||||
#define serNORMAL_IDLE_STATE 0
|
||||
#define serAUTO_BAUD_OFF 0
|
||||
#define serLOOPBACK_OFF 0
|
||||
#define serWAKE_UP_DISABLE 0
|
||||
#define serNO_HARDWARE_FLOW_CONTROL 0
|
||||
#define serSTANDARD_IO 0
|
||||
#define serNO_IRDA 0
|
||||
#define serCONTINUE_IN_IDLE_MODE 0
|
||||
#define serUART_ENABLED 1
|
||||
#define serINTERRUPT_ON_SINGLE_CHAR 0
|
||||
#define serTX_ENABLE 1
|
||||
#define serINTERRUPT_ENABLE 1
|
||||
#define serINTERRUPT_DISABLE 0
|
||||
#define serCLEAR_FLAG 0
|
||||
#define serSET_FLAG 1
|
||||
|
||||
|
||||
/* The queues used to communicate between tasks and ISR's. */
|
||||
static xQueueHandle xRxedChars;
|
||||
static xQueueHandle xCharsForTx;
|
||||
|
||||
static portBASE_TYPE xTxHasEnded;
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
|
||||
{
|
||||
portCHAR cChar;
|
||||
|
||||
/* Create the queues used by the com test task. */
|
||||
xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
|
||||
xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
|
||||
|
||||
/* Setup the UART. */
|
||||
U2MODEbits.BRGH = serLOW_SPEED;
|
||||
U2MODEbits.STSEL = serONE_STOP_BIT;
|
||||
U2MODEbits.PDSEL = serEIGHT_DATA_BITS_NO_PARITY;
|
||||
U2MODEbits.ABAUD = serAUTO_BAUD_OFF;
|
||||
U2MODEbits.LPBACK = serLOOPBACK_OFF;
|
||||
U2MODEbits.WAKE = serWAKE_UP_DISABLE;
|
||||
U2MODEbits.UEN = serNO_HARDWARE_FLOW_CONTROL;
|
||||
U2MODEbits.IREN = serNO_IRDA;
|
||||
U2MODEbits.USIDL = serCONTINUE_IN_IDLE_MODE;
|
||||
U2MODEbits.UARTEN = serUART_ENABLED;
|
||||
|
||||
U2BRG = (unsigned portSHORT)(( (float)configCPU_CLOCK_HZ / ( (float)16 * (float)ulWantedBaud ) ) - (float)0.5);
|
||||
|
||||
U2STAbits.URXISEL = serINTERRUPT_ON_SINGLE_CHAR;
|
||||
U2STAbits.UTXEN = serTX_ENABLE;
|
||||
U2STAbits.UTXINV = serNORMAL_IDLE_STATE;
|
||||
U2STAbits.UTXISEL0 = serINTERRUPT_ON_SINGLE_CHAR;
|
||||
U2STAbits.UTXISEL1 = serINTERRUPT_ON_SINGLE_CHAR;
|
||||
|
||||
/* It is assumed that this function is called prior to the scheduler being
|
||||
started. Therefore interrupts must not be allowed to occur yet as they
|
||||
may attempt to perform a context switch. */
|
||||
portDISABLE_INTERRUPTS();
|
||||
|
||||
IFS1bits.U2RXIF = serCLEAR_FLAG;
|
||||
IFS1bits.U2TXIF = serCLEAR_FLAG;
|
||||
IPC7bits.U2RXIP = portKERNEL_INTERRUPT_PRIORITY;
|
||||
IPC7bits.U2TXIP = portKERNEL_INTERRUPT_PRIORITY;
|
||||
IEC1bits.U2TXIE = serINTERRUPT_ENABLE;
|
||||
IEC1bits.U2RXIE = serINTERRUPT_ENABLE;
|
||||
|
||||
/* Clear the Rx buffer. */
|
||||
while( U2STAbits.URXDA == serSET_FLAG )
|
||||
{
|
||||
cChar = U2RXREG;
|
||||
}
|
||||
|
||||
xTxHasEnded = pdTRUE;
|
||||
|
||||
return NULL;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )
|
||||
{
|
||||
/* Only one port is supported. */
|
||||
( void ) pxPort;
|
||||
|
||||
/* Get the next character from the buffer. Return false if no characters
|
||||
are available or arrive before xBlockTime expires. */
|
||||
if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
|
||||
{
|
||||
return pdTRUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
return pdFALSE;
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )
|
||||
{
|
||||
/* Only one port is supported. */
|
||||
( void ) pxPort;
|
||||
|
||||
/* Return false if after the block time there is no room on the Tx queue. */
|
||||
if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
|
||||
{
|
||||
return pdFAIL;
|
||||
}
|
||||
|
||||
/* A critical section should not be required as xTxHasEnded will not be
|
||||
written to by the ISR if it is already 0 (is this correct?). */
|
||||
if( xTxHasEnded )
|
||||
{
|
||||
xTxHasEnded = pdFALSE;
|
||||
IFS1bits.U2TXIF = serSET_FLAG;
|
||||
}
|
||||
|
||||
return pdPASS;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vSerialClose( xComPortHandle xPort )
|
||||
{
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
volatile short s = 0;
|
||||
char c[80] = {0};
|
||||
|
||||
void __attribute__((__interrupt__)) _U2RXInterrupt( void )
|
||||
{
|
||||
portCHAR cChar;
|
||||
portBASE_TYPE xYieldRequired = pdFALSE;
|
||||
|
||||
/* Get the character and post it on the queue of Rxed characters.
|
||||
If the post causes a task to wake force a context switch as the woken task
|
||||
may have a higher priority than the task we have interrupted. */
|
||||
IFS1bits.U2RXIF = serCLEAR_FLAG;
|
||||
while( U2STAbits.URXDA )
|
||||
{
|
||||
cChar = U2RXREG;
|
||||
xYieldRequired = xQueueSendFromISR( xRxedChars, &cChar, xYieldRequired );
|
||||
}
|
||||
|
||||
if( xYieldRequired != pdFALSE )
|
||||
{
|
||||
taskYIELD();
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void __attribute__((__interrupt__)) _U2TXInterrupt( void )
|
||||
{
|
||||
signed portCHAR cChar;
|
||||
portBASE_TYPE xTaskWoken = pdFALSE;
|
||||
|
||||
/* If the transmit buffer is full we cannot get the next character.
|
||||
Another interrupt will occur the next time there is space so this does
|
||||
not matter. */
|
||||
IFS1bits.U2TXIF = serCLEAR_FLAG;
|
||||
while( !( U2STAbits.UTXBF ) )
|
||||
{
|
||||
if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWoken ) == pdTRUE )
|
||||
{
|
||||
/* Send the next character queued for Tx. */
|
||||
U2TXREG = cChar;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Queue empty, nothing to send. */
|
||||
xTxHasEnded = pdTRUE;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if( xTaskWoken != pdFALSE )
|
||||
{
|
||||
taskYIELD();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -0,0 +1,46 @@
|
||||
|
||||
2006-08-31 (REL_1_3) Christian Walter <wolti@sil.at>:
|
||||
Notes: Fixed some bugs in the lwIP porting layer. This includes a
|
||||
memory leak, wrong tasknames and an unnecessary lock of the
|
||||
scheduler.
|
||||
|
||||
Detailed notes:
|
||||
- BUG: Sys_arch_thread_remove did not free the memory from
|
||||
the TCB.
|
||||
- BUG: Unnecessary call to vTaskSuspendAll removed.
|
||||
- BUG: Bug with counting variable. The first to lwIP tasks
|
||||
got the same name (lwIP0).
|
||||
|
||||
2006-08-31 (REL_1_2) Christian Walter <wolti@sil.at>:
|
||||
Notes: Added HTML documentation used for FreeRTOS. Fixed copyright
|
||||
issues.
|
||||
|
||||
2006-08-30 (REL_1_2) Christian Walter <wolti@sil.at>:
|
||||
Notes: Fixed bug in serial transmission function vSerialPutString which
|
||||
gives unintended behaviour.
|
||||
|
||||
Detailed notes:
|
||||
- BUG: vSerialPutString should call xSerialPutChar with a small timeout
|
||||
such that a retransmission is tried rather fast. The previous
|
||||
port uses portMAX_DELAY which blocked it to long.
|
||||
|
||||
2006-08-29 (REL_1_1) Christian Walter <wolti@sil.at>:
|
||||
Notes: Updated lwip to 1.1.1 and fixed bugs in FEC driver as well as in
|
||||
the FreeRTOS porting layer (sys_arch.c)
|
||||
|
||||
Detailed notes:
|
||||
- BUG: Fixed thread creation in sys_thread_new which needs the scheduler
|
||||
disabled because otherwise a task could ge started immediately by
|
||||
portYIELD( ) leaving the lwIP thread datatstructures uninitialized.
|
||||
- BUG: The FEC driver must guard the ARP layer with a semaphore because
|
||||
it is not thread safe.
|
||||
- BUG: Repaired sys_mbox_free to work around an lwIP bug with a non empty
|
||||
mbox. An assertion is only triggered if a real memory leak is detected.
|
||||
- BUG: Timeouts are now correctly converted to ticks within the sys_arch
|
||||
layer.
|
||||
- FEATURES: General improvements in the sys_arch layer.
|
||||
author in this project.
|
||||
|
||||
2006-08-28 (REL_1_0) Christian Walter <wolti@sil.at>:
|
||||
Notes: Initial version of FreeRTOS/lwIP port for MCF5235.
|
||||
|
||||
@ -0,0 +1,75 @@
|
||||
/*
|
||||
FreeRTOS V4.1.0 - Copyright (C) 2003-2006 Richard Barry.
|
||||
MCF5235 Port - Copyright (C) 2006 Christian Walter.
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with FreeRTOS; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
|
||||
A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes FreeRTOS, without being obliged to provide
|
||||
the source code for any proprietary components. See the licensing section
|
||||
of http://www.FreeRTOS.org for full details of how and when the exception
|
||||
can be applied.
|
||||
|
||||
***************************************************************************
|
||||
See http://www.FreeRTOS.org for documentation, latest information, license
|
||||
and contact details. Please ensure to read the configuration and relevant
|
||||
port sections of the online documentation.
|
||||
***************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef FREERTOS_CONFIG_H
|
||||
#define FREERTOS_CONFIG_H
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Application specific definitions.
|
||||
*
|
||||
* These definitions should be adjusted for your particular hardware and
|
||||
* application requirements.
|
||||
*
|
||||
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
|
||||
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
|
||||
*----------------------------------------------------------*/
|
||||
|
||||
#define configUSE_PREEMPTION 1
|
||||
#define configUSE_IDLE_HOOK 0
|
||||
#define configUSE_TICK_HOOK 0
|
||||
#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 25000000 )
|
||||
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
|
||||
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )
|
||||
#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 )
|
||||
#define configMAX_TASK_NAME_LEN ( 16 )
|
||||
#define configUSE_TRACE_FACILITY 1
|
||||
#define configUSE_16_BIT_TICKS 0
|
||||
#define configIDLE_SHOULD_YIELD 1
|
||||
|
||||
/* Co-routine definitions. */
|
||||
#define configUSE_CO_ROUTINES 0
|
||||
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
|
||||
|
||||
/* Set the following definitions to 1 to include the API function, or zero
|
||||
to exclude the API function. */
|
||||
|
||||
#define INCLUDE_vTaskPrioritySet 1
|
||||
#define INCLUDE_uxTaskPriorityGet 1
|
||||
#define INCLUDE_vTaskDelete 1
|
||||
#define INCLUDE_vTaskCleanUpResources 0
|
||||
#define INCLUDE_vTaskSuspend 1
|
||||
#define INCLUDE_vTaskDelayUntil 1
|
||||
#define INCLUDE_vTaskDelay 1
|
||||
#define INCLUDE_xTaskGetCurrentTaskHandle 1
|
||||
|
||||
#endif /* FREERTOS_CONFIG_H */
|
||||
@ -0,0 +1,94 @@
|
||||
#
|
||||
# FreeRTOS 4.1.0 - MCF5235 Coldfire Port
|
||||
#
|
||||
# Copyright (c) 2006 Christian Walter, Vienna 2006.
|
||||
#
|
||||
# $Id: Makefile,v 1.4 2006/09/06 19:55:07 wolti Exp $
|
||||
#
|
||||
# ---------------------------------------------------------------------------
|
||||
BASE = /opt/gcc-m68k/bin
|
||||
CC = $(BASE)/m68k-elf-gcc
|
||||
CXX = $(BASE)/m68k-elf-g++
|
||||
OBJCOPY = $(BASE)/m68k-elf-objcopy
|
||||
SIZE = $(BASE)/m68k-elf-size
|
||||
INSIGHT = $(BASE)/m68k-bdm-elf-insight
|
||||
BDMFLASH = $(BASE)/bdmflash
|
||||
|
||||
#CFLAGS = -MD -gdwarf-2 -g3 -m528x -Wall
|
||||
CFLAGS = -MD -O2 -m528x -Wall \
|
||||
-D'GCC_MCF5235=1' -D'_GCC_USES_FP=1' \
|
||||
-D'__IPSBAR=((vuint8 *) 0x40000000)' -D'FSYS_2=25000000UL' \
|
||||
-I. -Iinclude -Iinclude/arch -Ifec \
|
||||
-I../../Source/include -I../Common/include \
|
||||
-Ilwip/src/include -Ilwip/src/include/ipv4 \
|
||||
-Ilwip/contrib/port/FreeRTOS/MCF5235 \
|
||||
-Ilwip/contrib/port/FreeRTOS/MCF5235/netif
|
||||
|
||||
ASFLAGS = -MD -gdwarf-2 -g3 -m528x -Wa,--register-prefix-optional \
|
||||
-Wa,--bitwise-or -Wa,--defsym,IPSBAR=0x40000000
|
||||
LDSCRIPT = m5235-ram.ld
|
||||
LDFLAGS = -nostartfiles -m528x -Wl,--script=$(LDSCRIPT)
|
||||
|
||||
TGT = demo
|
||||
OTHER_CSRC =
|
||||
OTHER_ASRC = $(addprefix system/, crt0.S vector.S)
|
||||
CSRC = demo.c web.c \
|
||||
$(addprefix system/, init.c newlib.c serial.c) \
|
||||
$(addprefix ../Common/Minimal/, PollQ.c integer.c flop.c BlockQ.c semtest.c dynamic.c ) \
|
||||
$(addprefix ../../Source/, tasks.c queue.c list.c) \
|
||||
$(addprefix ../../Source/portable/MemMang/, heap_3.c) \
|
||||
$(addprefix ../../Source/portable/GCC/MCF5235/, port.c) \
|
||||
$(addprefix lwip/src/core/, tcp_out.c inet.c mem.c memp.c netif.c pbuf.c raw.c stats.c sys.c tcp.c tcp_in.c udp.c ipv4/ip.c ipv4/ip_addr.c ipv4/icmp.c ipv4/ip_frag.c) \
|
||||
$(addprefix lwip/src/api/, tcpip.c api_msg.c err.c api_lib.c ) \
|
||||
$(addprefix lwip/src/netif/, etharp.c ) \
|
||||
$(addprefix lwip/contrib/port/FreeRTOS/MCF5235/, sys_arch.c netif/fec.c netif/nbuf.c)
|
||||
|
||||
ASRC = $(addprefix system/, mcf5xxx.S )
|
||||
OBJS = $(CSRC:.c=.o) $(ASRC:.S=.o)
|
||||
NOLINK_OBJS = $(OTHER_CSRC:.c=.o) $(OTHER_ASRC:.S=.o)
|
||||
DEPS = $(OBJS:.o=.d) $(NOLINK_OBJS:.o=.d)
|
||||
BIN = $(TGT).elf
|
||||
|
||||
.PHONY: clean all
|
||||
|
||||
all: $(BIN)
|
||||
|
||||
flash-programm: $(TGT).elf
|
||||
$(OBJCOPY) -O binary $(TGT).elf $(TGT).bin
|
||||
@BIN_SIZE=`du -b $(TGT).bin | awk '//{ print $$1; }'`; \
|
||||
echo "programming $(TGT).bin with size $$BIN_SIZE to flash..."; \
|
||||
$(BDMFLASH) /dev/bdmcf20 0x00000000 1 2 write $(TGT).bin 0
|
||||
|
||||
flash-verify:
|
||||
@BIN_SIZE=`du -b $(TGT).bin | awk '//{ print $$1; }'`; \
|
||||
echo "loading $$BIN_SIZE bytes from target into $(TGT).vrf..."; \
|
||||
$(BDMFLASH) /dev/bdmcf20 0x00000000 1 2 read $(TGT).vrf 0 $$BIN_SIZE
|
||||
|
||||
flash-erase:
|
||||
$(BDMFLASH) /dev/bdmcf20 0x00000000 1 2 erase
|
||||
|
||||
debug:
|
||||
$(INSIGHT) --command=m5235.gdb --se=$(TGT).elf
|
||||
|
||||
$(BIN): $(OBJS) $(NOLINK_OBJS)
|
||||
$(CC) $(LDFLAGS) -Wl,-Map=$(TGT).map $(OBJS) $(LDLIBS) -o $@
|
||||
|
||||
clean:
|
||||
rm -f $(DEPS)
|
||||
rm -f $(OBJS) $(NOLINK_OBJS)
|
||||
rm -f $(BIN) $(TGT).map
|
||||
|
||||
# ---------------------------------------------------------------------------
|
||||
# rules for code generation
|
||||
# ---------------------------------------------------------------------------
|
||||
%.o: %.c
|
||||
$(CC) $(CFLAGS) -o $@ -c $<
|
||||
|
||||
%.o: %.S
|
||||
$(CC) $(ASFLAGS) -o $@ -c $<
|
||||
|
||||
# ---------------------------------------------------------------------------
|
||||
# # compiler generated dependencies
|
||||
# ---------------------------------------------------------------------------
|
||||
-include $(DEPS)
|
||||
|
||||
@ -0,0 +1,56 @@
|
||||
|
||||
FREERTOS COLDFIRE MCF523x PORT with lwIP
|
||||
|
||||
REQUIREMENTS
|
||||
============
|
||||
|
||||
The FreeRTOS port is designed for the MCF523x processor where the hardware
|
||||
dependent part consists of the CPU and the peripherals used in this port.
|
||||
This includes a programmable timer (PIT) for the preemptive scheduler
|
||||
and a UART for the demo application. The Coldfire specific part includes
|
||||
the number and type of processor registers, the stack frame layout and
|
||||
the usage of a software interrupt (trap) for the yield call.
|
||||
|
||||
The development environment used is based on the GNU C Compiler for
|
||||
a m68k-elf target as well as the insight debugger with some patches for
|
||||
the BDM interface[1]. GDB startup and linker scripts are supplied with
|
||||
the demo for the M5235BCC evaluation kit from Freescale.
|
||||
|
||||
[1] ... BDM tools: http://sourceforge.net/projects/bdm/
|
||||
|
||||
USAGE
|
||||
=====
|
||||
|
||||
A makefile is supplied with the demo application and a binary can be
|
||||
produced by calling 'make all'. A special target 'debug' is provided
|
||||
which executes the insight debugger. At the insight debugger prompt
|
||||
one should select the appropriate target interface (either BDM/Direct
|
||||
or BDM/TCP) and should download the application to the development
|
||||
board. It is important that the GDB script setup-and-load is executed
|
||||
prior to downloading to initialize the SDRAM. After downloading one
|
||||
should call the GDB function 'execute' and the PC is set to the start
|
||||
of the executable. Execution can be started by typing 'continue' at
|
||||
the Insight console interface.
|
||||
After this startup phase the insight debugger should work as usual, i.e.
|
||||
no grayed out buttons, ...
|
||||
|
||||
|
||||
COMMON PROBLEMS
|
||||
===============
|
||||
|
||||
Most of the problems have their origin in the startup scripts. The
|
||||
following list should serve as a checklist where each point must be
|
||||
satisfied for the port to work.
|
||||
|
||||
- The FreeRTOS port only works correctly in the supervisor mode. There-
|
||||
fore the Coldfire CPU must run in the supervisor mode.
|
||||
|
||||
- portVECTOR_TABLE does not point to the currently active vector table.
|
||||
Please also note that the vector table must be in RAM such that the
|
||||
FreeRTOS port can install a traphandler for the portYIELD() call.
|
||||
|
||||
|
||||
$Id: README.txt,v 1.1 2006/08/29 02:24:03 wolti Exp $
|
||||
|
||||
MCF5235 + lwIP port - Copyright (c) 2006 Christian Walter.
|
||||
|
||||
@ -0,0 +1,287 @@
|
||||
/*
|
||||
FreeRTOS V4.1.0 - copyright (C) 2003-2006 Richard Barry.
|
||||
MCF5235 Port - Copyright (C) 2006 Christian Walter.
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with FreeRTOS; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
|
||||
A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes FreeRTOS, without being obliged to provide
|
||||
the source code for any proprietary components. See the licensing section
|
||||
of http://www.FreeRTOS.org for full details of how and when the exception
|
||||
can be applied.
|
||||
|
||||
***************************************************************************
|
||||
See http://www.FreeRTOS.org for documentation, latest information, license
|
||||
and contact details. Please ensure to read the configuration and relevant
|
||||
port sections of the online documentation.
|
||||
***************************************************************************
|
||||
*/
|
||||
|
||||
/* ------------------------ System includes ------------------------------- */
|
||||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <assert.h>
|
||||
|
||||
/* ------------------------ FreeRTOS includes ----------------------------- */
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
|
||||
/* ------------------------ LWIP includes --------------------------------- */
|
||||
#include "lwip/api.h"
|
||||
#include "lwip/tcpip.h"
|
||||
#include "lwip/memp.h"
|
||||
|
||||
/* ------------------------ Project includes ------------------------------ */
|
||||
#include "mcf5xxx.h"
|
||||
#include "mcf523x.h"
|
||||
#include "serial.h"
|
||||
|
||||
#include "web.h"
|
||||
#include "integer.h"
|
||||
#include "PollQ.h"
|
||||
#include "semtest.h"
|
||||
#include "BlockQ.h"
|
||||
#include "dynamic.h"
|
||||
#include "flop.h"
|
||||
|
||||
/* ------------------------ Defines --------------------------------------- */
|
||||
#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 38400 )
|
||||
|
||||
/* Priorities for the demo application tasks. */
|
||||
#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
|
||||
#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )
|
||||
#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )
|
||||
#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 )
|
||||
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
|
||||
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )
|
||||
#define mainWEB_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
|
||||
#define STACK_DEFAULT ( 1024 )
|
||||
|
||||
/* Interval in which tasks are checked. */
|
||||
#define mainCHECK_PERIOD ( ( portTickType ) 2000 / portTICK_RATE_MS )
|
||||
|
||||
/* Constants used by the vMemCheckTask() task. */
|
||||
#define mainCOUNT_INITIAL_VALUE ( ( unsigned portLONG ) 0 )
|
||||
#define mainNO_TASK ( 0 )
|
||||
|
||||
/* The size of the memory blocks allocated by the vMemCheckTask() task. */
|
||||
#define mainMEM_CHECK_SIZE_1 ( ( size_t ) 51 )
|
||||
#define mainMEM_CHECK_SIZE_2 ( ( size_t ) 52 )
|
||||
#define mainMEM_CHECK_SIZE_3 ( ( size_t ) 151 )
|
||||
|
||||
/* ------------------------ Static variables ------------------------------ */
|
||||
xComPortHandle xSTDComPort = NULL;
|
||||
|
||||
/* ------------------------ Static functions ------------------------------ */
|
||||
static portTASK_FUNCTION( vErrorChecks, pvParameters );
|
||||
static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG
|
||||
ulMemCheckTaskCount );
|
||||
static portTASK_FUNCTION( vMemCheckTask, pvParameters );
|
||||
|
||||
/* ------------------------ Implementation -------------------------------- */
|
||||
int
|
||||
main( int argc, char *argv[] )
|
||||
{
|
||||
asm volatile ( "move.w #0x2000, %sr\n\t" );
|
||||
|
||||
xSTDComPort = xSerialPortInitMinimal( 38400, 8 );
|
||||
vlwIPInit( );
|
||||
|
||||
/* Start the demo/test application tasks. */
|
||||
vStartIntegerMathTasks( tskIDLE_PRIORITY );
|
||||
vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
|
||||
//vStartMathTasks( tskIDLE_PRIORITY );
|
||||
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
|
||||
vStartDynamicPriorityTasks( );
|
||||
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
|
||||
|
||||
/* Start the webserver. */
|
||||
( void )sys_thread_new( vBasicWEBServer, NULL, mainWEB_TASK_PRIORITY );
|
||||
|
||||
/* Start the check task - which is defined in this file. */
|
||||
xTaskCreate( vErrorChecks, ( signed portCHAR * )"Check", 512, NULL,
|
||||
mainCHECK_TASK_PRIORITY, NULL );
|
||||
/* Now all the tasks have been started - start the scheduler. */
|
||||
vTaskStartScheduler( );
|
||||
|
||||
/* Should never get here! */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static
|
||||
portTASK_FUNCTION( vErrorChecks, pvParameters )
|
||||
{
|
||||
unsigned portLONG ulMemCheckTaskRunningCount;
|
||||
xTaskHandle xCreatedTask;
|
||||
|
||||
/* The parameters are not used in this function. */
|
||||
( void )pvParameters;
|
||||
|
||||
for( ;; )
|
||||
{
|
||||
ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE;
|
||||
xCreatedTask = mainNO_TASK;
|
||||
if( xTaskCreate( vMemCheckTask, ( signed portCHAR * )"MEM",
|
||||
configMINIMAL_STACK_SIZE, ( void * )&ulMemCheckTaskRunningCount,
|
||||
tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS )
|
||||
{
|
||||
xSerialPutChar( xSTDComPort, 'E', portMAX_DELAY );
|
||||
}
|
||||
/* Delay until it is time to execute again. */
|
||||
vTaskDelay( mainCHECK_PERIOD );
|
||||
|
||||
/* Delete the dynamically created task. */
|
||||
if( xCreatedTask != mainNO_TASK )
|
||||
{
|
||||
vTaskDelete( xCreatedTask );
|
||||
}
|
||||
|
||||
if( prvCheckOtherTasksAreStillRunning( ulMemCheckTaskRunningCount ) != pdPASS )
|
||||
{
|
||||
xSerialPutChar( xSTDComPort, 'E', portMAX_DELAY );
|
||||
}
|
||||
else
|
||||
{
|
||||
xSerialPutChar( xSTDComPort, '.', portMAX_DELAY );
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static portLONG
|
||||
prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount )
|
||||
{
|
||||
portLONG lReturn = ( portLONG ) pdPASS;
|
||||
|
||||
/* Check all the demo tasks (other than the flash tasks) to ensure
|
||||
* that they are all still running, and that none of them have detected
|
||||
* an error.
|
||||
*/
|
||||
if( xAreIntegerMathsTaskStillRunning( ) != pdTRUE )
|
||||
{
|
||||
lReturn = ( portLONG ) pdFAIL;
|
||||
}
|
||||
|
||||
if( xArePollingQueuesStillRunning( ) != pdTRUE )
|
||||
{
|
||||
lReturn = ( portLONG ) pdFAIL;
|
||||
}
|
||||
|
||||
if( xAreSemaphoreTasksStillRunning( ) != pdTRUE )
|
||||
{
|
||||
lReturn = ( portLONG ) pdFAIL;
|
||||
}
|
||||
|
||||
if( xAreDynamicPriorityTasksStillRunning( ) != pdTRUE )
|
||||
{
|
||||
lReturn = ( portLONG ) pdFAIL;
|
||||
}
|
||||
|
||||
if( xAreBlockingQueuesStillRunning( ) != pdTRUE )
|
||||
{
|
||||
lReturn = ( portLONG ) pdFAIL;
|
||||
}
|
||||
|
||||
if( ulMemCheckTaskCount == mainCOUNT_INITIAL_VALUE )
|
||||
{
|
||||
/* The vMemCheckTask did not increment the counter - it must
|
||||
* have failed.
|
||||
*/
|
||||
lReturn = ( portLONG ) pdFAIL;
|
||||
}
|
||||
return lReturn;
|
||||
}
|
||||
|
||||
static void
|
||||
vMemCheckTask( void *pvParameters )
|
||||
{
|
||||
unsigned portLONG *pulMemCheckTaskRunningCounter;
|
||||
void *pvMem1, *pvMem2, *pvMem3;
|
||||
static portLONG lErrorOccurred = pdFALSE;
|
||||
|
||||
/* This task is dynamically created then deleted during each cycle of the
|
||||
vErrorChecks task to check the operation of the memory allocator. Each time
|
||||
the task is created memory is allocated for the stack and TCB. Each time
|
||||
the task is deleted this memory is returned to the heap. This task itself
|
||||
exercises the allocator by allocating and freeing blocks.
|
||||
|
||||
The task executes at the idle priority so does not require a delay.
|
||||
|
||||
pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the
|
||||
vErrorChecks() task that this task is still executing without error. */
|
||||
|
||||
pulMemCheckTaskRunningCounter = ( unsigned portLONG * )pvParameters;
|
||||
|
||||
for( ;; )
|
||||
{
|
||||
if( lErrorOccurred == pdFALSE )
|
||||
{
|
||||
/* We have never seen an error so increment the counter. */
|
||||
( *pulMemCheckTaskRunningCounter )++;
|
||||
}
|
||||
|
||||
/* Allocate some memory - just to give the allocator some extra
|
||||
exercise. This has to be in a critical section to ensure the
|
||||
task does not get deleted while it has memory allocated. */
|
||||
vTaskSuspendAll( );
|
||||
{
|
||||
pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 );
|
||||
if( pvMem1 == NULL )
|
||||
{
|
||||
lErrorOccurred = pdTRUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 );
|
||||
vPortFree( pvMem1 );
|
||||
}
|
||||
}
|
||||
xTaskResumeAll( );
|
||||
|
||||
/* Again - with a different size block. */
|
||||
vTaskSuspendAll( );
|
||||
{
|
||||
pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 );
|
||||
if( pvMem2 == NULL )
|
||||
{
|
||||
lErrorOccurred = pdTRUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 );
|
||||
vPortFree( pvMem2 );
|
||||
}
|
||||
}
|
||||
xTaskResumeAll( );
|
||||
|
||||
/* Again - with a different size block. */
|
||||
vTaskSuspendAll( );
|
||||
{
|
||||
pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 );
|
||||
if( pvMem3 == NULL )
|
||||
{
|
||||
lErrorOccurred = pdTRUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 );
|
||||
vPortFree( pvMem3 );
|
||||
}
|
||||
}
|
||||
xTaskResumeAll( );
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,46 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_H__
|
||||
#define __MCF523X_H__
|
||||
|
||||
/*********************************************************************/
|
||||
|
||||
#include "mcf523x/mcf523x_fec.h"
|
||||
#include "mcf523x/mcf523x_rng.h"
|
||||
#include "mcf523x/mcf523x_fmpll.h"
|
||||
#include "mcf523x/mcf523x_cs.h"
|
||||
#include "mcf523x/mcf523x_intc0.h"
|
||||
#include "mcf523x/mcf523x_intc1.h"
|
||||
#include "mcf523x/mcf523x_sdramc.h"
|
||||
#include "mcf523x/mcf523x_sram.h"
|
||||
#include "mcf523x/mcf523x_uart.h"
|
||||
#include "mcf523x/mcf523x_timer.h"
|
||||
#include "mcf523x/mcf523x_qspi.h"
|
||||
#include "mcf523x/mcf523x_eport.h"
|
||||
#include "mcf523x/mcf523x_i2c.h"
|
||||
#include "mcf523x/mcf523x_scm.h"
|
||||
#include "mcf523x/mcf523x_pit.h"
|
||||
#include "mcf523x/mcf523x_can.h"
|
||||
#include "mcf523x/mcf523x_wtm.h"
|
||||
#include "mcf523x/mcf523x_gpio.h"
|
||||
#include "mcf523x/mcf523x_mdha.h"
|
||||
#include "mcf523x/mcf523x_ccm.h"
|
||||
#include "mcf523x/mcf523x_rcm.h"
|
||||
#include "mcf523x/mcf523x_etpu.h"
|
||||
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_H__ */
|
||||
@ -0,0 +1,325 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_can.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_CAN_H__
|
||||
#define __MCF523X_CAN_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* FlexCAN Module (CAN)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_CAN_CANMCR0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0000]))
|
||||
#define MCF_CAN_CANCTRL0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0004]))
|
||||
#define MCF_CAN_TIMER0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0008]))
|
||||
#define MCF_CAN_RXGMASK0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0010]))
|
||||
#define MCF_CAN_RX14MASK0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0014]))
|
||||
#define MCF_CAN_RX15MASK0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0018]))
|
||||
#define MCF_CAN_ERRCNT0 (*(vuint32*)(void*)(&__IPSBAR[0x1C001C]))
|
||||
#define MCF_CAN_ERRSTAT0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0020]))
|
||||
#define MCF_CAN_IMASK0 (*(vuint16*)(void*)(&__IPSBAR[0x1C002A]))
|
||||
#define MCF_CAN_IFLAG0 (*(vuint16*)(void*)(&__IPSBAR[0x1C0032]))
|
||||
#define MCF_CAN_CANMCR1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0000]))
|
||||
#define MCF_CAN_CANCTRL1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0004]))
|
||||
#define MCF_CAN_TIMER1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0008]))
|
||||
#define MCF_CAN_RXGMASK1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0010]))
|
||||
#define MCF_CAN_RX14MASK1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0014]))
|
||||
#define MCF_CAN_RX15MASK1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0018]))
|
||||
#define MCF_CAN_ERRCNT1 (*(vuint32*)(void*)(&__IPSBAR[0x1F001C]))
|
||||
#define MCF_CAN_ERRSTAT1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0020]))
|
||||
#define MCF_CAN_IMASK1 (*(vuint16*)(void*)(&__IPSBAR[0x1F002A]))
|
||||
#define MCF_CAN_IFLAG1 (*(vuint16*)(void*)(&__IPSBAR[0x1F0032]))
|
||||
#define MCF_CAN_CANMCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0000+((x)*0x30000)]))
|
||||
#define MCF_CAN_CANCTRL(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0004+((x)*0x30000)]))
|
||||
#define MCF_CAN_TIMER(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0008+((x)*0x30000)]))
|
||||
#define MCF_CAN_RXGMASK(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0010+((x)*0x30000)]))
|
||||
#define MCF_CAN_RX14MASK(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0014+((x)*0x30000)]))
|
||||
#define MCF_CAN_RX15MASK(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0018+((x)*0x30000)]))
|
||||
#define MCF_CAN_ERRCNT(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C001C+((x)*0x30000)]))
|
||||
#define MCF_CAN_ERRSTAT(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0020+((x)*0x30000)]))
|
||||
#define MCF_CAN_IMASK(x) (*(vuint16*)(void*)(&__IPSBAR[0x1C002A+((x)*0x30000)]))
|
||||
#define MCF_CAN_IFLAG(x) (*(vuint16*)(void*)(&__IPSBAR[0x1C0032+((x)*0x30000)]))
|
||||
|
||||
#define MCF_CAN_MBUF0_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0080+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF0_TMSTP(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0082+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF0_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0084+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF0_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0088+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF0_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0089+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF0_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF0_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF0_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF0_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF0_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF0_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008F+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0090+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_TMSTP(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0092+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0094+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0098+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0099+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009F+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00A0+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00A4+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00A8+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00A9+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AA+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AB+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AC+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AD+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AE+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AF+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF3_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00B0+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF3_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00B4+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF3_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00B8+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF3_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00B9+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF3_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BA+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF3_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BB+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF3_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BC+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF3_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BD+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF3_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BE+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF3_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BF+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF4_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00C0+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF4_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00C4+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF4_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00C8+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF4_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00C9+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF4_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CA+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF4_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CB+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF4_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CC+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF4_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CD+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF4_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CE+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF4_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CF+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF5_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00D0+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF5_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00D4+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF5_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00D8+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF5_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00D9+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF5_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DA+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF5_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DB+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF5_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DC+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF5_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DD+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF5_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DE+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF5_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DF+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF6_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00E0+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF6_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00E4+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF6_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00E8+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF6_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00E9+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF6_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EA+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF6_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EB+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF6_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EC+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF6_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00ED+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF6_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EE+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF6_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EF+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF7_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00F0+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF7_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00F4+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF7_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00F8+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF7_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00F9+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF7_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FA+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF7_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FB+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF7_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FC+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF7_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FD+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF7_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FE+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF7_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FF+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0100+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0104+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0108+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0109+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010F+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0100+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0114+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0118+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0119+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011F+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0120+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0124+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0128+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0129+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012F+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0130+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0134+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0138+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0139+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013F+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0140+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0144+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0148+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0149+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014F+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0150+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0154+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0158+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0159+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015F+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0160+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0164+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0168+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0169+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016F+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0170+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0174+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0178+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0179+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017F+((x)*0x30000)]))
|
||||
|
||||
|
||||
#define MCF_CAN_MBUF0_DATAL(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0088+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF0_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C008C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_DATAL(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0098+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C009C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_DATAL(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00A8+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00AC+((x)*0x30000)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_CANMCR */
|
||||
#define MCF_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0)
|
||||
#define MCF_CAN_CANMCR_SUPV (0x00800000)
|
||||
#define MCF_CAN_CANMCR_FRZACK (0x01000000)
|
||||
#define MCF_CAN_CANMCR_SOFTRST (0x02000000)
|
||||
#define MCF_CAN_CANMCR_HALT (0x10000000)
|
||||
#define MCF_CAN_CANMCR_FRZ (0x40000000)
|
||||
#define MCF_CAN_CANMCR_MDIS (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_CANCTRL */
|
||||
#define MCF_CAN_CANCTRL_PROPSEG(x) (((x)&0x00000007)<<0)
|
||||
#define MCF_CAN_CANCTRL_LOM (0x00000008)
|
||||
#define MCF_CAN_CANCTRL_LBUF (0x00000010)
|
||||
#define MCF_CAN_CANCTRL_TSYNC (0x00000020)
|
||||
#define MCF_CAN_CANCTRL_BOFFREC (0x00000040)
|
||||
#define MCF_CAN_CANCTRL_SAMP (0x00000080)
|
||||
#define MCF_CAN_CANCTRL_LPB (0x00001000)
|
||||
#define MCF_CAN_CANCTRL_CLKSRC (0x00002000)
|
||||
#define MCF_CAN_CANCTRL_ERRMSK (0x00004000)
|
||||
#define MCF_CAN_CANCTRL_BOFFMSK (0x00008000)
|
||||
#define MCF_CAN_CANCTRL_PSEG2(x) (((x)&0x00000007)<<16)
|
||||
#define MCF_CAN_CANCTRL_PSEG1(x) (((x)&0x00000007)<<19)
|
||||
#define MCF_CAN_CANCTRL_RJW(x) (((x)&0x00000003)<<22)
|
||||
#define MCF_CAN_CANCTRL_PRESDIV(x) (((x)&0x000000FF)<<24)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_TIMER */
|
||||
#define MCF_CAN_TIMER_TIMER(x) (((x)&0x0000FFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_RXGMASK */
|
||||
#define MCF_CAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_RX14MASK */
|
||||
#define MCF_CAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_RX15MASK */
|
||||
#define MCF_CAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_ERRCNT */
|
||||
#define MCF_CAN_ERRCNT_TXECTR(x) (((x)&0x000000FF)<<0)
|
||||
#define MCF_CAN_ERRCNT_RXECTR(x) (((x)&0x000000FF)<<8)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_ERRSTAT */
|
||||
#define MCF_CAN_ERRSTAT_WAKINT (0x00000001)
|
||||
#define MCF_CAN_ERRSTAT_ERRINT (0x00000002)
|
||||
#define MCF_CAN_ERRSTAT_BOFFINT (0x00000004)
|
||||
#define MCF_CAN_ERRSTAT_FLTCONF(x) (((x)&0x00000003)<<4)
|
||||
#define MCF_CAN_ERRSTAT_TXRX (0x00000040)
|
||||
#define MCF_CAN_ERRSTAT_IDLE (0x00000080)
|
||||
#define MCF_CAN_ERRSTAT_RXWRN (0x00000100)
|
||||
#define MCF_CAN_ERRSTAT_TXWRN (0x00000200)
|
||||
#define MCF_CAN_ERRSTAT_STFERR (0x00000400)
|
||||
#define MCF_CAN_ERRSTAT_FRMERR (0x00000800)
|
||||
#define MCF_CAN_ERRSTAT_CRCERR (0x00001000)
|
||||
#define MCF_CAN_ERRSTAT_ACKERR (0x00002000)
|
||||
#define MCF_CAN_ERRSTAT_BITERR(x) (((x)&0x00000003)<<14)
|
||||
#define MCF_CAN_ERRSTAT_FLTCONF_ACTIVE (0x00000000)
|
||||
#define MCF_CAN_ERRSTAT_FLTCONF_PASSIVE (0x00000010)
|
||||
#define MCF_CAN_ERRSTAT_FLTCONF_BUSOFF (0x00000020)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_IMASK */
|
||||
#define MCF_CAN_IMASK_BUF0M (0x0001)
|
||||
#define MCF_CAN_IMASK_BUF1M (0x0002)
|
||||
#define MCF_CAN_IMASK_BUF2M (0x0004)
|
||||
#define MCF_CAN_IMASK_BUF3M (0x0008)
|
||||
#define MCF_CAN_IMASK_BUF4M (0x0010)
|
||||
#define MCF_CAN_IMASK_BUF5M (0x0020)
|
||||
#define MCF_CAN_IMASK_BUF6M (0x0040)
|
||||
#define MCF_CAN_IMASK_BUF7M (0x0080)
|
||||
#define MCF_CAN_IMASK_BUF8M (0x0100)
|
||||
#define MCF_CAN_IMASK_BUF9M (0x0200)
|
||||
#define MCF_CAN_IMASK_BUF10M (0x0400)
|
||||
#define MCF_CAN_IMASK_BUF11M (0x0800)
|
||||
#define MCF_CAN_IMASK_BUF12M (0x1000)
|
||||
#define MCF_CAN_IMASK_BUF13M (0x2000)
|
||||
#define MCF_CAN_IMASK_BUF14M (0x4000)
|
||||
#define MCF_CAN_IMASK_BUF15M (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_IFLAG */
|
||||
#define MCF_CAN_IFLAG_BUF0I (0x0001)
|
||||
#define MCF_CAN_IFLAG_BUF1I (0x0002)
|
||||
#define MCF_CAN_IFLAG_BUF2I (0x0004)
|
||||
#define MCF_CAN_IFLAG_BUF3I (0x0008)
|
||||
#define MCF_CAN_IFLAG_BUF4I (0x0010)
|
||||
#define MCF_CAN_IFLAG_BUF5I (0x0020)
|
||||
#define MCF_CAN_IFLAG_BUF6I (0x0040)
|
||||
#define MCF_CAN_IFLAG_BUF7I (0x0080)
|
||||
#define MCF_CAN_IFLAG_BUF8I (0x0100)
|
||||
#define MCF_CAN_IFLAG_BUF9I (0x0200)
|
||||
#define MCF_CAN_IFLAG_BUF10I (0x0400)
|
||||
#define MCF_CAN_IFLAG_BUF11I (0x0800)
|
||||
#define MCF_CAN_IFLAG_BUF12I (0x1000)
|
||||
#define MCF_CAN_IFLAG_BUF13I (0x2000)
|
||||
#define MCF_CAN_IFLAG_BUF14I (0x4000)
|
||||
#define MCF_CAN_IFLAG_BUF15I (0x8000)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_CAN_H__ */
|
||||
@ -0,0 +1,56 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_ccm.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_CCM_H__
|
||||
#define __MCF523X_CCM_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Chip Configuration Module (CCM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_CCM_CCR (*(vuint16*)(void*)(&__IPSBAR[0x110004]))
|
||||
#define MCF_CCM_LPCR (*(vuint8 *)(void*)(&__IPSBAR[0x110007]))
|
||||
#define MCF_CCM_CIR (*(vuint16*)(void*)(&__IPSBAR[0x11000A]))
|
||||
#define MCF_CCM_RCON (*(vuint16*)(void*)(&__IPSBAR[0x110008]))
|
||||
|
||||
/* Bit definitions and macros for MCF_CCM_CCR */
|
||||
#define MCF_CCM_CCR_BMT(x) (((x)&0x0007)<<0)
|
||||
#define MCF_CCM_CCR_BME (0x0008)
|
||||
#define MCF_CCM_CCR_SZEN (0x0040)
|
||||
#define MCF_CCM_CCR_MODE(x) (((x)&0x0007)<<8)
|
||||
|
||||
/* Bit definitions and macros for MCF_CCM_LPCR */
|
||||
#define MCF_CCM_LPCR_STPMD(x) (((x)&0x03)<<3)
|
||||
#define MCF_CCM_LPCR_LPMD(x) (((x)&0x03)<<6)
|
||||
#define MCF_CCM_LPCR_LPMD_STOP (0xC0)
|
||||
#define MCF_CCM_LPCR_LPMD_WAIT (0x80)
|
||||
#define MCF_CCM_LPCR_LPMD_DOZE (0x40)
|
||||
#define MCF_CCM_LPCR_LPMD_RUN (0x00)
|
||||
|
||||
/* Bit definitions and macros for MCF_CCM_CIR */
|
||||
#define MCF_CCM_CIR_PRN(x) (((x)&0x003F)<<0)
|
||||
#define MCF_CCM_CIR_PIN(x) (((x)&0x03FF)<<6)
|
||||
|
||||
/* Bit definitions and macros for MCF_CCM_RCON */
|
||||
#define MCF_CCM_RCON_MODE (0x0001)
|
||||
#define MCF_CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3)
|
||||
#define MCF_CCM_RCON_RLOAD (0x0020)
|
||||
#define MCF_CCM_RCON_RCSC(x) (((x)&0x0003)<<8)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_CCM_H__ */
|
||||
@ -0,0 +1,101 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_cs.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_CS_H__
|
||||
#define __MCF523X_CS_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Chip Selects (CS)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_CS_CSAR0 (*(vuint16*)(void*)(&__IPSBAR[0x000080]))
|
||||
#define MCF_CS_CSMR0 (*(vuint32*)(void*)(&__IPSBAR[0x000084]))
|
||||
#define MCF_CS_CSCR0 (*(vuint16*)(void*)(&__IPSBAR[0x00008A]))
|
||||
#define MCF_CS_CSAR1 (*(vuint16*)(void*)(&__IPSBAR[0x00008C]))
|
||||
#define MCF_CS_CSMR1 (*(vuint32*)(void*)(&__IPSBAR[0x000090]))
|
||||
#define MCF_CS_CSCR1 (*(vuint16*)(void*)(&__IPSBAR[0x000096]))
|
||||
#define MCF_CS_CSAR2 (*(vuint16*)(void*)(&__IPSBAR[0x000098]))
|
||||
#define MCF_CS_CSMR2 (*(vuint32*)(void*)(&__IPSBAR[0x00009C]))
|
||||
#define MCF_CS_CSCR2 (*(vuint16*)(void*)(&__IPSBAR[0x0000A2]))
|
||||
#define MCF_CS_CSAR3 (*(vuint16*)(void*)(&__IPSBAR[0x0000A4]))
|
||||
#define MCF_CS_CSMR3 (*(vuint32*)(void*)(&__IPSBAR[0x0000A8]))
|
||||
#define MCF_CS_CSCR3 (*(vuint16*)(void*)(&__IPSBAR[0x0000AE]))
|
||||
#define MCF_CS_CSAR4 (*(vuint16*)(void*)(&__IPSBAR[0x0000B0]))
|
||||
#define MCF_CS_CSMR4 (*(vuint32*)(void*)(&__IPSBAR[0x0000B4]))
|
||||
#define MCF_CS_CSCR4 (*(vuint16*)(void*)(&__IPSBAR[0x0000BA]))
|
||||
#define MCF_CS_CSAR5 (*(vuint16*)(void*)(&__IPSBAR[0x0000BC]))
|
||||
#define MCF_CS_CSMR5 (*(vuint32*)(void*)(&__IPSBAR[0x0000C0]))
|
||||
#define MCF_CS_CSCR5 (*(vuint16*)(void*)(&__IPSBAR[0x0000C6]))
|
||||
#define MCF_CS_CSAR6 (*(vuint16*)(void*)(&__IPSBAR[0x0000C8]))
|
||||
#define MCF_CS_CSMR6 (*(vuint32*)(void*)(&__IPSBAR[0x0000CC]))
|
||||
#define MCF_CS_CSCR6 (*(vuint16*)(void*)(&__IPSBAR[0x0000D2]))
|
||||
#define MCF_CS_CSAR7 (*(vuint16*)(void*)(&__IPSBAR[0x0000D4]))
|
||||
#define MCF_CS_CSMR7 (*(vuint32*)(void*)(&__IPSBAR[0x0000D8]))
|
||||
#define MCF_CS_CSCR7 (*(vuint16*)(void*)(&__IPSBAR[0x0000DE]))
|
||||
#define MCF_CS_CSAR(x) (*(vuint16*)(void*)(&__IPSBAR[0x000080+((x)*0x00C)]))
|
||||
#define MCF_CS_CSMR(x) (*(vuint32*)(void*)(&__IPSBAR[0x000084+((x)*0x00C)]))
|
||||
#define MCF_CS_CSCR(x) (*(vuint16*)(void*)(&__IPSBAR[0x00008A+((x)*0x00C)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_CS_CSAR */
|
||||
#define MCF_CS_CSAR_BA(x) ((uint16)(((x)&0xFFFF0000)>>16))
|
||||
|
||||
/* Bit definitions and macros for MCF_CS_CSMR */
|
||||
#define MCF_CS_CSMR_V (0x00000001)
|
||||
#define MCF_CS_CSMR_UD (0x00000002)
|
||||
#define MCF_CS_CSMR_UC (0x00000004)
|
||||
#define MCF_CS_CSMR_SD (0x00000008)
|
||||
#define MCF_CS_CSMR_SC (0x00000010)
|
||||
#define MCF_CS_CSMR_CI (0x00000020)
|
||||
#define MCF_CS_CSMR_AM (0x00000040)
|
||||
#define MCF_CS_CSMR_WP (0x00000100)
|
||||
#define MCF_CS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16)
|
||||
#define MCF_CS_CSMR_BAM_4G (0xFFFF0000)
|
||||
#define MCF_CS_CSMR_BAM_2G (0x7FFF0000)
|
||||
#define MCF_CS_CSMR_BAM_1G (0x3FFF0000)
|
||||
#define MCF_CS_CSMR_BAM_1024M (0x3FFF0000)
|
||||
#define MCF_CS_CSMR_BAM_512M (0x1FFF0000)
|
||||
#define MCF_CS_CSMR_BAM_256M (0x0FFF0000)
|
||||
#define MCF_CS_CSMR_BAM_128M (0x07FF0000)
|
||||
#define MCF_CS_CSMR_BAM_64M (0x03FF0000)
|
||||
#define MCF_CS_CSMR_BAM_32M (0x01FF0000)
|
||||
#define MCF_CS_CSMR_BAM_16M (0x00FF0000)
|
||||
#define MCF_CS_CSMR_BAM_8M (0x007F0000)
|
||||
#define MCF_CS_CSMR_BAM_4M (0x003F0000)
|
||||
#define MCF_CS_CSMR_BAM_2M (0x001F0000)
|
||||
#define MCF_CS_CSMR_BAM_1M (0x000F0000)
|
||||
#define MCF_CS_CSMR_BAM_1024K (0x000F0000)
|
||||
#define MCF_CS_CSMR_BAM_512K (0x00070000)
|
||||
#define MCF_CS_CSMR_BAM_256K (0x00030000)
|
||||
#define MCF_CS_CSMR_BAM_128K (0x00010000)
|
||||
#define MCF_CS_CSMR_BAM_64K (0x00000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_CS_CSCR */
|
||||
#define MCF_CS_CSCR_SWWS(x) (((x)&0x0007)<<0)
|
||||
#define MCF_CS_CSCR_BSTW (0x0008)
|
||||
#define MCF_CS_CSCR_BSTR (0x0010)
|
||||
#define MCF_CS_CSCR_BEM (0x0020)
|
||||
#define MCF_CS_CSCR_PS(x) (((x)&0x0003)<<6)
|
||||
#define MCF_CS_CSCR_AA (0x0100)
|
||||
#define MCF_CS_CSCR_IWS(x) (((x)&0x000F)<<10)
|
||||
#define MCF_CS_CSCR_SRWS(x) (((x)&0x0003)<<14)
|
||||
#define MCF_CS_CSCR_PS_8 (0x0040)
|
||||
#define MCF_CS_CSCR_PS_16 (0x0080)
|
||||
#define MCF_CS_CSCR_PS_32 (0x0000)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_CS_H__ */
|
||||
@ -0,0 +1,92 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_eport.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_EPORT_H__
|
||||
#define __MCF523X_EPORT_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Edge Port Module (EPORT)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_EPORT_EPPAR (*(vuint16*)(void*)(&__IPSBAR[0x130000]))
|
||||
#define MCF_EPORT_EPDDR (*(vuint8 *)(void*)(&__IPSBAR[0x130002]))
|
||||
#define MCF_EPORT_EPIER (*(vuint8 *)(void*)(&__IPSBAR[0x130003]))
|
||||
#define MCF_EPORT_EPDR (*(vuint8 *)(void*)(&__IPSBAR[0x130004]))
|
||||
#define MCF_EPORT_EPPDR (*(vuint8 *)(void*)(&__IPSBAR[0x130005]))
|
||||
#define MCF_EPORT_EPFR (*(vuint8 *)(void*)(&__IPSBAR[0x130006]))
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPPAR */
|
||||
#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
|
||||
#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4)
|
||||
#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6)
|
||||
#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8)
|
||||
#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10)
|
||||
#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12)
|
||||
#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14)
|
||||
#define MCF_EPORT_EPPAR_EPPAx_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPAx_RISING (1)
|
||||
#define MCF_EPORT_EPPAR_EPPAx_FALLING (2)
|
||||
#define MCF_EPORT_EPPAR_EPPAx_BOTH (3)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPDDR */
|
||||
#define MCF_EPORT_EPDDR_EPDD1 (0x02)
|
||||
#define MCF_EPORT_EPDDR_EPDD2 (0x04)
|
||||
#define MCF_EPORT_EPDDR_EPDD3 (0x08)
|
||||
#define MCF_EPORT_EPDDR_EPDD4 (0x10)
|
||||
#define MCF_EPORT_EPDDR_EPDD5 (0x20)
|
||||
#define MCF_EPORT_EPDDR_EPDD6 (0x40)
|
||||
#define MCF_EPORT_EPDDR_EPDD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPIER */
|
||||
#define MCF_EPORT_EPIER_EPIE1 (0x02)
|
||||
#define MCF_EPORT_EPIER_EPIE2 (0x04)
|
||||
#define MCF_EPORT_EPIER_EPIE3 (0x08)
|
||||
#define MCF_EPORT_EPIER_EPIE4 (0x10)
|
||||
#define MCF_EPORT_EPIER_EPIE5 (0x20)
|
||||
#define MCF_EPORT_EPIER_EPIE6 (0x40)
|
||||
#define MCF_EPORT_EPIER_EPIE7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPDR */
|
||||
#define MCF_EPORT_EPDR_EPD1 (0x02)
|
||||
#define MCF_EPORT_EPDR_EPD2 (0x04)
|
||||
#define MCF_EPORT_EPDR_EPD3 (0x08)
|
||||
#define MCF_EPORT_EPDR_EPD4 (0x10)
|
||||
#define MCF_EPORT_EPDR_EPD5 (0x20)
|
||||
#define MCF_EPORT_EPDR_EPD6 (0x40)
|
||||
#define MCF_EPORT_EPDR_EPD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPPDR */
|
||||
#define MCF_EPORT_EPPDR_EPPD1 (0x02)
|
||||
#define MCF_EPORT_EPPDR_EPPD2 (0x04)
|
||||
#define MCF_EPORT_EPPDR_EPPD3 (0x08)
|
||||
#define MCF_EPORT_EPPDR_EPPD4 (0x10)
|
||||
#define MCF_EPORT_EPPDR_EPPD5 (0x20)
|
||||
#define MCF_EPORT_EPPDR_EPPD6 (0x40)
|
||||
#define MCF_EPORT_EPPDR_EPPD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPFR */
|
||||
#define MCF_EPORT_EPFR_EPF1 (0x02)
|
||||
#define MCF_EPORT_EPFR_EPF2 (0x04)
|
||||
#define MCF_EPORT_EPFR_EPF3 (0x08)
|
||||
#define MCF_EPORT_EPFR_EPF4 (0x10)
|
||||
#define MCF_EPORT_EPFR_EPF5 (0x20)
|
||||
#define MCF_EPORT_EPFR_EPF6 (0x40)
|
||||
#define MCF_EPORT_EPFR_EPF7 (0x80)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_EPORT_H__ */
|
||||
@ -0,0 +1,493 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_etpu.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_ETPU_H__
|
||||
#define __MCF523X_ETPU_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* enhanced Time Processor Unit (ETPU)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_ETPU_EMCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0000]))
|
||||
#define MCF_ETPU_ECDCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0004]))
|
||||
#define MCF_ETPU_EMISCCR (*(vuint32*)(void*)(&__IPSBAR[0x1D000C]))
|
||||
#define MCF_ETPU_ESCMODR (*(vuint32*)(void*)(&__IPSBAR[0x1D0010]))
|
||||
#define MCF_ETPU_EECR (*(vuint32*)(void*)(&__IPSBAR[0x1D0014]))
|
||||
#define MCF_ETPU_ETBCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0020]))
|
||||
#define MCF_ETPU_ETB1R (*(vuint32*)(void*)(&__IPSBAR[0x1D0024]))
|
||||
#define MCF_ETPU_ETB2R (*(vuint32*)(void*)(&__IPSBAR[0x1D0028]))
|
||||
#define MCF_ETPU_EREDCR (*(vuint32*)(void*)(&__IPSBAR[0x1D002C]))
|
||||
#define MCF_ETPU_ECISR (*(vuint32*)(void*)(&__IPSBAR[0x1D0200]))
|
||||
#define MCF_ETPU_ECDTRSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0210]))
|
||||
#define MCF_ETPU_ECIOSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0220]))
|
||||
#define MCF_ETPU_ECDTROSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0230]))
|
||||
#define MCF_ETPU_ECIER (*(vuint32*)(void*)(&__IPSBAR[0x1D0240]))
|
||||
#define MCF_ETPU_ECDTRER (*(vuint32*)(void*)(&__IPSBAR[0x1D0250]))
|
||||
#define MCF_ETPU_ECPSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0280]))
|
||||
#define MCF_ETPU_ECSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0290]))
|
||||
#define MCF_ETPU_EC0SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0404]))
|
||||
#define MCF_ETPU_EC1SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0414]))
|
||||
#define MCF_ETPU_EC2SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0424]))
|
||||
#define MCF_ETPU_EC3SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0434]))
|
||||
#define MCF_ETPU_EC4SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0444]))
|
||||
#define MCF_ETPU_EC5SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0454]))
|
||||
#define MCF_ETPU_EC6SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0464]))
|
||||
#define MCF_ETPU_EC7SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0474]))
|
||||
#define MCF_ETPU_EC8SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0484]))
|
||||
#define MCF_ETPU_EC9SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0494]))
|
||||
#define MCF_ETPU_EC10SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A4]))
|
||||
#define MCF_ETPU_EC11SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B4]))
|
||||
#define MCF_ETPU_EC12SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C4]))
|
||||
#define MCF_ETPU_EC13SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D4]))
|
||||
#define MCF_ETPU_EC14SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E4]))
|
||||
#define MCF_ETPU_EC15SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F4]))
|
||||
#define MCF_ETPU_EC16SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0504]))
|
||||
#define MCF_ETPU_EC17SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0514]))
|
||||
#define MCF_ETPU_EC18SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0524]))
|
||||
#define MCF_ETPU_EC19SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0534]))
|
||||
#define MCF_ETPU_EC20SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0544]))
|
||||
#define MCF_ETPU_EC21SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0554]))
|
||||
#define MCF_ETPU_EC22SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0564]))
|
||||
#define MCF_ETPU_EC23SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0574]))
|
||||
#define MCF_ETPU_EC24SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0584]))
|
||||
#define MCF_ETPU_EC25SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0594]))
|
||||
#define MCF_ETPU_EC26SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A4]))
|
||||
#define MCF_ETPU_EC27SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B4]))
|
||||
#define MCF_ETPU_EC28SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C4]))
|
||||
#define MCF_ETPU_EC29SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D4]))
|
||||
#define MCF_ETPU_EC30SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E4]))
|
||||
#define MCF_ETPU_EC31SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F4]))
|
||||
#define MCF_ETPU_ECnSCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0404+((x)*0x010)]))
|
||||
#define MCF_ETPU_EC0CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0400]))
|
||||
#define MCF_ETPU_EC1CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0410]))
|
||||
#define MCF_ETPU_EC2CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0420]))
|
||||
#define MCF_ETPU_EC3CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0430]))
|
||||
#define MCF_ETPU_EC4CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0440]))
|
||||
#define MCF_ETPU_EC5CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0450]))
|
||||
#define MCF_ETPU_EC6CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0460]))
|
||||
#define MCF_ETPU_EC7CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0470]))
|
||||
#define MCF_ETPU_EC8CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0480]))
|
||||
#define MCF_ETPU_EC9CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0490]))
|
||||
#define MCF_ETPU_EC10CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A0]))
|
||||
#define MCF_ETPU_EC11CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B0]))
|
||||
#define MCF_ETPU_EC12CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C0]))
|
||||
#define MCF_ETPU_EC13CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D0]))
|
||||
#define MCF_ETPU_EC14CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E0]))
|
||||
#define MCF_ETPU_EC15CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F0]))
|
||||
#define MCF_ETPU_EC16CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0500]))
|
||||
#define MCF_ETPU_EC17CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0510]))
|
||||
#define MCF_ETPU_EC18CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0520]))
|
||||
#define MCF_ETPU_EC19CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0530]))
|
||||
#define MCF_ETPU_EC20CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0540]))
|
||||
#define MCF_ETPU_EC21CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0550]))
|
||||
#define MCF_ETPU_EC22CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0560]))
|
||||
#define MCF_ETPU_EC23CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0570]))
|
||||
#define MCF_ETPU_EC24CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0580]))
|
||||
#define MCF_ETPU_EC25CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0590]))
|
||||
#define MCF_ETPU_EC26CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A0]))
|
||||
#define MCF_ETPU_EC27CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B0]))
|
||||
#define MCF_ETPU_EC28CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C0]))
|
||||
#define MCF_ETPU_EC29CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D0]))
|
||||
#define MCF_ETPU_EC30CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E0]))
|
||||
#define MCF_ETPU_EC31CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F0]))
|
||||
#define MCF_ETPU_ECnCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0400+((x)*0x010)]))
|
||||
#define MCF_ETPU_EC0HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0408]))
|
||||
#define MCF_ETPU_EC1HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0418]))
|
||||
#define MCF_ETPU_EC2HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0428]))
|
||||
#define MCF_ETPU_EC3HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0438]))
|
||||
#define MCF_ETPU_EC4HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0448]))
|
||||
#define MCF_ETPU_EC5HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0458]))
|
||||
#define MCF_ETPU_EC6HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0468]))
|
||||
#define MCF_ETPU_EC7HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0478]))
|
||||
#define MCF_ETPU_EC8HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0488]))
|
||||
#define MCF_ETPU_EC9HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0498]))
|
||||
#define MCF_ETPU_EC10HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A8]))
|
||||
#define MCF_ETPU_EC11HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B8]))
|
||||
#define MCF_ETPU_EC12HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C8]))
|
||||
#define MCF_ETPU_EC13HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D8]))
|
||||
#define MCF_ETPU_EC14HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E8]))
|
||||
#define MCF_ETPU_EC15HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F8]))
|
||||
#define MCF_ETPU_EC16HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0508]))
|
||||
#define MCF_ETPU_EC17HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0518]))
|
||||
#define MCF_ETPU_EC18HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0528]))
|
||||
#define MCF_ETPU_EC19HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0538]))
|
||||
#define MCF_ETPU_EC20HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0548]))
|
||||
#define MCF_ETPU_EC21HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0558]))
|
||||
#define MCF_ETPU_EC22HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0568]))
|
||||
#define MCF_ETPU_EC23HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0578]))
|
||||
#define MCF_ETPU_EC24HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0588]))
|
||||
#define MCF_ETPU_EC25HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0598]))
|
||||
#define MCF_ETPU_EC26HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A8]))
|
||||
#define MCF_ETPU_EC27HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B8]))
|
||||
#define MCF_ETPU_EC28HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C8]))
|
||||
#define MCF_ETPU_EC29HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D8]))
|
||||
#define MCF_ETPU_EC30HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E8]))
|
||||
#define MCF_ETPU_EC31HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F8]))
|
||||
#define MCF_ETPU_ECnHSSR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0408+((x)*0x010)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_EMCR */
|
||||
#define MCF_ETPU_EMCR_GTBE (0x00000001)
|
||||
#define MCF_ETPU_EMCR_VIS (0x00000040)
|
||||
#define MCF_ETPU_EMCR_SCMMISEN (0x00000200)
|
||||
#define MCF_ETPU_EMCR_SCMMISF (0x00000400)
|
||||
#define MCF_ETPU_EMCR_SCMSIZE(x) (((x)&0x0000001F)<<16)
|
||||
#define MCF_ETPU_EMCR_ILF2 (0x01000000)
|
||||
#define MCF_ETPU_EMCR_ILF1 (0x02000000)
|
||||
#define MCF_ETPU_EMCR_MGE2 (0x04000000)
|
||||
#define MCF_ETPU_EMCR_MGE1 (0x08000000)
|
||||
#define MCF_ETPU_EMCR_GEC (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECDCR */
|
||||
#define MCF_ETPU_ECDCR_PARM1(x) (((x)&0x0000007F)<<0)
|
||||
#define MCF_ETPU_ECDCR_WR (0x00000080)
|
||||
#define MCF_ETPU_ECDCR_PARM0(x) (((x)&0x0000007F)<<8)
|
||||
#define MCF_ETPU_ECDCR_PWIDTH (0x00008000)
|
||||
#define MCF_ETPU_ECDCR_PBASE(x) (((x)&0x000003FF)<<16)
|
||||
#define MCF_ETPU_ECDCR_CTBASE(x) (((x)&0x0000001F)<<26)
|
||||
#define MCF_ETPU_ECDCR_STS (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_EECR */
|
||||
#define MCF_ETPU_EECR_ETB(x) (((x)&0x0000001F)<<0)
|
||||
#define MCF_ETPU_EECR_CDFC(x) (((x)&0x00000003)<<14)
|
||||
#define MCF_ETPU_EECR_FPSK(x) (((x)&0x00000007)<<16)
|
||||
#define MCF_ETPU_EECR_HLTF (0x00800000)
|
||||
#define MCF_ETPU_EECR_STF (0x10000000)
|
||||
#define MCF_ETPU_EECR_MDIS (0x40000000)
|
||||
#define MCF_ETPU_EECR_FEND (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ETBCR */
|
||||
#define MCF_ETPU_ETBCR_TCR1P(x) (((x)&0x000000FF)<<0)
|
||||
#define MCF_ETPU_ETBCR_TCR1CTL(x) (((x)&0x00000003)<<14)
|
||||
#define MCF_ETPU_ETBCR_TCR2P(x) (((x)&0x0000003F)<<16)
|
||||
#define MCF_ETPU_ETBCR_AM (0x02000000)
|
||||
#define MCF_ETPU_ETBCR_TCRCF(x) (((x)&0x00000003)<<27)
|
||||
#define MCF_ETPU_ETBCR_TCR2CTL(x) (((x)&0x00000007)<<29)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ETB1R */
|
||||
#define MCF_ETPU_ETB1R_TCR1(x) (((x)&0x00FFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ETB2R */
|
||||
#define MCF_ETPU_ETB2R_TCR2(x) (((x)&0x00FFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_EREDCR */
|
||||
#define MCF_ETPU_EREDCR_SRV2(x) (((x)&0x0000000F)<<0)
|
||||
#define MCF_ETPU_EREDCR_SERVER_ID2(x) (((x)&0x0000000F)<<8)
|
||||
#define MCF_ETPU_EREDCR_RSC2 (0x00004000)
|
||||
#define MCF_ETPU_EREDCR_REN2 (0x00008000)
|
||||
#define MCF_ETPU_EREDCR_SRV1(x) (((x)&0x0000000F)<<16)
|
||||
#define MCF_ETPU_EREDCR_SERVER_ID1(x) (((x)&0x0000000F)<<24)
|
||||
#define MCF_ETPU_EREDCR_RSC1 (0x40000000)
|
||||
#define MCF_ETPU_EREDCR_REN1 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECISR */
|
||||
#define MCF_ETPU_ECISR_CIS0 (0x00000001)
|
||||
#define MCF_ETPU_ECISR_CIS1 (0x00000002)
|
||||
#define MCF_ETPU_ECISR_CIS2 (0x00000004)
|
||||
#define MCF_ETPU_ECISR_CIS3 (0x00000008)
|
||||
#define MCF_ETPU_ECISR_CIS4 (0x00000010)
|
||||
#define MCF_ETPU_ECISR_CIS5 (0x00000020)
|
||||
#define MCF_ETPU_ECISR_CIS6 (0x00000040)
|
||||
#define MCF_ETPU_ECISR_CIS7 (0x00000080)
|
||||
#define MCF_ETPU_ECISR_CIS8 (0x00000100)
|
||||
#define MCF_ETPU_ECISR_CIS9 (0x00000200)
|
||||
#define MCF_ETPU_ECISR_CIS10 (0x00000400)
|
||||
#define MCF_ETPU_ECISR_CIS11 (0x00000800)
|
||||
#define MCF_ETPU_ECISR_CIS12 (0x00001000)
|
||||
#define MCF_ETPU_ECISR_CIS13 (0x00002000)
|
||||
#define MCF_ETPU_ECISR_CIS14 (0x00004000)
|
||||
#define MCF_ETPU_ECISR_CIS15 (0x00008000)
|
||||
#define MCF_ETPU_ECISR_CIS16 (0x00010000)
|
||||
#define MCF_ETPU_ECISR_CIS17 (0x00020000)
|
||||
#define MCF_ETPU_ECISR_CIS18 (0x00040000)
|
||||
#define MCF_ETPU_ECISR_CIS19 (0x00080000)
|
||||
#define MCF_ETPU_ECISR_CIS20 (0x00100000)
|
||||
#define MCF_ETPU_ECISR_CIS21 (0x00200000)
|
||||
#define MCF_ETPU_ECISR_CIS22 (0x00400000)
|
||||
#define MCF_ETPU_ECISR_CIS23 (0x00800000)
|
||||
#define MCF_ETPU_ECISR_CIS24 (0x01000000)
|
||||
#define MCF_ETPU_ECISR_CIS25 (0x02000000)
|
||||
#define MCF_ETPU_ECISR_CIS26 (0x04000000)
|
||||
#define MCF_ETPU_ECISR_CIS27 (0x08000000)
|
||||
#define MCF_ETPU_ECISR_CIS28 (0x10000000)
|
||||
#define MCF_ETPU_ECISR_CIS29 (0x20000000)
|
||||
#define MCF_ETPU_ECISR_CIS30 (0x40000000)
|
||||
#define MCF_ETPU_ECISR_CIS31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECDTRSR */
|
||||
#define MCF_ETPU_ECDTRSR_DTRS0 (0x00000001)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS1 (0x00000002)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS2 (0x00000004)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS3 (0x00000008)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS4 (0x00000010)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS5 (0x00000020)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS6 (0x00000040)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS7 (0x00000080)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS8 (0x00000100)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS9 (0x00000200)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS10 (0x00000400)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS11 (0x00000800)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS12 (0x00001000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS13 (0x00002000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS14 (0x00004000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS15 (0x00008000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS16 (0x00010000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS17 (0x00020000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS18 (0x00040000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS19 (0x00080000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS20 (0x00100000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS21 (0x00200000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS22 (0x00400000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS23 (0x00800000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS24 (0x01000000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS25 (0x02000000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS26 (0x04000000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS27 (0x08000000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS28 (0x10000000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS29 (0x20000000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS30 (0x40000000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECIOSR */
|
||||
#define MCF_ETPU_ECIOSR_CIOS0 (0x00000001)
|
||||
#define MCF_ETPU_ECIOSR_CIOS1 (0x00000002)
|
||||
#define MCF_ETPU_ECIOSR_CIOS2 (0x00000004)
|
||||
#define MCF_ETPU_ECIOSR_CIOS3 (0x00000008)
|
||||
#define MCF_ETPU_ECIOSR_CIOS4 (0x00000010)
|
||||
#define MCF_ETPU_ECIOSR_CIOS5 (0x00000020)
|
||||
#define MCF_ETPU_ECIOSR_CIOS6 (0x00000040)
|
||||
#define MCF_ETPU_ECIOSR_CIOS7 (0x00000080)
|
||||
#define MCF_ETPU_ECIOSR_CIOS8 (0x00000100)
|
||||
#define MCF_ETPU_ECIOSR_CIOS9 (0x00000200)
|
||||
#define MCF_ETPU_ECIOSR_CIOS10 (0x00000400)
|
||||
#define MCF_ETPU_ECIOSR_CIOS11 (0x00000800)
|
||||
#define MCF_ETPU_ECIOSR_CIOS12 (0x00001000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS13 (0x00002000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS14 (0x00004000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS15 (0x00008000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS16 (0x00010000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS17 (0x00020000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS18 (0x00040000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS19 (0x00080000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS20 (0x00100000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS21 (0x00200000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS22 (0x00400000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS23 (0x00800000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS24 (0x01000000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS25 (0x02000000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS26 (0x04000000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS27 (0x08000000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS28 (0x10000000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS29 (0x20000000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS30 (0x40000000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECDTROSR */
|
||||
#define MCF_ETPU_ECDTROSR_DTROS0 (0x00000001)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS1 (0x00000002)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS2 (0x00000004)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS3 (0x00000008)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS4 (0x00000010)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS5 (0x00000020)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS6 (0x00000040)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS7 (0x00000080)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS8 (0x00000100)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS9 (0x00000200)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS10 (0x00000400)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS11 (0x00000800)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS12 (0x00001000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS13 (0x00002000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS14 (0x00004000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS15 (0x00008000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS16 (0x00010000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS17 (0x00020000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS18 (0x00040000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS19 (0x00080000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS20 (0x00100000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS21 (0x00200000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS22 (0x00400000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS23 (0x00800000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS24 (0x01000000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS25 (0x02000000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS26 (0x04000000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS27 (0x08000000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS28 (0x10000000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS29 (0x20000000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS30 (0x40000000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECIER */
|
||||
#define MCF_ETPU_ECIER_CIE0 (0x00000001)
|
||||
#define MCF_ETPU_ECIER_CIE1 (0x00000002)
|
||||
#define MCF_ETPU_ECIER_CIE2 (0x00000004)
|
||||
#define MCF_ETPU_ECIER_CIE3 (0x00000008)
|
||||
#define MCF_ETPU_ECIER_CIE4 (0x00000010)
|
||||
#define MCF_ETPU_ECIER_CIE5 (0x00000020)
|
||||
#define MCF_ETPU_ECIER_CIE6 (0x00000040)
|
||||
#define MCF_ETPU_ECIER_CIE7 (0x00000080)
|
||||
#define MCF_ETPU_ECIER_CIE8 (0x00000100)
|
||||
#define MCF_ETPU_ECIER_CIE9 (0x00000200)
|
||||
#define MCF_ETPU_ECIER_CIE10 (0x00000400)
|
||||
#define MCF_ETPU_ECIER_CIE11 (0x00000800)
|
||||
#define MCF_ETPU_ECIER_CIE12 (0x00001000)
|
||||
#define MCF_ETPU_ECIER_CIE13 (0x00002000)
|
||||
#define MCF_ETPU_ECIER_CIE14 (0x00004000)
|
||||
#define MCF_ETPU_ECIER_CIE15 (0x00008000)
|
||||
#define MCF_ETPU_ECIER_CIE16 (0x00010000)
|
||||
#define MCF_ETPU_ECIER_CIE17 (0x00020000)
|
||||
#define MCF_ETPU_ECIER_CIE18 (0x00040000)
|
||||
#define MCF_ETPU_ECIER_CIE19 (0x00080000)
|
||||
#define MCF_ETPU_ECIER_CIE20 (0x00100000)
|
||||
#define MCF_ETPU_ECIER_CIE21 (0x00200000)
|
||||
#define MCF_ETPU_ECIER_CIE22 (0x00400000)
|
||||
#define MCF_ETPU_ECIER_CIE23 (0x00800000)
|
||||
#define MCF_ETPU_ECIER_CIE24 (0x01000000)
|
||||
#define MCF_ETPU_ECIER_CIE25 (0x02000000)
|
||||
#define MCF_ETPU_ECIER_CIE26 (0x04000000)
|
||||
#define MCF_ETPU_ECIER_CIE27 (0x08000000)
|
||||
#define MCF_ETPU_ECIER_CIE28 (0x10000000)
|
||||
#define MCF_ETPU_ECIER_CIE29 (0x20000000)
|
||||
#define MCF_ETPU_ECIER_CIE30 (0x40000000)
|
||||
#define MCF_ETPU_ECIER_CIE31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECDTRER */
|
||||
#define MCF_ETPU_ECDTRER_DTRE0 (0x00000001)
|
||||
#define MCF_ETPU_ECDTRER_DTRE1 (0x00000002)
|
||||
#define MCF_ETPU_ECDTRER_DTRE2 (0x00000004)
|
||||
#define MCF_ETPU_ECDTRER_DTRE3 (0x00000008)
|
||||
#define MCF_ETPU_ECDTRER_DTRE4 (0x00000010)
|
||||
#define MCF_ETPU_ECDTRER_DTRE5 (0x00000020)
|
||||
#define MCF_ETPU_ECDTRER_DTRE6 (0x00000040)
|
||||
#define MCF_ETPU_ECDTRER_DTRE7 (0x00000080)
|
||||
#define MCF_ETPU_ECDTRER_DTRE8 (0x00000100)
|
||||
#define MCF_ETPU_ECDTRER_DTRE9 (0x00000200)
|
||||
#define MCF_ETPU_ECDTRER_DTRE10 (0x00000400)
|
||||
#define MCF_ETPU_ECDTRER_DTRE11 (0x00000800)
|
||||
#define MCF_ETPU_ECDTRER_DTRE12 (0x00001000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE13 (0x00002000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE14 (0x00004000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE15 (0x00008000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE16 (0x00010000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE17 (0x00020000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE18 (0x00040000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE19 (0x00080000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE20 (0x00100000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE21 (0x00200000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE22 (0x00400000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE23 (0x00800000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE24 (0x01000000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE25 (0x02000000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE26 (0x04000000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE27 (0x08000000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE28 (0x10000000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE29 (0x20000000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE30 (0x40000000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECPSSR */
|
||||
#define MCF_ETPU_ECPSSR_SR0 (0x00000001)
|
||||
#define MCF_ETPU_ECPSSR_SR1 (0x00000002)
|
||||
#define MCF_ETPU_ECPSSR_SR2 (0x00000004)
|
||||
#define MCF_ETPU_ECPSSR_SR3 (0x00000008)
|
||||
#define MCF_ETPU_ECPSSR_SR4 (0x00000010)
|
||||
#define MCF_ETPU_ECPSSR_SR5 (0x00000020)
|
||||
#define MCF_ETPU_ECPSSR_SR6 (0x00000040)
|
||||
#define MCF_ETPU_ECPSSR_SR7 (0x00000080)
|
||||
#define MCF_ETPU_ECPSSR_SR8 (0x00000100)
|
||||
#define MCF_ETPU_ECPSSR_SR9 (0x00000200)
|
||||
#define MCF_ETPU_ECPSSR_SR10 (0x00000400)
|
||||
#define MCF_ETPU_ECPSSR_SR11 (0x00000800)
|
||||
#define MCF_ETPU_ECPSSR_SR12 (0x00001000)
|
||||
#define MCF_ETPU_ECPSSR_SR13 (0x00002000)
|
||||
#define MCF_ETPU_ECPSSR_SR14 (0x00004000)
|
||||
#define MCF_ETPU_ECPSSR_SR15 (0x00008000)
|
||||
#define MCF_ETPU_ECPSSR_SR16 (0x00010000)
|
||||
#define MCF_ETPU_ECPSSR_SR17 (0x00020000)
|
||||
#define MCF_ETPU_ECPSSR_SR18 (0x00040000)
|
||||
#define MCF_ETPU_ECPSSR_SR19 (0x00080000)
|
||||
#define MCF_ETPU_ECPSSR_SR20 (0x00100000)
|
||||
#define MCF_ETPU_ECPSSR_SR21 (0x00200000)
|
||||
#define MCF_ETPU_ECPSSR_SR22 (0x00400000)
|
||||
#define MCF_ETPU_ECPSSR_SR23 (0x00800000)
|
||||
#define MCF_ETPU_ECPSSR_SR24 (0x01000000)
|
||||
#define MCF_ETPU_ECPSSR_SR25 (0x02000000)
|
||||
#define MCF_ETPU_ECPSSR_SR26 (0x04000000)
|
||||
#define MCF_ETPU_ECPSSR_SR27 (0x08000000)
|
||||
#define MCF_ETPU_ECPSSR_SR28 (0x10000000)
|
||||
#define MCF_ETPU_ECPSSR_SR29 (0x20000000)
|
||||
#define MCF_ETPU_ECPSSR_SR30 (0x40000000)
|
||||
#define MCF_ETPU_ECPSSR_SR31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECSSR */
|
||||
#define MCF_ETPU_ECSSR_SS0 (0x00000001)
|
||||
#define MCF_ETPU_ECSSR_SS1 (0x00000002)
|
||||
#define MCF_ETPU_ECSSR_SS2 (0x00000004)
|
||||
#define MCF_ETPU_ECSSR_SS3 (0x00000008)
|
||||
#define MCF_ETPU_ECSSR_SS4 (0x00000010)
|
||||
#define MCF_ETPU_ECSSR_SS5 (0x00000020)
|
||||
#define MCF_ETPU_ECSSR_SS6 (0x00000040)
|
||||
#define MCF_ETPU_ECSSR_SS7 (0x00000080)
|
||||
#define MCF_ETPU_ECSSR_SS8 (0x00000100)
|
||||
#define MCF_ETPU_ECSSR_SS9 (0x00000200)
|
||||
#define MCF_ETPU_ECSSR_SS10 (0x00000400)
|
||||
#define MCF_ETPU_ECSSR_SS11 (0x00000800)
|
||||
#define MCF_ETPU_ECSSR_SS12 (0x00001000)
|
||||
#define MCF_ETPU_ECSSR_SS13 (0x00002000)
|
||||
#define MCF_ETPU_ECSSR_SS14 (0x00004000)
|
||||
#define MCF_ETPU_ECSSR_SS15 (0x00008000)
|
||||
#define MCF_ETPU_ECSSR_SS16 (0x00010000)
|
||||
#define MCF_ETPU_ECSSR_SS17 (0x00020000)
|
||||
#define MCF_ETPU_ECSSR_SS18 (0x00040000)
|
||||
#define MCF_ETPU_ECSSR_SS19 (0x00080000)
|
||||
#define MCF_ETPU_ECSSR_SS20 (0x00100000)
|
||||
#define MCF_ETPU_ECSSR_SS21 (0x00200000)
|
||||
#define MCF_ETPU_ECSSR_SS22 (0x00400000)
|
||||
#define MCF_ETPU_ECSSR_SS23 (0x00800000)
|
||||
#define MCF_ETPU_ECSSR_SS24 (0x01000000)
|
||||
#define MCF_ETPU_ECSSR_SS25 (0x02000000)
|
||||
#define MCF_ETPU_ECSSR_SS26 (0x04000000)
|
||||
#define MCF_ETPU_ECSSR_SS27 (0x08000000)
|
||||
#define MCF_ETPU_ECSSR_SS28 (0x10000000)
|
||||
#define MCF_ETPU_ECSSR_SS29 (0x20000000)
|
||||
#define MCF_ETPU_ECSSR_SS30 (0x40000000)
|
||||
#define MCF_ETPU_ECSSR_SS31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECnSCR */
|
||||
#define MCF_ETPU_ECnSCR_FM(x) (((x)&0x00000003)<<0)
|
||||
#define MCF_ETPU_ECnSCR_OBE (0x00002000)
|
||||
#define MCF_ETPU_ECnSCR_OPS (0x00004000)
|
||||
#define MCF_ETPU_ECnSCR_IPS (0x00008000)
|
||||
#define MCF_ETPU_ECnSCR_DTROS (0x00400000)
|
||||
#define MCF_ETPU_ECnSCR_DTRS (0x00800000)
|
||||
#define MCF_ETPU_ECnSCR_CIOS (0x40000000)
|
||||
#define MCF_ETPU_ECnSCR_CIS (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECnCR */
|
||||
#define MCF_ETPU_ECnCR_CPBA(x) (((x)&0x000007FF)<<0)
|
||||
#define MCF_ETPU_ECnCR_OPOL (0x00004000)
|
||||
#define MCF_ETPU_ECnCR_ODIS (0x00008000)
|
||||
#define MCF_ETPU_ECnCR_CFS(x) (((x)&0x0000001F)<<16)
|
||||
#define MCF_ETPU_ECnCR_ETCS (0x01000000)
|
||||
#define MCF_ETPU_ECnCR_CPR(x) (((x)&0x00000003)<<28)
|
||||
#define MCF_ETPU_ECnCR_DTRE (0x40000000)
|
||||
#define MCF_ETPU_ECnCR_CIE (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECnHSSR */
|
||||
#define MCF_ETPU_ECnHSSR_HSR(x) (((x)&0x00000007)<<0)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_ETPU_H__ */
|
||||
@ -0,0 +1,208 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_fec.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_FEC_H__
|
||||
#define __MCF523X_FEC_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Fast Ethernet Controller (FEC)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_FEC_EIR (*(vuint32*)(void*)(&__IPSBAR[0x001004]))
|
||||
#define MCF_FEC_EIMR (*(vuint32*)(void*)(&__IPSBAR[0x001008]))
|
||||
#define MCF_FEC_RDAR (*(vuint32*)(void*)(&__IPSBAR[0x001010]))
|
||||
#define MCF_FEC_TDAR (*(vuint32*)(void*)(&__IPSBAR[0x001014]))
|
||||
#define MCF_FEC_ECR (*(vuint32*)(void*)(&__IPSBAR[0x001024]))
|
||||
#define MCF_FEC_MMFR (*(vuint32*)(void*)(&__IPSBAR[0x001040]))
|
||||
#define MCF_FEC_MSCR (*(vuint32*)(void*)(&__IPSBAR[0x001044]))
|
||||
#define MCF_FEC_MIBC (*(vuint32*)(void*)(&__IPSBAR[0x001064]))
|
||||
#define MCF_FEC_RCR (*(vuint32*)(void*)(&__IPSBAR[0x001084]))
|
||||
#define MCF_FEC_TCR (*(vuint32*)(void*)(&__IPSBAR[0x0010C4]))
|
||||
#define MCF_FEC_PALR (*(vuint32*)(void*)(&__IPSBAR[0x0010E4]))
|
||||
#define MCF_FEC_PAUR (*(vuint32*)(void*)(&__IPSBAR[0x0010E8]))
|
||||
#define MCF_FEC_OPD (*(vuint32*)(void*)(&__IPSBAR[0x0010EC]))
|
||||
#define MCF_FEC_IAUR (*(vuint32*)(void*)(&__IPSBAR[0x001118]))
|
||||
#define MCF_FEC_IALR (*(vuint32*)(void*)(&__IPSBAR[0x00111C]))
|
||||
#define MCF_FEC_GAUR (*(vuint32*)(void*)(&__IPSBAR[0x001120]))
|
||||
#define MCF_FEC_GALR (*(vuint32*)(void*)(&__IPSBAR[0x001124]))
|
||||
#define MCF_FEC_TFWR (*(vuint32*)(void*)(&__IPSBAR[0x001144]))
|
||||
#define MCF_FEC_FRBR (*(vuint32*)(void*)(&__IPSBAR[0x00114C]))
|
||||
#define MCF_FEC_FRSR (*(vuint32*)(void*)(&__IPSBAR[0x001150]))
|
||||
#define MCF_FEC_ERDSR (*(vuint32*)(void*)(&__IPSBAR[0x001180]))
|
||||
#define MCF_FEC_ETDSR (*(vuint32*)(void*)(&__IPSBAR[0x001184]))
|
||||
#define MCF_FEC_EMRBR (*(vuint32*)(void*)(&__IPSBAR[0x001188]))
|
||||
#define MCF_FEC_RMON_T_DROP (*(vuint32*)(void*)(&__IPSBAR[0x001200]))
|
||||
#define MCF_FEC_RMON_T_PACKETS (*(vuint32*)(void*)(&__IPSBAR[0x001204]))
|
||||
#define MCF_FEC_RMON_T_BC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x001208]))
|
||||
#define MCF_FEC_RMON_T_MC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x00120C]))
|
||||
#define MCF_FEC_RMON_T_CRC_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x001210]))
|
||||
#define MCF_FEC_RMON_T_UNDERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001214]))
|
||||
#define MCF_FEC_RMON_T_OVERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001218]))
|
||||
#define MCF_FEC_RMON_T_FRAG (*(vuint32*)(void*)(&__IPSBAR[0x00121C]))
|
||||
#define MCF_FEC_RMON_T_JAB (*(vuint32*)(void*)(&__IPSBAR[0x001220]))
|
||||
#define MCF_FEC_RMON_T_COL (*(vuint32*)(void*)(&__IPSBAR[0x001224]))
|
||||
#define MCF_FEC_RMON_T_P64 (*(vuint32*)(void*)(&__IPSBAR[0x001228]))
|
||||
#define MCF_FEC_RMON_T_P65TO127 (*(vuint32*)(void*)(&__IPSBAR[0x00122C]))
|
||||
#define MCF_FEC_RMON_T_P128TO255 (*(vuint32*)(void*)(&__IPSBAR[0x001230]))
|
||||
#define MCF_FEC_RMON_T_P256TO511 (*(vuint32*)(void*)(&__IPSBAR[0x001234]))
|
||||
#define MCF_FEC_RMON_T_P512TO1023 (*(vuint32*)(void*)(&__IPSBAR[0x001238]))
|
||||
#define MCF_FEC_RMON_T_P1024TO2047 (*(vuint32*)(void*)(&__IPSBAR[0x00123C]))
|
||||
#define MCF_FEC_RMON_T_P_GTE2048 (*(vuint32*)(void*)(&__IPSBAR[0x001240]))
|
||||
#define MCF_FEC_RMON_T_OCTETS (*(vuint32*)(void*)(&__IPSBAR[0x001244]))
|
||||
#define MCF_FEC_IEEE_T_DROP (*(vuint32*)(void*)(&__IPSBAR[0x001248]))
|
||||
#define MCF_FEC_IEEE_T_FRAME_OK (*(vuint32*)(void*)(&__IPSBAR[0x00124C]))
|
||||
#define MCF_FEC_IEEE_T_1COL (*(vuint32*)(void*)(&__IPSBAR[0x001250]))
|
||||
#define MCF_FEC_IEEE_T_MCOL (*(vuint32*)(void*)(&__IPSBAR[0x001254]))
|
||||
#define MCF_FEC_IEEE_T_DEF (*(vuint32*)(void*)(&__IPSBAR[0x001258]))
|
||||
#define MCF_FEC_IEEE_T_LCOL (*(vuint32*)(void*)(&__IPSBAR[0x00125C]))
|
||||
#define MCF_FEC_IEEE_T_EXCOL (*(vuint32*)(void*)(&__IPSBAR[0x001260]))
|
||||
#define MCF_FEC_IEEE_T_MACERR (*(vuint32*)(void*)(&__IPSBAR[0x001264]))
|
||||
#define MCF_FEC_IEEE_T_CSERR (*(vuint32*)(void*)(&__IPSBAR[0x001268]))
|
||||
#define MCF_FEC_IEEE_T_SQE (*(vuint32*)(void*)(&__IPSBAR[0x00126C]))
|
||||
#define MCF_FEC_IEEE_T_FDXFC (*(vuint32*)(void*)(&__IPSBAR[0x001270]))
|
||||
#define MCF_FEC_IEEE_T_OCTETS_OK (*(vuint32*)(void*)(&__IPSBAR[0x001274]))
|
||||
#define MCF_FEC_RMON_R_PACKETS (*(vuint32*)(void*)(&__IPSBAR[0x001284]))
|
||||
#define MCF_FEC_RMON_R_BC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x001288]))
|
||||
#define MCF_FEC_RMON_R_MC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x00128C]))
|
||||
#define MCF_FEC_RMON_R_CRC_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x001290]))
|
||||
#define MCF_FEC_RMON_R_UNDERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001294]))
|
||||
#define MCF_FEC_RMON_R_OVERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001298]))
|
||||
#define MCF_FEC_RMON_R_FRAG (*(vuint32*)(void*)(&__IPSBAR[0x00129C]))
|
||||
#define MCF_FEC_RMON_R_JAB (*(vuint32*)(void*)(&__IPSBAR[0x0012A0]))
|
||||
#define MCF_FEC_RMON_R_RESVD_0 (*(vuint32*)(void*)(&__IPSBAR[0x0012A4]))
|
||||
#define MCF_FEC_RMON_R_P64 (*(vuint32*)(void*)(&__IPSBAR[0x0012A8]))
|
||||
#define MCF_FEC_RMON_R_P65TO127 (*(vuint32*)(void*)(&__IPSBAR[0x0012AC]))
|
||||
#define MCF_FEC_RMON_R_P128TO255 (*(vuint32*)(void*)(&__IPSBAR[0x0012B0]))
|
||||
#define MCF_FEC_RMON_R_P256TO511 (*(vuint32*)(void*)(&__IPSBAR[0x0012B4]))
|
||||
#define MCF_FEC_RMON_R_512TO1023 (*(vuint32*)(void*)(&__IPSBAR[0x0012B8]))
|
||||
#define MCF_FEC_RMON_R_P_GTE2048 (*(vuint32*)(void*)(&__IPSBAR[0x0012C0]))
|
||||
#define MCF_FEC_RMON_R_1024TO2047 (*(vuint32*)(void*)(&__IPSBAR[0x0012BC]))
|
||||
#define MCF_FEC_RMON_R_OCTETS (*(vuint32*)(void*)(&__IPSBAR[0x0012C4]))
|
||||
#define MCF_FEC_IEEE_R_DROP (*(vuint32*)(void*)(&__IPSBAR[0x0012C8]))
|
||||
#define MCF_FEC_IEEE_R_FRAME_OK (*(vuint32*)(void*)(&__IPSBAR[0x0012CC]))
|
||||
#define MCF_FEC_IEEE_R_CRC (*(vuint32*)(void*)(&__IPSBAR[0x0012D0]))
|
||||
#define MCF_FEC_IEEE_R_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x0012D4]))
|
||||
#define MCF_FEC_IEEE_R_MACERR (*(vuint32*)(void*)(&__IPSBAR[0x0012D8]))
|
||||
#define MCF_FEC_IEEE_R_FDXFC (*(vuint32*)(void*)(&__IPSBAR[0x0012DC]))
|
||||
#define MCF_FEC_IEEE_R_OCTETS_OK (*(vuint32*)(void*)(&__IPSBAR[0x0012E0]))
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_EIR */
|
||||
#define MCF_FEC_EIR_UN (0x00080000)
|
||||
#define MCF_FEC_EIR_RL (0x00100000)
|
||||
#define MCF_FEC_EIR_LC (0x00200000)
|
||||
#define MCF_FEC_EIR_EBERR (0x00400000)
|
||||
#define MCF_FEC_EIR_MII (0x00800000)
|
||||
#define MCF_FEC_EIR_RXB (0x01000000)
|
||||
#define MCF_FEC_EIR_RXF (0x02000000)
|
||||
#define MCF_FEC_EIR_TXB (0x04000000)
|
||||
#define MCF_FEC_EIR_TXF (0x08000000)
|
||||
#define MCF_FEC_EIR_GRA (0x10000000)
|
||||
#define MCF_FEC_EIR_BABT (0x20000000)
|
||||
#define MCF_FEC_EIR_BABR (0x40000000)
|
||||
#define MCF_FEC_EIR_HBERR (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_EIMR */
|
||||
#define MCF_FEC_EIMR_UN (0x00080000)
|
||||
#define MCF_FEC_EIMR_RL (0x00100000)
|
||||
#define MCF_FEC_EIMR_LC (0x00200000)
|
||||
#define MCF_FEC_EIMR_EBERR (0x00400000)
|
||||
#define MCF_FEC_EIMR_MII (0x00800000)
|
||||
#define MCF_FEC_EIMR_RXB (0x01000000)
|
||||
#define MCF_FEC_EIMR_RXF (0x02000000)
|
||||
#define MCF_FEC_EIMR_TXB (0x04000000)
|
||||
#define MCF_FEC_EIMR_TXF (0x08000000)
|
||||
#define MCF_FEC_EIMR_GRA (0x10000000)
|
||||
#define MCF_FEC_EIMR_BABT (0x20000000)
|
||||
#define MCF_FEC_EIMR_BABR (0x40000000)
|
||||
#define MCF_FEC_EIMR_HBERR (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RDAR */
|
||||
#define MCF_FEC_RDAR_R_DES_ACTIVE (0x01000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_TDAR */
|
||||
#define MCF_FEC_TDAR_X_DES_ACTIVE (0x01000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_ECR */
|
||||
#define MCF_FEC_ECR_RESET (0x00000001)
|
||||
#define MCF_FEC_ECR_ETHER_EN (0x00000002)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_MMFR */
|
||||
#define MCF_FEC_MMFR_DATA(x) (((x)&0x0000FFFF)<<0)
|
||||
#define MCF_FEC_MMFR_TA(x) (((x)&0x00000003)<<16)
|
||||
#define MCF_FEC_MMFR_RA(x) (((x)&0x0000001F)<<18)
|
||||
#define MCF_FEC_MMFR_PA(x) (((x)&0x0000001F)<<23)
|
||||
#define MCF_FEC_MMFR_OP(x) (((x)&0x00000003)<<28)
|
||||
#define MCF_FEC_MMFR_ST(x) (((x)&0x00000003)<<30)
|
||||
#define MCF_FEC_MMFR_ST_01 (0x40000000)
|
||||
#define MCF_FEC_MMFR_OP_READ (0x20000000)
|
||||
#define MCF_FEC_MMFR_OP_WRITE (0x10000000)
|
||||
#define MCF_FEC_MMFR_TA_10 (0x00020000)
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_MSCR */
|
||||
#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x0000003F)<<1)
|
||||
#define MCF_FEC_MSCR_DIS_PREAMBLE (0x00000080)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_MIBC */
|
||||
#define MCF_FEC_MIBC_MIB_IDLE (0x40000000)
|
||||
#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RCR */
|
||||
#define MCF_FEC_RCR_LOOP (0x00000001)
|
||||
#define MCF_FEC_RCR_DRT (0x00000002)
|
||||
#define MCF_FEC_RCR_MII_MODE (0x00000004)
|
||||
#define MCF_FEC_RCR_PROM (0x00000008)
|
||||
#define MCF_FEC_RCR_BC_REJ (0x00000010)
|
||||
#define MCF_FEC_RCR_FCE (0x00000020)
|
||||
#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x000007FF)<<16)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_TCR */
|
||||
#define MCF_FEC_TCR_GTS (0x00000001)
|
||||
#define MCF_FEC_TCR_HBC (0x00000002)
|
||||
#define MCF_FEC_TCR_FDEN (0x00000004)
|
||||
#define MCF_FEC_TCR_TFC_PAUSE (0x00000008)
|
||||
#define MCF_FEC_TCR_RFC_PAUSE (0x00000010)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_PAUR */
|
||||
#define MCF_FEC_PAUR_TYPE(x) (((x)&0x0000FFFF)<<0)
|
||||
#define MCF_FEC_PAUR_PADDR2(x) (((x)&0x0000FFFF)<<16)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_OPD */
|
||||
#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0)
|
||||
#define MCF_FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_TFWR */
|
||||
#define MCF_FEC_TFWR_X_WMRK(x) (((x)&0x00000003)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FRBR */
|
||||
#define MCF_FEC_FRBR_R_BOUND(x) (((x)&0x000000FF)<<2)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FRSR */
|
||||
#define MCF_FEC_FRSR_R_FSTART(x) (((x)&0x000000FF)<<2)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_ERDSR */
|
||||
#define MCF_FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_ETDSR */
|
||||
#define MCF_FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_EMRBR */
|
||||
#define MCF_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x0000007F)<<4)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_FEC_H__ */
|
||||
@ -0,0 +1,55 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_fmpll.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_FMPLL_H__
|
||||
#define __MCF523X_FMPLL_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Frequency Modulated Phase Locked Loop (FMPLL)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_FMPLL_SYNCR (*(vuint32*)(void*)(&__IPSBAR[0x120000]))
|
||||
#define MCF_FMPLL_SYNSR (*(vuint32*)(void*)(&__IPSBAR[0x120004]))
|
||||
|
||||
/* Bit definitions and macros for MCF_FMPLL_SYNCR */
|
||||
#define MCF_FMPLL_SYNCR_EXP(x) (((x)&0x000003FF)<<0)
|
||||
#define MCF_FMPLL_SYNCR_DEPTH(x) (((x)&0x00000003)<<10)
|
||||
#define MCF_FMPLL_SYNCR_RATE (0x00001000)
|
||||
#define MCF_FMPLL_SYNCR_LOCIRQ (0x00002000)
|
||||
#define MCF_FMPLL_SYNCR_LOLIRQ (0x00004000)
|
||||
#define MCF_FMPLL_SYNCR_DISCLK (0x00008000)
|
||||
#define MCF_FMPLL_SYNCR_LOCRE (0x00010000)
|
||||
#define MCF_FMPLL_SYNCR_LOLRE (0x00020000)
|
||||
#define MCF_FMPLL_SYNCR_LOCEN (0x00040000)
|
||||
#define MCF_FMPLL_SYNCR_RFD(x) (((x)&0x00000007)<<19)
|
||||
#define MCF_FMPLL_SYNCR_MFD(x) (((x)&0x00000007)<<24)
|
||||
|
||||
/* Bit definitions and macros for MCF_FMPLL_SYNSR */
|
||||
#define MCF_FMPLL_SYNSR_CALPASS (0x00000001)
|
||||
#define MCF_FMPLL_SYNSR_CALDONE (0x00000002)
|
||||
#define MCF_FMPLL_SYNSR_LOCF (0x00000004)
|
||||
#define MCF_FMPLL_SYNSR_LOCK (0x00000008)
|
||||
#define MCF_FMPLL_SYNSR_LOCKS (0x00000010)
|
||||
#define MCF_FMPLL_SYNSR_PLLREF (0x00000020)
|
||||
#define MCF_FMPLL_SYNSR_PLLSEL (0x00000040)
|
||||
#define MCF_FMPLL_SYNSR_MODE (0x00000080)
|
||||
#define MCF_FMPLL_SYNSR_LOC (0x00000100)
|
||||
#define MCF_FMPLL_SYNSR_LOLF (0x00000200)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_FMPLL_H__ */
|
||||
@ -0,0 +1,676 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_gpio.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_GPIO_H__
|
||||
#define __MCF523X_GPIO_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* General Purpose I/O (GPIO)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_GPIO_PODR_ADDR (*(vuint8 *)(void*)(&__IPSBAR[0x100000]))
|
||||
#define MCF_GPIO_PODR_DATAH (*(vuint8 *)(void*)(&__IPSBAR[0x100001]))
|
||||
#define MCF_GPIO_PODR_DATAL (*(vuint8 *)(void*)(&__IPSBAR[0x100002]))
|
||||
#define MCF_GPIO_PODR_BUSCTL (*(vuint8 *)(void*)(&__IPSBAR[0x100003]))
|
||||
#define MCF_GPIO_PODR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100004]))
|
||||
#define MCF_GPIO_PODR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100005]))
|
||||
#define MCF_GPIO_PODR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100006]))
|
||||
#define MCF_GPIO_PODR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100007]))
|
||||
#define MCF_GPIO_PODR_UARTH (*(vuint8 *)(void*)(&__IPSBAR[0x100008]))
|
||||
#define MCF_GPIO_PODR_UARTL (*(vuint8 *)(void*)(&__IPSBAR[0x100009]))
|
||||
#define MCF_GPIO_PODR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10000A]))
|
||||
#define MCF_GPIO_PODR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x10000B]))
|
||||
#define MCF_GPIO_PODR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10000C]))
|
||||
#define MCF_GPIO_PDDR_APDDR (*(vuint8 *)(void*)(&__IPSBAR[0x100010]))
|
||||
#define MCF_GPIO_PDDR_DATAH (*(vuint8 *)(void*)(&__IPSBAR[0x100011]))
|
||||
#define MCF_GPIO_PDDR_DATAL (*(vuint8 *)(void*)(&__IPSBAR[0x100012]))
|
||||
#define MCF_GPIO_PDDR_BUSCTL (*(vuint8 *)(void*)(&__IPSBAR[0x100013]))
|
||||
#define MCF_GPIO_PDDR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100014]))
|
||||
#define MCF_GPIO_PDDR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100015]))
|
||||
#define MCF_GPIO_PDDR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100016]))
|
||||
#define MCF_GPIO_PDDR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100017]))
|
||||
#define MCF_GPIO_PDDR_UARTH (*(vuint8 *)(void*)(&__IPSBAR[0x100018]))
|
||||
#define MCF_GPIO_PDDR_UARTL (*(vuint8 *)(void*)(&__IPSBAR[0x100019]))
|
||||
#define MCF_GPIO_PDDR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10001A]))
|
||||
#define MCF_GPIO_PDDR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x10001B]))
|
||||
#define MCF_GPIO_PDDR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10001C]))
|
||||
#define MCF_GPIO_PPDSDR_ADDR (*(vuint8 *)(void*)(&__IPSBAR[0x100020]))
|
||||
#define MCF_GPIO_PPDSDR_DATAH (*(vuint8 *)(void*)(&__IPSBAR[0x100021]))
|
||||
#define MCF_GPIO_PPDSDR_DATAL (*(vuint8 *)(void*)(&__IPSBAR[0x100022]))
|
||||
#define MCF_GPIO_PPDSDR_BUSCTL (*(vuint8 *)(void*)(&__IPSBAR[0x100023]))
|
||||
#define MCF_GPIO_PPDSDR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100024]))
|
||||
#define MCF_GPIO_PPDSDR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100027]))
|
||||
#define MCF_GPIO_PPDSDR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100025]))
|
||||
#define MCF_GPIO_PPDSDR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100026]))
|
||||
#define MCF_GPIO_PPDSDR_UARTH (*(vuint8 *)(void*)(&__IPSBAR[0x100028]))
|
||||
#define MCF_GPIO_PPDSDR_UARTL (*(vuint8 *)(void*)(&__IPSBAR[0x100029]))
|
||||
#define MCF_GPIO_PPDSDR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10002A]))
|
||||
#define MCF_GPIO_PPDSDR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x10002B]))
|
||||
#define MCF_GPIO_PPDSDR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10002C]))
|
||||
#define MCF_GPIO_PCLRR_ADDR (*(vuint8 *)(void*)(&__IPSBAR[0x100030]))
|
||||
#define MCF_GPIO_PCLRR_DATAH (*(vuint8 *)(void*)(&__IPSBAR[0x100031]))
|
||||
#define MCF_GPIO_PCLRR_DATAL (*(vuint8 *)(void*)(&__IPSBAR[0x100032]))
|
||||
#define MCF_GPIO_PCLRR_BUSCTL (*(vuint8 *)(void*)(&__IPSBAR[0x100033]))
|
||||
#define MCF_GPIO_PCLRR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100034]))
|
||||
#define MCF_GPIO_PCLRR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100035]))
|
||||
#define MCF_GPIO_PCLRR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100036]))
|
||||
#define MCF_GPIO_PCLRR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100037]))
|
||||
#define MCF_GPIO_PCLRR_UARTH (*(vuint8 *)(void*)(&__IPSBAR[0x100038]))
|
||||
#define MCF_GPIO_PCLRR_UARTL (*(vuint8 *)(void*)(&__IPSBAR[0x100039]))
|
||||
#define MCF_GPIO_PCLRR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10003A]))
|
||||
#define MCF_GPIO_PCLRR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x10003B]))
|
||||
#define MCF_GPIO_PCLRR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10003C]))
|
||||
#define MCF_GPIO_PAR_AD (*(vuint8 *)(void*)(&__IPSBAR[0x100040]))
|
||||
#define MCF_GPIO_PAR_BUSCTL (*(vuint16*)(void*)(&__IPSBAR[0x100042]))
|
||||
#define MCF_GPIO_PAR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100044]))
|
||||
#define MCF_GPIO_PAR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100045]))
|
||||
#define MCF_GPIO_PAR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100046]))
|
||||
#define MCF_GPIO_PAR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100047]))
|
||||
#define MCF_GPIO_PAR_UART (*(vuint16*)(void*)(&__IPSBAR[0x100048]))
|
||||
#define MCF_GPIO_PAR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10004A]))
|
||||
#define MCF_GPIO_PAR_TIMER (*(vuint16*)(void*)(&__IPSBAR[0x10004C]))
|
||||
#define MCF_GPIO_PAR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10004E]))
|
||||
#define MCF_GPIO_DSCR_EIM (*(vuint8 *)(void*)(&__IPSBAR[0x100050]))
|
||||
#define MCF_GPIO_DSCR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x100051]))
|
||||
#define MCF_GPIO_DSCR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100052]))
|
||||
#define MCF_GPIO_DSCR_UART (*(vuint8 *)(void*)(&__IPSBAR[0x100053]))
|
||||
#define MCF_GPIO_DSCR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x100054]))
|
||||
#define MCF_GPIO_DSCR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x100055]))
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_ADDR */
|
||||
#define MCF_GPIO_PODR_ADDR_PODR_ADDR5 (0x20)
|
||||
#define MCF_GPIO_PODR_ADDR_PODR_ADDR6 (0x40)
|
||||
#define MCF_GPIO_PODR_ADDR_PODR_ADDR7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_DATAH */
|
||||
#define MCF_GPIO_PODR_DATAH_PODR_DATAH0 (0x01)
|
||||
#define MCF_GPIO_PODR_DATAH_PODR_DATAH1 (0x02)
|
||||
#define MCF_GPIO_PODR_DATAH_PODR_DATAH2 (0x04)
|
||||
#define MCF_GPIO_PODR_DATAH_PODR_DATAH3 (0x08)
|
||||
#define MCF_GPIO_PODR_DATAH_PODR_DATAH4 (0x10)
|
||||
#define MCF_GPIO_PODR_DATAH_PODR_DATAH5 (0x20)
|
||||
#define MCF_GPIO_PODR_DATAH_PODR_DATAH6 (0x40)
|
||||
#define MCF_GPIO_PODR_DATAH_PODR_DATAH7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_DATAL */
|
||||
#define MCF_GPIO_PODR_DATAL_PODR_DATAL0 (0x01)
|
||||
#define MCF_GPIO_PODR_DATAL_PODR_DATAL1 (0x02)
|
||||
#define MCF_GPIO_PODR_DATAL_PODR_DATAL2 (0x04)
|
||||
#define MCF_GPIO_PODR_DATAL_PODR_DATAL3 (0x08)
|
||||
#define MCF_GPIO_PODR_DATAL_PODR_DATAL4 (0x10)
|
||||
#define MCF_GPIO_PODR_DATAL_PODR_DATAL5 (0x20)
|
||||
#define MCF_GPIO_PODR_DATAL_PODR_DATAL6 (0x40)
|
||||
#define MCF_GPIO_PODR_DATAL_PODR_DATAL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_BUSCTL */
|
||||
#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL0 (0x01)
|
||||
#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL1 (0x02)
|
||||
#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL2 (0x04)
|
||||
#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL3 (0x08)
|
||||
#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL4 (0x10)
|
||||
#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL5 (0x20)
|
||||
#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL6 (0x40)
|
||||
#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_BS */
|
||||
#define MCF_GPIO_PODR_BS_PODR_BS0 (0x01)
|
||||
#define MCF_GPIO_PODR_BS_PODR_BS1 (0x02)
|
||||
#define MCF_GPIO_PODR_BS_PODR_BS2 (0x04)
|
||||
#define MCF_GPIO_PODR_BS_PODR_BS3 (0x08)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_CS */
|
||||
#define MCF_GPIO_PODR_CS_PODR_CS1 (0x02)
|
||||
#define MCF_GPIO_PODR_CS_PODR_CS2 (0x04)
|
||||
#define MCF_GPIO_PODR_CS_PODR_CS3 (0x08)
|
||||
#define MCF_GPIO_PODR_CS_PODR_CS4 (0x10)
|
||||
#define MCF_GPIO_PODR_CS_PODR_CS5 (0x20)
|
||||
#define MCF_GPIO_PODR_CS_PODR_CS6 (0x40)
|
||||
#define MCF_GPIO_PODR_CS_PODR_CS7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_SDRAM */
|
||||
#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM0 (0x01)
|
||||
#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM1 (0x02)
|
||||
#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM2 (0x04)
|
||||
#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM3 (0x08)
|
||||
#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM4 (0x10)
|
||||
#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM5 (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
|
||||
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01)
|
||||
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02)
|
||||
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04)
|
||||
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_UARTH */
|
||||
#define MCF_GPIO_PODR_UARTH_PODR_UARTH0 (0x01)
|
||||
#define MCF_GPIO_PODR_UARTH_PODR_UARTH1 (0x02)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_UARTL */
|
||||
#define MCF_GPIO_PODR_UARTL_PODR_UARTL0 (0x01)
|
||||
#define MCF_GPIO_PODR_UARTL_PODR_UARTL1 (0x02)
|
||||
#define MCF_GPIO_PODR_UARTL_PODR_UARTL2 (0x04)
|
||||
#define MCF_GPIO_PODR_UARTL_PODR_UARTL3 (0x08)
|
||||
#define MCF_GPIO_PODR_UARTL_PODR_UARTL4 (0x10)
|
||||
#define MCF_GPIO_PODR_UARTL_PODR_UARTL5 (0x20)
|
||||
#define MCF_GPIO_PODR_UARTL_PODR_UARTL6 (0x40)
|
||||
#define MCF_GPIO_PODR_UARTL_PODR_UARTL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_QSPI */
|
||||
#define MCF_GPIO_PODR_QSPI_PODR_QSPI0 (0x01)
|
||||
#define MCF_GPIO_PODR_QSPI_PODR_QSPI1 (0x02)
|
||||
#define MCF_GPIO_PODR_QSPI_PODR_QSPI2 (0x04)
|
||||
#define MCF_GPIO_PODR_QSPI_PODR_QSPI3 (0x08)
|
||||
#define MCF_GPIO_PODR_QSPI_PODR_QSPI4 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_TIMER */
|
||||
#define MCF_GPIO_PODR_TIMER_PODR_TIMER0 (0x01)
|
||||
#define MCF_GPIO_PODR_TIMER_PODR_TIMER1 (0x02)
|
||||
#define MCF_GPIO_PODR_TIMER_PODR_TIMER2 (0x04)
|
||||
#define MCF_GPIO_PODR_TIMER_PODR_TIMER3 (0x08)
|
||||
#define MCF_GPIO_PODR_TIMER_PODR_TIMER4 (0x10)
|
||||
#define MCF_GPIO_PODR_TIMER_PODR_TIMER5 (0x20)
|
||||
#define MCF_GPIO_PODR_TIMER_PODR_TIMER6 (0x40)
|
||||
#define MCF_GPIO_PODR_TIMER_PODR_TIMER7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_ETPU */
|
||||
#define MCF_GPIO_PODR_ETPU_PODR_ETPU0 (0x01)
|
||||
#define MCF_GPIO_PODR_ETPU_PODR_ETPU1 (0x02)
|
||||
#define MCF_GPIO_PODR_ETPU_PODR_ETPU2 (0x04)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_APDDR */
|
||||
#define MCF_GPIO_PDDR_APDDR_PDDR_APDDR5 (0x20)
|
||||
#define MCF_GPIO_PDDR_APDDR_PDDR_APDDR6 (0x40)
|
||||
#define MCF_GPIO_PDDR_APDDR_PDDR_APDDR7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_DATAH */
|
||||
#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH0 (0x01)
|
||||
#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH1 (0x02)
|
||||
#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH2 (0x04)
|
||||
#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH3 (0x08)
|
||||
#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH4 (0x10)
|
||||
#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH5 (0x20)
|
||||
#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH6 (0x40)
|
||||
#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_DATAL */
|
||||
#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL0 (0x01)
|
||||
#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL1 (0x02)
|
||||
#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL2 (0x04)
|
||||
#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL3 (0x08)
|
||||
#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL4 (0x10)
|
||||
#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL5 (0x20)
|
||||
#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL6 (0x40)
|
||||
#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_BUSCTL */
|
||||
#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL0 (0x01)
|
||||
#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1 (0x02)
|
||||
#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2 (0x04)
|
||||
#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3 (0x08)
|
||||
#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL4 (0x10)
|
||||
#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL5 (0x20)
|
||||
#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL6 (0x40)
|
||||
#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_BS */
|
||||
#define MCF_GPIO_PDDR_BS_PDDR_BS0 (0x01)
|
||||
#define MCF_GPIO_PDDR_BS_PDDR_BS3(x) (((x)&0x07)<<1)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_CS */
|
||||
#define MCF_GPIO_PDDR_CS_PDDR_CS1 (0x02)
|
||||
#define MCF_GPIO_PDDR_CS_PDDR_CS2 (0x04)
|
||||
#define MCF_GPIO_PDDR_CS_PDDR_CS3 (0x08)
|
||||
#define MCF_GPIO_PDDR_CS_PDDR_CS4 (0x10)
|
||||
#define MCF_GPIO_PDDR_CS_PDDR_CS5 (0x20)
|
||||
#define MCF_GPIO_PDDR_CS_PDDR_CS6 (0x40)
|
||||
#define MCF_GPIO_PDDR_CS_PDDR_CS7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_SDRAM */
|
||||
#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM0 (0x01)
|
||||
#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM1 (0x02)
|
||||
#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM2 (0x04)
|
||||
#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM3 (0x08)
|
||||
#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM4 (0x10)
|
||||
#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM5 (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
|
||||
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01)
|
||||
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02)
|
||||
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04)
|
||||
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_UARTH */
|
||||
#define MCF_GPIO_PDDR_UARTH_PDDR_UARTH0 (0x01)
|
||||
#define MCF_GPIO_PDDR_UARTH_PDDR_UARTH1 (0x02)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_UARTL */
|
||||
#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL0 (0x01)
|
||||
#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL1 (0x02)
|
||||
#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL2 (0x04)
|
||||
#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL3 (0x08)
|
||||
#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL4 (0x10)
|
||||
#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL5 (0x20)
|
||||
#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL6 (0x40)
|
||||
#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_QSPI */
|
||||
#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI0 (0x01)
|
||||
#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI1 (0x02)
|
||||
#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI2 (0x04)
|
||||
#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI3 (0x08)
|
||||
#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI4 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_TIMER */
|
||||
#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER0 (0x01)
|
||||
#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER1 (0x02)
|
||||
#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER2 (0x04)
|
||||
#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER3 (0x08)
|
||||
#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER4 (0x10)
|
||||
#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER5 (0x20)
|
||||
#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER6 (0x40)
|
||||
#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_ETPU */
|
||||
#define MCF_GPIO_PDDR_ETPU_PDDR_ETPU0 (0x01)
|
||||
#define MCF_GPIO_PDDR_ETPU_PDDR_ETPU1 (0x02)
|
||||
#define MCF_GPIO_PDDR_ETPU_PDDR_ETPU2 (0x04)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_ADDR */
|
||||
#define MCF_GPIO_PPDSDR_ADDR_PPDSDR_ADDR5 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_ADDR_PPDSDR_ADDR6 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_ADDR_PPDSDR_ADDR7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_DATAH */
|
||||
#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH0 (0x01)
|
||||
#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH1 (0x02)
|
||||
#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH2 (0x04)
|
||||
#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH3 (0x08)
|
||||
#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH5 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH6 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_DATAL */
|
||||
#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL0 (0x01)
|
||||
#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL1 (0x02)
|
||||
#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL2 (0x04)
|
||||
#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL3 (0x08)
|
||||
#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL5 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL6 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_BUSCTL */
|
||||
#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL0 (0x01)
|
||||
#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL1 (0x02)
|
||||
#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL2 (0x04)
|
||||
#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL3 (0x08)
|
||||
#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL5 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL6 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_BS */
|
||||
#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS0 (0x01)
|
||||
#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS1 (0x02)
|
||||
#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS2 (0x04)
|
||||
#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS3 (0x08)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
|
||||
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01)
|
||||
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02)
|
||||
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04)
|
||||
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_CS */
|
||||
#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS1 (0x02)
|
||||
#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS2 (0x04)
|
||||
#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS3 (0x08)
|
||||
#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS5 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS6 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_SDRAM */
|
||||
#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM0 (0x01)
|
||||
#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM1 (0x02)
|
||||
#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM2 (0x04)
|
||||
#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM3 (0x08)
|
||||
#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM5 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM6 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_UARTH */
|
||||
#define MCF_GPIO_PPDSDR_UARTH_PPDSDR_UARTH0 (0x01)
|
||||
#define MCF_GPIO_PPDSDR_UARTH_PPDSDR_UARTH1 (0x02)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_UARTL */
|
||||
#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL0 (0x01)
|
||||
#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL1 (0x02)
|
||||
#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL2 (0x04)
|
||||
#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL3 (0x08)
|
||||
#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL5 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL6 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_QSPI */
|
||||
#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI0 (0x01)
|
||||
#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI1 (0x02)
|
||||
#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI2 (0x04)
|
||||
#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI3 (0x08)
|
||||
#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI4 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_TIMER */
|
||||
#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER0 (0x01)
|
||||
#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER1 (0x02)
|
||||
#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER2 (0x04)
|
||||
#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER3 (0x08)
|
||||
#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER5 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER6 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_ETPU */
|
||||
#define MCF_GPIO_PPDSDR_ETPU_PPDSDR_ETPU0 (0x01)
|
||||
#define MCF_GPIO_PPDSDR_ETPU_PPDSDR_ETPU1 (0x02)
|
||||
#define MCF_GPIO_PPDSDR_ETPU_PPDSDR_ETPU2 (0x04)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_ADDR */
|
||||
#define MCF_GPIO_PCLRR_ADDR_PCLRR_ADDR5 (0x20)
|
||||
#define MCF_GPIO_PCLRR_ADDR_PCLRR_ADDR6 (0x40)
|
||||
#define MCF_GPIO_PCLRR_ADDR_PCLRR_ADDR7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_DATAH */
|
||||
#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH0 (0x01)
|
||||
#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH1 (0x02)
|
||||
#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH2 (0x04)
|
||||
#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH3 (0x08)
|
||||
#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH5 (0x20)
|
||||
#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH6 (0x40)
|
||||
#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_DATAL */
|
||||
#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL0 (0x01)
|
||||
#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL1 (0x02)
|
||||
#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL2 (0x04)
|
||||
#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL3 (0x08)
|
||||
#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL5 (0x20)
|
||||
#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL6 (0x40)
|
||||
#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_BUSCTL */
|
||||
#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL0 (0x01)
|
||||
#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL1 (0x02)
|
||||
#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL2 (0x04)
|
||||
#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL3 (0x08)
|
||||
#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL5 (0x20)
|
||||
#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL6 (0x40)
|
||||
#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_BS */
|
||||
#define MCF_GPIO_PCLRR_BS_PCLRR_BS0 (0x01)
|
||||
#define MCF_GPIO_PCLRR_BS_PCLRR_BS1 (0x02)
|
||||
#define MCF_GPIO_PCLRR_BS_PCLRR_BS2 (0x04)
|
||||
#define MCF_GPIO_PCLRR_BS_PCLRR_BS3 (0x08)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_CS */
|
||||
#define MCF_GPIO_PCLRR_CS_PCLRR_CS1 (0x02)
|
||||
#define MCF_GPIO_PCLRR_CS_PCLRR_CS2 (0x04)
|
||||
#define MCF_GPIO_PCLRR_CS_PCLRR_CS3 (0x08)
|
||||
#define MCF_GPIO_PCLRR_CS_PCLRR_CS4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_CS_PCLRR_CS5 (0x20)
|
||||
#define MCF_GPIO_PCLRR_CS_PCLRR_CS6 (0x40)
|
||||
#define MCF_GPIO_PCLRR_CS_PCLRR_CS7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_SDRAM */
|
||||
#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM0 (0x01)
|
||||
#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM1 (0x02)
|
||||
#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM2 (0x04)
|
||||
#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM3 (0x08)
|
||||
#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM5 (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
|
||||
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01)
|
||||
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02)
|
||||
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x04)
|
||||
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_UARTH */
|
||||
#define MCF_GPIO_PCLRR_UARTH_PCLRR_UARTH0 (0x01)
|
||||
#define MCF_GPIO_PCLRR_UARTH_PCLRR_UARTH1 (0x02)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_UARTL */
|
||||
#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL0 (0x01)
|
||||
#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL1 (0x02)
|
||||
#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL2 (0x04)
|
||||
#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL3 (0x08)
|
||||
#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL5 (0x20)
|
||||
#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL6 (0x40)
|
||||
#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_QSPI */
|
||||
#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI0 (0x01)
|
||||
#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI1 (0x02)
|
||||
#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI2 (0x04)
|
||||
#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI3 (0x08)
|
||||
#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI4 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_TIMER */
|
||||
#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER0 (0x01)
|
||||
#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER1 (0x02)
|
||||
#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER2 (0x04)
|
||||
#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER3 (0x08)
|
||||
#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER5 (0x20)
|
||||
#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER6 (0x40)
|
||||
#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_ETPU */
|
||||
#define MCF_GPIO_PCLRR_ETPU_PCLRR_ETPU0 (0x01)
|
||||
#define MCF_GPIO_PCLRR_ETPU_PCLRR_ETPU1 (0x02)
|
||||
#define MCF_GPIO_PCLRR_ETPU_PCLRR_ETPU2 (0x04)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PAR_AD */
|
||||
#define MCF_GPIO_PAR_AD_PAR_DATAL (0x01)
|
||||
#define MCF_GPIO_PAR_AD_PAR_ADDR21 (0x20)
|
||||
#define MCF_GPIO_PAR_AD_PAR_ADDR22 (0x40)
|
||||
#define MCF_GPIO_PAR_AD_PAR_ADDR23 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PAR_BUSCTL */
|
||||
#define MCF_GPIO_PAR_BUSCTL_PAR_TIP(x) (((x)&0x0003)<<0)
|
||||
#define MCF_GPIO_PAR_BUSCTL_PAR_TS(x) (((x)&0x0003)<<2)
|
||||
#define MCF_GPIO_PAR_BUSCTL_PAR_TSIZ0 (0x0010)
|
||||
#define MCF_GPIO_PAR_BUSCTL_PAR_TSIZ1 (0x0040)
|
||||
#define MCF_GPIO_PAR_BUSCTL_PAR_RWB (0x0100)
|
||||
#define MCF_GPIO_PAR_BUSCTL_PAR_TEA(x) (((x)&0x0003)<<10)
|
||||
#define MCF_GPIO_PAR_BUSCTL_PAR_TA (0x1000)
|
||||
#define MCF_GPIO_PAR_BUSCTL_PAR_OE (0x4000)
|
||||
#define MCF_GPIO_PAR_BUSCTL_PAR_TEA_GPIO (0x0000)
|
||||
#define MCF_GPIO_PAR_BUSCTL_PAR_TEA_DMA (0x0800)
|
||||
#define MCF_GPIO_PAR_BUSCTL_PAR_TEA_TEA (0x0C00)
|
||||
#define MCF_GPIO_PAR_BUSCTL_PAR_TS_GPIO (0x0000)
|
||||
#define MCF_GPIO_PAR_BUSCTL_PAR_TS_DMA (0x0080)
|
||||
#define MCF_GPIO_PAR_BUSCTL_PAR_TS_TS (0x00C0)
|
||||
#define MCF_GPIO_PAR_BUSCTL_PAR_TIP_GPIO (0x0000)
|
||||
#define MCF_GPIO_PAR_BUSCTL_PAR_TIP_DMA (0x0002)
|
||||
#define MCF_GPIO_PAR_BUSCTL_PAR_TIP_TEA (0x0003)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PAR_BS */
|
||||
#define MCF_GPIO_PAR_BS_PAR_BS0 (0x01)
|
||||
#define MCF_GPIO_PAR_BS_PAR_BS1 (0x02)
|
||||
#define MCF_GPIO_PAR_BS_PAR_BS2 (0x04)
|
||||
#define MCF_GPIO_PAR_BS_PAR_BS3 (0x08)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PAR_CS */
|
||||
#define MCF_GPIO_PAR_CS_PAR_CS1 (0x02)
|
||||
#define MCF_GPIO_PAR_CS_PAR_CS2 (0x04)
|
||||
#define MCF_GPIO_PAR_CS_PAR_CS3 (0x08)
|
||||
#define MCF_GPIO_PAR_CS_PAR_CS4 (0x10)
|
||||
#define MCF_GPIO_PAR_CS_PAR_CS5 (0x20)
|
||||
#define MCF_GPIO_PAR_CS_PAR_CS6 (0x40)
|
||||
#define MCF_GPIO_PAR_CS_PAR_CS7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PAR_SDRAM */
|
||||
#define MCF_GPIO_PAR_SDRAM_PAR_SDCS0 (0x01)
|
||||
#define MCF_GPIO_PAR_SDRAM_PAR_SDCS1 (0x02)
|
||||
#define MCF_GPIO_PAR_SDRAM_PAR_SCKE (0x04)
|
||||
#define MCF_GPIO_PAR_SDRAM_PAR_SRAS (0x08)
|
||||
#define MCF_GPIO_PAR_SDRAM_PAR_SCAS (0x10)
|
||||
#define MCF_GPIO_PAR_SDRAM_PAR_SDWE (0x20)
|
||||
#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PAR_FECI2C */
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x03)<<0)
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x03)<<2)
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO(x) (((x)&0x03)<<4)
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_EMDC(x) (((x)&0x03)<<6)
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_GPIO (0x00)
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_UART2 (0x40)
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_I2C (0x80)
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC (0xC0)
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_GPIO (0x00)
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_UART2 (0x10)
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_I2C (0x20)
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC (0x30)
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_SCL_GPIO (0x00)
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_SCL_FLEX (0x08)
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_SCL_I2C (0x0C)
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_SDA_GPIO (0x00)
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_SDA_FLEX (0x02)
|
||||
#define MCF_GPIO_PAR_FECI2C_PAR_SDA_I2C (0x03)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PAR_UART */
|
||||
#define MCF_GPIO_PAR_UART_PAR_U0RTS (0x0001)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U0CTS (0x0002)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U0TXD (0x0004)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U0RXD (0x0008)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U1RTS(x) (((x)&0x0003)<<4)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U1CTS(x) (((x)&0x0003)<<6)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U1TXD(x) (((x)&0x0003)<<8)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U1RXD(x) (((x)&0x0003)<<10)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U2TXD (0x1000)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U2RXD (0x2000)
|
||||
#define MCF_GPIO_PAR_UART_PAR_CAN1EN (0x4000)
|
||||
#define MCF_GPIO_PAR_UART_PAR_DREQ2 (0x8000)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U1RXD_GPIO (0x0000)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U1RXD_FLEX (0x0800)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U1RXD_UART1 (0x0C00)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U1TXD_GPIO (0x0000)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U1TXD_FLEX (0x0200)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U1TXD_UART1 (0x0300)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U1CTS_GPIO (0x0000)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U1CTS_UART2 (0x0080)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U1CTS_UART1 (0x00C0)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U1RTS_GPIO (0x0000)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U1RTS_UART2 (0x0020)
|
||||
#define MCF_GPIO_PAR_UART_PAR_U1RTS_UART1 (0x0030)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PAR_QSPI */
|
||||
#define MCF_GPIO_PAR_QSPI_PAR_SCK(x) (((x)&0x03)<<0)
|
||||
#define MCF_GPIO_PAR_QSPI_PAR_DOUT (0x04)
|
||||
#define MCF_GPIO_PAR_QSPI_PAR_DIN(x) (((x)&0x03)<<3)
|
||||
#define MCF_GPIO_PAR_QSPI_PAR_PCS0 (0x20)
|
||||
#define MCF_GPIO_PAR_QSPI_PAR_PCS1(x) (((x)&0x03)<<6)
|
||||
#define MCF_GPIO_PAR_QSPI_PAR_PCS1_GPIO (0x00)
|
||||
#define MCF_GPIO_PAR_QSPI_PAR_PCS1_SDRAMC (0x80)
|
||||
#define MCF_GPIO_PAR_QSPI_PAR_PCS1_QSPI (0xC0)
|
||||
#define MCF_GPIO_PAR_QSPI_PAR_DIN_GPIO (0x00)
|
||||
#define MCF_GPIO_PAR_QSPI_PAR_DIN_I2C (0x10)
|
||||
#define MCF_GPIO_PAR_QSPI_PAR_DIN_QSPI (0x1C)
|
||||
#define MCF_GPIO_PAR_QSPI_PAR_SCK_GPIO (0x00)
|
||||
#define MCF_GPIO_PAR_QSPI_PAR_SCK_I2C (0x02)
|
||||
#define MCF_GPIO_PAR_QSPI_PAR_SCK_QSPI (0x03)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T0OUT(x) (((x)&0x0003)<<0)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T1OUT(x) (((x)&0x0003)<<2)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T2OUT(x) (((x)&0x0003)<<4)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T3OUT(x) (((x)&0x0003)<<6)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T0IN(x) (((x)&0x0003)<<8)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T1IN(x) (((x)&0x0003)<<10)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T2IN(x) (((x)&0x0003)<<12)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T3IN(x) (((x)&0x0003)<<14)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T3IN_GPIO (0x0000)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T3IN_QSPI (0x4000)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T3IN_UART2 (0x8000)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T3IN_T3IN (0xC000)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T2IN_GPIO (0x0000)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T2IN_T2OUT (0x1000)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T2IN_DMA (0x2000)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T2IN_T2IN (0x3000)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T1IN_GPIO (0x0000)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T1IN_T1OUT (0x0400)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T1IN_DMA (0x0800)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T1IN_T1IN (0x0C00)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T0IN_GPIO (0x0000)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T0IN_DMA (0x0200)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T0IN_T0IN (0x0300)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_GPIO (0x0000)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_QSPI (0x0040)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_UART2 (0x0080)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_T3OUT (0x00C0)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T2OUT_GPIO (0x0000)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T2OUT_DMA (0x0020)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T2OUT_T2OUT (0x0030)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T1OUT_GPIO (0x0000)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T1OUT_DMA (0x0008)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T1OUT_T1OUT (0x000C)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T0OUT_GPIO (0x0000)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T0OUT_DMA (0x0002)
|
||||
#define MCF_GPIO_PAR_TIMER_PAR_T0OUT_T0OUT (0x0003)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PAR_ETPU */
|
||||
#define MCF_GPIO_PAR_ETPU_PAR_LTPU_ODIS (0x01)
|
||||
#define MCF_GPIO_PAR_ETPU_PAR_UTPU_ODIS (0x02)
|
||||
#define MCF_GPIO_PAR_ETPU_PAR_TCRCLK (0x04)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DSCR_EIM */
|
||||
#define MCF_GPIO_DSCR_EIM_DSCR_EIM0 (0x01)
|
||||
#define MCF_GPIO_DSCR_EIM_DSCR_EIM1 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DSCR_ETPU */
|
||||
#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_7_0 (0x01)
|
||||
#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_15_8 (0x04)
|
||||
#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_23_16 (0x10)
|
||||
#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_31_24 (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DSCR_FECI2C */
|
||||
#define MCF_GPIO_DSCR_FECI2C_DSCR_I2C (0x01)
|
||||
#define MCF_GPIO_DSCR_FECI2C_DSCR_FEC (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DSCR_UART */
|
||||
#define MCF_GPIO_DSCR_UART_DSCR_UART0 (0x01)
|
||||
#define MCF_GPIO_DSCR_UART_DSCR_UART1 (0x04)
|
||||
#define MCF_GPIO_DSCR_UART_DSCR_UART2 (0x10)
|
||||
#define MCF_GPIO_DSCR_UART_DSCR_IRQ (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DSCR_QSPI */
|
||||
#define MCF_GPIO_DSCR_QSPI_DSCR_QSPI (0x01)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DSCR_TIMER */
|
||||
#define MCF_GPIO_DSCR_TIMER_DSCR_TIMER (0x01)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_GPIO_H__ */
|
||||
@ -0,0 +1,63 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_i2c.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_I2C_H__
|
||||
#define __MCF523X_I2C_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* I2C Module (I2C)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_I2C_I2AR (*(vuint8 *)(void*)(&__IPSBAR[0x000300]))
|
||||
#define MCF_I2C_I2FDR (*(vuint8 *)(void*)(&__IPSBAR[0x000304]))
|
||||
#define MCF_I2C_I2CR (*(vuint8 *)(void*)(&__IPSBAR[0x000308]))
|
||||
#define MCF_I2C_I2SR (*(vuint8 *)(void*)(&__IPSBAR[0x00030C]))
|
||||
#define MCF_I2C_I2DR (*(vuint8 *)(void*)(&__IPSBAR[0x000310]))
|
||||
#define MCF_I2C_I2ICR (*(vuint8 *)(void*)(&__IPSBAR[0x000320]))
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2AR */
|
||||
#define MCF_I2C_I2AR_ADR(x) (((x)&0x7F)<<1)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2FDR */
|
||||
#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2CR */
|
||||
#define MCF_I2C_I2CR_RSTA (0x04)
|
||||
#define MCF_I2C_I2CR_TXAK (0x08)
|
||||
#define MCF_I2C_I2CR_MTX (0x10)
|
||||
#define MCF_I2C_I2CR_MSTA (0x20)
|
||||
#define MCF_I2C_I2CR_IIEN (0x40)
|
||||
#define MCF_I2C_I2CR_IEN (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2SR */
|
||||
#define MCF_I2C_I2SR_RXAK (0x01)
|
||||
#define MCF_I2C_I2SR_IIF (0x02)
|
||||
#define MCF_I2C_I2SR_SRW (0x04)
|
||||
#define MCF_I2C_I2SR_IAL (0x10)
|
||||
#define MCF_I2C_I2SR_IBB (0x20)
|
||||
#define MCF_I2C_I2SR_IAAS (0x40)
|
||||
#define MCF_I2C_I2SR_ICF (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2ICR */
|
||||
#define MCF_I2C_I2ICR_IE (0x01)
|
||||
#define MCF_I2C_I2ICR_RE (0x02)
|
||||
#define MCF_I2C_I2ICR_TE (0x04)
|
||||
#define MCF_I2C_I2ICR_BNBE (0x08)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_I2C_H__ */
|
||||
@ -0,0 +1,323 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_intc0.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_INTC0_H__
|
||||
#define __MCF523X_INTC0_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Interrupt Controller 0 (INTC0)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_INTC0_IPRH (*(vuint32*)(void*)(&__IPSBAR[0x000C00]))
|
||||
#define MCF_INTC0_IPRL (*(vuint32*)(void*)(&__IPSBAR[0x000C04]))
|
||||
#define MCF_INTC0_IMRH (*(vuint32*)(void*)(&__IPSBAR[0x000C08]))
|
||||
#define MCF_INTC0_IMRL (*(vuint32*)(void*)(&__IPSBAR[0x000C0C]))
|
||||
#define MCF_INTC0_INTFRCH (*(vuint32*)(void*)(&__IPSBAR[0x000C10]))
|
||||
#define MCF_INTC0_INTFRCL (*(vuint32*)(void*)(&__IPSBAR[0x000C14]))
|
||||
#define MCF_INTC0_IRLR (*(vuint8 *)(void*)(&__IPSBAR[0x000C18]))
|
||||
#define MCF_INTC0_IACKLPR (*(vuint8 *)(void*)(&__IPSBAR[0x000C19]))
|
||||
#define MCF_INTC0_ICR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000C40]))
|
||||
#define MCF_INTC0_ICR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000C41]))
|
||||
#define MCF_INTC0_ICR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000C42]))
|
||||
#define MCF_INTC0_ICR3 (*(vuint8 *)(void*)(&__IPSBAR[0x000C43]))
|
||||
#define MCF_INTC0_ICR4 (*(vuint8 *)(void*)(&__IPSBAR[0x000C44]))
|
||||
#define MCF_INTC0_ICR5 (*(vuint8 *)(void*)(&__IPSBAR[0x000C45]))
|
||||
#define MCF_INTC0_ICR6 (*(vuint8 *)(void*)(&__IPSBAR[0x000C46]))
|
||||
#define MCF_INTC0_ICR7 (*(vuint8 *)(void*)(&__IPSBAR[0x000C47]))
|
||||
#define MCF_INTC0_ICR8 (*(vuint8 *)(void*)(&__IPSBAR[0x000C48]))
|
||||
#define MCF_INTC0_ICR9 (*(vuint8 *)(void*)(&__IPSBAR[0x000C49]))
|
||||
#define MCF_INTC0_ICR10 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4A]))
|
||||
#define MCF_INTC0_ICR11 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4B]))
|
||||
#define MCF_INTC0_ICR12 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4C]))
|
||||
#define MCF_INTC0_ICR13 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4D]))
|
||||
#define MCF_INTC0_ICR14 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4E]))
|
||||
#define MCF_INTC0_ICR15 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4F]))
|
||||
#define MCF_INTC0_ICR16 (*(vuint8 *)(void*)(&__IPSBAR[0x000C50]))
|
||||
#define MCF_INTC0_ICR17 (*(vuint8 *)(void*)(&__IPSBAR[0x000C51]))
|
||||
#define MCF_INTC0_ICR18 (*(vuint8 *)(void*)(&__IPSBAR[0x000C52]))
|
||||
#define MCF_INTC0_ICR19 (*(vuint8 *)(void*)(&__IPSBAR[0x000C53]))
|
||||
#define MCF_INTC0_ICR20 (*(vuint8 *)(void*)(&__IPSBAR[0x000C54]))
|
||||
#define MCF_INTC0_ICR21 (*(vuint8 *)(void*)(&__IPSBAR[0x000C55]))
|
||||
#define MCF_INTC0_ICR22 (*(vuint8 *)(void*)(&__IPSBAR[0x000C56]))
|
||||
#define MCF_INTC0_ICR23 (*(vuint8 *)(void*)(&__IPSBAR[0x000C57]))
|
||||
#define MCF_INTC0_ICR24 (*(vuint8 *)(void*)(&__IPSBAR[0x000C58]))
|
||||
#define MCF_INTC0_ICR25 (*(vuint8 *)(void*)(&__IPSBAR[0x000C59]))
|
||||
#define MCF_INTC0_ICR26 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5A]))
|
||||
#define MCF_INTC0_ICR27 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5B]))
|
||||
#define MCF_INTC0_ICR28 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5C]))
|
||||
#define MCF_INTC0_ICR29 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5D]))
|
||||
#define MCF_INTC0_ICR30 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5E]))
|
||||
#define MCF_INTC0_ICR31 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5F]))
|
||||
#define MCF_INTC0_ICR32 (*(vuint8 *)(void*)(&__IPSBAR[0x000C60]))
|
||||
#define MCF_INTC0_ICR33 (*(vuint8 *)(void*)(&__IPSBAR[0x000C61]))
|
||||
#define MCF_INTC0_ICR34 (*(vuint8 *)(void*)(&__IPSBAR[0x000C62]))
|
||||
#define MCF_INTC0_ICR35 (*(vuint8 *)(void*)(&__IPSBAR[0x000C63]))
|
||||
#define MCF_INTC0_ICR36 (*(vuint8 *)(void*)(&__IPSBAR[0x000C64]))
|
||||
#define MCF_INTC0_ICR37 (*(vuint8 *)(void*)(&__IPSBAR[0x000C65]))
|
||||
#define MCF_INTC0_ICR38 (*(vuint8 *)(void*)(&__IPSBAR[0x000C66]))
|
||||
#define MCF_INTC0_ICR39 (*(vuint8 *)(void*)(&__IPSBAR[0x000C67]))
|
||||
#define MCF_INTC0_ICR40 (*(vuint8 *)(void*)(&__IPSBAR[0x000C68]))
|
||||
#define MCF_INTC0_ICR41 (*(vuint8 *)(void*)(&__IPSBAR[0x000C69]))
|
||||
#define MCF_INTC0_ICR42 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6A]))
|
||||
#define MCF_INTC0_ICR43 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6B]))
|
||||
#define MCF_INTC0_ICR44 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6C]))
|
||||
#define MCF_INTC0_ICR45 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6D]))
|
||||
#define MCF_INTC0_ICR46 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6E]))
|
||||
#define MCF_INTC0_ICR47 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6F]))
|
||||
#define MCF_INTC0_ICR48 (*(vuint8 *)(void*)(&__IPSBAR[0x000C70]))
|
||||
#define MCF_INTC0_ICR49 (*(vuint8 *)(void*)(&__IPSBAR[0x000C71]))
|
||||
#define MCF_INTC0_ICR50 (*(vuint8 *)(void*)(&__IPSBAR[0x000C72]))
|
||||
#define MCF_INTC0_ICR51 (*(vuint8 *)(void*)(&__IPSBAR[0x000C73]))
|
||||
#define MCF_INTC0_ICR52 (*(vuint8 *)(void*)(&__IPSBAR[0x000C74]))
|
||||
#define MCF_INTC0_ICR53 (*(vuint8 *)(void*)(&__IPSBAR[0x000C75]))
|
||||
#define MCF_INTC0_ICR54 (*(vuint8 *)(void*)(&__IPSBAR[0x000C76]))
|
||||
#define MCF_INTC0_ICR55 (*(vuint8 *)(void*)(&__IPSBAR[0x000C77]))
|
||||
#define MCF_INTC0_ICR56 (*(vuint8 *)(void*)(&__IPSBAR[0x000C78]))
|
||||
#define MCF_INTC0_ICR57 (*(vuint8 *)(void*)(&__IPSBAR[0x000C79]))
|
||||
#define MCF_INTC0_ICR58 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7A]))
|
||||
#define MCF_INTC0_ICR59 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7B]))
|
||||
#define MCF_INTC0_ICR60 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7C]))
|
||||
#define MCF_INTC0_ICR61 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7D]))
|
||||
#define MCF_INTC0_ICR62 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7E]))
|
||||
#define MCF_INTC0_ICR63 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7F]))
|
||||
#define MCF_INTC0_ICRn(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000C40+((x)*0x001)]))
|
||||
#define MCF_INTC0_SWIACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CE0]))
|
||||
#define MCF_INTC0_L1IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CE4]))
|
||||
#define MCF_INTC0_L2IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CE8]))
|
||||
#define MCF_INTC0_L3IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CEC]))
|
||||
#define MCF_INTC0_L4IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CF0]))
|
||||
#define MCF_INTC0_L5IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CF4]))
|
||||
#define MCF_INTC0_L6IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CF8]))
|
||||
#define MCF_INTC0_L7IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CFC]))
|
||||
#define MCF_INTC0_LnIACK(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000CE4+((x)*0x004)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_IPRH */
|
||||
#define MCF_INTC0_IPRH_INT32 (0x00000001)
|
||||
#define MCF_INTC0_IPRH_INT33 (0x00000002)
|
||||
#define MCF_INTC0_IPRH_INT34 (0x00000004)
|
||||
#define MCF_INTC0_IPRH_INT35 (0x00000008)
|
||||
#define MCF_INTC0_IPRH_INT36 (0x00000010)
|
||||
#define MCF_INTC0_IPRH_INT37 (0x00000020)
|
||||
#define MCF_INTC0_IPRH_INT38 (0x00000040)
|
||||
#define MCF_INTC0_IPRH_INT39 (0x00000080)
|
||||
#define MCF_INTC0_IPRH_INT40 (0x00000100)
|
||||
#define MCF_INTC0_IPRH_INT41 (0x00000200)
|
||||
#define MCF_INTC0_IPRH_INT42 (0x00000400)
|
||||
#define MCF_INTC0_IPRH_INT43 (0x00000800)
|
||||
#define MCF_INTC0_IPRH_INT44 (0x00001000)
|
||||
#define MCF_INTC0_IPRH_INT45 (0x00002000)
|
||||
#define MCF_INTC0_IPRH_INT46 (0x00004000)
|
||||
#define MCF_INTC0_IPRH_INT47 (0x00008000)
|
||||
#define MCF_INTC0_IPRH_INT48 (0x00010000)
|
||||
#define MCF_INTC0_IPRH_INT49 (0x00020000)
|
||||
#define MCF_INTC0_IPRH_INT50 (0x00040000)
|
||||
#define MCF_INTC0_IPRH_INT51 (0x00080000)
|
||||
#define MCF_INTC0_IPRH_INT52 (0x00100000)
|
||||
#define MCF_INTC0_IPRH_INT53 (0x00200000)
|
||||
#define MCF_INTC0_IPRH_INT54 (0x00400000)
|
||||
#define MCF_INTC0_IPRH_INT55 (0x00800000)
|
||||
#define MCF_INTC0_IPRH_INT56 (0x01000000)
|
||||
#define MCF_INTC0_IPRH_INT57 (0x02000000)
|
||||
#define MCF_INTC0_IPRH_INT58 (0x04000000)
|
||||
#define MCF_INTC0_IPRH_INT59 (0x08000000)
|
||||
#define MCF_INTC0_IPRH_INT60 (0x10000000)
|
||||
#define MCF_INTC0_IPRH_INT61 (0x20000000)
|
||||
#define MCF_INTC0_IPRH_INT62 (0x40000000)
|
||||
#define MCF_INTC0_IPRH_INT63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_IPRL */
|
||||
#define MCF_INTC0_IPRL_INT1 (0x00000002)
|
||||
#define MCF_INTC0_IPRL_INT2 (0x00000004)
|
||||
#define MCF_INTC0_IPRL_INT3 (0x00000008)
|
||||
#define MCF_INTC0_IPRL_INT4 (0x00000010)
|
||||
#define MCF_INTC0_IPRL_INT5 (0x00000020)
|
||||
#define MCF_INTC0_IPRL_INT6 (0x00000040)
|
||||
#define MCF_INTC0_IPRL_INT7 (0x00000080)
|
||||
#define MCF_INTC0_IPRL_INT8 (0x00000100)
|
||||
#define MCF_INTC0_IPRL_INT9 (0x00000200)
|
||||
#define MCF_INTC0_IPRL_INT10 (0x00000400)
|
||||
#define MCF_INTC0_IPRL_INT11 (0x00000800)
|
||||
#define MCF_INTC0_IPRL_INT12 (0x00001000)
|
||||
#define MCF_INTC0_IPRL_INT13 (0x00002000)
|
||||
#define MCF_INTC0_IPRL_INT14 (0x00004000)
|
||||
#define MCF_INTC0_IPRL_INT15 (0x00008000)
|
||||
#define MCF_INTC0_IPRL_INT16 (0x00010000)
|
||||
#define MCF_INTC0_IPRL_INT17 (0x00020000)
|
||||
#define MCF_INTC0_IPRL_INT18 (0x00040000)
|
||||
#define MCF_INTC0_IPRL_INT19 (0x00080000)
|
||||
#define MCF_INTC0_IPRL_INT20 (0x00100000)
|
||||
#define MCF_INTC0_IPRL_INT21 (0x00200000)
|
||||
#define MCF_INTC0_IPRL_INT22 (0x00400000)
|
||||
#define MCF_INTC0_IPRL_INT23 (0x00800000)
|
||||
#define MCF_INTC0_IPRL_INT24 (0x01000000)
|
||||
#define MCF_INTC0_IPRL_INT25 (0x02000000)
|
||||
#define MCF_INTC0_IPRL_INT26 (0x04000000)
|
||||
#define MCF_INTC0_IPRL_INT27 (0x08000000)
|
||||
#define MCF_INTC0_IPRL_INT28 (0x10000000)
|
||||
#define MCF_INTC0_IPRL_INT29 (0x20000000)
|
||||
#define MCF_INTC0_IPRL_INT30 (0x40000000)
|
||||
#define MCF_INTC0_IPRL_INT31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_IMRH */
|
||||
#define MCF_INTC0_IMRH_INT_MASK32 (0x00000001)
|
||||
#define MCF_INTC0_IMRH_INT_MASK33 (0x00000002)
|
||||
#define MCF_INTC0_IMRH_INT_MASK34 (0x00000004)
|
||||
#define MCF_INTC0_IMRH_INT_MASK35 (0x00000008)
|
||||
#define MCF_INTC0_IMRH_INT_MASK36 (0x00000010)
|
||||
#define MCF_INTC0_IMRH_INT_MASK37 (0x00000020)
|
||||
#define MCF_INTC0_IMRH_INT_MASK38 (0x00000040)
|
||||
#define MCF_INTC0_IMRH_INT_MASK39 (0x00000080)
|
||||
#define MCF_INTC0_IMRH_INT_MASK40 (0x00000100)
|
||||
#define MCF_INTC0_IMRH_INT_MASK41 (0x00000200)
|
||||
#define MCF_INTC0_IMRH_INT_MASK42 (0x00000400)
|
||||
#define MCF_INTC0_IMRH_INT_MASK43 (0x00000800)
|
||||
#define MCF_INTC0_IMRH_INT_MASK44 (0x00001000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK45 (0x00002000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK46 (0x00004000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK47 (0x00008000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK48 (0x00010000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK49 (0x00020000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK50 (0x00040000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK51 (0x00080000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK52 (0x00100000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK53 (0x00200000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK54 (0x00400000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK55 (0x00800000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK56 (0x01000000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK57 (0x02000000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK58 (0x04000000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK59 (0x08000000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK60 (0x10000000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK61 (0x20000000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK62 (0x40000000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_IMRL */
|
||||
#define MCF_INTC0_IMRL_MASKALL (0x00000001)
|
||||
#define MCF_INTC0_IMRL_INT_MASK1 (0x00000002)
|
||||
#define MCF_INTC0_IMRL_INT_MASK2 (0x00000004)
|
||||
#define MCF_INTC0_IMRL_INT_MASK3 (0x00000008)
|
||||
#define MCF_INTC0_IMRL_INT_MASK4 (0x00000010)
|
||||
#define MCF_INTC0_IMRL_INT_MASK5 (0x00000020)
|
||||
#define MCF_INTC0_IMRL_INT_MASK6 (0x00000040)
|
||||
#define MCF_INTC0_IMRL_INT_MASK7 (0x00000080)
|
||||
#define MCF_INTC0_IMRL_INT_MASK8 (0x00000100)
|
||||
#define MCF_INTC0_IMRL_INT_MASK9 (0x00000200)
|
||||
#define MCF_INTC0_IMRL_INT_MASK10 (0x00000400)
|
||||
#define MCF_INTC0_IMRL_INT_MASK11 (0x00000800)
|
||||
#define MCF_INTC0_IMRL_INT_MASK12 (0x00001000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK13 (0x00002000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK14 (0x00004000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK15 (0x00008000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK16 (0x00010000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK17 (0x00020000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK18 (0x00040000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK19 (0x00080000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK20 (0x00100000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK21 (0x00200000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK22 (0x00400000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK23 (0x00800000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK24 (0x01000000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK25 (0x02000000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK26 (0x04000000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK27 (0x08000000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK28 (0x10000000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK29 (0x20000000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK30 (0x40000000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_INTFRCH */
|
||||
#define MCF_INTC0_INTFRCH_INTFRC32 (0x00000001)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC33 (0x00000002)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC34 (0x00000004)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC35 (0x00000008)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC36 (0x00000010)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC37 (0x00000020)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC38 (0x00000040)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC39 (0x00000080)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC40 (0x00000100)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC41 (0x00000200)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC42 (0x00000400)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC43 (0x00000800)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC44 (0x00001000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC45 (0x00002000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC46 (0x00004000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC47 (0x00008000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC48 (0x00010000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC49 (0x00020000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC50 (0x00040000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC51 (0x00080000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC52 (0x00100000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC53 (0x00200000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC54 (0x00400000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC55 (0x00800000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC56 (0x01000000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC57 (0x02000000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC58 (0x04000000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC59 (0x08000000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC60 (0x10000000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC61 (0x20000000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC62 (0x40000000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_INTFRCL */
|
||||
#define MCF_INTC0_INTFRCL_INTFRC1 (0x00000002)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC2 (0x00000004)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC3 (0x00000008)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC4 (0x00000010)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC5 (0x00000020)
|
||||
#define MCF_INTC0_INTFRCL_INT6 (0x00000040)
|
||||
#define MCF_INTC0_INTFRCL_INT7 (0x00000080)
|
||||
#define MCF_INTC0_INTFRCL_INT8 (0x00000100)
|
||||
#define MCF_INTC0_INTFRCL_INT9 (0x00000200)
|
||||
#define MCF_INTC0_INTFRCL_INT10 (0x00000400)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC11 (0x00000800)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC12 (0x00001000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC13 (0x00002000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC14 (0x00004000)
|
||||
#define MCF_INTC0_INTFRCL_INT15 (0x00008000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC16 (0x00010000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC17 (0x00020000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC18 (0x00040000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC19 (0x00080000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC20 (0x00100000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC21 (0x00200000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC22 (0x00400000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC23 (0x00800000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC24 (0x01000000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC25 (0x02000000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC26 (0x04000000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC27 (0x08000000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC28 (0x10000000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC29 (0x20000000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC30 (0x40000000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_IRLR */
|
||||
#define MCF_INTC0_IRLR_IRQ(x) (((x)&0x7F)<<1)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_IACKLPR */
|
||||
#define MCF_INTC0_IACKLPR_PRI(x) (((x)&0x0F)<<0)
|
||||
#define MCF_INTC0_IACKLPR_LEVEL(x) (((x)&0x07)<<4)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_ICRn */
|
||||
#define MCF_INTC0_ICRn_IP(x) (((x)&0x07)<<0)
|
||||
#define MCF_INTC0_ICRn_IL(x) (((x)&0x07)<<3)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_INTC0_H__ */
|
||||
@ -0,0 +1,323 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_intc1.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_INTC1_H__
|
||||
#define __MCF523X_INTC1_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Interrupt Controller 1 (INTC1)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_INTC1_IPRH (*(vuint32*)(void*)(&__IPSBAR[0x000D00]))
|
||||
#define MCF_INTC1_IPRL (*(vuint32*)(void*)(&__IPSBAR[0x000D04]))
|
||||
#define MCF_INTC1_IMRH (*(vuint32*)(void*)(&__IPSBAR[0x000D08]))
|
||||
#define MCF_INTC1_IMRL (*(vuint32*)(void*)(&__IPSBAR[0x000D0C]))
|
||||
#define MCF_INTC1_INTFRCH (*(vuint32*)(void*)(&__IPSBAR[0x000D10]))
|
||||
#define MCF_INTC1_INTFRCL (*(vuint32*)(void*)(&__IPSBAR[0x000D14]))
|
||||
#define MCF_INTC1_IRLR (*(vuint8 *)(void*)(&__IPSBAR[0x000D18]))
|
||||
#define MCF_INTC1_IACKLPR (*(vuint8 *)(void*)(&__IPSBAR[0x000D19]))
|
||||
#define MCF_INTC1_ICR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000D40]))
|
||||
#define MCF_INTC1_ICR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000D41]))
|
||||
#define MCF_INTC1_ICR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000D42]))
|
||||
#define MCF_INTC1_ICR3 (*(vuint8 *)(void*)(&__IPSBAR[0x000D43]))
|
||||
#define MCF_INTC1_ICR4 (*(vuint8 *)(void*)(&__IPSBAR[0x000D44]))
|
||||
#define MCF_INTC1_ICR5 (*(vuint8 *)(void*)(&__IPSBAR[0x000D45]))
|
||||
#define MCF_INTC1_ICR6 (*(vuint8 *)(void*)(&__IPSBAR[0x000D46]))
|
||||
#define MCF_INTC1_ICR7 (*(vuint8 *)(void*)(&__IPSBAR[0x000D47]))
|
||||
#define MCF_INTC1_ICR8 (*(vuint8 *)(void*)(&__IPSBAR[0x000D48]))
|
||||
#define MCF_INTC1_ICR9 (*(vuint8 *)(void*)(&__IPSBAR[0x000D49]))
|
||||
#define MCF_INTC1_ICR10 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4A]))
|
||||
#define MCF_INTC1_ICR11 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4B]))
|
||||
#define MCF_INTC1_ICR12 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4C]))
|
||||
#define MCF_INTC1_ICR13 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4D]))
|
||||
#define MCF_INTC1_ICR14 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4E]))
|
||||
#define MCF_INTC1_ICR15 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4F]))
|
||||
#define MCF_INTC1_ICR16 (*(vuint8 *)(void*)(&__IPSBAR[0x000D50]))
|
||||
#define MCF_INTC1_ICR17 (*(vuint8 *)(void*)(&__IPSBAR[0x000D51]))
|
||||
#define MCF_INTC1_ICR18 (*(vuint8 *)(void*)(&__IPSBAR[0x000D52]))
|
||||
#define MCF_INTC1_ICR19 (*(vuint8 *)(void*)(&__IPSBAR[0x000D53]))
|
||||
#define MCF_INTC1_ICR20 (*(vuint8 *)(void*)(&__IPSBAR[0x000D54]))
|
||||
#define MCF_INTC1_ICR21 (*(vuint8 *)(void*)(&__IPSBAR[0x000D55]))
|
||||
#define MCF_INTC1_ICR22 (*(vuint8 *)(void*)(&__IPSBAR[0x000D56]))
|
||||
#define MCF_INTC1_ICR23 (*(vuint8 *)(void*)(&__IPSBAR[0x000D57]))
|
||||
#define MCF_INTC1_ICR24 (*(vuint8 *)(void*)(&__IPSBAR[0x000D58]))
|
||||
#define MCF_INTC1_ICR25 (*(vuint8 *)(void*)(&__IPSBAR[0x000D59]))
|
||||
#define MCF_INTC1_ICR26 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5A]))
|
||||
#define MCF_INTC1_ICR27 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5B]))
|
||||
#define MCF_INTC1_ICR28 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5C]))
|
||||
#define MCF_INTC1_ICR29 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5D]))
|
||||
#define MCF_INTC1_ICR30 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5E]))
|
||||
#define MCF_INTC1_ICR31 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5F]))
|
||||
#define MCF_INTC1_ICR32 (*(vuint8 *)(void*)(&__IPSBAR[0x000D60]))
|
||||
#define MCF_INTC1_ICR33 (*(vuint8 *)(void*)(&__IPSBAR[0x000D61]))
|
||||
#define MCF_INTC1_ICR34 (*(vuint8 *)(void*)(&__IPSBAR[0x000D62]))
|
||||
#define MCF_INTC1_ICR35 (*(vuint8 *)(void*)(&__IPSBAR[0x000D63]))
|
||||
#define MCF_INTC1_ICR36 (*(vuint8 *)(void*)(&__IPSBAR[0x000D64]))
|
||||
#define MCF_INTC1_ICR37 (*(vuint8 *)(void*)(&__IPSBAR[0x000D65]))
|
||||
#define MCF_INTC1_ICR38 (*(vuint8 *)(void*)(&__IPSBAR[0x000D66]))
|
||||
#define MCF_INTC1_ICR39 (*(vuint8 *)(void*)(&__IPSBAR[0x000D67]))
|
||||
#define MCF_INTC1_ICR40 (*(vuint8 *)(void*)(&__IPSBAR[0x000D68]))
|
||||
#define MCF_INTC1_ICR41 (*(vuint8 *)(void*)(&__IPSBAR[0x000D69]))
|
||||
#define MCF_INTC1_ICR42 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6A]))
|
||||
#define MCF_INTC1_ICR43 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6B]))
|
||||
#define MCF_INTC1_ICR44 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6C]))
|
||||
#define MCF_INTC1_ICR45 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6D]))
|
||||
#define MCF_INTC1_ICR46 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6E]))
|
||||
#define MCF_INTC1_ICR47 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6F]))
|
||||
#define MCF_INTC1_ICR48 (*(vuint8 *)(void*)(&__IPSBAR[0x000D70]))
|
||||
#define MCF_INTC1_ICR49 (*(vuint8 *)(void*)(&__IPSBAR[0x000D71]))
|
||||
#define MCF_INTC1_ICR50 (*(vuint8 *)(void*)(&__IPSBAR[0x000D72]))
|
||||
#define MCF_INTC1_ICR51 (*(vuint8 *)(void*)(&__IPSBAR[0x000D73]))
|
||||
#define MCF_INTC1_ICR52 (*(vuint8 *)(void*)(&__IPSBAR[0x000D74]))
|
||||
#define MCF_INTC1_ICR53 (*(vuint8 *)(void*)(&__IPSBAR[0x000D75]))
|
||||
#define MCF_INTC1_ICR54 (*(vuint8 *)(void*)(&__IPSBAR[0x000D76]))
|
||||
#define MCF_INTC1_ICR55 (*(vuint8 *)(void*)(&__IPSBAR[0x000D77]))
|
||||
#define MCF_INTC1_ICR56 (*(vuint8 *)(void*)(&__IPSBAR[0x000D78]))
|
||||
#define MCF_INTC1_ICR57 (*(vuint8 *)(void*)(&__IPSBAR[0x000D79]))
|
||||
#define MCF_INTC1_ICR58 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7A]))
|
||||
#define MCF_INTC1_ICR59 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7B]))
|
||||
#define MCF_INTC1_ICR60 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7C]))
|
||||
#define MCF_INTC1_ICR61 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7D]))
|
||||
#define MCF_INTC1_ICR62 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7E]))
|
||||
#define MCF_INTC1_ICR63 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7F]))
|
||||
#define MCF_INTC1_ICRn(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000D40+((x)*0x001)]))
|
||||
#define MCF_INTC1_SWIACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DE0]))
|
||||
#define MCF_INTC1_L1IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DE4]))
|
||||
#define MCF_INTC1_L2IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DE8]))
|
||||
#define MCF_INTC1_L3IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DEC]))
|
||||
#define MCF_INTC1_L4IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DF0]))
|
||||
#define MCF_INTC1_L5IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DF4]))
|
||||
#define MCF_INTC1_L6IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DF8]))
|
||||
#define MCF_INTC1_L7IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DFC]))
|
||||
#define MCF_INTC1_LnIACK(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000DE4+((x)*0x004)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_IPRH */
|
||||
#define MCF_INTC1_IPRH_INT32 (0x00000001)
|
||||
#define MCF_INTC1_IPRH_INT33 (0x00000002)
|
||||
#define MCF_INTC1_IPRH_INT34 (0x00000004)
|
||||
#define MCF_INTC1_IPRH_INT35 (0x00000008)
|
||||
#define MCF_INTC1_IPRH_INT36 (0x00000010)
|
||||
#define MCF_INTC1_IPRH_INT37 (0x00000020)
|
||||
#define MCF_INTC1_IPRH_INT38 (0x00000040)
|
||||
#define MCF_INTC1_IPRH_INT39 (0x00000080)
|
||||
#define MCF_INTC1_IPRH_INT40 (0x00000100)
|
||||
#define MCF_INTC1_IPRH_INT41 (0x00000200)
|
||||
#define MCF_INTC1_IPRH_INT42 (0x00000400)
|
||||
#define MCF_INTC1_IPRH_INT43 (0x00000800)
|
||||
#define MCF_INTC1_IPRH_INT44 (0x00001000)
|
||||
#define MCF_INTC1_IPRH_INT45 (0x00002000)
|
||||
#define MCF_INTC1_IPRH_INT46 (0x00004000)
|
||||
#define MCF_INTC1_IPRH_INT47 (0x00008000)
|
||||
#define MCF_INTC1_IPRH_INT48 (0x00010000)
|
||||
#define MCF_INTC1_IPRH_INT49 (0x00020000)
|
||||
#define MCF_INTC1_IPRH_INT50 (0x00040000)
|
||||
#define MCF_INTC1_IPRH_INT51 (0x00080000)
|
||||
#define MCF_INTC1_IPRH_INT52 (0x00100000)
|
||||
#define MCF_INTC1_IPRH_INT53 (0x00200000)
|
||||
#define MCF_INTC1_IPRH_INT54 (0x00400000)
|
||||
#define MCF_INTC1_IPRH_INT55 (0x00800000)
|
||||
#define MCF_INTC1_IPRH_INT56 (0x01000000)
|
||||
#define MCF_INTC1_IPRH_INT57 (0x02000000)
|
||||
#define MCF_INTC1_IPRH_INT58 (0x04000000)
|
||||
#define MCF_INTC1_IPRH_INT59 (0x08000000)
|
||||
#define MCF_INTC1_IPRH_INT60 (0x10000000)
|
||||
#define MCF_INTC1_IPRH_INT61 (0x20000000)
|
||||
#define MCF_INTC1_IPRH_INT62 (0x40000000)
|
||||
#define MCF_INTC1_IPRH_INT63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_IPRL */
|
||||
#define MCF_INTC1_IPRL_INT1 (0x00000002)
|
||||
#define MCF_INTC1_IPRL_INT2 (0x00000004)
|
||||
#define MCF_INTC1_IPRL_INT3 (0x00000008)
|
||||
#define MCF_INTC1_IPRL_INT4 (0x00000010)
|
||||
#define MCF_INTC1_IPRL_INT5 (0x00000020)
|
||||
#define MCF_INTC1_IPRL_INT6 (0x00000040)
|
||||
#define MCF_INTC1_IPRL_INT7 (0x00000080)
|
||||
#define MCF_INTC1_IPRL_INT8 (0x00000100)
|
||||
#define MCF_INTC1_IPRL_INT9 (0x00000200)
|
||||
#define MCF_INTC1_IPRL_INT10 (0x00000400)
|
||||
#define MCF_INTC1_IPRL_INT11 (0x00000800)
|
||||
#define MCF_INTC1_IPRL_INT12 (0x00001000)
|
||||
#define MCF_INTC1_IPRL_INT13 (0x00002000)
|
||||
#define MCF_INTC1_IPRL_INT14 (0x00004000)
|
||||
#define MCF_INTC1_IPRL_INT15 (0x00008000)
|
||||
#define MCF_INTC1_IPRL_INT16 (0x00010000)
|
||||
#define MCF_INTC1_IPRL_INT17 (0x00020000)
|
||||
#define MCF_INTC1_IPRL_INT18 (0x00040000)
|
||||
#define MCF_INTC1_IPRL_INT19 (0x00080000)
|
||||
#define MCF_INTC1_IPRL_INT20 (0x00100000)
|
||||
#define MCF_INTC1_IPRL_INT21 (0x00200000)
|
||||
#define MCF_INTC1_IPRL_INT22 (0x00400000)
|
||||
#define MCF_INTC1_IPRL_INT23 (0x00800000)
|
||||
#define MCF_INTC1_IPRL_INT24 (0x01000000)
|
||||
#define MCF_INTC1_IPRL_INT25 (0x02000000)
|
||||
#define MCF_INTC1_IPRL_INT26 (0x04000000)
|
||||
#define MCF_INTC1_IPRL_INT27 (0x08000000)
|
||||
#define MCF_INTC1_IPRL_INT28 (0x10000000)
|
||||
#define MCF_INTC1_IPRL_INT29 (0x20000000)
|
||||
#define MCF_INTC1_IPRL_INT30 (0x40000000)
|
||||
#define MCF_INTC1_IPRL_INT31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_IMRH */
|
||||
#define MCF_INTC1_IMRH_INT_MASK32 (0x00000001)
|
||||
#define MCF_INTC1_IMRH_INT_MASK33 (0x00000002)
|
||||
#define MCF_INTC1_IMRH_INT_MASK34 (0x00000004)
|
||||
#define MCF_INTC1_IMRH_INT_MASK35 (0x00000008)
|
||||
#define MCF_INTC1_IMRH_INT_MASK36 (0x00000010)
|
||||
#define MCF_INTC1_IMRH_INT_MASK37 (0x00000020)
|
||||
#define MCF_INTC1_IMRH_INT_MASK38 (0x00000040)
|
||||
#define MCF_INTC1_IMRH_INT_MASK39 (0x00000080)
|
||||
#define MCF_INTC1_IMRH_INT_MASK40 (0x00000100)
|
||||
#define MCF_INTC1_IMRH_INT_MASK41 (0x00000200)
|
||||
#define MCF_INTC1_IMRH_INT_MASK42 (0x00000400)
|
||||
#define MCF_INTC1_IMRH_INT_MASK43 (0x00000800)
|
||||
#define MCF_INTC1_IMRH_INT_MASK44 (0x00001000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK45 (0x00002000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK46 (0x00004000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK47 (0x00008000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK48 (0x00010000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK49 (0x00020000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK50 (0x00040000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK51 (0x00080000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK52 (0x00100000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK53 (0x00200000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK54 (0x00400000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK55 (0x00800000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK56 (0x01000000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK57 (0x02000000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK58 (0x04000000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK59 (0x08000000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK60 (0x10000000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK61 (0x20000000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK62 (0x40000000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_IMRL */
|
||||
#define MCF_INTC1_IMRL_MASKALL (0x00000001)
|
||||
#define MCF_INTC1_IMRL_INT_MASK1 (0x00000002)
|
||||
#define MCF_INTC1_IMRL_INT_MASK2 (0x00000004)
|
||||
#define MCF_INTC1_IMRL_INT_MASK3 (0x00000008)
|
||||
#define MCF_INTC1_IMRL_INT_MASK4 (0x00000010)
|
||||
#define MCF_INTC1_IMRL_INT_MASK5 (0x00000020)
|
||||
#define MCF_INTC1_IMRL_INT_MASK6 (0x00000040)
|
||||
#define MCF_INTC1_IMRL_INT_MASK7 (0x00000080)
|
||||
#define MCF_INTC1_IMRL_INT_MASK8 (0x00000100)
|
||||
#define MCF_INTC1_IMRL_INT_MASK9 (0x00000200)
|
||||
#define MCF_INTC1_IMRL_INT_MASK10 (0x00000400)
|
||||
#define MCF_INTC1_IMRL_INT_MASK11 (0x00000800)
|
||||
#define MCF_INTC1_IMRL_INT_MASK12 (0x00001000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK13 (0x00002000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK14 (0x00004000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK15 (0x00008000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK16 (0x00010000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK17 (0x00020000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK18 (0x00040000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK19 (0x00080000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK20 (0x00100000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK21 (0x00200000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK22 (0x00400000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK23 (0x00800000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK24 (0x01000000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK25 (0x02000000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK26 (0x04000000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK27 (0x08000000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK28 (0x10000000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK29 (0x20000000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK30 (0x40000000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_INTFRCH */
|
||||
#define MCF_INTC1_INTFRCH_INTFRC32 (0x00000001)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC33 (0x00000002)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC34 (0x00000004)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC35 (0x00000008)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC36 (0x00000010)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC37 (0x00000020)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC38 (0x00000040)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC39 (0x00000080)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC40 (0x00000100)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC41 (0x00000200)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC42 (0x00000400)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC43 (0x00000800)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC44 (0x00001000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC45 (0x00002000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC46 (0x00004000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC47 (0x00008000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC48 (0x00010000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC49 (0x00020000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC50 (0x00040000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC51 (0x00080000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC52 (0x00100000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC53 (0x00200000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC54 (0x00400000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC55 (0x00800000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC56 (0x01000000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC57 (0x02000000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC58 (0x04000000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC59 (0x08000000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC60 (0x10000000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC61 (0x20000000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC62 (0x40000000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_INTFRCL */
|
||||
#define MCF_INTC1_INTFRCL_INTFRC1 (0x00000002)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC2 (0x00000004)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC3 (0x00000008)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC4 (0x00000010)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC5 (0x00000020)
|
||||
#define MCF_INTC1_INTFRCL_INT6 (0x00000040)
|
||||
#define MCF_INTC1_INTFRCL_INT7 (0x00000080)
|
||||
#define MCF_INTC1_INTFRCL_INT8 (0x00000100)
|
||||
#define MCF_INTC1_INTFRCL_INT9 (0x00000200)
|
||||
#define MCF_INTC1_INTFRCL_INT10 (0x00000400)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC11 (0x00000800)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC12 (0x00001000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC13 (0x00002000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC14 (0x00004000)
|
||||
#define MCF_INTC1_INTFRCL_INT15 (0x00008000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC16 (0x00010000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC17 (0x00020000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC18 (0x00040000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC19 (0x00080000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC20 (0x00100000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC21 (0x00200000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC22 (0x00400000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC23 (0x00800000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC24 (0x01000000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC25 (0x02000000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC26 (0x04000000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC27 (0x08000000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC28 (0x10000000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC29 (0x20000000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC30 (0x40000000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_IRLR */
|
||||
#define MCF_INTC1_IRLR_IRQ(x) (((x)&0x7F)<<1)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_IACKLPR */
|
||||
#define MCF_INTC1_IACKLPR_PRI(x) (((x)&0x0F)<<0)
|
||||
#define MCF_INTC1_IACKLPR_LEVEL(x) (((x)&0x07)<<4)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_ICRn */
|
||||
#define MCF_INTC1_ICRn_IP(x) (((x)&0x07)<<0)
|
||||
#define MCF_INTC1_ICRn_IL(x) (((x)&0x07)<<3)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_INTC1_H__ */
|
||||
@ -0,0 +1,101 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_mdha.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_MDHA_H__
|
||||
#define __MCF523X_MDHA_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Message Digest Hardware Accelerator (MDHA)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_MDHA_MDMR (*(vuint32*)(void*)(&__IPSBAR[0x190000]))
|
||||
#define MCF_MDHA_MDCR (*(vuint32*)(void*)(&__IPSBAR[0x190004]))
|
||||
#define MCF_MDHA_MDCMR (*(vuint32*)(void*)(&__IPSBAR[0x190008]))
|
||||
#define MCF_MDHA_MDSR (*(vuint32*)(void*)(&__IPSBAR[0x19000C]))
|
||||
#define MCF_MDHA_MDISR (*(vuint32*)(void*)(&__IPSBAR[0x190010]))
|
||||
#define MCF_MDHA_MDIMR (*(vuint32*)(void*)(&__IPSBAR[0x190014]))
|
||||
#define MCF_MDHA_MDDSR (*(vuint32*)(void*)(&__IPSBAR[0x19001C]))
|
||||
#define MCF_MDHA_MDIN (*(vuint32*)(void*)(&__IPSBAR[0x190020]))
|
||||
#define MCF_MDHA_MDA0 (*(vuint32*)(void*)(&__IPSBAR[0x190030]))
|
||||
#define MCF_MDHA_MDB0 (*(vuint32*)(void*)(&__IPSBAR[0x190034]))
|
||||
#define MCF_MDHA_MDC0 (*(vuint32*)(void*)(&__IPSBAR[0x190038]))
|
||||
#define MCF_MDHA_MDD0 (*(vuint32*)(void*)(&__IPSBAR[0x19003C]))
|
||||
#define MCF_MDHA_MDE0 (*(vuint32*)(void*)(&__IPSBAR[0x190040]))
|
||||
#define MCF_MDHA_MDMDS (*(vuint32*)(void*)(&__IPSBAR[0x190044]))
|
||||
#define MCF_MDHA_MDA1 (*(vuint32*)(void*)(&__IPSBAR[0x190070]))
|
||||
#define MCF_MDHA_MDB1 (*(vuint32*)(void*)(&__IPSBAR[0x190074]))
|
||||
#define MCF_MDHA_MDC1 (*(vuint32*)(void*)(&__IPSBAR[0x190078]))
|
||||
#define MCF_MDHA_MDD1 (*(vuint32*)(void*)(&__IPSBAR[0x19007C]))
|
||||
#define MCF_MDHA_MDE1 (*(vuint32*)(void*)(&__IPSBAR[0x190080]))
|
||||
|
||||
/* Bit definitions and macros for MCF_MDHA_MDMR */
|
||||
#define MCF_MDHA_MDMR_ALG (0x00000001)
|
||||
#define MCF_MDHA_MDMR_PDATA (0x00000004)
|
||||
#define MCF_MDHA_MDMR_MAC(x) (((x)&0x00000003)<<3)
|
||||
#define MCF_MDHA_MDMR_INIT (0x00000020)
|
||||
#define MCF_MDHA_MDMR_IPAD (0x00000040)
|
||||
#define MCF_MDHA_MDMR_OPAD (0x00000080)
|
||||
#define MCF_MDHA_MDMR_SWAP (0x00000100)
|
||||
#define MCF_MDHA_MDMR_MACFULL (0x00000200)
|
||||
#define MCF_MDHA_MDMR_SSL (0x00000400)
|
||||
|
||||
/* Bit definitions and macros for MCF_MDHA_MDCR */
|
||||
#define MCF_MDHA_MDCR_IE (0x00000001)
|
||||
|
||||
/* Bit definitions and macros for MCF_MDHA_MDCMR */
|
||||
#define MCF_MDHA_MDCMR_SWR (0x00000001)
|
||||
#define MCF_MDHA_MDCMR_RI (0x00000002)
|
||||
#define MCF_MDHA_MDCMR_CI (0x00000004)
|
||||
#define MCF_MDHA_MDCMR_GO (0x00000008)
|
||||
|
||||
/* Bit definitions and macros for MCF_MDHA_MDSR */
|
||||
#define MCF_MDHA_MDSR_INT (0x00000001)
|
||||
#define MCF_MDHA_MDSR_DONE (0x00000002)
|
||||
#define MCF_MDHA_MDSR_ERR (0x00000004)
|
||||
#define MCF_MDHA_MDSR_RD (0x00000008)
|
||||
#define MCF_MDHA_MDSR_BUSY (0x00000010)
|
||||
#define MCF_MDHA_MDSR_END (0x00000020)
|
||||
#define MCF_MDHA_MDSR_HSH (0x00000040)
|
||||
#define MCF_MDHA_MDSR_GNW (0x00000080)
|
||||
#define MCF_MDHA_MDSR_FS(x) (((x)&0x00000007)<<8)
|
||||
#define MCF_MDHA_MDSR_APD(x) (((x)&0x00000007)<<13)
|
||||
#define MCF_MDHA_MDSR_IFL(x) (((x)&0x000000FF)<<16)
|
||||
|
||||
/* Bit definitions and macros for MCF_MDHA_MDIR */
|
||||
#define MCF_MDHA_MDIR_IFO (0x00000001)
|
||||
#define MCF_MDHA_MDIR_NON (0x00000004)
|
||||
#define MCF_MDHA_MDIR_IME (0x00000010)
|
||||
#define MCF_MDHA_MDIR_IDS (0x00000020)
|
||||
#define MCF_MDHA_MDIR_RMDP (0x00000080)
|
||||
#define MCF_MDHA_MDIR_ERE (0x00000100)
|
||||
#define MCF_MDHA_MDIR_GTDS (0x00000200)
|
||||
|
||||
/* Bit definitions and macros for MCF_MDHA_MDIMR */
|
||||
#define MCF_MDHA_MDIMR_IFO (0x00000001)
|
||||
#define MCF_MDHA_MDIMR_NON (0x00000004)
|
||||
#define MCF_MDHA_MDIMR_IME (0x00000010)
|
||||
#define MCF_MDHA_MDIMR_IDS (0x00000020)
|
||||
#define MCF_MDHA_MDIMR_RMDP (0x00000080)
|
||||
#define MCF_MDHA_MDIMR_ERE (0x00000100)
|
||||
#define MCF_MDHA_MDIMR_GTDS (0x00000200)
|
||||
|
||||
/* Bit definitions and macros for MCF_MDHA_MDDSR */
|
||||
#define MCF_MDHA_MDDSR_DATASIZE(x) (((x)&0x1FFFFFFF)<<0)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_MDHA_H__ */
|
||||
@ -0,0 +1,89 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_pit.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_PIT_H__
|
||||
#define __MCF523X_PIT_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Programmable Interrupt Timer Modules (PIT)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_PIT_PCSR0 (*(vuint16*)(void*)(&__IPSBAR[0x150000]))
|
||||
#define MCF_PIT_PMR0 (*(vuint16*)(void*)(&__IPSBAR[0x150002]))
|
||||
#define MCF_PIT_PCNTR0 (*(vuint16*)(void*)(&__IPSBAR[0x150004]))
|
||||
#define MCF_PIT_PCSR1 (*(vuint16*)(void*)(&__IPSBAR[0x160000]))
|
||||
#define MCF_PIT_PMR1 (*(vuint16*)(void*)(&__IPSBAR[0x160002]))
|
||||
#define MCF_PIT_PCNTR1 (*(vuint16*)(void*)(&__IPSBAR[0x160004]))
|
||||
#define MCF_PIT_PCSR2 (*(vuint16*)(void*)(&__IPSBAR[0x170000]))
|
||||
#define MCF_PIT_PMR2 (*(vuint16*)(void*)(&__IPSBAR[0x170002]))
|
||||
#define MCF_PIT_PCNTR2 (*(vuint16*)(void*)(&__IPSBAR[0x170004]))
|
||||
#define MCF_PIT_PCSR3 (*(vuint16*)(void*)(&__IPSBAR[0x180000]))
|
||||
#define MCF_PIT_PMR3 (*(vuint16*)(void*)(&__IPSBAR[0x180002]))
|
||||
#define MCF_PIT_PCNTR3 (*(vuint16*)(void*)(&__IPSBAR[0x180004]))
|
||||
#define MCF_PIT_PCSR(x) (*(vuint16*)(void*)(&__IPSBAR[0x150000+((x)*0x10000)]))
|
||||
#define MCF_PIT_PMR(x) (*(vuint16*)(void*)(&__IPSBAR[0x150002+((x)*0x10000)]))
|
||||
#define MCF_PIT_PCNTR(x) (*(vuint16*)(void*)(&__IPSBAR[0x150004+((x)*0x10000)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_PIT_PCSR */
|
||||
#define MCF_PIT_PCSR_EN (0x0001)
|
||||
#define MCF_PIT_PCSR_RLD (0x0002)
|
||||
#define MCF_PIT_PCSR_PIF (0x0004)
|
||||
#define MCF_PIT_PCSR_PIE (0x0008)
|
||||
#define MCF_PIT_PCSR_OVW (0x0010)
|
||||
#define MCF_PIT_PCSR_HALTED (0x0020)
|
||||
#define MCF_PIT_PCSR_DOZE (0x0040)
|
||||
#define MCF_PIT_PCSR_PRE(x) (((x)&0x000F)<<8)
|
||||
|
||||
/* Bit definitions and macros for MCF_PIT_PMR */
|
||||
#define MCF_PIT_PMR_PM0 (0x0001)
|
||||
#define MCF_PIT_PMR_PM1 (0x0002)
|
||||
#define MCF_PIT_PMR_PM2 (0x0004)
|
||||
#define MCF_PIT_PMR_PM3 (0x0008)
|
||||
#define MCF_PIT_PMR_PM4 (0x0010)
|
||||
#define MCF_PIT_PMR_PM5 (0x0020)
|
||||
#define MCF_PIT_PMR_PM6 (0x0040)
|
||||
#define MCF_PIT_PMR_PM7 (0x0080)
|
||||
#define MCF_PIT_PMR_PM8 (0x0100)
|
||||
#define MCF_PIT_PMR_PM9 (0x0200)
|
||||
#define MCF_PIT_PMR_PM10 (0x0400)
|
||||
#define MCF_PIT_PMR_PM11 (0x0800)
|
||||
#define MCF_PIT_PMR_PM12 (0x1000)
|
||||
#define MCF_PIT_PMR_PM13 (0x2000)
|
||||
#define MCF_PIT_PMR_PM14 (0x4000)
|
||||
#define MCF_PIT_PMR_PM15 (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PIT_PCNTR */
|
||||
#define MCF_PIT_PCNTR_PC0 (0x0001)
|
||||
#define MCF_PIT_PCNTR_PC1 (0x0002)
|
||||
#define MCF_PIT_PCNTR_PC2 (0x0004)
|
||||
#define MCF_PIT_PCNTR_PC3 (0x0008)
|
||||
#define MCF_PIT_PCNTR_PC4 (0x0010)
|
||||
#define MCF_PIT_PCNTR_PC5 (0x0020)
|
||||
#define MCF_PIT_PCNTR_PC6 (0x0040)
|
||||
#define MCF_PIT_PCNTR_PC7 (0x0080)
|
||||
#define MCF_PIT_PCNTR_PC8 (0x0100)
|
||||
#define MCF_PIT_PCNTR_PC9 (0x0200)
|
||||
#define MCF_PIT_PCNTR_PC10 (0x0400)
|
||||
#define MCF_PIT_PCNTR_PC11 (0x0800)
|
||||
#define MCF_PIT_PCNTR_PC12 (0x1000)
|
||||
#define MCF_PIT_PCNTR_PC13 (0x2000)
|
||||
#define MCF_PIT_PCNTR_PC14 (0x4000)
|
||||
#define MCF_PIT_PCNTR_PC15 (0x8000)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_PIT_H__ */
|
||||
@ -0,0 +1,69 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_qspi.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_QSPI_H__
|
||||
#define __MCF523X_QSPI_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Queued Serial Peripheral Interface (QSPI)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_QSPI_QMR (*(vuint16*)(void*)(&__IPSBAR[0x000340]))
|
||||
#define MCF_QSPI_QDLYR (*(vuint16*)(void*)(&__IPSBAR[0x000344]))
|
||||
#define MCF_QSPI_QWR (*(vuint16*)(void*)(&__IPSBAR[0x000348]))
|
||||
#define MCF_QSPI_QIR (*(vuint16*)(void*)(&__IPSBAR[0x00034C]))
|
||||
#define MCF_QSPI_QAR (*(vuint16*)(void*)(&__IPSBAR[0x000350]))
|
||||
#define MCF_QSPI_QDR (*(vuint16*)(void*)(&__IPSBAR[0x000354]))
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QMR */
|
||||
#define MCF_QSPI_QMR_BAUD(x) (((x)&0x00FF)<<0)
|
||||
#define MCF_QSPI_QMR_CPHA (0x0100)
|
||||
#define MCF_QSPI_QMR_CPOL (0x0200)
|
||||
#define MCF_QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
|
||||
#define MCF_QSPI_QMR_DOHIE (0x4000)
|
||||
#define MCF_QSPI_QMR_MSTR (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QDLYR */
|
||||
#define MCF_QSPI_QDLYR_DTL(x) (((x)&0x00FF)<<0)
|
||||
#define MCF_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
|
||||
#define MCF_QSPI_QDLYR_SPE (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QWR */
|
||||
#define MCF_QSPI_QWR_NEWQP(x) (((x)&0x000F)<<0)
|
||||
#define MCF_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
|
||||
#define MCF_QSPI_QWR_CSIV (0x1000)
|
||||
#define MCF_QSPI_QWR_WRTO (0x2000)
|
||||
#define MCF_QSPI_QWR_WREN (0x4000)
|
||||
#define MCF_QSPI_QWR_HALT (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QIR */
|
||||
#define MCF_QSPI_QIR_SPIF (0x0001)
|
||||
#define MCF_QSPI_QIR_ABRT (0x0004)
|
||||
#define MCF_QSPI_QIR_WCEF (0x0008)
|
||||
#define MCF_QSPI_QIR_SPIFE (0x0100)
|
||||
#define MCF_QSPI_QIR_ABRTE (0x0400)
|
||||
#define MCF_QSPI_QIR_WCEFE (0x0800)
|
||||
#define MCF_QSPI_QIR_ABRTL (0x1000)
|
||||
#define MCF_QSPI_QIR_ABRTB (0x4000)
|
||||
#define MCF_QSPI_QIR_WCEFB (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QAR */
|
||||
#define MCF_QSPI_QAR_ADDR(x) (((x)&0x003F)<<0)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_QSPI_H__ */
|
||||
@ -0,0 +1,42 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_rcm.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_RCM_H__
|
||||
#define __MCF523X_RCM_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Reset Configuration Module (RCM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_RCM_RCR (*(vuint8 *)(void*)(&__IPSBAR[0x110000]))
|
||||
#define MCF_RCM_RSR (*(vuint8 *)(void*)(&__IPSBAR[0x110001]))
|
||||
|
||||
/* Bit definitions and macros for MCF_RCM_RCR */
|
||||
#define MCF_RCM_RCR_FRCRSTOUT (0x40)
|
||||
#define MCF_RCM_RCR_SOFTRST (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_RCM_RSR */
|
||||
#define MCF_RCM_RSR_LOL (0x01)
|
||||
#define MCF_RCM_RSR_LOC (0x02)
|
||||
#define MCF_RCM_RSR_EXT (0x04)
|
||||
#define MCF_RCM_RSR_POR (0x08)
|
||||
#define MCF_RCM_RSR_WDR (0x10)
|
||||
#define MCF_RCM_RSR_SOFT (0x20)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_RCM_H__ */
|
||||
@ -0,0 +1,46 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_rng.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_RNG_H__
|
||||
#define __MCF523X_RNG_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Random Number Generator (RNG)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_RNG_RNGCR (*(vuint32*)(void*)(&__IPSBAR[0x1A0000]))
|
||||
#define MCF_RNG_RNGSR (*(vuint32*)(void*)(&__IPSBAR[0x1A0004]))
|
||||
#define MCF_RNG_RNGER (*(vuint32*)(void*)(&__IPSBAR[0x1A0008]))
|
||||
#define MCF_RNG_RNGOUT (*(vuint32*)(void*)(&__IPSBAR[0x1A000C]))
|
||||
|
||||
/* Bit definitions and macros for MCF_RNG_RNGCR */
|
||||
#define MCF_RNG_RNGCR_GO (0x00000001)
|
||||
#define MCF_RNG_RNGCR_HA (0x00000002)
|
||||
#define MCF_RNG_RNGCR_IM (0x00000004)
|
||||
#define MCF_RNG_RNGCR_CI (0x00000008)
|
||||
|
||||
/* Bit definitions and macros for MCF_RNG_RNGSR */
|
||||
#define MCF_RNG_RNGSR_SV (0x00000001)
|
||||
#define MCF_RNG_RNGSR_LRS (0x00000002)
|
||||
#define MCF_RNG_RNGSR_FUF (0x00000004)
|
||||
#define MCF_RNG_RNGSR_EI (0x00000008)
|
||||
#define MCF_RNG_RNGSR_OFL(x) (((x)&0x000000FF)<<8)
|
||||
#define MCF_RNG_RNGSR_OFS(x) (((x)&0x000000FF)<<16)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_RNG_H__ */
|
||||
@ -0,0 +1,150 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_scm.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_SCM_H__
|
||||
#define __MCF523X_SCM_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* System Control Module (SCM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_SCM_IPSBAR (*(vuint32*)(void*)(&__IPSBAR[0x000000]))
|
||||
#define MCF_SCM_RAMBAR (*(vuint32*)(void*)(&__IPSBAR[0x000008]))
|
||||
#define MCF_SCM_CRSR (*(vuint8 *)(void*)(&__IPSBAR[0x000010]))
|
||||
#define MCF_SCM_CWCR (*(vuint8 *)(void*)(&__IPSBAR[0x000011]))
|
||||
#define MCF_SCM_LPICR (*(vuint8 *)(void*)(&__IPSBAR[0x000012]))
|
||||
#define MCF_SCM_CWSR (*(vuint8 *)(void*)(&__IPSBAR[0x000013]))
|
||||
#define MCF_SCM_DMAREQC (*(vuint32*)(void*)(&__IPSBAR[0x000014]))
|
||||
#define MCF_SCM_MPARK (*(vuint32*)(void*)(&__IPSBAR[0x00001C]))
|
||||
#define MCF_SCM_MPR (*(vuint8 *)(void*)(&__IPSBAR[0x000020]))
|
||||
#define MCF_SCM_PACR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000024]))
|
||||
#define MCF_SCM_PACR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000025]))
|
||||
#define MCF_SCM_PACR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000026]))
|
||||
#define MCF_SCM_PACR3 (*(vuint8 *)(void*)(&__IPSBAR[0x000027]))
|
||||
#define MCF_SCM_PACR4 (*(vuint8 *)(void*)(&__IPSBAR[0x000028]))
|
||||
#define MCF_SCM_PACR5 (*(vuint8 *)(void*)(&__IPSBAR[0x00002A]))
|
||||
#define MCF_SCM_PACR6 (*(vuint8 *)(void*)(&__IPSBAR[0x00002B]))
|
||||
#define MCF_SCM_PACR7 (*(vuint8 *)(void*)(&__IPSBAR[0x00002C]))
|
||||
#define MCF_SCM_PACR8 (*(vuint8 *)(void*)(&__IPSBAR[0x00002E]))
|
||||
#define MCF_SCM_GPACR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000030]))
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_IPSBAR */
|
||||
#define MCF_SCM_IPSBAR_V (0x00000001)
|
||||
#define MCF_SCM_IPSBAR_BA(x) (((x)&0x00000003)<<30)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_RAMBAR */
|
||||
#define MCF_SCM_RAMBAR_BDE (0x00000200)
|
||||
#define MCF_SCM_RAMBAR_BA(x) (((x)&0x0000FFFF)<<16)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_CRSR */
|
||||
#define MCF_SCM_CRSR_CWDR (0x20)
|
||||
#define MCF_SCM_CRSR_EXT (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_CWCR */
|
||||
#define MCF_SCM_CWCR_CWTIC (0x01)
|
||||
#define MCF_SCM_CWCR_CWTAVAL (0x02)
|
||||
#define MCF_SCM_CWCR_CWTA (0x04)
|
||||
#define MCF_SCM_CWCR_CWT(x) (((x)&0x07)<<3)
|
||||
#define MCF_SCM_CWCR_CWRI (0x40)
|
||||
#define MCF_SCM_CWCR_CWE (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_LPICR */
|
||||
#define MCF_SCM_LPICR_XLPM_IPL(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_LPICR_ENBSTOP (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_DMAREQC */
|
||||
#define MCF_SCM_DMAREQC_DMAC0(x) (((x)&0x0000000F)<<0)
|
||||
#define MCF_SCM_DMAREQC_DMAC1(x) (((x)&0x0000000F)<<4)
|
||||
#define MCF_SCM_DMAREQC_DMAC2(x) (((x)&0x0000000F)<<8)
|
||||
#define MCF_SCM_DMAREQC_DMAC3(x) (((x)&0x0000000F)<<12)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_MPARK */
|
||||
#define MCF_SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0000000F)<<8)
|
||||
#define MCF_SCM_MPARK_PRKLAST (0x00001000)
|
||||
#define MCF_SCM_MPARK_TIMEOUT (0x00002000)
|
||||
#define MCF_SCM_MPARK_FIXED (0x00004000)
|
||||
#define MCF_SCM_MPARK_M1_PRTY(x) (((x)&0x00000003)<<16)
|
||||
#define MCF_SCM_MPARK_M0_PRTY(x) (((x)&0x00000003)<<18)
|
||||
#define MCF_SCM_MPARK_M2_PRTY(x) (((x)&0x00000003)<<20)
|
||||
#define MCF_SCM_MPARK_M3_PRTY(x) (((x)&0x00000003)<<22)
|
||||
#define MCF_SCM_MPARK_BCR24BIT (0x01000000)
|
||||
#define MCF_SCM_MPARK_M2_P_EN (0x02000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_MPR */
|
||||
#define MCF_SCM_MPR_MPR(x) (((x)&0x0F)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR0 */
|
||||
#define MCF_SCM_PACR0_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR0_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR0_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR0_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR1 */
|
||||
#define MCF_SCM_PACR1_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR1_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR1_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR1_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR2 */
|
||||
#define MCF_SCM_PACR2_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR2_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR2_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR2_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR3 */
|
||||
#define MCF_SCM_PACR3_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR3_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR3_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR3_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR4 */
|
||||
#define MCF_SCM_PACR4_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR4_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR4_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR4_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR5 */
|
||||
#define MCF_SCM_PACR5_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR5_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR5_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR5_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR6 */
|
||||
#define MCF_SCM_PACR6_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR6_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR6_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR6_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR7 */
|
||||
#define MCF_SCM_PACR7_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR7_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR7_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR7_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR8 */
|
||||
#define MCF_SCM_PACR8_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR8_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR8_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR8_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_GPACR0 */
|
||||
#define MCF_SCM_GPACR0_ACCESS_CTRL(x) (((x)&0x0F)<<0)
|
||||
#define MCF_SCM_GPACR0_LOCK (0x80)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_SCM_H__ */
|
||||
@ -0,0 +1,94 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_sdramc.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_SDRAMC_H__
|
||||
#define __MCF523X_SDRAMC_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* SDRAM Controller (SDRAMC)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_SDRAMC_DCR (*(vuint16*)(void*)(&__IPSBAR[0x000040]))
|
||||
#define MCF_SDRAMC_DACR0 (*(vuint32*)(void*)(&__IPSBAR[0x000048]))
|
||||
#define MCF_SDRAMC_DMR0 (*(vuint32*)(void*)(&__IPSBAR[0x00004C]))
|
||||
#define MCF_SDRAMC_DACR1 (*(vuint32*)(void*)(&__IPSBAR[0x000050]))
|
||||
#define MCF_SDRAMC_DMR1 (*(vuint32*)(void*)(&__IPSBAR[0x000054]))
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_DCR */
|
||||
#define MCF_SDRAMC_DCR_RC(x) (((x)&0x01FF)<<0)
|
||||
#define MCF_SDRAMC_DCR_RTIM(x) (((x)&0x0003)<<9)
|
||||
#define MCF_SDRAMC_DCR_IS (0x0800)
|
||||
#define MCF_SDRAMC_DCR_COC (0x1000)
|
||||
#define MCF_SDRAMC_DCR_NAM (0x2000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_DACR0 */
|
||||
#define MCF_SDRAMC_DACR0_IP (0x00000008)
|
||||
#define MCF_SDRAMC_DACR0_PS(x) (((x)&0x00000003)<<4)
|
||||
#define MCF_SDRAMC_DACR0_MRS (0x00000040)
|
||||
#define MCF_SDRAMC_DACR0_CBM(x) (((x)&0x00000007)<<8)
|
||||
#define MCF_SDRAMC_DACR0_CASL(x) (((x)&0x00000003)<<12)
|
||||
#define MCF_SDRAMC_DACR0_RE (0x00008000)
|
||||
#define MCF_SDRAMC_DACR0_BA(x) (((x)&0x00003FFF)<<18)
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_DMR0 */
|
||||
#define MCF_SDRAMC_DMR0_V (0x00000001)
|
||||
#define MCF_SDRAMC_DMR0_WP (0x00000100)
|
||||
#define MCF_SDRAMC_DMR0_BAM(x) (((x)&0x00003FFF)<<18)
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_DACR1 */
|
||||
#define MCF_SDRAMC_DACR1_IP (0x00000008)
|
||||
#define MCF_SDRAMC_DACR1_PS(x) (((x)&0x00000003)<<4)
|
||||
#define MCF_SDRAMC_DACR1_MRS (0x00000040)
|
||||
#define MCF_SDRAMC_DACR1_CBM(x) (((x)&0x00000007)<<8)
|
||||
#define MCF_SDRAMC_DACR1_CASL(x) (((x)&0x00000003)<<12)
|
||||
#define MCF_SDRAMC_DACR1_RE (0x00008000)
|
||||
#define MCF_SDRAMC_DACR1_BA(x) (((x)&0x00003FFF)<<18)
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_DMR1 */
|
||||
#define MCF_SDRAMC_DMR1_V (0x00000001)
|
||||
#define MCF_SDRAMC_DMR1_WP (0x00000100)
|
||||
#define MCF_SDRAMC_DMR1_BAM(x) (((x)&0x00003FFF)<<18)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#define MCF_SDRAMC_DMR_BAM_4G (0xFFFC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_2G (0x7FFC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_1G (0x3FFC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_1024M (0x3FFC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_512M (0x1FFC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_256M (0x0FFC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_128M (0x07FC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_64M (0x03FC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_32M (0x01FC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_16M (0x00FC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_8M (0x007C0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_4M (0x003C0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_2M (0x001C0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_1M (0x000C0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_1024K (0x000C0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_512K (0x00040000)
|
||||
#define MCF_SDRAMC_DMR_BAM_256K (0x00000000)
|
||||
#define MCF_SDRAMC_DMR_WP (0x00000100)
|
||||
#define MCF_SDRAMC_DMR_CI (0x00000040)
|
||||
#define MCF_SDRAMC_DMR_AM (0x00000020)
|
||||
#define MCF_SDRAMC_DMR_SC (0x00000010)
|
||||
#define MCF_SDRAMC_DMR_SD (0x00000008)
|
||||
#define MCF_SDRAMC_DMR_UC (0x00000004)
|
||||
#define MCF_SDRAMC_DMR_UD (0x00000002)
|
||||
#define MCF_SDRAMC_DMR_V (0x00000001)
|
||||
|
||||
#endif /* __MCF523X_SDRAMC_H__ */
|
||||
@ -0,0 +1,120 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_skha.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_SKHA_H__
|
||||
#define __MCF523X_SKHA_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Symmetric Key Hardware Accelerator (SKHA)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_SKHA_SKMR (*(vuint32*)(void*)(&__IPSBAR[0x1B0000]))
|
||||
#define MCF_SKHA_SKCR (*(vuint32*)(void*)(&__IPSBAR[0x1B0004]))
|
||||
#define MCF_SKHA_SKCMR (*(vuint32*)(void*)(&__IPSBAR[0x1B0008]))
|
||||
#define MCF_SKHA_SKSR (*(vuint32*)(void*)(&__IPSBAR[0x1B000C]))
|
||||
#define MCF_SKHA_SKIR (*(vuint32*)(void*)(&__IPSBAR[0x1B0010]))
|
||||
#define MCF_SKHA_SKIMR (*(vuint32*)(void*)(&__IPSBAR[0x1B0014]))
|
||||
#define MCF_SKHA_SKKSR (*(vuint32*)(void*)(&__IPSBAR[0x1B0018]))
|
||||
#define MCF_SKHA_SKDSR (*(vuint32*)(void*)(&__IPSBAR[0x1B001C]))
|
||||
#define MCF_SKHA_SKIN (*(vuint32*)(void*)(&__IPSBAR[0x1B0020]))
|
||||
#define MCF_SKHA_SKOUT (*(vuint32*)(void*)(&__IPSBAR[0x1B0024]))
|
||||
#define MCF_SKHA_SKKDR0 (*(vuint32*)(void*)(&__IPSBAR[0x1B0030]))
|
||||
#define MCF_SKHA_SKKDR1 (*(vuint32*)(void*)(&__IPSBAR[0x1B0034]))
|
||||
#define MCF_SKHA_SKKDR2 (*(vuint32*)(void*)(&__IPSBAR[0x1B0038]))
|
||||
#define MCF_SKHA_SKKDR3 (*(vuint32*)(void*)(&__IPSBAR[0x1B003C]))
|
||||
#define MCF_SKHA_SKKDR4 (*(vuint32*)(void*)(&__IPSBAR[0x1B0040]))
|
||||
#define MCF_SKHA_SKKDR5 (*(vuint32*)(void*)(&__IPSBAR[0x1B0044]))
|
||||
#define MCF_SKHA_SKKDRn(x) (*(vuint32*)(void*)(&__IPSBAR[0x1B0030+((x)*0x004)]))
|
||||
#define MCF_SKHA_SKCR0 (*(vuint32*)(void*)(&__IPSBAR[0x1B0070]))
|
||||
#define MCF_SKHA_SKCR1 (*(vuint32*)(void*)(&__IPSBAR[0x1B0074]))
|
||||
#define MCF_SKHA_SKCR2 (*(vuint32*)(void*)(&__IPSBAR[0x1B0078]))
|
||||
#define MCF_SKHA_SKCR3 (*(vuint32*)(void*)(&__IPSBAR[0x1B007C]))
|
||||
#define MCF_SKHA_SKCR4 (*(vuint32*)(void*)(&__IPSBAR[0x1B0080]))
|
||||
#define MCF_SKHA_SKCR5 (*(vuint32*)(void*)(&__IPSBAR[0x1B0084]))
|
||||
#define MCF_SKHA_SKCR6 (*(vuint32*)(void*)(&__IPSBAR[0x1B0088]))
|
||||
#define MCF_SKHA_SKCR7 (*(vuint32*)(void*)(&__IPSBAR[0x1B008C]))
|
||||
#define MCF_SKHA_SKCR8 (*(vuint32*)(void*)(&__IPSBAR[0x1B0090]))
|
||||
#define MCF_SKHA_SKCR9 (*(vuint32*)(void*)(&__IPSBAR[0x1B0094]))
|
||||
#define MCF_SKHA_SKCR10 (*(vuint32*)(void*)(&__IPSBAR[0x1B0098]))
|
||||
#define MCF_SKHA_SKCR11 (*(vuint32*)(void*)(&__IPSBAR[0x1B009C]))
|
||||
#define MCF_SKHA_SKCRn(x) (*(vuint32*)(void*)(&__IPSBAR[0x1B0070+((x)*0x004)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_SKHA_SKMR */
|
||||
#define MCF_SKHA_SKMR_ALG(x) (((x)&0x00000003)<<0)
|
||||
#define MCF_SKHA_SKMR_DIR (0x00000004)
|
||||
#define MCF_SKHA_SKMR_CM(x) (((x)&0x00000003)<<3)
|
||||
#define MCF_SKHA_SKMR_DKP (0x00000100)
|
||||
#define MCF_SKHA_SKMR_CTRM(x) (((x)&0x0000000F)<<9)
|
||||
#define MCF_SKHA_SKMR_CM_ECB (0x00000000)
|
||||
#define MCF_SKHA_SKMR_CM_CBC (0x00000008)
|
||||
#define MCF_SKHA_SKMR_CM_CTR (0x00000018)
|
||||
#define MCF_SKHA_SKMR_DIR_DEC (0x00000000)
|
||||
#define MCF_SKHA_SKMR_DIR_ENC (0x00000004)
|
||||
#define MCF_SKHA_SKMR_ALG_AES (0x00000000)
|
||||
#define MCF_SKHA_SKMR_ALG_DES (0x00000001)
|
||||
#define MCF_SKHA_SKMR_ALG_TDES (0x00000002)
|
||||
|
||||
/* Bit definitions and macros for MCF_SKHA_SKCR */
|
||||
#define MCF_SKHA_SKCR_IE (0x00000001)
|
||||
|
||||
/* Bit definitions and macros for MCF_SKHA_SKCMR */
|
||||
#define MCF_SKHA_SKCMR_SWR (0x00000001)
|
||||
#define MCF_SKHA_SKCMR_RI (0x00000002)
|
||||
#define MCF_SKHA_SKCMR_CI (0x00000004)
|
||||
#define MCF_SKHA_SKCMR_GO (0x00000008)
|
||||
|
||||
/* Bit definitions and macros for MCF_SKHA_SKSR */
|
||||
#define MCF_SKHA_SKSR_INT (0x00000001)
|
||||
#define MCF_SKHA_SKSR_DONE (0x00000002)
|
||||
#define MCF_SKHA_SKSR_ERR (0x00000004)
|
||||
#define MCF_SKHA_SKSR_RD (0x00000008)
|
||||
#define MCF_SKHA_SKSR_BUSY (0x00000010)
|
||||
#define MCF_SKHA_SKSR_IFL(x) (((x)&0x000000FF)<<16)
|
||||
#define MCF_SKHA_SKSR_OFL(x) (((x)&0x000000FF)<<24)
|
||||
|
||||
/* Bit definitions and macros for MCF_SKHA_SKIR */
|
||||
#define MCF_SKHA_SKIR_IFO (0x00000001)
|
||||
#define MCF_SKHA_SKIR_OFU (0x00000002)
|
||||
#define MCF_SKHA_SKIR_NEIF (0x00000004)
|
||||
#define MCF_SKHA_SKIR_NEOF (0x00000008)
|
||||
#define MCF_SKHA_SKIR_IME (0x00000010)
|
||||
#define MCF_SKHA_SKIR_DSE (0x00000020)
|
||||
#define MCF_SKHA_SKIR_KSE (0x00000040)
|
||||
#define MCF_SKHA_SKIR_RMDP (0x00000080)
|
||||
#define MCF_SKHA_SKIR_ERE (0x00000100)
|
||||
#define MCF_SKHA_SKIR_KPE (0x00000200)
|
||||
#define MCF_SKHA_SKIR_KRE (0x00000400)
|
||||
|
||||
/* Bit definitions and macros for MCF_SKHA_SKIMR */
|
||||
#define MCF_SKHA_SKIMR_IFO (0x00000001)
|
||||
#define MCF_SKHA_SKIMR_OFU (0x00000002)
|
||||
#define MCF_SKHA_SKIMR_NEIF (0x00000004)
|
||||
#define MCF_SKHA_SKIMR_NEOF (0x00000008)
|
||||
#define MCF_SKHA_SKIMR_IME (0x00000010)
|
||||
#define MCF_SKHA_SKIMR_DSE (0x00000020)
|
||||
#define MCF_SKHA_SKIMR_KSE (0x00000040)
|
||||
#define MCF_SKHA_SKIMR_RMDP (0x00000080)
|
||||
#define MCF_SKHA_SKIMR_ERE (0x00000100)
|
||||
#define MCF_SKHA_SKIMR_KPE (0x00000200)
|
||||
#define MCF_SKHA_SKIMR_KRE (0x00000400)
|
||||
|
||||
/* Bit definitions and macros for MCF_SKHA_SKKSR */
|
||||
#define MCF_SKHA_SKKSR_KEYSIZE(x) (((x)&0x0000003F)<<0)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_SKHA_H__ */
|
||||
@ -0,0 +1,42 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_sram.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_SRAM_H__
|
||||
#define __MCF523X_SRAM_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* 64KByte System SRAM (SRAM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_SRAM_RAMBAR (*(vuint32*)(void*)(&__IPSBAR[0x20000000]))
|
||||
|
||||
/* Bit definitions and macros for MCF_SRAM_RAMBAR */
|
||||
#define MCF_SRAM_RAMBAR_V (0x00000001)
|
||||
#define MCF_SRAM_RAMBAR_UD (0x00000002)
|
||||
#define MCF_SRAM_RAMBAR_UC (0x00000004)
|
||||
#define MCF_SRAM_RAMBAR_SD (0x00000008)
|
||||
#define MCF_SRAM_RAMBAR_SC (0x00000010)
|
||||
#define MCF_SRAM_RAMBAR_CI (0x00000020)
|
||||
#define MCF_SRAM_RAMBAR_WP (0x00000100)
|
||||
#define MCF_SRAM_RAMBAR_SPV (0x00000200)
|
||||
#define MCF_SRAM_RAMBAR_PRI2 (0x00000400)
|
||||
#define MCF_SRAM_RAMBAR_PRI1 (0x00000800)
|
||||
#define MCF_SRAM_RAMBAR_BA(x) (((x)&0x0000FFFF)<<16)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_SRAM_H__ */
|
||||
@ -0,0 +1,83 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_timer.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_TIMER_H__
|
||||
#define __MCF523X_TIMER_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* DMA Timers (TIMER)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_TIMER_DTMR0 (*(vuint16*)(void*)(&__IPSBAR[0x000400]))
|
||||
#define MCF_TIMER_DTXMR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000402]))
|
||||
#define MCF_TIMER_DTER0 (*(vuint8 *)(void*)(&__IPSBAR[0x000403]))
|
||||
#define MCF_TIMER_DTRR0 (*(vuint32*)(void*)(&__IPSBAR[0x000404]))
|
||||
#define MCF_TIMER_DTCR0 (*(vuint32*)(void*)(&__IPSBAR[0x000408]))
|
||||
#define MCF_TIMER_DTCN0 (*(vuint32*)(void*)(&__IPSBAR[0x00040C]))
|
||||
#define MCF_TIMER_DTMR1 (*(vuint16*)(void*)(&__IPSBAR[0x000440]))
|
||||
#define MCF_TIMER_DTXMR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000442]))
|
||||
#define MCF_TIMER_DTER1 (*(vuint8 *)(void*)(&__IPSBAR[0x000443]))
|
||||
#define MCF_TIMER_DTRR1 (*(vuint32*)(void*)(&__IPSBAR[0x000444]))
|
||||
#define MCF_TIMER_DTCR1 (*(vuint32*)(void*)(&__IPSBAR[0x000448]))
|
||||
#define MCF_TIMER_DTCN1 (*(vuint32*)(void*)(&__IPSBAR[0x00044C]))
|
||||
#define MCF_TIMER_DTMR2 (*(vuint16*)(void*)(&__IPSBAR[0x000480]))
|
||||
#define MCF_TIMER_DTXMR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000482]))
|
||||
#define MCF_TIMER_DTER2 (*(vuint8 *)(void*)(&__IPSBAR[0x000483]))
|
||||
#define MCF_TIMER_DTRR2 (*(vuint32*)(void*)(&__IPSBAR[0x000484]))
|
||||
#define MCF_TIMER_DTCR2 (*(vuint32*)(void*)(&__IPSBAR[0x000488]))
|
||||
#define MCF_TIMER_DTCN2 (*(vuint32*)(void*)(&__IPSBAR[0x00048C]))
|
||||
#define MCF_TIMER_DTMR3 (*(vuint16*)(void*)(&__IPSBAR[0x0004C0]))
|
||||
#define MCF_TIMER_DTXMR3 (*(vuint8 *)(void*)(&__IPSBAR[0x0004C2]))
|
||||
#define MCF_TIMER_DTER3 (*(vuint8 *)(void*)(&__IPSBAR[0x0004C3]))
|
||||
#define MCF_TIMER_DTRR3 (*(vuint32*)(void*)(&__IPSBAR[0x0004C4]))
|
||||
#define MCF_TIMER_DTCR3 (*(vuint32*)(void*)(&__IPSBAR[0x0004C8]))
|
||||
#define MCF_TIMER_DTCN3 (*(vuint32*)(void*)(&__IPSBAR[0x0004CC]))
|
||||
#define MCF_TIMER_DTMR(x) (*(vuint16*)(void*)(&__IPSBAR[0x000400+((x)*0x040)]))
|
||||
#define MCF_TIMER_DTXMR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000402+((x)*0x040)]))
|
||||
#define MCF_TIMER_DTER(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000403+((x)*0x040)]))
|
||||
#define MCF_TIMER_DTRR(x) (*(vuint32*)(void*)(&__IPSBAR[0x000404+((x)*0x040)]))
|
||||
#define MCF_TIMER_DTCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x000408+((x)*0x040)]))
|
||||
#define MCF_TIMER_DTCN(x) (*(vuint32*)(void*)(&__IPSBAR[0x00040C+((x)*0x040)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_TIMER_DTMR */
|
||||
#define MCF_TIMER_DTMR_RST (0x0001)
|
||||
#define MCF_TIMER_DTMR_CLK(x) (((x)&0x0003)<<1)
|
||||
#define MCF_TIMER_DTMR_FRR (0x0008)
|
||||
#define MCF_TIMER_DTMR_ORRI (0x0010)
|
||||
#define MCF_TIMER_DTMR_OM (0x0020)
|
||||
#define MCF_TIMER_DTMR_CE(x) (((x)&0x0003)<<6)
|
||||
#define MCF_TIMER_DTMR_PS(x) (((x)&0x00FF)<<8)
|
||||
#define MCF_TIMER_DTMR_CE_ANY (0x00C0)
|
||||
#define MCF_TIMER_DTMR_CE_FALL (0x0080)
|
||||
#define MCF_TIMER_DTMR_CE_RISE (0x0040)
|
||||
#define MCF_TIMER_DTMR_CE_NONE (0x0000)
|
||||
#define MCF_TIMER_DTMR_CLK_DTIN (0x0006)
|
||||
#define MCF_TIMER_DTMR_CLK_DIV16 (0x0004)
|
||||
#define MCF_TIMER_DTMR_CLK_DIV1 (0x0002)
|
||||
#define MCF_TIMER_DTMR_CLK_STOP (0x0000)
|
||||
|
||||
/* Bit definitions and macros for MCF_TIMER_DTXMR */
|
||||
#define MCF_TIMER_DTXMR_MODE16 (0x01)
|
||||
#define MCF_TIMER_DTXMR_DMAEN (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_TIMER_DTER */
|
||||
#define MCF_TIMER_DTER_CAP (0x01)
|
||||
#define MCF_TIMER_DTER_REF (0x02)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_TIMER_H__ */
|
||||
@ -0,0 +1,186 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_uart.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_UART_H__
|
||||
#define __MCF523X_UART_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Universal Asynchronous Receiver Transmitter (UART)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_UART_UMR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000200]))
|
||||
#define MCF_UART_USR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000204]))
|
||||
#define MCF_UART_UCSR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000204]))
|
||||
#define MCF_UART_UCR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000208]))
|
||||
#define MCF_UART_URB0 (*(vuint8 *)(void*)(&__IPSBAR[0x00020C]))
|
||||
#define MCF_UART_UTB0 (*(vuint8 *)(void*)(&__IPSBAR[0x00020C]))
|
||||
#define MCF_UART_UIPCR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000210]))
|
||||
#define MCF_UART_UACR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000210]))
|
||||
#define MCF_UART_UISR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000214]))
|
||||
#define MCF_UART_UIMR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000214]))
|
||||
#define MCF_UART_UBG10 (*(vuint8 *)(void*)(&__IPSBAR[0x000218]))
|
||||
#define MCF_UART_UBG20 (*(vuint8 *)(void*)(&__IPSBAR[0x00021C]))
|
||||
#define MCF_UART_UIP0 (*(vuint8 *)(void*)(&__IPSBAR[0x000234]))
|
||||
#define MCF_UART_UOP10 (*(vuint8 *)(void*)(&__IPSBAR[0x000238]))
|
||||
#define MCF_UART_UOP00 (*(vuint8 *)(void*)(&__IPSBAR[0x00023C]))
|
||||
#define MCF_UART_UMR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000240]))
|
||||
#define MCF_UART_USR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000244]))
|
||||
#define MCF_UART_UCSR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000244]))
|
||||
#define MCF_UART_UCR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000248]))
|
||||
#define MCF_UART_URB1 (*(vuint8 *)(void*)(&__IPSBAR[0x00024C]))
|
||||
#define MCF_UART_UTB1 (*(vuint8 *)(void*)(&__IPSBAR[0x00024C]))
|
||||
#define MCF_UART_UIPCR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000250]))
|
||||
#define MCF_UART_UACR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000250]))
|
||||
#define MCF_UART_UISR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000254]))
|
||||
#define MCF_UART_UIMR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000254]))
|
||||
#define MCF_UART_UBG11 (*(vuint8 *)(void*)(&__IPSBAR[0x000258]))
|
||||
#define MCF_UART_UBG21 (*(vuint8 *)(void*)(&__IPSBAR[0x00025C]))
|
||||
#define MCF_UART_UIP1 (*(vuint8 *)(void*)(&__IPSBAR[0x000274]))
|
||||
#define MCF_UART_UOP11 (*(vuint8 *)(void*)(&__IPSBAR[0x000278]))
|
||||
#define MCF_UART_UOP01 (*(vuint8 *)(void*)(&__IPSBAR[0x00027C]))
|
||||
#define MCF_UART_UMR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000280]))
|
||||
#define MCF_UART_USR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000284]))
|
||||
#define MCF_UART_UCSR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000284]))
|
||||
#define MCF_UART_UCR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000288]))
|
||||
#define MCF_UART_URB2 (*(vuint8 *)(void*)(&__IPSBAR[0x00028C]))
|
||||
#define MCF_UART_UTB2 (*(vuint8 *)(void*)(&__IPSBAR[0x00028C]))
|
||||
#define MCF_UART_UIPCR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000290]))
|
||||
#define MCF_UART_UACR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000290]))
|
||||
#define MCF_UART_UISR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000294]))
|
||||
#define MCF_UART_UIMR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000294]))
|
||||
#define MCF_UART_UBG12 (*(vuint8 *)(void*)(&__IPSBAR[0x000298]))
|
||||
#define MCF_UART_UBG22 (*(vuint8 *)(void*)(&__IPSBAR[0x00029C]))
|
||||
#define MCF_UART_UIP2 (*(vuint8 *)(void*)(&__IPSBAR[0x0002B4]))
|
||||
#define MCF_UART_UOP12 (*(vuint8 *)(void*)(&__IPSBAR[0x0002B8]))
|
||||
#define MCF_UART_UOP02 (*(vuint8 *)(void*)(&__IPSBAR[0x0002BC]))
|
||||
#define MCF_UART_UMR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000200+((x)*0x040)]))
|
||||
#define MCF_UART_USR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000204+((x)*0x040)]))
|
||||
#define MCF_UART_UCSR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000204+((x)*0x040)]))
|
||||
#define MCF_UART_UCR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000208+((x)*0x040)]))
|
||||
#define MCF_UART_URB(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00020C+((x)*0x040)]))
|
||||
#define MCF_UART_UTB(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00020C+((x)*0x040)]))
|
||||
#define MCF_UART_UIPCR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000210+((x)*0x040)]))
|
||||
#define MCF_UART_UACR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000210+((x)*0x040)]))
|
||||
#define MCF_UART_UISR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000214+((x)*0x040)]))
|
||||
#define MCF_UART_UIMR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000214+((x)*0x040)]))
|
||||
#define MCF_UART_UBG1(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000218+((x)*0x040)]))
|
||||
#define MCF_UART_UBG2(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00021C+((x)*0x040)]))
|
||||
#define MCF_UART_UIP(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000234+((x)*0x040)]))
|
||||
#define MCF_UART_UOP1(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000238+((x)*0x040)]))
|
||||
#define MCF_UART_UOP0(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00023C+((x)*0x040)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UMR */
|
||||
#define MCF_UART_UMR_BC(x) (((x)&0x03)<<0)
|
||||
#define MCF_UART_UMR_PT (0x04)
|
||||
#define MCF_UART_UMR_PM(x) (((x)&0x03)<<3)
|
||||
#define MCF_UART_UMR_ERR (0x20)
|
||||
#define MCF_UART_UMR_RXIRQ (0x40)
|
||||
#define MCF_UART_UMR_RXRTS (0x80)
|
||||
#define MCF_UART_UMR_SB(x) (((x)&0x0F)<<0)
|
||||
#define MCF_UART_UMR_TXCTS (0x10)
|
||||
#define MCF_UART_UMR_TXRTS (0x20)
|
||||
#define MCF_UART_UMR_CM(x) (((x)&0x03)<<6)
|
||||
#define MCF_UART_UMR_PM_MULTI_ADDR (0x1C)
|
||||
#define MCF_UART_UMR_PM_MULTI_DATA (0x18)
|
||||
#define MCF_UART_UMR_PM_NONE (0x10)
|
||||
#define MCF_UART_UMR_PM_FORCE_HI (0x0C)
|
||||
#define MCF_UART_UMR_PM_FORCE_LO (0x08)
|
||||
#define MCF_UART_UMR_PM_ODD (0x04)
|
||||
#define MCF_UART_UMR_PM_EVEN (0x00)
|
||||
#define MCF_UART_UMR_BC_5 (0x00)
|
||||
#define MCF_UART_UMR_BC_6 (0x01)
|
||||
#define MCF_UART_UMR_BC_7 (0x02)
|
||||
#define MCF_UART_UMR_BC_8 (0x03)
|
||||
#define MCF_UART_UMR_CM_NORMAL (0x00)
|
||||
#define MCF_UART_UMR_CM_ECHO (0x40)
|
||||
#define MCF_UART_UMR_CM_LOCAL_LOOP (0x80)
|
||||
#define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0)
|
||||
#define MCF_UART_UMR_SB_STOP_BITS_1 (0x07)
|
||||
#define MCF_UART_UMR_SB_STOP_BITS_15 (0x08)
|
||||
#define MCF_UART_UMR_SB_STOP_BITS_2 (0x0F)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_USR */
|
||||
#define MCF_UART_USR_RXRDY (0x01)
|
||||
#define MCF_UART_USR_FFULL (0x02)
|
||||
#define MCF_UART_USR_TXRDY (0x04)
|
||||
#define MCF_UART_USR_TXEMP (0x08)
|
||||
#define MCF_UART_USR_OE (0x10)
|
||||
#define MCF_UART_USR_PE (0x20)
|
||||
#define MCF_UART_USR_FE (0x40)
|
||||
#define MCF_UART_USR_RB (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UCSR */
|
||||
#define MCF_UART_UCSR_TCS(x) (((x)&0x0F)<<0)
|
||||
#define MCF_UART_UCSR_RCS(x) (((x)&0x0F)<<4)
|
||||
#define MCF_UART_UCSR_RCS_SYS_CLK (0xD0)
|
||||
#define MCF_UART_UCSR_RCS_CTM16 (0xE0)
|
||||
#define MCF_UART_UCSR_RCS_CTM (0xF0)
|
||||
#define MCF_UART_UCSR_TCS_SYS_CLK (0x0D)
|
||||
#define MCF_UART_UCSR_TCS_CTM16 (0x0E)
|
||||
#define MCF_UART_UCSR_TCS_CTM (0x0F)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UCR */
|
||||
#define MCF_UART_UCR_RXC(x) (((x)&0x03)<<0)
|
||||
#define MCF_UART_UCR_TXC(x) (((x)&0x03)<<2)
|
||||
#define MCF_UART_UCR_MISC(x) (((x)&0x07)<<4)
|
||||
#define MCF_UART_UCR_NONE (0x00)
|
||||
#define MCF_UART_UCR_STOP_BREAK (0x70)
|
||||
#define MCF_UART_UCR_START_BREAK (0x60)
|
||||
#define MCF_UART_UCR_BKCHGINT (0x50)
|
||||
#define MCF_UART_UCR_RESET_ERROR (0x40)
|
||||
#define MCF_UART_UCR_RESET_TX (0x30)
|
||||
#define MCF_UART_UCR_RESET_RX (0x20)
|
||||
#define MCF_UART_UCR_RESET_MR (0x10)
|
||||
#define MCF_UART_UCR_TX_DISABLED (0x08)
|
||||
#define MCF_UART_UCR_TX_ENABLED (0x04)
|
||||
#define MCF_UART_UCR_RX_DISABLED (0x02)
|
||||
#define MCF_UART_UCR_RX_ENABLED (0x01)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UIPCR */
|
||||
#define MCF_UART_UIPCR_CTS (0x01)
|
||||
#define MCF_UART_UIPCR_COS (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UACR */
|
||||
#define MCF_UART_UACR_IEC (0x01)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UISR */
|
||||
#define MCF_UART_UISR_TXRDY (0x01)
|
||||
#define MCF_UART_UISR_RXRDY_FU (0x02)
|
||||
#define MCF_UART_UISR_DB (0x04)
|
||||
#define MCF_UART_UISR_RXFTO (0x08)
|
||||
#define MCF_UART_UISR_TXFIFO (0x10)
|
||||
#define MCF_UART_UISR_RXFIFO (0x20)
|
||||
#define MCF_UART_UISR_COS (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UIMR */
|
||||
#define MCF_UART_UIMR_TXRDY (0x01)
|
||||
#define MCF_UART_UIMR_RXRDY_FU (0x02)
|
||||
#define MCF_UART_UIMR_DB (0x04)
|
||||
#define MCF_UART_UIMR_COS (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UIP */
|
||||
#define MCF_UART_UIP_CTS (0x01)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UOP1 */
|
||||
#define MCF_UART_UOP1_RTS (0x01)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UOP0 */
|
||||
#define MCF_UART_UOP0_RTS (0x01)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_UART_H__ */
|
||||
@ -0,0 +1,92 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_wtm.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_WTM_H__
|
||||
#define __MCF523X_WTM_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Watchdog Timer Modules (WTM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_WTM_WCR (*(vuint16*)(void*)(&__IPSBAR[0x140000]))
|
||||
#define MCF_WTM_WMR (*(vuint16*)(void*)(&__IPSBAR[0x140002]))
|
||||
#define MCF_WTM_WCNTR (*(vuint16*)(void*)(&__IPSBAR[0x140004]))
|
||||
#define MCF_WTM_WSR (*(vuint16*)(void*)(&__IPSBAR[0x140006]))
|
||||
|
||||
/* Bit definitions and macros for MCF_WTM_WCR */
|
||||
#define MCF_WTM_WCR_EN (0x0001)
|
||||
#define MCF_WTM_WCR_HALTED (0x0002)
|
||||
#define MCF_WTM_WCR_DOZE (0x0004)
|
||||
#define MCF_WTM_WCR_WAIT (0x0008)
|
||||
|
||||
/* Bit definitions and macros for MCF_WTM_WMR */
|
||||
#define MCF_WTM_WMR_WM0 (0x0001)
|
||||
#define MCF_WTM_WMR_WM1 (0x0002)
|
||||
#define MCF_WTM_WMR_WM2 (0x0004)
|
||||
#define MCF_WTM_WMR_WM3 (0x0008)
|
||||
#define MCF_WTM_WMR_WM4 (0x0010)
|
||||
#define MCF_WTM_WMR_WM5 (0x0020)
|
||||
#define MCF_WTM_WMR_WM6 (0x0040)
|
||||
#define MCF_WTM_WMR_WM7 (0x0080)
|
||||
#define MCF_WTM_WMR_WM8 (0x0100)
|
||||
#define MCF_WTM_WMR_WM9 (0x0200)
|
||||
#define MCF_WTM_WMR_WM10 (0x0400)
|
||||
#define MCF_WTM_WMR_WM11 (0x0800)
|
||||
#define MCF_WTM_WMR_WM12 (0x1000)
|
||||
#define MCF_WTM_WMR_WM13 (0x2000)
|
||||
#define MCF_WTM_WMR_WM14 (0x4000)
|
||||
#define MCF_WTM_WMR_WM15 (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_WTM_WCNTR */
|
||||
#define MCF_WTM_WCNTR_WC0 (0x0001)
|
||||
#define MCF_WTM_WCNTR_WC1 (0x0002)
|
||||
#define MCF_WTM_WCNTR_WC2 (0x0004)
|
||||
#define MCF_WTM_WCNTR_WC3 (0x0008)
|
||||
#define MCF_WTM_WCNTR_WC4 (0x0010)
|
||||
#define MCF_WTM_WCNTR_WC5 (0x0020)
|
||||
#define MCF_WTM_WCNTR_WC6 (0x0040)
|
||||
#define MCF_WTM_WCNTR_WC7 (0x0080)
|
||||
#define MCF_WTM_WCNTR_WC8 (0x0100)
|
||||
#define MCF_WTM_WCNTR_WC9 (0x0200)
|
||||
#define MCF_WTM_WCNTR_WC10 (0x0400)
|
||||
#define MCF_WTM_WCNTR_WC11 (0x0800)
|
||||
#define MCF_WTM_WCNTR_WC12 (0x1000)
|
||||
#define MCF_WTM_WCNTR_WC13 (0x2000)
|
||||
#define MCF_WTM_WCNTR_WC14 (0x4000)
|
||||
#define MCF_WTM_WCNTR_WC15 (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_WTM_WSR */
|
||||
#define MCF_WTM_WSR_WS0 (0x0001)
|
||||
#define MCF_WTM_WSR_WS1 (0x0002)
|
||||
#define MCF_WTM_WSR_WS2 (0x0004)
|
||||
#define MCF_WTM_WSR_WS3 (0x0008)
|
||||
#define MCF_WTM_WSR_WS4 (0x0010)
|
||||
#define MCF_WTM_WSR_WS5 (0x0020)
|
||||
#define MCF_WTM_WSR_WS6 (0x0040)
|
||||
#define MCF_WTM_WSR_WS7 (0x0080)
|
||||
#define MCF_WTM_WSR_WS8 (0x0100)
|
||||
#define MCF_WTM_WSR_WS9 (0x0200)
|
||||
#define MCF_WTM_WSR_WS10 (0x0400)
|
||||
#define MCF_WTM_WSR_WS11 (0x0800)
|
||||
#define MCF_WTM_WSR_WS12 (0x1000)
|
||||
#define MCF_WTM_WSR_WS13 (0x2000)
|
||||
#define MCF_WTM_WSR_WS14 (0x4000)
|
||||
#define MCF_WTM_WSR_WS15 (0x8000)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_WTM_H__ */
|
||||
@ -0,0 +1,196 @@
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf5xxx.h
|
||||
* Purpose: Definitions common to all ColdFire processors
|
||||
*
|
||||
* Notes:
|
||||
*/
|
||||
|
||||
#ifndef _CPU_MCF5XXX_H
|
||||
#define _CPU_MCF5XXX_H
|
||||
|
||||
/***********************************************************************/
|
||||
/*
|
||||
* Misc. Defines
|
||||
*/
|
||||
|
||||
#ifdef FALSE
|
||||
#undef FALSE
|
||||
#endif
|
||||
#define FALSE (0)
|
||||
|
||||
#ifdef TRUE
|
||||
#undef TRUE
|
||||
#endif
|
||||
#define TRUE (1)
|
||||
|
||||
#ifdef NULL
|
||||
#undef NULL
|
||||
#endif
|
||||
#define NULL (0)
|
||||
|
||||
/***********************************************************************/
|
||||
/*
|
||||
* The basic data types
|
||||
*/
|
||||
|
||||
typedef unsigned char uint8; /* 8 bits */
|
||||
typedef unsigned short int uint16; /* 16 bits */
|
||||
typedef unsigned long int uint32; /* 32 bits */
|
||||
|
||||
typedef signed char int8; /* 8 bits */
|
||||
typedef signed short int int16; /* 16 bits */
|
||||
typedef signed long int int32; /* 32 bits */
|
||||
|
||||
typedef volatile uint8 vuint8; /* 8 bits */
|
||||
typedef volatile uint16 vuint16; /* 16 bits */
|
||||
typedef volatile uint32 vuint32; /* 32 bits */
|
||||
|
||||
/***********************************************************************/
|
||||
/*
|
||||
* Common M68K & ColdFire definitions
|
||||
*/
|
||||
|
||||
#define ADDRESS uint32
|
||||
#define INSTRUCTION uint16
|
||||
#define ILLEGAL 0x4AFC
|
||||
#define CPU_WORD_SIZE 16
|
||||
|
||||
#define MCF5XXX_SR_T (0x8000)
|
||||
#define MCF5XXX_SR_S (0x2000)
|
||||
#define MCF5XXX_SR_M (0x1000)
|
||||
#define MCF5XXX_SR_IPL (0x0700)
|
||||
#define MCF5XXX_SR_IPL_0 (0x0000)
|
||||
#define MCF5XXX_SR_IPL_1 (0x0100)
|
||||
#define MCF5XXX_SR_IPL_2 (0x0200)
|
||||
#define MCF5XXX_SR_IPL_3 (0x0300)
|
||||
#define MCF5XXX_SR_IPL_4 (0x0400)
|
||||
#define MCF5XXX_SR_IPL_5 (0x0500)
|
||||
#define MCF5XXX_SR_IPL_6 (0x0600)
|
||||
#define MCF5XXX_SR_IPL_7 (0x0700)
|
||||
#define MCF5XXX_SR_X (0x0010)
|
||||
#define MCF5XXX_SR_N (0x0008)
|
||||
#define MCF5XXX_SR_Z (0x0004)
|
||||
#define MCF5XXX_SR_V (0x0002)
|
||||
#define MCF5XXX_SR_C (0x0001)
|
||||
|
||||
#define MCF5XXX_CACR_CENB (0x80000000)
|
||||
#define MCF5XXX_CACR_CPDI (0x10000000)
|
||||
#define MCF5XXX_CACR_CPD (0x10000000)
|
||||
#define MCF5XXX_CACR_CFRZ (0x08000000)
|
||||
#define MCF5XXX_CACR_CINV (0x01000000)
|
||||
#define MCF5XXX_CACR_DIDI (0x00800000)
|
||||
#define MCF5XXX_CACR_DISD (0x00400000)
|
||||
#define MCF5XXX_CACR_INVI (0x00200000)
|
||||
#define MCF5XXX_CACR_INVD (0x00100000)
|
||||
#define MCF5XXX_CACR_CEIB (0x00000400)
|
||||
#define MCF5XXX_CACR_DCM_WR (0x00000000)
|
||||
#define MCF5XXX_CACR_DCM_CB (0x00000100)
|
||||
#define MCF5XXX_CACR_DCM_IP (0x00000200)
|
||||
#define MCF5XXX_CACR_DCM (0x00000200)
|
||||
#define MCF5XXX_CACR_DCM_II (0x00000300)
|
||||
#define MCF5XXX_CACR_DBWE (0x00000100)
|
||||
#define MCF5XXX_CACR_DWP (0x00000020)
|
||||
#define MCF5XXX_CACR_EUST (0x00000010)
|
||||
#define MCF5XXX_CACR_CLNF_00 (0x00000000)
|
||||
#define MCF5XXX_CACR_CLNF_01 (0x00000002)
|
||||
#define MCF5XXX_CACR_CLNF_10 (0x00000004)
|
||||
#define MCF5XXX_CACR_CLNF_11 (0x00000006)
|
||||
|
||||
#define MCF5XXX_ACR_AB(a) ((a)&0xFF000000)
|
||||
#define MCF5XXX_ACR_AM(a) (((a)&0xFF000000) >> 8)
|
||||
#define MCF5XXX_ACR_EN (0x00008000)
|
||||
#define MCF5XXX_ACR_SM_USER (0x00000000)
|
||||
#define MCF5XXX_ACR_SM_SUPER (0x00002000)
|
||||
#define MCF5XXX_ACR_SM_IGNORE (0x00006000)
|
||||
#define MCF5XXX_ACR_ENIB (0x00000080)
|
||||
#define MCF5XXX_ACR_CM (0x00000040)
|
||||
#define MCF5XXX_ACR_DCM_WR (0x00000000)
|
||||
#define MCF5XXX_ACR_DCM_CB (0x00000020)
|
||||
#define MCF5XXX_ACR_DCM_IP (0x00000040)
|
||||
#define MCF5XXX_ACR_DCM_II (0x00000060)
|
||||
#define MCF5XXX_ACR_CM (0x00000040)
|
||||
#define MCF5XXX_ACR_BWE (0x00000020)
|
||||
#define MCF5XXX_ACR_WP (0x00000004)
|
||||
|
||||
#define MCF5XXX_RAMBAR_BA(a) ((a)&0xFFFFC000)
|
||||
#define MCF5XXX_RAMBAR_PRI_00 (0x00000000)
|
||||
#define MCF5XXX_RAMBAR_PRI_01 (0x00004000)
|
||||
#define MCF5XXX_RAMBAR_PRI_10 (0x00008000)
|
||||
#define MCF5XXX_RAMBAR_PRI_11 (0x0000C000)
|
||||
#define MCF5XXX_RAMBAR_WP (0x00000100)
|
||||
#define MCF5XXX_RAMBAR_CI (0x00000020)
|
||||
#define MCF5XXX_RAMBAR_SC (0x00000010)
|
||||
#define MCF5XXX_RAMBAR_SD (0x00000008)
|
||||
#define MCF5XXX_RAMBAR_UC (0x00000004)
|
||||
#define MCF5XXX_RAMBAR_UD (0x00000002)
|
||||
#define MCF5XXX_RAMBAR_V (0x00000001)
|
||||
|
||||
/***********************************************************************/
|
||||
/*
|
||||
* The ColdFire family of processors has a simplified exception stack
|
||||
* frame that looks like the following:
|
||||
*
|
||||
* 3322222222221111 111111
|
||||
* 1098765432109876 5432109876543210
|
||||
* 8 +----------------+----------------+
|
||||
* | Program Counter |
|
||||
* 4 +----------------+----------------+
|
||||
* |FS/Fmt/Vector/FS| SR |
|
||||
* SP --> 0 +----------------+----------------+
|
||||
*
|
||||
* The stack self-aligns to a 4-byte boundary at an exception, with
|
||||
* the FS/Fmt/Vector/FS field indicating the size of the adjustment
|
||||
* (SP += 0,1,2,3 bytes).
|
||||
*/
|
||||
|
||||
#define MCF5XXX_RD_SF_FORMAT(PTR) \
|
||||
((*((uint16 *)(PTR)) >> 12) & 0x00FF)
|
||||
|
||||
#define MCF5XXX_RD_SF_VECTOR(PTR) \
|
||||
((*((uint16 *)(PTR)) >> 2) & 0x00FF)
|
||||
|
||||
#define MCF5XXX_RD_SF_FS(PTR) \
|
||||
( ((*((uint16 *)(PTR)) & 0x0C00) >> 8) | (*((uint16 *)(PTR)) & 0x0003) )
|
||||
|
||||
#define MCF5XXX_SF_SR(PTR) *((uint16 *)(PTR)+1)
|
||||
#define MCF5XXX_SF_PC(PTR) *((uint32 *)(PTR)+1)
|
||||
|
||||
/********************************************************************/
|
||||
/*
|
||||
* Functions provided by mcf5xxx.s
|
||||
*/
|
||||
|
||||
int asm_set_ipl (uint32);
|
||||
void mcf5xxx_wr_cacr (uint32);
|
||||
void mcf5xxx_wr_acr0 (uint32);
|
||||
void mcf5xxx_wr_acr1 (uint32);
|
||||
void mcf5xxx_wr_acr2 (uint32);
|
||||
void mcf5xxx_wr_acr3 (uint32);
|
||||
void mcf5xxx_wr_other_a7 (uint32);
|
||||
void mcf5xxx_wr_other_sp (uint32);
|
||||
void mcf5xxx_wr_vbr (uint32);
|
||||
void mcf5xxx_wr_macsr (uint32);
|
||||
void mcf5xxx_wr_mask (uint32);
|
||||
void mcf5xxx_wr_acc0 (uint32);
|
||||
void mcf5xxx_wr_accext01 (uint32);
|
||||
void mcf5xxx_wr_accext23 (uint32);
|
||||
void mcf5xxx_wr_acc1 (uint32);
|
||||
void mcf5xxx_wr_acc2 (uint32);
|
||||
void mcf5xxx_wr_acc3 (uint32);
|
||||
void mcf5xxx_wr_sr (uint32);
|
||||
void mcf5xxx_wr_rambar0 (uint32);
|
||||
void mcf5xxx_wr_rambar1 (uint32);
|
||||
void mcf5xxx_wr_mbar (uint32);
|
||||
void mcf5xxx_wr_mbar0 (uint32);
|
||||
void mcf5xxx_wr_mbar1 (uint32);
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* _CPU_MCF5XXX_H */
|
||||
|
||||
@ -0,0 +1,596 @@
|
||||
FUTURE
|
||||
|
||||
* TODO: The lwIP source code makes some invalid assumptions on processor
|
||||
word-length, storage sizes and alignment. See the mailing lists for
|
||||
problems with exoteric (/DSP) architectures showing these problems.
|
||||
We still have to fix some of these issues neatly.
|
||||
|
||||
* TODO: the ARP layer is not protected against concurrent access. If
|
||||
you run from a multitasking OS, serialize access to ARP (called from
|
||||
your network device driver and from a timeout thread.)
|
||||
|
||||
* TODO: the PPP code is broken in a few ways. There are namespace
|
||||
collisions on BSD systems and many assumptions on word-length
|
||||
(sizeof(int)). In ppp.c an assumption is made on the availability of
|
||||
a thread subsystem. Either PPP needs to be moved to contrib/ports/???
|
||||
or rearranged to be more generic.
|
||||
|
||||
HISTORY
|
||||
|
||||
(CVS HEAD)
|
||||
|
||||
* [New changes go here]
|
||||
|
||||
(STABLE-1_1_1)
|
||||
|
||||
2006-03-03 Christiaan Simons
|
||||
* ipv4/ip_frag.c: Added bound-checking assertions on ip_reassbitmap
|
||||
access and added pbuf_alloc() return value checks.
|
||||
|
||||
2006-01-01 Leon Woestenberg <leon.woestenberg@gmx.net>
|
||||
* tcp_{in,out}.c, tcp_out.c: Removed 'even sndbuf' fix in TCP, which is
|
||||
now handled by the checksum routine properly.
|
||||
|
||||
2006-02-27 Leon Woestenberg <leon.woestenberg@gmx.net>
|
||||
* pbuf.c: Fix alignment; pbuf_init() would not work unless
|
||||
pbuf_pool_memory[] was properly aligned. (Patch by Curt McDowell.)
|
||||
|
||||
2005-12-20 Leon Woestenberg <leon.woestenberg@gmx.net>
|
||||
* tcp.c: Remove PCBs which stay in LAST_ACK state too long. Patch
|
||||
submitted by Mitrani Hiroshi.
|
||||
|
||||
2005-12-15 Christiaan Simons
|
||||
* inet.c: Disabled the added summing routine to preserve code space.
|
||||
|
||||
2005-12-14 Leon Woestenberg <leon.woestenberg@gmx.net>
|
||||
* tcp_in.c: Duplicate FIN ACK race condition fix by Kelvin Lawson.
|
||||
Added Curt McDowell's optimized checksumming routine for future
|
||||
inclusion. Need to create test case for unaliged, aligned, odd,
|
||||
even length combination of cases on various endianess machines.
|
||||
|
||||
2005-12-09 Christiaan Simons
|
||||
* inet.c: Rewrote standard checksum routine in proper portable C.
|
||||
|
||||
2005-11-25 Christiaan Simons
|
||||
* udp.c tcp.c: Removed SO_REUSE hack. Should reside in socket code only.
|
||||
* *.c: introduced cc.h LWIP_DEBUG formatters matching the u16_t, s16_t,
|
||||
u32_t, s32_t typedefs. This solves most debug word-length assumes.
|
||||
|
||||
2005-07-17 Leon Woestenberg <leon.woestenberg@gmx.net>
|
||||
* inet.c: Fixed unaligned 16-bit access in the standard checksum
|
||||
routine by Peter Jolasson.
|
||||
* slipif.c: Fixed implementation assumption of single-pbuf datagrams.
|
||||
|
||||
2005-02-04 Leon Woestenberg <leon.woestenberg@gmx.net>
|
||||
* tcp_out.c: Fixed uninitialized 'queue' referenced in memerr branch.
|
||||
* tcp_{out|in}.c: Applied patch fixing unaligned access.
|
||||
|
||||
2005-01-04 Leon Woestenberg <leon.woestenberg@gmx.net>
|
||||
* pbuf.c: Fixed missing semicolon after LWIP_DEBUG statement.
|
||||
|
||||
2005-01-03 Leon Woestenberg <leon.woestenberg@gmx.net>
|
||||
* udp.c: UDP pcb->recv() was called even when it was NULL.
|
||||
|
||||
(STABLE-1_1_0)
|
||||
|
||||
2004-12-28 Leon Woestenberg <leon.woestenberg@gmx.net>
|
||||
* etharp.*: Disabled multiple packets on the ARP queue.
|
||||
This clashes with TCP queueing.
|
||||
|
||||
2004-11-28 Leon Woestenberg <leon.woestenberg@gmx.net>
|
||||
* etharp.*: Fixed race condition from ARP request to ARP timeout.
|
||||
Halved the ARP period, doubled the period counts.
|
||||
ETHARP_MAX_PENDING now should be at least 2. This prevents
|
||||
the counter from reaching 0 right away (which would allow
|
||||
too little time for ARP responses to be received).
|
||||
|
||||
2004-11-25 Leon Woestenberg <leon.woestenberg@gmx.net>
|
||||
* dhcp.c: Decline messages were not multicast but unicast.
|
||||
* etharp.c: ETHARP_CREATE is renamed to ETHARP_TRY_HARD.
|
||||
Do not try hard to insert arbitrary packet's source address,
|
||||
etharp_ip_input() now calls etharp_update() without ETHARP_TRY_HARD.
|
||||
etharp_query() now always DOES call ETHARP_TRY_HARD so that users
|
||||
querying an address will see it appear in the cache (DHCP could
|
||||
suffer from this when a server invalidly gave an in-use address.)
|
||||
* ipv4/ip_addr.h: Renamed ip_addr_maskcmp() to _netcmp() as we are
|
||||
comparing network addresses (identifiers), not the network masks
|
||||
themselves.
|
||||
* ipv4/ip_addr.c: ip_addr_isbroadcast() now checks that the given
|
||||
IP address actually belongs to the network of the given interface.
|
||||
|
||||
2004-11-24 Kieran Mansley <kjm25@cam.ac.uk>
|
||||
* tcp.c: Increment pcb->snd_buf when ACK is received in SYN_SENT state.
|
||||
|
||||
(STABLE-1_1_0-RC1)
|
||||
|
||||
2004-10-16 Kieran Mansley <kjm25@cam.ac.uk>
|
||||
* tcp.c: Add code to tcp_recved() to send an ACK (window update) immediately,
|
||||
even if one is already pending, if the rcv_wnd is above a threshold
|
||||
(currently TCP_WND/2). This avoids waiting for a timer to expire to send a
|
||||
delayed ACK in order to open the window if the stack is only receiving data.
|
||||
|
||||
2004-09-12 Kieran Mansley <kjm25@cam.ac.uk>
|
||||
* tcp*.*: Retransmit time-out handling improvement by Sam Jansen.
|
||||
|
||||
2004-08-20 Tony Mountifield <tony@softins.co.uk>
|
||||
* etharp.c: Make sure the first pbuf queued on an ARP entry
|
||||
is properly ref counted.
|
||||
|
||||
2004-07-27 Tony Mountifield <tony@softins.co.uk>
|
||||
* debug.h: Added (int) cast in LWIP_DEBUGF() to avoid compiler
|
||||
warnings about comparison.
|
||||
* pbuf.c: Stopped compiler complaining of empty if statement
|
||||
when LWIP_DEBUGF() empty. Closed an unclosed comment.
|
||||
* tcp.c: Stopped compiler complaining of empty if statement
|
||||
when LWIP_DEBUGF() empty.
|
||||
* ip.h Corrected IPH_TOS() macro: returns a byte, so doesn't need htons().
|
||||
* inet.c: Added a couple of casts to quiet the compiler.
|
||||
No need to test isascii(c) before isdigit(c) or isxdigit(c).
|
||||
|
||||
2004-07-22 Tony Mountifield <tony@softins.co.uk>
|
||||
* inet.c: Made data types consistent in inet_ntoa().
|
||||
Added casts for return values of checksum routines, to pacify compiler.
|
||||
* ip_frag.c, tcp_out.c, sockets.c, pbuf.c
|
||||
Small corrections to some debugging statements, to pacify compiler.
|
||||
|
||||
2004-07-21 Tony Mountifield <tony@softins.co.uk>
|
||||
* etharp.c: Removed spurious semicolon and added missing end-of-comment.
|
||||
* ethernetif.c Updated low_level_output() to match prototype for
|
||||
netif->linkoutput and changed low_level_input() similarly for consistency.
|
||||
* api_msg.c: Changed recv_raw() from int to u8_t, to match prototype
|
||||
of raw_recv() in raw.h and so avoid compiler error.
|
||||
* sockets.c: Added trivial (int) cast to keep compiler happier.
|
||||
* ip.c, netif.c Changed debug statements to use the tidier ip4_addrN() macros.
|
||||
|
||||
(STABLE-1_0_0)
|
||||
|
||||
++ Changes:
|
||||
|
||||
2004-07-05 Leon Woestenberg <leon.woestenberg@gmx.net>
|
||||
* sockets.*: Restructured LWIP_PRIVATE_TIMEVAL. Make sure
|
||||
your cc.h file defines this either 1 or 0. If non-defined,
|
||||
defaults to 1.
|
||||
* .c: Added <string.h> and <errno.h> includes where used.
|
||||
* etharp.c: Made some array indices unsigned.
|
||||
|
||||
2004-06-27 Leon Woestenberg <leon.woestenberg@gmx.net>
|
||||
* netif.*: Added netif_set_up()/down().
|
||||
* dhcp.c: Changes to restart program flow.
|
||||
|
||||
2004-05-07 Leon Woestenberg <leon.woestenberg@gmx.net>
|
||||
* etharp.c: In find_entry(), instead of a list traversal per candidate, do a
|
||||
single-pass lookup for different candidates. Should exploit locality.
|
||||
|
||||
2004-04-29 Leon Woestenberg <leon.woestenberg@gmx.net>
|
||||
* tcp*.c: Cleaned up source comment documentation for Doxygen processing.
|
||||
* opt.h: ETHARP_ALWAYS_INSERT option removed to comply with ARP RFC.
|
||||
* etharp.c: update_arp_entry() only adds new ARP entries when adviced to by
|
||||
the caller. This deprecates the ETHARP_ALWAYS_INSERT overrule option.
|
||||
|
||||
++ Bug fixes:
|
||||
|
||||
2004-04-27 Leon Woestenberg <leon.woestenberg@gmx.net>
|
||||
* etharp.c: Applied patch of bug #8708 by Toni Mountifield with a solution
|
||||
suggested by Timmy Brolin. Fix for 32-bit processors that cannot access
|
||||
non-aligned 32-bit words, such as soms 32-bit TCP/IP header fields. Fix
|
||||
is to prefix the 14-bit Ethernet headers with two padding bytes.
|
||||
|
||||
2004-04-23 Leon Woestenberg <leon.woestenberg@gmx.net>
|
||||
* ip_addr.c: Fix in the ip_addr_isbroadcast() check.
|
||||
* etharp.c: Fixed the case where the packet that initiates the ARP request
|
||||
is not queued, and gets lost. Fixed the case where the packets destination
|
||||
address is already known; we now always queue the packet and perform an ARP
|
||||
request.
|
||||
|
||||
(STABLE-0_7_0)
|
||||
|
||||
++ Bug fixes:
|
||||
|
||||
* Fixed TCP bug for SYN_SENT to ESTABLISHED state transition.
|
||||
* Fixed TCP bug in dequeueing of FIN from out of order segment queue.
|
||||
* Fixed two possible NULL references in rare cases.
|
||||
|
||||
(STABLE-0_6_6)
|
||||
|
||||
++ Bug fixes:
|
||||
|
||||
* Fixed DHCP which did not include the IP address in DECLINE messages.
|
||||
|
||||
++ Changes:
|
||||
|
||||
* etharp.c has been hauled over a bit.
|
||||
|
||||
(STABLE-0_6_5)
|
||||
|
||||
++ Bug fixes:
|
||||
|
||||
* Fixed TCP bug induced by bad window resizing with unidirectional TCP traffic.
|
||||
* Packets sent from ARP queue had invalid source hardware address.
|
||||
|
||||
++ Changes:
|
||||
|
||||
* Pass-by ARP requests do now update the cache.
|
||||
|
||||
++ New features:
|
||||
|
||||
* No longer dependent on ctype.h.
|
||||
* New socket options.
|
||||
* Raw IP pcb support.
|
||||
|
||||
(STABLE-0_6_4)
|
||||
|
||||
++ Bug fixes:
|
||||
|
||||
* Some debug formatters and casts fixed.
|
||||
* Numereous fixes in PPP.
|
||||
|
||||
++ Changes:
|
||||
|
||||
* DEBUGF now is LWIP_DEBUGF
|
||||
* pbuf_dechain() has been re-enabled.
|
||||
* Mentioned the changed use of CVS branches in README.
|
||||
|
||||
(STABLE-0_6_3)
|
||||
|
||||
++ Bug fixes:
|
||||
|
||||
* Fixed pool pbuf memory leak in pbuf_alloc().
|
||||
Occured if not enough PBUF_POOL pbufs for a packet pbuf chain.
|
||||
Reported by Savin Zlobec.
|
||||
|
||||
* PBUF_POOL chains had their tot_len field not set for non-first
|
||||
pbufs. Fixed in pbuf_alloc().
|
||||
|
||||
++ New features:
|
||||
|
||||
* Added PPP stack contributed by Marc Boucher
|
||||
|
||||
++ Changes:
|
||||
|
||||
* Now drops short packets for ICMP/UDP/TCP protocols. More robust.
|
||||
|
||||
* ARP queueuing now queues the latest packet instead of the first.
|
||||
This is the RFC recommended behaviour, but can be overridden in
|
||||
lwipopts.h.
|
||||
|
||||
(0.6.2)
|
||||
|
||||
++ Bugfixes:
|
||||
|
||||
* TCP has been fixed to deal with the new use of the pbuf->ref
|
||||
counter.
|
||||
|
||||
* DHCP dhcp_inform() crash bug fixed.
|
||||
|
||||
++ Changes:
|
||||
|
||||
* Removed pbuf_pool_free_cache and pbuf_pool_alloc_cache. Also removed
|
||||
pbuf_refresh(). This has sped up pbuf pool operations considerably.
|
||||
Implemented by David Haas.
|
||||
|
||||
(0.6.1)
|
||||
|
||||
++ New features:
|
||||
|
||||
* The packet buffer implementation has been enhanced to support
|
||||
zero-copy and copy-on-demand for packet buffers which have their
|
||||
payloads in application-managed memory.
|
||||
Implemented by David Haas.
|
||||
|
||||
Use PBUF_REF to make a pbuf refer to RAM. lwIP will use zero-copy
|
||||
if an outgoing packet can be directly sent on the link, or perform
|
||||
a copy-on-demand when necessary.
|
||||
|
||||
The application can safely assume the packet is sent, and the RAM
|
||||
is available to the application directly after calling udp_send()
|
||||
or similar function.
|
||||
|
||||
++ Bugfixes:
|
||||
|
||||
* ARP_QUEUEING should now correctly work for all cases, including
|
||||
PBUF_REF.
|
||||
Implemented by Leon Woestenberg.
|
||||
|
||||
++ Changes:
|
||||
|
||||
* IP_ADDR_ANY is no longer a NULL pointer. Instead, it is a pointer
|
||||
to a '0.0.0.0' IP address.
|
||||
|
||||
* The packet buffer implementation is changed. The pbuf->ref counter
|
||||
meaning has changed, and several pbuf functions have been
|
||||
adapted accordingly.
|
||||
|
||||
* netif drivers have to be changed to set the hardware address length field
|
||||
that must be initialized correctly by the driver (hint: 6 for Ethernet MAC).
|
||||
See the contrib/ports/c16x cs8900 driver as a driver example.
|
||||
|
||||
* netif's have a dhcp field that must be initialized to NULL by the driver.
|
||||
See the contrib/ports/c16x cs8900 driver as a driver example.
|
||||
|
||||
(0.5.x) This file has been unmaintained up to 0.6.1. All changes are
|
||||
logged in CVS but have not been explained here.
|
||||
|
||||
(0.5.3) Changes since version 0.5.2
|
||||
|
||||
++ Bugfixes:
|
||||
|
||||
* memp_malloc(MEMP_API_MSG) could fail with multiple application
|
||||
threads because it wasn't protected by semaphores.
|
||||
|
||||
++ Other changes:
|
||||
|
||||
* struct ip_addr now packed.
|
||||
|
||||
* The name of the time variable in arp.c has been changed to ctime
|
||||
to avoid conflicts with the time() function.
|
||||
|
||||
(0.5.2) Changes since version 0.5.1
|
||||
|
||||
++ New features:
|
||||
|
||||
* A new TCP function, tcp_tmr(), now handles both TCP timers.
|
||||
|
||||
++ Bugfixes:
|
||||
|
||||
* A bug in tcp_parseopt() could cause the stack to hang because of a
|
||||
malformed TCP option.
|
||||
|
||||
* The address of new connections in the accept() function in the BSD
|
||||
socket library was not handled correctly.
|
||||
|
||||
* pbuf_dechain() did not update the ->tot_len field of the tail.
|
||||
|
||||
* Aborted TCP connections were not handled correctly in all
|
||||
situations.
|
||||
|
||||
++ Other changes:
|
||||
|
||||
* All protocol header structs are now packed.
|
||||
|
||||
* The ->len field in the tcp_seg structure now counts the actual
|
||||
amount of data, and does not add one for SYN and FIN segments.
|
||||
|
||||
(0.5.1) Changes since version 0.5.0
|
||||
|
||||
++ New features:
|
||||
|
||||
* Possible to run as a user process under Linux.
|
||||
|
||||
* Preliminary support for cross platform packed structs.
|
||||
|
||||
* ARP timer now implemented.
|
||||
|
||||
++ Bugfixes:
|
||||
|
||||
* TCP output queue length was badly initialized when opening
|
||||
connections.
|
||||
|
||||
* TCP delayed ACKs were not sent correctly.
|
||||
|
||||
* Explicit initialization of BSS segment variables.
|
||||
|
||||
* read() in BSD socket library could drop data.
|
||||
|
||||
* Problems with memory alignment.
|
||||
|
||||
* Situations when all TCP buffers were used could lead to
|
||||
starvation.
|
||||
|
||||
* TCP MSS option wasn't parsed correctly.
|
||||
|
||||
* Problems with UDP checksum calculation.
|
||||
|
||||
* IP multicast address tests had endianess problems.
|
||||
|
||||
* ARP requests had wrong destination hardware address.
|
||||
|
||||
++ Other changes:
|
||||
|
||||
* struct eth_addr changed from u16_t[3] array to u8_t[6].
|
||||
|
||||
* A ->linkoutput() member was added to struct netif.
|
||||
|
||||
* TCP and UDP ->dest_* struct members where changed to ->remote_*.
|
||||
|
||||
* ntoh* macros are now null definitions for big endian CPUs.
|
||||
|
||||
(0.5.0) Changes since version 0.4.2
|
||||
|
||||
++ New features:
|
||||
|
||||
* Redesigned operating system emulation layer to make porting easier.
|
||||
|
||||
* Better control over TCP output buffers.
|
||||
|
||||
* Documenation added.
|
||||
|
||||
++ Bugfixes:
|
||||
|
||||
* Locking issues in buffer management.
|
||||
|
||||
* Bugfixes in the sequential API.
|
||||
|
||||
* IP forwarding could cause memory leakage. This has been fixed.
|
||||
|
||||
++ Other changes:
|
||||
|
||||
* Directory structure somewhat changed; the core/ tree has been
|
||||
collapsed.
|
||||
|
||||
(0.4.2) Changes since version 0.4.1
|
||||
|
||||
++ New features:
|
||||
|
||||
* Experimental ARP implementation added.
|
||||
|
||||
* Skeleton Ethernet driver added.
|
||||
|
||||
* Experimental BSD socket API library added.
|
||||
|
||||
++ Bugfixes:
|
||||
|
||||
* In very intense situations, memory leakage could occur. This has
|
||||
been fixed.
|
||||
|
||||
++ Other changes:
|
||||
|
||||
* Variables named "data" and "code" have been renamed in order to
|
||||
avoid name conflicts in certain compilers.
|
||||
|
||||
* Variable++ have in appliciable cases been translated to ++variable
|
||||
since some compilers generate better code in the latter case.
|
||||
|
||||
(0.4.1) Changes since version 0.4
|
||||
|
||||
++ New features:
|
||||
|
||||
* TCP: Connection attempts time out earlier than data
|
||||
transmissions. Nagle algorithm implemented. Push flag set on the
|
||||
last segment in a burst.
|
||||
|
||||
* UDP: experimental support for UDP-Lite extensions.
|
||||
|
||||
++ Bugfixes:
|
||||
|
||||
* TCP: out of order segments were in some cases handled incorrectly,
|
||||
and this has now been fixed. Delayed acknowledgements was broken
|
||||
in 0.4, has now been fixed. Binding to an address that is in use
|
||||
now results in an error. Reset connections sometimes hung an
|
||||
application; this has been fixed.
|
||||
|
||||
* Checksum calculation sometimes failed for chained pbufs with odd
|
||||
lengths. This has been fixed.
|
||||
|
||||
* API: a lot of bug fixes in the API. The UDP API has been improved
|
||||
and tested. Error reporting and handling has been
|
||||
improved. Logical flaws and race conditions for incoming TCP
|
||||
connections has been found and removed.
|
||||
|
||||
* Memory manager: alignment issues. Reallocating memory sometimes
|
||||
failed, this has been fixed.
|
||||
|
||||
* Generic library: bcopy was flawed and has been fixed.
|
||||
|
||||
++ Other changes:
|
||||
|
||||
* API: all datatypes has been changed from generic ones such as
|
||||
ints, to specified ones such as u16_t. Functions that return
|
||||
errors now have the correct type (err_t).
|
||||
|
||||
* General: A lot of code cleaned up and debugging code removed. Many
|
||||
portability issues have been fixed.
|
||||
|
||||
* The license was changed; the advertising clause was removed.
|
||||
|
||||
* C64 port added.
|
||||
|
||||
* Thanks: Huge thanks go to Dagan Galarneau, Horst Garnetzke, Petri
|
||||
Kosunen, Mikael Caleres, and Frits Wilmink for reporting and
|
||||
fixing bugs!
|
||||
|
||||
(0.4) Changes since version 0.3.1
|
||||
|
||||
* Memory management has been radically changed; instead of
|
||||
allocating memory from a shared heap, memory for objects that are
|
||||
rapidly allocated and deallocated is now kept in pools. Allocation
|
||||
and deallocation from those memory pools is very fast. The shared
|
||||
heap is still present but is used less frequently.
|
||||
|
||||
* The memory, memory pool, and packet buffer subsystems now support
|
||||
4-, 2-, or 1-byte alignment.
|
||||
|
||||
* "Out of memory" situations are handled in a more robust way.
|
||||
|
||||
* Stack usage has been reduced.
|
||||
|
||||
* Easier configuration of lwIP parameters such as memory usage,
|
||||
TTLs, statistics gathering, etc. All configuration parameters are
|
||||
now kept in a single header file "lwipopts.h".
|
||||
|
||||
* The directory structure has been changed slightly so that all
|
||||
architecture specific files are kept under the src/arch
|
||||
hierarchy.
|
||||
|
||||
* Error propagation has been improved, both in the protocol modules
|
||||
and in the API.
|
||||
|
||||
* The code for the RTXC architecture has been implemented, tested
|
||||
and put to use.
|
||||
|
||||
* Bugs have been found and corrected in the TCP, UDP, IP, API, and
|
||||
the Internet checksum modules.
|
||||
|
||||
* Bugs related to porting between a 32-bit and a 16-bit architecture
|
||||
have been found and corrected.
|
||||
|
||||
* The license has been changed slightly to conform more with the
|
||||
original BSD license, including the advertisement clause.
|
||||
|
||||
(0.3.1) Changes since version 0.3
|
||||
|
||||
* Fix of a fatal bug in the buffer management. Pbufs with allocated
|
||||
RAM never returned the RAM when the pbuf was deallocated.
|
||||
|
||||
* TCP congestion control, window updates and retransmissions did not
|
||||
work correctly. This has now been fixed.
|
||||
|
||||
* Bugfixes in the API.
|
||||
|
||||
(0.3) Changes since version 0.2
|
||||
|
||||
* New and improved directory structure. All include files are now
|
||||
kept in a dedicated include/ directory.
|
||||
|
||||
* The API now has proper error handling. A new function,
|
||||
netconn_err(), now returns an error code for the connection in
|
||||
case of errors.
|
||||
|
||||
* Improvements in the memory management subsystem. The system now
|
||||
keeps a pointer to the lowest free memory block. A new function,
|
||||
mem_malloc2() tries to allocate memory once, and if it fails tries
|
||||
to free some memory and retry the allocation.
|
||||
|
||||
* Much testing has been done with limited memory
|
||||
configurations. lwIP now does a better job when overloaded.
|
||||
|
||||
* Some bugfixes and improvements to the buffer (pbuf) subsystem.
|
||||
|
||||
* Many bugfixes in the TCP code:
|
||||
|
||||
- Fixed a bug in tcp_close().
|
||||
|
||||
- The TCP receive window was incorrectly closed when out of
|
||||
sequence segments was received. This has been fixed.
|
||||
|
||||
- Connections are now timed-out of the FIN-WAIT-2 state.
|
||||
|
||||
- The initial congestion window could in some cases be too
|
||||
large. This has been fixed.
|
||||
|
||||
- The retransmission queue could in some cases be screwed up. This
|
||||
has been fixed.
|
||||
|
||||
- TCP RST flag now handled correctly.
|
||||
|
||||
- Out of sequence data was in some cases never delivered to the
|
||||
application. This has been fixed.
|
||||
|
||||
- Retransmitted segments now contain the correct acknowledgment
|
||||
number and advertised window.
|
||||
|
||||
- TCP retransmission timeout backoffs are not correctly computed
|
||||
(ala BSD). After a number of retransmissions, TCP now gives up
|
||||
the connection.
|
||||
|
||||
* TCP connections now are kept on three lists, one for active
|
||||
connections, one for listening connections, and one for
|
||||
connections that are in TIME-WAIT. This greatly speeds up the fast
|
||||
timeout processing for sending delayed ACKs.
|
||||
|
||||
* TCP now provides proper feedback to the application when a
|
||||
connection has been successfully set up.
|
||||
|
||||
* More comments have been added to the code. The code has also been
|
||||
somewhat cleaned up.
|
||||
|
||||
(0.2) Initial public release.
|
||||
@ -0,0 +1,33 @@
|
||||
/*
|
||||
* Copyright (c) 2001, 2002 Swedish Institute of Computer Science.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
* This file is part of the lwIP TCP/IP stack.
|
||||
*
|
||||
* Author: Adam Dunkels <adam@sics.se>
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
@ -0,0 +1,4 @@
|
||||
src/ - The source code for the lwIP TCP/IP stack.
|
||||
doc/ - The documentation for lwIP.
|
||||
|
||||
See also the FILES file in each subdirectory.
|
||||
@ -0,0 +1,74 @@
|
||||
INTRODUCTION
|
||||
|
||||
lwIP is a small independent implementation of the TCP/IP protocol
|
||||
suite that has been developed by Adam Dunkels at the Computer and
|
||||
Networks Architectures (CNA) lab at the Swedish Institute of Computer
|
||||
Science (SICS).
|
||||
|
||||
The focus of the lwIP TCP/IP implementation is to reduce the RAM usage
|
||||
while still having a full scale TCP. This making lwIP suitable for use
|
||||
in embedded systems with tens of kilobytes of free RAM and room for
|
||||
around 40 kilobytes of code ROM.
|
||||
|
||||
FEATURES
|
||||
|
||||
* IP (Internet Protocol) including packet forwarding over multiple
|
||||
network interfaces
|
||||
* ICMP (Internet Control Message Protocol) for network maintenance
|
||||
and debugging
|
||||
* UDP (User Datagram Protocol) including experimental UDP-lite
|
||||
extensions
|
||||
* TCP (Transmission Control Protocol) with congestion control, RTT
|
||||
estimation and fast recovery/fast retransmit
|
||||
* Specialized API for enhanced performance
|
||||
* Optional Berkeley socket API
|
||||
|
||||
LICENSE
|
||||
|
||||
lwIP is freely available under a BSD license.
|
||||
|
||||
DEVELOPMENT
|
||||
|
||||
lwIP has grown into an excellent TCP/IP stack for embedded devices,
|
||||
and developers using the stack often submit bug fixes, improvements,
|
||||
and additions to the stack to further increase its usefulness.
|
||||
|
||||
Development of lwIP is hosted on Savannah, a central point for
|
||||
software development, maintenance and distribution. Everyone can
|
||||
help improve lwIP by use of Savannah's interface, CVS and the
|
||||
mailing list. A core team of developers will commit changes to the
|
||||
CVS source tree.
|
||||
|
||||
The lwIP TCP/IP stack is maintained in the 'lwip' CVS module and
|
||||
contributions (such as platform ports) are in the 'contrib' module.
|
||||
|
||||
See doc/savannah.txt for details on CVS server access for users and
|
||||
developers.
|
||||
|
||||
Last night's CVS tar ball can be downloaded from:
|
||||
http://savannah.gnu.org/cvs.backups/lwip.tar.gz [CHANGED - NEEDS FIXING]
|
||||
|
||||
The current CVS trees are web-browsable:
|
||||
http://savannah.nongnu.org/cgi-bin/viewcvs/lwip/lwip/
|
||||
http://savannah.nongnu.org/cgi-bin/viewcvs/lwip/contrib/
|
||||
|
||||
Submit patches and bugs via the lwIP project page:
|
||||
http://savannah.nongnu.org/projects/lwip/
|
||||
|
||||
|
||||
DOCUMENTATION
|
||||
|
||||
The original out-dated homepage of lwIP and Adam Dunkels' papers on
|
||||
lwIP are at the official lwIP home page:
|
||||
http://www.sics.se/~adam/lwip/
|
||||
|
||||
Self documentation of the source code is regularly extracted from the
|
||||
current CVS sources and is available from this web page:
|
||||
http://www.nongnu.org/lwip/
|
||||
|
||||
Reading Adam's papers, the files in docs/, browsing the source code
|
||||
documentation and browsing the mailing list archives is a good way to
|
||||
become familiar with the design of lwIP.
|
||||
|
||||
Adam Dunkels <adam@sics.se>
|
||||
Leon Woestenberg <leon.woestenberg@gmx.net>
|
||||
@ -0,0 +1,77 @@
|
||||
/*
|
||||
* Copyright (c) 2001-2003 Swedish Institute of Computer Science.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
* This file is part of the lwIP TCP/IP stack.
|
||||
*
|
||||
* Author: Adam Dunkels <adam@sics.se>
|
||||
* Modifcations: Christian Walter <wolti@sil.at>
|
||||
*/
|
||||
#ifndef __CC_H__
|
||||
#define __CC_H__
|
||||
|
||||
/* ------------------------ System includes ------------------------------- */
|
||||
#include <string.h>
|
||||
|
||||
/* ------------------------ Project includes ------------------------------ */
|
||||
#include "cpu.h"
|
||||
#include "sys_arch.h"
|
||||
|
||||
/* ------------------------ Defines --------------------------------------- */
|
||||
|
||||
#define PACK_STRUCT_BEGIN
|
||||
#define PACK_STRUCT_STRUCT __attribute__ ((__packed__))
|
||||
#define PACK_STRUCT_END
|
||||
|
||||
#define PACK_STRUCT_FIELD( x ) x
|
||||
|
||||
#define ALIGN_STRUCT_8_BEGIN
|
||||
#define ALIGN_STRUCT_8 __attribute__ ((aligned (8)))
|
||||
#define ALIGN_STRUCT_8_END
|
||||
|
||||
#define LWIP_PLATFORM_ASSERT( x ) sys_assert( x )
|
||||
#define LWIP_PLATFORM_DIAG( x, ... ) do{ sys_debug x; } while( 0 );
|
||||
|
||||
/* Define (sn)printf formatters for these lwIP types */
|
||||
#define U16_F "hu"
|
||||
#define S16_F "hd"
|
||||
#define X16_F "hx"
|
||||
#define U32_F "lu"
|
||||
#define S32_F "ld"
|
||||
#define X32_F "lx"
|
||||
|
||||
/* ------------------------ Type definitions (lwIP) ----------------------- */
|
||||
typedef unsigned char u8_t;
|
||||
typedef signed char s8_t;
|
||||
typedef unsigned short u16_t;
|
||||
typedef signed short s16_t;
|
||||
typedef unsigned long u32_t;
|
||||
typedef signed long s32_t;
|
||||
typedef u32_t mem_ptr_t;
|
||||
typedef int sys_prot_t;
|
||||
|
||||
/* ------------------------ Prototypes ------------------------------------ */
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,38 @@
|
||||
/*
|
||||
* Copyright (c) 2001-2003 Swedish Institute of Computer Science.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
* This file is part of the lwIP TCP/IP stack.
|
||||
*
|
||||
* Author: Adam Dunkels <adam@sics.se>
|
||||
*
|
||||
*/
|
||||
#ifndef __CPU_H__
|
||||
#define __CPU_H__
|
||||
|
||||
/* ------------------------ Defines --------------------------------------- */
|
||||
#define BYTE_ORDER BIG_ENDIAN
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,39 @@
|
||||
/*
|
||||
* Copyright (c) 2001-2003 Swedish Institute of Computer Science.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
* This file is part of the lwIP TCP/IP stack.
|
||||
*
|
||||
* Author: Adam Dunkels <adam@sics.se>
|
||||
*
|
||||
*/
|
||||
#ifndef __PERF_H__
|
||||
#define __PERF_H__
|
||||
|
||||
/* ------------------------ Defines --------------------------------------- */
|
||||
#define PERF_START /* null definition */
|
||||
#define PERF_STOP(x) /* null definition */
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,62 @@
|
||||
/*
|
||||
* Copyright (c) 2001-2003 Swedish Institute of Computer Science.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
* This file is part of the lwIP TCP/IP stack.
|
||||
*
|
||||
* Author: Adam Dunkels <adam@sics.se>
|
||||
*
|
||||
*/
|
||||
#ifndef __SYS_ARCH_H__
|
||||
#define __SYS_ARCH_H__
|
||||
|
||||
/* ------------------------ Project includes ------------------------------ */
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
#include "queue.h"
|
||||
#include "semphr.h"
|
||||
|
||||
/* ------------------------ Defines --------------------------------------- */
|
||||
#define SYS_MBOX_NULL ( xQueueHandle )0
|
||||
#define SYS_THREAD_NULL NULL
|
||||
#define SYS_SEM_NULL ( xSemaphoreHandle )0
|
||||
#define SIO_FD_NULL ( sio_fd_t )NULL
|
||||
|
||||
/* ------------------------ Type definitions ------------------------------ */
|
||||
|
||||
|
||||
typedef xSemaphoreHandle sys_sem_t;
|
||||
typedef xQueueHandle sys_mbox_t;
|
||||
typedef void *sys_thread_t;
|
||||
|
||||
/* ------------------------ Prototypes ------------------------------------ */
|
||||
sys_thread_t sys_arch_thread_new( void ( *thread ) ( void *arg ), void *arg,
|
||||
int prio, size_t ssize );
|
||||
sys_thread_t sys_arch_thread_current( void );
|
||||
void sys_arch_thread_remove( sys_thread_t hdl );
|
||||
void sys_assert( const char *const msg );
|
||||
void sys_debug( const char *const fmt, ... );
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,582 @@
|
||||
/*
|
||||
* Copyright (c) 2006 Christian Walter
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
* Author: Christian Walter <wolti@sil.at>
|
||||
*
|
||||
* TODO:
|
||||
* - Introduce another task create function in the sys_arch layer which allows
|
||||
* for passing the stack size.
|
||||
* - Avoid copying the buffers - this requires changeing the nbuf driver code
|
||||
* to use the lwIP pbuf buffer implementation.
|
||||
*
|
||||
* File: $Id: fec.c,v 1.3 2006/08/29 18:53:46 wolti Exp $
|
||||
*/
|
||||
|
||||
/* ------------------------ System includes ------------------------------- */
|
||||
#include <stdlib.h>
|
||||
|
||||
/* ------------------------ Platform includes ----------------------------- */
|
||||
#include "mcf5xxx.h"
|
||||
#include "mcf523x.h"
|
||||
|
||||
#include "nbuf.h"
|
||||
|
||||
/* ------------------------ lwIP includes --------------------------------- */
|
||||
#include "lwip/opt.h"
|
||||
#include "lwip/def.h"
|
||||
#include "lwip/mem.h"
|
||||
#include "lwip/pbuf.h"
|
||||
#include "lwip/sys.h"
|
||||
#include "lwip/stats.h"
|
||||
#include "lwip/debug.h"
|
||||
#include "netif/etharp.h"
|
||||
|
||||
/* ------------------------ Defines --------------------------------------- */
|
||||
#ifdef FEC_DEBUG
|
||||
#define FEC_DEBUG_INIT \
|
||||
do \
|
||||
{ \
|
||||
MCF_GPIO_PDDR_FECI2C = ( MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 | \
|
||||
MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 ); \
|
||||
} while( 0 )
|
||||
|
||||
#define FEC_DEBUG_RX_TIMING( x ) \
|
||||
do \
|
||||
{ \
|
||||
if( x ) \
|
||||
MCF_GPIO_PPDSDR_FECI2C = MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0; \
|
||||
else \
|
||||
MCF_GPIO_PCLRR_FECI2C = ~( MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 ); \
|
||||
} while( 0 )
|
||||
|
||||
#define FEC_DEBUG_TX_TIMING( x ) \
|
||||
do \
|
||||
{ \
|
||||
if( x ) \
|
||||
MCF_GPIO_PPDSDR_FECI2C = MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1; \
|
||||
else \
|
||||
MCF_GPIO_PCLRR_FECI2C = ~( MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 ); \
|
||||
} while( 0 )
|
||||
|
||||
#else
|
||||
#define FEC_DEBUG DBG_OFF
|
||||
#define FEC_DEBUG_INIT
|
||||
#define FEC_DEBUG_RX_TIMING( x )
|
||||
#define FEC_DEBUG_TX_TIMING( x )
|
||||
#endif
|
||||
|
||||
#define MCF_FEC_INT_LEVEL ( 6 )
|
||||
#define MCF_FEC_INT_PRIORITY ( 0 )
|
||||
#define MCF_FEC_VEC_RXF ( 64 + 27 )
|
||||
#define MCF_FEC_MTU ( 1518 )
|
||||
|
||||
#define ETH_ADDR_LEN ( 6 )
|
||||
|
||||
#define TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
|
||||
|
||||
/* ------------------------ Type definitions ------------------------------ */
|
||||
typedef struct
|
||||
{
|
||||
struct netif *netif; /* lwIP network interface. */
|
||||
struct eth_addr *self; /* MAC address of FEC interface. */
|
||||
sys_sem_t tx_sem; /* Control access to transmitter. */
|
||||
sys_sem_t rx_sem; /* Semaphore to signal receive thread. */
|
||||
} mcf523xfec_if_t;
|
||||
|
||||
/* ------------------------ Static variables ------------------------------ */
|
||||
static mcf523xfec_if_t *fecif_g;
|
||||
|
||||
/* ------------------------ Static functions ------------------------------ */
|
||||
static err_t mcf523xfec_output( struct netif *, struct pbuf *, struct ip_addr * );
|
||||
static err_t mcf523xfec_output_raw( struct netif *, struct pbuf * );
|
||||
|
||||
static void mcf523xfec_reset( mcf523xfec_if_t * fecif );
|
||||
static void mcf523xfec_enable( mcf523xfec_if_t * fecif );
|
||||
static void mcf523xfec_disable( mcf523xfec_if_t * fecif );
|
||||
static void mcf523xfec_get_mac( mcf523xfec_if_t * fecif, struct eth_addr *mac );
|
||||
static void mcf523xfec_rx_irq( void );
|
||||
static void mcf523xfec_rx_task( void *arg );
|
||||
|
||||
static void arp_timer( void *arg );
|
||||
static void eth_input( struct netif *netif, struct pbuf *p );
|
||||
|
||||
/* ------------------------ Start implementation -------------------------- */
|
||||
|
||||
static void
|
||||
arp_timer( void *arg )
|
||||
{
|
||||
( void )arg;
|
||||
etharp_tmr( );
|
||||
sys_timeout( ARP_TMR_INTERVAL, arp_timer, NULL );
|
||||
}
|
||||
|
||||
err_t
|
||||
mcf523xfec_output_raw( struct netif *netif, struct pbuf *p )
|
||||
{
|
||||
err_t res;
|
||||
nbuf_t *pNBuf;
|
||||
mcf523xfec_if_t *fecif = netif->state;
|
||||
int i;
|
||||
struct pbuf *q;
|
||||
|
||||
#if ETH_PAD_SIZE
|
||||
pbuf_header( p, -ETH_PAD_SIZE ); /* drop the padding word */
|
||||
#endif
|
||||
|
||||
|
||||
/* Test if we can handle such big frames. If not drop it. */
|
||||
if( p->tot_len > MCF_FEC_MTU )
|
||||
{
|
||||
#if LINK_STATS
|
||||
lwip_stats.link.lenerr++;
|
||||
#endif
|
||||
res = ERR_BUF;
|
||||
}
|
||||
/* Test if our network buffer scheme can handle a packet of this size. If
|
||||
* not drop it and return a memory error. */
|
||||
else if( p->tot_len > TX_BUFFER_SIZE )
|
||||
{
|
||||
#ifdef LINK_STATS
|
||||
lwip_stats.link.memerr++;
|
||||
#endif
|
||||
res = ERR_MEM;
|
||||
}
|
||||
/* Allocate a transmit buffer. If no buffer is available drop the frame. */
|
||||
else if( ( pNBuf = nbuf_tx_allocate( ) ) == NULL )
|
||||
{
|
||||
LWIP_ASSERT( "mcf523xfec_output_raw: pNBuf != NULL\n", pNBuf != NULL );
|
||||
#ifdef LINK_STATS
|
||||
lwip_stats.link.memerr++;
|
||||
#endif
|
||||
res = ERR_MEM;
|
||||
}
|
||||
else
|
||||
{
|
||||
q = p;
|
||||
i = 0;
|
||||
do
|
||||
{
|
||||
memcpy( &pNBuf->data[i], q->payload, q->len );
|
||||
i += q->len;
|
||||
}
|
||||
while( ( q = q->next ) != NULL );
|
||||
pNBuf->length = p->tot_len;
|
||||
|
||||
/* Set Frame ready for transmission. */
|
||||
pNBuf->status |= TX_BD_R;
|
||||
/* Mark the buffer as not in use so the FEC can take it. */
|
||||
nbuf_tx_release( pNBuf );
|
||||
/* Indicate that a new transmit buffer has been produced. */
|
||||
MCF_FEC_TDAR = 1;
|
||||
#if LINK_STATS
|
||||
lwip_stats.link.xmit++;
|
||||
#endif
|
||||
res = ERR_OK;
|
||||
}
|
||||
|
||||
sys_sem_signal( fecif->tx_sem );
|
||||
#if ETH_PAD_SIZE
|
||||
buf_header( p, ETH_PAD_SIZE );
|
||||
#endif
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
/* This function is called by the TCP/IP stack when an IP packet should be
|
||||
* sent. It uses the ethernet ARP module provided by lwIP to resolve the
|
||||
* destination MAC address. The ARP module will later call our low level
|
||||
* output function mcf523xfec_output_raw.
|
||||
*/
|
||||
err_t
|
||||
mcf523xfec_output( struct netif * netif, struct pbuf * p, struct ip_addr * ipaddr )
|
||||
{
|
||||
err_t res;
|
||||
mcf523xfec_if_t *fecif = netif->state;
|
||||
|
||||
FEC_DEBUG_TX_TIMING( 1 );
|
||||
/* Make sure only one thread is in this function. */
|
||||
sys_sem_wait( fecif->tx_sem );
|
||||
res = etharp_output( netif, ipaddr, p );
|
||||
FEC_DEBUG_TX_TIMING( 0 );
|
||||
return res;
|
||||
}
|
||||
|
||||
void
|
||||
mcf523xfec_rx_task( void *arg )
|
||||
{
|
||||
mcf523xfec_if_t *fecif = arg;
|
||||
struct pbuf *p, *q;
|
||||
nbuf_t *pNBuf;
|
||||
uint8 *pPayLoad;
|
||||
|
||||
do
|
||||
{
|
||||
sys_sem_wait( fecif->rx_sem );
|
||||
while( nbuf_rx_next_ready( ) )
|
||||
{
|
||||
pNBuf = nbuf_rx_allocate( );
|
||||
if( pNBuf != NULL )
|
||||
{
|
||||
LWIP_ASSERT( "mcf523xfec_rx_task: pNBuf->status & RX_BD_L ",
|
||||
pNBuf->status & RX_BD_L );
|
||||
|
||||
/* This flags indicate that the frame has been damaged. In
|
||||
* this case we must update the link stats if enabled and
|
||||
* remove the frame from the FEC. */
|
||||
if ( pNBuf->status & ( RX_BD_LG | RX_BD_NO |
|
||||
RX_BD_CR | RX_BD_OV ) )
|
||||
{
|
||||
#ifdef LINK_STATS
|
||||
lwip_stats.link.drop++;
|
||||
if ( pNBuf->status & RX_BD_LG)
|
||||
{
|
||||
lwip_stats.link.lenerr++;
|
||||
}
|
||||
else if ( pNBuf->status & ( RX_BD_NO | RX_BD_OV ) )
|
||||
{
|
||||
lwip_stats.link.err++;
|
||||
}
|
||||
else
|
||||
{
|
||||
lwip_stats.link.chkerr++;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
/* The frame must no be valid. Perform some checks to see if the FEC
|
||||
* driver is working correctly.
|
||||
*/
|
||||
LWIP_ASSERT( "mcf523xfec_rx_task: pNBuf->length != 0", pNBuf->length != 0 );
|
||||
p = pbuf_alloc( PBUF_RAW, pNBuf->length, PBUF_POOL );
|
||||
if( p != NULL )
|
||||
{
|
||||
#if ETH_PAD_SIZE
|
||||
pbuf_header( p, -ETH_PAD_SIZE );
|
||||
#endif
|
||||
pPayLoad = pNBuf->data;
|
||||
for( q = p; q != NULL; q = q->next )
|
||||
{
|
||||
memcpy( q->payload, pPayLoad, q->len );
|
||||
pPayLoad += q->len;
|
||||
}
|
||||
#if ETH_PAD_SIZE
|
||||
pbuf_header( p, ETH_PAD_SIZE );
|
||||
#endif
|
||||
|
||||
/* Ethernet frame received. Handling it is not device
|
||||
* dependent and therefore done in another function.
|
||||
*/
|
||||
eth_input( fecif->netif, p );
|
||||
}
|
||||
}
|
||||
nbuf_rx_release( pNBuf );
|
||||
|
||||
/* Tell the HW that there are new free RX buffers. */
|
||||
MCF_FEC_RDAR = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
#if LINK_STATS
|
||||
lwip_stats.link.memerr++;
|
||||
lwip_stats.link.drop++;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
/* Set RX Debug PIN to low since handling of next frame is possible. */
|
||||
FEC_DEBUG_RX_TIMING( 0 );
|
||||
}
|
||||
while( 1 );
|
||||
}
|
||||
|
||||
void
|
||||
eth_input( struct netif *netif, struct pbuf *p )
|
||||
{
|
||||
struct eth_hdr *eth_hdr = p->payload;
|
||||
|
||||
LWIP_ASSERT( "eth_input: p != NULL ", p != NULL );
|
||||
|
||||
switch ( htons( eth_hdr->type ) )
|
||||
{
|
||||
case ETHTYPE_IP:
|
||||
/* Pass to ARP layer. */
|
||||
etharp_ip_input( netif, p );
|
||||
|
||||
/* Skip Ethernet header. */
|
||||
pbuf_header( p, ( s16_t ) - sizeof( struct eth_hdr ) );
|
||||
|
||||
/* Pass to network layer. */
|
||||
netif->input( p, netif );
|
||||
break;
|
||||
|
||||
case ETHTYPE_ARP:
|
||||
/* Pass to ARP layer. */
|
||||
etharp_arp_input( netif, ( struct eth_addr * )netif->hwaddr, p );
|
||||
break;
|
||||
|
||||
default:
|
||||
pbuf_free( p );
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
mcf523xfec_rx_irq( void )
|
||||
{
|
||||
static portBASE_TYPE xNeedSwitch = pdFALSE;
|
||||
|
||||
/* Workaround GCC if frame pointers are enabled. This is an ISR and
|
||||
* we must not modify the stack before portENTER_SWITCHING_ISR( )
|
||||
* has been called. */
|
||||
#if _GCC_USES_FP == 1
|
||||
asm volatile ( "unlk %fp\n\t" );
|
||||
#endif
|
||||
|
||||
/* This ISR can cause a context switch, so the first statement must be
|
||||
* a call to the portENTER_SWITCHING_ISR() macro.
|
||||
*/
|
||||
portENTER_SWITCHING_ISR( );
|
||||
|
||||
/* Set Debug PIN to high to measure RX latency. */
|
||||
FEC_DEBUG_RX_TIMING( 1 );
|
||||
|
||||
/* Clear FEC RX Event from the Event Register (by writing 1) */
|
||||
if( MCF_FEC_EIR & ( MCF_FEC_EIR_RXB | MCF_FEC_EIR_RXF ) )
|
||||
{
|
||||
/* Clear interrupt from EIR register immediately */
|
||||
MCF_FEC_EIR = ( MCF_FEC_EIR_RXB | MCF_FEC_EIR_RXF );
|
||||
xNeedSwitch = xSemaphoreGiveFromISR( fecif_g->rx_sem, pdFALSE );
|
||||
}
|
||||
portEXIT_SWITCHING_ISR( xNeedSwitch );
|
||||
}
|
||||
|
||||
void
|
||||
mcf523xfec_reset( mcf523xfec_if_t * fecif )
|
||||
{
|
||||
extern void ( *__RAMVEC[] ) ( );
|
||||
|
||||
int old_ipl = asm_set_ipl( 7 );
|
||||
|
||||
/* Reset the FEC - equivalent to a hard reset */
|
||||
MCF_FEC_ECR = MCF_FEC_ECR_RESET;
|
||||
|
||||
/* Wait for the reset sequence to complete */
|
||||
while( MCF_FEC_ECR & MCF_FEC_ECR_RESET );
|
||||
|
||||
/* Disable all FEC interrupts by clearing the EIMR register */
|
||||
MCF_FEC_EIMR = 0;
|
||||
|
||||
/* Clear any interrupts by setting all bits in the EIR register */
|
||||
MCF_FEC_EIR = 0xFFFFFFFFUL;
|
||||
|
||||
/* Configure Interrupt vectors. */
|
||||
__RAMVEC[MCF_FEC_VEC_RXF] = mcf523xfec_rx_irq;
|
||||
|
||||
/* Set the source address for the controller */
|
||||
MCF_FEC_PALR =
|
||||
( fecif->self->addr[0] << 24U ) | ( fecif->self->addr[1] << 16U ) |
|
||||
( fecif->self->addr[2] << 8U ) | ( fecif->self->addr[3] << 0U );
|
||||
MCF_FEC_PAUR = ( fecif->self->addr[4] << 24U ) | ( fecif->self->addr[5] << 16U );
|
||||
|
||||
/* Initialize the hash table registers */
|
||||
MCF_FEC_IAUR = 0;
|
||||
MCF_FEC_IALR = 0;
|
||||
|
||||
/* Set Receive Buffer Size */
|
||||
#if RX_BUFFER_SIZE != 2048
|
||||
#error "RX_BUFFER_SIZE must be set to 2048 for safe FEC operation."
|
||||
#endif
|
||||
MCF_FEC_EMRBR = RX_BUFFER_SIZE - 1;
|
||||
|
||||
/* Point to the start of the circular Rx buffer descriptor queue */
|
||||
MCF_FEC_ERDSR = nbuf_get_start( NBUF_RX );
|
||||
|
||||
/* Point to the start of the circular Tx buffer descriptor queue */
|
||||
MCF_FEC_ETDSR = nbuf_get_start( NBUF_TX );
|
||||
|
||||
/* Set the tranceiver interface to MII mode */
|
||||
MCF_FEC_RCR = MCF_FEC_RCR_MAX_FL( MCF_FEC_MTU ) | MCF_FEC_RCR_MII_MODE;
|
||||
|
||||
/* Set MII Speed Control Register for 2.5Mhz */
|
||||
MCF_FEC_MSCR = MCF_FEC_MSCR_MII_SPEED( FSYS_2 / ( 2UL * 2500000UL ) );
|
||||
|
||||
/* Only operate in half-duplex, no heart beat control */
|
||||
MCF_FEC_TCR = 0;
|
||||
|
||||
/* Enable Debug support */
|
||||
FEC_DEBUG_INIT;
|
||||
FEC_DEBUG_RX_TIMING( 0 );
|
||||
FEC_DEBUG_TX_TIMING( 0 );
|
||||
( void )asm_set_ipl( old_ipl );
|
||||
}
|
||||
|
||||
void
|
||||
mcf523xfec_get_mac( mcf523xfec_if_t * hw, struct eth_addr *mac )
|
||||
{
|
||||
int i;
|
||||
static const struct eth_addr mac_default = {
|
||||
{0x00, 0xCF, 0x52, 0x35, 0x00, 0x01}
|
||||
};
|
||||
|
||||
( void )hw;
|
||||
|
||||
for( i = 0; i < ETH_ADDR_LEN; i++ )
|
||||
{
|
||||
mac->addr[i] = mac_default.addr[i];
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
mcf523xfec_enable( mcf523xfec_if_t * fecif )
|
||||
{
|
||||
( void )fecif;
|
||||
|
||||
int old_ipl = asm_set_ipl( 7 );
|
||||
|
||||
/* Configure I/O pins for the FEC. */
|
||||
MCF_GPIO_PAR_FECI2C = ( MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC | MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC );
|
||||
|
||||
/* Allow interrupts by setting IMR register */
|
||||
MCF_FEC_EIMR = MCF_FEC_EIMR_RXF;
|
||||
|
||||
/* Configure the interrupt controller. */
|
||||
MCF_INTC0_ICR27 = ( MCF_INTC0_ICRn_IL( MCF_FEC_INT_LEVEL ) |
|
||||
MCF_INTC0_ICRn_IP( MCF_FEC_INT_PRIORITY ) );
|
||||
MCF_INTC0_IMRL &= ~( MCF_INTC0_IMRL_INT_MASK27 | MCF_INTC0_IMRL_MASKALL );
|
||||
|
||||
/* Enable FEC */
|
||||
MCF_FEC_ECR = MCF_FEC_ECR_ETHER_EN;
|
||||
|
||||
/* Indicate that there have been empty receive buffers produced */
|
||||
MCF_FEC_RDAR = 1;
|
||||
( void )asm_set_ipl( old_ipl );
|
||||
}
|
||||
|
||||
void
|
||||
mcf523xfec_disable( mcf523xfec_if_t * fecif )
|
||||
{
|
||||
( void )fecif;
|
||||
|
||||
int old_ipl = asm_set_ipl( 7 );
|
||||
|
||||
/* Set the Graceful Transmit Stop bit */
|
||||
MCF_FEC_TCR = ( MCF_FEC_TCR | MCF_FEC_TCR_GTS );
|
||||
|
||||
/* Wait for the current transmission to complete */
|
||||
while( !( MCF_FEC_EIR & MCF_FEC_EIR_GRA ) );
|
||||
|
||||
/* Clear the GRA event */
|
||||
MCF_FEC_EIR = MCF_FEC_EIR_GRA;
|
||||
|
||||
/* Disable the FEC */
|
||||
MCF_FEC_ECR = 0;
|
||||
|
||||
/* Disable all FEC interrupts by clearing the IMR register */
|
||||
MCF_FEC_EIMR = 0;
|
||||
|
||||
/* Unconfigure the interrupt controller. */
|
||||
MCF_INTC0_ICR27 = MCF_INTC0_ICRn_IL( 0 ) | MCF_INTC0_ICRn_IP( 0 );
|
||||
MCF_INTC0_IMRL |= MCF_INTC0_IMRL_INT_MASK27;
|
||||
|
||||
/* Clear the GTS bit so frames can be tranmitted when restarted */
|
||||
MCF_FEC_TCR = ( MCF_FEC_TCR & ~MCF_FEC_TCR_GTS );
|
||||
|
||||
/* Disable I/O pins used by the FEC. */
|
||||
MCF_GPIO_PAR_FECI2C &= ~( MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC |
|
||||
MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC );
|
||||
( void )asm_set_ipl( old_ipl );
|
||||
}
|
||||
|
||||
err_t
|
||||
mcf523xfec_init( struct netif *netif )
|
||||
{
|
||||
err_t res;
|
||||
|
||||
mcf523xfec_if_t *fecif = mem_malloc( sizeof( mcf523xfec_if_t ) );
|
||||
|
||||
if( fecif != NULL )
|
||||
{
|
||||
/* Global copy used in ISR. */
|
||||
fecif_g = fecif;
|
||||
fecif->self = ( struct eth_addr * )&netif->hwaddr[0];
|
||||
fecif->netif = netif;
|
||||
fecif->tx_sem = NULL;
|
||||
fecif->rx_sem = NULL;
|
||||
|
||||
if( ( fecif->tx_sem = sys_sem_new( 1 ) ) == NULL )
|
||||
{
|
||||
res = ERR_MEM;
|
||||
}
|
||||
else if( ( fecif->rx_sem = sys_sem_new( 0 ) ) == NULL )
|
||||
{
|
||||
res = ERR_MEM;
|
||||
}
|
||||
else if( sys_thread_new( mcf523xfec_rx_task, fecif, TASK_PRIORITY ) == NULL )
|
||||
{
|
||||
res = ERR_MEM;
|
||||
}
|
||||
else
|
||||
{
|
||||
netif->state = fecif;
|
||||
netif->name[0] = 'C';
|
||||
netif->name[1] = 'F';
|
||||
netif->hwaddr_len = ETH_ADDR_LEN;
|
||||
netif->mtu = MCF_FEC_MTU;
|
||||
netif->flags = NETIF_FLAG_BROADCAST;
|
||||
netif->output = mcf523xfec_output;
|
||||
netif->linkoutput = mcf523xfec_output_raw;
|
||||
|
||||
nbuf_init( );
|
||||
mcf523xfec_get_mac( fecif, fecif->self );
|
||||
mcf523xfec_reset( fecif );
|
||||
mcf523xfec_enable( fecif );
|
||||
|
||||
etharp_init( );
|
||||
sys_timeout( ARP_TMR_INTERVAL, arp_timer, NULL );
|
||||
|
||||
res = ERR_OK;
|
||||
}
|
||||
|
||||
if( res != ERR_OK )
|
||||
{
|
||||
free( fecif );
|
||||
if( fecif->tx_sem != NULL )
|
||||
{
|
||||
mem_free( fecif->tx_sem );
|
||||
}
|
||||
if( fecif->rx_sem != NULL )
|
||||
{
|
||||
mem_free( fecif->rx_sem );
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
res = ERR_MEM;
|
||||
}
|
||||
|
||||
return res;
|
||||
}
|
||||
@ -0,0 +1,40 @@
|
||||
/*
|
||||
* Copyright (c) 2006 Christian Walter
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
* Author: Christian Walter <wolti@sil.at>
|
||||
*
|
||||
* File: $Id: fec.h,v 1.1 2006/08/29 00:04:06 wolti Exp $
|
||||
*/
|
||||
|
||||
#ifndef _FEC_H
|
||||
#define _FEC_H
|
||||
|
||||
/* ------------------------ Defines --------------------------------------- */
|
||||
|
||||
/* ------------------------ Prototypes ------------------------------------ */
|
||||
err_t mcf523xfec_init( struct netif *netif );
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,186 @@
|
||||
/*
|
||||
* Network buffer code based on the MCF523x examples from Freescale.
|
||||
*
|
||||
* File: $Id: nbuf.c,v 1.2 2006/08/31 22:28:21 wolti Exp $
|
||||
*/
|
||||
|
||||
/* ------------------------ Platform includes ----------------------------- */
|
||||
#include "mcf5xxx.h"
|
||||
#include "mcf523x.h"
|
||||
|
||||
#include "nbuf.h"
|
||||
|
||||
/* ------------------------ Static variables ------------------------------ */
|
||||
|
||||
/* Buffer descriptor indexes */
|
||||
static uint8 tx_bd_idx;
|
||||
static uint8 rx_bd_idx;
|
||||
|
||||
/* Buffer Descriptors -- must be aligned on a 4-byte boundary but a
|
||||
* 16-byte boundary is recommended. */
|
||||
static nbuf_t tx_nbuf[sizeof( nbuf_t ) * NUM_TXBDS] ATTR_FECMEM;
|
||||
static nbuf_t rx_nbuf[sizeof( nbuf_t ) * NUM_RXBDS] ATTR_FECMEM;
|
||||
|
||||
/* Data Buffers -- must be aligned on a 16-byte boundary. */
|
||||
static uint8 tx_buf[TX_BUFFER_SIZE * NUM_TXBDS] ATTR_FECMEM;
|
||||
static uint8 rx_buf[RX_BUFFER_SIZE * NUM_RXBDS] ATTR_FECMEM;
|
||||
|
||||
/* ------------------------ Start implementation -------------------------- */
|
||||
void
|
||||
nbuf_init( )
|
||||
{
|
||||
|
||||
uint8 i;
|
||||
|
||||
/* Initialize receive descriptor ring */
|
||||
for( i = 0; i < NUM_RXBDS; i++ )
|
||||
{
|
||||
rx_nbuf[i].status = RX_BD_E;
|
||||
rx_nbuf[i].length = 0;
|
||||
rx_nbuf[i].data = &rx_buf[i * RX_BUFFER_SIZE];
|
||||
}
|
||||
|
||||
/* Set the Wrap bit on the last one in the ring */
|
||||
rx_nbuf[NUM_RXBDS - 1].status |= RX_BD_W;
|
||||
|
||||
/* Initialize transmit descriptor ring */
|
||||
for( i = 0; i < NUM_TXBDS; i++ )
|
||||
{
|
||||
tx_nbuf[i].status = TX_BD_L | TX_BD_TC;
|
||||
tx_nbuf[i].length = 0;
|
||||
tx_nbuf[i].data = &tx_buf[i * TX_BUFFER_SIZE];
|
||||
}
|
||||
|
||||
/* Set the Wrap bit on the last one in the ring */
|
||||
tx_nbuf[NUM_TXBDS - 1].status |= TX_BD_W;
|
||||
|
||||
/* Initialize the buffer descriptor indexes */
|
||||
tx_bd_idx = rx_bd_idx = 0;
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
/********************************************************************/
|
||||
uint32
|
||||
nbuf_get_start( uint8 direction )
|
||||
{
|
||||
/*
|
||||
* Return the address of the first buffer descriptor in the ring.
|
||||
* This routine is needed by the FEC of the MPC860T , MCF5282, and MCF523x
|
||||
* in order to write the Rx/Tx descriptor ring start registers
|
||||
*/
|
||||
switch ( direction )
|
||||
{
|
||||
case NBUF_RX:
|
||||
return ( uint32 ) rx_nbuf;
|
||||
case NBUF_TX:
|
||||
default:
|
||||
return ( uint32 ) tx_nbuf;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/********************************************************************/
|
||||
nbuf_t *
|
||||
nbuf_rx_allocate( )
|
||||
{
|
||||
/* This routine alters shared data. Disable interrupts! */
|
||||
int old_ipl = asm_set_ipl( 6 );
|
||||
|
||||
/* Return a pointer to the next empty Rx Buffer Descriptor */
|
||||
int i = rx_bd_idx;
|
||||
|
||||
|
||||
/* Check to see if the ring of BDs is full */
|
||||
if( rx_nbuf[i].status & RX_BD_INUSE )
|
||||
return NULL;
|
||||
|
||||
/* Mark the buffer as in use */
|
||||
rx_nbuf[i].status |= RX_BD_INUSE;
|
||||
|
||||
/* increment the circular index */
|
||||
rx_bd_idx = ( uint8 ) ( ( rx_bd_idx + 1 ) % NUM_RXBDS );
|
||||
|
||||
/* Restore previous IPL */
|
||||
asm_set_ipl( old_ipl );
|
||||
|
||||
return &rx_nbuf[i];
|
||||
}
|
||||
|
||||
|
||||
/********************************************************************/
|
||||
nbuf_t *
|
||||
nbuf_tx_allocate( )
|
||||
{
|
||||
/* This routine alters shared data. Disable interrupts! */
|
||||
int old_ipl = asm_set_ipl( 6 );
|
||||
|
||||
/* Return a pointer to the next empty Tx Buffer Descriptor */
|
||||
int i = tx_bd_idx;
|
||||
|
||||
/* Check to see if ring of BDs is full */
|
||||
if( ( tx_nbuf[i].status & TX_BD_INUSE ) || ( tx_nbuf[i].status & TX_BD_R ) )
|
||||
return NULL;
|
||||
|
||||
/* Mark the buffer as Ready (in use) */
|
||||
/* FEC must set R bit in transmit routine */
|
||||
tx_nbuf[i].status |= TX_BD_INUSE;
|
||||
|
||||
/* increment the circular index */
|
||||
tx_bd_idx = ( uint8 ) ( ( tx_bd_idx + 1 ) % NUM_TXBDS );
|
||||
|
||||
/* Restore previous IPL */
|
||||
asm_set_ipl( old_ipl );
|
||||
|
||||
return &tx_nbuf[i];
|
||||
}
|
||||
|
||||
|
||||
/********************************************************************/
|
||||
void
|
||||
nbuf_rx_release( nbuf_t * pNbuf )
|
||||
{
|
||||
/* This routine alters shared data. Disable interrupts! */
|
||||
int old_ipl = asm_set_ipl( 6 );
|
||||
|
||||
/* Mark the buffer as empty and not in use */
|
||||
pNbuf->status |= RX_BD_E;
|
||||
pNbuf->status &= ~RX_BD_INUSE;
|
||||
|
||||
/* Restore previous IPL */
|
||||
asm_set_ipl( old_ipl );
|
||||
}
|
||||
|
||||
/********************************************************************/
|
||||
void
|
||||
nbuf_tx_release( nbuf_t * pNbuf )
|
||||
{
|
||||
/* This routine alters shared data. Disable interrupts! */
|
||||
int old_ipl = asm_set_ipl( 6 );
|
||||
|
||||
/* Mark the buffer as not in use */
|
||||
pNbuf->status &= ~TX_BD_INUSE;
|
||||
|
||||
/* Restore previous IPL */
|
||||
asm_set_ipl( old_ipl );
|
||||
}
|
||||
|
||||
/********************************************************************/
|
||||
int
|
||||
nbuf_rx_next_ready( )
|
||||
{
|
||||
/****************************************************************
|
||||
This function checks the EMPTY bit of the next Rx buffer to be
|
||||
allocated. If the EMPTY bit is cleared, then the next buffer in
|
||||
the ring has been filled by the FEC and has not already been
|
||||
allocated and passed up the stack. In this case, the next buffer
|
||||
in the ring is ready to be allocated. Otherwise, the buffer is
|
||||
either empty or not empty but still in use by a higher level
|
||||
protocol. The FEC receive routine uses this function to determine
|
||||
if multiple buffers where filled by the FEC during a single
|
||||
interrupt event.
|
||||
****************************************************************/
|
||||
|
||||
return ( !( rx_nbuf[rx_bd_idx].status & RX_BD_E ) );
|
||||
}
|
||||
@ -0,0 +1,95 @@
|
||||
/*
|
||||
* Network buffer code based on the MCF523x examples from Freescale.
|
||||
*
|
||||
* Freescale explicitly grants the redistribution and modification
|
||||
* of these source files. The complete licensing information is
|
||||
* available in the file LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* Modifications Copyright (c) 2006 Christian Walter <wolti@sil.at>
|
||||
*
|
||||
* File: $Id: nbuf.h,v 1.3 2006/09/24 22:50:23 wolti Exp $
|
||||
*/
|
||||
|
||||
#ifndef _NBUF_H
|
||||
#define _NBUF_H
|
||||
|
||||
/* ------------------------ Defines --------------------------------------- */
|
||||
|
||||
#ifdef __GNUC__
|
||||
#define ATTR_FECMEM \
|
||||
__attribute__((section(".nbuf"),aligned(16)))
|
||||
#endif
|
||||
|
||||
#define NBUF_RX ( 1 )
|
||||
#define NBUF_TX ( 0 )
|
||||
|
||||
/* We set the receiver buffers to the maximum size the FEC supports ( See
|
||||
* MCF5235 reference manual 19.2.5.1.2 - Driver/DMA Operation with Receive
|
||||
* BDs). This gives us the benefit that any frame fits into one buffer. A
|
||||
* maximum size of 2047 is guaranteed by the FEC and 2048 is therefore a
|
||||
* safe value.
|
||||
* Note: The value MUST be dividable by 16!
|
||||
*/
|
||||
#define RX_BUFFER_SIZE ( 2048 )
|
||||
|
||||
/* Size of the transmit buffers. If you set this value to small all frames
|
||||
* greater than this size will be dropped. The value 1520 was choosen because
|
||||
* it is bigger than the FEC MTU (1518) and is dividable by 16.
|
||||
* Note: The value MUST be dividable by 16! */
|
||||
#define TX_BUFFER_SIZE ( 1520 )
|
||||
|
||||
/* Number of Receive and Transmit Buffers and Buffer Descriptors */
|
||||
#define NUM_RXBDS ( 2 )
|
||||
#define NUM_TXBDS ( 2 )
|
||||
|
||||
/* ------------------------ Defines ( Buffer Descriptor Flags )------------ */
|
||||
|
||||
#define TX_BD_R ( 0x8000 )
|
||||
#define TX_BD_INUSE ( 0x4000 )
|
||||
#define TX_BD_TO1 ( 0x4000 )
|
||||
#define TX_BD_W ( 0x2000 )
|
||||
#define TX_BD_TO2 ( 0x1000 )
|
||||
#define TX_BD_L ( 0x0800 )
|
||||
#define TX_BD_TC ( 0x0400 )
|
||||
#define TX_BD_DEF ( 0x0200 )
|
||||
#define TX_BD_HB ( 0x0100 )
|
||||
#define TX_BD_LC ( 0x0080 )
|
||||
#define TX_BD_RL ( 0x0040 )
|
||||
#define TX_BD_UN ( 0x0002 )
|
||||
#define TX_BD_CSL ( 0x0001 )
|
||||
|
||||
#define RX_BD_E ( 0x8000 )
|
||||
#define RX_BD_INUSE ( 0x4000 )
|
||||
#define RX_BD_R01 ( 0x4000 )
|
||||
#define RX_BD_W ( 0x2000 )
|
||||
#define RX_BD_R02 ( 0x1000 )
|
||||
#define RX_BD_L ( 0x0800 )
|
||||
#define RX_BD_M ( 0x0100 )
|
||||
#define RX_BD_BC ( 0x0080 )
|
||||
#define RX_BD_MC ( 0x0040 )
|
||||
#define RX_BD_LG ( 0x0020 )
|
||||
#define RX_BD_NO ( 0x0010 )
|
||||
#define RX_BD_SH ( 0x0008 )
|
||||
#define RX_BD_CR ( 0x0004 )
|
||||
#define RX_BD_OV ( 0x0002 )
|
||||
#define RX_BD_TR ( 0x0001 )
|
||||
|
||||
/* ------------------------ Type definitions ------------------------------ */
|
||||
typedef struct
|
||||
{
|
||||
uint16 status; /* control and status */
|
||||
uint16 length; /* transfer length */
|
||||
uint8 *data; /* buffer address */
|
||||
} nbuf_t;
|
||||
|
||||
/* ------------------------ Prototypes ------------------------------------ */
|
||||
|
||||
void nbuf_init( void );
|
||||
uint32 nbuf_get_start( uint8 );
|
||||
nbuf_t *nbuf_rx_allocate( void );
|
||||
nbuf_t *nbuf_tx_allocate( void );
|
||||
void nbuf_rx_release( nbuf_t * );
|
||||
void nbuf_tx_release( nbuf_t * );
|
||||
int nbuf_rx_next_ready( void );
|
||||
|
||||
#endif
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue