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148 lines
6.4 KiB
C
148 lines
6.4 KiB
C
16 years ago
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/*
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* File: mii.h
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* Purpose:
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*
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* Notes:
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*/
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#ifndef _MII_H_
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#define _MII_H_
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/********************************************************************/
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/* Timeout for MII communications */
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#define FEC_MII_TIMEOUT 0x10000
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/********************************************************************/
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//Fucntion Protoypes
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int FEC_Mii_Write(int, int, int);
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int FEC_Mii_Read(int, int, unsigned short*);
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void FEC_Mii_Init(void);
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void fec_mii_reg_printf(void);
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/********************************************************************/
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//Register Mask and Other
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//===============
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/* Definition of allowed values for MDCSEL */
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#define MII_MDCSEL(x) x/5000000
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#define MII_WRITE 0x01
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#define MII_READ 0x02
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#define TCMD_START 0x01 /* Transmit buffer frame */
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#define TCMD_PAUSE 0x02 /* Transmit PAUSE frame */
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#define TCMD_ABORT 0x03 /* Abort transmission */
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/* PHY registers symbolic names */
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/* (located in MII memory map, accessible through MDIO) */
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#define PHY_REG_CR 0x00 /* Control Register */
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#define PHY_REG_SR 0x01 /* Status Register */
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#define PHY_REG_ID1 0x02 /* PHY Identification Register 1 */
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#define PHY_REG_ID2 0x03 /* PHY Identification Register 2 */
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#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement Register */
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#define PHY_REG_ANLPAR 0x05 /* Auto-Negotiation Link Partner Ability Register */
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#define PHY_REG_ER 0x06 /* Auto-Negotiation Expansion Register */
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#define PHY_REG_NPTR 0x07 /* Auto-Negotiation Next Page Transfer Register */
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#define PHY_REG_IR 0x10 /* Interrupt Register */
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#define PHY_REG_PSR 0x11 /* Proprietary Status Register */
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#define PHY_REG_PCR 0x12 /* Proprietary Control Register */
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#define PHY_REG_10BTBC 0x13 /* 10Base-T Bypass Control Register */
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#define PHY_REG_100BXBC 0x14 /* 100Base-X Bypass Control Register */
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#define PHY_REG_ADDR 0x15 /* Test & Trim Control Register */
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#define PHY_REG_DSPRC 0x17 /* DSP Reset Control */
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#define PHY_REG_DSPRR1 0x18 /* 100Base-X DSP Read Registers */
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#define PHY_REG_DSPRR2 0x19
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#define PHY_REG_DSPRR3 0x1A
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#define PHY_REG_DSPWR1 0x1B /* 100Base-X DSP Write Registers */
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#define PHY_REG_DSPWR2 0x1C
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#define PHY_REG_DSPWR3 0x1D
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/* PHY registers structure */
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/* 0 - Control Register */
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#define PHY_R0_RESET 0x8000 /* Reset */
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#define PHY_R0_LB 0x4000 /* Loop Back */
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#define PHY_R0_DR 0x2000 /* Data Rate (100Mb/s) */
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#define PHY_R0_ANE 0x1000 /* Auto-Negotiation Enable */
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#define PHY_R0_PD 0x0800 /* Power Down */
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#define PHY_R0_ISOLATE 0x0400 /* Isolate (MII is disconnected) */
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#define PHY_R0_RAN 0x0200 /* Restart Auto-Negotiation */
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#define PHY_R0_DPLX 0x0100 /* Duplex (Full duplex) */
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#define PHY_R0_CT 0x0080 /* Collision Test (Enable) */
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/* 1 - Status Register */
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#define PHY_R1_100T4 0x8000 /* 100BASET4 Supported */
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#define PHY_R1_100F 0x4000 /* 100Mb/s Full Duplex Supported */
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#define PHY_R1_100H 0x2000 /* 100Mb/s Half Duplex Supported */
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#define PHY_R1_10F 0x1000 /* 10Mb/s Full Duplex Supported */
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#define PHY_R1_10H 0x0800 /* 10Mb/s Half Duplex Supported */
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#define PHY_R1_SUP 0x0040 /* MI Preamble Supression (capable of) */
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#define PHY_R1_ANC 0x0020 /* Auto Negotiation Complete */
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#define PHY_R1_RF 0x0010 /* Remote Fault */
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#define PHY_R1_ANA 0x0008 /* Auto-Negotiation Ability (present) */
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#define PHY_R1_LS 0x0004 /* Link Status (Link is Up) */
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#define PHY_R1_JD 0x0002 /* Jabber Detect (detected) */
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#define PHY_R1_EC 0x0001 /* Extended Capability (regs 2 to 31 exists) */
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/* 2 - PHY Identifier Register 1 */
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/* 3 - PHY Identifier Register 2 */
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/* read only - contains Manufacturer's info etc.
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see documentation for the detailed description */
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/* 4 - Auto Negotiation Advertisement Register */
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#define PHY_R4_NP 0x8000 /* Next Page (capable of sending next pages) */
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#define PHY_R4_RF 0x2000 /* Remote Fault */
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#define PHY_R4_FC 0x0400 /* Flow Control */
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#define PHY_R4_100F 0x0100 /* 100Base-TX Full Duplex Capable */
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#define PHY_R4_100H 0x0080 /* 100Base-TX Half Duplex Capable */
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#define PHY_R4_10F 0x0040 /* 10Base-T Full Duplex Capable */
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#define PHY_R4_10H 0x0020 /* 10Base-T Half Duplex Capable */
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/* bits 4 to 0 are Selector Field (IEEE Std 802.3 = 00001) */
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/* 5 - Auto Negotiation Link Partner Ability Register (Base Page & Next Page) */
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/* read only - please consult PHY documentation */
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#define PHY_R5_FCTL 0x0400 /* 10Base-T Half Duplex Capable */
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/* 16 - Interrupt Control Register */
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#define PHY_R16_ACKIE 0x4000 //Acknowledge Bit Received Interrupt Enable
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#define PHY_R16_PRIE 0x2000 //Page Received INT Enable
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#define PHY_R16_LCIE 0x1000 //Link Changed Enable
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#define PHY_R16_ANIE 0x0800 //Auto-Negotiation Changed Enable
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#define PHY_R16_PDFIE 0x0400 //Parallel Detect Fault Enable
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#define PHY_R16_RFIE 0x0200 //Remote Fault Interrupt Enable
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#define PHY_R16_JABIE 0x0100 //Jabber Interrupt Enable
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#define PHY_R16_ACKR 0x0040 //Acknowledge Bit Received Interrupt
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#define PHY_R16_PGR 0x0020 //Page Received
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#define PHY_R16_LKC 0x0010 //Link Changed
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#define PHY_R16_ANC 0x0008 //Auto-Negotiation Changed
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#define PHY_R16_PDF 0x0004 //Parallel Detect Fault
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#define PHY_R16_RMTF 0x0002 //Remote Fault Interrupt
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#define PHY_R16_JABI 0x0001 //Jabber Interrupt
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////Proprietary Status Register
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#define PHY_R17_LNK 0x4000 //
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#define PHY_R17_DPM 0x2000 //Duplex Mode
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#define PHY_R17_SPD 0x1000 //Speed
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#define PHY_R17_ANNC 0x0400 //Auto-Negotiation Complete
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#define PHY_R17_PRCVD 0x0200 //
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#define PHY_R17_ANCM 0x0100 // Auto-Negotiation (A-N) Common Operating Mode
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#define PHY_R17_PLR 0x0020 //
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/* Bit definitions and macros for MCF_FEC_MMFR */
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#define FEC_MMFR_DATA(x) (((x)&0x0000FFFF)<<0)
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#define FEC_MMFR_TA(x) (((x)&0x00000003)<<16)
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#define FEC_MMFR_RA(x) (((x)&0x0000001F)<<18)
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#define FEC_MMFR_PA(x) (((x)&0x0000001F)<<23)
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#define FEC_MMFR_OP(x) (((x)&0x00000003)<<28)
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#define FEC_MMFR_ST(x) (((x)&0x00000003)<<30)
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#define FEC_MMFR_ST_01 (0x40000000)
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#define FEC_MMFR_OP_READ (0x20000000)
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#define FEC_MMFR_OP_WRITE (0x10000000)
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#define FEC_MMFR_TA_10 (0x00020000)
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/********************************************************************/
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#endif /* _MII_H_ */
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