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122 lines
4.3 KiB
C
122 lines
4.3 KiB
C
14 years ago
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/******************************************************************************
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* DISCLAIMER
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* Please refer to http://www.renesas.com/disclaimer
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******************************************************************************
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Copyright (C) 2008. Renesas Technology Corp., All Rights Reserved.
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*******************************************************************************
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* File Name : rsksh7216.h
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* Version : 1.00
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* Description : RSK 7216 board specific settings
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******************************************************************************
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* History : DD.MM.YYYY Version Description
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* : 06.10.2009 1.00 First Release
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******************************************************************************/
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#ifndef RSKRX62N_H
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#define RSKRX62N_H
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/******************************************************************************
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Includes <System Includes> , "Project Includes"
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******************************************************************************/
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/******************************************************************************
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Typedef definitions
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******************************************************************************/
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/******************************************************************************
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Macro definitions
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******************************************************************************/
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/* System Clock Settings */
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#define CLK_SRC_HOCO 0
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/* DETAIL THIS LATER !!!! */
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#if (CLK_SRC_HOCO == 0)
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/* External xtal and PLL circuit */
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#define XTAL_FREQUENCY (20000000L)
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#define PLL_MUL (8)
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#define PLL_INPUT_FREQ_DIV (2)
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#define ICLK_DIV (2)
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#define PCLK_DIV (8)
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#define BCLK_DIV (8)
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#define PLL_FREQUENCY (XTAL_FREQUENCY * (PLL_MUL / PLL_INPUT_FREQ_DIV))
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#define ICLK_FREQUENCY (PLL_FREQUENCY / ICLK_DIV)
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#define PCLK_FREQUENCY (PLL_FREQUENCY / PCLK_DIV)
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#define BCLK_FREQUENCY (PLL_FREQUENCY / BCLK_DIV)
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#else
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/* Internal high speed on-chip oscillator (HOCO) */
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#define XTAL_FREQUENCY (50000000L)
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#define PLL_MUL (1)
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#define PLL_INPUT_FREQ_DIV (1)
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#define ICLK_DIV (2)
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#define PCLK_DIV (8)
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#define BCLK_DIV (8)
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#define PLL_FREQUENCY (XTAL_FREQUENCY * (PLL_MUL / PLL_INPUT_FREQ_DIV))
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#define ICLK_FREQUENCY (PLL_FREQUENCY / ICLK_DIV)
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#define PCLK_FREQUENCY (PLL_FREQUENCY / PCLK_DIV)
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#define BCLK_FREQUENCY (PLL_FREQUENCY / BCLK_DIV)
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#endif
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#define CMT0_CLK_SELECT (512)
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/* General Values */
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#define LED_ON (0)
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#define LED_OFF (1)
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#define SET_BIT_HIGH (1)
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#define SET_BIT_LOW (0)
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#define SET_BYTE_HIGH (0xFF)
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#define SET_BYTE_LOW (0x00)
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/* Define switches to be polled if not available as interrupts */
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#define SW_ACTIVE FALSE
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#define SW1 PORT0.DR.BIT.B0
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#define SW2 PORT0.DR.BIT.B1
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#define SW3 PORT0.DR.BIT.B7
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#define SW1_DDR PORT0.DDR.BIT.B0
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#define SW2_DDR PORT0.DDR.BIT.B1
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#define SW3_DDR PORT0.DDR.BIT.B7
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#define SW1_ICR PORT0.ICR.BIT.B0
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#define SW2_ICR PORT0.ICR.BIT.B1
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#define SW3_ICR PORT0.ICR.BIT.B7
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/* LEDs */
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#define LED0 PORT1.PODR.BIT.B4
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#define LED1 PORT1.PODR.BIT.B5
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#define LED2 PORT1.PODR.BIT.B6
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#define LED3 PORT1.PODR.BIT.B7
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//#define LED4 PORT6.DR.BIT.B0
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//#define LED5 PORT7.DR.BIT.B3
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#define LED0_DDR PORT1.PDR.BIT.B4
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#define LED1_DDR PORT1.PDR.BIT.B5
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#define LED2_DDR PORT1.PDR.BIT.B6
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#define LED3_DDR PORT1.PDR.BIT.B7
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//#define LED4_DDR PORT6.DDR.BIT.B0
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//#define LED5_DDR PORT7.DDR.BIT.B3
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/* 2x8 segment LCD */
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#define INCLUDE_LCD 1
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#define LCD_RS PORTJ.PODR.BIT.B1
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#define LCD_EN PORTJ.PODR.BIT.B3
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#define LCD_DATA PORTH.PODR.BYTE
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#define LCD_RS_DDR PORTJ.PDR.BIT.B1
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#define LCD_EN_DDR PORTJ.PDR.BIT.B3
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#define LCD_DATA_DDR PORTH.PDR.BYTE
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/******************************************************************************
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Variable Externs
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******************************************************************************/
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/******************************************************************************
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Functions Prototypes
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******************************************************************************/
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/* RSKRX62N_H */
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#endif
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