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361 lines
13 KiB
C
361 lines
13 KiB
C
10 years ago
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/* --COPYRIGHT--,BSD
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* Copyright (c) 2014, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* * Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* --/COPYRIGHT--*/
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//*****************************************************************************
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//
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// mpu.c - Driver for the mpu Module.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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//! \addtogroup mpu_api mpu
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//! @{
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//
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//*****************************************************************************
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#include "inc/hw_regaccess.h"
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#include "inc/hw_memmap.h"
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#ifdef __MSP430_HAS_MPU__
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#include "mpu.h"
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#include <assert.h>
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//*****************************************************************************
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//
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// The following value is used by createTwoSegments, createThreeSegments to
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// check the user has passed a valid segmentation value. This value was
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// obtained from the User's Guide.
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//
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//*****************************************************************************
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#define MPU_MAX_SEG_VALUE 0x13C1
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void MPU_initTwoSegments(uint16_t baseAddress,
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uint16_t seg1boundary,
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uint8_t seg1accmask,
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uint8_t seg2accmask)
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{
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// Write MPU password to allow MPU register configuration
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HWREG16(baseAddress + OFS_MPUCTL0) = MPUPW | HWREG8(
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baseAddress + OFS_MPUCTL0);
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// Create two memory segmentations
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HWREG16(baseAddress + OFS_MPUSEGB1) = seg1boundary;
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HWREG16(baseAddress + OFS_MPUSEGB2) = seg1boundary;
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// Set access rights based on user's selection for segment1
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switch(seg1accmask)
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{
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case MPU_EXEC | MPU_READ:
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HWREG16(baseAddress + OFS_MPUSAM) &= ~MPUSEG1WE;
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HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG1XE + MPUSEG1RE;
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break;
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case MPU_READ | MPU_WRITE:
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HWREG16(baseAddress + OFS_MPUSAM) &= ~MPUSEG1XE;
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HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG1RE + MPUSEG1WE;
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break;
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case MPU_READ:
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HWREG16(baseAddress + OFS_MPUSAM) &= ~(MPUSEG1XE + MPUSEG1WE);
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HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG1RE;
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break;
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case MPU_EXEC | MPU_READ | MPU_WRITE:
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HWREG16(baseAddress +
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OFS_MPUSAM) |= (MPUSEG1XE + MPUSEG1WE + MPUSEG1RE);
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break;
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case MPU_NO_READ_WRITE_EXEC:
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HWREG16(baseAddress +
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OFS_MPUSAM) &= ~(MPUSEG1XE + MPUSEG1WE + MPUSEG1RE);
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break;
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default:
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break;
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}
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// Set access rights based on user's selection for segment2
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switch(seg2accmask)
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{
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case MPU_EXEC | MPU_READ:
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HWREG16(baseAddress + OFS_MPUSAM) &= ~(MPUSEG3WE + MPUSEG2WE);
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HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG3XE + MPUSEG3RE +
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MPUSEG2XE + MPUSEG2RE;
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break;
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case MPU_READ | MPU_WRITE:
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HWREG16(baseAddress + OFS_MPUSAM) &= ~(MPUSEG3XE + MPUSEG2XE);
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HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG3RE + MPUSEG3WE +
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MPUSEG2RE + MPUSEG2WE;
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break;
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case MPU_READ:
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HWREG16(baseAddress + OFS_MPUSAM) &= ~(MPUSEG3XE + MPUSEG3WE +
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MPUSEG2XE + MPUSEG2WE);
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HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG3RE + MPUSEG2RE;
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break;
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case MPU_EXEC | MPU_READ | MPU_WRITE:
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HWREG16(baseAddress + OFS_MPUSAM) |= (MPUSEG3XE + MPUSEG3WE +
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MPUSEG3RE + MPUSEG2XE +
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MPUSEG2WE + MPUSEG2RE);
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break;
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case MPU_NO_READ_WRITE_EXEC:
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HWREG16(baseAddress + OFS_MPUSAM) &= ~(MPUSEG3XE + MPUSEG3WE +
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MPUSEG3RE + MPUSEG2XE +
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MPUSEG2WE + MPUSEG2RE);
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break;
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default:
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break;
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}
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//Lock MPU to disable writing to all registers
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HWREG8(baseAddress + OFS_MPUCTL0_H) = 0x00;
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}
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void MPU_initThreeSegments(uint16_t baseAddress,
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MPU_initThreeSegmentsParam *param)
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{
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// Write MPU password to allow MPU register configuration
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HWREG16(baseAddress + OFS_MPUCTL0) = MPUPW | HWREG8(
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baseAddress + OFS_MPUCTL0);
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// Create two memory segmentations
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HWREG16(baseAddress + OFS_MPUSEGB1) = param->seg1boundary;
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HWREG16(baseAddress + OFS_MPUSEGB2) = param->seg2boundary;
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// Set access rights based on user's selection for segment1
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switch(param->seg1accmask)
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{
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case MPU_EXEC | MPU_READ:
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HWREG16(baseAddress + OFS_MPUSAM) &= ~MPUSEG1WE;
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HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG1XE + MPUSEG1RE;
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break;
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case MPU_READ | MPU_WRITE:
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HWREG16(baseAddress + OFS_MPUSAM) &= ~MPUSEG1XE;
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HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG1RE + MPUSEG1WE;
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break;
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case MPU_READ:
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HWREG16(baseAddress + OFS_MPUSAM) &= ~(MPUSEG1XE + MPUSEG1WE);
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HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG1RE;
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break;
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case MPU_EXEC | MPU_READ | MPU_WRITE:
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HWREG16(baseAddress +
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OFS_MPUSAM) |= (MPUSEG1XE + MPUSEG1WE + MPUSEG1RE);
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break;
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case MPU_NO_READ_WRITE_EXEC:
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HWREG16(baseAddress +
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OFS_MPUSAM) &= ~(MPUSEG1XE + MPUSEG1WE + MPUSEG1RE);
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break;
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default:
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break;
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}
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// Set access rights based on user's selection for segment2
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switch(param->seg2accmask)
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{
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case MPU_EXEC | MPU_READ:
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HWREG16(baseAddress + OFS_MPUSAM) &= ~MPUSEG2WE;
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HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG2XE + MPUSEG2RE;
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break;
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case MPU_READ | MPU_WRITE:
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HWREG16(baseAddress + OFS_MPUSAM) &= ~MPUSEG2XE;
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HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG2RE + MPUSEG2WE;
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break;
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case MPU_READ:
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HWREG16(baseAddress + OFS_MPUSAM) &= ~(MPUSEG2XE + MPUSEG2WE);
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HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG2RE;
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break;
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case MPU_EXEC | MPU_READ | MPU_WRITE:
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HWREG16(baseAddress +
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OFS_MPUSAM) |= (MPUSEG2XE + MPUSEG2WE + MPUSEG2RE);
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break;
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case MPU_NO_READ_WRITE_EXEC:
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HWREG16(baseAddress +
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OFS_MPUSAM) &= ~(MPUSEG2XE + MPUSEG2WE + MPUSEG2RE);
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break;
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default:
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break;
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}
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// Set access rights based on user's selection for segment3
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switch(param->seg3accmask)
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{
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case MPU_EXEC | MPU_READ:
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HWREG16(baseAddress + OFS_MPUSAM) &= ~MPUSEG3WE;
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HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG3XE + MPUSEG3RE;
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break;
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case MPU_READ | MPU_WRITE:
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HWREG16(baseAddress + OFS_MPUSAM) &= ~MPUSEG3XE;
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HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG3RE + MPUSEG3WE;
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break;
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case MPU_READ:
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HWREG16(baseAddress + OFS_MPUSAM) &= ~(MPUSEG3XE + MPUSEG3WE);
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HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEG3RE;
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break;
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case MPU_EXEC | MPU_READ | MPU_WRITE:
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HWREG16(baseAddress +
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OFS_MPUSAM) |= (MPUSEG3XE + MPUSEG3WE + MPUSEG3WE);
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break;
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case MPU_NO_READ_WRITE_EXEC:
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HWREG16(baseAddress +
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OFS_MPUSAM) &= ~(MPUSEG3XE + MPUSEG3WE + MPUSEG3WE);
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break;
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default:
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break;
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}
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//Lock MPU to disable writing to all registers
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HWREG8(baseAddress + OFS_MPUCTL0_H) = 0x00;
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}
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void MPU_initInfoSegment(uint16_t baseAddress,
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uint8_t accmask)
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{
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// Write MPU password to allow MPU register configuration
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HWREG16(baseAddress + OFS_MPUCTL0) = MPUPW | HWREG8(
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baseAddress + OFS_MPUCTL0);
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// Set access rights based on user's selection for segment1
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switch(accmask)
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{
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case MPU_EXEC | MPU_READ:
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HWREG16(baseAddress + OFS_MPUSAM) &= ~MPUSEGIWE;
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HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEGIXE + MPUSEGIRE;
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break;
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case MPU_READ | MPU_WRITE:
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HWREG16(baseAddress + OFS_MPUSAM) &= ~MPUSEGIXE;
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HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEGIRE + MPUSEGIWE;
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break;
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case MPU_READ:
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HWREG16(baseAddress + OFS_MPUSAM) &= ~(MPUSEGIXE + MPUSEGIWE);
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HWREG16(baseAddress + OFS_MPUSAM) |= MPUSEGIRE;
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break;
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case MPU_EXEC | MPU_READ | MPU_WRITE:
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HWREG16(baseAddress +
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OFS_MPUSAM) |= (MPUSEGIXE + MPUSEGIWE + MPUSEGIRE);
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break;
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case MPU_NO_READ_WRITE_EXEC:
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HWREG16(baseAddress +
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OFS_MPUSAM) &= ~(MPUSEGIXE + MPUSEGIWE + MPUSEGIRE);
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break;
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default:
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break;
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}
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//Lock MPU to disable writing to all registers
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HWREG8(baseAddress + OFS_MPUCTL0_H) = 0x00;
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}
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void MPU_enableNMIevent(uint16_t baseAddress)
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{
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HWREG16(baseAddress + OFS_MPUCTL0) = MPUPW | MPUSEGIE |
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HWREG8(baseAddress + OFS_MPUCTL0);
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//Lock MPU to disable writing to all registers
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HWREG8(baseAddress + OFS_MPUCTL0_H) = 0x00;
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}
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void MPU_start(uint16_t baseAddress)
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{
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HWREG16(baseAddress + OFS_MPUCTL0) = MPUPW | MPUENA | HWREG8(
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baseAddress + OFS_MPUCTL0);
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//Lock MPU to disable writing to all registers
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HWREG8(baseAddress + OFS_MPUCTL0_H) = 0x00;
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}
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void MPU_enablePUCOnViolation(uint16_t baseAddress,
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uint16_t segment)
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{
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HWREG16(baseAddress + OFS_MPUCTL0) = MPUPW | HWREG8(
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baseAddress + OFS_MPUCTL0);
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HWREG16(baseAddress + OFS_MPUSAM) |= segment;
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//Lock MPU to disable writing to all registers
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HWREG8(baseAddress + OFS_MPUCTL0_H) = 0x00;
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}
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void MPU_disablePUCOnViolation(uint16_t baseAddress,
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uint16_t segment)
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{
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HWREG16(baseAddress + OFS_MPUCTL0) = MPUPW | HWREG8(
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baseAddress + OFS_MPUCTL0);
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HWREG16(baseAddress + OFS_MPUSAM) &= ~segment;
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//Lock MPU to disable writing to all registers
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HWREG8(baseAddress + OFS_MPUCTL0_H) = 0x00;
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}
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uint16_t MPU_getInterruptStatus(uint16_t baseAddress,
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uint16_t memAccFlag)
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{
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return (HWREG16(baseAddress + OFS_MPUCTL1) & memAccFlag);
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}
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uint16_t MPU_clearInterrupt(uint16_t baseAddress,
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uint16_t memAccFlag)
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{
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HWREG16(baseAddress + OFS_MPUCTL0) = MPUPW | HWREG8(
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baseAddress + OFS_MPUCTL0);
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HWREG16(baseAddress + OFS_MPUCTL1) &= ~memAccFlag;
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//Lock MPU to disable writing to all registers
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HWREG8(baseAddress + OFS_MPUCTL0_H) = 0x00;
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return (HWREG16(baseAddress + OFS_MPUCTL1) & memAccFlag);
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}
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uint16_t MPU_clearAllInterrupts(uint16_t baseAddress)
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{
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HWREG16(baseAddress + OFS_MPUCTL0) = MPUPW | HWREG8(
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baseAddress + OFS_MPUCTL0);
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HWREG16(baseAddress +
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OFS_MPUCTL1) &= ~(MPUSEG1IFG + MPUSEG2IFG + MPUSEG3IFG);
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||
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//Lock MPU to disable writing to all registers
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HWREG8(baseAddress + OFS_MPUCTL0_H) = 0x00;
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||
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|
||
|
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return (HWREG16(baseAddress +
|
||
|
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OFS_MPUCTL1) & (MPUSEG1IFG + MPUSEG2IFG + MPUSEG3IFG));
|
||
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}
|
||
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|
|
||
|
|
void MPU_lockMPU(uint16_t baseAddress)
|
||
|
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{
|
||
|
|
HWREG16(baseAddress + OFS_MPUCTL0) = MPUPW | MPULOCK |
|
||
|
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HWREG8(baseAddress + OFS_MPUCTL0);
|
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|
|
|
||
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|
//Lock MPU to disable writing to all registers
|
||
|
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HWREG8(baseAddress + OFS_MPUCTL0_H) = 0x00;
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||
|
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}
|
||
|
|
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#endif
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//*****************************************************************************
|
||
|
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//
|
||
|
|
//! Close the doxygen group for mpu_api
|
||
|
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//! @}
|
||
|
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//
|
||
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//*****************************************************************************
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