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611 lines
11 KiB
C
611 lines
11 KiB
C
19 years ago
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/******************** (C) COPYRIGHT 2003 STMicroelectronics ********************
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* File Name : 71x_map.h
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* Author : MCD Application Team
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* Date First Issued : 05/16/2003
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* Description : Peripherals memory mapping and registers structures
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********************************************************************************
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* History:
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* 30/11/2004 : V2.0
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* 14/07/2004 : V1.3
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* 01/01/2004 : V1.2
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*******************************************************************************
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THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
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CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
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OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
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OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
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CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*******************************************************************************/
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#ifndef __71x_map_H
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#define __71x_map_H
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#ifndef EXT
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#define EXT extern
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#endif
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#include "71x_conf.h"
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#include "71x_type.h"
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/* IP registers structures */
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typedef volatile struct
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{
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vu16 DATA0;
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vu16 EMPTY1[3];
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vu16 DATA1;
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vu16 EMPTY2[3];
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vu16 DATA2;
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vu16 EMPTY3[3];
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vu16 DATA3;
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vu16 EMPTY4[3];
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vu16 CSR;
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vu16 EMPTY5[7];
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vu16 CPR;
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} ADC12_TypeDef;
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typedef volatile struct
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{
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vu32 CKDIS;
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vu32 SWRES;
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} APB_TypeDef;
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typedef volatile struct
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{
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vu16 RXR;
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vu16 EMPTY1;
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vu16 TXR;
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vu16 EMPTY2;
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vu16 CSR1;
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vu16 EMPTY3;
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vu16 CSR2;
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vu16 EMPTY4;
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vu16 CLK;
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} BSPI_TypeDef;
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typedef volatile struct
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{
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vu16 CRR;
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vu16 EMPTY1;
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vu16 CMR;
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vu16 EMPTY2;
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vu16 M1R;
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vu16 EMPTY3;
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vu16 M2R;
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vu16 EMPTY4;
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vu16 A1R;
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vu16 EMPTY5;
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vu16 A2R;
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vu16 EMPTY6;
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vu16 MCR;
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vu16 EMPTY7;
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vu16 DA1R;
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vu16 EMPTY8;
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vu16 DA2R;
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vu16 EMPTY9;
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vu16 DB1R;
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vu16 EMPTY10;
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vu16 DB2R;
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vu16 EMPTY11[27];
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} CAN_MsgObj_TypeDef;
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typedef volatile struct
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{
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vu16 CR;
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vu16 EMPTY1;
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vu16 SR;
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vu16 EMPTY2;
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vu16 ERR;
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vu16 EMPTY3;
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vu16 BTR;
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vu16 EMPTY4;
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vu16 IDR;
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vu16 EMPTY5;
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vu16 TESTR;
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vu16 EMPTY6;
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vu16 BRPR;
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vu16 EMPTY7[3];
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CAN_MsgObj_TypeDef sMsgObj[2];
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vu16 EMPTY8[16];
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vu16 TR1R;
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vu16 EMPTY9;
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vu16 TR2R;
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vu16 EMPTY10[13];
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vu16 ND1R;
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vu16 EMPTY11;
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vu16 ND2R;
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vu16 EMPTY12[13];
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vu16 IP1R;
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vu16 EMPTY13;
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vu16 IP2R;
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vu16 EMPTY14[13];
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vu16 MV1R;
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vu16 EMPTY15;
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vu16 MV2R;
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vu16 EMPTY16;
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} CAN_TypeDef;
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typedef volatile struct
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{
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vu32 ICR;
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vu32 CICR;
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vu32 CIPR;
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vu32 EMPTY1[3];
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vu32 IVR;
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vu32 FIR;
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vu32 IER;
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vu32 EMPTY2[7];
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vu32 IPR;
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vu32 EMPTY3[7];
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vu32 SIR[32];
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} EIC_TypeDef;
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typedef volatile struct
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{
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vu16 BCON0;
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vu16 EMPTY1;
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vu16 BCON1;
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vu16 EMPTY2;
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vu16 BCON2;
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vu16 EMPTY3;
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vu16 BCON3;
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vu16 EMPTY4;
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} EMI_TypeDef;
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typedef volatile struct
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{
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vu32 CR0;
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vu32 CR1;
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vu32 DR0;
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vu32 DR1;
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vu32 AR;
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vu32 ER;
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} FLASHR_TypeDef;
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typedef volatile struct
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{
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vu32 NVWPAR;
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vu32 EMPTY;
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vu32 NVAPR0;
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vu32 NVAPR1;
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} FLASHPR_TypeDef;
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typedef volatile struct
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{
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vu16 PC0;
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vu16 EMPTY1;
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vu16 PC1;
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vu16 EMPTY2;
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vu16 PC2;
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vu16 EMPTY3;
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vu16 PD;
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vu16 EMPTY4;
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} GPIO_TypeDef;
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typedef volatile struct
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{
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vu8 CR;
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vu8 EMPTY1[3];
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vu8 SR1;
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vu8 EMPTY2[3];
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vu8 SR2;
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vu8 EMPTY3[3];
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vu8 CCR;
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vu8 EMPTY4[3];
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vu8 OAR1;
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vu8 EMPTY5[3];
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vu8 OAR2;
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vu8 EMPTY6[3];
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vu8 DR;
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vu8 EMPTY7[3];
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vu8 ECCR;
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} I2C_TypeDef;
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typedef volatile struct
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{
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vu32 CCR;
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vu32 EMPTY1;
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vu32 CFR;
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vu32 EMPTY2[3];
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vu32 PLL1CR;
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vu32 PER;
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vu32 SMR;
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} RCCU_TypeDef;
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typedef volatile struct
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{
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vu16 MDIVR;
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vu16 EMPTY1;
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vu16 PDIVR;
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vu16 EMPTY2;
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vu16 RSTR;
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vu16 EMPTY3;
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vu16 PLL2CR;
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vu16 EMPTY4;
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vu16 BOOTCR;
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vu16 EMPTY5;
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vu16 PWRCR;
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} PCU_TypeDef;
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typedef volatile struct
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{
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vu16 CRH;
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vu16 EMPTY1;
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vu16 CRL;
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vu16 EMPTY2;
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vu16 PRLH;
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vu16 EMPTY3;
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vu16 PRLL;
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vu16 EMPTY4;
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vu16 DIVH;
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vu16 EMPTY5;
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vu16 DIVL;
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vu16 EMPTY6;
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vu16 CNTH;
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vu16 EMPTY7;
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vu16 CNTL;
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vu16 EMPTY8;
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vu16 ALRH;
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vu16 EMPTY9;
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vu16 ALRL;
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} RTC_TypeDef;
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typedef volatile struct
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{
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vu16 ICAR;
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vu16 EMPTY1;
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vu16 ICBR;
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vu16 EMPTY2;
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vu16 OCAR;
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vu16 EMPTY3;
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vu16 OCBR;
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vu16 EMPTY4;
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vu16 CNTR;
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vu16 EMPTY5;
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vu16 CR1;
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vu16 EMPTY6;
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vu16 CR2;
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vu16 EMPTY7;
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vu16 SR;
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} TIM_TypeDef;
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typedef volatile struct
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{
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vu16 BR;
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vu16 EMPTY1;
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vu16 TxBUFR;
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vu16 EMPTY2;
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vu16 RxBUFR;
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vu16 EMPTY3;
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vu16 CR;
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vu16 EMPTY4;
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vu16 IER;
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vu16 EMPTY5;
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vu16 SR;
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vu16 EMPTY6;
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vu16 GTR;
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vu16 EMPTY7;
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vu16 TOR;
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vu16 EMPTY8;
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vu16 TxRSTR;
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vu16 EMPTY9;
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vu16 RxRSTR;
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} UART_TypeDef;
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typedef volatile struct
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{
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vu32 EP0R;
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vu32 EP1R;
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vu32 EP2R;
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vu32 EP3R;
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vu32 EP4R;
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vu32 EP5R;
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vu32 EP6R;
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vu32 EP7R;
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vu32 EP8R;
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vu32 EP9R;
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vu32 EP10R;
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vu32 EP11R;
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vu32 EP12R;
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vu32 EP13R;
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vu32 EP14R;
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vu32 EP15R;
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vu32 CNTR;
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vu32 ISTR;
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vu32 FNR;
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vu32 DADDR;
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vu32 BTABLE;
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} USB_TypeDef;
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typedef volatile struct
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{
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vu16 CR;
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vu16 EMPTY1;
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vu16 PR;
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vu16 EMPTY2;
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vu16 VR;
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vu16 EMPTY3;
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vu16 CNT;
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vu16 EMPTY4;
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vu16 SR;
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vu16 EMPTY5;
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vu16 MR;
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vu16 EMPTY6;
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vu16 KR;
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} WDG_TypeDef;
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typedef volatile struct
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{
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vu8 SR;
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vu8 EMPTY1[7];
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vu8 CTRL;
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vu8 EMPTY2[3];
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vu8 MRH;
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vu8 EMPTY3[3];
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vu8 MRL;
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vu8 EMPTY4[3];
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vu8 TRH;
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vu8 EMPTY5[3];
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vu8 TRL;
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vu8 EMPTY6[3];
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vu8 PRH;
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vu8 EMPTY7[3];
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vu8 PRL;
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} XTI_TypeDef;
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/* IRQ vectors */
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typedef volatile struct
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{
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vu32 T0TIMI_IRQHandler;
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vu32 FLASH_IRQHandler;
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vu32 RCCU_IRQHandler;
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vu32 RTC_IRQHandler;
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vu32 WDG_IRQHandler;
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vu32 XTI_IRQHandler;
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vu32 USBHP_IRQHandler;
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vu32 I2C0ITERR_IRQHandler;
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vu32 I2C1ITERR_IRQHandler;
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vu32 UART0_IRQHandler;
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vu32 UART1_IRQHandler;
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vu32 UART2_IRQHandler;
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vu32 UART3_IRQHandler;
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vu32 BSPI0_IRQHandler;
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vu32 BSPI1_IRQHandler;
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vu32 I2C0_IRQHandler;
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vu32 I2C1_IRQHandler;
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vu32 CAN_IRQHandler;
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vu32 ADC12_IRQHandler;
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vu32 T1TIMI_IRQHandler;
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vu32 T2TIMI_IRQHandler;
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vu32 T3TIMI_IRQHandler;
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vu32 EMPTY1[3];
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vu32 HDLC_IRQHandler;
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vu32 USBLP_IRQHandler;
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vu32 EMPTY2[2];
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vu32 T0TOI_IRQHandler;
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vu32 T0OC1_IRQHandler;
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vu32 T0OC2_IRQHandler;
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} IRQVectors_TypeDef;
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/*===================================================================*/
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||
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/* Memory mapping */
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||
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#define RAM_BASE 0x20000000
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#define FLASHR_BASE 0x40100000
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#define FLASHPR_BASE 0x4010DFB0
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#define EXTMEM_BASE 0x60000000
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#define RCCU_BASE 0xA0000000
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#define PCU_BASE 0xA0000040
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#define APB1_BASE 0xC0000000
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#define APB2_BASE 0xE0000000
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#define EIC_BASE 0xFFFFF800
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#define I2C0_BASE (APB1_BASE + 0x1000)
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||
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#define I2C1_BASE (APB1_BASE + 0x2000)
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||
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#define UART0_BASE (APB1_BASE + 0x4000)
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||
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#define UART1_BASE (APB1_BASE + 0x5000)
|
||
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|
#define UART2_BASE (APB1_BASE + 0x6000)
|
||
|
|
#define UART3_BASE (APB1_BASE + 0x7000)
|
||
|
|
#define CAN_BASE (APB1_BASE + 0x9000)
|
||
|
|
#define BSPI0_BASE (APB1_BASE + 0xA000)
|
||
|
|
#define BSPI1_BASE (APB1_BASE + 0xB000)
|
||
|
|
#define USB_BASE (APB1_BASE + 0x8800)
|
||
|
|
|
||
|
|
#define XTI_BASE (APB2_BASE + 0x101C)
|
||
|
|
#define GPIO0_BASE (APB2_BASE + 0x3000)
|
||
|
|
#define GPIO1_BASE (APB2_BASE + 0x4000)
|
||
|
|
#define GPIO2_BASE (APB2_BASE + 0x5000)
|
||
|
|
#define ADC12_BASE (APB2_BASE + 0x7000)
|
||
|
|
#define TIM0_BASE (APB2_BASE + 0x9000)
|
||
|
|
#define TIM1_BASE (APB2_BASE + 0xA000)
|
||
|
|
#define TIM2_BASE (APB2_BASE + 0xB000)
|
||
|
|
#define TIM3_BASE (APB2_BASE + 0xC000)
|
||
|
|
#define RTC_BASE (APB2_BASE + 0xD000)
|
||
|
|
#define WDG_BASE (APB2_BASE + 0xE000)
|
||
|
|
|
||
|
|
#define EMI_BASE (EXTMEM_BASE + 0x0C000000)
|
||
|
|
|
||
|
|
/*===================================================================*/
|
||
|
|
|
||
|
|
/* IP data access */
|
||
|
|
|
||
|
|
#ifndef DEBUG
|
||
|
|
#define ADC12 ((ADC12_TypeDef *)ADC12_BASE)
|
||
|
|
|
||
|
|
#define APB1 ((APB_TypeDef *)APB1_BASE)
|
||
|
|
#define APB2 ((APB_TypeDef *)APB2_BASE+0x10)
|
||
|
|
|
||
|
|
#define BSPI0 ((BSPI_TypeDef *)BSPI0_BASE)
|
||
|
|
#define BSPI1 ((BSPI_TypeDef *)BSPI1_BASE)
|
||
|
|
|
||
|
|
#define CAN ((CAN_TypeDef *)CAN_BASE)
|
||
|
|
|
||
|
|
#define EIC ((EIC_TypeDef *)EIC_BASE)
|
||
|
|
|
||
|
|
#define EMI ((EMI_TypeDef *)EMI_BASE)
|
||
|
|
|
||
|
|
#define FLASHR ((FLASHR_TypeDef *)FLASHR_BASE)
|
||
|
|
#define FLASHPR ((FLASHPR_TypeDef *)FLASHPR_BASE)
|
||
|
|
|
||
|
|
#define GPIO0 ((GPIO_TypeDef *)GPIO0_BASE)
|
||
|
|
#define GPIO1 ((GPIO_TypeDef *)GPIO1_BASE)
|
||
|
|
#define GPIO2 ((GPIO_TypeDef *)GPIO2_BASE)
|
||
|
|
|
||
|
|
#define I2C0 ((I2C_TypeDef *)I2C0_BASE)
|
||
|
|
#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
|
||
|
|
|
||
|
|
#define PCU ((PCU_TypeDef *)PCU_BASE)
|
||
|
|
|
||
|
|
#define RCCU ((RCCU_TypeDef *)RCCU_BASE)
|
||
|
|
|
||
|
|
#define RTC ((RTC_TypeDef *)RTC_BASE)
|
||
|
|
|
||
|
|
#define TIM0 ((TIM_TypeDef *)TIM0_BASE)
|
||
|
|
#define TIM1 ((TIM_TypeDef *)TIM1_BASE)
|
||
|
|
#define TIM2 ((TIM_TypeDef *)TIM2_BASE)
|
||
|
|
#define TIM3 ((TIM_TypeDef *)TIM3_BASE)
|
||
|
|
|
||
|
|
#define UART0 ((UART_TypeDef *)UART0_BASE)
|
||
|
|
#define UART1 ((UART_TypeDef *)UART1_BASE)
|
||
|
|
#define UART2 ((UART_TypeDef *)UART2_BASE)
|
||
|
|
#define UART3 ((UART_TypeDef *)UART3_BASE)
|
||
|
|
|
||
|
|
#define USB ((USB_TypeDef *)USB_BASE)
|
||
|
|
|
||
|
|
#define WDG ((WDG_TypeDef *)WDG_BASE)
|
||
|
|
|
||
|
|
#define XTI ((XTI_TypeDef *)XTI_BASE)
|
||
|
|
|
||
|
|
#define IRQVectors ((IRQVectors_TypeDef *)&T0TIMI_Addr)
|
||
|
|
|
||
|
|
#else /* DEBUG */
|
||
|
|
|
||
|
|
#ifdef _ADC12
|
||
|
|
EXT ADC12_TypeDef *ADC12;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef _APB
|
||
|
|
#ifdef _APB1
|
||
|
|
EXT APB_TypeDef *APB1;
|
||
|
|
#endif
|
||
|
|
#ifdef _APB2
|
||
|
|
EXT APB_TypeDef *APB2;
|
||
|
|
#endif
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef _BSPI
|
||
|
|
#ifdef _BSPI0
|
||
|
|
EXT BSPI_TypeDef *BSPI0;
|
||
|
|
#endif
|
||
|
|
#ifdef _BSPI1
|
||
|
|
EXT BSPI_TypeDef *BSPI1;
|
||
|
|
#endif
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef _CAN
|
||
|
|
EXT CAN_TypeDef *CAN;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef _EIC
|
||
|
|
EXT EIC_TypeDef *EIC;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef _EMI
|
||
|
|
EXT EMI_TypeDef *EMI;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef _FLASH
|
||
|
|
EXT FLASHR_TypeDef *FLASHR;
|
||
|
|
EXT FLASHPR_TypeDef *FLASHPR;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef _GPIO
|
||
|
|
#ifdef _GPIO0
|
||
|
|
EXT GPIO_TypeDef *GPIO0;
|
||
|
|
#endif
|
||
|
|
#ifdef _GPIO1
|
||
|
|
EXT GPIO_TypeDef *GPIO1;
|
||
|
|
#endif
|
||
|
|
#ifdef _GPIO2
|
||
|
|
EXT GPIO_TypeDef *GPIO2;
|
||
|
|
#endif
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef _I2C
|
||
|
|
#ifdef _I2C0
|
||
|
|
EXT I2C_TypeDef *I2C0;
|
||
|
|
#endif
|
||
|
|
#ifdef _I2C1
|
||
|
|
EXT I2C_TypeDef *I2C1;
|
||
|
|
#endif
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef _PCU
|
||
|
|
EXT PCU_TypeDef *PCU;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef _RCCU
|
||
|
|
EXT RCCU_TypeDef *RCCU;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef _RTC
|
||
|
|
EXT RTC_TypeDef *RTC;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef _TIM
|
||
|
|
#ifdef _TIM0
|
||
|
|
EXT TIM_TypeDef *TIM0;
|
||
|
|
#endif
|
||
|
|
#ifdef _TIM1
|
||
|
|
EXT TIM_TypeDef *TIM1;
|
||
|
|
#endif
|
||
|
|
#ifdef _TIM2
|
||
|
|
EXT TIM_TypeDef *TIM2;
|
||
|
|
#endif
|
||
|
|
#ifdef _TIM3
|
||
|
|
EXT TIM_TypeDef *TIM3;
|
||
|
|
#endif
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef _UART
|
||
|
|
#ifdef _UART0
|
||
|
|
EXT UART_TypeDef *UART0;
|
||
|
|
#endif
|
||
|
|
#ifdef _UART1
|
||
|
|
EXT UART_TypeDef *UART1;
|
||
|
|
#endif
|
||
|
|
#ifdef _UART2
|
||
|
|
EXT UART_TypeDef *UART2;
|
||
|
|
#endif
|
||
|
|
#ifdef _UART3
|
||
|
|
EXT UART_TypeDef *UART3;
|
||
|
|
#endif
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef _USB
|
||
|
|
EXT USB_TypeDef *USB;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef _WDG
|
||
|
|
EXT WDG_TypeDef *WDG;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef _XTI
|
||
|
|
EXT XTI_TypeDef *XTI;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef _IRQVectors
|
||
|
|
EXT IRQVectors_TypeDef *IRQVectors;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* DEBUG */
|
||
|
|
|
||
|
|
#endif /* __71x_map_H */
|
||
|
|
|
||
|
|
/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/
|