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486 lines
18 KiB
Plaintext
486 lines
18 KiB
Plaintext
14 years ago
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# ##############################################################################
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# Created by Base System Builder Wizard for Xilinx EDK 13.1 Build EDK_O.40d
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# Sun Aug 28 16:20:06 2011
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# Target Board: xilinx.com sp605 Rev C
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# Family: spartan6
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# Device: xc6slx45t
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# Package: fgg484
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# Speed Grade: -3
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# ##############################################################################
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PARAMETER VERSION = 2.1.0
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PORT RESET = RESET, DIR = I, SIGIS = RST, RST_POLARITY = 1
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PORT CLK_P = CLK, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 200000000
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PORT CLK_N = CLK, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 200000000
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PORT RS232_Uart_1_sout = RS232_Uart_1_sout, DIR = O
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PORT RS232_Uart_1_sin = RS232_Uart_1_sin, DIR = I
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PORT DIP_Switches_4Bits_TRI_I = DIP_Switches_4Bits_TRI_I, DIR = I, VEC = [0:3]
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PORT LEDs_4Bits_TRI_O = LEDs_4Bits_TRI_O, DIR = O, VEC = [0:3]
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PORT Push_Buttons_4Bits_TRI_I = Push_Buttons_4Bits_TRI_I, DIR = I, VEC = [0:3]
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PORT mcbx_dram_clk = mcbx_dram_clk, DIR = O
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PORT mcbx_dram_clk_n = mcbx_dram_clk_n, DIR = O
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PORT mcbx_dram_cke = mcbx_dram_cke, DIR = O
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PORT mcbx_dram_odt = mcbx_dram_odt, DIR = O
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PORT mcbx_dram_ras_n = mcbx_dram_ras_n, DIR = O
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PORT mcbx_dram_cas_n = mcbx_dram_cas_n, DIR = O
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PORT mcbx_dram_we_n = mcbx_dram_we_n, DIR = O
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PORT mcbx_dram_udm = mcbx_dram_udm, DIR = O
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PORT mcbx_dram_ldm = mcbx_dram_ldm, DIR = O
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PORT mcbx_dram_ba = mcbx_dram_ba, DIR = O, VEC = [2:0]
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PORT mcbx_dram_addr = mcbx_dram_addr, DIR = O, VEC = [12:0]
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PORT mcbx_dram_ddr3_rst = mcbx_dram_ddr3_rst, DIR = O
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PORT mcbx_dram_dq = mcbx_dram_dq, DIR = IO, VEC = [15:0]
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PORT mcbx_dram_dqs = mcbx_dram_dqs, DIR = IO
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PORT mcbx_dram_dqs_n = mcbx_dram_dqs_n, DIR = IO
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PORT mcbx_dram_udqs = mcbx_dram_udqs, DIR = IO
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PORT mcbx_dram_udqs_n = mcbx_dram_udqs_n, DIR = IO
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PORT rzq = rzq, DIR = IO
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PORT zio = zio, DIR = IO
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PORT ETHERNET_MDIO = ETHERNET_MDIO, DIR = IO
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PORT ETHERNET_MDC = ETHERNET_MDC, DIR = O
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PORT ETHERNET_TX_ER = ETHERNET_TX_ER, DIR = O
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PORT ETHERNET_TXD = ETHERNET_TXD, DIR = O, VEC = [7:0]
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PORT ETHERNET_TX_EN = ETHERNET_TX_EN, DIR = O
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PORT ETHERNET_MII_TX_CLK = ETHERNET_MII_TX_CLK, DIR = I
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PORT ETHERNET_TX_CLK = ETHERNET_TX_CLK, DIR = O
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PORT ETHERNET_RXD = ETHERNET_RXD, DIR = I, VEC = [7:0]
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PORT ETHERNET_RX_ER = ETHERNET_RX_ER, DIR = I
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PORT ETHERNET_RX_CLK = ETHERNET_RX_CLK, DIR = I
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PORT ETHERNET_RX_DV = ETHERNET_RX_DV, DIR = I
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PORT ETHERNET_PHY_RST_N = ETHERNET_PHY_RST_N, DIR = O
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BEGIN axi_interconnect
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PARAMETER INSTANCE = axi4_0
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PARAMETER HW_VER = 1.02.a
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PORT interconnect_aclk = clk_100_0000MHzPLL0
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PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
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END
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BEGIN axi_interconnect
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PARAMETER INSTANCE = axi4lite_0
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PARAMETER HW_VER = 1.02.a
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PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
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PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
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PORT INTERCONNECT_ACLK = clk_50_0000MHzPLL0
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END
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BEGIN microblaze
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PARAMETER INSTANCE = microblaze_0
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PARAMETER HW_VER = 8.10.a
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PARAMETER C_INTERCONNECT = 2
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PARAMETER C_USE_BARREL = 1
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PARAMETER C_USE_FPU = 0
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PARAMETER C_DEBUG_ENABLED = 1
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PARAMETER C_ICACHE_BASEADDR = 0xc0000000
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PARAMETER C_ICACHE_HIGHADDR = 0xc7ffffff
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PARAMETER C_USE_ICACHE = 1
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PARAMETER C_ICACHE_ALWAYS_USED = 1
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PARAMETER C_DCACHE_BASEADDR = 0xc0000000
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PARAMETER C_DCACHE_HIGHADDR = 0xc7ffffff
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PARAMETER C_USE_DCACHE = 1
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PARAMETER C_DCACHE_ALWAYS_USED = 1
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PARAMETER C_INTERCONNECT_M_AXI_DC_AW_REGISTER = 1
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PARAMETER C_INTERCONNECT_M_AXI_DC_W_REGISTER = 1
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PARAMETER C_INTERCONNECT_M_AXI_DP_AW_REGISTER = 1
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PARAMETER C_INTERCONNECT_M_AXI_DP_AR_REGISTER = 1
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PARAMETER C_INTERCONNECT_M_AXI_DP_W_REGISTER = 1
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PARAMETER C_INTERCONNECT_M_AXI_DP_R_REGISTER = 1
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PARAMETER C_INTERCONNECT_M_AXI_DP_B_REGISTER = 1
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PARAMETER C_INTERCONNECT_M_AXI_DC_AR_REGISTER = 1
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PARAMETER C_INTERCONNECT_M_AXI_DC_R_REGISTER = 1
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PARAMETER C_INTERCONNECT_M_AXI_DC_B_REGISTER = 1
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PARAMETER C_INTERCONNECT_M_AXI_IC_AW_REGISTER = 1
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PARAMETER C_INTERCONNECT_M_AXI_IC_AR_REGISTER = 1
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PARAMETER C_INTERCONNECT_M_AXI_IC_W_REGISTER = 1
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PARAMETER C_INTERCONNECT_M_AXI_IC_R_REGISTER = 1
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PARAMETER C_INTERCONNECT_M_AXI_IC_B_REGISTER = 1
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BUS_INTERFACE ILMB = microblaze_0_ilmb
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BUS_INTERFACE DLMB = microblaze_0_dlmb
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BUS_INTERFACE M_AXI_DP = axi4lite_0
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BUS_INTERFACE M_AXI_DC = axi4_0
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BUS_INTERFACE M_AXI_IC = axi4_0
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BUS_INTERFACE DEBUG = microblaze_0_debug
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PORT MB_RESET = proc_sys_reset_0_MB_Reset
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PORT CLK = clk_100_0000MHzPLL0
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PORT INTERRUPT = microblaze_0_interrupt
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END
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BEGIN lmb_v10
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PARAMETER INSTANCE = microblaze_0_ilmb
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PARAMETER HW_VER = 2.00.a
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PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
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PORT LMB_CLK = clk_100_0000MHzPLL0
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END
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BEGIN lmb_v10
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PARAMETER INSTANCE = microblaze_0_dlmb
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PARAMETER HW_VER = 2.00.a
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PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
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PORT LMB_CLK = clk_100_0000MHzPLL0
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END
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BEGIN lmb_bram_if_cntlr
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PARAMETER INSTANCE = microblaze_0_i_bram_ctrl
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PARAMETER HW_VER = 3.00.a
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PARAMETER C_BASEADDR = 0x00000000
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PARAMETER C_HIGHADDR = 0x00001fff
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BUS_INTERFACE SLMB = microblaze_0_ilmb
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BUS_INTERFACE BRAM_PORT = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
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END
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BEGIN lmb_bram_if_cntlr
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PARAMETER INSTANCE = microblaze_0_d_bram_ctrl
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PARAMETER HW_VER = 3.00.a
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PARAMETER C_BASEADDR = 0x00000000
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PARAMETER C_HIGHADDR = 0x00001fff
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BUS_INTERFACE SLMB = microblaze_0_dlmb
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BUS_INTERFACE BRAM_PORT = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
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END
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BEGIN bram_block
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PARAMETER INSTANCE = microblaze_0_bram_block
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PARAMETER HW_VER = 1.00.a
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BUS_INTERFACE PORTA = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
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BUS_INTERFACE PORTB = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
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END
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BEGIN proc_sys_reset
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PARAMETER INSTANCE = proc_sys_reset_0
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PARAMETER HW_VER = 3.00.a
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PARAMETER C_EXT_RESET_HIGH = 1
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PORT Ext_Reset_In = RESET
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PORT MB_Reset = proc_sys_reset_0_MB_Reset
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PORT Slowest_sync_clk = clk_50_0000MHzPLL0
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PORT Interconnect_aresetn = proc_sys_reset_0_Interconnect_aresetn
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PORT Dcm_locked = proc_sys_reset_0_Dcm_locked
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PORT MB_Debug_Sys_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst
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PORT BUS_STRUCT_RESET = proc_sys_reset_0_BUS_STRUCT_RESET
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END
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BEGIN clock_generator
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PARAMETER INSTANCE = clock_generator_0
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PARAMETER HW_VER = 4.01.a
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PARAMETER C_CLKIN_FREQ = 200000000
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PARAMETER C_CLKOUT0_FREQ = 600000000
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PARAMETER C_CLKOUT0_GROUP = PLL0
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PARAMETER C_CLKOUT0_BUF = FALSE
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PARAMETER C_CLKOUT1_FREQ = 600000000
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PARAMETER C_CLKOUT1_PHASE = 180
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PARAMETER C_CLKOUT1_GROUP = PLL0
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PARAMETER C_CLKOUT1_BUF = FALSE
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PARAMETER C_CLKOUT2_FREQ = 100000000
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PARAMETER C_CLKOUT2_GROUP = PLL0
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PARAMETER C_CLKOUT3_FREQ = 125000000
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PARAMETER C_CLKOUT3_GROUP = NONE
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PARAMETER C_CLKOUT4_FREQ = 200000000
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PARAMETER C_CLKOUT4_GROUP = PLL0
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PARAMETER C_CLKOUT5_FREQ = 50000000
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PARAMETER C_CLKOUT5_GROUP = PLL0
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PORT RST = RESET
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PORT CLKIN = CLK
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PORT CLKOUT2 = clk_100_0000MHzPLL0
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PORT CLKOUT5 = clk_50_0000MHzPLL0
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PORT CLKOUT3 = clk_125_0000MHz
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PORT CLKOUT4 = clk_200_0000MHzPLL0
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PORT CLKOUT0 = clk_600_0000MHzPLL0_nobuf
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PORT CLKOUT1 = clk_600_0000MHz180PLL0_nobuf
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PORT LOCKED = proc_sys_reset_0_Dcm_locked
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END
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BEGIN mdm
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PARAMETER INSTANCE = debug_module
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PARAMETER HW_VER = 2.00.b
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PARAMETER C_INTERCONNECT = 2
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PARAMETER C_USE_UART = 1
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PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
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PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
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PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
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PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
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PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
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PARAMETER C_BASEADDR = 0x74800000
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PARAMETER C_HIGHADDR = 0x7480ffff
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BUS_INTERFACE S_AXI = axi4lite_0
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BUS_INTERFACE MBDEBUG_0 = microblaze_0_debug
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PORT S_AXI_ACLK = clk_50_0000MHzPLL0
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PORT Debug_SYS_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst
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END
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BEGIN axi_uartlite
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PARAMETER INSTANCE = RS232_Uart_1
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PARAMETER HW_VER = 1.01.a
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PARAMETER C_BAUDRATE = 115200
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PARAMETER C_DATA_BITS = 8
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PARAMETER C_USE_PARITY = 0
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PARAMETER C_ODD_PARITY = 1
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PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
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PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
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PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
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PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
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PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
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PARAMETER C_BASEADDR = 0x40600000
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PARAMETER C_HIGHADDR = 0x4060ffff
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BUS_INTERFACE S_AXI = axi4lite_0
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PORT TX = RS232_Uart_1_sout
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PORT RX = RS232_Uart_1_sin
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PORT S_AXI_ACLK = clk_50_0000MHzPLL0
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PORT Interrupt = RS232_Uart_1_Interrupt
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END
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BEGIN axi_gpio
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PARAMETER INSTANCE = DIP_Switches_4Bits
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PARAMETER HW_VER = 1.01.a
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PARAMETER C_GPIO_WIDTH = 4
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PARAMETER C_ALL_INPUTS = 1
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PARAMETER C_INTERRUPT_PRESENT = 1
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PARAMETER C_IS_DUAL = 0
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PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
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PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
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PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
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PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
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PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
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PARAMETER C_BASEADDR = 0x40040000
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PARAMETER C_HIGHADDR = 0x4004ffff
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BUS_INTERFACE S_AXI = axi4lite_0
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PORT GPIO_IO_I = DIP_Switches_4Bits_TRI_I
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PORT S_AXI_ACLK = clk_50_0000MHzPLL0
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PORT IP2INTC_Irpt = DIP_Switches_4Bits_IP2INTC_Irpt
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END
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BEGIN axi_gpio
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PARAMETER INSTANCE = LEDs_4Bits
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PARAMETER HW_VER = 1.01.a
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PARAMETER C_GPIO_WIDTH = 4
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PARAMETER C_ALL_INPUTS = 0
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PARAMETER C_INTERRUPT_PRESENT = 0
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PARAMETER C_IS_DUAL = 0
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PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
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PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
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PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
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PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
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PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
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PARAMETER C_BASEADDR = 0x40020000
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PARAMETER C_HIGHADDR = 0x4002ffff
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BUS_INTERFACE S_AXI = axi4lite_0
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PORT GPIO_IO_O = LEDs_4Bits_TRI_O
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PORT S_AXI_ACLK = clk_50_0000MHzPLL0
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END
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BEGIN axi_gpio
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PARAMETER INSTANCE = Push_Buttons_4Bits
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PARAMETER HW_VER = 1.01.a
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PARAMETER C_GPIO_WIDTH = 4
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PARAMETER C_ALL_INPUTS = 1
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PARAMETER C_INTERRUPT_PRESENT = 1
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PARAMETER C_IS_DUAL = 0
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PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
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PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
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PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
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PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
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PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
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PARAMETER C_BASEADDR = 0x40000000
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PARAMETER C_HIGHADDR = 0x4000ffff
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BUS_INTERFACE S_AXI = axi4lite_0
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PORT GPIO_IO_I = Push_Buttons_4Bits_TRI_I
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PORT S_AXI_ACLK = clk_50_0000MHzPLL0
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PORT IP2INTC_Irpt = Push_Buttons_4Bits_IP2INTC_Irpt
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END
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BEGIN axi_s6_ddrx
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PARAMETER INSTANCE = MCB_DDR3
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PARAMETER HW_VER = 1.02.a
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PARAMETER C_MCB_RZQ_LOC = K7
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PARAMETER C_MCB_ZIO_LOC = R7
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PARAMETER C_MEM_TYPE = DDR3
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PARAMETER C_MEM_PARTNO = MT41J64M16XX-187E
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PARAMETER C_MEM_BANKADDR_WIDTH = 3
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PARAMETER C_MEM_NUM_COL_BITS = 10
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PARAMETER C_SKIP_IN_TERM_CAL = 0
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PARAMETER C_S0_AXI_ENABLE = 1
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PARAMETER C_INTERCONNECT_S0_AXI_MASTERS = microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM
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PARAMETER C_INTERCONNECT_S0_AXI_AW_REGISTER = 1
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PARAMETER C_INTERCONNECT_S0_AXI_AR_REGISTER = 1
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PARAMETER C_INTERCONNECT_S0_AXI_W_REGISTER = 1
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PARAMETER C_INTERCONNECT_S0_AXI_R_REGISTER = 1
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PARAMETER C_INTERCONNECT_S0_AXI_B_REGISTER = 1
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PARAMETER C_S0_AXI_BASEADDR = 0xc0000000
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PARAMETER C_S0_AXI_HIGHADDR = 0xc7ffffff
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BUS_INTERFACE S0_AXI = axi4_0
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PORT mcbx_dram_clk = mcbx_dram_clk
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PORT mcbx_dram_clk_n = mcbx_dram_clk_n
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PORT mcbx_dram_cke = mcbx_dram_cke
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PORT mcbx_dram_odt = mcbx_dram_odt
|
||
|
PORT mcbx_dram_ras_n = mcbx_dram_ras_n
|
||
|
PORT mcbx_dram_cas_n = mcbx_dram_cas_n
|
||
|
PORT mcbx_dram_we_n = mcbx_dram_we_n
|
||
|
PORT mcbx_dram_udm = mcbx_dram_udm
|
||
|
PORT mcbx_dram_ldm = mcbx_dram_ldm
|
||
|
PORT mcbx_dram_ba = mcbx_dram_ba
|
||
|
PORT mcbx_dram_addr = mcbx_dram_addr
|
||
|
PORT mcbx_dram_ddr3_rst = mcbx_dram_ddr3_rst
|
||
|
PORT mcbx_dram_dq = mcbx_dram_dq
|
||
|
PORT mcbx_dram_dqs = mcbx_dram_dqs
|
||
|
PORT mcbx_dram_dqs_n = mcbx_dram_dqs_n
|
||
|
PORT mcbx_dram_udqs = mcbx_dram_udqs
|
||
|
PORT mcbx_dram_udqs_n = mcbx_dram_udqs_n
|
||
|
PORT rzq = rzq
|
||
|
PORT zio = zio
|
||
|
PORT s0_axi_aclk = clk_100_0000MHzPLL0
|
||
|
PORT ui_clk = clk_100_0000MHzPLL0
|
||
|
PORT sysclk_2x = clk_600_0000MHzPLL0_nobuf
|
||
|
PORT sysclk_2x_180 = clk_600_0000MHz180PLL0_nobuf
|
||
|
PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
|
||
|
PORT PLL_LOCK = proc_sys_reset_0_Dcm_locked
|
||
|
END
|
||
|
|
||
|
BEGIN axi_ethernet
|
||
|
PARAMETER INSTANCE = ETHERNET
|
||
|
PARAMETER HW_VER = 2.01.a
|
||
|
PARAMETER C_PHYADDR = 0B00001
|
||
|
PARAMETER C_INCLUDE_IO = 1
|
||
|
PARAMETER C_TYPE = 1
|
||
|
PARAMETER C_PHY_TYPE = 1
|
||
|
PARAMETER C_HALFDUP = 0
|
||
|
PARAMETER C_TXMEM = 4096
|
||
|
PARAMETER C_RXMEM = 4096
|
||
|
PARAMETER C_TXCSUM = 0
|
||
|
PARAMETER C_RXCSUM = 0
|
||
|
PARAMETER C_TXVLAN_TRAN = 0
|
||
|
PARAMETER C_RXVLAN_TRAN = 0
|
||
|
PARAMETER C_TXVLAN_TAG = 0
|
||
|
PARAMETER C_RXVLAN_TAG = 0
|
||
|
PARAMETER C_TXVLAN_STRP = 0
|
||
|
PARAMETER C_RXVLAN_STRP = 0
|
||
|
PARAMETER C_MCAST_EXTEND = 0
|
||
|
PARAMETER C_STATS = 0
|
||
|
PARAMETER C_AVB = 0
|
||
|
PARAMETER C_INTERCONNECT_S_AXI_IS_ACLK_ASYNC = 0
|
||
|
PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
|
||
|
PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
|
||
|
PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
|
||
|
PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
|
||
|
PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
|
||
|
PARAMETER C_BASEADDR = 0x41240000
|
||
|
PARAMETER C_HIGHADDR = 0x4127ffff
|
||
|
BUS_INTERFACE S_AXI = axi4lite_0
|
||
|
BUS_INTERFACE AXI_STR_TXD = ETHERNET_dma_txd
|
||
|
BUS_INTERFACE AXI_STR_TXC = ETHERNET_dma_txc
|
||
|
BUS_INTERFACE AXI_STR_RXS = ETHERNET_dma_rxs
|
||
|
BUS_INTERFACE AXI_STR_RXD = ETHERNET_dma_rxd
|
||
|
PORT MDIO = ETHERNET_MDIO
|
||
|
PORT MDC = ETHERNET_MDC
|
||
|
PORT GMII_TX_ER = ETHERNET_TX_ER
|
||
|
PORT GMII_TXD = ETHERNET_TXD
|
||
|
PORT GMII_TX_EN = ETHERNET_TX_EN
|
||
|
PORT MII_TX_CLK = ETHERNET_MII_TX_CLK
|
||
|
PORT GMII_TX_CLK = ETHERNET_TX_CLK
|
||
|
PORT GMII_RXD = ETHERNET_RXD
|
||
|
PORT GMII_RX_ER = ETHERNET_RX_ER
|
||
|
PORT GMII_RX_CLK = ETHERNET_RX_CLK
|
||
|
PORT GMII_RX_DV = ETHERNET_RX_DV
|
||
|
PORT PHY_RST_N = ETHERNET_PHY_RST_N
|
||
|
PORT S_AXI_ACLK = clk_50_0000MHzPLL0
|
||
|
PORT GTX_CLK = clk_125_0000MHz
|
||
|
PORT REF_CLK = clk_200_0000MHzPLL0
|
||
|
PORT AXI_STR_TXD_ACLK = clk_100_0000MHzPLL0
|
||
|
PORT AXI_STR_TXC_ACLK = clk_100_0000MHzPLL0
|
||
|
PORT AXI_STR_RXD_ACLK = clk_100_0000MHzPLL0
|
||
|
PORT AXI_STR_RXS_ACLK = clk_100_0000MHzPLL0
|
||
|
PORT AXI_STR_TXD_ARESETN = AXI_STR_TXD_ARESETN
|
||
|
PORT AXI_STR_TXC_ARESETN = AXI_STR_TXC_ARESETN
|
||
|
PORT AXI_STR_RXD_ARESETN = AXI_STR_RXD_ARESETN
|
||
|
PORT AXI_STR_RXS_ARESETN = AXI_STR_RXS_ARESETN
|
||
|
PORT INTERRUPT = ETHERNET_INTERRUPT
|
||
|
END
|
||
|
|
||
|
BEGIN axi_timer
|
||
|
PARAMETER INSTANCE = axi_timer_0
|
||
|
PARAMETER HW_VER = 1.01.a
|
||
|
PARAMETER C_COUNT_WIDTH = 32
|
||
|
PARAMETER C_ONE_TIMER_ONLY = 0
|
||
|
PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
|
||
|
PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
|
||
|
PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
|
||
|
PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
|
||
|
PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
|
||
|
PARAMETER C_BASEADDR = 0x41c00000
|
||
|
PARAMETER C_HIGHADDR = 0x41c0ffff
|
||
|
BUS_INTERFACE S_AXI = axi4lite_0
|
||
|
PORT S_AXI_ACLK = clk_50_0000MHzPLL0
|
||
|
PORT Interrupt = axi_timer_0_Interrupt
|
||
|
END
|
||
|
|
||
|
BEGIN axi_dma
|
||
|
PARAMETER INSTANCE = ETHERNET_dma
|
||
|
PARAMETER HW_VER = 3.00.a
|
||
|
PARAMETER C_SG_INCLUDE_DESC_QUEUE = 1
|
||
|
PARAMETER C_SG_USE_STSAPP_LENGTH = 1
|
||
|
PARAMETER C_INCLUDE_MM2S_DRE = 1
|
||
|
PARAMETER C_INCLUDE_S2MM_DRE = 1
|
||
|
PARAMETER C_DLYTMR_RESOLUTION = 1250
|
||
|
PARAMETER C_PRMRY_IS_ACLK_ASYNC = 0
|
||
|
PARAMETER C_SG_INCLUDE_STSCNTRL_STRM = 1
|
||
|
PARAMETER C_SG_LENGTH_WIDTH = 16
|
||
|
PARAMETER C_INCLUDE_MM2S = 1
|
||
|
PARAMETER C_INCLUDE_S2MM = 1
|
||
|
PARAMETER C_INTERCONNECT_S_AXI_LITE_AW_REGISTER = 1
|
||
|
PARAMETER C_INTERCONNECT_S_AXI_LITE_AR_REGISTER = 1
|
||
|
PARAMETER C_INTERCONNECT_S_AXI_LITE_W_REGISTER = 1
|
||
|
PARAMETER C_INTERCONNECT_S_AXI_LITE_R_REGISTER = 1
|
||
|
PARAMETER C_INTERCONNECT_S_AXI_LITE_B_REGISTER = 1
|
||
|
PARAMETER C_INTERCONNECT_M_AXI_SG_AW_REGISTER = 1
|
||
|
PARAMETER C_INTERCONNECT_M_AXI_SG_AR_REGISTER = 1
|
||
|
PARAMETER C_INTERCONNECT_M_AXI_SG_W_REGISTER = 1
|
||
|
PARAMETER C_INTERCONNECT_M_AXI_SG_R_REGISTER = 1
|
||
|
PARAMETER C_INTERCONNECT_M_AXI_SG_B_REGISTER = 1
|
||
|
PARAMETER C_INTERCONNECT_M_AXI_MM2S_AW_REGISTER = 1
|
||
|
PARAMETER C_INTERCONNECT_M_AXI_MM2S_AR_REGISTER = 1
|
||
|
PARAMETER C_INTERCONNECT_M_AXI_MM2S_W_REGISTER = 1
|
||
|
PARAMETER C_INTERCONNECT_M_AXI_MM2S_R_REGISTER = 1
|
||
|
PARAMETER C_INTERCONNECT_M_AXI_MM2S_B_REGISTER = 1
|
||
|
PARAMETER C_INTERCONNECT_M_AXI_S2MM_AW_REGISTER = 1
|
||
|
PARAMETER C_INTERCONNECT_M_AXI_S2MM_AR_REGISTER = 1
|
||
|
PARAMETER C_INTERCONNECT_M_AXI_S2MM_W_REGISTER = 1
|
||
|
PARAMETER C_INTERCONNECT_M_AXI_S2MM_R_REGISTER = 1
|
||
|
PARAMETER C_INTERCONNECT_M_AXI_S2MM_B_REGISTER = 1
|
||
|
PARAMETER C_BASEADDR = 0x41e00000
|
||
|
PARAMETER C_HIGHADDR = 0x41e0ffff
|
||
|
BUS_INTERFACE S_AXI_LITE = axi4lite_0
|
||
|
BUS_INTERFACE M_AXI_SG = axi4_0
|
||
|
BUS_INTERFACE M_AXI_MM2S = axi4_0
|
||
|
BUS_INTERFACE M_AXI_S2MM = axi4_0
|
||
|
BUS_INTERFACE M_AXIS_MM2S = ETHERNET_dma_txd
|
||
|
BUS_INTERFACE M_AXIS_CNTRL = ETHERNET_dma_txc
|
||
|
BUS_INTERFACE S_AXIS_STS = ETHERNET_dma_rxs
|
||
|
BUS_INTERFACE S_AXIS_S2MM = ETHERNET_dma_rxd
|
||
|
PORT s_axi_lite_aclk = clk_100_0000MHzPLL0
|
||
|
PORT m_axi_sg_aclk = clk_100_0000MHzPLL0
|
||
|
PORT m_axi_mm2s_aclk = clk_100_0000MHzPLL0
|
||
|
PORT m_axi_s2mm_aclk = clk_100_0000MHzPLL0
|
||
|
PORT mm2s_prmry_reset_out_n = AXI_STR_TXD_ARESETN
|
||
|
PORT mm2s_cntrl_reset_out_n = AXI_STR_TXC_ARESETN
|
||
|
PORT s2mm_prmry_reset_out_n = AXI_STR_RXD_ARESETN
|
||
|
PORT s2mm_sts_reset_out_n = AXI_STR_RXS_ARESETN
|
||
|
PORT mm2s_introut = ETHERNET_dma_mm2s_introut
|
||
|
PORT s2mm_introut = ETHERNET_dma_s2mm_introut
|
||
|
END
|
||
|
|
||
|
BEGIN axi_intc
|
||
|
PARAMETER INSTANCE = microblaze_0_intc
|
||
|
PARAMETER HW_VER = 1.01.a
|
||
|
PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
|
||
|
PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
|
||
|
PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
|
||
|
PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
|
||
|
PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
|
||
|
PARAMETER C_BASEADDR = 0x41200000
|
||
|
PARAMETER C_HIGHADDR = 0x4120ffff
|
||
|
BUS_INTERFACE S_AXI = axi4lite_0
|
||
|
PORT IRQ = microblaze_0_interrupt
|
||
|
PORT S_AXI_ACLK = clk_50_0000MHzPLL0
|
||
|
PORT INTR = RS232_Uart_1_Interrupt & DIP_Switches_4Bits_IP2INTC_Irpt & Push_Buttons_4Bits_IP2INTC_Irpt & ETHERNET_INTERRUPT & axi_timer_0_Interrupt & ETHERNET_dma_mm2s_introut & ETHERNET_dma_s2mm_introut
|
||
|
END
|
||
|
|