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/*
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FreeRTOS.org V4.7.2 - Copyright (C) 2003-2008 Richard Barry.
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This file is part of the FreeRTOS.org distribution.
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FreeRTOS.org is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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FreeRTOS.org is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with FreeRTOS.org; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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A special exception to the GPL can be applied should you wish to distribute
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a combined work that includes FreeRTOS.org, without being obliged to provide
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the source code for any proprietary components. See the licensing section
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of http://www.FreeRTOS.org for full details of how and when the exception
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can be applied.
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***************************************************************************
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Please ensure to read the configuration and relevant port sections of the
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online documentation.
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+++ http://www.FreeRTOS.org +++
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Documentation, latest information, license and contact details.
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+++ http://www.SafeRTOS.com +++
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A version that is certified for use in safety critical systems.
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+++ http://www.OpenRTOS.com +++
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Commercial support, development, porting, licensing and training services.
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***************************************************************************
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*/
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#include "FreeRTOSConfig.h"
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#define portCONTEXT_SIZE 136
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#define portEXL_AND_IE_BITS 0x03
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#define portEPC_STACK_LOCATION 124
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#define portSTATUS_STACK_LOCATION 128
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#define portCAUSE_STACK_LOCATION 132
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/******************************************************************/
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.macro portSAVE_CONTEXT
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/* Make room for the context. */
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addiu sp, sp, -portCONTEXT_SIZE
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/* Get interrupts above the kernel priority enabled again ASAP. First
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save the current status so we can manipulate it, and the cause and EPC
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registers so we capture their original values in case of interrupt nesting. */
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mfc0 k0, _CP0_CAUSE
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sw k0, portCAUSE_STACK_LOCATION(sp)
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mfc0 k1, _CP0_STATUS
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sw k1, portSTATUS_STACK_LOCATION(sp)
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/* Also save s6 so we can use it during this interrupt. Any
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nesting interrupts should maintain the values of this register
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accross the ISR. */
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sw s6, 44(sp)
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/* s6 holds the EPC value, we may want this during the context switch. */
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mfc0 s6, _CP0_EPC
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/* Enable interrupts above the kernel priority. */
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addiu k0, zero, configKERNEL_INTERRUPT_PRIORITY
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ins k1, k0, 10, 6
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ins k1, zero, 1, 4
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mtc0 k1, _CP0_STATUS
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/* Save the context into the space just created. s6 is saved again
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here as it now contains the EPC value. */
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sw ra, 120(sp)
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sw s8, 116(sp)
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sw t9, 112(sp)
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sw t8, 108(sp)
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sw t7, 104(sp)
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sw t6, 100(sp)
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sw t5, 96(sp)
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sw t4, 92(sp)
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sw t3, 88(sp)
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sw t2, 84(sp)
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sw t1, 80(sp)
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sw t0, 76(sp)
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sw a3, 72(sp)
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sw a2, 68(sp)
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sw a1, 64(sp)
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sw a0, 60(sp)
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sw v1, 56(sp)
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sw v0, 52(sp)
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sw s7, 48(sp)
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sw s6, portEPC_STACK_LOCATION(sp)
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sw s5, 40(sp)
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sw s4, 36(sp)
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sw s3, 32(sp)
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sw s2, 28(sp)
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sw s1, 24(sp)
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sw s0, 20(sp)
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sw $1, 16(sp)
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/* s7 is used as a scratch register. */
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mfhi s7
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sw s7, 12(sp)
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mflo s7
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sw s7, 8(sp)
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/* Each task maintains its own nesting count. */
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la s7, uxCriticalNesting
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lw s7, (s7)
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sw s7, 4(sp)
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/* Update the TCB stack pointer value */
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la s7, pxCurrentTCB
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lw s7, (s7)
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sw sp, (s7)
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/* Switch to the ISR stack, saving the current stack in s5. This might
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be used to determine the cause of a general exception. */
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add s5, zero, sp
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la s7, xISRStackTop
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lw sp, (s7)
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.endm
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/******************************************************************/
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.macro portRESTORE_CONTEXT
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/* Restore the stack pointer from the TCB */
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la s0, pxCurrentTCB
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lw s1, (s0)
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lw sp, (s1)
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/* Restore the context, the first item of which is the critical nesting
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depth. */
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la s0, uxCriticalNesting
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lw s1, 4(sp)
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sw s1, (s0)
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/* Restore the rest of the context. */
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lw s0, 8(sp)
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mtlo s0
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lw s0, 12(sp)
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mthi s0
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lw $1, 16(sp)
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lw s0, 20(sp)
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lw s1, 24(sp)
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lw s2, 28(sp)
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lw s3, 32(sp)
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lw s4, 36(sp)
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lw s5, 40(sp)
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lw s6, 44(sp)
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lw s7, 48(sp)
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lw v0, 52(sp)
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lw v1, 56(sp)
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lw a0, 60(sp)
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lw a1, 64(sp)
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lw a2, 68(sp)
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lw a3, 72(sp)
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lw t0, 76(sp)
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lw t1, 80(sp)
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lw t2, 84(sp)
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lw t3, 88(sp)
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lw t4, 92(sp)
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lw t5, 96(sp)
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lw t6, 100(sp)
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lw t7, 104(sp)
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lw t8, 108(sp)
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lw t9, 112(sp)
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lw s8, 116(sp)
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lw ra, 120(sp)
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/* Protect access to the k registers. */
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di
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lw k1, portSTATUS_STACK_LOCATION(sp)
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lw k0, portEPC_STACK_LOCATION(sp)
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/* Leave the stack how we found it. */
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addiu sp, sp, portCONTEXT_SIZE
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mtc0 k1, _CP0_STATUS
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ehb
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mtc0 k0, _CP0_EPC
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eret
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nop
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.endm
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